DevIommuIntel.cpp@ 89578

Last change on this file since 89578 was 89578, checked in by vboxsync, 4 years ago
Intel IOMMU: bugref:9967 Implemented bulk memory access requests.
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1	/* $Id: DevIommuIntel.cpp 89578 2021-06-09 11:41:54Z vboxsync $ */
2	/** @file
3	* IOMMU - Input/Output Memory Management Unit - Intel implementation.
4	*/
5
6	/*
7	* Copyright (C) 2021 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_DEV_IOMMU
23	#include "VBoxDD.h"
24	#include "DevIommuIntel.h"
25
26	#include <iprt/mem.h>
27	#include <iprt/string.h>
28
29
30	/*********************************************************************************************************************************
31	* Defined Constants And Macros *
32	*********************************************************************************************************************************/
33	/** Gets the low uint32_t of a uint64_t or something equivalent.
34	*
35	* This is suitable for casting constants outside code (since RT_LO_U32 can't be
36	* used as it asserts for correctness when compiling on certain compilers). */
37	#define DMAR_LO_U32(a) (uint32_t)(UINT32_MAX & (a))
38
39	/** Gets the high uint32_t of a uint64_t or something equivalent.
40	*
41	* This is suitable for casting constants outside code (since RT_HI_U32 can't be
42	* used as it asserts for correctness when compiling on certain compilers). */
43	#define DMAR_HI_U32(a) (uint32_t)((a) >> 32)
44
45	/** Asserts MMIO access' offset and size are valid or returns appropriate error
46	* code suitable for returning from MMIO access handlers. */
47	#define DMAR_ASSERT_MMIO_ACCESS_RET(a_off, a_cb) \
48	do { \
49	AssertReturn((a_cb) == 4 \|\| (a_cb) == 8, VINF_IOM_MMIO_UNUSED_FF); \
50	AssertReturn(!((a_off) & ((a_cb) - 1)), VINF_IOM_MMIO_UNUSED_FF); \
51	} while (0)
52
53	/** Checks if the MMIO offset is valid. */
54	#define DMAR_IS_MMIO_OFF_VALID(a_off) ( (a_off) < DMAR_MMIO_GROUP_0_OFF_END \
55	\|\| (a_off) - DMAR_MMIO_GROUP_1_OFF_FIRST < DMAR_MMIO_GROUP_1_SIZE)
56
57	/** Acquires the DMAR lock but returns with the given busy error code on failure. */
58	#define DMAR_LOCK_RET(a_pDevIns, a_pThisCC, a_rcBusy) \
59	do { \
60	if ((a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLock((a_pDevIns), (a_rcBusy)) == VINF_SUCCESS) \
61	{ /* likely */ } \
62	else \
63	return (a_rcBusy); \
64	} while (0)
65
66	/** Acquires the DMAR lock (not expected to fail). */
67	#ifdef IN_RING3
68	# define DMAR_LOCK(a_pDevIns, a_pThisCC) (a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLock((a_pDevIns), VERR_IGNORED)
69	#else
70	# define DMAR_LOCK(a_pDevIns, a_pThisCC) \
71	do { \
72	int const rcLock = (a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLock((a_pDevIns), VINF_SUCCESS); \
73	AssertRC(rcLock); \
74	} while (0)
75	#endif
76
77	/** Release the DMAR lock. */
78	#define DMAR_UNLOCK(a_pDevIns, a_pThisCC) (a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnUnlock(a_pDevIns)
79
80	/** Asserts that the calling thread owns the DMAR lock. */
81	#define DMAR_ASSERT_LOCK_IS_OWNER(a_pDevIns, a_pThisCC) \
82	do { \
83	Assert((a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLockIsOwner(a_pDevIns)); \
84	RT_NOREF1(a_pThisCC); \
85	} while (0)
86
87	/** Asserts that the calling thread does not own the DMAR lock. */
88	#define DMAR_ASSERT_LOCK_IS_NOT_OWNER(a_pDevIns, a_pThisCC) \
89	do { \
90	Assert((a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLockIsOwner(a_pDevIns) == false); \
91	RT_NOREF1(a_pThisCC); \
92	} while (0)
93
94	/** The number of fault recording registers our implementation supports.
95	* Normal guest operation shouldn't trigger faults anyway, so we only support the
96	* minimum number of registers (which is 1).
97	*
98	* See Intel VT-d spec. 10.4.2 "Capability Register" (CAP_REG.NFR). */
99	#define DMAR_FRCD_REG_COUNT UINT32_C(1)
100
101	/** Number of register groups (used in saved states). */
102	#define DMAR_MMIO_GROUP_COUNT 2
103	/** Offset of first register in group 0. */
104	#define DMAR_MMIO_GROUP_0_OFF_FIRST VTD_MMIO_OFF_VER_REG
105	/** Offset of last register in group 0 (inclusive). */
106	#define DMAR_MMIO_GROUP_0_OFF_LAST VTD_MMIO_OFF_MTRR_PHYSMASK9_REG
107	/** Last valid offset in group 0 (exclusive). */
108	#define DMAR_MMIO_GROUP_0_OFF_END (DMAR_MMIO_GROUP_0_OFF_LAST + 8 /* sizeof MTRR_PHYSMASK9_REG */)
109	/** Size of the group 0 (in bytes). */
110	#define DMAR_MMIO_GROUP_0_SIZE (DMAR_MMIO_GROUP_0_OFF_END - DMAR_MMIO_GROUP_0_OFF_FIRST)
111	/*< Implementation-specific MMIO offset of IVA_REG. /
112	#define DMAR_MMIO_OFF_IVA_REG 0xe50
113	/*< Implementation-specific MMIO offset of IOTLB_REG. /
114	#define DMAR_MMIO_OFF_IOTLB_REG 0xe58
115	/*< Implementation-specific MMIO offset of FRCD_LO_REG. /
116	#define DMAR_MMIO_OFF_FRCD_LO_REG 0xe70
117	/*< Implementation-specific MMIO offset of FRCD_HI_REG. /
118	#define DMAR_MMIO_OFF_FRCD_HI_REG 0xe78
119	AssertCompile(!(DMAR_MMIO_OFF_FRCD_LO_REG & 0xf));
120
121	/** Offset of first register in group 1. */
122	#define DMAR_MMIO_GROUP_1_OFF_FIRST VTD_MMIO_OFF_VCCAP_REG
123	/** Offset of last register in group 1 (inclusive). */
124	#define DMAR_MMIO_GROUP_1_OFF_LAST (DMAR_MMIO_OFF_FRCD_LO_REG + 8) * DMAR_FRCD_REG_COUNT
125	/** Last valid offset in group 1 (exclusive). */
126	#define DMAR_MMIO_GROUP_1_OFF_END (DMAR_MMIO_GROUP_1_OFF_LAST + 8 /* sizeof FRCD_HI_REG */)
127	/** Size of the group 1 (in bytes). */
128	#define DMAR_MMIO_GROUP_1_SIZE (DMAR_MMIO_GROUP_1_OFF_END - DMAR_MMIO_GROUP_1_OFF_FIRST)
129
130	/** DMAR implementation's major version number (exposed to software).
131	* We report 6 as the major version since we support queued-invalidations as
132	* software may make assumptions based on that.
133	*
134	* See Intel VT-d spec. 10.4.7 "Context Command Register" (CCMD_REG.CAIG). */
135	#define DMAR_VER_MAJOR 6
136	/** DMAR implementation's minor version number (exposed to software). */
137	#define DMAR_VER_MINOR 0
138
139	/** Number of domain supported (0=16, 1=64, 2=256, 3=1K, 4=4K, 5=16K, 6=64K,
140	* 7=Reserved). */
141	#define DMAR_ND 6
142
143	/** @name DMAR_PERM_XXX: DMA request permissions.
144	* The order of R, W, X bits is important as it corresponds to those bits in
145	* page-table entries.
146	*
147	* @{ */
148	/** DMA request permission: Read. */
149	#define DMAR_PERM_READ RT_BIT(0)
150	/** DMA request permission: Write. */
151	#define DMAR_PERM_WRITE RT_BIT(1)
152	/** DMA request permission: Execute (ER). */
153	#define DMAR_PERM_EXE RT_BIT(2)
154	/** DMA request permission: Supervisor privilege (PR). */
155	#define DMAR_PERM_PRIV RT_BIT(3)
156	/** DMA request permissions: All. */
157	#define DMAR_PERM_ALL (DMAR_PERM_READ \| DMAR_PERM_WRITE \| DMAR_PERM_EXE \| DMAR_PERM_PRIV)
158	/** @} */
159
160	/** Release log prefix string. */
161	#define DMAR_LOG_PFX "Intel-IOMMU"
162	/** The current saved state version. */
163	#define DMAR_SAVED_STATE_VERSION 1
164
165
166	/*********************************************************************************************************************************
167	* Structures and Typedefs *
168	*********************************************************************************************************************************/
169	/**
170	* DMAR error diagnostics.
171	* Sorted alphabetically so it's easier to add and locate items, no other reason.
172	*
173	* @note Members of this enum are used as array indices, so no gaps in enum
174	* values are not allowed. Update g_apszDmarDiagDesc when you modify
175	* fields in this enum.
176	*/
177	typedef enum
178	{
179	/* No error, this must be zero! */
180	kDmarDiag_None = 0,
181
182	/* Address Translation Faults. */
183	kDmarDiag_At_Lm_CtxEntry_Not_Present,
184	kDmarDiag_At_Lm_CtxEntry_Read_Failed,
185	kDmarDiag_At_Lm_CtxEntry_Rsvd,
186	kDmarDiag_At_Lm_Pt_At_Block,
187	kDmarDiag_At_Lm_Pt_Aw_Invalid,
188	kDmarDiag_At_Lm_RootEntry_Not_Present,
189	kDmarDiag_At_Lm_RootEntry_Read_Failed,
190	kDmarDiag_At_Lm_RootEntry_Rsvd,
191	kDmarDiag_At_Lm_Tt_Invalid,
192	kDmarDiag_At_Lm_Ut_At_Block,
193	kDmarDiag_At_Lm_Ut_Aw_Invalid,
194	kDmarDiag_At_Rta_Adms_Not_Supported,
195	kDmarDiag_At_Rta_Rsvd,
196	kDmarDiag_At_Rta_Smts_Not_Supported,
197	kDmarDiag_At_Xm_AddrIn_Invalid,
198	kDmarDiag_At_Xm_AddrOut_Invalid,
199	kDmarDiag_At_Xm_Perm_Denied,
200	kDmarDiag_At_Xm_Pte_Rsvd,
201	kDmarDiag_At_Xm_Pte_Sllps_Invalid,
202	kDmarDiag_At_Xm_Read_Pte_Failed,
203	kDmarDiag_At_Xm_Slpptr_Read_Failed,
204
205	/* CCMD_REG faults. */
206	kDmarDiag_CcmdReg_Not_Supported,
207	kDmarDiag_CcmdReg_Qi_Enabled,
208	kDmarDiag_CcmdReg_Ttm_Invalid,
209
210	/* IQA_REG faults. */
211	kDmarDiag_IqaReg_Dsc_Fetch_Error,
212	kDmarDiag_IqaReg_Dw_128_Invalid,
213	kDmarDiag_IqaReg_Dw_256_Invalid,
214
215	/* Invalidation Queue Error Info. */
216	kDmarDiag_Iqei_Dsc_Type_Invalid,
217	kDmarDiag_Iqei_Inv_Wait_Dsc_0_1_Rsvd,
218	kDmarDiag_Iqei_Inv_Wait_Dsc_2_3_Rsvd,
219	kDmarDiag_Iqei_Inv_Wait_Dsc_Invalid,
220	kDmarDiag_Iqei_Ttm_Rsvd,
221
222	/* IQT_REG faults. */
223	kDmarDiag_IqtReg_Qt_Invalid,
224	kDmarDiag_IqtReg_Qt_Not_Aligned,
225
226	/* Interrupt Remapping Faults. */
227	kDmarDiag_Ir_Cfi_Blocked,
228	kDmarDiag_Ir_Rfi_Intr_Index_Invalid,
229	kDmarDiag_Ir_Rfi_Irte_Mode_Invalid,
230	kDmarDiag_Ir_Rfi_Irte_Not_Present,
231	kDmarDiag_Ir_Rfi_Irte_Read_Failed,
232	kDmarDiag_Ir_Rfi_Irte_Rsvd,
233	kDmarDiag_Ir_Rfi_Irte_Svt_Bus,
234	kDmarDiag_Ir_Rfi_Irte_Svt_Masked,
235	kDmarDiag_Ir_Rfi_Irte_Svt_Rsvd,
236	kDmarDiag_Ir_Rfi_Rsvd,
237
238	/* Member for determining array index limit. */
239	kDmarDiag_End,
240
241	/* Usual 32-bit type size hack. */
242	kDmarDiag_32Bit_Hack = 0x7fffffff
243	} DMARDIAG;
244	AssertCompileSize(DMARDIAG, 4);
245
246	/** DMAR diagnostic enum description expansion.
247	* The below construct ensures typos in the input to this macro are caught
248	* during compile time. */
249	#define DMARDIAG_DESC(a_Name) RT_CONCAT(kDmarDiag_, a_Name) < kDmarDiag_End ? RT_STR(a_Name) : "Ignored"
250
251	/** DMAR diagnostics description for members in DMARDIAG. */
252	static const char *const g_apszDmarDiagDesc[] =
253	{
254	DMARDIAG_DESC(None ),
255
256	/* Address Translation Faults. */
257	DMARDIAG_DESC(At_Lm_CtxEntry_Not_Present ),
258	DMARDIAG_DESC(At_Lm_CtxEntry_Read_Failed ),
259	DMARDIAG_DESC(At_Lm_CtxEntry_Rsvd ),
260	DMARDIAG_DESC(At_Lm_Pt_At_Block ),
261	DMARDIAG_DESC(At_Lm_Pt_Aw_Invalid ),
262	DMARDIAG_DESC(At_Lm_RootEntry_Not_Present),
263	DMARDIAG_DESC(At_Lm_RootEntry_Read_Failed),
264	DMARDIAG_DESC(At_Lm_RootEntry_Rsvd ),
265	DMARDIAG_DESC(At_Lm_Tt_Invalid ),
266	DMARDIAG_DESC(At_Lm_Ut_At_Block ),
267	DMARDIAG_DESC(At_Lm_Ut_Aw_Invalid ),
268	DMARDIAG_DESC(At_Rta_Adms_Not_Supported ),
269	DMARDIAG_DESC(At_Rta_Rsvd ),
270	DMARDIAG_DESC(At_Rta_Smts_Not_Supported ),
271	DMARDIAG_DESC(At_Xm_AddrIn_Invalid ),
272	DMARDIAG_DESC(At_Xm_AddrOut_Invalid ),
273	DMARDIAG_DESC(At_Xm_Perm_Denied ),
274	DMARDIAG_DESC(At_Xm_Pte_Rsvd ),
275	DMARDIAG_DESC(At_Xm_Pte_Sllps_Invalid ),
276	DMARDIAG_DESC(At_Xm_Read_Pte_Failed ),
277	DMARDIAG_DESC(At_Xm_Slpptr_Read_Failed ),
278
279	/* CCMD_REG faults. */
280	DMARDIAG_DESC(CcmdReg_Not_Supported ),
281	DMARDIAG_DESC(CcmdReg_Qi_Enabled ),
282	DMARDIAG_DESC(CcmdReg_Ttm_Invalid ),
283
284	/* IQA_REG faults. */
285	DMARDIAG_DESC(IqaReg_Dsc_Fetch_Error ),
286	DMARDIAG_DESC(IqaReg_Dw_128_Invalid ),
287	DMARDIAG_DESC(IqaReg_Dw_256_Invalid ),
288
289	/* Invalidation Queue Error Info. */
290	DMARDIAG_DESC(Iqei_Dsc_Type_Invalid ),
291	DMARDIAG_DESC(Iqei_Inv_Wait_Dsc_0_1_Rsvd ),
292	DMARDIAG_DESC(Iqei_Inv_Wait_Dsc_2_3_Rsvd ),
293	DMARDIAG_DESC(Iqei_Inv_Wait_Dsc_Invalid ),
294	DMARDIAG_DESC(Iqei_Ttm_Rsvd ),
295
296	/* IQT_REG faults. */
297	DMARDIAG_DESC(IqtReg_Qt_Invalid ),
298	DMARDIAG_DESC(IqtReg_Qt_Not_Aligned ),
299
300	/* Interrupt remapping faults. */
301	DMARDIAG_DESC(Ir_Cfi_Blocked ),
302	DMARDIAG_DESC(Ir_Rfi_Intr_Index_Invalid ),
303	DMARDIAG_DESC(Ir_Rfi_Irte_Mode_Invalid ),
304	DMARDIAG_DESC(Ir_Rfi_Irte_Not_Present ),
305	DMARDIAG_DESC(Ir_Rfi_Irte_Read_Failed ),
306	DMARDIAG_DESC(Ir_Rfi_Irte_Rsvd ),
307	DMARDIAG_DESC(Ir_Rfi_Irte_Svt_Bus ),
308	DMARDIAG_DESC(Ir_Rfi_Irte_Svt_Masked ),
309	DMARDIAG_DESC(Ir_Rfi_Irte_Svt_Rsvd ),
310	DMARDIAG_DESC(Ir_Rfi_Rsvd ),
311	/* kDmarDiag_End */
312	};
313	AssertCompile(RT_ELEMENTS(g_apszDmarDiagDesc) == kDmarDiag_End);
314	#undef DMARDIAG_DESC
315
316	/**
317	* The shared DMAR device state.
318	*/
319	typedef struct DMAR
320	{
321	/** IOMMU device index. */
322	uint32_t idxIommu;
323	/** Padding. */
324	uint32_t u32Padding0;
325
326	/** Registers (group 0). */
327	uint8_t abRegs0[DMAR_MMIO_GROUP_0_SIZE];
328	/** Registers (group 1). */
329	uint8_t abRegs1[DMAR_MMIO_GROUP_1_SIZE];
330
331	/** @name Lazily activated registers.
332	* These are the active values for lazily activated registers. Software is free to
333	* modify the actual register values while remapping/translation is enabled but they
334	* take effect only when explicitly signaled by software, hence we need to hold the
335	* active values separately.
336	* @{ */
337	/** Currently active IRTA_REG. */
338	uint64_t uIrtaReg;
339	/** Currently active RTADDR_REG. */
340	uint64_t uRtaddrReg;
341	/** @} */
342
343	/** @name Register copies for a tiny bit faster and more convenient access.
344	* @{ */
345	/** Copy of VER_REG. */
346	uint8_t uVerReg;
347	/** Alignment. */
348	uint8_t abPadding[7];
349	/** Copy of CAP_REG. */
350	uint64_t fCapReg;
351	/** Copy of ECAP_REG. */
352	uint64_t fExtCapReg;
353	/** @} */
354
355	/** Host-address width (HAW) base address mask. */
356	uint64_t fHawBaseMask;
357	/** Maximum guest-address width (MGAW) invalid address mask. */
358	uint64_t fMgawInvMask;
359	/** Maximum supported paging level (3, 4 or 5). */
360	uint8_t cMaxPagingLevel;
361	/** DMA request valid permissions mask. */
362	uint8_t fPermValidMask;
363
364	/** The event semaphore the invalidation-queue thread waits on. */
365	SUPSEMEVENT hEvtInvQueue;
366	/** Padding. */
367	uint32_t uPadding0;
368	/** Error diagnostic. */
369	DMARDIAG enmDiag;
370	/** The MMIO handle. */
371	IOMMMIOHANDLE hMmio;
372
373	#ifdef VBOX_WITH_STATISTICS
374	STAMCOUNTER StatMmioReadR3; /*< Number of MMIO reads in R3. /
375	STAMCOUNTER StatMmioReadRZ; /*< Number of MMIO reads in RZ. /
376	STAMCOUNTER StatMmioWriteR3; /*< Number of MMIO writes in R3. /
377	STAMCOUNTER StatMmioWriteRZ; /*< Number of MMIO writes in RZ. /
378
379	STAMCOUNTER StatMsiRemapCfiR3; /*< Number of compatibility-format interrupts remap requests in R3. /
380	STAMCOUNTER StatMsiRemapCfiRZ; /*< Number of compatibility-format interrupts remap requests in RZ. /
381	STAMCOUNTER StatMsiRemapRfiR3; /*< Number of remappable-format interrupts remap requests in R3. /
382	STAMCOUNTER StatMsiRemapRfiRZ; /*< Number of remappable-format interrupts remap requests in RZ. /
383
384	STAMCOUNTER StatMemReadR3; /*< Number of memory read translation requests in R3. /
385	STAMCOUNTER StatMemReadRZ; /*< Number of memory read translation requests in RZ. /
386	STAMCOUNTER StatMemWriteR3; /*< Number of memory write translation requests in R3. /
387	STAMCOUNTER StatMemWriteRZ; /*< Number of memory write translation requests in RZ. /
388
389	STAMCOUNTER StatMemBulkReadR3; /*< Number of memory read bulk translation requests in R3. /
390	STAMCOUNTER StatMemBulkReadRZ; /*< Number of memory read bulk translation requests in RZ. /
391	STAMCOUNTER StatMemBulkWriteR3; /*< Number of memory write bulk translation requests in R3. /
392	STAMCOUNTER StatMemBulkWriteRZ; /*< Number of memory write bulk translation requests in RZ. /
393
394	STAMCOUNTER StatCcInvDsc; /*< Number of Context-cache descriptors processed. /
395	STAMCOUNTER StatIotlbInvDsc; /*< Number of IOTLB descriptors processed. /
396	STAMCOUNTER StatDevtlbInvDsc; /*< Number of Device-TLB descriptors processed. /
397	STAMCOUNTER StatIecInvDsc; /*< Number of Interrupt-Entry cache descriptors processed. /
398	STAMCOUNTER StatInvWaitDsc; /*< Number of Invalidation wait descriptors processed. /
399	STAMCOUNTER StatPasidIotlbInvDsc; /*< Number of PASID-based IOTLB descriptors processed. /
400	STAMCOUNTER StatPasidCacheInvDsc; /*< Number of PASID-cache descriptors processed. /
401	STAMCOUNTER StatPasidDevtlbInvDsc; /*< Number of PASID-based device-TLB descriptors processed. /
402	#endif
403	} DMAR;
404	/** Pointer to the DMAR device state. */
405	typedef DMAR *PDMAR;
406	/** Pointer to the const DMAR device state. */
407	typedef DMAR const *PCDMAR;
408	AssertCompileMemberAlignment(DMAR, abRegs0, 8);
409	AssertCompileMemberAlignment(DMAR, abRegs1, 8);
410
411	/**
412	* The ring-3 DMAR device state.
413	*/
414	typedef struct DMARR3
415	{
416	/** Device instance. */
417	PPDMDEVINSR3 pDevInsR3;
418	/** The IOMMU helper. */
419	R3PTRTYPE(PCPDMIOMMUHLPR3) pIommuHlpR3;
420	/** The invalidation-queue thread. */
421	R3PTRTYPE(PPDMTHREAD) pInvQueueThread;
422	} DMARR3;
423	/** Pointer to the ring-3 DMAR device state. */
424	typedef DMARR3 *PDMARR3;
425	/** Pointer to the const ring-3 DMAR device state. */
426	typedef DMARR3 const *PCDMARR3;
427
428	/**
429	* The ring-0 DMAR device state.
430	*/
431	typedef struct DMARR0
432	{
433	/** Device instance. */
434	PPDMDEVINSR0 pDevInsR0;
435	/** The IOMMU helper. */
436	R0PTRTYPE(PCPDMIOMMUHLPR0) pIommuHlpR0;
437	} DMARR0;
438	/** Pointer to the ring-0 IOMMU device state. */
439	typedef DMARR0 *PDMARR0;
440	/** Pointer to the const ring-0 IOMMU device state. */
441	typedef DMARR0 const *PCDMARR0;
442
443	/**
444	* The raw-mode DMAR device state.
445	*/
446	typedef struct DMARRC
447	{
448	/** Device instance. */
449	PPDMDEVINSRC pDevInsRC;
450	/** The IOMMU helper. */
451	RCPTRTYPE(PCPDMIOMMUHLPRC) pIommuHlpRC;
452	} DMARRC;
453	/** Pointer to the raw-mode DMAR device state. */
454	typedef DMARRC *PDMARRC;
455	/** Pointer to the const raw-mode DMAR device state. */
456	typedef DMARRC const *PCIDMARRC;
457
458	/** The DMAR device state for the current context. */
459	typedef CTX_SUFF(DMAR) DMARCC;
460	/** Pointer to the DMAR device state for the current context. */
461	typedef CTX_SUFF(PDMAR) PDMARCC;
462	/** Pointer to the const DMAR device state for the current context. */
463	typedef CTX_SUFF(PDMAR) const PCDMARCC;
464
465	/**
466	* DMAR originated events that generate interrupts.
467	*/
468	typedef enum DMAREVENTTYPE
469	{
470	/** Invalidation completion event. */
471	DMAREVENTTYPE_INV_COMPLETE = 0,
472	/** Fault event. */
473	DMAREVENTTYPE_FAULT
474	} DMAREVENTTYPE;
475
476	/**
477	* I/O Page.
478	*/
479	typedef struct DMARIOPAGE
480	{
481	/** The base DMA address of a page. */
482	RTGCPHYS GCPhysBase;
483	/** The page shift. */
484	uint8_t cShift;
485	/** The permissions of this page (DMAR_PERM_XXX). */
486	uint8_t fPerm;
487	} DMARIOPAGE;
488	/** Pointer to an I/O page. */
489	typedef DMARIOPAGE *PDMARIOPAGE;
490	/** Pointer to a const I/O address range. */
491	typedef DMARIOPAGE const *PCDMARIOPAGE;
492
493	/**
494	* I/O Address Range.
495	*/
496	typedef struct DMARIOADDRRANGE
497	{
498	/** The starting DMA address of this range. */
499	uint64_t uAddr;
500	/** The size of the range (in bytes). */
501	size_t cb;
502	/** The permissions of this range (DMAR_PERM_XXX). */
503	uint8_t fPerm;
504	} DMARIOADDRRANGE;
505	/** Pointer to an I/O address range. */
506	typedef DMARIOADDRRANGE *PDMARIOADDRRANGE;
507	/** Pointer to a const I/O address range. */
508	typedef DMARIOADDRRANGE const *PCDMARIOADDRRANGE;
509
510	/**
511	* DMA Memory Request (Input).
512	*/
513	typedef struct DMARMEMREQIN
514	{
515	/** The address range being accessed. */
516	DMARIOADDRRANGE AddrRange;
517	/** The source device ID (bus, device, function). */
518	uint16_t idDevice;
519	/** The PASID if present (can be NIL_PCIPASID). */
520	PCIPASID Pasid;
521	/* The address translation type. */
522	PCIADDRTYPE enmAddrType;
523	/** The request type. */
524	VTDREQTYPE enmReqType;
525	} DMARMEMREQIN;
526	/** Pointer to a DMA memory request input. */
527	typedef DMARMEMREQIN *PDMARMEMREQIN;
528	/** Pointer to a const DMA memory input. */
529	typedef DMARMEMREQIN const *PCDMARMEMREQIN;
530
531	/**
532	* DMA Memory Request (Output).
533	*/
534	typedef struct DMARMEMREQOUT
535	{
536	/** The address range of the translated region. */
537	DMARIOADDRRANGE AddrRange;
538	/** The domain ID of the translated region. */
539	uint16_t idDomain;
540	} DMARMEMREQOUT;
541	/** Pointer to a DMA memory request output. */
542	typedef DMARMEMREQOUT *PDMARMEMREQOUT;
543	/** Pointer to a const DMA memory request output. */
544	typedef DMARMEMREQOUT const *PCDMARMEMREQOUT;
545
546	/**
547	* DMA Memory Request (Auxiliary Info).
548	* These get updated and used as part of the translation process.
549	*/
550	typedef struct DMARMEMREQAUX
551	{
552	/** The table translation mode (VTD_TTM_XXX). */
553	uint8_t fTtm;
554	/** The fault processing disabled (FPD) bit. */
555	uint8_t fFpd;
556	/** The paging level of the translation. */
557	uint8_t cPagingLevel;
558	uint8_t afPadding[5];
559	/** The address of the first-level page-table. */
560	uint64_t GCPhysFlPt;
561	/** The address of second-level page-table. */
562	uint64_t GCPhysSlPt;
563	} DMARMEMREQAUX;
564	/** Pointer to a DMA memory request output. */
565	typedef DMARMEMREQAUX *PDMARMEMREQAUX;
566	/** Pointer to a const DMA memory request output. */
567	typedef DMARMEMREQAUX const *PCDMARMEMREQAUX;
568
569	/**
570	* DMA Memory Request Remapping Information.
571	*/
572	typedef struct DMARMEMREQREMAP
573	{
574	/** The DMA memory request input. */
575	DMARMEMREQIN In;
576	/** DMA memory request auxiliary information. */
577	DMARMEMREQAUX Aux;
578	/** The DMA memory request output. */
579	DMARMEMREQOUT Out;
580	} DMARMEMREQREMAP;
581	/** Pointer to a DMA remap info. */
582	typedef DMARMEMREQREMAP *PDMARMEMREQREMAP;
583	/** Pointer to a const DMA remap info. */
584	typedef DMARMEMREQREMAP const *PCDMARMEMREQREMAP;
585
586	/**
587	* Callback function to lookup a DMA address.
588	*
589	* @returns VBox status code.
590	* @param pDevIns The IOMMU device instance.
591	* @param pMemReqIn The DMA memory request input.
592	* @param pMemReqAux The DMA memory request auxiliary info.
593	* @param pIoPageOut Where to store the output of the lookup.
594	*/
595	typedef DECLCALLBACKTYPE(int, FNDMADDRLOOKUP,(PPDMDEVINS pDevIns, PCDMARMEMREQIN pMemReqIn, PCDMARMEMREQAUX pMemReqAux,
596	PDMARIOPAGE pIoPageOut));
597	/** Pointer to a DMA address-lookup function. */
598	typedef FNDMADDRLOOKUP *PFNDMADDRLOOKUP;
599
600
601	/*********************************************************************************************************************************
602	* Global Variables *
603	*********************************************************************************************************************************/
604	/**
605	* Read-write masks for DMAR registers (group 0).
606	*/
607	static uint32_t const g_au32RwMasks0[] =
608	{
609	/* Offset Register Low High */
610	/* 0x000 VER_REG */ VTD_VER_REG_RW_MASK,
611	/* 0x004 Reserved */ 0,
612	/* 0x008 CAP_REG */ DMAR_LO_U32(VTD_CAP_REG_RW_MASK), DMAR_HI_U32(VTD_CAP_REG_RW_MASK),
613	/* 0x010 ECAP_REG */ DMAR_LO_U32(VTD_ECAP_REG_RW_MASK), DMAR_HI_U32(VTD_ECAP_REG_RW_MASK),
614	/* 0x018 GCMD_REG */ VTD_GCMD_REG_RW_MASK,
615	/* 0x01c GSTS_REG */ VTD_GSTS_REG_RW_MASK,
616	/* 0x020 RTADDR_REG */ DMAR_LO_U32(VTD_RTADDR_REG_RW_MASK), DMAR_HI_U32(VTD_RTADDR_REG_RW_MASK),
617	/* 0x028 CCMD_REG */ DMAR_LO_U32(VTD_CCMD_REG_RW_MASK), DMAR_HI_U32(VTD_CCMD_REG_RW_MASK),
618	/* 0x030 Reserved */ 0,
619	/* 0x034 FSTS_REG */ VTD_FSTS_REG_RW_MASK,
620	/* 0x038 FECTL_REG */ VTD_FECTL_REG_RW_MASK,
621	/* 0x03c FEDATA_REG */ VTD_FEDATA_REG_RW_MASK,
622	/* 0x040 FEADDR_REG */ VTD_FEADDR_REG_RW_MASK,
623	/* 0x044 FEUADDR_REG */ VTD_FEUADDR_REG_RW_MASK,
624	/* 0x048 Reserved */ 0, 0,
625	/* 0x050 Reserved */ 0, 0,
626	/* 0x058 AFLOG_REG */ DMAR_LO_U32(VTD_AFLOG_REG_RW_MASK), DMAR_HI_U32(VTD_AFLOG_REG_RW_MASK),
627	/* 0x060 Reserved */ 0,
628	/* 0x064 PMEN_REG / 0, / RO as we don't support PLMR and PHMR. */
629	/* 0x068 PLMBASE_REG / 0, / RO as we don't support PLMR. */
630	/* 0x06c PLMLIMIT_REG / 0, / RO as we don't support PLMR. */
631	/* 0x070 PHMBASE_REG / 0, 0, / RO as we don't support PHMR. */
632	/* 0x078 PHMLIMIT_REG / 0, 0, / RO as we don't support PHMR. */
633	/* 0x080 IQH_REG */ DMAR_LO_U32(VTD_IQH_REG_RW_MASK), DMAR_HI_U32(VTD_IQH_REG_RW_MASK),
634	/* 0x088 IQT_REG */ DMAR_LO_U32(VTD_IQT_REG_RW_MASK), DMAR_HI_U32(VTD_IQT_REG_RW_MASK),
635	/* 0x090 IQA_REG */ DMAR_LO_U32(VTD_IQA_REG_RW_MASK), DMAR_HI_U32(VTD_IQA_REG_RW_MASK),
636	/* 0x098 Reserved */ 0,
637	/* 0x09c ICS_REG */ VTD_ICS_REG_RW_MASK,
638	/* 0x0a0 IECTL_REG */ VTD_IECTL_REG_RW_MASK,
639	/* 0x0a4 IEDATA_REG */ VTD_IEDATA_REG_RW_MASK,
640	/* 0x0a8 IEADDR_REG */ VTD_IEADDR_REG_RW_MASK,
641	/* 0x0ac IEUADDR_REG */ VTD_IEUADDR_REG_RW_MASK,
642	/* 0x0b0 IQERCD_REG */ DMAR_LO_U32(VTD_IQERCD_REG_RW_MASK), DMAR_HI_U32(VTD_IQERCD_REG_RW_MASK),
643	/* 0x0b8 IRTA_REG */ DMAR_LO_U32(VTD_IRTA_REG_RW_MASK), DMAR_HI_U32(VTD_IRTA_REG_RW_MASK),
644	/* 0x0c0 PQH_REG */ DMAR_LO_U32(VTD_PQH_REG_RW_MASK), DMAR_HI_U32(VTD_PQH_REG_RW_MASK),
645	/* 0x0c8 PQT_REG */ DMAR_LO_U32(VTD_PQT_REG_RW_MASK), DMAR_HI_U32(VTD_PQT_REG_RW_MASK),
646	/* 0x0d0 PQA_REG */ DMAR_LO_U32(VTD_PQA_REG_RW_MASK), DMAR_HI_U32(VTD_PQA_REG_RW_MASK),
647	/* 0x0d8 Reserved */ 0,
648	/* 0x0dc PRS_REG */ VTD_PRS_REG_RW_MASK,
649	/* 0x0e0 PECTL_REG */ VTD_PECTL_REG_RW_MASK,
650	/* 0x0e4 PEDATA_REG */ VTD_PEDATA_REG_RW_MASK,
651	/* 0x0e8 PEADDR_REG */ VTD_PEADDR_REG_RW_MASK,
652	/* 0x0ec PEUADDR_REG */ VTD_PEUADDR_REG_RW_MASK,
653	/* 0x0f0 Reserved */ 0, 0,
654	/* 0x0f8 Reserved */ 0, 0,
655	/* 0x100 MTRRCAP_REG */ DMAR_LO_U32(VTD_MTRRCAP_REG_RW_MASK), DMAR_HI_U32(VTD_MTRRCAP_REG_RW_MASK),
656	/* 0x108 MTRRDEF_REG / 0, 0, / RO as we don't support MTS. */
657	/* 0x110 Reserved */ 0, 0,
658	/* 0x118 Reserved */ 0, 0,
659	/* 0x120 MTRR_FIX64_00000_REG / 0, 0, / RO as we don't support MTS. */
660	/* 0x128 MTRR_FIX16K_80000_REG */ 0, 0,
661	/* 0x130 MTRR_FIX16K_A0000_REG */ 0, 0,
662	/* 0x138 MTRR_FIX4K_C0000_REG */ 0, 0,
663	/* 0x140 MTRR_FIX4K_C8000_REG */ 0, 0,
664	/* 0x148 MTRR_FIX4K_D0000_REG */ 0, 0,
665	/* 0x150 MTRR_FIX4K_D8000_REG */ 0, 0,
666	/* 0x158 MTRR_FIX4K_E0000_REG */ 0, 0,
667	/* 0x160 MTRR_FIX4K_E8000_REG */ 0, 0,
668	/* 0x168 MTRR_FIX4K_F0000_REG */ 0, 0,
669	/* 0x170 MTRR_FIX4K_F8000_REG */ 0, 0,
670	/* 0x178 Reserved */ 0, 0,
671	/* 0x180 MTRR_PHYSBASE0_REG / 0, 0, / RO as we don't support MTS. */
672	/* 0x188 MTRR_PHYSMASK0_REG */ 0, 0,
673	/* 0x190 MTRR_PHYSBASE1_REG */ 0, 0,
674	/* 0x198 MTRR_PHYSMASK1_REG */ 0, 0,
675	/* 0x1a0 MTRR_PHYSBASE2_REG */ 0, 0,
676	/* 0x1a8 MTRR_PHYSMASK2_REG */ 0, 0,
677	/* 0x1b0 MTRR_PHYSBASE3_REG */ 0, 0,
678	/* 0x1b8 MTRR_PHYSMASK3_REG */ 0, 0,
679	/* 0x1c0 MTRR_PHYSBASE4_REG */ 0, 0,
680	/* 0x1c8 MTRR_PHYSMASK4_REG */ 0, 0,
681	/* 0x1d0 MTRR_PHYSBASE5_REG */ 0, 0,
682	/* 0x1d8 MTRR_PHYSMASK5_REG */ 0, 0,
683	/* 0x1e0 MTRR_PHYSBASE6_REG */ 0, 0,
684	/* 0x1e8 MTRR_PHYSMASK6_REG */ 0, 0,
685	/* 0x1f0 MTRR_PHYSBASE7_REG */ 0, 0,
686	/* 0x1f8 MTRR_PHYSMASK7_REG */ 0, 0,
687	/* 0x200 MTRR_PHYSBASE8_REG */ 0, 0,
688	/* 0x208 MTRR_PHYSMASK8_REG */ 0, 0,
689	/* 0x210 MTRR_PHYSBASE9_REG */ 0, 0,
690	/* 0x218 MTRR_PHYSMASK9_REG */ 0, 0,
691	};
692	AssertCompile(sizeof(g_au32RwMasks0) == DMAR_MMIO_GROUP_0_SIZE);
693
694	/**
695	* Read-only Status, Write-1-to-clear masks for DMAR registers (group 0).
696	*/
697	static uint32_t const g_au32Rw1cMasks0[] =
698	{
699	/* Offset Register Low High */
700	/* 0x000 VER_REG */ 0,
701	/* 0x004 Reserved */ 0,
702	/* 0x008 CAP_REG */ 0, 0,
703	/* 0x010 ECAP_REG */ 0, 0,
704	/* 0x018 GCMD_REG */ 0,
705	/* 0x01c GSTS_REG */ 0,
706	/* 0x020 RTADDR_REG */ 0, 0,
707	/* 0x028 CCMD_REG */ 0, 0,
708	/* 0x030 Reserved */ 0,
709	/* 0x034 FSTS_REG */ VTD_FSTS_REG_RW1C_MASK,
710	/* 0x038 FECTL_REG */ 0,
711	/* 0x03c FEDATA_REG */ 0,
712	/* 0x040 FEADDR_REG */ 0,
713	/* 0x044 FEUADDR_REG */ 0,
714	/* 0x048 Reserved */ 0, 0,
715	/* 0x050 Reserved */ 0, 0,
716	/* 0x058 AFLOG_REG */ 0, 0,
717	/* 0x060 Reserved */ 0,
718	/* 0x064 PMEN_REG */ 0,
719	/* 0x068 PLMBASE_REG */ 0,
720	/* 0x06c PLMLIMIT_REG */ 0,
721	/* 0x070 PHMBASE_REG */ 0, 0,
722	/* 0x078 PHMLIMIT_REG */ 0, 0,
723	/* 0x080 IQH_REG */ 0, 0,
724	/* 0x088 IQT_REG */ 0, 0,
725	/* 0x090 IQA_REG */ 0, 0,
726	/* 0x098 Reserved */ 0,
727	/* 0x09c ICS_REG */ VTD_ICS_REG_RW1C_MASK,
728	/* 0x0a0 IECTL_REG */ 0,
729	/* 0x0a4 IEDATA_REG */ 0,
730	/* 0x0a8 IEADDR_REG */ 0,
731	/* 0x0ac IEUADDR_REG */ 0,
732	/* 0x0b0 IQERCD_REG */ 0, 0,
733	/* 0x0b8 IRTA_REG */ 0, 0,
734	/* 0x0c0 PQH_REG */ 0, 0,
735	/* 0x0c8 PQT_REG */ 0, 0,
736	/* 0x0d0 PQA_REG */ 0, 0,
737	/* 0x0d8 Reserved */ 0,
738	/* 0x0dc PRS_REG */ 0,
739	/* 0x0e0 PECTL_REG */ 0,
740	/* 0x0e4 PEDATA_REG */ 0,
741	/* 0x0e8 PEADDR_REG */ 0,
742	/* 0x0ec PEUADDR_REG */ 0,
743	/* 0x0f0 Reserved */ 0, 0,
744	/* 0x0f8 Reserved */ 0, 0,
745	/* 0x100 MTRRCAP_REG */ 0, 0,
746	/* 0x108 MTRRDEF_REG */ 0, 0,
747	/* 0x110 Reserved */ 0, 0,
748	/* 0x118 Reserved */ 0, 0,
749	/* 0x120 MTRR_FIX64_00000_REG */ 0, 0,
750	/* 0x128 MTRR_FIX16K_80000_REG */ 0, 0,
751	/* 0x130 MTRR_FIX16K_A0000_REG */ 0, 0,
752	/* 0x138 MTRR_FIX4K_C0000_REG */ 0, 0,
753	/* 0x140 MTRR_FIX4K_C8000_REG */ 0, 0,
754	/* 0x148 MTRR_FIX4K_D0000_REG */ 0, 0,
755	/* 0x150 MTRR_FIX4K_D8000_REG */ 0, 0,
756	/* 0x158 MTRR_FIX4K_E0000_REG */ 0, 0,
757	/* 0x160 MTRR_FIX4K_E8000_REG */ 0, 0,
758	/* 0x168 MTRR_FIX4K_F0000_REG */ 0, 0,
759	/* 0x170 MTRR_FIX4K_F8000_REG */ 0, 0,
760	/* 0x178 Reserved */ 0, 0,
761	/* 0x180 MTRR_PHYSBASE0_REG */ 0, 0,
762	/* 0x188 MTRR_PHYSMASK0_REG */ 0, 0,
763	/* 0x190 MTRR_PHYSBASE1_REG */ 0, 0,
764	/* 0x198 MTRR_PHYSMASK1_REG */ 0, 0,
765	/* 0x1a0 MTRR_PHYSBASE2_REG */ 0, 0,
766	/* 0x1a8 MTRR_PHYSMASK2_REG */ 0, 0,
767	/* 0x1b0 MTRR_PHYSBASE3_REG */ 0, 0,
768	/* 0x1b8 MTRR_PHYSMASK3_REG */ 0, 0,
769	/* 0x1c0 MTRR_PHYSBASE4_REG */ 0, 0,
770	/* 0x1c8 MTRR_PHYSMASK4_REG */ 0, 0,
771	/* 0x1d0 MTRR_PHYSBASE5_REG */ 0, 0,
772	/* 0x1d8 MTRR_PHYSMASK5_REG */ 0, 0,
773	/* 0x1e0 MTRR_PHYSBASE6_REG */ 0, 0,
774	/* 0x1e8 MTRR_PHYSMASK6_REG */ 0, 0,
775	/* 0x1f0 MTRR_PHYSBASE7_REG */ 0, 0,
776	/* 0x1f8 MTRR_PHYSMASK7_REG */ 0, 0,
777	/* 0x200 MTRR_PHYSBASE8_REG */ 0, 0,
778	/* 0x208 MTRR_PHYSMASK8_REG */ 0, 0,
779	/* 0x210 MTRR_PHYSBASE9_REG */ 0, 0,
780	/* 0x218 MTRR_PHYSMASK9_REG */ 0, 0,
781	};
782	AssertCompile(sizeof(g_au32Rw1cMasks0) == DMAR_MMIO_GROUP_0_SIZE);
783
784	/**
785	* Read-write masks for DMAR registers (group 1).
786	*/
787	static uint32_t const g_au32RwMasks1[] =
788	{
789	/* Offset Register Low High */
790	/* 0xe00 VCCAP_REG */ DMAR_LO_U32(VTD_VCCAP_REG_RW_MASK), DMAR_HI_U32(VTD_VCCAP_REG_RW_MASK),
791	/* 0xe08 VCMD_EO_REG */ DMAR_LO_U32(VTD_VCMD_EO_REG_RW_MASK), DMAR_HI_U32(VTD_VCMD_EO_REG_RW_MASK),
792	/* 0xe10 VCMD_REG / 0, 0, / RO: VCS not supported. */
793	/* 0xe18 VCMDRSVD_REG */ 0, 0,
794	/* 0xe20 VCRSP_REG / 0, 0, / RO: VCS not supported. */
795	/* 0xe28 VCRSPRSVD_REG */ 0, 0,
796	/* 0xe30 Reserved */ 0, 0,
797	/* 0xe38 Reserved */ 0, 0,
798	/* 0xe40 Reserved */ 0, 0,
799	/* 0xe48 Reserved */ 0, 0,
800	/* 0xe50 IVA_REG */ DMAR_LO_U32(VTD_IVA_REG_RW_MASK), DMAR_HI_U32(VTD_IVA_REG_RW_MASK),
801	/* 0xe58 IOTLB_REG */ DMAR_LO_U32(VTD_IOTLB_REG_RW_MASK), DMAR_HI_U32(VTD_IOTLB_REG_RW_MASK),
802	/* 0xe60 Reserved */ 0, 0,
803	/* 0xe68 Reserved */ 0, 0,
804	/* 0xe70 FRCD_REG_LO */ DMAR_LO_U32(VTD_FRCD_REG_LO_RW_MASK), DMAR_HI_U32(VTD_FRCD_REG_LO_RW_MASK),
805	/* 0xe78 FRCD_REG_HI */ DMAR_LO_U32(VTD_FRCD_REG_HI_RW_MASK), DMAR_HI_U32(VTD_FRCD_REG_HI_RW_MASK),
806	};
807	AssertCompile(sizeof(g_au32RwMasks1) == DMAR_MMIO_GROUP_1_SIZE);
808	AssertCompile((DMAR_MMIO_OFF_FRCD_LO_REG - DMAR_MMIO_GROUP_1_OFF_FIRST) + DMAR_FRCD_REG_COUNT * 2 * sizeof(uint64_t) );
809
810	/**
811	* Read-only Status, Write-1-to-clear masks for DMAR registers (group 1).
812	*/
813	static uint32_t const g_au32Rw1cMasks1[] =
814	{
815	/* Offset Register Low High */
816	/* 0xe00 VCCAP_REG */ 0, 0,
817	/* 0xe08 VCMD_EO_REG */ 0, 0,
818	/* 0xe10 VCMD_REG */ 0, 0,
819	/* 0xe18 VCMDRSVD_REG */ 0, 0,
820	/* 0xe20 VCRSP_REG */ 0, 0,
821	/* 0xe28 VCRSPRSVD_REG */ 0, 0,
822	/* 0xe30 Reserved */ 0, 0,
823	/* 0xe38 Reserved */ 0, 0,
824	/* 0xe40 Reserved */ 0, 0,
825	/* 0xe48 Reserved */ 0, 0,
826	/* 0xe50 IVA_REG */ 0, 0,
827	/* 0xe58 IOTLB_REG */ 0, 0,
828	/* 0xe60 Reserved */ 0, 0,
829	/* 0xe68 Reserved */ 0, 0,
830	/* 0xe70 FRCD_REG_LO */ DMAR_LO_U32(VTD_FRCD_REG_LO_RW1C_MASK), DMAR_HI_U32(VTD_FRCD_REG_LO_RW1C_MASK),
831	/* 0xe78 FRCD_REG_HI */ DMAR_LO_U32(VTD_FRCD_REG_HI_RW1C_MASK), DMAR_HI_U32(VTD_FRCD_REG_HI_RW1C_MASK),
832	};
833	AssertCompile(sizeof(g_au32Rw1cMasks1) == DMAR_MMIO_GROUP_1_SIZE);
834
835	/** Array of RW masks for each register group. */
836	static uint8_t const g_apbRwMasks[] = { (uint8_t )&g_au32RwMasks0[0], (uint8_t *)&g_au32RwMasks1[0] };
837
838	/** Array of RW1C masks for each register group. */
839	static uint8_t const g_apbRw1cMasks[] = { (uint8_t )&g_au32Rw1cMasks0[0], (uint8_t *)&g_au32Rw1cMasks1[0] };
840
841	/* Masks arrays must be identical in size (even bounds checking code assumes this). */
842	AssertCompile(sizeof(g_apbRw1cMasks) == sizeof(g_apbRwMasks));
843
844	/** Array of valid domain-ID bits. */
845	static uint16_t const g_auNdMask[] = { 0xf, 0x3f, 0xff, 0x3ff, 0xfff, 0x3fff, 0xffff, 0 };
846	AssertCompile(RT_ELEMENTS(g_auNdMask) >= DMAR_ND);
847
848
849	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
850	/** @todo Add IOMMU struct size/alignment verification, see
851	* Devices/testcase/Makefile.kmk and
852	* Devices/testcase/tstDeviceStructSize[RC].cpp */
853
854	/**
855	* Returns the supported adjusted guest-address width (SAGAW) given the maximum
856	* guest address width (MGAW).
857	*
858	* @returns The CAP_REG.SAGAW value.
859	* @param uMgaw The CAP_REG.MGAW value.
860	*/
861	static uint8_t vtdCapRegGetSagaw(uint8_t uMgaw)
862	{
863	/*
864	* It doesn't make sense to me that a CPU (or IOMMU hardware) will ever support
865	* 5-level paging but not 4 or 3-level paging. So smaller page-table levels
866	* are always OR'ed in below.
867	*
868	* The bit values below (57, 48, 39 bits) represents the levels of page-table walks
869	* for 4KB base page size (5-level, 4-level and 3-level paging respectively).
870	*
871	* See Intel VT-d spec. 10.4.2 "Capability Register".
872	*/
873	++uMgaw;
874	uint8_t const fSagaw = uMgaw >= 57 ? RT_BIT(3) \| RT_BIT(2) \| RT_BIT(1)
875	: uMgaw >= 48 ? RT_BIT(2) \| RT_BIT(1)
876	: uMgaw >= 39 ? RT_BIT(1)
877	: 0;
878	return fSagaw;
879	}
880
881
882	/**
883	* Returns the maximum supported paging level given the supported adjusted
884	* guest-address width (SAGAW) field.
885	*
886	* @returns The highest paging level supported, 0 if invalid.
887	* @param fSagaw The CAP_REG.SAGAW value.
888	*/
889	static uint8_t vtdCapRegGetMaxPagingLevel(uint8_t fSagaw)
890	{
891	uint8_t const cMaxPagingLevel = fSagaw & RT_BIT(3) ? 5
892	: fSagaw & RT_BIT(2) ? 4
893	: fSagaw & RT_BIT(1) ? 3
894	: 0;
895	return cMaxPagingLevel;
896	}
897
898
899	/**
900	* Returns whether the interrupt remapping (IR) fault is qualified or not.
901	*
902	* @returns @c true if qualified, @c false otherwise.
903	* @param enmIrFault The interrupt remapping fault condition.
904	*/
905	static bool vtdIrFaultIsQualified(VTDIRFAULT enmIrFault)
906	{
907	switch (enmIrFault)
908	{
909	case VTDIRFAULT_IRTE_NOT_PRESENT:
910	case VTDIRFAULT_IRTE_PRESENT_RSVD:
911	case VTDIRFAULT_IRTE_PRESENT_INVALID:
912	case VTDIRFAULT_PID_READ_FAILED:
913	case VTDIRFAULT_PID_RSVD:
914	return true;
915	default:
916	return false;
917	}
918	}
919
920
921	/**
922	* Returns table translation mode's descriptive name.
923	*
924	* @returns The descriptive name.
925	* @param uTtm The RTADDR_REG.TTM value.
926	*/
927	static const char* vtdRtaddrRegGetTtmDesc(uint8_t uTtm)
928	{
929	Assert(!(uTtm & 3));
930	static const char* s_apszTtmNames[] =
931	{
932	"Legacy Mode",
933	"Scalable Mode",
934	"Reserved",
935	"Abort-DMA Mode"
936	};
937	return s_apszTtmNames[uTtm & (RT_ELEMENTS(s_apszTtmNames) - 1)];
938	}
939
940
941	/**
942	* Gets the index of the group the register belongs to given its MMIO offset.
943	*
944	* @returns The group index.
945	* @param offReg The MMIO offset of the register.
946	* @param cbReg The size of the access being made (for bounds checking on
947	* debug builds).
948	*/
949	DECLINLINE(uint8_t) dmarRegGetGroupIndex(uint16_t offReg, uint8_t cbReg)
950	{
951	uint16_t const offLast = offReg + cbReg - 1;
952	AssertCompile(DMAR_MMIO_GROUP_0_OFF_FIRST == 0);
953	AssertMsg(DMAR_IS_MMIO_OFF_VALID(offLast), ("off=%#x cb=%u\n", offReg, cbReg));
954	return !(offLast < DMAR_MMIO_GROUP_0_OFF_END);
955	}
956
957
958	/**
959	* Gets the group the register belongs to given its MMIO offset.
960	*
961	* @returns Pointer to the first element of the register group.
962	* @param pThis The shared DMAR device state.
963	* @param offReg The MMIO offset of the register.
964	* @param cbReg The size of the access being made (for bounds checking on
965	* debug builds).
966	* @param pIdxGroup Where to store the index of the register group the register
967	* belongs to.
968	*/
969	DECLINLINE(uint8_t ) dmarRegGetGroup(PDMAR pThis, uint16_t offReg, uint8_t cbReg, uint8_t pIdxGroup)
970	{
971	*pIdxGroup = dmarRegGetGroupIndex(offReg, cbReg);
972	uint8_t *apbRegs[] = { &pThis->abRegs0[0], &pThis->abRegs1[0] };
973	return apbRegs[*pIdxGroup];
974	}
975
976
977	/**
978	* Const/read-only version of dmarRegGetGroup.
979	*
980	* @copydoc dmarRegGetGroup
981	*/
982	DECLINLINE(uint8_t const) dmarRegGetGroupRo(PCDMAR pThis, uint16_t offReg, uint8_t cbReg, uint8_t pIdxGroup)
983	{
984	*pIdxGroup = dmarRegGetGroupIndex(offReg, cbReg);
985	uint8_t const *apbRegs[] = { &pThis->abRegs0[0], &pThis->abRegs1[0] };
986	return apbRegs[*pIdxGroup];
987	}
988
989
990	/**
991	* Writes a 32-bit register with the exactly the supplied value.
992	*
993	* @param pThis The shared DMAR device state.
994	* @param offReg The MMIO offset of the register.
995	* @param uReg The 32-bit value to write.
996	*/
997	static void dmarRegWriteRaw32(PDMAR pThis, uint16_t offReg, uint32_t uReg)
998	{
999	uint8_t idxGroup;
1000	uint8_t *pabRegs = dmarRegGetGroup(pThis, offReg, sizeof(uint32_t), &idxGroup);
1001	NOREF(idxGroup);
1002	(uint32_t )(pabRegs + offReg) = uReg;
1003	}
1004
1005
1006	/**
1007	* Writes a 64-bit register with the exactly the supplied value.
1008	*
1009	* @param pThis The shared DMAR device state.
1010	* @param offReg The MMIO offset of the register.
1011	* @param uReg The 64-bit value to write.
1012	*/
1013	static void dmarRegWriteRaw64(PDMAR pThis, uint16_t offReg, uint64_t uReg)
1014	{
1015	uint8_t idxGroup;
1016	uint8_t *pabRegs = dmarRegGetGroup(pThis, offReg, sizeof(uint64_t), &idxGroup);
1017	NOREF(idxGroup);
1018	(uint64_t )(pabRegs + offReg) = uReg;
1019	}
1020
1021
1022	/**
1023	* Reads a 32-bit register with exactly the value it contains.
1024	*
1025	* @returns The raw register value.
1026	* @param pThis The shared DMAR device state.
1027	* @param offReg The MMIO offset of the register.
1028	*/
1029	static uint32_t dmarRegReadRaw32(PCDMAR pThis, uint16_t offReg)
1030	{
1031	uint8_t idxGroup;
1032	uint8_t const *pabRegs = dmarRegGetGroupRo(pThis, offReg, sizeof(uint32_t), &idxGroup);
1033	NOREF(idxGroup);
1034	return (uint32_t )(pabRegs + offReg);
1035	}
1036
1037
1038	/**
1039	* Reads a 64-bit register with exactly the value it contains.
1040	*
1041	* @returns The raw register value.
1042	* @param pThis The shared DMAR device state.
1043	* @param offReg The MMIO offset of the register.
1044	*/
1045	static uint64_t dmarRegReadRaw64(PCDMAR pThis, uint16_t offReg)
1046	{
1047	uint8_t idxGroup;
1048	uint8_t const *pabRegs = dmarRegGetGroupRo(pThis, offReg, sizeof(uint64_t), &idxGroup);
1049	NOREF(idxGroup);
1050	return (uint64_t )(pabRegs + offReg);
1051	}
1052
1053
1054	/**
1055	* Reads a 32-bit register with exactly the value it contains along with their
1056	* corresponding masks
1057	*
1058	* @param pThis The shared DMAR device state.
1059	* @param offReg The MMIO offset of the register.
1060	* @param puReg Where to store the raw 32-bit register value.
1061	* @param pfRwMask Where to store the RW mask corresponding to this register.
1062	* @param pfRw1cMask Where to store the RW1C mask corresponding to this register.
1063	*/
1064	static void dmarRegReadRaw32Ex(PCDMAR pThis, uint16_t offReg, uint32_t puReg, uint32_t pfRwMask, uint32_t *pfRw1cMask)
1065	{
1066	uint8_t idxGroup;
1067	uint8_t const *pabRegs = dmarRegGetGroupRo(pThis, offReg, sizeof(uint32_t), &idxGroup);
1068	Assert(idxGroup < RT_ELEMENTS(g_apbRwMasks));
1069	uint8_t const *pabRwMasks = g_apbRwMasks[idxGroup];
1070	uint8_t const *pabRw1cMasks = g_apbRw1cMasks[idxGroup];
1071	puReg = (uint32_t *)(pabRegs + offReg);
1072	pfRwMask = (uint32_t *)(pabRwMasks + offReg);
1073	pfRw1cMask = (uint32_t *)(pabRw1cMasks + offReg);
1074	}
1075
1076
1077	/**
1078	* Reads a 64-bit register with exactly the value it contains along with their
1079	* corresponding masks.
1080	*
1081	* @param pThis The shared DMAR device state.
1082	* @param offReg The MMIO offset of the register.
1083	* @param puReg Where to store the raw 64-bit register value.
1084	* @param pfRwMask Where to store the RW mask corresponding to this register.
1085	* @param pfRw1cMask Where to store the RW1C mask corresponding to this register.
1086	*/
1087	static void dmarRegReadRaw64Ex(PCDMAR pThis, uint16_t offReg, uint64_t puReg, uint64_t pfRwMask, uint64_t *pfRw1cMask)
1088	{
1089	uint8_t idxGroup;
1090	uint8_t const *pabRegs = dmarRegGetGroupRo(pThis, offReg, sizeof(uint64_t), &idxGroup);
1091	Assert(idxGroup < RT_ELEMENTS(g_apbRwMasks));
1092	uint8_t const *pabRwMasks = g_apbRwMasks[idxGroup];
1093	uint8_t const *pabRw1cMasks = g_apbRw1cMasks[idxGroup];
1094	puReg = (uint64_t *)(pabRegs + offReg);
1095	pfRwMask = (uint64_t *)(pabRwMasks + offReg);
1096	pfRw1cMask = (uint64_t *)(pabRw1cMasks + offReg);
1097	}
1098
1099
1100	/**
1101	* Writes a 32-bit register as it would be when written by software.
1102	* This will preserve read-only bits, mask off reserved bits and clear RW1C bits.
1103	*
1104	* @returns The value that's actually written to the register.
1105	* @param pThis The shared DMAR device state.
1106	* @param offReg The MMIO offset of the register.
1107	* @param uReg The 32-bit value to write.
1108	* @param puPrev Where to store the register value prior to writing.
1109	*/
1110	static uint32_t dmarRegWrite32(PDMAR pThis, uint16_t offReg, uint32_t uReg, uint32_t *puPrev)
1111	{
1112	/* Read current value from the 32-bit register. */
1113	uint32_t uCurReg;
1114	uint32_t fRwMask;
1115	uint32_t fRw1cMask;
1116	dmarRegReadRaw32Ex(pThis, offReg, &uCurReg, &fRwMask, &fRw1cMask);
1117	*puPrev = uCurReg;
1118
1119	uint32_t const fRoBits = uCurReg & ~fRwMask; /* Preserve current read-only and reserved bits. */
1120	uint32_t const fRwBits = uReg & fRwMask; /* Merge newly written read/write bits. */
1121	uint32_t const fRw1cBits = uReg & fRw1cMask; /* Clear 1s written to RW1C bits. */
1122	uint32_t const uNewReg = (fRoBits \| fRwBits) & ~fRw1cBits;
1123
1124	/* Write new value to the 32-bit register. */
1125	dmarRegWriteRaw32(pThis, offReg, uNewReg);
1126	return uNewReg;
1127	}
1128
1129
1130	/**
1131	* Writes a 64-bit register as it would be when written by software.
1132	* This will preserve read-only bits, mask off reserved bits and clear RW1C bits.
1133	*
1134	* @returns The value that's actually written to the register.
1135	* @param pThis The shared DMAR device state.
1136	* @param offReg The MMIO offset of the register.
1137	* @param uReg The 64-bit value to write.
1138	* @param puPrev Where to store the register value prior to writing.
1139	*/
1140	static uint64_t dmarRegWrite64(PDMAR pThis, uint16_t offReg, uint64_t uReg, uint64_t *puPrev)
1141	{
1142	/* Read current value from the 64-bit register. */
1143	uint64_t uCurReg;
1144	uint64_t fRwMask;
1145	uint64_t fRw1cMask;
1146	dmarRegReadRaw64Ex(pThis, offReg, &uCurReg, &fRwMask, &fRw1cMask);
1147	*puPrev = uCurReg;
1148
1149	uint64_t const fRoBits = uCurReg & ~fRwMask; /* Preserve current read-only and reserved bits. */
1150	uint64_t const fRwBits = uReg & fRwMask; /* Merge newly written read/write bits. */
1151	uint64_t const fRw1cBits = uReg & fRw1cMask; /* Clear 1s written to RW1C bits. */
1152	uint64_t const uNewReg = (fRoBits \| fRwBits) & ~fRw1cBits;
1153
1154	/* Write new value to the 64-bit register. */
1155	dmarRegWriteRaw64(pThis, offReg, uNewReg);
1156	return uNewReg;
1157	}
1158
1159
1160	/**
1161	* Reads a 32-bit register as it would be when read by software.
1162	*
1163	* @returns The register value.
1164	* @param pThis The shared DMAR device state.
1165	* @param offReg The MMIO offset of the register.
1166	*/
1167	static uint32_t dmarRegRead32(PCDMAR pThis, uint16_t offReg)
1168	{
1169	return dmarRegReadRaw32(pThis, offReg);
1170	}
1171
1172
1173	/**
1174	* Reads a 64-bit register as it would be when read by software.
1175	*
1176	* @returns The register value.
1177	* @param pThis The shared DMAR device state.
1178	* @param offReg The MMIO offset of the register.
1179	*/
1180	static uint64_t dmarRegRead64(PCDMAR pThis, uint16_t offReg)
1181	{
1182	return dmarRegReadRaw64(pThis, offReg);
1183	}
1184
1185
1186	/**
1187	* Modifies a 32-bit register.
1188	*
1189	* @param pThis The shared DMAR device state.
1190	* @param offReg The MMIO offset of the register.
1191	* @param fAndMask The AND mask (applied first).
1192	* @param fOrMask The OR mask.
1193	* @remarks This does NOT apply RO or RW1C masks while modifying the
1194	* register.
1195	*/
1196	static void dmarRegChangeRaw32(PDMAR pThis, uint16_t offReg, uint32_t fAndMask, uint32_t fOrMask)
1197	{
1198	uint32_t uReg = dmarRegReadRaw32(pThis, offReg);
1199	uReg = (uReg & fAndMask) \| fOrMask;
1200	dmarRegWriteRaw32(pThis, offReg, uReg);
1201	}
1202
1203
1204	/**
1205	* Modifies a 64-bit register.
1206	*
1207	* @param pThis The shared DMAR device state.
1208	* @param offReg The MMIO offset of the register.
1209	* @param fAndMask The AND mask (applied first).
1210	* @param fOrMask The OR mask.
1211	* @remarks This does NOT apply RO or RW1C masks while modifying the
1212	* register.
1213	*/
1214	static void dmarRegChangeRaw64(PDMAR pThis, uint16_t offReg, uint64_t fAndMask, uint64_t fOrMask)
1215	{
1216	uint64_t uReg = dmarRegReadRaw64(pThis, offReg);
1217	uReg = (uReg & fAndMask) \| fOrMask;
1218	dmarRegWriteRaw64(pThis, offReg, uReg);
1219	}
1220
1221
1222	/**
1223	* Checks if the invalidation-queue is empty.
1224	*
1225	* Extended version which optionally returns the current queue head and tail
1226	* offsets.
1227	*
1228	* @returns @c true if empty, @c false otherwise.
1229	* @param pThis The shared DMAR device state.
1230	* @param poffQh Where to store the queue head offset. Optional, can be NULL.
1231	* @param poffQt Where to store the queue tail offset. Optional, can be NULL.
1232	*/
1233	static bool dmarInvQueueIsEmptyEx(PCDMAR pThis, uint32_t poffQh, uint32_t poffQt)
1234	{
1235	/* Read only the low-32 bits of the queue head and queue tail as high bits are all RsvdZ.*/
1236	uint32_t const uIqtReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IQT_REG);
1237	uint32_t const uIqhReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IQH_REG);
1238
1239	/* Don't bother masking QT, QH since other bits are RsvdZ. */
1240	Assert(!(uIqtReg & ~VTD_BF_IQT_REG_QT_MASK));
1241	Assert(!(uIqhReg & ~VTD_BF_IQH_REG_QH_MASK));
1242	if (poffQh)
1243	*poffQh = uIqhReg;
1244	if (poffQt)
1245	*poffQt = uIqtReg;
1246	return uIqtReg == uIqhReg;
1247	}
1248
1249
1250	/**
1251	* Checks if the invalidation-queue is empty.
1252	*
1253	* @returns @c true if empty, @c false otherwise.
1254	* @param pThis The shared DMAR device state.
1255	*/
1256	static bool dmarInvQueueIsEmpty(PCDMAR pThis)
1257	{
1258	return dmarInvQueueIsEmptyEx(pThis, NULL /* poffQh /, NULL / poffQt */);
1259	}
1260
1261
1262	/**
1263	* Checks if the invalidation-queue is capable of processing requests.
1264	*
1265	* @returns @c true if the invalidation-queue can process requests, @c false
1266	* otherwise.
1267	* @param pThis The shared DMAR device state.
1268	*/
1269	static bool dmarInvQueueCanProcessRequests(PCDMAR pThis)
1270	{
1271	/* Check if queued-invalidation is enabled. */
1272	uint32_t const uGstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GSTS_REG);
1273	if (uGstsReg & VTD_BF_GSTS_REG_QIES_MASK)
1274	{
1275	/* Check if there are no invalidation-queue or timeout errors. */
1276	uint32_t const uFstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FSTS_REG);
1277	if (!(uFstsReg & (VTD_BF_FSTS_REG_IQE_MASK \| VTD_BF_FSTS_REG_ITE_MASK)))
1278	return true;
1279	}
1280	return false;
1281	}
1282
1283
1284	/**
1285	* Wakes up the invalidation-queue thread if there are requests to be processed.
1286	*
1287	* @param pDevIns The IOMMU device instance.
1288	*/
1289	static void dmarInvQueueThreadWakeUpIfNeeded(PPDMDEVINS pDevIns)
1290	{
1291	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1292	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1293	Log4Func(("\n"));
1294
1295	DMAR_ASSERT_LOCK_IS_OWNER(pDevIns, pThisCC);
1296
1297	if ( dmarInvQueueCanProcessRequests(pThis)
1298	&& !dmarInvQueueIsEmpty(pThis))
1299	{
1300	Log4Func(("Signaling the invalidation-queue thread\n"));
1301	PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEvtInvQueue);
1302	}
1303	}
1304
1305
1306	/**
1307	* Raises an event on behalf of the DMAR.
1308	*
1309	* These are events that are generated by the DMAR itself (like faults and
1310	* invalidation completion notifications).
1311	*
1312	* @param pDevIns The IOMMU device instance.
1313	* @param enmEventType The DMAR event type.
1314	*
1315	* @remarks The DMAR lock must be held while calling this function.
1316	*/
1317	static void dmarEventRaiseInterrupt(PPDMDEVINS pDevIns, DMAREVENTTYPE enmEventType)
1318	{
1319	uint16_t offCtlReg;
1320	uint32_t fIntrMaskedMask;
1321	uint32_t fIntrPendingMask;
1322	uint16_t offMsiAddrLoReg;
1323	uint16_t offMsiAddrHiReg;
1324	uint16_t offMsiDataReg;
1325	switch (enmEventType)
1326	{
1327	case DMAREVENTTYPE_INV_COMPLETE:
1328	{
1329	offCtlReg = VTD_MMIO_OFF_IECTL_REG;
1330	fIntrMaskedMask = VTD_BF_IECTL_REG_IM_MASK;
1331	fIntrPendingMask = VTD_BF_IECTL_REG_IP_MASK;
1332	offMsiAddrLoReg = VTD_MMIO_OFF_IEADDR_REG;
1333	offMsiAddrHiReg = VTD_MMIO_OFF_IEUADDR_REG;
1334	offMsiDataReg = VTD_MMIO_OFF_IEDATA_REG;
1335	break;
1336	}
1337
1338	case DMAREVENTTYPE_FAULT:
1339	{
1340	offCtlReg = VTD_MMIO_OFF_FECTL_REG;
1341	fIntrMaskedMask = VTD_BF_FECTL_REG_IM_MASK;
1342	fIntrPendingMask = VTD_BF_FECTL_REG_IP_MASK;
1343	offMsiAddrLoReg = VTD_MMIO_OFF_FEADDR_REG;
1344	offMsiAddrHiReg = VTD_MMIO_OFF_FEUADDR_REG;
1345	offMsiDataReg = VTD_MMIO_OFF_FEDATA_REG;
1346	break;
1347	}
1348
1349	default:
1350	{
1351	/* Shouldn't ever happen. */
1352	AssertMsgFailedReturnVoid(("DMAR event type %#x unknown!\n", enmEventType));
1353	}
1354	}
1355
1356	/* Check if software has masked the interrupt. */
1357	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1358	uint32_t uCtlReg = dmarRegReadRaw32(pThis, offCtlReg);
1359	if (!(uCtlReg & fIntrMaskedMask))
1360	{
1361	/*
1362	* Interrupt is unmasked, raise it.
1363	* Interrupts generated by the DMAR have trigger mode and level as 0.
1364	* See Intel spec. 5.1.6 "Remapping Hardware Event Interrupt Programming".
1365	*/
1366	MSIMSG Msi;
1367	Msi.Addr.au32[0] = dmarRegReadRaw32(pThis, offMsiAddrLoReg);
1368	Msi.Addr.au32[1] = (pThis->fExtCapReg & VTD_BF_ECAP_REG_EIM_MASK) ? dmarRegReadRaw32(pThis, offMsiAddrHiReg) : 0;
1369	Msi.Data.u32 = dmarRegReadRaw32(pThis, offMsiDataReg);
1370	Assert(Msi.Data.n.u1Level == 0);
1371	Assert(Msi.Data.n.u1TriggerMode == 0);
1372
1373	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1374	pThisCC->CTX_SUFF(pIommuHlp)->pfnSendMsi(pDevIns, &Msi, 0 /* uTagSrc */);
1375
1376	/* Clear interrupt pending bit. */
1377	uCtlReg &= ~fIntrPendingMask;
1378	dmarRegWriteRaw32(pThis, offCtlReg, uCtlReg);
1379	}
1380	else
1381	{
1382	/* Interrupt is masked, set the interrupt pending bit. */
1383	uCtlReg \|= fIntrPendingMask;
1384	dmarRegWriteRaw32(pThis, offCtlReg, uCtlReg);
1385	}
1386	}
1387
1388
1389	/**
1390	* Raises an interrupt in response to a fault event.
1391	*
1392	* @param pDevIns The IOMMU device instance.
1393	*
1394	* @remarks This assumes the caller has already set the required status bits in the
1395	* FSTS_REG (namely one or more of PPF, PFO, IQE, ICE or ITE bits).
1396	*/
1397	static void dmarFaultEventRaiseInterrupt(PPDMDEVINS pDevIns)
1398	{
1399	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1400	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1401	DMAR_ASSERT_LOCK_IS_OWNER(pDevIns, pThisCC);
1402
1403	#ifdef RT_STRICT
1404	{
1405	uint32_t const uFstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FSTS_REG);
1406	uint32_t const fFaultMask = VTD_BF_FSTS_REG_PPF_MASK \| VTD_BF_FSTS_REG_PFO_MASK
1407	/* \| VTD_BF_FSTS_REG_APF_MASK \| VTD_BF_FSTS_REG_AFO_MASK / / AFL not supported */
1408	/* \| VTD_BF_FSTS_REG_ICE_MASK \| VTD_BF_FSTS_REG_ITE_MASK / / Device-TLBs not supported */
1409	\| VTD_BF_FSTS_REG_IQE_MASK;
1410	Assert(uFstsReg & fFaultMask);
1411	}
1412	#endif
1413	dmarEventRaiseInterrupt(pDevIns, DMAREVENTTYPE_FAULT);
1414	}
1415
1416
1417	#ifdef IN_RING3
1418	/**
1419	* Raises an interrupt in response to an invalidation (complete) event.
1420	*
1421	* @param pDevIns The IOMMU device instance.
1422	*/
1423	static void dmarR3InvEventRaiseInterrupt(PPDMDEVINS pDevIns)
1424	{
1425	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1426	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1427	DMAR_ASSERT_LOCK_IS_OWNER(pDevIns, pThisCC);
1428
1429	uint32_t const uIcsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_ICS_REG);
1430	if (!(uIcsReg & VTD_BF_ICS_REG_IWC_MASK))
1431	{
1432	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_ICS_REG, UINT32_MAX, VTD_BF_ICS_REG_IWC_MASK);
1433	dmarEventRaiseInterrupt(pDevIns, DMAREVENTTYPE_INV_COMPLETE);
1434	}
1435	}
1436	#endif /* IN_RING3 */
1437
1438
1439	/**
1440	* Checks if a primary fault can be recorded.
1441	*
1442	* @returns @c true if the fault can be recorded, @c false otherwise.
1443	* @param pDevIns The IOMMU device instance.
1444	* @param pThis The shared DMAR device state.
1445	*
1446	* @remarks Warning: This function has side-effects wrt the DMAR register state. Do
1447	* NOT call it unless there is a fault condition!
1448	*/
1449	static bool dmarPrimaryFaultCanRecord(PPDMDEVINS pDevIns, PDMAR pThis)
1450	{
1451	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1452	DMAR_ASSERT_LOCK_IS_OWNER(pDevIns, pThisCC);
1453
1454	uint32_t uFstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FSTS_REG);
1455	if (uFstsReg & VTD_BF_FSTS_REG_PFO_MASK)
1456	return false;
1457
1458	/*
1459	* If we add more FRCD registers, we'll have to loop through them here.
1460	* Since we support only one FRCD_REG, we don't support "compression of multiple faults",
1461	* nor do we need to increment FRI.
1462	*
1463	* See Intel VT-d spec. 7.2.1 "Primary Fault Logging".
1464	*/
1465	AssertCompile(DMAR_FRCD_REG_COUNT == 1);
1466	uint64_t const uFrcdRegHi = dmarRegReadRaw64(pThis, DMAR_MMIO_OFF_FRCD_HI_REG);
1467	if (uFrcdRegHi & VTD_BF_1_FRCD_REG_F_MASK)
1468	{
1469	uFstsReg \|= VTD_BF_FSTS_REG_PFO_MASK;
1470	dmarRegWriteRaw32(pThis, VTD_MMIO_OFF_FSTS_REG, uFstsReg);
1471	return false;
1472	}
1473
1474	return true;
1475	}
1476
1477
1478	/**
1479	* Records a primary fault.
1480	*
1481	* @param pDevIns The IOMMU device instance.
1482	* @param uFrcdHi The FRCD_HI_REG value for this fault.
1483	* @param uFrcdLo The FRCD_LO_REG value for this fault.
1484	*/
1485	static void dmarPrimaryFaultRecord(PPDMDEVINS pDevIns, uint64_t uFrcdHi, uint64_t uFrcdLo)
1486	{
1487	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1488	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1489
1490	DMAR_LOCK(pDevIns, pThisCC);
1491
1492	/* We don't support advance fault logging. */
1493	Assert(!(dmarRegRead32(pThis, VTD_MMIO_OFF_GSTS_REG) & VTD_BF_GSTS_REG_AFLS_MASK));
1494
1495	if (dmarPrimaryFaultCanRecord(pDevIns, pThis))
1496	{
1497	/* Update the fault recording registers with the fault information. */
1498	dmarRegWriteRaw64(pThis, DMAR_MMIO_OFF_FRCD_HI_REG, uFrcdHi);
1499	dmarRegWriteRaw64(pThis, DMAR_MMIO_OFF_FRCD_LO_REG, uFrcdLo);
1500
1501	/* Set the Pending Primary Fault (PPF) field in the status register. */
1502	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_FSTS_REG, UINT32_MAX, VTD_BF_FSTS_REG_PPF_MASK);
1503
1504	/* Raise interrupt if necessary. */
1505	dmarFaultEventRaiseInterrupt(pDevIns);
1506	}
1507
1508	DMAR_UNLOCK(pDevIns, pThisCC);
1509	}
1510
1511
1512	/**
1513	* Records an interrupt request fault.
1514	*
1515	* @param pDevIns The IOMMU device instance.
1516	* @param enmDiag The diagnostic reason.
1517	* @param idDevice The device ID (bus, device, function).
1518	* @param idxIntr The interrupt index.
1519	* @param pIrte The IRTE that caused this fault. Can be NULL if the fault is
1520	* not qualified.
1521	*/
1522	static void dmarIrFaultRecord(PPDMDEVINS pDevIns, DMARDIAG enmDiag, uint16_t idDevice, uint16_t idxIntr, PCVTD_IRTE_T pIrte)
1523	{
1524	/*
1525	* Update the diagnostic reason (even if software wants to supress faults).
1526	*/
1527	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1528	pThis->enmDiag = enmDiag;
1529
1530	/*
1531	* Figure out the fault reason to report to software from our diagnostic code.
1532	* The case labels below are sorted alphabetically for convenience.
1533	*/
1534	VTDIRFAULT enmIrFault;
1535	switch (enmDiag)
1536	{
1537	case kDmarDiag_Ir_Cfi_Blocked: enmIrFault = VTDIRFAULT_CFI_BLOCKED; break;
1538	case kDmarDiag_Ir_Rfi_Intr_Index_Invalid: enmIrFault = VTDIRFAULT_INTR_INDEX_INVALID; break;
1539	case kDmarDiag_Ir_Rfi_Irte_Mode_Invalid: enmIrFault = VTDIRFAULT_IRTE_PRESENT_RSVD; break;
1540	case kDmarDiag_Ir_Rfi_Irte_Not_Present: enmIrFault = VTDIRFAULT_IRTE_NOT_PRESENT; break;
1541	case kDmarDiag_Ir_Rfi_Irte_Read_Failed: enmIrFault = VTDIRFAULT_IRTE_READ_FAILED; break;
1542	case kDmarDiag_Ir_Rfi_Irte_Rsvd:
1543	case kDmarDiag_Ir_Rfi_Irte_Svt_Bus:
1544	case kDmarDiag_Ir_Rfi_Irte_Svt_Masked:
1545	case kDmarDiag_Ir_Rfi_Irte_Svt_Rsvd: enmIrFault = VTDIRFAULT_IRTE_PRESENT_RSVD; break;
1546	case kDmarDiag_Ir_Rfi_Rsvd: enmIrFault = VTDIRFAULT_REMAPPABLE_INTR_RSVD; break;
1547
1548	/* Shouldn't ever happen. */
1549	default:
1550	{
1551	AssertLogRelMsgFailedReturnVoid(("%s: Invalid interrupt remapping fault diagnostic code %#x\n", DMAR_LOG_PFX,
1552	enmDiag));
1553	}
1554	}
1555
1556	/*
1557	* Qualified faults are those that can be suppressed by software using the FPD bit
1558	* in the interrupt-remapping table entry.
1559	*/
1560	bool fFpd;
1561	bool const fQualifiedFault = vtdIrFaultIsQualified(enmIrFault);
1562	if (fQualifiedFault)
1563	{
1564	AssertReturnVoid(pIrte);
1565	fFpd = RT_BOOL(pIrte->au64[0] & VTD_BF_0_IRTE_FPD_MASK);
1566	}
1567	else
1568	fFpd = false;
1569
1570	if (!fFpd)
1571	{
1572	/* Construct and record the error. */
1573	uint64_t const uFrcdHi = RT_BF_MAKE(VTD_BF_1_FRCD_REG_SID, idDevice)
1574	\| RT_BF_MAKE(VTD_BF_1_FRCD_REG_FR, enmIrFault)
1575	\| RT_BF_MAKE(VTD_BF_1_FRCD_REG_F, 1);
1576	uint64_t const uFrcdLo = (uint64_t)idxIntr << 48;
1577	dmarPrimaryFaultRecord(pDevIns, uFrcdHi, uFrcdLo);
1578	}
1579	}
1580
1581
1582	/**
1583	* Records an address translation fault.
1584	*
1585	* @param pDevIns The IOMMU device instance.
1586	* @param enmDiag The diagnostic reason.
1587	* @param pMemReqIn The DMA memory request input.
1588	* @param pMemReqAux The DMA memory request auxiliary info.
1589	*/
1590	static void dmarAtFaultRecord(PPDMDEVINS pDevIns, DMARDIAG enmDiag, PCDMARMEMREQIN pMemReqIn, PCDMARMEMREQAUX pMemReqAux)
1591	{
1592	/*
1593	* Update the diagnostic reason (even if software wants to supress faults).
1594	*/
1595	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1596	pThis->enmDiag = enmDiag;
1597
1598	/*
1599	* Qualified faults are those that can be suppressed by software using the FPD bit
1600	* in the context entry, scalable-mode context entry etc.
1601	*/
1602	if (!pMemReqAux->fFpd)
1603	{
1604	/*
1605	* Figure out the fault reason to report to software from our diagnostic code.
1606	* The case labels below are sorted alphabetically for convenience.
1607	*/
1608	VTDATFAULT enmAtFault;
1609	bool const fLm = pMemReqAux->fTtm == VTD_TTM_LEGACY_MODE;
1610	switch (enmDiag)
1611	{
1612	/* LM (Legacy Mode) faults. */
1613	case kDmarDiag_At_Lm_CtxEntry_Not_Present: enmAtFault = VTDATFAULT_LCT_2; break;
1614	case kDmarDiag_At_Lm_CtxEntry_Read_Failed: enmAtFault = VTDATFAULT_LCT_1; break;
1615	case kDmarDiag_At_Lm_CtxEntry_Rsvd: enmAtFault = VTDATFAULT_LCT_3; break;
1616	case kDmarDiag_At_Lm_Pt_At_Block: enmAtFault = VTDATFAULT_LCT_5; break;
1617	case kDmarDiag_At_Lm_Pt_Aw_Invalid: enmAtFault = VTDATFAULT_LGN_1_3; break;
1618	case kDmarDiag_At_Lm_RootEntry_Not_Present: enmAtFault = VTDATFAULT_LRT_2; break;
1619	case kDmarDiag_At_Lm_RootEntry_Read_Failed: enmAtFault = VTDATFAULT_LRT_1; break;
1620	case kDmarDiag_At_Lm_RootEntry_Rsvd: enmAtFault = VTDATFAULT_LRT_3; break;
1621	case kDmarDiag_At_Lm_Tt_Invalid: enmAtFault = VTDATFAULT_LCT_4_2; break;
1622	case kDmarDiag_At_Lm_Ut_At_Block: enmAtFault = VTDATFAULT_LCT_5; break;
1623	case kDmarDiag_At_Lm_Ut_Aw_Invalid: enmAtFault = VTDATFAULT_LCT_4_1; break;
1624
1625	/* RTA (Root Table Address) faults. */
1626	case kDmarDiag_At_Rta_Adms_Not_Supported: enmAtFault = VTDATFAULT_RTA_1_1; break;
1627	case kDmarDiag_At_Rta_Rsvd: enmAtFault = VTDATFAULT_RTA_1_2; break;
1628	case kDmarDiag_At_Rta_Smts_Not_Supported: enmAtFault = VTDATFAULT_RTA_1_3; break;
1629
1630	/* XM (Legacy mode or Scalable Mode) faults. */
1631	case kDmarDiag_At_Xm_AddrIn_Invalid: enmAtFault = fLm ? VTDATFAULT_LGN_1_1 : VTDATFAULT_SGN_5; break;
1632	case kDmarDiag_At_Xm_AddrOut_Invalid: enmAtFault = fLm ? VTDATFAULT_LGN_4 : VTDATFAULT_SGN_8; break;
1633	case kDmarDiag_At_Xm_Perm_Denied: enmAtFault = fLm ? VTDATFAULT_LSL_2 : VTDATFAULT_SSL_2; break;
1634	case kDmarDiag_At_Xm_Pte_Rsvd:
1635	case kDmarDiag_At_Xm_Pte_Sllps_Invalid: enmAtFault = fLm ? VTDATFAULT_LSL_2 : VTDATFAULT_SSL_3; break;
1636	case kDmarDiag_At_Xm_Read_Pte_Failed: enmAtFault = fLm ? VTDATFAULT_LSL_1 : VTDATFAULT_SSL_1; break;
1637	case kDmarDiag_At_Xm_Slpptr_Read_Failed: enmAtFault = fLm ? VTDATFAULT_LCT_4_3 : VTDATFAULT_SSL_4; break;
1638
1639	/* Shouldn't ever happen. */
1640	default:
1641	{
1642	AssertLogRelMsgFailedReturnVoid(("%s: Invalid address translation fault diagnostic code %#x\n",
1643	DMAR_LOG_PFX, enmDiag));
1644	}
1645	}
1646
1647	/* Construct and record the error. */
1648	uint16_t const idDevice = pMemReqIn->idDevice;
1649	uint8_t const fType1 = pMemReqIn->enmReqType & RT_BIT(1);
1650	uint8_t const fType2 = pMemReqIn->enmReqType & RT_BIT(0);
1651	uint8_t const fExec = pMemReqIn->AddrRange.fPerm & DMAR_PERM_EXE;
1652	uint8_t const fPriv = pMemReqIn->AddrRange.fPerm & DMAR_PERM_PRIV;
1653	bool const fHasPasid = PCIPASID_IS_VALID(pMemReqIn->Pasid);
1654	uint32_t const uPasid = PCIPASID_VAL(pMemReqIn->Pasid);
1655	PCIADDRTYPE const enmAt = pMemReqIn->enmAddrType;
1656
1657	uint64_t const uFrcdHi = RT_BF_MAKE(VTD_BF_1_FRCD_REG_SID, idDevice)
1658	\| RT_BF_MAKE(VTD_BF_1_FRCD_REG_T2, fType2)
1659	\| RT_BF_MAKE(VTD_BF_1_FRCD_REG_PP, fHasPasid)
1660	\| RT_BF_MAKE(VTD_BF_1_FRCD_REG_EXE, fExec)
1661	\| RT_BF_MAKE(VTD_BF_1_FRCD_REG_PRIV, fPriv)
1662	\| RT_BF_MAKE(VTD_BF_1_FRCD_REG_FR, enmAtFault)
1663	\| RT_BF_MAKE(VTD_BF_1_FRCD_REG_PV, uPasid)
1664	\| RT_BF_MAKE(VTD_BF_1_FRCD_REG_AT, enmAt)
1665	\| RT_BF_MAKE(VTD_BF_1_FRCD_REG_T1, fType1)
1666	\| RT_BF_MAKE(VTD_BF_1_FRCD_REG_F, 1);
1667	uint64_t const uFrcdLo = pMemReqIn->AddrRange.uAddr & X86_PAGE_BASE_MASK;
1668	dmarPrimaryFaultRecord(pDevIns, uFrcdHi, uFrcdLo);
1669	}
1670	}
1671
1672
1673	/**
1674	* Records an IQE fault.
1675	*
1676	* @param pDevIns The IOMMU device instance.
1677	* @param enmIqei The IQE information.
1678	* @param enmDiag The diagnostic reason.
1679	*/
1680	static void dmarIqeFaultRecord(PPDMDEVINS pDevIns, DMARDIAG enmDiag, VTDIQEI enmIqei)
1681	{
1682	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1683	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1684
1685	DMAR_LOCK(pDevIns, pThisCC);
1686
1687	/* Update the diagnostic reason. */
1688	pThis->enmDiag = enmDiag;
1689
1690	/* Set the error bit. */
1691	uint32_t const fIqe = RT_BF_MAKE(VTD_BF_FSTS_REG_IQE, 1);
1692	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_FSTS_REG, UINT32_MAX, fIqe);
1693
1694	/* Set the error information. */
1695	uint64_t const fIqei = RT_BF_MAKE(VTD_BF_IQERCD_REG_IQEI, enmIqei);
1696	dmarRegChangeRaw64(pThis, VTD_MMIO_OFF_IQERCD_REG, UINT64_MAX, fIqei);
1697
1698	dmarFaultEventRaiseInterrupt(pDevIns);
1699
1700	DMAR_UNLOCK(pDevIns, pThisCC);
1701	}
1702
1703
1704	/**
1705	* Handles writes to GCMD_REG.
1706	*
1707	* @returns Strict VBox status code.
1708	* @param pDevIns The IOMMU device instance.
1709	* @param uGcmdReg The value written to GCMD_REG.
1710	*/
1711	static VBOXSTRICTRC dmarGcmdRegWrite(PPDMDEVINS pDevIns, uint32_t uGcmdReg)
1712	{
1713	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1714	uint32_t const uGstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GSTS_REG);
1715	uint32_t const fChanged = uGstsReg ^ uGcmdReg;
1716	uint64_t const fExtCapReg = pThis->fExtCapReg;
1717
1718	/* Queued-invalidation. */
1719	if ( (fExtCapReg & VTD_BF_ECAP_REG_QI_MASK)
1720	&& (fChanged & VTD_BF_GCMD_REG_QIE_MASK))
1721	{
1722	if (uGcmdReg & VTD_BF_GCMD_REG_QIE_MASK)
1723	{
1724	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, UINT32_MAX, VTD_BF_GSTS_REG_QIES_MASK);
1725	dmarInvQueueThreadWakeUpIfNeeded(pDevIns);
1726	}
1727	else
1728	{
1729	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, ~VTD_BF_GSTS_REG_QIES_MASK, 0 /* fOrMask */);
1730	dmarRegWriteRaw32(pThis, VTD_MMIO_OFF_IQH_REG, 0);
1731	}
1732	}
1733
1734	if (fExtCapReg & VTD_BF_ECAP_REG_IR_MASK)
1735	{
1736	/* Set Interrupt Remapping Table Pointer (SIRTP). */
1737	if (uGcmdReg & VTD_BF_GCMD_REG_SIRTP_MASK)
1738	{
1739	/** @todo Perform global invalidation of all interrupt-entry cache when ESIRTPS is
1740	* supported. */
1741	pThis->uIrtaReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IRTA_REG);
1742	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, UINT32_MAX, VTD_BF_GSTS_REG_IRTPS_MASK);
1743	}
1744
1745	/* Interrupt remapping. */
1746	if (fChanged & VTD_BF_GCMD_REG_IRE_MASK)
1747	{
1748	if (uGcmdReg & VTD_BF_GCMD_REG_IRE_MASK)
1749	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, UINT32_MAX, VTD_BF_GSTS_REG_IRES_MASK);
1750	else
1751	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, ~VTD_BF_GSTS_REG_IRES_MASK, 0 /* fOrMask */);
1752	}
1753
1754	/* Compatibility format interrupts. */
1755	if (fChanged & VTD_BF_GCMD_REG_CFI_MASK)
1756	{
1757	if (uGcmdReg & VTD_BF_GCMD_REG_CFI_MASK)
1758	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, UINT32_MAX, VTD_BF_GSTS_REG_CFIS_MASK);
1759	else
1760	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, ~VTD_BF_GSTS_REG_CFIS_MASK, 0 /* fOrMask */);
1761	}
1762	}
1763
1764	/* Set Root Table Pointer (SRTP). */
1765	if (uGcmdReg & VTD_BF_GCMD_REG_SRTP_MASK)
1766	{
1767	/** @todo Perform global invalidation of all remapping translation caches when
1768	* ESRTPS is supported. */
1769	pThis->uRtaddrReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_RTADDR_REG);
1770	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, UINT32_MAX, VTD_BF_GSTS_REG_RTPS_MASK);
1771	}
1772
1773	/* Translation (DMA remapping). */
1774	if (fChanged & VTD_BF_GCMD_REG_TE_MASK)
1775	{
1776	if (uGcmdReg & VTD_BF_GCMD_REG_TE_MASK)
1777	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, UINT32_MAX, VTD_BF_GSTS_REG_TES_MASK);
1778	else
1779	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, ~VTD_BF_GSTS_REG_TES_MASK, 0 /* fOrMask */);
1780	}
1781
1782	return VINF_SUCCESS;
1783	}
1784
1785
1786	/**
1787	* Handles writes to CCMD_REG.
1788	*
1789	* @returns Strict VBox status code.
1790	* @param pDevIns The IOMMU device instance.
1791	* @param offReg The MMIO register offset.
1792	* @param cbReg The size of the MMIO access (in bytes).
1793	* @param uCcmdReg The value written to CCMD_REG.
1794	*/
1795	static VBOXSTRICTRC dmarCcmdRegWrite(PPDMDEVINS pDevIns, uint16_t offReg, uint8_t cbReg, uint64_t uCcmdReg)
1796	{
1797	/* At present, we only care about responding to high 32-bits writes, low 32-bits are data. */
1798	if (offReg + cbReg > VTD_MMIO_OFF_CCMD_REG + 4)
1799	{
1800	/* Check if we need to invalidate the context-context. */
1801	bool const fIcc = RT_BF_GET(uCcmdReg, VTD_BF_CCMD_REG_ICC);
1802	if (fIcc)
1803	{
1804	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1805	uint8_t const uMajorVersion = RT_BF_GET(pThis->uVerReg, VTD_BF_VER_REG_MAX);
1806	if (uMajorVersion < 6)
1807	{
1808	/* Register-based invalidation can only be used when queued-invalidations are not enabled. */
1809	uint32_t const uGstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GSTS_REG);
1810	if (!(uGstsReg & VTD_BF_GSTS_REG_QIES_MASK))
1811	{
1812	/* Verify table translation mode is legacy. */
1813	uint8_t const fTtm = RT_BF_GET(pThis->uRtaddrReg, VTD_BF_RTADDR_REG_TTM);
1814	if (fTtm == VTD_TTM_LEGACY_MODE)
1815	{
1816	/** @todo Invalidate. */
1817	return VINF_SUCCESS;
1818	}
1819	pThis->enmDiag = kDmarDiag_CcmdReg_Ttm_Invalid;
1820	}
1821	else
1822	pThis->enmDiag = kDmarDiag_CcmdReg_Qi_Enabled;
1823	}
1824	else
1825	pThis->enmDiag = kDmarDiag_CcmdReg_Not_Supported;
1826	dmarRegChangeRaw64(pThis, VTD_MMIO_OFF_GSTS_REG, ~VTD_BF_CCMD_REG_CAIG_MASK, 0 /* fOrMask */);
1827	}
1828	}
1829	return VINF_SUCCESS;
1830	}
1831
1832
1833	/**
1834	* Handles writes to FECTL_REG.
1835	*
1836	* @returns Strict VBox status code.
1837	* @param pDevIns The IOMMU device instance.
1838	* @param uFectlReg The value written to FECTL_REG.
1839	*/
1840	static VBOXSTRICTRC dmarFectlRegWrite(PPDMDEVINS pDevIns, uint32_t uFectlReg)
1841	{
1842	/*
1843	* If software unmasks the interrupt when the interrupt is pending, we must raise
1844	* the interrupt now (which will consequently clear the interrupt pending (IP) bit).
1845	*/
1846	if ( (uFectlReg & VTD_BF_FECTL_REG_IP_MASK)
1847	&& ~(uFectlReg & VTD_BF_FECTL_REG_IM_MASK))
1848	dmarEventRaiseInterrupt(pDevIns, DMAREVENTTYPE_FAULT);
1849	return VINF_SUCCESS;
1850	}
1851
1852
1853	/**
1854	* Handles writes to FSTS_REG.
1855	*
1856	* @returns Strict VBox status code.
1857	* @param pDevIns The IOMMU device instance.
1858	* @param uFstsReg The value written to FSTS_REG.
1859	* @param uPrev The value in FSTS_REG prior to writing it.
1860	*/
1861	static VBOXSTRICTRC dmarFstsRegWrite(PPDMDEVINS pDevIns, uint32_t uFstsReg, uint32_t uPrev)
1862	{
1863	/*
1864	* If software clears other status bits in FSTS_REG (pertaining to primary fault logging),
1865	* the interrupt pending (IP) bit must be cleared.
1866	*
1867	* See Intel VT-d spec. 10.4.10 "Fault Event Control Register".
1868	*/
1869	uint32_t const fChanged = uPrev ^ uFstsReg;
1870	if (fChanged & ( VTD_BF_FSTS_REG_ICE_MASK \| VTD_BF_FSTS_REG_ITE_MASK
1871	\| VTD_BF_FSTS_REG_IQE_MASK \| VTD_BF_FSTS_REG_PFO_MASK))
1872	{
1873	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1874	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_FECTL_REG, ~VTD_BF_FECTL_REG_IP_MASK, 0 /* fOrMask */);
1875	}
1876	return VINF_SUCCESS;
1877	}
1878
1879
1880	/**
1881	* Handles writes to IQT_REG.
1882	*
1883	* @returns Strict VBox status code.
1884	* @param pDevIns The IOMMU device instance.
1885	* @param offReg The MMIO register offset.
1886	* @param uIqtReg The value written to IQT_REG.
1887	*/
1888	static VBOXSTRICTRC dmarIqtRegWrite(PPDMDEVINS pDevIns, uint16_t offReg, uint64_t uIqtReg)
1889	{
1890	/* We only care about the low 32-bits, high 32-bits are reserved. */
1891	Assert(offReg == VTD_MMIO_OFF_IQT_REG);
1892	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1893
1894	/* Paranoia. */
1895	Assert(!(uIqtReg & ~VTD_BF_IQT_REG_QT_MASK));
1896
1897	uint32_t const offQt = uIqtReg;
1898	uint64_t const uIqaReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IQA_REG);
1899	uint8_t const fDw = RT_BF_GET(uIqaReg, VTD_BF_IQA_REG_DW);
1900
1901	/* If the descriptor width is 256-bits, the queue tail offset must be aligned accordingly. */
1902	if ( fDw != VTD_IQA_REG_DW_256_BIT
1903	\|\| !(offQt & RT_BIT(4)))
1904	dmarInvQueueThreadWakeUpIfNeeded(pDevIns);
1905	else
1906	{
1907	/* Hardware treats bit 4 as RsvdZ in this situation, so clear it. */
1908	dmarRegChangeRaw32(pThis, offReg, ~RT_BIT(4), 0 /* fOrMask */);
1909	dmarIqeFaultRecord(pDevIns, kDmarDiag_IqtReg_Qt_Not_Aligned, VTDIQEI_QUEUE_TAIL_MISALIGNED);
1910	}
1911	return VINF_SUCCESS;
1912	}
1913
1914
1915	/**
1916	* Handles writes to IQA_REG.
1917	*
1918	* @returns Strict VBox status code.
1919	* @param pDevIns The IOMMU device instance.
1920	* @param offReg The MMIO register offset.
1921	* @param uIqaReg The value written to IQA_REG.
1922	*/
1923	static VBOXSTRICTRC dmarIqaRegWrite(PPDMDEVINS pDevIns, uint16_t offReg, uint64_t uIqaReg)
1924	{
1925	/* At present, we only care about the low 32-bits, high 32-bits are data. */
1926	Assert(offReg == VTD_MMIO_OFF_IQA_REG); NOREF(offReg);
1927
1928	/** @todo What happens if IQA_REG is written when dmarInvQueueCanProcessRequests
1929	* returns true? The Intel VT-d spec. doesn't state anywhere that it
1930	* cannot happen or that it's ignored when it does happen. */
1931
1932	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1933	uint8_t const fDw = RT_BF_GET(uIqaReg, VTD_BF_IQA_REG_DW);
1934	if (fDw == VTD_IQA_REG_DW_256_BIT)
1935	{
1936	bool const fSupports256BitDw = (pThis->fExtCapReg & (VTD_BF_ECAP_REG_SMTS_MASK \| VTD_BF_ECAP_REG_ADMS_MASK));
1937	if (fSupports256BitDw)
1938	{ /* likely */ }
1939	else
1940	dmarIqeFaultRecord(pDevIns, kDmarDiag_IqaReg_Dw_256_Invalid, VTDIQEI_INVALID_DESCRIPTOR_WIDTH);
1941	}
1942	/* else: 128-bit descriptor width is validated lazily, see explanation in dmarR3InvQueueProcessRequests. */
1943
1944	return VINF_SUCCESS;
1945	}
1946
1947
1948	/**
1949	* Handles writes to ICS_REG.
1950	*
1951	* @returns Strict VBox status code.
1952	* @param pDevIns The IOMMU device instance.
1953	* @param uIcsReg The value written to ICS_REG.
1954	*/
1955	static VBOXSTRICTRC dmarIcsRegWrite(PPDMDEVINS pDevIns, uint32_t uIcsReg)
1956	{
1957	/*
1958	* If the IP field is set when software services the interrupt condition,
1959	* (by clearing the IWC field), the IP field must be cleared.
1960	*/
1961	if (!(uIcsReg & VTD_BF_ICS_REG_IWC_MASK))
1962	{
1963	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1964	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_IECTL_REG, ~VTD_BF_IECTL_REG_IP_MASK, 0 /* fOrMask */);
1965	}
1966	return VINF_SUCCESS;
1967	}
1968
1969
1970	/**
1971	* Handles writes to IECTL_REG.
1972	*
1973	* @returns Strict VBox status code.
1974	* @param pDevIns The IOMMU device instance.
1975	* @param uIectlReg The value written to IECTL_REG.
1976	*/
1977	static VBOXSTRICTRC dmarIectlRegWrite(PPDMDEVINS pDevIns, uint32_t uIectlReg)
1978	{
1979	/*
1980	* If software unmasks the interrupt when the interrupt is pending, we must raise
1981	* the interrupt now (which will consequently clear the interrupt pending (IP) bit).
1982	*/
1983	if ( (uIectlReg & VTD_BF_IECTL_REG_IP_MASK)
1984	&& ~(uIectlReg & VTD_BF_IECTL_REG_IM_MASK))
1985	dmarEventRaiseInterrupt(pDevIns, DMAREVENTTYPE_INV_COMPLETE);
1986	return VINF_SUCCESS;
1987	}
1988
1989
1990	/**
1991	* Handles writes to FRCD_REG (High 64-bits).
1992	*
1993	* @returns Strict VBox status code.
1994	* @param pDevIns The IOMMU device instance.
1995	* @param offReg The MMIO register offset.
1996	* @param cbReg The size of the MMIO access (in bytes).
1997	* @param uFrcdHiReg The value written to FRCD_REG.
1998	* @param uPrev The value in FRCD_REG prior to writing it.
1999	*/
2000	static VBOXSTRICTRC dmarFrcdHiRegWrite(PPDMDEVINS pDevIns, uint16_t offReg, uint8_t cbReg, uint64_t uFrcdHiReg, uint64_t uPrev)
2001	{
2002	/* We only care about responding to high 32-bits, low 32-bits are read-only. */
2003	if (offReg + cbReg > DMAR_MMIO_OFF_FRCD_HI_REG + 4)
2004	{
2005	/*
2006	* If software cleared the RW1C F (fault) bit in all FRCD_REGs, hardware clears the
2007	* Primary Pending Fault (PPF) and the interrupt pending (IP) bits. Our implementation
2008	* has only 1 FRCD register.
2009	*
2010	* See Intel VT-d spec. 10.4.10 "Fault Event Control Register".
2011	*/
2012	AssertCompile(DMAR_FRCD_REG_COUNT == 1);
2013	uint64_t const fChanged = uPrev ^ uFrcdHiReg;
2014	if (fChanged & VTD_BF_1_FRCD_REG_F_MASK)
2015	{
2016	Assert(!(uFrcdHiReg & VTD_BF_1_FRCD_REG_F_MASK)); /* Software should only ever be able to clear this bit. */
2017	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
2018	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_FSTS_REG, ~VTD_BF_FSTS_REG_PPF_MASK, 0 /* fOrMask */);
2019	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_FECTL_REG, ~VTD_BF_FECTL_REG_IP_MASK, 0 /* fOrMask */);
2020	}
2021	}
2022	return VINF_SUCCESS;
2023	}
2024
2025
2026	/**
2027	* Performs a PCI target abort for a DMA remapping (DR) operation.
2028	*
2029	* @param pDevIns The IOMMU device instance.
2030	*/
2031	static void dmarDrTargetAbort(PPDMDEVINS pDevIns)
2032	{
2033	/** @todo r=ramshankar: I don't know for sure if a PCI target abort is caused or not
2034	* as the Intel VT-d spec. is vague. Wording seems to suggest it does, but
2035	* who knows. */
2036	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
2037	uint16_t const u16Status = PDMPciDevGetStatus(pPciDev) \| VBOX_PCI_STATUS_SIG_TARGET_ABORT;
2038	PDMPciDevSetStatus(pPciDev, u16Status);
2039	}
2040
2041
2042	/**
2043	* Checks whether the address width (AW) is supported by our hardware
2044	* implementation for legacy mode address translation.
2045	*
2046	* @returns @c true if it's supported, @c false otherwise.
2047	* @param pThis The shared DMAR device state.
2048	* @param pCtxEntry The context entry.
2049	* @param pcPagingLevel Where to store the paging level. Optional, can be NULL.
2050	*/
2051	static bool dmarDrLegacyModeIsAwValid(PCDMAR pThis, PCVTD_CONTEXT_ENTRY_T pCtxEntry, uint8_t *pcPagingLevel)
2052	{
2053	uint8_t const fTt = RT_BF_GET(pCtxEntry->au64[0], VTD_BF_0_CONTEXT_ENTRY_TT);
2054	uint8_t const fAw = RT_BF_GET(pCtxEntry->au64[1], VTD_BF_1_CONTEXT_ENTRY_AW);
2055	uint8_t const fAwMask = RT_BIT(fAw);
2056	uint8_t const fSagaw = RT_BF_GET(pThis->fCapReg, VTD_BF_CAP_REG_SAGAW);
2057	Assert(!(fSagaw & ~(RT_BIT(1) \| RT_BIT(2) \| RT_BIT(3))));
2058
2059	uint8_t const cPagingLevel = fAw + 2;
2060	if (pcPagingLevel)
2061	*pcPagingLevel = cPagingLevel;
2062
2063	/* With pass-through, the address width must be the largest AGAW supported by hardware. */
2064	if (fTt == VTD_TT_UNTRANSLATED_PT)
2065	{
2066	Assert(pThis->cMaxPagingLevel >= 3 && pThis->cMaxPagingLevel <= 5); /* Paranoia. */
2067	return cPagingLevel == pThis->cMaxPagingLevel;
2068	}
2069
2070	/* The address width must be any of the ones supported by hardware. */
2071	if (fAw < 4)
2072	return (fSagaw & fAwMask) != 0;
2073
2074	return false;
2075	}
2076
2077
2078	/**
2079	* Reads a root entry from guest memory.
2080	*
2081	* @returns VBox status code.
2082	* @param pDevIns The IOMMU device instance.
2083	* @param uRtaddrReg The current RTADDR_REG value.
2084	* @param idxRootEntry The index of the root entry to read.
2085	* @param pRootEntry Where to store the read root entry.
2086	*/
2087	static int dmarDrReadRootEntry(PPDMDEVINS pDevIns, uint64_t uRtaddrReg, uint8_t idxRootEntry, PVTD_ROOT_ENTRY_T pRootEntry)
2088	{
2089	size_t const cbRootEntry = sizeof(*pRootEntry);
2090	RTGCPHYS const GCPhysRootEntry = (uRtaddrReg & VTD_BF_RTADDR_REG_RTA_MASK) + (idxRootEntry * cbRootEntry);
2091	return PDMDevHlpPhysReadMeta(pDevIns, GCPhysRootEntry, pRootEntry, cbRootEntry);
2092	}
2093
2094
2095	/**
2096	* Reads a context entry from guest memory.
2097	*
2098	* @returns VBox status code.
2099	* @param pDevIns The IOMMU device instance.
2100	* @param GCPhysCtxTable The physical address of the context table.
2101	* @param idxCtxEntry The index of the context entry to read.
2102	* @param pCtxEntry Where to store the read context entry.
2103	*/
2104	static int dmarDrReadCtxEntry(PPDMDEVINS pDevIns, RTGCPHYS GCPhysCtxTable, uint8_t idxCtxEntry, PVTD_CONTEXT_ENTRY_T pCtxEntry)
2105	{
2106	/* We don't verify bits 63:HAW of GCPhysCtxTable is 0 since reading from such an address should fail anyway. */
2107	size_t const cbCtxEntry = sizeof(*pCtxEntry);
2108	RTGCPHYS const GCPhysCtxEntry = GCPhysCtxTable + (idxCtxEntry * cbCtxEntry);
2109	return PDMDevHlpPhysReadMeta(pDevIns, GCPhysCtxEntry, pCtxEntry, cbCtxEntry);
2110	}
2111
2112
2113	/**
2114	* Validates and updates the output I/O page of a translation.
2115	*
2116	* @returns VBox status code.
2117	* @param pDevIns The IOMMU device instance.
2118	* @param GCPhysBase The output address of the translation.
2119	* @param cShift The page shift of the translated address.
2120	* @param fPerm The permissions granted for the translated region.
2121	* @param pMemReqIn The DMA memory request input.
2122	* @param pMemReqAux The DMA memory request auxiliary info.
2123	* @param pIoPageOut Where to store the output of the translation.
2124	*/
2125	static int dmarDrUpdateIoPageOut(PPDMDEVINS pDevIns, RTGCPHYS GCPhysBase, uint8_t cShift, uint8_t fPerm,
2126	PCDMARMEMREQIN pMemReqIn, PCDMARMEMREQAUX pMemReqAux, PDMARIOPAGE pIoPageOut)
2127	{
2128	Assert(!(GCPhysBase & X86_PAGE_4K_OFFSET_MASK));
2129
2130	/* Ensure the output address is not in the interrupt address range. */
2131	if (GCPhysBase - VBOX_MSI_ADDR_BASE >= VBOX_MSI_ADDR_SIZE)
2132	{
2133	pIoPageOut->GCPhysBase = GCPhysBase;
2134	pIoPageOut->cShift = cShift;
2135	pIoPageOut->fPerm = fPerm;
2136	return VINF_SUCCESS;
2137	}
2138
2139	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Xm_AddrOut_Invalid, pMemReqIn, pMemReqAux);
2140	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2141	}
2142
2143
2144	/**
2145	* Performs second level translation by walking the I/O page tables.
2146	*
2147	* This is a DMA address-lookup callback function which performs the translation
2148	* (and access control) as part of the lookup.
2149	*
2150	* @returns VBox status code.
2151	* @param pDevIns The IOMMU device instance.
2152	* @param pMemReqIn The DMA memory request input.
2153	* @param pMemReqAux The DMA memory request auxiliary info.
2154	* @param pIoPageOut Where to store the output of the translation.
2155	*/
2156	static DECLCALLBACK(int) dmarDrSecondLevelTranslate(PPDMDEVINS pDevIns, PCDMARMEMREQIN pMemReqIn, PCDMARMEMREQAUX pMemReqAux,
2157	PDMARIOPAGE pIoPageOut)
2158	{
2159	PCDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PCDMAR);
2160
2161	/* Sanity. */
2162	Assert(pIoPageOut);
2163	Assert(pMemReqIn->AddrRange.fPerm & (DMAR_PERM_READ \| DMAR_PERM_WRITE));
2164	Assert( pMemReqAux->fTtm == VTD_TTM_LEGACY_MODE
2165	\|\| pMemReqAux->fTtm == VTD_TTM_SCALABLE_MODE);
2166	Assert(!(pMemReqAux->GCPhysSlPt & X86_PAGE_4K_OFFSET_MASK));
2167
2168	/* Mask of valid paging entry bits. */
2169	static uint64_t const s_auPtEntityRsvd[] = { VTD_SL_PTE_VALID_MASK,
2170	VTD_SL_PDE_VALID_MASK,
2171	VTD_SL_PDPE_VALID_MASK,
2172	VTD_SL_PML4E_VALID_MASK,
2173	VTD_SL_PML5E_VALID_MASK };
2174
2175	/* Paranoia. */
2176	Assert(pMemReqAux->cPagingLevel >= 3 && pMemReqAux->cPagingLevel <= 5);
2177	AssertCompile(RT_ELEMENTS(s_auPtEntityRsvd) == 5);
2178
2179	/* Second-level translations restricts input address to an implementation-specific MGAW. */
2180	uint64_t const uAddrIn = pMemReqIn->AddrRange.uAddr;
2181	if (!(uAddrIn & pThis->fMgawInvMask))
2182	{ /* likely */ }
2183	else
2184	{
2185	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Xm_AddrIn_Invalid, pMemReqIn, pMemReqAux);
2186	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2187	}
2188
2189	/*
2190	* Traverse the I/O page table starting with the SLPTPTR (second-level page table pointer).
2191	* Unlike AMD IOMMU paging, here there is no feature for "skipping" levels.
2192	*/
2193	uint64_t uPtEntity = pMemReqAux->GCPhysSlPt;
2194	for (int8_t idxLevel = pMemReqAux->cPagingLevel - 1; idxLevel >= 0; idxLevel--)
2195	{
2196	/*
2197	* Read the paging entry for the current level.
2198	*/
2199	uint8_t const cLevelShift = X86_PAGE_4K_SHIFT + (idxLevel * 9);
2200	{
2201	uint16_t const idxPte = (uAddrIn >> cLevelShift) & UINT64_C(0x1ff);
2202	uint16_t const offPte = idxPte << 3;
2203	RTGCPHYS const GCPhysPtEntity = (uPtEntity & X86_PAGE_4K_BASE_MASK) \| offPte;
2204	int const rc = PDMDevHlpPhysReadMeta(pDevIns, GCPhysPtEntity, &uPtEntity, sizeof(uPtEntity));
2205	if (RT_SUCCESS(rc))
2206	{ /* likely */ }
2207	else
2208	{
2209	if ((GCPhysPtEntity & X86_PAGE_BASE_MASK) == pMemReqAux->GCPhysSlPt)
2210	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Xm_Slpptr_Read_Failed, pMemReqIn, pMemReqAux);
2211	else
2212	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Xm_Read_Pte_Failed, pMemReqIn, pMemReqAux);
2213	break;
2214	}
2215	}
2216
2217	/*
2218	* Check I/O permissions.
2219	* This must be done prior to check reserved bits for properly reporting errors SSL.2 and SSL.3.
2220	* See Intel spec. 7.1.3 "Fault conditions and Remapping hardware behavior for various request".
2221	*/
2222	uint8_t const fReqPerm = pMemReqIn->AddrRange.fPerm & pThis->fPermValidMask;
2223	uint8_t const fPtPerm = uPtEntity & pThis->fPermValidMask;
2224	Assert(!(fReqPerm & DMAR_PERM_EXE)); /* No Execute-requests support yet. */
2225	Assert(!(pThis->fExtCapReg & VTD_BF_ECAP_REG_SLADS_MASK)); /* No Second-level access/dirty support. */
2226	if ((fPtPerm & fReqPerm) == fReqPerm)
2227	{ /* likely */ }
2228	else
2229	{
2230	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Xm_Perm_Denied, pMemReqIn, pMemReqAux);
2231	break;
2232	}
2233
2234	/*
2235	* Validate reserved bits of the current paging entry.
2236	*/
2237	if (!(uPtEntity & ~s_auPtEntityRsvd[idxLevel]))
2238	{ /* likely */ }
2239	else
2240	{
2241	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Xm_Pte_Rsvd, pMemReqIn, pMemReqAux);
2242	break;
2243	}
2244
2245	/*
2246	* Check if this is a 1GB page or a 2MB page.
2247	*/
2248	AssertCompile(VTD_BF_SL_PDE_PS_MASK == VTD_BF_SL_PDPE_PS_MASK);
2249	uint8_t const fLargePage = RT_BF_GET(uPtEntity, VTD_BF_SL_PDE_PS);
2250	if (fLargePage && idxLevel > 0)
2251	{
2252	Assert(idxLevel == 1 \|\| idxLevel == 2); /* Is guaranteed by the reserved bits check above. */
2253	uint8_t const fSllpsMask = RT_BF_GET(pThis->fCapReg, VTD_BF_CAP_REG_SLLPS);
2254	if (fSllpsMask & RT_BIT(idxLevel - 1))
2255	{
2256	/*
2257	* We don't support MTS (asserted below), hence IPAT and EMT fields of the paging entity are ignored.
2258	* All other reserved bits are identical to the regular page-size paging entity which we've already
2259	* checked above.
2260	*/
2261	Assert(!(pThis->fExtCapReg & VTD_BF_ECAP_REG_MTS_MASK));
2262
2263	RTGCPHYS const GCPhysBase = uPtEntity & X86_GET_PAGE_BASE_MASK(cLevelShift);
2264	return dmarDrUpdateIoPageOut(pDevIns, GCPhysBase, cLevelShift, fPtPerm, pMemReqIn, pMemReqAux, pIoPageOut);
2265	}
2266
2267	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Xm_Pte_Sllps_Invalid, pMemReqIn, pMemReqAux);
2268	break;
2269	}
2270
2271	/*
2272	* If this is the final PTE, compute the translation address and we're done.
2273	*/
2274	if (idxLevel == 0)
2275	{
2276	RTGCPHYS const GCPhysBase = uPtEntity & X86_GET_PAGE_BASE_MASK(cLevelShift);
2277	return dmarDrUpdateIoPageOut(pDevIns, GCPhysBase, cLevelShift, fPtPerm, pMemReqIn, pMemReqAux, pIoPageOut);
2278	}
2279	}
2280
2281	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2282	}
2283
2284
2285	/**
2286	* Checks whether two consecutive I/O page results of a DMA memory request
2287	* translates to a physically contiguous region.
2288	*
2289	* @returns @c true if the I/O pages are contiguous, @c false otherwise.
2290	* @param pIoPagePrev The previous I/O page.
2291	* @param pIoPage The current I/O page.
2292	*/
2293	static bool dmarIsIoPageAccessContig(PCDMARIOPAGE pIoPagePrev, PCDMARIOPAGE pIoPage)
2294	{
2295	/* Paranoia: Permissions for pages of a DMA memory request must be identical. */
2296	Assert(pIoPagePrev->fPerm == pIoPage->fPerm);
2297
2298	size_t const cbPrev = RT_BIT_64(pIoPagePrev->cShift);
2299	RTGCPHYS const GCPhysPrev = pIoPagePrev->GCPhysBase;
2300	RTGCPHYS const GCPhys = pIoPage->GCPhysBase;
2301	#ifdef RT_STRICT
2302	/* Paranoia: Ensure offset bits are 0. */
2303	{
2304	uint64_t const fOffMaskPrev = X86_GET_PAGE_OFFSET_MASK(pIoPagePrev->cShift);
2305	uint64_t const fOffMask = X86_GET_PAGE_OFFSET_MASK(pIoPage->cShift);
2306	Assert(!(GCPhysPrev & fOffMaskPrev));
2307	Assert(!(GCPhys & fOffMask));
2308	}
2309	#endif
2310	return GCPhysPrev + cbPrev == GCPhys;
2311	}
2312
2313
2314	/**
2315	* Looks up the range of addresses for a DMA memory request remapping.
2316	*
2317	* @returns VBox status code.
2318	* @param pDevIns The IOMMU device instance.
2319	* @param pfnLookup The DMA address lookup function.
2320	* @param pMemReqRemap The DMA memory request remapping info.
2321	*/
2322	static int dmarDrMemRangeLookup(PPDMDEVINS pDevIns, PFNDMADDRLOOKUP pfnLookup, PDMARMEMREQREMAP pMemReqRemap)
2323	{
2324	AssertPtr(pfnLookup);
2325
2326	RTGCPHYS GCPhysAddr = NIL_RTGCPHYS;
2327	DMARMEMREQIN MemReqIn = pMemReqRemap->In;
2328	uint64_t const uAddrIn = MemReqIn.AddrRange.uAddr;
2329	size_t const cbAddrIn = MemReqIn.AddrRange.cb;
2330	uint64_t uAddrInBase = MemReqIn.AddrRange.uAddr & X86_PAGE_4K_BASE_MASK;
2331	uint64_t offAddrIn = MemReqIn.AddrRange.uAddr & X86_PAGE_4K_OFFSET_MASK;
2332	size_t cbRemaining = cbAddrIn;
2333
2334	int rc;
2335	DMARIOPAGE IoPagePrev;
2336	RT_ZERO(IoPagePrev);
2337	for (;;)
2338	{
2339	/* Update the input memory request with the next address in our range that needs translation. */
2340	MemReqIn.AddrRange.uAddr = uAddrInBase;
2341	MemReqIn.AddrRange.cb = cbRemaining; /* Not currently accessed by pfnLookup, but keep things consistent. */
2342
2343	DMARIOPAGE IoPage;
2344	rc = pfnLookup(pDevIns, &MemReqIn, &pMemReqRemap->Aux, &IoPage);
2345	if (RT_SUCCESS(rc))
2346	{
2347	Assert(IoPage.cShift >= X86_PAGE_4K_SHIFT && IoPage.cShift <= X86_PAGE_1G_SHIFT);
2348
2349	/* Store the translated address before continuing to access more pages. */
2350	if (cbRemaining == cbAddrIn)
2351	{
2352	uint64_t const fOffMask = X86_GET_PAGE_OFFSET_MASK(IoPage.cShift);
2353	uint64_t const offAddrOut = uAddrIn & fOffMask;
2354	Assert(!(IoPage.GCPhysBase & fOffMask));
2355	GCPhysAddr = IoPage.GCPhysBase \| offAddrOut;
2356	}
2357	/* Check if addresses translated so far result in a physically contiguous region. */
2358	else if (!dmarIsIoPageAccessContig(&IoPagePrev, &IoPage))
2359	{
2360	rc = VERR_OUT_OF_RANGE;
2361	break;
2362	}
2363
2364	/* Store the I/O page lookup from the first/previous access. */
2365	IoPagePrev = IoPage;
2366
2367	/* Check if we need to access more pages. */
2368	size_t const cbPage = RT_BIT_64(IoPage.cShift);
2369	if (cbRemaining > cbPage - offAddrIn)
2370	{
2371	cbRemaining -= (cbPage - offAddrIn); /* Calculate how much more we need to access. */
2372	uAddrInBase += cbPage; /* Update address of the next access. */
2373	offAddrIn = 0; /* After first page, all pages are accessed from offset 0. */
2374	}
2375	else
2376	{
2377	/* Caller (PDM) doesn't expect more data accessed than what was requested. */
2378	cbRemaining = 0;
2379	break;
2380	}
2381	}
2382	else
2383	break;
2384	}
2385
2386	pMemReqRemap->Out.AddrRange.uAddr = GCPhysAddr;
2387	pMemReqRemap->Out.AddrRange.cb = cbAddrIn - cbRemaining;
2388	pMemReqRemap->Out.AddrRange.fPerm = IoPagePrev.fPerm;
2389	return rc;
2390	}
2391
2392
2393	/**
2394	* Handles legacy mode DMA address remapping.
2395	*
2396	* @returns VBox status code.
2397	* @param pDevIns The IOMMU device instance.
2398	* @param uRtaddrReg The current RTADDR_REG value.
2399	* @param pMemReqRemap The DMA memory request remapping info.
2400	*/
2401	static int dmarDrLegacyModeRemapAddr(PPDMDEVINS pDevIns, uint64_t uRtaddrReg, PDMARMEMREQREMAP pMemReqRemap)
2402	{
2403	PCDMARMEMREQIN pMemReqIn = &pMemReqRemap->In;
2404	PDMARMEMREQAUX pMemReqAux = &pMemReqRemap->Aux;
2405	PDMARMEMREQOUT pMemReqOut = &pMemReqRemap->Out;
2406	Assert(pMemReqAux->fTtm == VTD_TTM_LEGACY_MODE); /* Paranoia. */
2407
2408	/* Read the root-entry from guest memory. */
2409	uint8_t const idxRootEntry = RT_HI_U8(pMemReqIn->idDevice);
2410	VTD_ROOT_ENTRY_T RootEntry;
2411	int rc = dmarDrReadRootEntry(pDevIns, uRtaddrReg, idxRootEntry, &RootEntry);
2412	if (RT_SUCCESS(rc))
2413	{
2414	/* Check if the root entry is present (must be done before validating reserved bits). */
2415	uint64_t const uRootEntryQword0 = RootEntry.au64[0];
2416	uint64_t const uRootEntryQword1 = RootEntry.au64[1];
2417	bool const fRootEntryPresent = RT_BF_GET(uRootEntryQword0, VTD_BF_0_ROOT_ENTRY_P);
2418	if (fRootEntryPresent)
2419	{
2420	/* Validate reserved bits in the root entry. */
2421	if ( !(uRootEntryQword0 & ~VTD_ROOT_ENTRY_0_VALID_MASK)
2422	&& !(uRootEntryQword1 & ~VTD_ROOT_ENTRY_1_VALID_MASK))
2423	{
2424	/* Read the context-entry from guest memory. */
2425	RTGCPHYS const GCPhysCtxTable = uRootEntryQword0 & VTD_BF_0_ROOT_ENTRY_CTP_MASK;
2426	uint8_t const idxCtxEntry = RT_LO_U8(pMemReqIn->idDevice);
2427	VTD_CONTEXT_ENTRY_T CtxEntry;
2428	rc = dmarDrReadCtxEntry(pDevIns, GCPhysCtxTable, idxCtxEntry, &CtxEntry);
2429	if (RT_SUCCESS(rc))
2430	{
2431	uint64_t const uCtxEntryQword0 = CtxEntry.au64[0];
2432	uint64_t const uCtxEntryQword1 = CtxEntry.au64[1];
2433
2434	/* Note the FPD bit which software can use to supress translation faults from here on in. */
2435	pMemReqAux->fFpd = RT_BF_GET(uCtxEntryQword0, VTD_BF_0_CONTEXT_ENTRY_FPD);
2436
2437	/* Check if the context-entry is present (must be done before validating reserved bits). */
2438	bool const fCtxEntryPresent = RT_BF_GET(uCtxEntryQword0, VTD_BF_0_CONTEXT_ENTRY_P);
2439	if (fCtxEntryPresent)
2440	{
2441	/* Validate reserved bits in the context-entry. */
2442	if ( !(uCtxEntryQword0 & ~VTD_CONTEXT_ENTRY_0_VALID_MASK)
2443	&& !(uCtxEntryQword1 & ~VTD_CONTEXT_ENTRY_1_VALID_MASK))
2444	{
2445	/* Get the domain ID for this mapping. */
2446	pMemReqOut->idDomain = RT_BF_GET(uCtxEntryQword1, VTD_BF_1_CONTEXT_ENTRY_DID);
2447
2448	/* Validate the translation type (TT). */
2449	PCDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PCDMAR);
2450	uint8_t const fTt = RT_BF_GET(uCtxEntryQword0, VTD_BF_0_CONTEXT_ENTRY_TT);
2451	switch (fTt)
2452	{
2453	case VTD_TT_UNTRANSLATED_SLP:
2454	{
2455	/*
2456	* Untranslated requests are translated using second-level paging structures referenced
2457	* through SLPTPTR. Translated requests and Translation Requests are blocked.
2458	*/
2459	if (pMemReqIn->enmAddrType == PCIADDRTYPE_UNTRANSLATED)
2460	{
2461	/* Validate the address width and get the paging level. */
2462	uint8_t cPagingLevel;
2463	if (dmarDrLegacyModeIsAwValid(pThis, &CtxEntry, &cPagingLevel))
2464	{
2465	/*
2466	* The second-level page table is located at the physical address specified
2467	* in the context entry with which we can finally perform second-level translation.
2468	*/
2469	pMemReqAux->cPagingLevel = cPagingLevel;
2470	pMemReqAux->GCPhysSlPt = uCtxEntryQword0 & VTD_BF_0_CONTEXT_ENTRY_SLPTPTR_MASK;
2471	return dmarDrMemRangeLookup(pDevIns, dmarDrSecondLevelTranslate, pMemReqRemap);
2472	}
2473	else
2474	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Lm_Ut_Aw_Invalid, pMemReqIn, pMemReqAux);
2475	}
2476	else
2477	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Lm_Ut_At_Block, pMemReqIn, pMemReqAux);
2478	break;
2479	}
2480
2481	case VTD_TT_UNTRANSLATED_PT:
2482	{
2483	/*
2484	* Untranslated requests are processed as pass-through (PT) if PT is supported.
2485	* Translated and translation requests are blocked. If PT isn't supported this TT value
2486	* is reserved which I assume raises a fault (hence fallthru below).
2487	*/
2488	if (pThis->fExtCapReg & VTD_BF_ECAP_REG_PT_MASK)
2489	{
2490	if (pMemReqRemap->In.enmAddrType == PCIADDRTYPE_UNTRANSLATED)
2491	{
2492	if (dmarDrLegacyModeIsAwValid(pThis, &CtxEntry, NULL /* pcPagingLevel */))
2493	{
2494	PDMARMEMREQOUT pOut = &pMemReqRemap->Out;
2495	PCDMARMEMREQIN pIn = &pMemReqRemap->In;
2496	pOut->AddrRange.uAddr = pIn->AddrRange.uAddr & X86_PAGE_4K_BASE_MASK;
2497	pOut->AddrRange.cb = pIn->AddrRange.cb;
2498	pOut->AddrRange.fPerm = DMAR_PERM_ALL;
2499	return VINF_SUCCESS;
2500	}
2501	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Lm_Pt_Aw_Invalid, pMemReqIn, pMemReqAux);
2502	}
2503	else
2504	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Lm_Pt_At_Block, pMemReqIn, pMemReqAux);
2505	break;
2506	}
2507	RT_FALL_THRU();
2508	}
2509
2510	case VTD_TT_UNTRANSLATED_DEV_TLB:
2511	{
2512	/*
2513	* Untranslated, translated and translation requests are supported but requires
2514	* device-TLB support. We don't support device-TLBs, so it's treated as reserved.
2515	*/
2516	Assert(!(pThis->fExtCapReg & VTD_BF_ECAP_REG_DT_MASK));
2517	RT_FALL_THRU();
2518	}
2519
2520	default:
2521	{
2522	/* Any other TT value is reserved. */
2523	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Lm_Tt_Invalid, pMemReqIn, pMemReqAux);
2524	break;
2525	}
2526	}
2527	}
2528	else
2529	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Lm_CtxEntry_Rsvd, pMemReqIn, pMemReqAux);
2530	}
2531	else
2532	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Lm_CtxEntry_Not_Present, pMemReqIn, pMemReqAux);
2533	}
2534	else
2535	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Lm_CtxEntry_Read_Failed, pMemReqIn, pMemReqAux);
2536	}
2537	else
2538	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Lm_RootEntry_Rsvd, pMemReqIn, pMemReqAux);
2539	}
2540	else
2541	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Lm_RootEntry_Not_Present, pMemReqIn, pMemReqAux);
2542	}
2543	else
2544	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Lm_RootEntry_Read_Failed, pMemReqIn, pMemReqAux);
2545	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2546	}
2547
2548
2549	/**
2550	* Handles remapping of DMA address requests in scalable mode.
2551	*
2552	* @returns VBox status code.
2553	* @param pDevIns The IOMMU device instance.
2554	* @param uRtaddrReg The current RTADDR_REG value.
2555	* @param pMemReqRemap The DMA memory request remapping info.
2556	*/
2557	static int dmarDrScalableModeRemapAddr(PPDMDEVINS pDevIns, uint64_t uRtaddrReg, PDMARMEMREQREMAP pMemReqRemap)
2558	{
2559	RT_NOREF2(uRtaddrReg, pMemReqRemap);
2560	PCDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
2561	Assert(pThis->fExtCapReg & VTD_BF_ECAP_REG_SMTS_MASK);
2562	return VERR_NOT_IMPLEMENTED;
2563	}
2564
2565
2566	/**
2567	* Gets the DMA access permissions and the address-translation request
2568	* type given the PDM IOMMU memory access flags.
2569	*
2570	* @param pDevIns The IOMMU device instance.
2571	* @param fFlags The access flags, see PDMIOMMU_MEM_F_XXX.
2572	* @param fBulk Whether this is a bulk memory access (used for
2573	* statistics).
2574	* @param penmReqType Where to store the address-translation request type.
2575	* @param pfReqPerm Where to store the DMA access permissions.
2576	*/
2577	static void dmarDrGetPermAndReqType(PPDMDEVINS pDevIns, uint32_t fFlags, bool fBulk, PVTDREQTYPE penmReqType, uint8_t *pfReqPerm)
2578	{
2579	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
2580	if (fFlags & PDMIOMMU_MEM_F_READ)
2581	{
2582	*penmReqType = VTDREQTYPE_READ;
2583	*pfReqPerm = DMAR_PERM_READ;
2584	#ifdef VBOX_WITH_STATISTICS
2585	if (!fBulk)
2586	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMemRead));
2587	else
2588	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMemBulkRead));
2589	#else
2590	RT_NOREF2(pThis, fBulk);
2591	#endif
2592	}
2593	else
2594	{
2595	*penmReqType = VTDREQTYPE_WRITE;
2596	*pfReqPerm = DMAR_PERM_WRITE;
2597	#ifdef VBOX_WITH_STATISTICS
2598	if (!fBulk)
2599	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMemWrite));
2600	else
2601	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMemBulkWrite));
2602	#else
2603	RT_NOREF2(pThis, fBulk);
2604	#endif
2605	}
2606	}
2607
2608
2609	/**
2610	* Handles DMA remapping based on the table translation mode (TTM).
2611	*
2612	* @returns VBox status code.
2613	* @param pDevIns The IOMMU device instance.
2614	* @param uRtaddrReg The current RTADDR_REG value.
2615	* @param pMemReqRemap The DMA memory request remapping info.
2616	*/
2617	static int dmarDrMemReqRemap(PPDMDEVINS pDevIns, uint64_t uRtaddrReg, PDMARMEMREQREMAP pMemReqRemap)
2618	{
2619	int rc;
2620	switch (pMemReqRemap->Aux.fTtm)
2621	{
2622	case VTD_TTM_LEGACY_MODE:
2623	{
2624	rc = dmarDrLegacyModeRemapAddr(pDevIns, uRtaddrReg, pMemReqRemap);
2625	break;
2626	}
2627
2628	case VTD_TTM_SCALABLE_MODE:
2629	{
2630	PCDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PCDMAR);
2631	if (pThis->fExtCapReg & VTD_BF_ECAP_REG_SMTS_MASK)
2632	rc = dmarDrScalableModeRemapAddr(pDevIns, uRtaddrReg, pMemReqRemap);
2633	else
2634	{
2635	rc = VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2636	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Rta_Smts_Not_Supported, &pMemReqRemap->In, &pMemReqRemap->Aux);
2637	}
2638	break;
2639	}
2640
2641	case VTD_TTM_ABORT_DMA_MODE:
2642	{
2643	PCDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PCDMAR);
2644	if (pThis->fExtCapReg & VTD_BF_ECAP_REG_ADMS_MASK)
2645	dmarDrTargetAbort(pDevIns);
2646	else
2647	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Rta_Adms_Not_Supported, &pMemReqRemap->In, &pMemReqRemap->Aux);
2648	rc = VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2649	break;
2650	}
2651
2652	default:
2653	{
2654	rc = VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2655	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Rta_Rsvd, &pMemReqRemap->In, &pMemReqRemap->Aux);
2656	break;
2657	}
2658	}
2659	return rc;
2660	}
2661
2662
2663	/**
2664	* Memory access bulk (one or more 4K pages) request from a device.
2665	*
2666	* @returns VBox status code.
2667	* @param pDevIns The IOMMU device instance.
2668	* @param idDevice The device ID (bus, device, function).
2669	* @param cIovas The number of addresses being accessed.
2670	* @param pauIovas The I/O virtual addresses for each page being accessed.
2671	* @param fFlags The access flags, see PDMIOMMU_MEM_F_XXX.
2672	* @param paGCPhysSpa Where to store the translated physical addresses.
2673	*
2674	* @thread Any.
2675	*/
2676	static DECLCALLBACK(int) iommuIntelMemBulkAccess(PPDMDEVINS pDevIns, uint16_t idDevice, size_t cIovas, uint64_t const *pauIovas,
2677	uint32_t fFlags, PRTGCPHYS paGCPhysSpa)
2678	{
2679	/* Validate. */
2680	AssertPtr(pDevIns);
2681	Assert(cIovas > 0);
2682	AssertPtr(pauIovas);
2683	AssertPtr(paGCPhysSpa);
2684	Assert(!(fFlags & ~PDMIOMMU_MEM_F_VALID_MASK));
2685
2686	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
2687	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
2688
2689	DMAR_LOCK(pDevIns, pThisCC);
2690	uint32_t const uGstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GSTS_REG);
2691	uint64_t const uRtaddrReg = pThis->uRtaddrReg;
2692	DMAR_UNLOCK(pDevIns, pThisCC);
2693
2694	if (uGstsReg & VTD_BF_GSTS_REG_TES_MASK)
2695	{
2696	VTDREQTYPE enmReqType;
2697	uint8_t fReqPerm;
2698	dmarDrGetPermAndReqType(pDevIns, fFlags, true /* fBulk */, &enmReqType, &fReqPerm);
2699
2700	DMARMEMREQREMAP MemReqRemap;
2701	RT_ZERO(MemReqRemap);
2702	MemReqRemap.In.AddrRange.cb = X86_PAGE_SIZE;
2703	MemReqRemap.In.AddrRange.fPerm = fReqPerm;
2704	MemReqRemap.In.idDevice = idDevice;
2705	MemReqRemap.In.Pasid = NIL_PCIPASID;
2706	MemReqRemap.In.enmAddrType = PCIADDRTYPE_UNTRANSLATED;
2707	MemReqRemap.In.enmReqType = enmReqType;
2708	MemReqRemap.Aux.fTtm = RT_BF_GET(uRtaddrReg, VTD_BF_RTADDR_REG_TTM);
2709	MemReqRemap.Out.AddrRange.uAddr = NIL_RTGCPHYS;
2710
2711	for (size_t i = 0; i < cIovas; i++)
2712	{
2713	MemReqRemap.In.AddrRange.uAddr = pauIovas[i] & X86_PAGE_BASE_MASK;
2714	int const rc = dmarDrMemReqRemap(pDevIns, uRtaddrReg, &MemReqRemap);
2715	if (RT_SUCCESS(rc))
2716	{
2717	paGCPhysSpa[i] = MemReqRemap.Out.AddrRange.uAddr \| (pauIovas[i] & X86_PAGE_OFFSET_MASK);
2718	Assert(MemReqRemap.Out.AddrRange.cb == MemReqRemap.In.AddrRange.cb);
2719	}
2720	else
2721	{
2722	LogFlowFunc(("idDevice=%#x uIova=%#RX64 fPerm=%#x rc=%Rrc\n", idDevice, pauIovas[i], fReqPerm, rc));
2723	return rc;
2724	}
2725	}
2726	}
2727	else
2728	{
2729	/* Addresses are forwarded without translation when the translation is disabled. */
2730	for (size_t i = 0; i < cIovas; i++)
2731	paGCPhysSpa[i] = pauIovas[i];
2732	}
2733
2734	return VINF_SUCCESS;
2735	}
2736
2737
2738	/**
2739	* Memory access transaction from a device.
2740	*
2741	* @returns VBox status code.
2742	* @param pDevIns The IOMMU device instance.
2743	* @param idDevice The device ID (bus, device, function).
2744	* @param uIova The I/O virtual address being accessed.
2745	* @param cbIova The size of the access.
2746	* @param fFlags The access flags, see PDMIOMMU_MEM_F_XXX.
2747	* @param pGCPhysSpa Where to store the translated system physical address.
2748	* @param pcbContiguous Where to store the number of contiguous bytes translated
2749	* and permission-checked.
2750	*
2751	* @thread Any.
2752	*/
2753	static DECLCALLBACK(int) iommuIntelMemAccess(PPDMDEVINS pDevIns, uint16_t idDevice, uint64_t uIova, size_t cbIova,
2754	uint32_t fFlags, PRTGCPHYS pGCPhysSpa, size_t *pcbContiguous)
2755	{
2756	/* Validate. */
2757	AssertPtr(pDevIns);
2758	AssertPtr(pGCPhysSpa);
2759	AssertPtr(pcbContiguous);
2760	Assert(cbIova > 0); /** @todo Are we going to support ZLR (zero-length reads to write-only pages)? */
2761	Assert(!(fFlags & ~PDMIOMMU_MEM_F_VALID_MASK));
2762
2763	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
2764	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
2765
2766	DMAR_LOCK(pDevIns, pThisCC);
2767	uint32_t const uGstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GSTS_REG);
2768	uint64_t const uRtaddrReg = pThis->uRtaddrReg;
2769	DMAR_UNLOCK(pDevIns, pThisCC);
2770
2771	if (uGstsReg & VTD_BF_GSTS_REG_TES_MASK)
2772	{
2773	VTDREQTYPE enmReqType;
2774	uint8_t fReqPerm;
2775	dmarDrGetPermAndReqType(pDevIns, fFlags, false /* fBulk */, &enmReqType, &fReqPerm);
2776
2777	DMARMEMREQREMAP MemReqRemap;
2778	RT_ZERO(MemReqRemap);
2779	MemReqRemap.In.AddrRange.uAddr = uIova;
2780	MemReqRemap.In.AddrRange.cb = cbIova;
2781	MemReqRemap.In.AddrRange.fPerm = fReqPerm;
2782	MemReqRemap.In.idDevice = idDevice;
2783	MemReqRemap.In.Pasid = NIL_PCIPASID;
2784	MemReqRemap.In.enmAddrType = PCIADDRTYPE_UNTRANSLATED;
2785	MemReqRemap.In.enmReqType = enmReqType;
2786	MemReqRemap.Aux.fTtm = RT_BF_GET(uRtaddrReg, VTD_BF_RTADDR_REG_TTM);
2787	MemReqRemap.Out.AddrRange.uAddr = NIL_RTGCPHYS;
2788
2789	int const rc = dmarDrMemReqRemap(pDevIns, uRtaddrReg, &MemReqRemap);
2790	*pGCPhysSpa = MemReqRemap.Out.AddrRange.uAddr;
2791	*pcbContiguous = MemReqRemap.Out.AddrRange.cb;
2792	return rc;
2793	}
2794
2795	*pGCPhysSpa = uIova;
2796	*pcbContiguous = cbIova;
2797	return VINF_SUCCESS;
2798	}
2799
2800
2801	/**
2802	* Reads an IRTE from guest memory.
2803	*
2804	* @returns VBox status code.
2805	* @param pDevIns The IOMMU device instance.
2806	* @param uIrtaReg The IRTA_REG.
2807	* @param idxIntr The interrupt index.
2808	* @param pIrte Where to store the read IRTE.
2809	*/
2810	static int dmarIrReadIrte(PPDMDEVINS pDevIns, uint64_t uIrtaReg, uint16_t idxIntr, PVTD_IRTE_T pIrte)
2811	{
2812	Assert(idxIntr < VTD_IRTA_REG_GET_ENTRY_COUNT(uIrtaReg));
2813
2814	size_t const cbIrte = sizeof(*pIrte);
2815	RTGCPHYS const GCPhysIrte = (uIrtaReg & VTD_BF_IRTA_REG_IRTA_MASK) + (idxIntr * cbIrte);
2816	return PDMDevHlpPhysReadMeta(pDevIns, GCPhysIrte, pIrte, cbIrte);
2817	}
2818
2819
2820	/**
2821	* Remaps the source MSI to the destination MSI given the IRTE.
2822	*
2823	* @param fExtIntrMode Whether extended interrupt mode is enabled (i.e
2824	* IRTA_REG.EIME).
2825	* @param pIrte The IRTE used for the remapping.
2826	* @param pMsiIn The source MSI (currently unused).
2827	* @param pMsiOut Where to store the remapped MSI.
2828	*/
2829	static void dmarIrRemapFromIrte(bool fExtIntrMode, PCVTD_IRTE_T pIrte, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
2830	{
2831	NOREF(pMsiIn);
2832	uint64_t const uIrteQword0 = pIrte->au64[0];
2833
2834	/*
2835	* Let's start with a clean slate and preserve unspecified bits if the need arises.
2836	* For instance, address bits 1:0 is supposed to be "ignored" by remapping hardware,
2837	* but it's not clear if hardware zeroes out these bits in the remapped MSI or if
2838	* it copies it from the source MSI.
2839	*/
2840	RT_ZERO(*pMsiOut);
2841	pMsiOut->Addr.n.u1DestMode = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_DM);
2842	pMsiOut->Addr.n.u1RedirHint = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_RH);
2843	pMsiOut->Addr.n.u12Addr = VBOX_MSI_ADDR_BASE >> VBOX_MSI_ADDR_SHIFT;
2844	if (fExtIntrMode)
2845	{
2846	/*
2847	* Apparently the DMAR stuffs the high 24-bits of the destination ID into the
2848	* high 24-bits of the upper 32-bits of the message address, see @bugref{9967#c22}.
2849	*/
2850	uint32_t const idDest = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_DST);
2851	pMsiOut->Addr.n.u8DestId = idDest;
2852	pMsiOut->Addr.n.u32Rsvd0 = idDest & UINT32_C(0xffffff00);
2853	}
2854	else
2855	pMsiOut->Addr.n.u8DestId = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_DST_XAPIC);
2856
2857	pMsiOut->Data.n.u8Vector = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_V);
2858	pMsiOut->Data.n.u3DeliveryMode = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_DLM);
2859	pMsiOut->Data.n.u1Level = 1;
2860	pMsiOut->Data.n.u1TriggerMode = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_TM);
2861	}
2862
2863
2864	/**
2865	* Handles remapping of interrupts in remappable interrupt format.
2866	*
2867	* @returns VBox status code.
2868	* @param pDevIns The IOMMU device instance.
2869	* @param uIrtaReg The IRTA_REG.
2870	* @param idDevice The device ID (bus, device, function).
2871	* @param pMsiIn The source MSI.
2872	* @param pMsiOut Where to store the remapped MSI.
2873	*/
2874	static int dmarIrRemapIntr(PPDMDEVINS pDevIns, uint64_t uIrtaReg, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
2875	{
2876	Assert(pMsiIn->Addr.dmar_remap.fIntrFormat == VTD_INTR_FORMAT_REMAPPABLE);
2877
2878	/* Validate reserved bits in the interrupt request. */
2879	AssertCompile(VTD_REMAPPABLE_MSI_ADDR_VALID_MASK == UINT32_MAX);
2880	if (!(pMsiIn->Data.u32 & ~VTD_REMAPPABLE_MSI_DATA_VALID_MASK))
2881	{
2882	/* Compute the index into the interrupt remap table. */
2883	uint16_t const uHandleHi = RT_BF_GET(pMsiIn->Addr.au32[0], VTD_BF_REMAPPABLE_MSI_ADDR_HANDLE_HI);
2884	uint16_t const uHandleLo = RT_BF_GET(pMsiIn->Addr.au32[0], VTD_BF_REMAPPABLE_MSI_ADDR_HANDLE_LO);
2885	uint16_t const uHandle = uHandleLo \| (uHandleHi << 15);
2886	bool const fSubHandleValid = RT_BF_GET(pMsiIn->Addr.au32[0], VTD_BF_REMAPPABLE_MSI_ADDR_SHV);
2887	uint16_t const idxIntr = fSubHandleValid
2888	? uHandle + RT_BF_GET(pMsiIn->Data.u32, VTD_BF_REMAPPABLE_MSI_DATA_SUBHANDLE)
2889	: uHandle;
2890
2891	/* Validate the index. */
2892	uint32_t const cEntries = VTD_IRTA_REG_GET_ENTRY_COUNT(uIrtaReg);
2893	if (idxIntr < cEntries)
2894	{
2895	/** @todo Implement and read IRTE from interrupt-entry cache here. */
2896
2897	/* Read the interrupt remap table entry (IRTE) at the index. */
2898	VTD_IRTE_T Irte;
2899	int rc = dmarIrReadIrte(pDevIns, uIrtaReg, idxIntr, &Irte);
2900	if (RT_SUCCESS(rc))
2901	{
2902	/* Check if the IRTE is present (this must be done -before- checking reserved bits). */
2903	uint64_t const uIrteQword0 = Irte.au64[0];
2904	uint64_t const uIrteQword1 = Irte.au64[1];
2905	bool const fPresent = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_P);
2906	if (fPresent)
2907	{
2908	/* Validate reserved bits in the IRTE. */
2909	bool const fExtIntrMode = RT_BF_GET(uIrtaReg, VTD_BF_IRTA_REG_EIME);
2910	uint64_t const fQw0ValidMask = fExtIntrMode ? VTD_IRTE_0_X2APIC_VALID_MASK : VTD_IRTE_0_XAPIC_VALID_MASK;
2911	if ( !(uIrteQword0 & ~fQw0ValidMask)
2912	&& !(uIrteQword1 & ~VTD_IRTE_1_VALID_MASK))
2913	{
2914	/* Validate requester id (the device ID) as configured in the IRTE. */
2915	bool fSrcValid;
2916	DMARDIAG enmIrDiag;
2917	uint8_t const fSvt = RT_BF_GET(uIrteQword1, VTD_BF_1_IRTE_SVT);
2918	switch (fSvt)
2919	{
2920	case VTD_IRTE_SVT_NONE:
2921	{
2922	fSrcValid = true;
2923	enmIrDiag = kDmarDiag_None;
2924	break;
2925	}
2926
2927	case VTD_IRTE_SVT_VALIDATE_MASK:
2928	{
2929	static uint16_t const s_afValidMasks[] = { 0xffff, 0xfffb, 0xfff9, 0xfff8 };
2930	uint8_t const idxMask = RT_BF_GET(uIrteQword1, VTD_BF_1_IRTE_SQ) & 3;
2931	uint16_t const fValidMask = s_afValidMasks[idxMask];
2932	uint16_t const idSource = RT_BF_GET(uIrteQword1, VTD_BF_1_IRTE_SID);
2933	fSrcValid = (idDevice & fValidMask) == (idSource & fValidMask);
2934	enmIrDiag = kDmarDiag_Ir_Rfi_Irte_Svt_Masked;
2935	break;
2936	}
2937
2938	case VTD_IRTE_SVT_VALIDATE_BUS_RANGE:
2939	{
2940	uint16_t const idSource = RT_BF_GET(uIrteQword1, VTD_BF_1_IRTE_SID);
2941	uint8_t const uBusFirst = RT_HI_U8(idSource);
2942	uint8_t const uBusLast = RT_LO_U8(idSource);
2943	uint8_t const idDeviceBus = idDevice >> VBOX_PCI_BUS_SHIFT;
2944	fSrcValid = (idDeviceBus >= uBusFirst && idDeviceBus <= uBusLast);
2945	enmIrDiag = kDmarDiag_Ir_Rfi_Irte_Svt_Bus;
2946	break;
2947	}
2948
2949	default:
2950	{
2951	fSrcValid = false;
2952	enmIrDiag = kDmarDiag_Ir_Rfi_Irte_Svt_Rsvd;
2953	break;
2954	}
2955	}
2956
2957	if (fSrcValid)
2958	{
2959	uint8_t const fPostedMode = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_IM);
2960	if (!fPostedMode)
2961	{
2962	dmarIrRemapFromIrte(fExtIntrMode, &Irte, pMsiIn, pMsiOut);
2963	return VINF_SUCCESS;
2964	}
2965	dmarIrFaultRecord(pDevIns, kDmarDiag_Ir_Rfi_Irte_Mode_Invalid, idDevice, idxIntr, &Irte);
2966	}
2967	else
2968	dmarIrFaultRecord(pDevIns, enmIrDiag, idDevice, idxIntr, &Irte);
2969	}
2970	else
2971	dmarIrFaultRecord(pDevIns, kDmarDiag_Ir_Rfi_Irte_Rsvd, idDevice, idxIntr, &Irte);
2972	}
2973	else
2974	dmarIrFaultRecord(pDevIns, kDmarDiag_Ir_Rfi_Irte_Not_Present, idDevice, idxIntr, &Irte);
2975	}
2976	else
2977	dmarIrFaultRecord(pDevIns, kDmarDiag_Ir_Rfi_Irte_Read_Failed, idDevice, idxIntr, NULL /* pIrte */);
2978	}
2979	else
2980	dmarIrFaultRecord(pDevIns, kDmarDiag_Ir_Rfi_Intr_Index_Invalid, idDevice, idxIntr, NULL /* pIrte */);
2981	}
2982	else
2983	dmarIrFaultRecord(pDevIns, kDmarDiag_Ir_Rfi_Rsvd, idDevice, 0 /* idxIntr /, NULL / pIrte */);
2984	return VERR_IOMMU_INTR_REMAP_DENIED;
2985	}
2986
2987
2988	/**
2989	* Interrupt remap request from a device.
2990	*
2991	* @returns VBox status code.
2992	* @param pDevIns The IOMMU device instance.
2993	* @param idDevice The device ID (bus, device, function).
2994	* @param pMsiIn The source MSI.
2995	* @param pMsiOut Where to store the remapped MSI.
2996	*/
2997	static DECLCALLBACK(int) iommuIntelMsiRemap(PPDMDEVINS pDevIns, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
2998	{
2999	/* Validate. */
3000	Assert(pDevIns);
3001	Assert(pMsiIn);
3002	Assert(pMsiOut);
3003	RT_NOREF1(idDevice);
3004
3005	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
3006	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
3007
3008	/* Lock and read all registers required for interrupt remapping up-front. */
3009	DMAR_LOCK(pDevIns, pThisCC);
3010	uint32_t const uGstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GSTS_REG);
3011	uint64_t const uIrtaReg = pThis->uIrtaReg;
3012	DMAR_UNLOCK(pDevIns, pThisCC);
3013
3014	/* Check if interrupt remapping is enabled. */
3015	if (uGstsReg & VTD_BF_GSTS_REG_IRES_MASK)
3016	{
3017	bool const fIsRemappable = RT_BF_GET(pMsiIn->Addr.au32[0], VTD_BF_REMAPPABLE_MSI_ADDR_INTR_FMT);
3018	if (!fIsRemappable)
3019	{
3020	/* Handle compatibility format interrupts. */
3021	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMsiRemapCfi));
3022
3023	/* If EIME is enabled or CFIs are disabled, block the interrupt. */
3024	if ( (uIrtaReg & VTD_BF_IRTA_REG_EIME_MASK)
3025	\|\| !(uGstsReg & VTD_BF_GSTS_REG_CFIS_MASK))
3026	{
3027	dmarIrFaultRecord(pDevIns, kDmarDiag_Ir_Cfi_Blocked, VTDIRFAULT_CFI_BLOCKED, idDevice, 0 /* idxIntr */);
3028	return VERR_IOMMU_INTR_REMAP_DENIED;
3029	}
3030
3031	/* Interrupt isn't subject to remapping, pass-through the interrupt. */
3032	pMsiOut = pMsiIn;
3033	return VINF_SUCCESS;
3034	}
3035
3036	/* Handle remappable format interrupts. */
3037	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMsiRemapRfi));
3038	return dmarIrRemapIntr(pDevIns, uIrtaReg, idDevice, pMsiIn, pMsiOut);
3039	}
3040
3041	/* Interrupt-remapping isn't enabled, all interrupts are pass-through. */
3042	pMsiOut = pMsiIn;
3043	return VINF_SUCCESS;
3044	}
3045
3046
3047	/**
3048	* @callback_method_impl{FNIOMMMIONEWWRITE}
3049	*/
3050	static DECLCALLBACK(VBOXSTRICTRC) dmarMmioWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS off, void const pv, unsigned cb)
3051	{
3052	RT_NOREF1(pvUser);
3053	DMAR_ASSERT_MMIO_ACCESS_RET(off, cb);
3054
3055	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
3056	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioWrite));
3057
3058	uint16_t const offReg = off;
3059	uint16_t const offLast = offReg + cb - 1;
3060	if (DMAR_IS_MMIO_OFF_VALID(offLast))
3061	{
3062	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
3063	DMAR_LOCK_RET(pDevIns, pThisCC, VINF_IOM_R3_MMIO_WRITE);
3064
3065	uint64_t uPrev = 0;
3066	uint64_t const uRegWritten = cb == 8 ? dmarRegWrite64(pThis, offReg, (uint64_t )pv, &uPrev)
3067	: dmarRegWrite32(pThis, offReg, (uint32_t )pv, (uint32_t *)&uPrev);
3068	VBOXSTRICTRC rcStrict = VINF_SUCCESS;
3069	switch (off)
3070	{
3071	case VTD_MMIO_OFF_GCMD_REG: /* 32-bit */
3072	{
3073	rcStrict = dmarGcmdRegWrite(pDevIns, uRegWritten);
3074	break;
3075	}
3076
3077	case VTD_MMIO_OFF_CCMD_REG: /* 64-bit */
3078	case VTD_MMIO_OFF_CCMD_REG + 4:
3079	{
3080	rcStrict = dmarCcmdRegWrite(pDevIns, offReg, cb, uRegWritten);
3081	break;
3082	}
3083
3084	case VTD_MMIO_OFF_FSTS_REG: /* 32-bit */
3085	{
3086	rcStrict = dmarFstsRegWrite(pDevIns, uRegWritten, uPrev);
3087	break;
3088	}
3089
3090	case VTD_MMIO_OFF_FECTL_REG: /* 32-bit */
3091	{
3092	rcStrict = dmarFectlRegWrite(pDevIns, uRegWritten);
3093	break;
3094	}
3095
3096	case VTD_MMIO_OFF_IQT_REG: /* 64-bit */
3097	/* VTD_MMIO_OFF_IQT_REG + 4: / / High 32-bits reserved. */
3098	{
3099	rcStrict = dmarIqtRegWrite(pDevIns, offReg, uRegWritten);
3100	break;
3101	}
3102
3103	case VTD_MMIO_OFF_IQA_REG: /* 64-bit */
3104	/* VTD_MMIO_OFF_IQA_REG + 4: / / High 32-bits data. */
3105	{
3106	rcStrict = dmarIqaRegWrite(pDevIns, offReg, uRegWritten);
3107	break;
3108	}
3109
3110	case VTD_MMIO_OFF_ICS_REG: /* 32-bit */
3111	{
3112	rcStrict = dmarIcsRegWrite(pDevIns, uRegWritten);
3113	break;
3114	}
3115
3116	case VTD_MMIO_OFF_IECTL_REG: /* 32-bit */
3117	{
3118	rcStrict = dmarIectlRegWrite(pDevIns, uRegWritten);
3119	break;
3120	}
3121
3122	case DMAR_MMIO_OFF_FRCD_HI_REG: /* 64-bit */
3123	case DMAR_MMIO_OFF_FRCD_HI_REG + 4:
3124	{
3125	rcStrict = dmarFrcdHiRegWrite(pDevIns, offReg, cb, uRegWritten, uPrev);
3126	break;
3127	}
3128	}
3129
3130	DMAR_UNLOCK(pDevIns, pThisCC);
3131	LogFlowFunc(("offReg=%#x uRegWritten=%#RX64 rc=%Rrc\n", offReg, uRegWritten, VBOXSTRICTRC_VAL(rcStrict)));
3132	return rcStrict;
3133	}
3134
3135	return VINF_IOM_MMIO_UNUSED_FF;
3136	}
3137
3138
3139	/**
3140	* @callback_method_impl{FNIOMMMIONEWREAD}
3141	*/
3142	static DECLCALLBACK(VBOXSTRICTRC) dmarMmioRead(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS off, void pv, unsigned cb)
3143	{
3144	RT_NOREF1(pvUser);
3145	DMAR_ASSERT_MMIO_ACCESS_RET(off, cb);
3146
3147	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
3148	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioRead));
3149
3150	uint16_t const offReg = off;
3151	uint16_t const offLast = offReg + cb - 1;
3152	if (DMAR_IS_MMIO_OFF_VALID(offLast))
3153	{
3154	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
3155	DMAR_LOCK_RET(pDevIns, pThisCC, VINF_IOM_R3_MMIO_READ);
3156
3157	if (cb == 8)
3158	{
3159	(uint64_t )pv = dmarRegRead64(pThis, offReg);
3160	LogFlowFunc(("offReg=%#x pv=%#RX64\n", offReg, (uint64_t )pv));
3161	}
3162	else
3163	{
3164	(uint32_t )pv = dmarRegRead32(pThis, offReg);
3165	LogFlowFunc(("offReg=%#x pv=%#RX32\n", offReg, (uint32_t )pv));
3166	}
3167
3168	DMAR_UNLOCK(pDevIns, pThisCC);
3169	return VINF_SUCCESS;
3170	}
3171
3172	return VINF_IOM_MMIO_UNUSED_FF;
3173	}
3174
3175
3176	#ifdef IN_RING3
3177	/**
3178	* Process requests in the invalidation queue.
3179	*
3180	* @param pDevIns The IOMMU device instance.
3181	* @param pvRequests The requests to process.
3182	* @param cbRequests The size of all requests (in bytes).
3183	* @param fDw The descriptor width (VTD_IQA_REG_DW_128_BIT or
3184	* VTD_IQA_REG_DW_256_BIT).
3185	* @param fTtm The table translation mode. Must not be VTD_TTM_RSVD.
3186	*/
3187	static void dmarR3InvQueueProcessRequests(PPDMDEVINS pDevIns, void const *pvRequests, uint32_t cbRequests, uint8_t fDw,
3188	uint8_t fTtm)
3189	{
3190	#define DMAR_IQE_FAULT_RECORD_RET(a_enmDiag, a_enmIqei) \
3191	do \
3192	{ \
3193	dmarIqeFaultRecord(pDevIns, (a_enmDiag), (a_enmIqei)); \
3194	return; \
3195	} while (0)
3196
3197	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
3198	PCDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARR3);
3199
3200	DMAR_ASSERT_LOCK_IS_NOT_OWNER(pDevIns, pThisR3);
3201	Assert(fTtm != VTD_TTM_RSVD); /* Should've beeen handled by caller. */
3202
3203	/*
3204	* The below check is redundant since we check both TTM and DW for each
3205	* descriptor type we process. However, the order of errors reported by hardware
3206	* may differ hence this is kept commented out but not removed if we need to
3207	* change this in the future.
3208	*
3209	* In our implementation, we would report the descriptor type as invalid,
3210	* while on real hardware it may report descriptor width as invalid.
3211	* The Intel VT-d spec. is not clear which error takes preceedence.
3212	*/
3213	#if 0
3214	/*
3215	* Verify that 128-bit descriptors are not used when operating in scalable mode.
3216	* We don't check this while software writes IQA_REG but defer it until now because
3217	* RTADDR_REG can be updated lazily (via GCMD_REG.SRTP). The 256-bit descriptor check
3218	* -IS- performed when software writes IQA_REG since it only requires checking against
3219	* immutable hardware features.
3220	*/
3221	if ( fTtm != VTD_TTM_SCALABLE_MODE
3222	\|\| fDw != VTD_IQA_REG_DW_128_BIT)
3223	{ /* likely */ }
3224	else
3225	DMAR_IQE_FAULT_RECORD_RET(kDmarDiag_IqaReg_Dw_128_Invalid, VTDIQEI_INVALID_DESCRIPTOR_WIDTH);
3226	#endif
3227
3228	/*
3229	* Process requests in FIFO order.
3230	*/
3231	uint8_t const cbDsc = fDw == VTD_IQA_REG_DW_256_BIT ? 32 : 16;
3232	for (uint32_t offDsc = 0; offDsc < cbRequests; offDsc += cbDsc)
3233	{
3234	uint64_t const puDscQwords = (uint64_t const )((uintptr_t)pvRequests + offDsc);
3235	uint64_t const uQword0 = puDscQwords[0];
3236	uint64_t const uQword1 = puDscQwords[1];
3237	uint8_t const fDscType = VTD_GENERIC_INV_DSC_GET_TYPE(uQword0);
3238	switch (fDscType)
3239	{
3240	case VTD_INV_WAIT_DSC_TYPE:
3241	{
3242	/* Validate descriptor type. */
3243	if ( fTtm == VTD_TTM_LEGACY_MODE
3244	\|\| fDw == VTD_IQA_REG_DW_256_BIT)
3245	{ /* likely */ }
3246	else
3247	DMAR_IQE_FAULT_RECORD_RET(kDmarDiag_Iqei_Inv_Wait_Dsc_Invalid, VTDIQEI_INVALID_DESCRIPTOR_TYPE);
3248
3249	/* Validate reserved bits. */
3250	uint64_t const fValidMask0 = !(pThis->fExtCapReg & VTD_BF_ECAP_REG_PDS_MASK)
3251	? VTD_INV_WAIT_DSC_0_VALID_MASK & ~VTD_BF_0_INV_WAIT_DSC_PD_MASK
3252	: VTD_INV_WAIT_DSC_0_VALID_MASK;
3253	if ( !(uQword0 & ~fValidMask0)
3254	&& !(uQword1 & ~VTD_INV_WAIT_DSC_1_VALID_MASK))
3255	{ /* likely */ }
3256	else
3257	DMAR_IQE_FAULT_RECORD_RET(kDmarDiag_Iqei_Inv_Wait_Dsc_0_1_Rsvd, VTDIQEI_RSVD_FIELD_VIOLATION);
3258
3259	if (fDw == VTD_IQA_REG_DW_256_BIT)
3260	{
3261	if ( !puDscQwords[2]
3262	&& !puDscQwords[3])
3263	{ /* likely */ }
3264	else
3265	DMAR_IQE_FAULT_RECORD_RET(kDmarDiag_Iqei_Inv_Wait_Dsc_2_3_Rsvd, VTDIQEI_RSVD_FIELD_VIOLATION);
3266	}
3267
3268	/* Perform status write (this must be done prior to generating the completion interrupt). */
3269	bool const fSw = RT_BF_GET(uQword0, VTD_BF_0_INV_WAIT_DSC_SW);
3270	if (fSw)
3271	{
3272	uint32_t const uStatus = RT_BF_GET(uQword0, VTD_BF_0_INV_WAIT_DSC_STDATA);
3273	RTGCPHYS const GCPhysStatus = uQword1 & VTD_BF_1_INV_WAIT_DSC_STADDR_MASK;
3274	int const rc = PDMDevHlpPhysWrite(pDevIns, GCPhysStatus, (void const*)&uStatus, sizeof(uStatus));
3275	AssertRC(rc);
3276	}
3277
3278	/* Generate invalidation event interrupt. */
3279	bool const fIf = RT_BF_GET(uQword0, VTD_BF_0_INV_WAIT_DSC_IF);
3280	if (fIf)
3281	{
3282	DMAR_LOCK(pDevIns, pThisR3);
3283	dmarR3InvEventRaiseInterrupt(pDevIns);
3284	DMAR_UNLOCK(pDevIns, pThisR3);
3285	}
3286
3287	STAM_COUNTER_INC(&pThis->StatInvWaitDsc);
3288	break;
3289	}
3290
3291	case VTD_CC_INV_DSC_TYPE: STAM_COUNTER_INC(&pThis->StatCcInvDsc); break;
3292	case VTD_IOTLB_INV_DSC_TYPE: STAM_COUNTER_INC(&pThis->StatIotlbInvDsc); break;
3293	case VTD_DEV_TLB_INV_DSC_TYPE: STAM_COUNTER_INC(&pThis->StatDevtlbInvDsc); break;
3294	case VTD_IEC_INV_DSC_TYPE: STAM_COUNTER_INC(&pThis->StatIecInvDsc); break;
3295	case VTD_P_IOTLB_INV_DSC_TYPE: STAM_COUNTER_INC(&pThis->StatPasidIotlbInvDsc); break;
3296	case VTD_PC_INV_DSC_TYPE: STAM_COUNTER_INC(&pThis->StatPasidCacheInvDsc); break;
3297	case VTD_P_DEV_TLB_INV_DSC_TYPE: STAM_COUNTER_INC(&pThis->StatPasidDevtlbInvDsc); break;
3298	default:
3299	{
3300	/* Stop processing further requests. */
3301	LogFunc(("Invalid descriptor type: %#x\n", fDscType));
3302	DMAR_IQE_FAULT_RECORD_RET(kDmarDiag_Iqei_Dsc_Type_Invalid, VTDIQEI_INVALID_DESCRIPTOR_TYPE);
3303	}
3304	}
3305	}
3306	#undef DMAR_IQE_FAULT_RECORD_RET
3307	}
3308
3309
3310	/**
3311	* The invalidation-queue thread.
3312	*
3313	* @returns VBox status code.
3314	* @param pDevIns The IOMMU device instance.
3315	* @param pThread The command thread.
3316	*/
3317	static DECLCALLBACK(int) dmarR3InvQueueThread(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
3318	{
3319	NOREF(pThread);
3320	LogFlowFunc(("\n"));
3321
3322	if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
3323	return VINF_SUCCESS;
3324
3325	/*
3326	* Pre-allocate the maximum size of the invalidation queue allowed by the spec.
3327	* This prevents trashing the heap as well as deal with out-of-memory situations
3328	* up-front while starting the VM. It also simplifies the code from having to
3329	* dynamically grow/shrink the allocation based on how software sizes the queue.
3330	* Guests normally don't alter the queue size all the time, but that's not an
3331	* assumption we can make.
3332	*/
3333	uint8_t const cMaxPages = 1 << VTD_BF_IQA_REG_QS_MASK;
3334	size_t const cbMaxQs = cMaxPages << X86_PAGE_SHIFT;
3335	void *pvRequests = RTMemAllocZ(cbMaxQs);
3336	AssertPtrReturn(pvRequests, VERR_NO_MEMORY);
3337
3338	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
3339	PCDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARR3);
3340
3341	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
3342	{
3343	/*
3344	* Sleep until we are woken up.
3345	*/
3346	{
3347	int const rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->hEvtInvQueue, RT_INDEFINITE_WAIT);
3348	AssertLogRelMsgReturn(RT_SUCCESS(rc) \|\| rc == VERR_INTERRUPTED, ("%Rrc\n", rc), rc);
3349	if (RT_UNLIKELY(pThread->enmState != PDMTHREADSTATE_RUNNING))
3350	break;
3351	}
3352
3353	DMAR_LOCK(pDevIns, pThisR3);
3354	if (dmarInvQueueCanProcessRequests(pThis))
3355	{
3356	uint32_t offQueueHead;
3357	uint32_t offQueueTail;
3358	bool const fIsEmpty = dmarInvQueueIsEmptyEx(pThis, &offQueueHead, &offQueueTail);
3359	if (!fIsEmpty)
3360	{
3361	/*
3362	* Get the current queue size, descriptor width, queue base address and the
3363	* table translation mode while the lock is still held.
3364	*/
3365	uint64_t const uIqaReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IQA_REG);
3366	uint8_t const cQueuePages = 1 << (uIqaReg & VTD_BF_IQA_REG_QS_MASK);
3367	uint32_t const cbQueue = cQueuePages << X86_PAGE_SHIFT;
3368	uint8_t const fDw = RT_BF_GET(uIqaReg, VTD_BF_IQA_REG_DW);
3369	uint8_t const fTtm = RT_BF_GET(pThis->uRtaddrReg, VTD_BF_RTADDR_REG_TTM);
3370	RTGCPHYS const GCPhysRequests = (uIqaReg & VTD_BF_IQA_REG_IQA_MASK) + offQueueHead;
3371
3372	/* Paranoia. */
3373	Assert(cbQueue <= cbMaxQs);
3374	Assert(!(offQueueTail & ~VTD_BF_IQT_REG_QT_MASK));
3375	Assert(!(offQueueHead & ~VTD_BF_IQH_REG_QH_MASK));
3376	Assert(fDw != VTD_IQA_REG_DW_256_BIT \|\| !(offQueueTail & RT_BIT(4)));
3377	Assert(fDw != VTD_IQA_REG_DW_256_BIT \|\| !(offQueueHead & RT_BIT(4)));
3378	Assert(offQueueHead < cbQueue);
3379
3380	/*
3381	* A table translation mode of "reserved" isn't valid for any descriptor type.
3382	* However, RTADDR_REG can be modified in parallel to invalidation-queue processing,
3383	* but if ESRTPS is support, we will perform a global invalidation when software
3384	* changes RTADDR_REG, or it's the responsibility of software to do it explicitly.
3385	* So caching TTM while reading all descriptors should not be a problem.
3386	*
3387	* Also, validate the queue tail offset as it's mutable by software.
3388	*/
3389	if ( fTtm != VTD_TTM_RSVD
3390	&& offQueueTail < cbQueue)
3391	{
3392	/* Don't hold the lock while reading (a potentially large amount of) requests */
3393	DMAR_UNLOCK(pDevIns, pThisR3);
3394
3395	int rc;
3396	uint32_t cbRequests;
3397	if (offQueueTail > offQueueHead)
3398	{
3399	/* The requests have not wrapped around, read them in one go. */
3400	cbRequests = offQueueTail - offQueueHead;
3401	rc = PDMDevHlpPhysReadMeta(pDevIns, GCPhysRequests, pvRequests, cbRequests);
3402	}
3403	else
3404	{
3405	/* The requests have wrapped around, read forward and wrapped-around. */
3406	uint32_t const cbForward = cbQueue - offQueueHead;
3407	rc = PDMDevHlpPhysReadMeta(pDevIns, GCPhysRequests, pvRequests, cbForward);
3408
3409	uint32_t const cbWrapped = offQueueTail;
3410	if ( RT_SUCCESS(rc)
3411	&& cbWrapped > 0)
3412	{
3413	rc = PDMDevHlpPhysReadMeta(pDevIns, GCPhysRequests + cbForward,
3414	(void *)((uintptr_t)pvRequests + cbForward), cbWrapped);
3415	}
3416	cbRequests = cbForward + cbWrapped;
3417	}
3418
3419	/* Re-acquire the lock since we need to update device state. */
3420	DMAR_LOCK(pDevIns, pThisR3);
3421
3422	if (RT_SUCCESS(rc))
3423	{
3424	/* Indicate to software we've fetched all requests. */
3425	dmarRegWriteRaw64(pThis, VTD_MMIO_OFF_IQH_REG, offQueueTail);
3426
3427	/* Don't hold the lock while processing requests. */
3428	DMAR_UNLOCK(pDevIns, pThisR3);
3429
3430	/* Process all requests. */
3431	Assert(cbRequests <= cbQueue);
3432	dmarR3InvQueueProcessRequests(pDevIns, pvRequests, cbRequests, fDw, fTtm);
3433
3434	/*
3435	* We've processed all requests and the lock shouldn't be held at this point.
3436	* Using 'continue' here allows us to skip re-acquiring the lock just to release
3437	* it again before going back to the thread loop. It's a bit ugly but it certainly
3438	* helps with performance.
3439	*/
3440	DMAR_ASSERT_LOCK_IS_NOT_OWNER(pDevIns, pThisR3);
3441	continue;
3442	}
3443	else
3444	dmarIqeFaultRecord(pDevIns, kDmarDiag_IqaReg_Dsc_Fetch_Error, VTDIQEI_FETCH_DESCRIPTOR_ERR);
3445	}
3446	else
3447	{
3448	if (fTtm == VTD_TTM_RSVD)
3449	dmarIqeFaultRecord(pDevIns, kDmarDiag_Iqei_Ttm_Rsvd, VTDIQEI_INVALID_TTM);
3450	else
3451	{
3452	Assert(offQueueTail >= cbQueue);
3453	dmarIqeFaultRecord(pDevIns, kDmarDiag_IqtReg_Qt_Invalid, VTDIQEI_INVALID_TAIL_PTR);
3454	}
3455	}
3456	}
3457	}
3458	DMAR_UNLOCK(pDevIns, pThisR3);
3459	}
3460
3461	RTMemFree(pvRequests);
3462	pvRequests = NULL;
3463
3464	LogFlowFunc(("Invalidation-queue thread terminating\n"));
3465	return VINF_SUCCESS;
3466	}
3467
3468
3469	/**
3470	* Wakes up the invalidation-queue thread so it can respond to a state
3471	* change.
3472	*
3473	* @returns VBox status code.
3474	* @param pDevIns The IOMMU device instance.
3475	* @param pThread The invalidation-queue thread.
3476	*
3477	* @thread EMT.
3478	*/
3479	static DECLCALLBACK(int) dmarR3InvQueueThreadWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
3480	{
3481	RT_NOREF(pThread);
3482	LogFlowFunc(("\n"));
3483	PCDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
3484	return PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEvtInvQueue);
3485	}
3486
3487
3488	/**
3489	* @callback_method_impl{FNDBGFHANDLERDEV}
3490	*/
3491	static DECLCALLBACK(void) dmarR3DbgInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
3492	{
3493	PCDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
3494	PCDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARR3);
3495	bool const fVerbose = RTStrCmp(pszArgs, "verbose") == 0;
3496
3497	/*
3498	* We lock the device to get a consistent register state as it is
3499	* ASSUMED pHlp->pfnPrintf is expensive, so we copy the registers (the
3500	* ones we care about here) into temporaries and release the lock ASAP.
3501	*
3502	* Order of register being read and outputted is in accordance with the
3503	* spec. for no particular reason.
3504	* See Intel VT-d spec. 10.4 "Register Descriptions".
3505	*/
3506	DMAR_LOCK(pDevIns, pThisR3);
3507
3508	DMARDIAG const enmDiag = pThis->enmDiag;
3509	uint32_t const uVerReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_VER_REG);
3510	uint64_t const uCapReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_CAP_REG);
3511	uint64_t const uEcapReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_ECAP_REG);
3512	uint32_t const uGcmdReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GCMD_REG);
3513	uint32_t const uGstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GSTS_REG);
3514	uint64_t const uRtaddrReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_RTADDR_REG);
3515	uint64_t const uCcmdReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_CCMD_REG);
3516	uint32_t const uFstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FSTS_REG);
3517	uint32_t const uFectlReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FECTL_REG);
3518	uint32_t const uFedataReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FEDATA_REG);
3519	uint32_t const uFeaddrReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FEADDR_REG);
3520	uint32_t const uFeuaddrReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FEUADDR_REG);
3521	uint64_t const uAflogReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_AFLOG_REG);
3522	uint32_t const uPmenReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PMEN_REG);
3523	uint32_t const uPlmbaseReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PLMBASE_REG);
3524	uint32_t const uPlmlimitReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PLMLIMIT_REG);
3525	uint64_t const uPhmbaseReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_PHMBASE_REG);
3526	uint64_t const uPhmlimitReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_PHMLIMIT_REG);
3527	uint64_t const uIqhReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IQH_REG);
3528	uint64_t const uIqtReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IQT_REG);
3529	uint64_t const uIqaReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IQA_REG);
3530	uint32_t const uIcsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_ICS_REG);
3531	uint32_t const uIectlReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IECTL_REG);
3532	uint32_t const uIedataReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IEDATA_REG);
3533	uint32_t const uIeaddrReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IEADDR_REG);
3534	uint32_t const uIeuaddrReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IEUADDR_REG);
3535	uint64_t const uIqercdReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IQERCD_REG);
3536	uint64_t const uIrtaReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IRTA_REG);
3537	uint64_t const uPqhReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_PQH_REG);
3538	uint64_t const uPqtReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_PQT_REG);
3539	uint64_t const uPqaReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_PQA_REG);
3540	uint32_t const uPrsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PRS_REG);
3541	uint32_t const uPectlReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PECTL_REG);
3542	uint32_t const uPedataReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PEDATA_REG);
3543	uint32_t const uPeaddrReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PEADDR_REG);
3544	uint32_t const uPeuaddrReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PEUADDR_REG);
3545	uint64_t const uMtrrcapReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_MTRRCAP_REG);
3546	uint64_t const uMtrrdefReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_MTRRDEF_REG);
3547
3548	DMAR_UNLOCK(pDevIns, pThisR3);
3549
3550	const char *const pszDiag = enmDiag < RT_ELEMENTS(g_apszDmarDiagDesc) ? g_apszDmarDiagDesc[enmDiag] : "(Unknown)";
3551	pHlp->pfnPrintf(pHlp, "Intel-IOMMU:\n");
3552	pHlp->pfnPrintf(pHlp, " Diag = %s\n", pszDiag);
3553
3554	/*
3555	* Non-verbose output.
3556	*/
3557	if (!fVerbose)
3558	{
3559	pHlp->pfnPrintf(pHlp, " VER_REG = %#RX32\n", uVerReg);
3560	pHlp->pfnPrintf(pHlp, " CAP_REG = %#RX64\n", uCapReg);
3561	pHlp->pfnPrintf(pHlp, " ECAP_REG = %#RX64\n", uEcapReg);
3562	pHlp->pfnPrintf(pHlp, " GCMD_REG = %#RX32\n", uGcmdReg);
3563	pHlp->pfnPrintf(pHlp, " GSTS_REG = %#RX32\n", uGstsReg);
3564	pHlp->pfnPrintf(pHlp, " RTADDR_REG = %#RX64\n", uRtaddrReg);
3565	pHlp->pfnPrintf(pHlp, " CCMD_REG = %#RX64\n", uCcmdReg);
3566	pHlp->pfnPrintf(pHlp, " FSTS_REG = %#RX32\n", uFstsReg);
3567	pHlp->pfnPrintf(pHlp, " FECTL_REG = %#RX32\n", uFectlReg);
3568	pHlp->pfnPrintf(pHlp, " FEDATA_REG = %#RX32\n", uFedataReg);
3569	pHlp->pfnPrintf(pHlp, " FEADDR_REG = %#RX32\n", uFeaddrReg);
3570	pHlp->pfnPrintf(pHlp, " FEUADDR_REG = %#RX32\n", uFeuaddrReg);
3571	pHlp->pfnPrintf(pHlp, " AFLOG_REG = %#RX64\n", uAflogReg);
3572	pHlp->pfnPrintf(pHlp, " PMEN_REG = %#RX32\n", uPmenReg);
3573	pHlp->pfnPrintf(pHlp, " PLMBASE_REG = %#RX32\n", uPlmbaseReg);
3574	pHlp->pfnPrintf(pHlp, " PLMLIMIT_REG = %#RX32\n", uPlmlimitReg);
3575	pHlp->pfnPrintf(pHlp, " PHMBASE_REG = %#RX64\n", uPhmbaseReg);
3576	pHlp->pfnPrintf(pHlp, " PHMLIMIT_REG = %#RX64\n", uPhmlimitReg);
3577	pHlp->pfnPrintf(pHlp, " IQH_REG = %#RX64\n", uIqhReg);
3578	pHlp->pfnPrintf(pHlp, " IQT_REG = %#RX64\n", uIqtReg);
3579	pHlp->pfnPrintf(pHlp, " IQA_REG = %#RX64\n", uIqaReg);
3580	pHlp->pfnPrintf(pHlp, " ICS_REG = %#RX32\n", uIcsReg);
3581	pHlp->pfnPrintf(pHlp, " IECTL_REG = %#RX32\n", uIectlReg);
3582	pHlp->pfnPrintf(pHlp, " IEDATA_REG = %#RX32\n", uIedataReg);
3583	pHlp->pfnPrintf(pHlp, " IEADDR_REG = %#RX32\n", uIeaddrReg);
3584	pHlp->pfnPrintf(pHlp, " IEUADDR_REG = %#RX32\n", uIeuaddrReg);
3585	pHlp->pfnPrintf(pHlp, " IQERCD_REG = %#RX64\n", uIqercdReg);
3586	pHlp->pfnPrintf(pHlp, " IRTA_REG = %#RX64\n", uIrtaReg);
3587	pHlp->pfnPrintf(pHlp, " PQH_REG = %#RX64\n", uPqhReg);
3588	pHlp->pfnPrintf(pHlp, " PQT_REG = %#RX64\n", uPqtReg);
3589	pHlp->pfnPrintf(pHlp, " PQA_REG = %#RX64\n", uPqaReg);
3590	pHlp->pfnPrintf(pHlp, " PRS_REG = %#RX32\n", uPrsReg);
3591	pHlp->pfnPrintf(pHlp, " PECTL_REG = %#RX32\n", uPectlReg);
3592	pHlp->pfnPrintf(pHlp, " PEDATA_REG = %#RX32\n", uPedataReg);
3593	pHlp->pfnPrintf(pHlp, " PEADDR_REG = %#RX32\n", uPeaddrReg);
3594	pHlp->pfnPrintf(pHlp, " PEUADDR_REG = %#RX32\n", uPeuaddrReg);
3595	pHlp->pfnPrintf(pHlp, " MTRRCAP_REG = %#RX64\n", uMtrrcapReg);
3596	pHlp->pfnPrintf(pHlp, " MTRRDEF_REG = %#RX64\n", uMtrrdefReg);
3597	pHlp->pfnPrintf(pHlp, "\n");
3598	return;
3599	}
3600
3601	/*
3602	* Verbose output.
3603	*/
3604	pHlp->pfnPrintf(pHlp, " VER_REG = %#RX32\n", uVerReg);
3605	{
3606	pHlp->pfnPrintf(pHlp, " MAJ = %#x\n", RT_BF_GET(uVerReg, VTD_BF_VER_REG_MAX));
3607	pHlp->pfnPrintf(pHlp, " MIN = %#x\n", RT_BF_GET(uVerReg, VTD_BF_VER_REG_MIN));
3608	}
3609	pHlp->pfnPrintf(pHlp, " CAP_REG = %#RX64\n", uCapReg);
3610	{
3611	uint8_t const uMgaw = RT_BF_GET(uCapReg, VTD_BF_CAP_REG_MGAW);
3612	uint8_t const uNfr = RT_BF_GET(uCapReg, VTD_BF_CAP_REG_NFR);
3613	pHlp->pfnPrintf(pHlp, " ND = %u\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_ND));
3614	pHlp->pfnPrintf(pHlp, " AFL = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_AFL));
3615	pHlp->pfnPrintf(pHlp, " RWBF = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_RWBF));
3616	pHlp->pfnPrintf(pHlp, " PLMR = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_PLMR));
3617	pHlp->pfnPrintf(pHlp, " PHMR = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_PHMR));
3618	pHlp->pfnPrintf(pHlp, " CM = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_CM));
3619	pHlp->pfnPrintf(pHlp, " SAGAW = %#x\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_SAGAW));
3620	pHlp->pfnPrintf(pHlp, " MGAW = %#x (%u bits)\n", uMgaw, uMgaw + 1);
3621	pHlp->pfnPrintf(pHlp, " ZLR = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_ZLR));
3622	pHlp->pfnPrintf(pHlp, " FRO = %#x bytes\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_FRO));
3623	pHlp->pfnPrintf(pHlp, " SLLPS = %#x\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_SLLPS));
3624	pHlp->pfnPrintf(pHlp, " PSI = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_PSI));
3625	pHlp->pfnPrintf(pHlp, " NFR = %u (%u FRCD register%s)\n", uNfr, uNfr + 1, uNfr > 0 ? "s" : "");
3626	pHlp->pfnPrintf(pHlp, " MAMV = %#x\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_MAMV));
3627	pHlp->pfnPrintf(pHlp, " DWD = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_DWD));
3628	pHlp->pfnPrintf(pHlp, " DRD = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_DRD));
3629	pHlp->pfnPrintf(pHlp, " FL1GP = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_FL1GP));
3630	pHlp->pfnPrintf(pHlp, " PI = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_PI));
3631	pHlp->pfnPrintf(pHlp, " FL5LP = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_FL5LP));
3632	pHlp->pfnPrintf(pHlp, " ESIRTPS = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_ESIRTPS));
3633	pHlp->pfnPrintf(pHlp, " ESRTPS = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_ESRTPS));
3634	}
3635	pHlp->pfnPrintf(pHlp, " ECAP_REG = %#RX64\n", uEcapReg);
3636	{
3637	uint8_t const uPss = RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_PSS);
3638	pHlp->pfnPrintf(pHlp, " C = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_C));
3639	pHlp->pfnPrintf(pHlp, " QI = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_QI));
3640	pHlp->pfnPrintf(pHlp, " DT = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_DT));
3641	pHlp->pfnPrintf(pHlp, " IR = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_IR));
3642	pHlp->pfnPrintf(pHlp, " EIM = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_EIM));
3643	pHlp->pfnPrintf(pHlp, " PT = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_PT));
3644	pHlp->pfnPrintf(pHlp, " SC = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_SC));
3645	pHlp->pfnPrintf(pHlp, " IRO = %#x bytes\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_IRO));
3646	pHlp->pfnPrintf(pHlp, " MHMV = %#x\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_MHMV));
3647	pHlp->pfnPrintf(pHlp, " MTS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_MTS));
3648	pHlp->pfnPrintf(pHlp, " NEST = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_NEST));
3649	pHlp->pfnPrintf(pHlp, " PRS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_PRS));
3650	pHlp->pfnPrintf(pHlp, " ERS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_ERS));
3651	pHlp->pfnPrintf(pHlp, " SRS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_SRS));
3652	pHlp->pfnPrintf(pHlp, " NWFS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_NWFS));
3653	pHlp->pfnPrintf(pHlp, " EAFS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_EAFS));
3654	pHlp->pfnPrintf(pHlp, " PSS = %u (%u bits)\n", uPss, uPss > 0 ? uPss + 1 : 0);
3655	pHlp->pfnPrintf(pHlp, " PASID = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_PASID));
3656	pHlp->pfnPrintf(pHlp, " DIT = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_DIT));
3657	pHlp->pfnPrintf(pHlp, " PDS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_PDS));
3658	pHlp->pfnPrintf(pHlp, " SMTS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_SMTS));
3659	pHlp->pfnPrintf(pHlp, " VCS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_VCS));
3660	pHlp->pfnPrintf(pHlp, " SLADS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_SLADS));
3661	pHlp->pfnPrintf(pHlp, " SLTS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_SLTS));
3662	pHlp->pfnPrintf(pHlp, " FLTS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_FLTS));
3663	pHlp->pfnPrintf(pHlp, " SMPWCS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_SMPWCS));
3664	pHlp->pfnPrintf(pHlp, " RPS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_RPS));
3665	pHlp->pfnPrintf(pHlp, " ADMS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_ADMS));
3666	pHlp->pfnPrintf(pHlp, " RPRIVS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_RPRIVS));
3667	}
3668	pHlp->pfnPrintf(pHlp, " GCMD_REG = %#RX32\n", uGcmdReg);
3669	{
3670	uint8_t const fCfi = RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_CFI);
3671	pHlp->pfnPrintf(pHlp, " CFI = %u (%s)\n", fCfi, fCfi ? "Passthrough" : "Blocked");
3672	pHlp->pfnPrintf(pHlp, " SIRTP = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_SIRTP));
3673	pHlp->pfnPrintf(pHlp, " IRE = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_IRE));
3674	pHlp->pfnPrintf(pHlp, " QIE = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_QIE));
3675	pHlp->pfnPrintf(pHlp, " WBF = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_WBF));
3676	pHlp->pfnPrintf(pHlp, " EAFL = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_SFL));
3677	pHlp->pfnPrintf(pHlp, " SFL = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_SFL));
3678	pHlp->pfnPrintf(pHlp, " SRTP = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_SRTP));
3679	pHlp->pfnPrintf(pHlp, " TE = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_TE));
3680	}
3681	pHlp->pfnPrintf(pHlp, " GSTS_REG = %#RX32\n", uGstsReg);
3682	{
3683	uint8_t const fCfis = RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_CFIS);
3684	pHlp->pfnPrintf(pHlp, " CFIS = %u (%s)\n", fCfis, fCfis ? "Passthrough" : "Blocked");
3685	pHlp->pfnPrintf(pHlp, " IRTPS = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_IRTPS));
3686	pHlp->pfnPrintf(pHlp, " IRES = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_IRES));
3687	pHlp->pfnPrintf(pHlp, " QIES = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_QIES));
3688	pHlp->pfnPrintf(pHlp, " WBFS = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_WBFS));
3689	pHlp->pfnPrintf(pHlp, " AFLS = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_AFLS));
3690	pHlp->pfnPrintf(pHlp, " FLS = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_FLS));
3691	pHlp->pfnPrintf(pHlp, " RTPS = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_RTPS));
3692	pHlp->pfnPrintf(pHlp, " TES = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_TES));
3693	}
3694	pHlp->pfnPrintf(pHlp, " RTADDR_REG = %#RX64\n", uRtaddrReg);
3695	{
3696	uint8_t const uTtm = RT_BF_GET(uRtaddrReg, VTD_BF_RTADDR_REG_TTM);
3697	pHlp->pfnPrintf(pHlp, " RTA = %#RX64\n", uRtaddrReg & VTD_BF_RTADDR_REG_RTA_MASK);
3698	pHlp->pfnPrintf(pHlp, " TTM = %u (%s)\n", uTtm, vtdRtaddrRegGetTtmDesc(uTtm));
3699	}
3700	pHlp->pfnPrintf(pHlp, " CCMD_REG = %#RX64\n", uCcmdReg);
3701	pHlp->pfnPrintf(pHlp, " FSTS_REG = %#RX32\n", uFstsReg);
3702	{
3703	pHlp->pfnPrintf(pHlp, " PFO = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_PFO));
3704	pHlp->pfnPrintf(pHlp, " PPF = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_PPF));
3705	pHlp->pfnPrintf(pHlp, " AFO = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_AFO));
3706	pHlp->pfnPrintf(pHlp, " APF = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_APF));
3707	pHlp->pfnPrintf(pHlp, " IQE = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_IQE));
3708	pHlp->pfnPrintf(pHlp, " ICS = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_ICE));
3709	pHlp->pfnPrintf(pHlp, " ITE = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_ITE));
3710	pHlp->pfnPrintf(pHlp, " FRI = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_FRI));
3711	}
3712	pHlp->pfnPrintf(pHlp, " FECTL_REG = %#RX32\n", uFectlReg);
3713	{
3714	pHlp->pfnPrintf(pHlp, " IM = %RTbool\n", RT_BF_GET(uFectlReg, VTD_BF_FECTL_REG_IM));
3715	pHlp->pfnPrintf(pHlp, " IP = %RTbool\n", RT_BF_GET(uFectlReg, VTD_BF_FECTL_REG_IP));
3716	}
3717	pHlp->pfnPrintf(pHlp, " FEDATA_REG = %#RX32\n", uFedataReg);
3718	pHlp->pfnPrintf(pHlp, " FEADDR_REG = %#RX32\n", uFeaddrReg);
3719	pHlp->pfnPrintf(pHlp, " FEUADDR_REG = %#RX32\n", uFeuaddrReg);
3720	pHlp->pfnPrintf(pHlp, " AFLOG_REG = %#RX64\n", uAflogReg);
3721	pHlp->pfnPrintf(pHlp, " PMEN_REG = %#RX32\n", uPmenReg);
3722	pHlp->pfnPrintf(pHlp, " PLMBASE_REG = %#RX32\n", uPlmbaseReg);
3723	pHlp->pfnPrintf(pHlp, " PLMLIMIT_REG = %#RX32\n", uPlmlimitReg);
3724	pHlp->pfnPrintf(pHlp, " PHMBASE_REG = %#RX64\n", uPhmbaseReg);
3725	pHlp->pfnPrintf(pHlp, " PHMLIMIT_REG = %#RX64\n", uPhmlimitReg);
3726	pHlp->pfnPrintf(pHlp, " IQH_REG = %#RX64\n", uIqhReg);
3727	pHlp->pfnPrintf(pHlp, " IQT_REG = %#RX64\n", uIqtReg);
3728	pHlp->pfnPrintf(pHlp, " IQA_REG = %#RX64\n", uIqaReg);
3729	{
3730	uint8_t const fDw = RT_BF_GET(uIqaReg, VTD_BF_IQA_REG_DW);
3731	uint8_t const fQs = RT_BF_GET(uIqaReg, VTD_BF_IQA_REG_QS);
3732	uint8_t const cQueuePages = 1 << fQs;
3733	pHlp->pfnPrintf(pHlp, " DW = %u (%s)\n", fDw, fDw == VTD_IQA_REG_DW_128_BIT ? "128-bit" : "256-bit");
3734	pHlp->pfnPrintf(pHlp, " QS = %u (%u page%s)\n", fQs, cQueuePages, cQueuePages > 1 ? "s" : "");
3735	}
3736	pHlp->pfnPrintf(pHlp, " ICS_REG = %#RX32\n", uIcsReg);
3737	{
3738	pHlp->pfnPrintf(pHlp, " IWC = %u\n", RT_BF_GET(uIcsReg, VTD_BF_ICS_REG_IWC));
3739	}
3740	pHlp->pfnPrintf(pHlp, " IECTL_REG = %#RX32\n", uIectlReg);
3741	{
3742	pHlp->pfnPrintf(pHlp, " IM = %RTbool\n", RT_BF_GET(uIectlReg, VTD_BF_IECTL_REG_IM));
3743	pHlp->pfnPrintf(pHlp, " IP = %RTbool\n", RT_BF_GET(uIectlReg, VTD_BF_IECTL_REG_IP));
3744	}
3745	pHlp->pfnPrintf(pHlp, " IEDATA_REG = %#RX32\n", uIedataReg);
3746	pHlp->pfnPrintf(pHlp, " IEADDR_REG = %#RX32\n", uIeaddrReg);
3747	pHlp->pfnPrintf(pHlp, " IEUADDR_REG = %#RX32\n", uIeuaddrReg);
3748	pHlp->pfnPrintf(pHlp, " IQERCD_REG = %#RX64\n", uIqercdReg);
3749	{
3750	pHlp->pfnPrintf(pHlp, " ICESID = %#RX32\n", RT_BF_GET(uIqercdReg, VTD_BF_IQERCD_REG_ICESID));
3751	pHlp->pfnPrintf(pHlp, " ITESID = %#RX32\n", RT_BF_GET(uIqercdReg, VTD_BF_IQERCD_REG_ITESID));
3752	pHlp->pfnPrintf(pHlp, " IQEI = %#RX32\n", RT_BF_GET(uIqercdReg, VTD_BF_IQERCD_REG_IQEI));
3753	}
3754	pHlp->pfnPrintf(pHlp, " IRTA_REG = %#RX64\n", uIrtaReg);
3755	{
3756	uint32_t const cIrtEntries = VTD_IRTA_REG_GET_ENTRY_COUNT(uIrtaReg);
3757	uint32_t const cbIrt = sizeof(VTD_IRTE_T) * cIrtEntries;
3758	pHlp->pfnPrintf(pHlp, " IRTA = %#RX64\n", uIrtaReg & VTD_BF_IRTA_REG_IRTA_MASK);
3759	pHlp->pfnPrintf(pHlp, " EIME = %RTbool\n", RT_BF_GET(uIrtaReg, VTD_BF_IRTA_REG_EIME));
3760	pHlp->pfnPrintf(pHlp, " S = %u entries (%u bytes)\n", cIrtEntries, cbIrt);
3761	}
3762	pHlp->pfnPrintf(pHlp, " PQH_REG = %#RX64\n", uPqhReg);
3763	pHlp->pfnPrintf(pHlp, " PQT_REG = %#RX64\n", uPqtReg);
3764	pHlp->pfnPrintf(pHlp, " PQA_REG = %#RX64\n", uPqaReg);
3765	pHlp->pfnPrintf(pHlp, " PRS_REG = %#RX32\n", uPrsReg);
3766	pHlp->pfnPrintf(pHlp, " PECTL_REG = %#RX32\n", uPectlReg);
3767	pHlp->pfnPrintf(pHlp, " PEDATA_REG = %#RX32\n", uPedataReg);
3768	pHlp->pfnPrintf(pHlp, " PEADDR_REG = %#RX32\n", uPeaddrReg);
3769	pHlp->pfnPrintf(pHlp, " PEUADDR_REG = %#RX32\n", uPeuaddrReg);
3770	pHlp->pfnPrintf(pHlp, " MTRRCAP_REG = %#RX64\n", uMtrrcapReg);
3771	pHlp->pfnPrintf(pHlp, " MTRRDEF_REG = %#RX64\n", uMtrrdefReg);
3772	pHlp->pfnPrintf(pHlp, "\n");
3773	}
3774
3775
3776	/**
3777	* Initializes all registers in the DMAR unit.
3778	*
3779	* @param pDevIns The IOMMU device instance.
3780	*/
3781	static void dmarR3RegsInit(PPDMDEVINS pDevIns)
3782	{
3783	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
3784	LogFlowFunc(("\n"));
3785
3786	/*
3787	* Wipe all registers (required on reset).
3788	*/
3789	RT_ZERO(pThis->abRegs0);
3790	RT_ZERO(pThis->abRegs1);
3791
3792	/*
3793	* Initialize registers not mutable by software prior to initializing other registers.
3794	*/
3795	/* VER_REG */
3796	{
3797	pThis->uVerReg = RT_BF_MAKE(VTD_BF_VER_REG_MIN, DMAR_VER_MINOR)
3798	\| RT_BF_MAKE(VTD_BF_VER_REG_MAX, DMAR_VER_MAJOR);
3799	dmarRegWriteRaw64(pThis, VTD_MMIO_OFF_VER_REG, pThis->uVerReg);
3800	}
3801
3802	uint8_t const fFlts = 1; /* First-level translation support. */
3803	uint8_t const fSlts = 1; /* Second-level translation support. */
3804	uint8_t const fPt = 1; /* Pass-Through support. */
3805	uint8_t const fSmts = fFlts & fSlts & fPt; /* Scalable mode translation support.*/
3806	uint8_t const fNest = 0; /* Nested translation support. */
3807
3808	/* CAP_REG */
3809	{
3810	uint8_t cGstPhysAddrBits;
3811	uint8_t cGstLinearAddrBits;
3812	PDMDevHlpCpuGetGuestAddrWidths(pDevIns, &cGstPhysAddrBits, &cGstLinearAddrBits);
3813
3814	uint8_t const fFl1gp = 1; /* First-level 1GB pages support. */
3815	uint8_t const fFl5lp = 1; /* First-level 5-level paging support (PML5E). */
3816	uint8_t const fSl2mp = 1; /* Second-level 2MB pages support. */
3817	uint8_t const fSl2gp = fSl2mp & 1; /* Second-level 1GB pages support. */
3818	uint8_t const fSllps = fSl2mp \| (fSl2gp << 1); /* Second-level large page support. */
3819	uint8_t const fMamv = (fSl2gp ? X86_PAGE_1G_SHIFT /* Maximum address mask value (for 2nd-level invalidations). */
3820	: X86_PAGE_2M_SHIFT)
3821	- X86_PAGE_4K_SHIFT;
3822	uint8_t const fNd = DMAR_ND; /* Number of domains supported. */
3823	uint8_t const fPsi = 1; /* Page selective invalidation. */
3824	uint8_t const uMgaw = cGstPhysAddrBits - 1; /* Maximum guest address width. */
3825	uint8_t const fSagaw = vtdCapRegGetSagaw(uMgaw); /* Supported adjust guest address width. */
3826	uint16_t const offFro = DMAR_MMIO_OFF_FRCD_LO_REG >> 4; /* MMIO offset of FRCD registers. */
3827	uint8_t const fEsrtps = 1; /* Enhanced SRTPS (auto invalidate cache on SRTP). */
3828	uint8_t const fEsirtps = 1; /* Enhanced SIRTPS (auto invalidate cache on SIRTP). */
3829	AssertCompile(DMAR_ND <= 6);
3830
3831	pThis->fCapReg = RT_BF_MAKE(VTD_BF_CAP_REG_ND, fNd)
3832	\| RT_BF_MAKE(VTD_BF_CAP_REG_AFL, 0) /* Advanced fault logging not supported. */
3833	\| RT_BF_MAKE(VTD_BF_CAP_REG_RWBF, 0) /* Software need not flush write-buffers. */
3834	\| RT_BF_MAKE(VTD_BF_CAP_REG_PLMR, 0) /* Protected Low-Memory Region not supported. */
3835	\| RT_BF_MAKE(VTD_BF_CAP_REG_PHMR, 0) /* Protected High-Memory Region not supported. */
3836	\| RT_BF_MAKE(VTD_BF_CAP_REG_CM, 1) /* Software should invalidate on mapping structure changes. */
3837	\| RT_BF_MAKE(VTD_BF_CAP_REG_SAGAW, fSlts ? fSagaw : 0)
3838	\| RT_BF_MAKE(VTD_BF_CAP_REG_MGAW, uMgaw)
3839	\| RT_BF_MAKE(VTD_BF_CAP_REG_ZLR, 1) /** @todo Figure out if/how to support zero-length reads. */
3840	\| RT_BF_MAKE(VTD_BF_CAP_REG_FRO, offFro)
3841	\| RT_BF_MAKE(VTD_BF_CAP_REG_SLLPS, fSlts & fSllps)
3842	\| RT_BF_MAKE(VTD_BF_CAP_REG_PSI, fPsi)
3843	\| RT_BF_MAKE(VTD_BF_CAP_REG_NFR, DMAR_FRCD_REG_COUNT - 1)
3844	\| RT_BF_MAKE(VTD_BF_CAP_REG_MAMV, fPsi & fMamv)
3845	\| RT_BF_MAKE(VTD_BF_CAP_REG_DWD, 1)
3846	\| RT_BF_MAKE(VTD_BF_CAP_REG_DRD, 1)
3847	\| RT_BF_MAKE(VTD_BF_CAP_REG_FL1GP, fFlts & fFl1gp)
3848	\| RT_BF_MAKE(VTD_BF_CAP_REG_PI, 0) /* Posted Interrupts not supported. */
3849	\| RT_BF_MAKE(VTD_BF_CAP_REG_FL5LP, fFlts & fFl5lp)
3850	\| RT_BF_MAKE(VTD_BF_CAP_REG_ESIRTPS, fEsirtps)
3851	\| RT_BF_MAKE(VTD_BF_CAP_REG_ESRTPS, fEsrtps);
3852	dmarRegWriteRaw64(pThis, VTD_MMIO_OFF_CAP_REG, pThis->fCapReg);
3853
3854	pThis->fHawBaseMask = ~(UINT64_MAX << cGstPhysAddrBits) & X86_PAGE_4K_BASE_MASK;
3855	pThis->fMgawInvMask = UINT64_MAX << cGstPhysAddrBits;
3856	pThis->cMaxPagingLevel = vtdCapRegGetMaxPagingLevel(fSagaw);
3857	}
3858
3859	/* ECAP_REG */
3860	{
3861	uint8_t const fQi = 1; /* Queued-invalidations. */
3862	uint8_t const fIr = !!(DMAR_ACPI_DMAR_FLAGS & ACPI_DMAR_F_INTR_REMAP); /* Interrupt remapping support. */
3863	uint8_t const fMhmv = 0xf; /* Maximum handle mask value. */
3864	uint16_t const offIro = DMAR_MMIO_OFF_IVA_REG >> 4; /* MMIO offset of IOTLB registers. */
3865	uint8_t const fEim = 1; /* Extended interrupt mode.*/
3866	uint8_t const fAdms = 1; /* Abort DMA mode support. */
3867	uint8_t const fErs = 0; /* Execute Request (not supported). */
3868
3869	pThis->fExtCapReg = RT_BF_MAKE(VTD_BF_ECAP_REG_C, 0) /* Accesses don't snoop CPU cache. */
3870	\| RT_BF_MAKE(VTD_BF_ECAP_REG_QI, fQi)
3871	\| RT_BF_MAKE(VTD_BF_ECAP_REG_DT, 0) /* Device-TLBs not supported. */
3872	\| RT_BF_MAKE(VTD_BF_ECAP_REG_IR, fQi & fIr)
3873	\| RT_BF_MAKE(VTD_BF_ECAP_REG_EIM, fIr & fEim)
3874	\| RT_BF_MAKE(VTD_BF_ECAP_REG_PT, fPt)
3875	\| RT_BF_MAKE(VTD_BF_ECAP_REG_SC, 0) /* Snoop control not supported. */
3876	\| RT_BF_MAKE(VTD_BF_ECAP_REG_IRO, offIro)
3877	\| RT_BF_MAKE(VTD_BF_ECAP_REG_MHMV, fIr & fMhmv)
3878	\| RT_BF_MAKE(VTD_BF_ECAP_REG_MTS, 0) /* Memory type not supported. */
3879	\| RT_BF_MAKE(VTD_BF_ECAP_REG_NEST, fNest)
3880	\| RT_BF_MAKE(VTD_BF_ECAP_REG_PRS, 0) /* 0 as DT not supported. */
3881	\| RT_BF_MAKE(VTD_BF_ECAP_REG_ERS, fErs)
3882	\| RT_BF_MAKE(VTD_BF_ECAP_REG_SRS, 0) /* Supervisor request not supported. */
3883	\| RT_BF_MAKE(VTD_BF_ECAP_REG_NWFS, 0) /* 0 as DT not supported. */
3884	\| RT_BF_MAKE(VTD_BF_ECAP_REG_EAFS, 0) /* 0 as SMPWCS not supported. */
3885	\| RT_BF_MAKE(VTD_BF_ECAP_REG_PSS, 0) /* 0 as PASID not supported. */
3886	\| RT_BF_MAKE(VTD_BF_ECAP_REG_PASID, 0) /* PASID not supported. */
3887	\| RT_BF_MAKE(VTD_BF_ECAP_REG_DIT, 0) /* 0 as DT not supported. */
3888	\| RT_BF_MAKE(VTD_BF_ECAP_REG_PDS, 0) /* 0 as DT not supported. */
3889	\| RT_BF_MAKE(VTD_BF_ECAP_REG_SMTS, fSmts)
3890	\| RT_BF_MAKE(VTD_BF_ECAP_REG_VCS, 0) /* 0 as PASID not supported (commands seem PASID specific). */
3891	\| RT_BF_MAKE(VTD_BF_ECAP_REG_SLADS, 0) /* Second-level accessed/dirty not supported. */
3892	\| RT_BF_MAKE(VTD_BF_ECAP_REG_SLTS, fSlts)
3893	\| RT_BF_MAKE(VTD_BF_ECAP_REG_FLTS, fFlts)
3894	\| RT_BF_MAKE(VTD_BF_ECAP_REG_SMPWCS, 0) /* 0 as PASID not supported. */
3895	\| RT_BF_MAKE(VTD_BF_ECAP_REG_RPS, 0) /* We don't support RID_PASID field in SM context entry. */
3896	\| RT_BF_MAKE(VTD_BF_ECAP_REG_ADMS, fAdms)
3897	\| RT_BF_MAKE(VTD_BF_ECAP_REG_RPRIVS, 0); /* 0 as SRS not supported. */
3898	dmarRegWriteRaw64(pThis, VTD_MMIO_OFF_ECAP_REG, pThis->fExtCapReg);
3899
3900	pThis->fPermValidMask = DMAR_PERM_READ \| DMAR_PERM_WRITE;
3901	if (fErs)
3902	pThis->fPermValidMask = DMAR_PERM_EXE;
3903	}
3904
3905	/*
3906	* Initialize registers mutable by software.
3907	*/
3908	/* FECTL_REG */
3909	{
3910	uint32_t const uCtl = RT_BF_MAKE(VTD_BF_FECTL_REG_IM, 1);
3911	dmarRegWriteRaw32(pThis, VTD_MMIO_OFF_FECTL_REG, uCtl);
3912	}
3913
3914	/* ICETL_REG */
3915	{
3916	uint32_t const uCtl = RT_BF_MAKE(VTD_BF_IECTL_REG_IM, 1);
3917	dmarRegWriteRaw32(pThis, VTD_MMIO_OFF_IECTL_REG, uCtl);
3918	}
3919
3920	#ifdef VBOX_STRICT
3921	Assert(!RT_BF_GET(pThis->fExtCapReg, VTD_BF_ECAP_REG_PRS)); /* PECTL_REG - Reserved if don't support PRS. */
3922	Assert(!RT_BF_GET(pThis->fExtCapReg, VTD_BF_ECAP_REG_MTS)); /* MTRRCAP_REG - Reserved if we don't support MTS. */
3923	#endif
3924	}
3925
3926
3927	/**
3928	* @callback_method_impl{FNSSMDEVSAVEEXEC}
3929	*/
3930	static DECLCALLBACK(int) dmarR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
3931	{
3932	PCDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PCDMAR);
3933	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
3934	LogFlowFunc(("\n"));
3935
3936	/* First, save software-immutable registers that we validate on state load. */
3937	pHlp->pfnSSMPutU32(pSSM, pThis->uVerReg);
3938	pHlp->pfnSSMPutU64(pSSM, pThis->fCapReg);
3939	pHlp->pfnSSMPutU64(pSSM, pThis->fExtCapReg);
3940
3941	/* Save MMIO registers. */
3942	pHlp->pfnSSMPutU32(pSSM, DMAR_MMIO_GROUP_COUNT);
3943	pHlp->pfnSSMPutU32(pSSM, sizeof(pThis->abRegs0));
3944	pHlp->pfnSSMPutMem(pSSM, &pThis->abRegs0[0], sizeof(pThis->abRegs0));
3945	pHlp->pfnSSMPutU32(pSSM, sizeof(pThis->abRegs1));
3946	pHlp->pfnSSMPutMem(pSSM, &pThis->abRegs1[0], sizeof(pThis->abRegs1));
3947
3948	/* Save lazily activated registers. */
3949	pHlp->pfnSSMPutU64(pSSM, pThis->uIrtaReg);
3950	pHlp->pfnSSMPutU64(pSSM, pThis->uRtaddrReg);
3951
3952	/* Save terminator marker and return status. */
3953	return pHlp->pfnSSMPutU32(pSSM, UINT32_MAX);
3954	}
3955
3956
3957	/**
3958	* @callback_method_impl{FNSSMDEVLOADEXEC}
3959	*/
3960	static DECLCALLBACK(int) dmarR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
3961	{
3962	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
3963	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
3964	int const rcDataErr = VERR_SSM_UNEXPECTED_DATA;
3965	int const rcFmtErr = VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
3966	LogFlowFunc(("\n"));
3967
3968	/*
3969	* Validate saved-state version.
3970	*/
3971	AssertReturn(uPass == SSM_PASS_FINAL, VERR_WRONG_ORDER);
3972	if (uVersion != DMAR_SAVED_STATE_VERSION)
3973	{
3974	LogRel(("%s: Invalid saved-state version %#x\n", DMAR_LOG_PFX, uVersion));
3975	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
3976	}
3977
3978	/*
3979	* Load and validate software-immutable registers.
3980	*/
3981	{
3982	/* VER_REG */
3983	uint32_t uVerReg;
3984	int rc = pHlp->pfnSSMGetU32(pSSM, &uVerReg);
3985	AssertRCReturn(rc, rc);
3986	AssertLogRelMsgReturn(uVerReg == pThis->uVerReg,
3987	("%s: VER_REG mismatch (expected %#RX32 got %#RX32)\n", DMAR_LOG_PFX, pThis->uVerReg, uVerReg),
3988	rcDataErr);
3989
3990	/* CAP_REG */
3991	uint64_t fCapReg;
3992	pHlp->pfnSSMGetU64(pSSM, &fCapReg);
3993	AssertLogRelMsgReturn(fCapReg == pThis->fCapReg,
3994	("%s: CAP_REG mismatch (expected %#RX64 got %#RX64)\n", DMAR_LOG_PFX, pThis->fCapReg, fCapReg),
3995	rcDataErr);
3996
3997	/* ECAP_REG */
3998	uint64_t fExtCapReg;
3999	pHlp->pfnSSMGetU64(pSSM, &fExtCapReg);
4000	AssertLogRelMsgReturn(fExtCapReg == pThis->fExtCapReg,
4001	("%s: ECAP_REG mismatch (expected %#RX64 got %#RX64)\n", DMAR_LOG_PFX, pThis->fExtCapReg,
4002	fExtCapReg), rcDataErr);
4003	}
4004
4005	/*
4006	* Load MMIO registers.
4007	*/
4008	{
4009	/* Group count. */
4010	uint32_t cRegGroups;
4011	pHlp->pfnSSMGetU32(pSSM, &cRegGroups);
4012	AssertLogRelMsgReturn(cRegGroups == DMAR_MMIO_GROUP_COUNT,
4013	("%s: MMIO group count mismatch (expected %u got %u)\n", DMAR_LOG_PFX, DMAR_MMIO_GROUP_COUNT,
4014	cRegGroups), rcFmtErr);
4015
4016	/* Group 0. */
4017	uint32_t cbRegs0;
4018	pHlp->pfnSSMGetU32(pSSM, &cbRegs0);
4019	AssertLogRelMsgReturn(cbRegs0 == sizeof(pThis->abRegs0),
4020	("%s: MMIO group 0 size mismatch (expected %u got %u)\n", DMAR_LOG_PFX, sizeof(pThis->abRegs0),
4021	cbRegs0), rcFmtErr);
4022	pHlp->pfnSSMGetMem(pSSM, &pThis->abRegs0[0], cbRegs0);
4023
4024	/* Group 1. */
4025	uint32_t cbRegs1;
4026	pHlp->pfnSSMGetU32(pSSM, &cbRegs1);
4027	AssertLogRelMsgReturn(cbRegs1 == sizeof(pThis->abRegs1),
4028	("%s: MMIO group 1 size mismatch (expected %u got %u)\n", DMAR_LOG_PFX, sizeof(pThis->abRegs1),
4029	cbRegs1), rcFmtErr);
4030	pHlp->pfnSSMGetMem(pSSM, &pThis->abRegs1[0], cbRegs1);
4031	}
4032
4033	/*
4034	* Load lazily activated registers.
4035	*/
4036	{
4037	/* Active IRTA_REG. */
4038	pHlp->pfnSSMGetU64(pSSM, &pThis->uIrtaReg);
4039	AssertLogRelMsgReturn(!(pThis->uIrtaReg & ~VTD_IRTA_REG_RW_MASK),
4040	("%s: IRTA_REG reserved bits set %#RX64\n", DMAR_LOG_PFX, pThis->uIrtaReg), rcDataErr);
4041
4042	/* Active RTADDR_REG. */
4043	pHlp->pfnSSMGetU64(pSSM, &pThis->uRtaddrReg);
4044	AssertLogRelMsgReturn(!(pThis->uRtaddrReg & ~VTD_RTADDR_REG_RW_MASK),
4045	("%s: RTADDR_REG reserved bits set %#RX64\n", DMAR_LOG_PFX, pThis->uRtaddrReg), rcDataErr);
4046	}
4047
4048	/*
4049	* Verify terminator marker.
4050	*/
4051	{
4052	uint32_t uEndMarker;
4053	int const rc = pHlp->pfnSSMGetU32(pSSM, &uEndMarker);
4054	AssertRCReturn(rc, rc);
4055	AssertLogRelMsgReturn(uEndMarker == UINT32_MAX,
4056	("%s: End marker mismatch (expected %#RX32 got %#RX32)\n", DMAR_LOG_PFX, UINT32_MAX, uEndMarker),
4057	rcFmtErr);
4058	}
4059	return VINF_SUCCESS;
4060	}
4061
4062
4063	/**
4064	* @callback_method_impl{FNSSMDEVLOADDONE}
4065	*/
4066	static DECLCALLBACK(int) dmarR3LoadDone(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
4067	{
4068	PDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PDMARR3);
4069	LogFlowFunc(("\n"));
4070	RT_NOREF(pSSM);
4071	AssertPtrReturn(pThisR3, VERR_INVALID_POINTER);
4072
4073	DMAR_LOCK(pDevIns, pThisR3);
4074	dmarInvQueueThreadWakeUpIfNeeded(pDevIns);
4075	DMAR_UNLOCK(pDevIns, pThisR3);
4076	return VINF_SUCCESS;
4077	}
4078
4079
4080	/**
4081	* @interface_method_impl{PDMDEVREG,pfnReset}
4082	*/
4083	static DECLCALLBACK(void) iommuIntelR3Reset(PPDMDEVINS pDevIns)
4084	{
4085	PCDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARR3);
4086	LogFlowFunc(("\n"));
4087
4088	DMAR_LOCK(pDevIns, pThisR3);
4089	dmarR3RegsInit(pDevIns);
4090	DMAR_UNLOCK(pDevIns, pThisR3);
4091	}
4092
4093
4094	/**
4095	* @interface_method_impl{PDMDEVREG,pfnDestruct}
4096	*/
4097	static DECLCALLBACK(int) iommuIntelR3Destruct(PPDMDEVINS pDevIns)
4098	{
4099	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
4100	PCDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARR3);
4101	LogFlowFunc(("\n"));
4102
4103	DMAR_LOCK(pDevIns, pThisR3);
4104
4105	if (pThis->hEvtInvQueue != NIL_SUPSEMEVENT)
4106	{
4107	PDMDevHlpSUPSemEventClose(pDevIns, pThis->hEvtInvQueue);
4108	pThis->hEvtInvQueue = NIL_SUPSEMEVENT;
4109	}
4110
4111	DMAR_UNLOCK(pDevIns, pThisR3);
4112	return VINF_SUCCESS;
4113	}
4114
4115
4116	/**
4117	* @interface_method_impl{PDMDEVREG,pfnConstruct}
4118	*/
4119	static DECLCALLBACK(int) iommuIntelR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
4120	{
4121	RT_NOREF(pCfg);
4122
4123	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
4124	PDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PDMARR3);
4125	pThisR3->pDevInsR3 = pDevIns;
4126
4127	LogFlowFunc(("iInstance=%d\n", iInstance));
4128	NOREF(iInstance);
4129
4130	/*
4131	* Register the IOMMU with PDM.
4132	*/
4133	PDMIOMMUREGR3 IommuReg;
4134	RT_ZERO(IommuReg);
4135	IommuReg.u32Version = PDM_IOMMUREGCC_VERSION;
4136	IommuReg.pfnMemAccess = iommuIntelMemAccess;
4137	IommuReg.pfnMemBulkAccess = iommuIntelMemBulkAccess;
4138	IommuReg.pfnMsiRemap = iommuIntelMsiRemap;
4139	IommuReg.u32TheEnd = PDM_IOMMUREGCC_VERSION;
4140	int rc = PDMDevHlpIommuRegister(pDevIns, &IommuReg, &pThisR3->CTX_SUFF(pIommuHlp), &pThis->idxIommu);
4141	if (RT_FAILURE(rc))
4142	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to register ourselves as an IOMMU device"));
4143	if (pThisR3->CTX_SUFF(pIommuHlp)->u32Version != PDM_IOMMUHLPR3_VERSION)
4144	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
4145	N_("IOMMU helper version mismatch; got %#x expected %#x"),
4146	pThisR3->CTX_SUFF(pIommuHlp)->u32Version, PDM_IOMMUHLPR3_VERSION);
4147	if (pThisR3->CTX_SUFF(pIommuHlp)->u32TheEnd != PDM_IOMMUHLPR3_VERSION)
4148	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
4149	N_("IOMMU helper end-version mismatch; got %#x expected %#x"),
4150	pThisR3->CTX_SUFF(pIommuHlp)->u32TheEnd, PDM_IOMMUHLPR3_VERSION);
4151	AssertPtr(pThisR3->pIommuHlpR3->pfnLock);
4152	AssertPtr(pThisR3->pIommuHlpR3->pfnUnlock);
4153	AssertPtr(pThisR3->pIommuHlpR3->pfnLockIsOwner);
4154	AssertPtr(pThisR3->pIommuHlpR3->pfnSendMsi);
4155
4156	/*
4157	* Use PDM's critical section (via helpers) for the IOMMU device.
4158	*/
4159	rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
4160	AssertRCReturn(rc, rc);
4161
4162	/*
4163	* Initialize PCI configuration registers.
4164	*/
4165	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
4166	PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
4167
4168	/* Header. */
4169	PDMPciDevSetVendorId(pPciDev, DMAR_PCI_VENDOR_ID); /* Intel */
4170	PDMPciDevSetDeviceId(pPciDev, DMAR_PCI_DEVICE_ID); /* VirtualBox DMAR device */
4171	PDMPciDevSetRevisionId(pPciDev, DMAR_PCI_REVISION_ID); /* VirtualBox specific device implementation revision */
4172	PDMPciDevSetClassBase(pPciDev, VBOX_PCI_CLASS_SYSTEM); /* System Base Peripheral */
4173	PDMPciDevSetClassSub(pPciDev, VBOX_PCI_SUB_SYSTEM_OTHER); /* Other */
4174	PDMPciDevSetHeaderType(pPciDev, 0); /* Single function, type 0 */
4175	PDMPciDevSetSubSystemId(pPciDev, DMAR_PCI_DEVICE_ID); /* VirtualBox DMAR device */
4176	PDMPciDevSetSubSystemVendorId(pPciDev, DMAR_PCI_VENDOR_ID); /* Intel */
4177
4178	/** @todo Chipset spec says PCI Express Capability Id. Relevant for us? */
4179	PDMPciDevSetStatus(pPciDev, 0);
4180	PDMPciDevSetCapabilityList(pPciDev, 0);
4181	/** @todo VTBAR at 0x180? */
4182
4183	/*
4184	* Register the PCI function with PDM.
4185	*/
4186	rc = PDMDevHlpPCIRegister(pDevIns, pPciDev);
4187	AssertLogRelRCReturn(rc, rc);
4188
4189	/*
4190	* Register MMIO region.
4191	*/
4192	AssertCompile(!(DMAR_MMIO_BASE_PHYSADDR & X86_PAGE_4K_OFFSET_MASK));
4193	rc = PDMDevHlpMmioCreateAndMap(pDevIns, DMAR_MMIO_BASE_PHYSADDR, DMAR_MMIO_SIZE, dmarMmioWrite, dmarMmioRead,
4194	IOMMMIO_FLAGS_READ_DWORD_QWORD \| IOMMMIO_FLAGS_WRITE_DWORD_QWORD_ZEROED, "Intel-IOMMU",
4195	&pThis->hMmio);
4196	AssertLogRelRCReturn(rc, rc);
4197
4198	/*
4199	* Register saved state handlers.
4200	*/
4201	rc = PDMDevHlpSSMRegisterEx(pDevIns, DMAR_SAVED_STATE_VERSION, sizeof(DMAR), NULL /* pszBefore */,
4202	NULL /* pfnLivePrep /, NULL / pfnLiveExec /, NULL / pfnLiveVote */,
4203	NULL /* pfnSavePrep /, dmarR3SaveExec, NULL / pfnSaveDone */,
4204	NULL /* pfnLoadPrep */, dmarR3LoadExec, dmarR3LoadDone);
4205	AssertLogRelRCReturn(rc, rc);
4206
4207	/*
4208	* Register debugger info items.
4209	*/
4210	rc = PDMDevHlpDBGFInfoRegister(pDevIns, "iommu", "Display IOMMU state.", dmarR3DbgInfo);
4211	AssertLogRelRCReturn(rc, rc);
4212
4213	#ifdef VBOX_WITH_STATISTICS
4214	/*
4215	* Statistics.
4216	*/
4217	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadR3, STAMTYPE_COUNTER, "R3/MmioRead", STAMUNIT_OCCURENCES, "Number of MMIO reads in R3");
4218	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadRZ, STAMTYPE_COUNTER, "RZ/MmioRead", STAMUNIT_OCCURENCES, "Number of MMIO reads in RZ.");
4219
4220	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteR3, STAMTYPE_COUNTER, "R3/MmioWrite", STAMUNIT_OCCURENCES, "Number of MMIO writes in R3.");
4221	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteRZ, STAMTYPE_COUNTER, "RZ/MmioWrite", STAMUNIT_OCCURENCES, "Number of MMIO writes in RZ.");
4222
4223	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapCfiR3, STAMTYPE_COUNTER, "R3/MsiRemapCfi", STAMUNIT_OCCURENCES, "Number of compatibility-format interrupt remap requests in R3.");
4224	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapCfiRZ, STAMTYPE_COUNTER, "RZ/MsiRemapCfi", STAMUNIT_OCCURENCES, "Number of compatibility-format interrupt remap requests in RZ.");
4225	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapRfiR3, STAMTYPE_COUNTER, "R3/MsiRemapRfi", STAMUNIT_OCCURENCES, "Number of remappable-format interrupt remap requests in R3.");
4226	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapRfiRZ, STAMTYPE_COUNTER, "RZ/MsiRemapRfi", STAMUNIT_OCCURENCES, "Number of remappable-format interrupt remap requests in RZ.");
4227
4228	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemReadR3, STAMTYPE_COUNTER, "R3/MemRead", STAMUNIT_OCCURENCES, "Number of memory read translation requests in R3.");
4229	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemReadRZ, STAMTYPE_COUNTER, "RZ/MemRead", STAMUNIT_OCCURENCES, "Number of memory read translation requests in RZ.");
4230
4231	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemWriteR3, STAMTYPE_COUNTER, "R3/MemWrite", STAMUNIT_OCCURENCES, "Number of memory write translation requests in R3.");
4232	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemWriteRZ, STAMTYPE_COUNTER, "RZ/MemWrite", STAMUNIT_OCCURENCES, "Number of memory write translation requests in RZ.");
4233
4234	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkReadR3, STAMTYPE_COUNTER, "R3/MemBulkRead", STAMUNIT_OCCURENCES, "Number of memory bulk read translation requests in R3.");
4235	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkReadRZ, STAMTYPE_COUNTER, "RZ/MemBulkRead", STAMUNIT_OCCURENCES, "Number of memory bulk read translation requests in RZ.");
4236
4237	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkWriteR3, STAMTYPE_COUNTER, "R3/MemBulkWrite", STAMUNIT_OCCURENCES, "Number of memory bulk write translation requests in R3.");
4238	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkWriteRZ, STAMTYPE_COUNTER, "RZ/MemBulkWrite", STAMUNIT_OCCURENCES, "Number of memory bulk write translation requests in RZ.");
4239
4240	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCcInvDsc, STAMTYPE_COUNTER, "R3/QI/CcInv", STAMUNIT_OCCURENCES, "Number of cc_inv_dsc processed.");
4241	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIotlbInvDsc, STAMTYPE_COUNTER, "R3/QI/IotlbInv", STAMUNIT_OCCURENCES, "Number of iotlb_inv_dsc processed.");
4242	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatDevtlbInvDsc, STAMTYPE_COUNTER, "R3/QI/DevtlbInv", STAMUNIT_OCCURENCES, "Number of dev_tlb_inv_dsc processed.");
4243	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIecInvDsc, STAMTYPE_COUNTER, "R3/QI/IecInv", STAMUNIT_OCCURENCES, "Number of iec_inv processed.");
4244	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatInvWaitDsc, STAMTYPE_COUNTER, "R3/QI/InvWait", STAMUNIT_OCCURENCES, "Number of inv_wait_dsc processed.");
4245	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatPasidIotlbInvDsc, STAMTYPE_COUNTER, "R3/QI/PasidIotlbInv", STAMUNIT_OCCURENCES, "Number of p_iotlb_inv_dsc processed.");
4246	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatPasidCacheInvDsc, STAMTYPE_COUNTER, "R3/QI/PasidCacheInv", STAMUNIT_OCCURENCES, "Number of pc_inv_dsc pprocessed.");
4247	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatPasidDevtlbInvDsc, STAMTYPE_COUNTER, "R3/QI/PasidDevtlbInv", STAMUNIT_OCCURENCES, "Number of p_dev_tlb_inv_dsc processed.");
4248	#endif
4249
4250	/*
4251	* Initialize registers.
4252	*/
4253	dmarR3RegsInit(pDevIns);
4254
4255	/*
4256	* Create invalidation-queue thread and semaphore.
4257	*/
4258	char szInvQueueThread[32];
4259	RT_ZERO(szInvQueueThread);
4260	RTStrPrintf(szInvQueueThread, sizeof(szInvQueueThread), "IOMMU-QI-%u", iInstance);
4261	rc = PDMDevHlpThreadCreate(pDevIns, &pThisR3->pInvQueueThread, pThis, dmarR3InvQueueThread, dmarR3InvQueueThreadWakeUp,
4262	0 /* cbStack */, RTTHREADTYPE_IO, szInvQueueThread);
4263	AssertLogRelRCReturn(rc, rc);
4264
4265	rc = PDMDevHlpSUPSemEventCreate(pDevIns, &pThis->hEvtInvQueue);
4266	AssertLogRelRCReturn(rc, rc);
4267
4268	/*
4269	* Log some of the features exposed to software.
4270	*/
4271	uint8_t const uVerMax = RT_BF_GET(pThis->uVerReg, VTD_BF_VER_REG_MAX);
4272	uint8_t const uVerMin = RT_BF_GET(pThis->uVerReg, VTD_BF_VER_REG_MIN);
4273	uint8_t const cMgawBits = RT_BF_GET(pThis->fCapReg, VTD_BF_CAP_REG_MGAW) + 1;
4274	uint8_t const fSagaw = RT_BF_GET(pThis->fCapReg, VTD_BF_CAP_REG_SAGAW);
4275	uint16_t const offFrcd = RT_BF_GET(pThis->fCapReg, VTD_BF_CAP_REG_FRO);
4276	uint16_t const offIva = RT_BF_GET(pThis->fExtCapReg, VTD_BF_ECAP_REG_IRO);
4277	LogRel(("%s: Mapped at %#RGp (%u-level page-table supported)\n",
4278	DMAR_LOG_PFX, DMAR_MMIO_BASE_PHYSADDR, pThis->cMaxPagingLevel));
4279	LogRel(("%s: Version=%u.%u Cap=%#RX64 ExtCap=%#RX64 Mgaw=%u bits Sagaw=%#x HawBaseMask=%#RX64 MgawInvMask=%#RX64 FRO=%#x IRO=%#x\n",
4280	DMAR_LOG_PFX, uVerMax, uVerMin, pThis->fCapReg, pThis->fExtCapReg, cMgawBits, fSagaw, pThis->fHawBaseMask,
4281	pThis->fMgawInvMask, offFrcd, offIva));
4282	return VINF_SUCCESS;
4283	}
4284
4285	#else
4286
4287	/**
4288	* @callback_method_impl{PDMDEVREGR0,pfnConstruct}
4289	*/
4290	static DECLCALLBACK(int) iommuIntelRZConstruct(PPDMDEVINS pDevIns)
4291	{
4292	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
4293	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
4294	PDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PDMARCC);
4295	pThisCC->CTX_SUFF(pDevIns) = pDevIns;
4296
4297	/* We will use PDM's critical section (via helpers) for the IOMMU device. */
4298	int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
4299	AssertRCReturn(rc, rc);
4300
4301	/* Set up the MMIO RZ handlers. */
4302	rc = PDMDevHlpMmioSetUpContext(pDevIns, pThis->hMmio, dmarMmioWrite, dmarMmioRead, NULL /* pvUser */);
4303	AssertRCReturn(rc, rc);
4304
4305	/* Set up the IOMMU RZ callbacks. */
4306	PDMIOMMUREGCC IommuReg;
4307	RT_ZERO(IommuReg);
4308	IommuReg.u32Version = PDM_IOMMUREGCC_VERSION;
4309	IommuReg.idxIommu = pThis->idxIommu;
4310	IommuReg.pfnMemAccess = iommuIntelMemAccess;
4311	IommuReg.pfnMemBulkAccess = iommuIntelMemBulkAccess;
4312	IommuReg.pfnMsiRemap = iommuIntelMsiRemap;
4313	IommuReg.u32TheEnd = PDM_IOMMUREGCC_VERSION;
4314
4315	rc = PDMDevHlpIommuSetUpContext(pDevIns, &IommuReg, &pThisCC->CTX_SUFF(pIommuHlp));
4316	AssertRCReturn(rc, rc);
4317	AssertPtrReturn(pThisCC->CTX_SUFF(pIommuHlp), VERR_IOMMU_IPE_1);
4318	AssertReturn(pThisCC->CTX_SUFF(pIommuHlp)->u32Version == CTX_MID(PDM_IOMMUHLP,_VERSION), VERR_VERSION_MISMATCH);
4319	AssertReturn(pThisCC->CTX_SUFF(pIommuHlp)->u32TheEnd == CTX_MID(PDM_IOMMUHLP,_VERSION), VERR_VERSION_MISMATCH);
4320	AssertPtr(pThisCC->CTX_SUFF(pIommuHlp)->pfnLock);
4321	AssertPtr(pThisCC->CTX_SUFF(pIommuHlp)->pfnUnlock);
4322	AssertPtr(pThisCC->CTX_SUFF(pIommuHlp)->pfnLockIsOwner);
4323	AssertPtr(pThisCC->CTX_SUFF(pIommuHlp)->pfnSendMsi);
4324
4325	return VINF_SUCCESS;
4326	}
4327
4328	#endif
4329
4330
4331	/**
4332	* The device registration structure.
4333	*/
4334	PDMDEVREG const g_DeviceIommuIntel =
4335	{
4336	/* .u32Version = */ PDM_DEVREG_VERSION,
4337	/* .uReserved0 = */ 0,
4338	/* .szName = */ "iommu-intel",
4339	/* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RZ \| PDM_DEVREG_FLAGS_NEW_STYLE,
4340	/* .fClass = */ PDM_DEVREG_CLASS_PCI_BUILTIN,
4341	/* .cMaxInstances = */ 1,
4342	/* .uSharedVersion = */ 42,
4343	/* .cbInstanceShared = */ sizeof(DMAR),
4344	/* .cbInstanceCC = */ sizeof(DMARCC),
4345	/* .cbInstanceRC = */ sizeof(DMARRC),
4346	/* .cMaxPciDevices = */ 1,
4347	/* .cMaxMsixVectors = */ 0,
4348	/* .pszDescription = */ "IOMMU (Intel)",
4349	#if defined(IN_RING3)
4350	/* .pszRCMod = */ "VBoxDDRC.rc",
4351	/* .pszR0Mod = */ "VBoxDDR0.r0",
4352	/* .pfnConstruct = */ iommuIntelR3Construct,
4353	/* .pfnDestruct = */ iommuIntelR3Destruct,
4354	/* .pfnRelocate = */ NULL,
4355	/* .pfnMemSetup = */ NULL,
4356	/* .pfnPowerOn = */ NULL,
4357	/* .pfnReset = */ iommuIntelR3Reset,
4358	/* .pfnSuspend = */ NULL,
4359	/* .pfnResume = */ NULL,
4360	/* .pfnAttach = */ NULL,
4361	/* .pfnDetach = */ NULL,
4362	/* .pfnQueryInterface = */ NULL,
4363	/* .pfnInitComplete = */ NULL,
4364	/* .pfnPowerOff = */ NULL,
4365	/* .pfnSoftReset = */ NULL,
4366	/* .pfnReserved0 = */ NULL,
4367	/* .pfnReserved1 = */ NULL,
4368	/* .pfnReserved2 = */ NULL,
4369	/* .pfnReserved3 = */ NULL,
4370	/* .pfnReserved4 = */ NULL,
4371	/* .pfnReserved5 = */ NULL,
4372	/* .pfnReserved6 = */ NULL,
4373	/* .pfnReserved7 = */ NULL,
4374	#elif defined(IN_RING0)
4375	/* .pfnEarlyConstruct = */ NULL,
4376	/* .pfnConstruct = */ iommuIntelRZConstruct,
4377	/* .pfnDestruct = */ NULL,
4378	/* .pfnFinalDestruct = */ NULL,
4379	/* .pfnRequest = */ NULL,
4380	/* .pfnReserved0 = */ NULL,
4381	/* .pfnReserved1 = */ NULL,
4382	/* .pfnReserved2 = */ NULL,
4383	/* .pfnReserved3 = */ NULL,
4384	/* .pfnReserved4 = */ NULL,
4385	/* .pfnReserved5 = */ NULL,
4386	/* .pfnReserved6 = */ NULL,
4387	/* .pfnReserved7 = */ NULL,
4388	#elif defined(IN_RC)
4389	/* .pfnConstruct = */ iommuIntelRZConstruct,
4390	/* .pfnReserved0 = */ NULL,
4391	/* .pfnReserved1 = */ NULL,
4392	/* .pfnReserved2 = */ NULL,
4393	/* .pfnReserved3 = */ NULL,
4394	/* .pfnReserved4 = */ NULL,
4395	/* .pfnReserved5 = */ NULL,
4396	/* .pfnReserved6 = */ NULL,
4397	/* .pfnReserved7 = */ NULL,
4398	#else
4399	# error "Not in IN_RING3, IN_RING0 or IN_RC!"
4400	#endif
4401	/* .u32VersionEnd = */ PDM_DEVREG_VERSION
4402	};
4403
4404	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
4405

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source: vbox/trunk/src/VBox/Devices/Bus/DevIommuIntel.cpp@ 89578

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