DevIommuIntel.cpp@ 89729

Last change on this file since 89729 was 89729, checked in by vboxsync, 3 years ago
Intel IOMMU: bugref:9967 Build fix for gcc.
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1	/* $Id: DevIommuIntel.cpp 89729 2021-06-16 05:57:51Z vboxsync $ */
2	/** @file
3	* IOMMU - Input/Output Memory Management Unit - Intel implementation.
4	*/
5
6	/*
7	* Copyright (C) 2021 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_DEV_IOMMU
23	#include "VBoxDD.h"
24	#include "DevIommuIntel.h"
25
26	#include <VBox/iommu-intel.h>
27	#include <iprt/mem.h>
28	#include <iprt/string.h>
29
30
31	/*********************************************************************************************************************************
32	* Defined Constants And Macros *
33	*********************************************************************************************************************************/
34	/** Gets the low uint32_t of a uint64_t or something equivalent.
35	*
36	* This is suitable for casting constants outside code (since RT_LO_U32 can't be
37	* used as it asserts for correctness when compiling on certain compilers). */
38	#define DMAR_LO_U32(a) (uint32_t)(UINT32_MAX & (a))
39
40	/** Gets the high uint32_t of a uint64_t or something equivalent.
41	*
42	* This is suitable for casting constants outside code (since RT_HI_U32 can't be
43	* used as it asserts for correctness when compiling on certain compilers). */
44	#define DMAR_HI_U32(a) (uint32_t)((a) >> 32)
45
46	/** Asserts MMIO access' offset and size are valid or returns appropriate error
47	* code suitable for returning from MMIO access handlers. */
48	#define DMAR_ASSERT_MMIO_ACCESS_RET(a_off, a_cb) \
49	do { \
50	AssertReturn((a_cb) == 4 \|\| (a_cb) == 8, VINF_IOM_MMIO_UNUSED_FF); \
51	AssertReturn(!((a_off) & ((a_cb) - 1)), VINF_IOM_MMIO_UNUSED_FF); \
52	} while (0)
53
54	/** Checks if the MMIO offset is valid. */
55	#define DMAR_IS_MMIO_OFF_VALID(a_off) ( (a_off) < DMAR_MMIO_GROUP_0_OFF_END \
56	\|\| (a_off) - DMAR_MMIO_GROUP_1_OFF_FIRST < (unsigned)DMAR_MMIO_GROUP_1_SIZE)
57
58	/** Acquires the DMAR lock but returns with the given busy error code on failure. */
59	#define DMAR_LOCK_RET(a_pDevIns, a_pThisCC, a_rcBusy) \
60	do { \
61	if ((a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLock((a_pDevIns), (a_rcBusy)) == VINF_SUCCESS) \
62	{ /* likely */ } \
63	else \
64	return (a_rcBusy); \
65	} while (0)
66
67	/** Acquires the DMAR lock (not expected to fail). */
68	#ifdef IN_RING3
69	# define DMAR_LOCK(a_pDevIns, a_pThisCC) (a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLock((a_pDevIns), VERR_IGNORED)
70	#else
71	# define DMAR_LOCK(a_pDevIns, a_pThisCC) \
72	do { \
73	int const rcLock = (a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLock((a_pDevIns), VINF_SUCCESS); \
74	AssertRC(rcLock); \
75	} while (0)
76	#endif
77
78	/** Release the DMAR lock. */
79	#define DMAR_UNLOCK(a_pDevIns, a_pThisCC) (a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnUnlock(a_pDevIns)
80
81	/** Asserts that the calling thread owns the DMAR lock. */
82	#define DMAR_ASSERT_LOCK_IS_OWNER(a_pDevIns, a_pThisCC) \
83	do { \
84	Assert((a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLockIsOwner(a_pDevIns)); \
85	RT_NOREF1(a_pThisCC); \
86	} while (0)
87
88	/** Asserts that the calling thread does not own the DMAR lock. */
89	#define DMAR_ASSERT_LOCK_IS_NOT_OWNER(a_pDevIns, a_pThisCC) \
90	do { \
91	Assert((a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLockIsOwner(a_pDevIns) == false); \
92	RT_NOREF1(a_pThisCC); \
93	} while (0)
94
95	/** The number of fault recording registers our implementation supports.
96	* Normal guest operation shouldn't trigger faults anyway, so we only support the
97	* minimum number of registers (which is 1).
98	*
99	* See Intel VT-d spec. 10.4.2 "Capability Register" (CAP_REG.NFR). */
100	#define DMAR_FRCD_REG_COUNT UINT32_C(1)
101
102	/** Number of register groups (used in saved states). */
103	#define DMAR_MMIO_GROUP_COUNT 2
104	/** Offset of first register in group 0. */
105	#define DMAR_MMIO_GROUP_0_OFF_FIRST VTD_MMIO_OFF_VER_REG
106	/** Offset of last register in group 0 (inclusive). */
107	#define DMAR_MMIO_GROUP_0_OFF_LAST VTD_MMIO_OFF_MTRR_PHYSMASK9_REG
108	/** Last valid offset in group 0 (exclusive). */
109	#define DMAR_MMIO_GROUP_0_OFF_END (DMAR_MMIO_GROUP_0_OFF_LAST + 8 /* sizeof MTRR_PHYSMASK9_REG */)
110	/** Size of the group 0 (in bytes). */
111	#define DMAR_MMIO_GROUP_0_SIZE (DMAR_MMIO_GROUP_0_OFF_END - DMAR_MMIO_GROUP_0_OFF_FIRST)
112	/** Number of implementation-defined MMIO register offsets - IVA_REG and
113	* FRCD_LO_REG (used in saved state). IOTLB_REG and FRCD_HI_REG are derived from
114	* IVA_REG and FRCD_LO_REG respectively */
115	#define DMAR_MMIO_OFF_IMPL_COUNT 2
116	/** Implementation-specific MMIO offset of IVA_REG (used in saved state). */
117	#define DMAR_MMIO_OFF_IVA_REG 0xe50
118	/** Implementation-specific MMIO offset of IOTLB_REG. */
119	#define DMAR_MMIO_OFF_IOTLB_REG 0xe58
120	/** Implementation-specific MMIO offset of FRCD_LO_REG (used in saved state). */
121	#define DMAR_MMIO_OFF_FRCD_LO_REG 0xe70
122	/** Implementation-specific MMIO offset of FRCD_HI_REG. */
123	#define DMAR_MMIO_OFF_FRCD_HI_REG 0xe78
124	AssertCompile(!(DMAR_MMIO_OFF_FRCD_LO_REG & 0xf));
125	AssertCompile(DMAR_MMIO_OFF_IOTLB_REG == DMAR_MMIO_OFF_IVA_REG + 8);
126	AssertCompile(DMAR_MMIO_OFF_FRCD_HI_REG == DMAR_MMIO_OFF_FRCD_LO_REG + 8);
127
128	/** Offset of first register in group 1. */
129	#define DMAR_MMIO_GROUP_1_OFF_FIRST VTD_MMIO_OFF_VCCAP_REG
130	/** Offset of last register in group 1 (inclusive). */
131	#define DMAR_MMIO_GROUP_1_OFF_LAST (DMAR_MMIO_OFF_FRCD_LO_REG + 8) * DMAR_FRCD_REG_COUNT
132	/** Last valid offset in group 1 (exclusive). */
133	#define DMAR_MMIO_GROUP_1_OFF_END (DMAR_MMIO_GROUP_1_OFF_LAST + 8 /* sizeof FRCD_HI_REG */)
134	/** Size of the group 1 (in bytes). */
135	#define DMAR_MMIO_GROUP_1_SIZE (DMAR_MMIO_GROUP_1_OFF_END - DMAR_MMIO_GROUP_1_OFF_FIRST)
136
137	/** DMAR implementation's major version number (exposed to software).
138	* We report 6 as the major version since we support queued-invalidations as
139	* software may make assumptions based on that.
140	*
141	* See Intel VT-d spec. 10.4.7 "Context Command Register" (CCMD_REG.CAIG). */
142	#define DMAR_VER_MAJOR 6
143	/** DMAR implementation's minor version number (exposed to software). */
144	#define DMAR_VER_MINOR 0
145
146	/** Number of domain supported (0=16, 1=64, 2=256, 3=1K, 4=4K, 5=16K, 6=64K,
147	* 7=Reserved). */
148	#define DMAR_ND 6
149
150	/** @name DMAR_PERM_XXX: DMA request permissions.
151	* The order of R, W, X bits is important as it corresponds to those bits in
152	* page-table entries.
153	*
154	* @{ */
155	/** DMA request permission: Read. */
156	#define DMAR_PERM_READ RT_BIT(0)
157	/** DMA request permission: Write. */
158	#define DMAR_PERM_WRITE RT_BIT(1)
159	/** DMA request permission: Execute (ER). */
160	#define DMAR_PERM_EXE RT_BIT(2)
161	/** DMA request permission: Supervisor privilege (PR). */
162	#define DMAR_PERM_PRIV RT_BIT(3)
163	/** DMA request permissions: All. */
164	#define DMAR_PERM_ALL (DMAR_PERM_READ \| DMAR_PERM_WRITE \| DMAR_PERM_EXE \| DMAR_PERM_PRIV)
165	/** @} */
166
167	/** Release log prefix string. */
168	#define DMAR_LOG_PFX "Intel-IOMMU"
169	/** The current saved state version. */
170	#define DMAR_SAVED_STATE_VERSION 1
171
172
173	/*********************************************************************************************************************************
174	* Structures and Typedefs *
175	*********************************************************************************************************************************/
176	/**
177	* DMAR error diagnostics.
178	* Sorted alphabetically so it's easier to add and locate items, no other reason.
179	*
180	* @note Members of this enum are used as array indices, so no gaps in enum
181	* values are not allowed. Update g_apszDmarDiagDesc when you modify
182	* fields in this enum.
183	*/
184	typedef enum
185	{
186	/* No error, this must be zero! */
187	kDmarDiag_None = 0,
188
189	/* Address Translation Faults. */
190	kDmarDiag_At_Lm_CtxEntry_Not_Present,
191	kDmarDiag_At_Lm_CtxEntry_Read_Failed,
192	kDmarDiag_At_Lm_CtxEntry_Rsvd,
193	kDmarDiag_At_Lm_Pt_At_Block,
194	kDmarDiag_At_Lm_Pt_Aw_Invalid,
195	kDmarDiag_At_Lm_RootEntry_Not_Present,
196	kDmarDiag_At_Lm_RootEntry_Read_Failed,
197	kDmarDiag_At_Lm_RootEntry_Rsvd,
198	kDmarDiag_At_Lm_Tt_Invalid,
199	kDmarDiag_At_Lm_Ut_At_Block,
200	kDmarDiag_At_Lm_Ut_Aw_Invalid,
201	kDmarDiag_At_Rta_Adms_Not_Supported,
202	kDmarDiag_At_Rta_Rsvd,
203	kDmarDiag_At_Rta_Smts_Not_Supported,
204	kDmarDiag_At_Xm_AddrIn_Invalid,
205	kDmarDiag_At_Xm_AddrOut_Invalid,
206	kDmarDiag_At_Xm_Perm_Denied,
207	kDmarDiag_At_Xm_Pte_Rsvd,
208	kDmarDiag_At_Xm_Pte_Sllps_Invalid,
209	kDmarDiag_At_Xm_Read_Pte_Failed,
210	kDmarDiag_At_Xm_Slpptr_Read_Failed,
211
212	/* CCMD_REG faults. */
213	kDmarDiag_CcmdReg_Not_Supported,
214	kDmarDiag_CcmdReg_Qi_Enabled,
215	kDmarDiag_CcmdReg_Ttm_Invalid,
216
217	/* IQA_REG faults. */
218	kDmarDiag_IqaReg_Dsc_Fetch_Error,
219	kDmarDiag_IqaReg_Dw_128_Invalid,
220	kDmarDiag_IqaReg_Dw_256_Invalid,
221
222	/* Invalidation Queue Error Info. */
223	kDmarDiag_Iqei_Dsc_Type_Invalid,
224	kDmarDiag_Iqei_Inv_Wait_Dsc_0_1_Rsvd,
225	kDmarDiag_Iqei_Inv_Wait_Dsc_2_3_Rsvd,
226	kDmarDiag_Iqei_Inv_Wait_Dsc_Invalid,
227	kDmarDiag_Iqei_Ttm_Rsvd,
228
229	/* IQT_REG faults. */
230	kDmarDiag_IqtReg_Qt_Invalid,
231	kDmarDiag_IqtReg_Qt_Not_Aligned,
232
233	/* Interrupt Remapping Faults. */
234	kDmarDiag_Ir_Cfi_Blocked,
235	kDmarDiag_Ir_Rfi_Intr_Index_Invalid,
236	kDmarDiag_Ir_Rfi_Irte_Mode_Invalid,
237	kDmarDiag_Ir_Rfi_Irte_Not_Present,
238	kDmarDiag_Ir_Rfi_Irte_Read_Failed,
239	kDmarDiag_Ir_Rfi_Irte_Rsvd,
240	kDmarDiag_Ir_Rfi_Irte_Svt_Bus,
241	kDmarDiag_Ir_Rfi_Irte_Svt_Masked,
242	kDmarDiag_Ir_Rfi_Irte_Svt_Rsvd,
243	kDmarDiag_Ir_Rfi_Rsvd,
244
245	/* Member for determining array index limit. */
246	kDmarDiag_End,
247
248	/* Usual 32-bit type size hack. */
249	kDmarDiag_32Bit_Hack = 0x7fffffff
250	} DMARDIAG;
251	AssertCompileSize(DMARDIAG, 4);
252
253	/** DMAR diagnostic enum description expansion.
254	* The below construct ensures typos in the input to this macro are caught
255	* during compile time. */
256	#define DMARDIAG_DESC(a_Name) RT_CONCAT(kDmarDiag_, a_Name) < kDmarDiag_End ? RT_STR(a_Name) : "Ignored"
257
258	/** DMAR diagnostics description for members in DMARDIAG. */
259	static const char *const g_apszDmarDiagDesc[] =
260	{
261	DMARDIAG_DESC(None ),
262
263	/* Address Translation Faults. */
264	DMARDIAG_DESC(At_Lm_CtxEntry_Not_Present ),
265	DMARDIAG_DESC(At_Lm_CtxEntry_Read_Failed ),
266	DMARDIAG_DESC(At_Lm_CtxEntry_Rsvd ),
267	DMARDIAG_DESC(At_Lm_Pt_At_Block ),
268	DMARDIAG_DESC(At_Lm_Pt_Aw_Invalid ),
269	DMARDIAG_DESC(At_Lm_RootEntry_Not_Present),
270	DMARDIAG_DESC(At_Lm_RootEntry_Read_Failed),
271	DMARDIAG_DESC(At_Lm_RootEntry_Rsvd ),
272	DMARDIAG_DESC(At_Lm_Tt_Invalid ),
273	DMARDIAG_DESC(At_Lm_Ut_At_Block ),
274	DMARDIAG_DESC(At_Lm_Ut_Aw_Invalid ),
275	DMARDIAG_DESC(At_Rta_Adms_Not_Supported ),
276	DMARDIAG_DESC(At_Rta_Rsvd ),
277	DMARDIAG_DESC(At_Rta_Smts_Not_Supported ),
278	DMARDIAG_DESC(At_Xm_AddrIn_Invalid ),
279	DMARDIAG_DESC(At_Xm_AddrOut_Invalid ),
280	DMARDIAG_DESC(At_Xm_Perm_Denied ),
281	DMARDIAG_DESC(At_Xm_Pte_Rsvd ),
282	DMARDIAG_DESC(At_Xm_Pte_Sllps_Invalid ),
283	DMARDIAG_DESC(At_Xm_Read_Pte_Failed ),
284	DMARDIAG_DESC(At_Xm_Slpptr_Read_Failed ),
285
286	/* CCMD_REG faults. */
287	DMARDIAG_DESC(CcmdReg_Not_Supported ),
288	DMARDIAG_DESC(CcmdReg_Qi_Enabled ),
289	DMARDIAG_DESC(CcmdReg_Ttm_Invalid ),
290
291	/* IQA_REG faults. */
292	DMARDIAG_DESC(IqaReg_Dsc_Fetch_Error ),
293	DMARDIAG_DESC(IqaReg_Dw_128_Invalid ),
294	DMARDIAG_DESC(IqaReg_Dw_256_Invalid ),
295
296	/* Invalidation Queue Error Info. */
297	DMARDIAG_DESC(Iqei_Dsc_Type_Invalid ),
298	DMARDIAG_DESC(Iqei_Inv_Wait_Dsc_0_1_Rsvd ),
299	DMARDIAG_DESC(Iqei_Inv_Wait_Dsc_2_3_Rsvd ),
300	DMARDIAG_DESC(Iqei_Inv_Wait_Dsc_Invalid ),
301	DMARDIAG_DESC(Iqei_Ttm_Rsvd ),
302
303	/* IQT_REG faults. */
304	DMARDIAG_DESC(IqtReg_Qt_Invalid ),
305	DMARDIAG_DESC(IqtReg_Qt_Not_Aligned ),
306
307	/* Interrupt remapping faults. */
308	DMARDIAG_DESC(Ir_Cfi_Blocked ),
309	DMARDIAG_DESC(Ir_Rfi_Intr_Index_Invalid ),
310	DMARDIAG_DESC(Ir_Rfi_Irte_Mode_Invalid ),
311	DMARDIAG_DESC(Ir_Rfi_Irte_Not_Present ),
312	DMARDIAG_DESC(Ir_Rfi_Irte_Read_Failed ),
313	DMARDIAG_DESC(Ir_Rfi_Irte_Rsvd ),
314	DMARDIAG_DESC(Ir_Rfi_Irte_Svt_Bus ),
315	DMARDIAG_DESC(Ir_Rfi_Irte_Svt_Masked ),
316	DMARDIAG_DESC(Ir_Rfi_Irte_Svt_Rsvd ),
317	DMARDIAG_DESC(Ir_Rfi_Rsvd ),
318	/* kDmarDiag_End */
319	};
320	AssertCompile(RT_ELEMENTS(g_apszDmarDiagDesc) == kDmarDiag_End);
321	#undef DMARDIAG_DESC
322
323	/**
324	* The shared DMAR device state.
325	*/
326	typedef struct DMAR
327	{
328	/** IOMMU device index. */
329	uint32_t idxIommu;
330	/** Padding. */
331	uint32_t u32Padding0;
332
333	/** Registers (group 0). */
334	uint8_t abRegs0[DMAR_MMIO_GROUP_0_SIZE];
335	/** Registers (group 1). */
336	uint8_t abRegs1[DMAR_MMIO_GROUP_1_SIZE];
337
338	/** @name Lazily activated registers.
339	* These are the active values for lazily activated registers. Software is free to
340	* modify the actual register values while remapping/translation is enabled but they
341	* take effect only when explicitly signaled by software, hence we need to hold the
342	* active values separately.
343	* @{ */
344	/** Currently active IRTA_REG. */
345	uint64_t uIrtaReg;
346	/** Currently active RTADDR_REG. */
347	uint64_t uRtaddrReg;
348	/** @} */
349
350	/** @name Register copies for a tiny bit faster and more convenient access.
351	* @{ */
352	/** Copy of VER_REG. */
353	uint8_t uVerReg;
354	/** Alignment. */
355	uint8_t abPadding0[7];
356	/** Copy of CAP_REG. */
357	uint64_t fCapReg;
358	/** Copy of ECAP_REG. */
359	uint64_t fExtCapReg;
360	/** @} */
361
362	/** Host-address width (HAW) base address mask. */
363	uint64_t fHawBaseMask;
364	/** Maximum guest-address width (MGAW) invalid address mask. */
365	uint64_t fMgawInvMask;
366	/** Context-entry qword-1 valid mask. */
367	uint64_t fCtxEntryQw1ValidMask;
368	/** Maximum supported paging level (3, 4 or 5). */
369	uint8_t cMaxPagingLevel;
370	/** DMA request valid permissions mask. */
371	uint8_t fPermValidMask;
372	/** Alignment. */
373	uint8_t abPadding1[6];
374
375	/** The event semaphore the invalidation-queue thread waits on. */
376	SUPSEMEVENT hEvtInvQueue;
377	/** Error diagnostic. */
378	DMARDIAG enmDiag;
379	/** Padding. */
380	uint32_t uPadding0;
381	/** The MMIO handle. */
382	IOMMMIOHANDLE hMmio;
383
384	#ifdef VBOX_WITH_STATISTICS
385	STAMCOUNTER StatMmioReadR3; /*< Number of MMIO reads in R3. /
386	STAMCOUNTER StatMmioReadRZ; /*< Number of MMIO reads in RZ. /
387	STAMCOUNTER StatMmioWriteR3; /*< Number of MMIO writes in R3. /
388	STAMCOUNTER StatMmioWriteRZ; /*< Number of MMIO writes in RZ. /
389
390	STAMCOUNTER StatMsiRemapCfiR3; /*< Number of compatibility-format interrupts remap requests in R3. /
391	STAMCOUNTER StatMsiRemapCfiRZ; /*< Number of compatibility-format interrupts remap requests in RZ. /
392	STAMCOUNTER StatMsiRemapRfiR3; /*< Number of remappable-format interrupts remap requests in R3. /
393	STAMCOUNTER StatMsiRemapRfiRZ; /*< Number of remappable-format interrupts remap requests in RZ. /
394
395	STAMCOUNTER StatMemReadR3; /*< Number of memory read translation requests in R3. /
396	STAMCOUNTER StatMemReadRZ; /*< Number of memory read translation requests in RZ. /
397	STAMCOUNTER StatMemWriteR3; /*< Number of memory write translation requests in R3. /
398	STAMCOUNTER StatMemWriteRZ; /*< Number of memory write translation requests in RZ. /
399
400	STAMCOUNTER StatMemBulkReadR3; /*< Number of memory read bulk translation requests in R3. /
401	STAMCOUNTER StatMemBulkReadRZ; /*< Number of memory read bulk translation requests in RZ. /
402	STAMCOUNTER StatMemBulkWriteR3; /*< Number of memory write bulk translation requests in R3. /
403	STAMCOUNTER StatMemBulkWriteRZ; /*< Number of memory write bulk translation requests in RZ. /
404
405	STAMCOUNTER StatCcInvDsc; /*< Number of Context-cache descriptors processed. /
406	STAMCOUNTER StatIotlbInvDsc; /*< Number of IOTLB descriptors processed. /
407	STAMCOUNTER StatDevtlbInvDsc; /*< Number of Device-TLB descriptors processed. /
408	STAMCOUNTER StatIecInvDsc; /*< Number of Interrupt-Entry cache descriptors processed. /
409	STAMCOUNTER StatInvWaitDsc; /*< Number of Invalidation wait descriptors processed. /
410	STAMCOUNTER StatPasidIotlbInvDsc; /*< Number of PASID-based IOTLB descriptors processed. /
411	STAMCOUNTER StatPasidCacheInvDsc; /*< Number of PASID-cache descriptors processed. /
412	STAMCOUNTER StatPasidDevtlbInvDsc; /*< Number of PASID-based device-TLB descriptors processed. /
413	#endif
414	} DMAR;
415	/** Pointer to the DMAR device state. */
416	typedef DMAR *PDMAR;
417	/** Pointer to the const DMAR device state. */
418	typedef DMAR const *PCDMAR;
419	AssertCompileMemberAlignment(DMAR, abRegs0, 8);
420	AssertCompileMemberAlignment(DMAR, abRegs1, 8);
421
422	/**
423	* The ring-3 DMAR device state.
424	*/
425	typedef struct DMARR3
426	{
427	/** Device instance. */
428	PPDMDEVINSR3 pDevInsR3;
429	/** The IOMMU helper. */
430	R3PTRTYPE(PCPDMIOMMUHLPR3) pIommuHlpR3;
431	/** The invalidation-queue thread. */
432	R3PTRTYPE(PPDMTHREAD) pInvQueueThread;
433	} DMARR3;
434	/** Pointer to the ring-3 DMAR device state. */
435	typedef DMARR3 *PDMARR3;
436	/** Pointer to the const ring-3 DMAR device state. */
437	typedef DMARR3 const *PCDMARR3;
438
439	/**
440	* The ring-0 DMAR device state.
441	*/
442	typedef struct DMARR0
443	{
444	/** Device instance. */
445	PPDMDEVINSR0 pDevInsR0;
446	/** The IOMMU helper. */
447	R0PTRTYPE(PCPDMIOMMUHLPR0) pIommuHlpR0;
448	} DMARR0;
449	/** Pointer to the ring-0 IOMMU device state. */
450	typedef DMARR0 *PDMARR0;
451	/** Pointer to the const ring-0 IOMMU device state. */
452	typedef DMARR0 const *PCDMARR0;
453
454	/**
455	* The raw-mode DMAR device state.
456	*/
457	typedef struct DMARRC
458	{
459	/** Device instance. */
460	PPDMDEVINSRC pDevInsRC;
461	/** The IOMMU helper. */
462	RCPTRTYPE(PCPDMIOMMUHLPRC) pIommuHlpRC;
463	} DMARRC;
464	/** Pointer to the raw-mode DMAR device state. */
465	typedef DMARRC *PDMARRC;
466	/** Pointer to the const raw-mode DMAR device state. */
467	typedef DMARRC const *PCIDMARRC;
468
469	/** The DMAR device state for the current context. */
470	typedef CTX_SUFF(DMAR) DMARCC;
471	/** Pointer to the DMAR device state for the current context. */
472	typedef CTX_SUFF(PDMAR) PDMARCC;
473	/** Pointer to the const DMAR device state for the current context. */
474	typedef CTX_SUFF(PDMAR) const PCDMARCC;
475
476	/**
477	* DMAR originated events that generate interrupts.
478	*/
479	typedef enum DMAREVENTTYPE
480	{
481	/** Invalidation completion event. */
482	DMAREVENTTYPE_INV_COMPLETE = 0,
483	/** Fault event. */
484	DMAREVENTTYPE_FAULT
485	} DMAREVENTTYPE;
486
487	/**
488	* I/O Page.
489	*/
490	typedef struct DMARIOPAGE
491	{
492	/** The base DMA address of a page. */
493	RTGCPHYS GCPhysBase;
494	/** The page shift. */
495	uint8_t cShift;
496	/** The permissions of this page (DMAR_PERM_XXX). */
497	uint8_t fPerm;
498	} DMARIOPAGE;
499	/** Pointer to an I/O page. */
500	typedef DMARIOPAGE *PDMARIOPAGE;
501	/** Pointer to a const I/O address range. */
502	typedef DMARIOPAGE const *PCDMARIOPAGE;
503
504	/**
505	* I/O Address Range.
506	*/
507	typedef struct DMARIOADDRRANGE
508	{
509	/** The starting DMA address of this range. */
510	uint64_t uAddr;
511	/** The size of the range (in bytes). */
512	size_t cb;
513	/** The permissions of this range (DMAR_PERM_XXX). */
514	uint8_t fPerm;
515	} DMARIOADDRRANGE;
516	/** Pointer to an I/O address range. */
517	typedef DMARIOADDRRANGE *PDMARIOADDRRANGE;
518	/** Pointer to a const I/O address range. */
519	typedef DMARIOADDRRANGE const *PCDMARIOADDRRANGE;
520
521	/**
522	* DMA Memory Request (Input).
523	*/
524	typedef struct DMARMEMREQIN
525	{
526	/** The address range being accessed. */
527	DMARIOADDRRANGE AddrRange;
528	/** The source device ID (bus, device, function). */
529	uint16_t idDevice;
530	/** The PASID if present (can be NIL_PCIPASID). */
531	PCIPASID Pasid;
532	/* The address translation type. */
533	PCIADDRTYPE enmAddrType;
534	/** The request type. */
535	VTDREQTYPE enmReqType;
536	} DMARMEMREQIN;
537	/** Pointer to a DMA memory request input. */
538	typedef DMARMEMREQIN *PDMARMEMREQIN;
539	/** Pointer to a const DMA memory input. */
540	typedef DMARMEMREQIN const *PCDMARMEMREQIN;
541
542	/**
543	* DMA Memory Request (Output).
544	*/
545	typedef struct DMARMEMREQOUT
546	{
547	/** The address range of the translated region. */
548	DMARIOADDRRANGE AddrRange;
549	/** The domain ID of the translated region. */
550	uint16_t idDomain;
551	} DMARMEMREQOUT;
552	/** Pointer to a DMA memory request output. */
553	typedef DMARMEMREQOUT *PDMARMEMREQOUT;
554	/** Pointer to a const DMA memory request output. */
555	typedef DMARMEMREQOUT const *PCDMARMEMREQOUT;
556
557	/**
558	* DMA Memory Request (Auxiliary Info).
559	* These get updated and used as part of the translation process.
560	*/
561	typedef struct DMARMEMREQAUX
562	{
563	/** The table translation mode (VTD_TTM_XXX). */
564	uint8_t fTtm;
565	/** The fault processing disabled (FPD) bit. */
566	uint8_t fFpd;
567	/** The paging level of the translation. */
568	uint8_t cPagingLevel;
569	uint8_t abPadding[5];
570	/** The address of the first-level page-table. */
571	uint64_t GCPhysFlPt;
572	/** The address of second-level page-table. */
573	uint64_t GCPhysSlPt;
574	} DMARMEMREQAUX;
575	/** Pointer to a DMA memory request output. */
576	typedef DMARMEMREQAUX *PDMARMEMREQAUX;
577	/** Pointer to a const DMA memory request output. */
578	typedef DMARMEMREQAUX const *PCDMARMEMREQAUX;
579
580	/**
581	* DMA Memory Request Remapping Information.
582	*/
583	typedef struct DMARMEMREQREMAP
584	{
585	/** The DMA memory request input. */
586	DMARMEMREQIN In;
587	/** DMA memory request auxiliary information. */
588	DMARMEMREQAUX Aux;
589	/** The DMA memory request output. */
590	DMARMEMREQOUT Out;
591	} DMARMEMREQREMAP;
592	/** Pointer to a DMA remap info. */
593	typedef DMARMEMREQREMAP *PDMARMEMREQREMAP;
594	/** Pointer to a const DMA remap info. */
595	typedef DMARMEMREQREMAP const *PCDMARMEMREQREMAP;
596
597	/**
598	* Callback function to lookup a DMA address.
599	*
600	* @returns VBox status code.
601	* @param pDevIns The IOMMU device instance.
602	* @param pMemReqIn The DMA memory request input.
603	* @param pMemReqAux The DMA memory request auxiliary info.
604	* @param pIoPageOut Where to store the output of the lookup.
605	*/
606	typedef DECLCALLBACKTYPE(int, FNDMADDRLOOKUP,(PPDMDEVINS pDevIns, PCDMARMEMREQIN pMemReqIn, PCDMARMEMREQAUX pMemReqAux,
607	PDMARIOPAGE pIoPageOut));
608	/** Pointer to a DMA address-lookup function. */
609	typedef FNDMADDRLOOKUP *PFNDMADDRLOOKUP;
610
611
612	/*********************************************************************************************************************************
613	* Global Variables *
614	*********************************************************************************************************************************/
615	/**
616	* Read-write masks for DMAR registers (group 0).
617	*/
618	static uint32_t const g_au32RwMasks0[] =
619	{
620	/* Offset Register Low High */
621	/* 0x000 VER_REG */ VTD_VER_REG_RW_MASK,
622	/* 0x004 Reserved */ 0,
623	/* 0x008 CAP_REG */ DMAR_LO_U32(VTD_CAP_REG_RW_MASK), DMAR_HI_U32(VTD_CAP_REG_RW_MASK),
624	/* 0x010 ECAP_REG */ DMAR_LO_U32(VTD_ECAP_REG_RW_MASK), DMAR_HI_U32(VTD_ECAP_REG_RW_MASK),
625	/* 0x018 GCMD_REG */ VTD_GCMD_REG_RW_MASK,
626	/* 0x01c GSTS_REG */ VTD_GSTS_REG_RW_MASK,
627	/* 0x020 RTADDR_REG */ DMAR_LO_U32(VTD_RTADDR_REG_RW_MASK), DMAR_HI_U32(VTD_RTADDR_REG_RW_MASK),
628	/* 0x028 CCMD_REG */ DMAR_LO_U32(VTD_CCMD_REG_RW_MASK), DMAR_HI_U32(VTD_CCMD_REG_RW_MASK),
629	/* 0x030 Reserved */ 0,
630	/* 0x034 FSTS_REG */ VTD_FSTS_REG_RW_MASK,
631	/* 0x038 FECTL_REG */ VTD_FECTL_REG_RW_MASK,
632	/* 0x03c FEDATA_REG */ VTD_FEDATA_REG_RW_MASK,
633	/* 0x040 FEADDR_REG */ VTD_FEADDR_REG_RW_MASK,
634	/* 0x044 FEUADDR_REG */ VTD_FEUADDR_REG_RW_MASK,
635	/* 0x048 Reserved */ 0, 0,
636	/* 0x050 Reserved */ 0, 0,
637	/* 0x058 AFLOG_REG */ DMAR_LO_U32(VTD_AFLOG_REG_RW_MASK), DMAR_HI_U32(VTD_AFLOG_REG_RW_MASK),
638	/* 0x060 Reserved */ 0,
639	/* 0x064 PMEN_REG / 0, / RO as we don't support PLMR and PHMR. */
640	/* 0x068 PLMBASE_REG / 0, / RO as we don't support PLMR. */
641	/* 0x06c PLMLIMIT_REG / 0, / RO as we don't support PLMR. */
642	/* 0x070 PHMBASE_REG / 0, 0, / RO as we don't support PHMR. */
643	/* 0x078 PHMLIMIT_REG / 0, 0, / RO as we don't support PHMR. */
644	/* 0x080 IQH_REG */ DMAR_LO_U32(VTD_IQH_REG_RW_MASK), DMAR_HI_U32(VTD_IQH_REG_RW_MASK),
645	/* 0x088 IQT_REG */ DMAR_LO_U32(VTD_IQT_REG_RW_MASK), DMAR_HI_U32(VTD_IQT_REG_RW_MASK),
646	/* 0x090 IQA_REG */ DMAR_LO_U32(VTD_IQA_REG_RW_MASK), DMAR_HI_U32(VTD_IQA_REG_RW_MASK),
647	/* 0x098 Reserved */ 0,
648	/* 0x09c ICS_REG */ VTD_ICS_REG_RW_MASK,
649	/* 0x0a0 IECTL_REG */ VTD_IECTL_REG_RW_MASK,
650	/* 0x0a4 IEDATA_REG */ VTD_IEDATA_REG_RW_MASK,
651	/* 0x0a8 IEADDR_REG */ VTD_IEADDR_REG_RW_MASK,
652	/* 0x0ac IEUADDR_REG */ VTD_IEUADDR_REG_RW_MASK,
653	/* 0x0b0 IQERCD_REG */ DMAR_LO_U32(VTD_IQERCD_REG_RW_MASK), DMAR_HI_U32(VTD_IQERCD_REG_RW_MASK),
654	/* 0x0b8 IRTA_REG */ DMAR_LO_U32(VTD_IRTA_REG_RW_MASK), DMAR_HI_U32(VTD_IRTA_REG_RW_MASK),
655	/* 0x0c0 PQH_REG */ DMAR_LO_U32(VTD_PQH_REG_RW_MASK), DMAR_HI_U32(VTD_PQH_REG_RW_MASK),
656	/* 0x0c8 PQT_REG */ DMAR_LO_U32(VTD_PQT_REG_RW_MASK), DMAR_HI_U32(VTD_PQT_REG_RW_MASK),
657	/* 0x0d0 PQA_REG */ DMAR_LO_U32(VTD_PQA_REG_RW_MASK), DMAR_HI_U32(VTD_PQA_REG_RW_MASK),
658	/* 0x0d8 Reserved */ 0,
659	/* 0x0dc PRS_REG */ VTD_PRS_REG_RW_MASK,
660	/* 0x0e0 PECTL_REG */ VTD_PECTL_REG_RW_MASK,
661	/* 0x0e4 PEDATA_REG */ VTD_PEDATA_REG_RW_MASK,
662	/* 0x0e8 PEADDR_REG */ VTD_PEADDR_REG_RW_MASK,
663	/* 0x0ec PEUADDR_REG */ VTD_PEUADDR_REG_RW_MASK,
664	/* 0x0f0 Reserved */ 0, 0,
665	/* 0x0f8 Reserved */ 0, 0,
666	/* 0x100 MTRRCAP_REG */ DMAR_LO_U32(VTD_MTRRCAP_REG_RW_MASK), DMAR_HI_U32(VTD_MTRRCAP_REG_RW_MASK),
667	/* 0x108 MTRRDEF_REG / 0, 0, / RO as we don't support MTS. */
668	/* 0x110 Reserved */ 0, 0,
669	/* 0x118 Reserved */ 0, 0,
670	/* 0x120 MTRR_FIX64_00000_REG / 0, 0, / RO as we don't support MTS. */
671	/* 0x128 MTRR_FIX16K_80000_REG */ 0, 0,
672	/* 0x130 MTRR_FIX16K_A0000_REG */ 0, 0,
673	/* 0x138 MTRR_FIX4K_C0000_REG */ 0, 0,
674	/* 0x140 MTRR_FIX4K_C8000_REG */ 0, 0,
675	/* 0x148 MTRR_FIX4K_D0000_REG */ 0, 0,
676	/* 0x150 MTRR_FIX4K_D8000_REG */ 0, 0,
677	/* 0x158 MTRR_FIX4K_E0000_REG */ 0, 0,
678	/* 0x160 MTRR_FIX4K_E8000_REG */ 0, 0,
679	/* 0x168 MTRR_FIX4K_F0000_REG */ 0, 0,
680	/* 0x170 MTRR_FIX4K_F8000_REG */ 0, 0,
681	/* 0x178 Reserved */ 0, 0,
682	/* 0x180 MTRR_PHYSBASE0_REG / 0, 0, / RO as we don't support MTS. */
683	/* 0x188 MTRR_PHYSMASK0_REG */ 0, 0,
684	/* 0x190 MTRR_PHYSBASE1_REG */ 0, 0,
685	/* 0x198 MTRR_PHYSMASK1_REG */ 0, 0,
686	/* 0x1a0 MTRR_PHYSBASE2_REG */ 0, 0,
687	/* 0x1a8 MTRR_PHYSMASK2_REG */ 0, 0,
688	/* 0x1b0 MTRR_PHYSBASE3_REG */ 0, 0,
689	/* 0x1b8 MTRR_PHYSMASK3_REG */ 0, 0,
690	/* 0x1c0 MTRR_PHYSBASE4_REG */ 0, 0,
691	/* 0x1c8 MTRR_PHYSMASK4_REG */ 0, 0,
692	/* 0x1d0 MTRR_PHYSBASE5_REG */ 0, 0,
693	/* 0x1d8 MTRR_PHYSMASK5_REG */ 0, 0,
694	/* 0x1e0 MTRR_PHYSBASE6_REG */ 0, 0,
695	/* 0x1e8 MTRR_PHYSMASK6_REG */ 0, 0,
696	/* 0x1f0 MTRR_PHYSBASE7_REG */ 0, 0,
697	/* 0x1f8 MTRR_PHYSMASK7_REG */ 0, 0,
698	/* 0x200 MTRR_PHYSBASE8_REG */ 0, 0,
699	/* 0x208 MTRR_PHYSMASK8_REG */ 0, 0,
700	/* 0x210 MTRR_PHYSBASE9_REG */ 0, 0,
701	/* 0x218 MTRR_PHYSMASK9_REG */ 0, 0,
702	};
703	AssertCompile(sizeof(g_au32RwMasks0) == DMAR_MMIO_GROUP_0_SIZE);
704
705	/**
706	* Read-only Status, Write-1-to-clear masks for DMAR registers (group 0).
707	*/
708	static uint32_t const g_au32Rw1cMasks0[] =
709	{
710	/* Offset Register Low High */
711	/* 0x000 VER_REG */ 0,
712	/* 0x004 Reserved */ 0,
713	/* 0x008 CAP_REG */ 0, 0,
714	/* 0x010 ECAP_REG */ 0, 0,
715	/* 0x018 GCMD_REG */ 0,
716	/* 0x01c GSTS_REG */ 0,
717	/* 0x020 RTADDR_REG */ 0, 0,
718	/* 0x028 CCMD_REG */ 0, 0,
719	/* 0x030 Reserved */ 0,
720	/* 0x034 FSTS_REG */ VTD_FSTS_REG_RW1C_MASK,
721	/* 0x038 FECTL_REG */ 0,
722	/* 0x03c FEDATA_REG */ 0,
723	/* 0x040 FEADDR_REG */ 0,
724	/* 0x044 FEUADDR_REG */ 0,
725	/* 0x048 Reserved */ 0, 0,
726	/* 0x050 Reserved */ 0, 0,
727	/* 0x058 AFLOG_REG */ 0, 0,
728	/* 0x060 Reserved */ 0,
729	/* 0x064 PMEN_REG */ 0,
730	/* 0x068 PLMBASE_REG */ 0,
731	/* 0x06c PLMLIMIT_REG */ 0,
732	/* 0x070 PHMBASE_REG */ 0, 0,
733	/* 0x078 PHMLIMIT_REG */ 0, 0,
734	/* 0x080 IQH_REG */ 0, 0,
735	/* 0x088 IQT_REG */ 0, 0,
736	/* 0x090 IQA_REG */ 0, 0,
737	/* 0x098 Reserved */ 0,
738	/* 0x09c ICS_REG */ VTD_ICS_REG_RW1C_MASK,
739	/* 0x0a0 IECTL_REG */ 0,
740	/* 0x0a4 IEDATA_REG */ 0,
741	/* 0x0a8 IEADDR_REG */ 0,
742	/* 0x0ac IEUADDR_REG */ 0,
743	/* 0x0b0 IQERCD_REG */ 0, 0,
744	/* 0x0b8 IRTA_REG */ 0, 0,
745	/* 0x0c0 PQH_REG */ 0, 0,
746	/* 0x0c8 PQT_REG */ 0, 0,
747	/* 0x0d0 PQA_REG */ 0, 0,
748	/* 0x0d8 Reserved */ 0,
749	/* 0x0dc PRS_REG */ 0,
750	/* 0x0e0 PECTL_REG */ 0,
751	/* 0x0e4 PEDATA_REG */ 0,
752	/* 0x0e8 PEADDR_REG */ 0,
753	/* 0x0ec PEUADDR_REG */ 0,
754	/* 0x0f0 Reserved */ 0, 0,
755	/* 0x0f8 Reserved */ 0, 0,
756	/* 0x100 MTRRCAP_REG */ 0, 0,
757	/* 0x108 MTRRDEF_REG */ 0, 0,
758	/* 0x110 Reserved */ 0, 0,
759	/* 0x118 Reserved */ 0, 0,
760	/* 0x120 MTRR_FIX64_00000_REG */ 0, 0,
761	/* 0x128 MTRR_FIX16K_80000_REG */ 0, 0,
762	/* 0x130 MTRR_FIX16K_A0000_REG */ 0, 0,
763	/* 0x138 MTRR_FIX4K_C0000_REG */ 0, 0,
764	/* 0x140 MTRR_FIX4K_C8000_REG */ 0, 0,
765	/* 0x148 MTRR_FIX4K_D0000_REG */ 0, 0,
766	/* 0x150 MTRR_FIX4K_D8000_REG */ 0, 0,
767	/* 0x158 MTRR_FIX4K_E0000_REG */ 0, 0,
768	/* 0x160 MTRR_FIX4K_E8000_REG */ 0, 0,
769	/* 0x168 MTRR_FIX4K_F0000_REG */ 0, 0,
770	/* 0x170 MTRR_FIX4K_F8000_REG */ 0, 0,
771	/* 0x178 Reserved */ 0, 0,
772	/* 0x180 MTRR_PHYSBASE0_REG */ 0, 0,
773	/* 0x188 MTRR_PHYSMASK0_REG */ 0, 0,
774	/* 0x190 MTRR_PHYSBASE1_REG */ 0, 0,
775	/* 0x198 MTRR_PHYSMASK1_REG */ 0, 0,
776	/* 0x1a0 MTRR_PHYSBASE2_REG */ 0, 0,
777	/* 0x1a8 MTRR_PHYSMASK2_REG */ 0, 0,
778	/* 0x1b0 MTRR_PHYSBASE3_REG */ 0, 0,
779	/* 0x1b8 MTRR_PHYSMASK3_REG */ 0, 0,
780	/* 0x1c0 MTRR_PHYSBASE4_REG */ 0, 0,
781	/* 0x1c8 MTRR_PHYSMASK4_REG */ 0, 0,
782	/* 0x1d0 MTRR_PHYSBASE5_REG */ 0, 0,
783	/* 0x1d8 MTRR_PHYSMASK5_REG */ 0, 0,
784	/* 0x1e0 MTRR_PHYSBASE6_REG */ 0, 0,
785	/* 0x1e8 MTRR_PHYSMASK6_REG */ 0, 0,
786	/* 0x1f0 MTRR_PHYSBASE7_REG */ 0, 0,
787	/* 0x1f8 MTRR_PHYSMASK7_REG */ 0, 0,
788	/* 0x200 MTRR_PHYSBASE8_REG */ 0, 0,
789	/* 0x208 MTRR_PHYSMASK8_REG */ 0, 0,
790	/* 0x210 MTRR_PHYSBASE9_REG */ 0, 0,
791	/* 0x218 MTRR_PHYSMASK9_REG */ 0, 0,
792	};
793	AssertCompile(sizeof(g_au32Rw1cMasks0) == DMAR_MMIO_GROUP_0_SIZE);
794
795	/**
796	* Read-write masks for DMAR registers (group 1).
797	*/
798	static uint32_t const g_au32RwMasks1[] =
799	{
800	/* Offset Register Low High */
801	/* 0xe00 VCCAP_REG */ DMAR_LO_U32(VTD_VCCAP_REG_RW_MASK), DMAR_HI_U32(VTD_VCCAP_REG_RW_MASK),
802	/* 0xe08 VCMD_EO_REG */ DMAR_LO_U32(VTD_VCMD_EO_REG_RW_MASK), DMAR_HI_U32(VTD_VCMD_EO_REG_RW_MASK),
803	/* 0xe10 VCMD_REG / 0, 0, / RO: VCS not supported. */
804	/* 0xe18 VCMDRSVD_REG */ 0, 0,
805	/* 0xe20 VCRSP_REG / 0, 0, / RO: VCS not supported. */
806	/* 0xe28 VCRSPRSVD_REG */ 0, 0,
807	/* 0xe30 Reserved */ 0, 0,
808	/* 0xe38 Reserved */ 0, 0,
809	/* 0xe40 Reserved */ 0, 0,
810	/* 0xe48 Reserved */ 0, 0,
811	/* 0xe50 IVA_REG */ DMAR_LO_U32(VTD_IVA_REG_RW_MASK), DMAR_HI_U32(VTD_IVA_REG_RW_MASK),
812	/* 0xe58 IOTLB_REG */ DMAR_LO_U32(VTD_IOTLB_REG_RW_MASK), DMAR_HI_U32(VTD_IOTLB_REG_RW_MASK),
813	/* 0xe60 Reserved */ 0, 0,
814	/* 0xe68 Reserved */ 0, 0,
815	/* 0xe70 FRCD_REG_LO */ DMAR_LO_U32(VTD_FRCD_REG_LO_RW_MASK), DMAR_HI_U32(VTD_FRCD_REG_LO_RW_MASK),
816	/* 0xe78 FRCD_REG_HI */ DMAR_LO_U32(VTD_FRCD_REG_HI_RW_MASK), DMAR_HI_U32(VTD_FRCD_REG_HI_RW_MASK),
817	};
818	AssertCompile(sizeof(g_au32RwMasks1) == DMAR_MMIO_GROUP_1_SIZE);
819	AssertCompile((DMAR_MMIO_OFF_FRCD_LO_REG - DMAR_MMIO_GROUP_1_OFF_FIRST) + DMAR_FRCD_REG_COUNT * 2 * sizeof(uint64_t) );
820
821	/**
822	* Read-only Status, Write-1-to-clear masks for DMAR registers (group 1).
823	*/
824	static uint32_t const g_au32Rw1cMasks1[] =
825	{
826	/* Offset Register Low High */
827	/* 0xe00 VCCAP_REG */ 0, 0,
828	/* 0xe08 VCMD_EO_REG */ 0, 0,
829	/* 0xe10 VCMD_REG */ 0, 0,
830	/* 0xe18 VCMDRSVD_REG */ 0, 0,
831	/* 0xe20 VCRSP_REG */ 0, 0,
832	/* 0xe28 VCRSPRSVD_REG */ 0, 0,
833	/* 0xe30 Reserved */ 0, 0,
834	/* 0xe38 Reserved */ 0, 0,
835	/* 0xe40 Reserved */ 0, 0,
836	/* 0xe48 Reserved */ 0, 0,
837	/* 0xe50 IVA_REG */ 0, 0,
838	/* 0xe58 IOTLB_REG */ 0, 0,
839	/* 0xe60 Reserved */ 0, 0,
840	/* 0xe68 Reserved */ 0, 0,
841	/* 0xe70 FRCD_REG_LO */ DMAR_LO_U32(VTD_FRCD_REG_LO_RW1C_MASK), DMAR_HI_U32(VTD_FRCD_REG_LO_RW1C_MASK),
842	/* 0xe78 FRCD_REG_HI */ DMAR_LO_U32(VTD_FRCD_REG_HI_RW1C_MASK), DMAR_HI_U32(VTD_FRCD_REG_HI_RW1C_MASK),
843	};
844	AssertCompile(sizeof(g_au32Rw1cMasks1) == DMAR_MMIO_GROUP_1_SIZE);
845
846	/** Array of RW masks for each register group. */
847	static uint8_t const g_apbRwMasks[] = { (uint8_t )&g_au32RwMasks0[0], (uint8_t *)&g_au32RwMasks1[0] };
848
849	/** Array of RW1C masks for each register group. */
850	static uint8_t const g_apbRw1cMasks[] = { (uint8_t )&g_au32Rw1cMasks0[0], (uint8_t *)&g_au32Rw1cMasks1[0] };
851
852	/* Masks arrays must be identical in size (even bounds checking code assumes this). */
853	AssertCompile(sizeof(g_apbRw1cMasks) == sizeof(g_apbRwMasks));
854
855	/** Array of valid domain-ID bits. */
856	static uint16_t const g_auNdMask[] = { 0xf, 0x3f, 0xff, 0x3ff, 0xfff, 0x3fff, 0xffff, 0 };
857	AssertCompile(RT_ELEMENTS(g_auNdMask) >= DMAR_ND);
858
859
860	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
861	/**
862	* Returns the supported adjusted guest-address width (SAGAW) given the maximum
863	* guest address width (MGAW).
864	*
865	* @returns The CAP_REG.SAGAW value.
866	* @param uMgaw The CAP_REG.MGAW value.
867	*/
868	static uint8_t vtdCapRegGetSagaw(uint8_t uMgaw)
869	{
870	/*
871	* It doesn't make sense to me that a CPU (or IOMMU hardware) will ever support
872	* 5-level paging but not 4 or 3-level paging. So smaller page-table levels
873	* are always OR'ed in below.
874	*
875	* The bit values below (57, 48, 39 bits) represents the levels of page-table walks
876	* for 4KB base page size (5-level, 4-level and 3-level paging respectively).
877	*
878	* See Intel VT-d spec. 10.4.2 "Capability Register".
879	*/
880	++uMgaw;
881	uint8_t const fSagaw = uMgaw >= 57 ? RT_BIT(3) \| RT_BIT(2) \| RT_BIT(1)
882	: uMgaw >= 48 ? RT_BIT(2) \| RT_BIT(1)
883	: uMgaw >= 39 ? RT_BIT(1)
884	: 0;
885	return fSagaw;
886	}
887
888
889	/**
890	* Returns the maximum supported paging level given the supported adjusted
891	* guest-address width (SAGAW) field.
892	*
893	* @returns The highest paging level supported, 0 if invalid.
894	* @param fSagaw The CAP_REG.SAGAW value.
895	*/
896	static uint8_t vtdCapRegGetMaxPagingLevel(uint8_t fSagaw)
897	{
898	uint8_t const cMaxPagingLevel = fSagaw & RT_BIT(3) ? 5
899	: fSagaw & RT_BIT(2) ? 4
900	: fSagaw & RT_BIT(1) ? 3
901	: 0;
902	return cMaxPagingLevel;
903	}
904
905
906	/**
907	* Returns whether the interrupt remapping (IR) fault is qualified or not.
908	*
909	* @returns @c true if qualified, @c false otherwise.
910	* @param enmIrFault The interrupt remapping fault condition.
911	*/
912	static bool vtdIrFaultIsQualified(VTDIRFAULT enmIrFault)
913	{
914	switch (enmIrFault)
915	{
916	case VTDIRFAULT_IRTE_NOT_PRESENT:
917	case VTDIRFAULT_IRTE_PRESENT_RSVD:
918	case VTDIRFAULT_IRTE_PRESENT_INVALID:
919	case VTDIRFAULT_PID_READ_FAILED:
920	case VTDIRFAULT_PID_RSVD:
921	return true;
922	default:
923	return false;
924	}
925	}
926
927
928	/**
929	* Returns table translation mode's descriptive name.
930	*
931	* @returns The descriptive name.
932	* @param uTtm The RTADDR_REG.TTM value.
933	*/
934	static const char* vtdRtaddrRegGetTtmDesc(uint8_t uTtm)
935	{
936	Assert(!(uTtm & 3));
937	static const char* s_apszTtmNames[] =
938	{
939	"Legacy Mode",
940	"Scalable Mode",
941	"Reserved",
942	"Abort-DMA Mode"
943	};
944	return s_apszTtmNames[uTtm & (RT_ELEMENTS(s_apszTtmNames) - 1)];
945	}
946
947
948	/**
949	* Gets the index of the group the register belongs to given its MMIO offset.
950	*
951	* @returns The group index.
952	* @param offReg The MMIO offset of the register.
953	* @param cbReg The size of the access being made (for bounds checking on
954	* debug builds).
955	*/
956	DECLINLINE(uint8_t) dmarRegGetGroupIndex(uint16_t offReg, uint8_t cbReg)
957	{
958	uint16_t const offLast = offReg + cbReg - 1;
959	AssertCompile(DMAR_MMIO_GROUP_0_OFF_FIRST == 0);
960	AssertMsg(DMAR_IS_MMIO_OFF_VALID(offLast), ("off=%#x cb=%u\n", offReg, cbReg));
961	return !(offLast < DMAR_MMIO_GROUP_0_OFF_END);
962	}
963
964
965	/**
966	* Gets the group the register belongs to given its MMIO offset.
967	*
968	* @returns Pointer to the first element of the register group.
969	* @param pThis The shared DMAR device state.
970	* @param offReg The MMIO offset of the register.
971	* @param cbReg The size of the access being made (for bounds checking on
972	* debug builds).
973	* @param pIdxGroup Where to store the index of the register group the register
974	* belongs to.
975	*/
976	DECLINLINE(uint8_t ) dmarRegGetGroup(PDMAR pThis, uint16_t offReg, uint8_t cbReg, uint8_t pIdxGroup)
977	{
978	*pIdxGroup = dmarRegGetGroupIndex(offReg, cbReg);
979	uint8_t *apbRegs[] = { &pThis->abRegs0[0], &pThis->abRegs1[0] };
980	return apbRegs[*pIdxGroup];
981	}
982
983
984	/**
985	* Const/read-only version of dmarRegGetGroup.
986	*
987	* @copydoc dmarRegGetGroup
988	*/
989	DECLINLINE(uint8_t const) dmarRegGetGroupRo(PCDMAR pThis, uint16_t offReg, uint8_t cbReg, uint8_t pIdxGroup)
990	{
991	*pIdxGroup = dmarRegGetGroupIndex(offReg, cbReg);
992	uint8_t const *apbRegs[] = { &pThis->abRegs0[0], &pThis->abRegs1[0] };
993	return apbRegs[*pIdxGroup];
994	}
995
996
997	/**
998	* Writes a 32-bit register with the exactly the supplied value.
999	*
1000	* @param pThis The shared DMAR device state.
1001	* @param offReg The MMIO offset of the register.
1002	* @param uReg The 32-bit value to write.
1003	*/
1004	static void dmarRegWriteRaw32(PDMAR pThis, uint16_t offReg, uint32_t uReg)
1005	{
1006	uint8_t idxGroup;
1007	uint8_t *pabRegs = dmarRegGetGroup(pThis, offReg, sizeof(uint32_t), &idxGroup);
1008	NOREF(idxGroup);
1009	(uint32_t )(pabRegs + offReg) = uReg;
1010	}
1011
1012
1013	/**
1014	* Writes a 64-bit register with the exactly the supplied value.
1015	*
1016	* @param pThis The shared DMAR device state.
1017	* @param offReg The MMIO offset of the register.
1018	* @param uReg The 64-bit value to write.
1019	*/
1020	static void dmarRegWriteRaw64(PDMAR pThis, uint16_t offReg, uint64_t uReg)
1021	{
1022	uint8_t idxGroup;
1023	uint8_t *pabRegs = dmarRegGetGroup(pThis, offReg, sizeof(uint64_t), &idxGroup);
1024	NOREF(idxGroup);
1025	(uint64_t )(pabRegs + offReg) = uReg;
1026	}
1027
1028
1029	/**
1030	* Reads a 32-bit register with exactly the value it contains.
1031	*
1032	* @returns The raw register value.
1033	* @param pThis The shared DMAR device state.
1034	* @param offReg The MMIO offset of the register.
1035	*/
1036	static uint32_t dmarRegReadRaw32(PCDMAR pThis, uint16_t offReg)
1037	{
1038	uint8_t idxGroup;
1039	uint8_t const *pabRegs = dmarRegGetGroupRo(pThis, offReg, sizeof(uint32_t), &idxGroup);
1040	NOREF(idxGroup);
1041	return (uint32_t )(pabRegs + offReg);
1042	}
1043
1044
1045	/**
1046	* Reads a 64-bit register with exactly the value it contains.
1047	*
1048	* @returns The raw register value.
1049	* @param pThis The shared DMAR device state.
1050	* @param offReg The MMIO offset of the register.
1051	*/
1052	static uint64_t dmarRegReadRaw64(PCDMAR pThis, uint16_t offReg)
1053	{
1054	uint8_t idxGroup;
1055	uint8_t const *pabRegs = dmarRegGetGroupRo(pThis, offReg, sizeof(uint64_t), &idxGroup);
1056	NOREF(idxGroup);
1057	return (uint64_t )(pabRegs + offReg);
1058	}
1059
1060
1061	/**
1062	* Reads a 32-bit register with exactly the value it contains along with their
1063	* corresponding masks
1064	*
1065	* @param pThis The shared DMAR device state.
1066	* @param offReg The MMIO offset of the register.
1067	* @param puReg Where to store the raw 32-bit register value.
1068	* @param pfRwMask Where to store the RW mask corresponding to this register.
1069	* @param pfRw1cMask Where to store the RW1C mask corresponding to this register.
1070	*/
1071	static void dmarRegReadRaw32Ex(PCDMAR pThis, uint16_t offReg, uint32_t puReg, uint32_t pfRwMask, uint32_t *pfRw1cMask)
1072	{
1073	uint8_t idxGroup;
1074	uint8_t const *pabRegs = dmarRegGetGroupRo(pThis, offReg, sizeof(uint32_t), &idxGroup);
1075	Assert(idxGroup < RT_ELEMENTS(g_apbRwMasks));
1076	uint8_t const *pabRwMasks = g_apbRwMasks[idxGroup];
1077	uint8_t const *pabRw1cMasks = g_apbRw1cMasks[idxGroup];
1078	puReg = (uint32_t *)(pabRegs + offReg);
1079	pfRwMask = (uint32_t *)(pabRwMasks + offReg);
1080	pfRw1cMask = (uint32_t *)(pabRw1cMasks + offReg);
1081	}
1082
1083
1084	/**
1085	* Reads a 64-bit register with exactly the value it contains along with their
1086	* corresponding masks.
1087	*
1088	* @param pThis The shared DMAR device state.
1089	* @param offReg The MMIO offset of the register.
1090	* @param puReg Where to store the raw 64-bit register value.
1091	* @param pfRwMask Where to store the RW mask corresponding to this register.
1092	* @param pfRw1cMask Where to store the RW1C mask corresponding to this register.
1093	*/
1094	static void dmarRegReadRaw64Ex(PCDMAR pThis, uint16_t offReg, uint64_t puReg, uint64_t pfRwMask, uint64_t *pfRw1cMask)
1095	{
1096	uint8_t idxGroup;
1097	uint8_t const *pabRegs = dmarRegGetGroupRo(pThis, offReg, sizeof(uint64_t), &idxGroup);
1098	Assert(idxGroup < RT_ELEMENTS(g_apbRwMasks));
1099	uint8_t const *pabRwMasks = g_apbRwMasks[idxGroup];
1100	uint8_t const *pabRw1cMasks = g_apbRw1cMasks[idxGroup];
1101	puReg = (uint64_t *)(pabRegs + offReg);
1102	pfRwMask = (uint64_t *)(pabRwMasks + offReg);
1103	pfRw1cMask = (uint64_t *)(pabRw1cMasks + offReg);
1104	}
1105
1106
1107	/**
1108	* Writes a 32-bit register as it would be when written by software.
1109	* This will preserve read-only bits, mask off reserved bits and clear RW1C bits.
1110	*
1111	* @returns The value that's actually written to the register.
1112	* @param pThis The shared DMAR device state.
1113	* @param offReg The MMIO offset of the register.
1114	* @param uReg The 32-bit value to write.
1115	* @param puPrev Where to store the register value prior to writing.
1116	*/
1117	static uint32_t dmarRegWrite32(PDMAR pThis, uint16_t offReg, uint32_t uReg, uint32_t *puPrev)
1118	{
1119	/* Read current value from the 32-bit register. */
1120	uint32_t uCurReg;
1121	uint32_t fRwMask;
1122	uint32_t fRw1cMask;
1123	dmarRegReadRaw32Ex(pThis, offReg, &uCurReg, &fRwMask, &fRw1cMask);
1124	*puPrev = uCurReg;
1125
1126	uint32_t const fRoBits = uCurReg & ~fRwMask; /* Preserve current read-only and reserved bits. */
1127	uint32_t const fRwBits = uReg & fRwMask; /* Merge newly written read/write bits. */
1128	uint32_t const fRw1cBits = uReg & fRw1cMask; /* Clear 1s written to RW1C bits. */
1129	uint32_t const uNewReg = (fRoBits \| fRwBits) & ~fRw1cBits;
1130
1131	/* Write new value to the 32-bit register. */
1132	dmarRegWriteRaw32(pThis, offReg, uNewReg);
1133	return uNewReg;
1134	}
1135
1136
1137	/**
1138	* Writes a 64-bit register as it would be when written by software.
1139	* This will preserve read-only bits, mask off reserved bits and clear RW1C bits.
1140	*
1141	* @returns The value that's actually written to the register.
1142	* @param pThis The shared DMAR device state.
1143	* @param offReg The MMIO offset of the register.
1144	* @param uReg The 64-bit value to write.
1145	* @param puPrev Where to store the register value prior to writing.
1146	*/
1147	static uint64_t dmarRegWrite64(PDMAR pThis, uint16_t offReg, uint64_t uReg, uint64_t *puPrev)
1148	{
1149	/* Read current value from the 64-bit register. */
1150	uint64_t uCurReg;
1151	uint64_t fRwMask;
1152	uint64_t fRw1cMask;
1153	dmarRegReadRaw64Ex(pThis, offReg, &uCurReg, &fRwMask, &fRw1cMask);
1154	*puPrev = uCurReg;
1155
1156	uint64_t const fRoBits = uCurReg & ~fRwMask; /* Preserve current read-only and reserved bits. */
1157	uint64_t const fRwBits = uReg & fRwMask; /* Merge newly written read/write bits. */
1158	uint64_t const fRw1cBits = uReg & fRw1cMask; /* Clear 1s written to RW1C bits. */
1159	uint64_t const uNewReg = (fRoBits \| fRwBits) & ~fRw1cBits;
1160
1161	/* Write new value to the 64-bit register. */
1162	dmarRegWriteRaw64(pThis, offReg, uNewReg);
1163	return uNewReg;
1164	}
1165
1166
1167	/**
1168	* Reads a 32-bit register as it would be when read by software.
1169	*
1170	* @returns The register value.
1171	* @param pThis The shared DMAR device state.
1172	* @param offReg The MMIO offset of the register.
1173	*/
1174	static uint32_t dmarRegRead32(PCDMAR pThis, uint16_t offReg)
1175	{
1176	return dmarRegReadRaw32(pThis, offReg);
1177	}
1178
1179
1180	/**
1181	* Reads a 64-bit register as it would be when read by software.
1182	*
1183	* @returns The register value.
1184	* @param pThis The shared DMAR device state.
1185	* @param offReg The MMIO offset of the register.
1186	*/
1187	static uint64_t dmarRegRead64(PCDMAR pThis, uint16_t offReg)
1188	{
1189	return dmarRegReadRaw64(pThis, offReg);
1190	}
1191
1192
1193	/**
1194	* Modifies a 32-bit register.
1195	*
1196	* @param pThis The shared DMAR device state.
1197	* @param offReg The MMIO offset of the register.
1198	* @param fAndMask The AND mask (applied first).
1199	* @param fOrMask The OR mask.
1200	* @remarks This does NOT apply RO or RW1C masks while modifying the
1201	* register.
1202	*/
1203	static void dmarRegChangeRaw32(PDMAR pThis, uint16_t offReg, uint32_t fAndMask, uint32_t fOrMask)
1204	{
1205	uint32_t uReg = dmarRegReadRaw32(pThis, offReg);
1206	uReg = (uReg & fAndMask) \| fOrMask;
1207	dmarRegWriteRaw32(pThis, offReg, uReg);
1208	}
1209
1210
1211	/**
1212	* Modifies a 64-bit register.
1213	*
1214	* @param pThis The shared DMAR device state.
1215	* @param offReg The MMIO offset of the register.
1216	* @param fAndMask The AND mask (applied first).
1217	* @param fOrMask The OR mask.
1218	* @remarks This does NOT apply RO or RW1C masks while modifying the
1219	* register.
1220	*/
1221	static void dmarRegChangeRaw64(PDMAR pThis, uint16_t offReg, uint64_t fAndMask, uint64_t fOrMask)
1222	{
1223	uint64_t uReg = dmarRegReadRaw64(pThis, offReg);
1224	uReg = (uReg & fAndMask) \| fOrMask;
1225	dmarRegWriteRaw64(pThis, offReg, uReg);
1226	}
1227
1228
1229	/**
1230	* Checks if the invalidation-queue is empty.
1231	*
1232	* Extended version which optionally returns the current queue head and tail
1233	* offsets.
1234	*
1235	* @returns @c true if empty, @c false otherwise.
1236	* @param pThis The shared DMAR device state.
1237	* @param poffQh Where to store the queue head offset. Optional, can be NULL.
1238	* @param poffQt Where to store the queue tail offset. Optional, can be NULL.
1239	*/
1240	static bool dmarInvQueueIsEmptyEx(PCDMAR pThis, uint32_t poffQh, uint32_t poffQt)
1241	{
1242	/* Read only the low-32 bits of the queue head and queue tail as high bits are all RsvdZ.*/
1243	uint32_t const uIqtReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IQT_REG);
1244	uint32_t const uIqhReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IQH_REG);
1245
1246	/* Don't bother masking QT, QH since other bits are RsvdZ. */
1247	Assert(!(uIqtReg & ~VTD_BF_IQT_REG_QT_MASK));
1248	Assert(!(uIqhReg & ~VTD_BF_IQH_REG_QH_MASK));
1249	if (poffQh)
1250	*poffQh = uIqhReg;
1251	if (poffQt)
1252	*poffQt = uIqtReg;
1253	return uIqtReg == uIqhReg;
1254	}
1255
1256
1257	/**
1258	* Checks if the invalidation-queue is empty.
1259	*
1260	* @returns @c true if empty, @c false otherwise.
1261	* @param pThis The shared DMAR device state.
1262	*/
1263	static bool dmarInvQueueIsEmpty(PCDMAR pThis)
1264	{
1265	return dmarInvQueueIsEmptyEx(pThis, NULL /* poffQh /, NULL / poffQt */);
1266	}
1267
1268
1269	/**
1270	* Checks if the invalidation-queue is capable of processing requests.
1271	*
1272	* @returns @c true if the invalidation-queue can process requests, @c false
1273	* otherwise.
1274	* @param pThis The shared DMAR device state.
1275	*/
1276	static bool dmarInvQueueCanProcessRequests(PCDMAR pThis)
1277	{
1278	/* Check if queued-invalidation is enabled. */
1279	uint32_t const uGstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GSTS_REG);
1280	if (uGstsReg & VTD_BF_GSTS_REG_QIES_MASK)
1281	{
1282	/* Check if there are no invalidation-queue or timeout errors. */
1283	uint32_t const uFstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FSTS_REG);
1284	if (!(uFstsReg & (VTD_BF_FSTS_REG_IQE_MASK \| VTD_BF_FSTS_REG_ITE_MASK)))
1285	return true;
1286	}
1287	return false;
1288	}
1289
1290
1291	/**
1292	* Wakes up the invalidation-queue thread if there are requests to be processed.
1293	*
1294	* @param pDevIns The IOMMU device instance.
1295	*/
1296	static void dmarInvQueueThreadWakeUpIfNeeded(PPDMDEVINS pDevIns)
1297	{
1298	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1299	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1300	LogFlowFunc(("\n"));
1301
1302	DMAR_ASSERT_LOCK_IS_OWNER(pDevIns, pThisCC);
1303
1304	if ( dmarInvQueueCanProcessRequests(pThis)
1305	&& !dmarInvQueueIsEmpty(pThis))
1306	{
1307	Log4Func(("Signaling the invalidation-queue thread\n"));
1308	PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEvtInvQueue);
1309	}
1310	}
1311
1312
1313	/**
1314	* Raises an event on behalf of the DMAR.
1315	*
1316	* These are events that are generated by the DMAR itself (like faults and
1317	* invalidation completion notifications).
1318	*
1319	* @param pDevIns The IOMMU device instance.
1320	* @param enmEventType The DMAR event type.
1321	*
1322	* @remarks The DMAR lock must be held while calling this function.
1323	*/
1324	static void dmarEventRaiseInterrupt(PPDMDEVINS pDevIns, DMAREVENTTYPE enmEventType)
1325	{
1326	uint16_t offCtlReg;
1327	uint32_t fIntrMaskedMask;
1328	uint32_t fIntrPendingMask;
1329	uint16_t offMsiAddrLoReg;
1330	uint16_t offMsiAddrHiReg;
1331	uint16_t offMsiDataReg;
1332	switch (enmEventType)
1333	{
1334	case DMAREVENTTYPE_INV_COMPLETE:
1335	{
1336	offCtlReg = VTD_MMIO_OFF_IECTL_REG;
1337	fIntrMaskedMask = VTD_BF_IECTL_REG_IM_MASK;
1338	fIntrPendingMask = VTD_BF_IECTL_REG_IP_MASK;
1339	offMsiAddrLoReg = VTD_MMIO_OFF_IEADDR_REG;
1340	offMsiAddrHiReg = VTD_MMIO_OFF_IEUADDR_REG;
1341	offMsiDataReg = VTD_MMIO_OFF_IEDATA_REG;
1342	break;
1343	}
1344
1345	case DMAREVENTTYPE_FAULT:
1346	{
1347	offCtlReg = VTD_MMIO_OFF_FECTL_REG;
1348	fIntrMaskedMask = VTD_BF_FECTL_REG_IM_MASK;
1349	fIntrPendingMask = VTD_BF_FECTL_REG_IP_MASK;
1350	offMsiAddrLoReg = VTD_MMIO_OFF_FEADDR_REG;
1351	offMsiAddrHiReg = VTD_MMIO_OFF_FEUADDR_REG;
1352	offMsiDataReg = VTD_MMIO_OFF_FEDATA_REG;
1353	break;
1354	}
1355
1356	default:
1357	{
1358	/* Shouldn't ever happen. */
1359	AssertMsgFailedReturnVoid(("DMAR event type %#x unknown!\n", enmEventType));
1360	}
1361	}
1362
1363	/* Check if software has masked the interrupt. */
1364	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1365	uint32_t uCtlReg = dmarRegReadRaw32(pThis, offCtlReg);
1366	if (!(uCtlReg & fIntrMaskedMask))
1367	{
1368	/*
1369	* Interrupt is unmasked, raise it.
1370	* Interrupts generated by the DMAR have trigger mode and level as 0.
1371	* See Intel spec. 5.1.6 "Remapping Hardware Event Interrupt Programming".
1372	*/
1373	MSIMSG Msi;
1374	Msi.Addr.au32[0] = dmarRegReadRaw32(pThis, offMsiAddrLoReg);
1375	Msi.Addr.au32[1] = (pThis->fExtCapReg & VTD_BF_ECAP_REG_EIM_MASK) ? dmarRegReadRaw32(pThis, offMsiAddrHiReg) : 0;
1376	Msi.Data.u32 = dmarRegReadRaw32(pThis, offMsiDataReg);
1377	Assert(Msi.Data.n.u1Level == 0);
1378	Assert(Msi.Data.n.u1TriggerMode == 0);
1379
1380	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1381	pThisCC->CTX_SUFF(pIommuHlp)->pfnSendMsi(pDevIns, &Msi, 0 /* uTagSrc */);
1382
1383	/* Clear interrupt pending bit. */
1384	uCtlReg &= ~fIntrPendingMask;
1385	dmarRegWriteRaw32(pThis, offCtlReg, uCtlReg);
1386	}
1387	else
1388	{
1389	/* Interrupt is masked, set the interrupt pending bit. */
1390	uCtlReg \|= fIntrPendingMask;
1391	dmarRegWriteRaw32(pThis, offCtlReg, uCtlReg);
1392	}
1393	}
1394
1395
1396	/**
1397	* Raises an interrupt in response to a fault event.
1398	*
1399	* @param pDevIns The IOMMU device instance.
1400	*
1401	* @remarks This assumes the caller has already set the required status bits in the
1402	* FSTS_REG (namely one or more of PPF, PFO, IQE, ICE or ITE bits).
1403	*/
1404	static void dmarFaultEventRaiseInterrupt(PPDMDEVINS pDevIns)
1405	{
1406	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1407	DMAR_ASSERT_LOCK_IS_OWNER(pDevIns, pThisCC);
1408
1409	#ifdef RT_STRICT
1410	{
1411	PCDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PCDMAR);
1412	uint32_t const uFstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FSTS_REG);
1413	uint32_t const fFaultMask = VTD_BF_FSTS_REG_PPF_MASK \| VTD_BF_FSTS_REG_PFO_MASK
1414	/* \| VTD_BF_FSTS_REG_APF_MASK \| VTD_BF_FSTS_REG_AFO_MASK / / AFL not supported */
1415	/* \| VTD_BF_FSTS_REG_ICE_MASK \| VTD_BF_FSTS_REG_ITE_MASK / / Device-TLBs not supported */
1416	\| VTD_BF_FSTS_REG_IQE_MASK;
1417	Assert(uFstsReg & fFaultMask);
1418	}
1419	#endif
1420	dmarEventRaiseInterrupt(pDevIns, DMAREVENTTYPE_FAULT);
1421	}
1422
1423
1424	#ifdef IN_RING3
1425	/**
1426	* Raises an interrupt in response to an invalidation (complete) event.
1427	*
1428	* @param pDevIns The IOMMU device instance.
1429	*/
1430	static void dmarR3InvEventRaiseInterrupt(PPDMDEVINS pDevIns)
1431	{
1432	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1433	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1434	DMAR_ASSERT_LOCK_IS_OWNER(pDevIns, pThisCC);
1435
1436	uint32_t const uIcsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_ICS_REG);
1437	if (!(uIcsReg & VTD_BF_ICS_REG_IWC_MASK))
1438	{
1439	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_ICS_REG, UINT32_MAX, VTD_BF_ICS_REG_IWC_MASK);
1440	dmarEventRaiseInterrupt(pDevIns, DMAREVENTTYPE_INV_COMPLETE);
1441	}
1442	}
1443	#endif /* IN_RING3 */
1444
1445
1446	/**
1447	* Checks if a primary fault can be recorded.
1448	*
1449	* @returns @c true if the fault can be recorded, @c false otherwise.
1450	* @param pDevIns The IOMMU device instance.
1451	* @param pThis The shared DMAR device state.
1452	*
1453	* @remarks Warning: This function has side-effects wrt the DMAR register state. Do
1454	* NOT call it unless there is a fault condition!
1455	*/
1456	static bool dmarPrimaryFaultCanRecord(PPDMDEVINS pDevIns, PDMAR pThis)
1457	{
1458	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1459	DMAR_ASSERT_LOCK_IS_OWNER(pDevIns, pThisCC);
1460
1461	uint32_t uFstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FSTS_REG);
1462	if (uFstsReg & VTD_BF_FSTS_REG_PFO_MASK)
1463	return false;
1464
1465	/*
1466	* If we add more FRCD registers, we'll have to loop through them here.
1467	* Since we support only one FRCD_REG, we don't support "compression of multiple faults",
1468	* nor do we need to increment FRI.
1469	*
1470	* See Intel VT-d spec. 7.2.1 "Primary Fault Logging".
1471	*/
1472	AssertCompile(DMAR_FRCD_REG_COUNT == 1);
1473	uint64_t const uFrcdRegHi = dmarRegReadRaw64(pThis, DMAR_MMIO_OFF_FRCD_HI_REG);
1474	if (uFrcdRegHi & VTD_BF_1_FRCD_REG_F_MASK)
1475	{
1476	uFstsReg \|= VTD_BF_FSTS_REG_PFO_MASK;
1477	dmarRegWriteRaw32(pThis, VTD_MMIO_OFF_FSTS_REG, uFstsReg);
1478	return false;
1479	}
1480
1481	return true;
1482	}
1483
1484
1485	/**
1486	* Records a primary fault.
1487	*
1488	* @param pDevIns The IOMMU device instance.
1489	* @param uFrcdHi The FRCD_HI_REG value for this fault.
1490	* @param uFrcdLo The FRCD_LO_REG value for this fault.
1491	*/
1492	static void dmarPrimaryFaultRecord(PPDMDEVINS pDevIns, uint64_t uFrcdHi, uint64_t uFrcdLo)
1493	{
1494	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1495	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1496
1497	DMAR_LOCK(pDevIns, pThisCC);
1498
1499	/* We don't support advance fault logging. */
1500	Assert(!(dmarRegRead32(pThis, VTD_MMIO_OFF_GSTS_REG) & VTD_BF_GSTS_REG_AFLS_MASK));
1501
1502	if (dmarPrimaryFaultCanRecord(pDevIns, pThis))
1503	{
1504	/* Update the fault recording registers with the fault information. */
1505	dmarRegWriteRaw64(pThis, DMAR_MMIO_OFF_FRCD_HI_REG, uFrcdHi);
1506	dmarRegWriteRaw64(pThis, DMAR_MMIO_OFF_FRCD_LO_REG, uFrcdLo);
1507
1508	/* Set the Pending Primary Fault (PPF) field in the status register. */
1509	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_FSTS_REG, UINT32_MAX, VTD_BF_FSTS_REG_PPF_MASK);
1510
1511	/* Raise interrupt if necessary. */
1512	dmarFaultEventRaiseInterrupt(pDevIns);
1513	}
1514
1515	DMAR_UNLOCK(pDevIns, pThisCC);
1516	}
1517
1518
1519	/**
1520	* Records an interrupt request fault.
1521	*
1522	* @param pDevIns The IOMMU device instance.
1523	* @param enmDiag The diagnostic reason.
1524	* @param idDevice The device ID (bus, device, function).
1525	* @param idxIntr The interrupt index.
1526	* @param pIrte The IRTE that caused this fault. Can be NULL if the fault is
1527	* not qualified.
1528	*/
1529	static void dmarIrFaultRecord(PPDMDEVINS pDevIns, DMARDIAG enmDiag, uint16_t idDevice, uint16_t idxIntr, PCVTD_IRTE_T pIrte)
1530	{
1531	/*
1532	* Update the diagnostic reason (even if software wants to supress faults).
1533	*/
1534	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1535	pThis->enmDiag = enmDiag;
1536
1537	/*
1538	* Figure out the fault reason to report to software from our diagnostic code.
1539	* The case labels below are sorted alphabetically for convenience.
1540	*/
1541	VTDIRFAULT enmIrFault;
1542	switch (enmDiag)
1543	{
1544	case kDmarDiag_Ir_Cfi_Blocked: enmIrFault = VTDIRFAULT_CFI_BLOCKED; break;
1545	case kDmarDiag_Ir_Rfi_Intr_Index_Invalid: enmIrFault = VTDIRFAULT_INTR_INDEX_INVALID; break;
1546	case kDmarDiag_Ir_Rfi_Irte_Mode_Invalid: enmIrFault = VTDIRFAULT_IRTE_PRESENT_RSVD; break;
1547	case kDmarDiag_Ir_Rfi_Irte_Not_Present: enmIrFault = VTDIRFAULT_IRTE_NOT_PRESENT; break;
1548	case kDmarDiag_Ir_Rfi_Irte_Read_Failed: enmIrFault = VTDIRFAULT_IRTE_READ_FAILED; break;
1549	case kDmarDiag_Ir_Rfi_Irte_Rsvd:
1550	case kDmarDiag_Ir_Rfi_Irte_Svt_Bus:
1551	case kDmarDiag_Ir_Rfi_Irte_Svt_Masked:
1552	case kDmarDiag_Ir_Rfi_Irte_Svt_Rsvd: enmIrFault = VTDIRFAULT_IRTE_PRESENT_RSVD; break;
1553	case kDmarDiag_Ir_Rfi_Rsvd: enmIrFault = VTDIRFAULT_REMAPPABLE_INTR_RSVD; break;
1554
1555	/* Shouldn't ever happen. */
1556	default:
1557	{
1558	AssertLogRelMsgFailedReturnVoid(("%s: Invalid interrupt remapping fault diagnostic code %#x\n", DMAR_LOG_PFX,
1559	enmDiag));
1560	}
1561	}
1562
1563	/*
1564	* Qualified faults are those that can be suppressed by software using the FPD bit
1565	* in the interrupt-remapping table entry.
1566	*/
1567	bool fFpd;
1568	bool const fQualifiedFault = vtdIrFaultIsQualified(enmIrFault);
1569	if (fQualifiedFault)
1570	{
1571	AssertReturnVoid(pIrte);
1572	fFpd = RT_BOOL(pIrte->au64[0] & VTD_BF_0_IRTE_FPD_MASK);
1573	}
1574	else
1575	fFpd = false;
1576
1577	if (!fFpd)
1578	{
1579	/* Construct and record the error. */
1580	uint64_t const uFrcdHi = RT_BF_MAKE(VTD_BF_1_FRCD_REG_SID, idDevice)
1581	\| RT_BF_MAKE(VTD_BF_1_FRCD_REG_FR, enmIrFault)
1582	\| RT_BF_MAKE(VTD_BF_1_FRCD_REG_F, 1);
1583	uint64_t const uFrcdLo = (uint64_t)idxIntr << 48;
1584	dmarPrimaryFaultRecord(pDevIns, uFrcdHi, uFrcdLo);
1585	}
1586	}
1587
1588
1589	/**
1590	* Records an address translation fault.
1591	*
1592	* @param pDevIns The IOMMU device instance.
1593	* @param enmDiag The diagnostic reason.
1594	* @param pMemReqIn The DMA memory request input.
1595	* @param pMemReqAux The DMA memory request auxiliary info.
1596	*/
1597	static void dmarAtFaultRecord(PPDMDEVINS pDevIns, DMARDIAG enmDiag, PCDMARMEMREQIN pMemReqIn, PCDMARMEMREQAUX pMemReqAux)
1598	{
1599	/*
1600	* Update the diagnostic reason (even if software wants to supress faults).
1601	*/
1602	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1603	pThis->enmDiag = enmDiag;
1604
1605	/*
1606	* Qualified faults are those that can be suppressed by software using the FPD bit
1607	* in the context entry, scalable-mode context entry etc.
1608	*/
1609	if (!pMemReqAux->fFpd)
1610	{
1611	/*
1612	* Figure out the fault reason to report to software from our diagnostic code.
1613	* The case labels below are sorted alphabetically for convenience.
1614	*/
1615	VTDATFAULT enmAtFault;
1616	bool const fLm = pMemReqAux->fTtm == VTD_TTM_LEGACY_MODE;
1617	switch (enmDiag)
1618	{
1619	/* LM (Legacy Mode) faults. */
1620	case kDmarDiag_At_Lm_CtxEntry_Not_Present: enmAtFault = VTDATFAULT_LCT_2; break;
1621	case kDmarDiag_At_Lm_CtxEntry_Read_Failed: enmAtFault = VTDATFAULT_LCT_1; break;
1622	case kDmarDiag_At_Lm_CtxEntry_Rsvd: enmAtFault = VTDATFAULT_LCT_3; break;
1623	case kDmarDiag_At_Lm_Pt_At_Block: enmAtFault = VTDATFAULT_LCT_5; break;
1624	case kDmarDiag_At_Lm_Pt_Aw_Invalid: enmAtFault = VTDATFAULT_LGN_1_3; break;
1625	case kDmarDiag_At_Lm_RootEntry_Not_Present: enmAtFault = VTDATFAULT_LRT_2; break;
1626	case kDmarDiag_At_Lm_RootEntry_Read_Failed: enmAtFault = VTDATFAULT_LRT_1; break;
1627	case kDmarDiag_At_Lm_RootEntry_Rsvd: enmAtFault = VTDATFAULT_LRT_3; break;
1628	case kDmarDiag_At_Lm_Tt_Invalid: enmAtFault = VTDATFAULT_LCT_4_2; break;
1629	case kDmarDiag_At_Lm_Ut_At_Block: enmAtFault = VTDATFAULT_LCT_5; break;
1630	case kDmarDiag_At_Lm_Ut_Aw_Invalid: enmAtFault = VTDATFAULT_LCT_4_1; break;
1631
1632	/* RTA (Root Table Address) faults. */
1633	case kDmarDiag_At_Rta_Adms_Not_Supported: enmAtFault = VTDATFAULT_RTA_1_1; break;
1634	case kDmarDiag_At_Rta_Rsvd: enmAtFault = VTDATFAULT_RTA_1_2; break;
1635	case kDmarDiag_At_Rta_Smts_Not_Supported: enmAtFault = VTDATFAULT_RTA_1_3; break;
1636
1637	/* XM (Legacy mode or Scalable Mode) faults. */
1638	case kDmarDiag_At_Xm_AddrIn_Invalid: enmAtFault = fLm ? VTDATFAULT_LGN_1_1 : VTDATFAULT_SGN_5; break;
1639	case kDmarDiag_At_Xm_AddrOut_Invalid: enmAtFault = fLm ? VTDATFAULT_LGN_4 : VTDATFAULT_SGN_8; break;
1640	case kDmarDiag_At_Xm_Perm_Denied: enmAtFault = fLm ? VTDATFAULT_LSL_2 : VTDATFAULT_SSL_2; break;
1641	case kDmarDiag_At_Xm_Pte_Rsvd:
1642	case kDmarDiag_At_Xm_Pte_Sllps_Invalid: enmAtFault = fLm ? VTDATFAULT_LSL_2 : VTDATFAULT_SSL_3; break;
1643	case kDmarDiag_At_Xm_Read_Pte_Failed: enmAtFault = fLm ? VTDATFAULT_LSL_1 : VTDATFAULT_SSL_1; break;
1644	case kDmarDiag_At_Xm_Slpptr_Read_Failed: enmAtFault = fLm ? VTDATFAULT_LCT_4_3 : VTDATFAULT_SSL_4; break;
1645
1646	/* Shouldn't ever happen. */
1647	default:
1648	{
1649	AssertLogRelMsgFailedReturnVoid(("%s: Invalid address translation fault diagnostic code %#x\n",
1650	DMAR_LOG_PFX, enmDiag));
1651	}
1652	}
1653
1654	/* Construct and record the error. */
1655	uint16_t const idDevice = pMemReqIn->idDevice;
1656	uint8_t const fType1 = pMemReqIn->enmReqType & RT_BIT(1);
1657	uint8_t const fType2 = pMemReqIn->enmReqType & RT_BIT(0);
1658	uint8_t const fExec = pMemReqIn->AddrRange.fPerm & DMAR_PERM_EXE;
1659	uint8_t const fPriv = pMemReqIn->AddrRange.fPerm & DMAR_PERM_PRIV;
1660	bool const fHasPasid = PCIPASID_IS_VALID(pMemReqIn->Pasid);
1661	uint32_t const uPasid = PCIPASID_VAL(pMemReqIn->Pasid);
1662	PCIADDRTYPE const enmAt = pMemReqIn->enmAddrType;
1663
1664	uint64_t const uFrcdHi = RT_BF_MAKE(VTD_BF_1_FRCD_REG_SID, idDevice)
1665	\| RT_BF_MAKE(VTD_BF_1_FRCD_REG_T2, fType2)
1666	\| RT_BF_MAKE(VTD_BF_1_FRCD_REG_PP, fHasPasid)
1667	\| RT_BF_MAKE(VTD_BF_1_FRCD_REG_EXE, fExec)
1668	\| RT_BF_MAKE(VTD_BF_1_FRCD_REG_PRIV, fPriv)
1669	\| RT_BF_MAKE(VTD_BF_1_FRCD_REG_FR, enmAtFault)
1670	\| RT_BF_MAKE(VTD_BF_1_FRCD_REG_PV, uPasid)
1671	\| RT_BF_MAKE(VTD_BF_1_FRCD_REG_AT, enmAt)
1672	\| RT_BF_MAKE(VTD_BF_1_FRCD_REG_T1, fType1)
1673	\| RT_BF_MAKE(VTD_BF_1_FRCD_REG_F, 1);
1674	uint64_t const uFrcdLo = pMemReqIn->AddrRange.uAddr & X86_PAGE_BASE_MASK;
1675	dmarPrimaryFaultRecord(pDevIns, uFrcdHi, uFrcdLo);
1676	}
1677	}
1678
1679
1680	/**
1681	* Records an IQE fault.
1682	*
1683	* @param pDevIns The IOMMU device instance.
1684	* @param enmIqei The IQE information.
1685	* @param enmDiag The diagnostic reason.
1686	*/
1687	static void dmarIqeFaultRecord(PPDMDEVINS pDevIns, DMARDIAG enmDiag, VTDIQEI enmIqei)
1688	{
1689	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1690	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1691
1692	DMAR_LOCK(pDevIns, pThisCC);
1693
1694	/* Update the diagnostic reason. */
1695	pThis->enmDiag = enmDiag;
1696
1697	/* Set the error bit. */
1698	uint32_t const fIqe = RT_BF_MAKE(VTD_BF_FSTS_REG_IQE, 1);
1699	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_FSTS_REG, UINT32_MAX, fIqe);
1700
1701	/* Set the error information. */
1702	uint64_t const fIqei = RT_BF_MAKE(VTD_BF_IQERCD_REG_IQEI, enmIqei);
1703	dmarRegChangeRaw64(pThis, VTD_MMIO_OFF_IQERCD_REG, UINT64_MAX, fIqei);
1704
1705	dmarFaultEventRaiseInterrupt(pDevIns);
1706
1707	DMAR_UNLOCK(pDevIns, pThisCC);
1708	}
1709
1710
1711	/**
1712	* Handles writes to GCMD_REG.
1713	*
1714	* @returns Strict VBox status code.
1715	* @param pDevIns The IOMMU device instance.
1716	* @param uGcmdReg The value written to GCMD_REG.
1717	*/
1718	static VBOXSTRICTRC dmarGcmdRegWrite(PPDMDEVINS pDevIns, uint32_t uGcmdReg)
1719	{
1720	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1721	uint32_t const uGstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GSTS_REG);
1722	uint32_t const fChanged = uGstsReg ^ uGcmdReg;
1723	uint64_t const fExtCapReg = pThis->fExtCapReg;
1724
1725	/* Queued-invalidation. */
1726	if ( (fExtCapReg & VTD_BF_ECAP_REG_QI_MASK)
1727	&& (fChanged & VTD_BF_GCMD_REG_QIE_MASK))
1728	{
1729	if (uGcmdReg & VTD_BF_GCMD_REG_QIE_MASK)
1730	{
1731	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, UINT32_MAX, VTD_BF_GSTS_REG_QIES_MASK);
1732	dmarInvQueueThreadWakeUpIfNeeded(pDevIns);
1733	}
1734	else
1735	{
1736	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, ~VTD_BF_GSTS_REG_QIES_MASK, 0 /* fOrMask */);
1737	dmarRegWriteRaw32(pThis, VTD_MMIO_OFF_IQH_REG, 0);
1738	}
1739	}
1740
1741	if (fExtCapReg & VTD_BF_ECAP_REG_IR_MASK)
1742	{
1743	/* Set Interrupt Remapping Table Pointer (SIRTP). */
1744	if (uGcmdReg & VTD_BF_GCMD_REG_SIRTP_MASK)
1745	{
1746	/** @todo Perform global invalidation of all interrupt-entry cache when ESIRTPS is
1747	* supported. */
1748	pThis->uIrtaReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IRTA_REG);
1749	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, UINT32_MAX, VTD_BF_GSTS_REG_IRTPS_MASK);
1750	}
1751
1752	/* Interrupt remapping. */
1753	if (fChanged & VTD_BF_GCMD_REG_IRE_MASK)
1754	{
1755	if (uGcmdReg & VTD_BF_GCMD_REG_IRE_MASK)
1756	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, UINT32_MAX, VTD_BF_GSTS_REG_IRES_MASK);
1757	else
1758	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, ~VTD_BF_GSTS_REG_IRES_MASK, 0 /* fOrMask */);
1759	}
1760
1761	/* Compatibility format interrupts. */
1762	if (fChanged & VTD_BF_GCMD_REG_CFI_MASK)
1763	{
1764	if (uGcmdReg & VTD_BF_GCMD_REG_CFI_MASK)
1765	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, UINT32_MAX, VTD_BF_GSTS_REG_CFIS_MASK);
1766	else
1767	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, ~VTD_BF_GSTS_REG_CFIS_MASK, 0 /* fOrMask */);
1768	}
1769	}
1770
1771	/* Set Root Table Pointer (SRTP). */
1772	if (uGcmdReg & VTD_BF_GCMD_REG_SRTP_MASK)
1773	{
1774	/** @todo Perform global invalidation of all remapping translation caches when
1775	* ESRTPS is supported. */
1776	pThis->uRtaddrReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_RTADDR_REG);
1777	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, UINT32_MAX, VTD_BF_GSTS_REG_RTPS_MASK);
1778	}
1779
1780	/* Translation (DMA remapping). */
1781	if (fChanged & VTD_BF_GCMD_REG_TE_MASK)
1782	{
1783	if (uGcmdReg & VTD_BF_GCMD_REG_TE_MASK)
1784	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, UINT32_MAX, VTD_BF_GSTS_REG_TES_MASK);
1785	else
1786	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, ~VTD_BF_GSTS_REG_TES_MASK, 0 /* fOrMask */);
1787	}
1788
1789	return VINF_SUCCESS;
1790	}
1791
1792
1793	/**
1794	* Handles writes to CCMD_REG.
1795	*
1796	* @returns Strict VBox status code.
1797	* @param pDevIns The IOMMU device instance.
1798	* @param offReg The MMIO register offset.
1799	* @param cbReg The size of the MMIO access (in bytes).
1800	* @param uCcmdReg The value written to CCMD_REG.
1801	*/
1802	static VBOXSTRICTRC dmarCcmdRegWrite(PPDMDEVINS pDevIns, uint16_t offReg, uint8_t cbReg, uint64_t uCcmdReg)
1803	{
1804	/* At present, we only care about responding to high 32-bits writes, low 32-bits are data. */
1805	if (offReg + cbReg > VTD_MMIO_OFF_CCMD_REG + 4)
1806	{
1807	/* Check if we need to invalidate the context-context. */
1808	bool const fIcc = RT_BF_GET(uCcmdReg, VTD_BF_CCMD_REG_ICC);
1809	if (fIcc)
1810	{
1811	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1812	uint8_t const uMajorVersion = RT_BF_GET(pThis->uVerReg, VTD_BF_VER_REG_MAX);
1813	if (uMajorVersion < 6)
1814	{
1815	/* Register-based invalidation can only be used when queued-invalidations are not enabled. */
1816	uint32_t const uGstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GSTS_REG);
1817	if (!(uGstsReg & VTD_BF_GSTS_REG_QIES_MASK))
1818	{
1819	/* Verify table translation mode is legacy. */
1820	uint8_t const fTtm = RT_BF_GET(pThis->uRtaddrReg, VTD_BF_RTADDR_REG_TTM);
1821	if (fTtm == VTD_TTM_LEGACY_MODE)
1822	{
1823	/** @todo Invalidate. */
1824	return VINF_SUCCESS;
1825	}
1826	pThis->enmDiag = kDmarDiag_CcmdReg_Ttm_Invalid;
1827	}
1828	else
1829	pThis->enmDiag = kDmarDiag_CcmdReg_Qi_Enabled;
1830	}
1831	else
1832	pThis->enmDiag = kDmarDiag_CcmdReg_Not_Supported;
1833	dmarRegChangeRaw64(pThis, VTD_MMIO_OFF_GSTS_REG, ~VTD_BF_CCMD_REG_CAIG_MASK, 0 /* fOrMask */);
1834	}
1835	}
1836	return VINF_SUCCESS;
1837	}
1838
1839
1840	/**
1841	* Handles writes to FECTL_REG.
1842	*
1843	* @returns Strict VBox status code.
1844	* @param pDevIns The IOMMU device instance.
1845	* @param uFectlReg The value written to FECTL_REG.
1846	*/
1847	static VBOXSTRICTRC dmarFectlRegWrite(PPDMDEVINS pDevIns, uint32_t uFectlReg)
1848	{
1849	/*
1850	* If software unmasks the interrupt when the interrupt is pending, we must raise
1851	* the interrupt now (which will consequently clear the interrupt pending (IP) bit).
1852	*/
1853	if ( (uFectlReg & VTD_BF_FECTL_REG_IP_MASK)
1854	&& ~(uFectlReg & VTD_BF_FECTL_REG_IM_MASK))
1855	dmarEventRaiseInterrupt(pDevIns, DMAREVENTTYPE_FAULT);
1856	return VINF_SUCCESS;
1857	}
1858
1859
1860	/**
1861	* Handles writes to FSTS_REG.
1862	*
1863	* @returns Strict VBox status code.
1864	* @param pDevIns The IOMMU device instance.
1865	* @param uFstsReg The value written to FSTS_REG.
1866	* @param uPrev The value in FSTS_REG prior to writing it.
1867	*/
1868	static VBOXSTRICTRC dmarFstsRegWrite(PPDMDEVINS pDevIns, uint32_t uFstsReg, uint32_t uPrev)
1869	{
1870	/*
1871	* If software clears other status bits in FSTS_REG (pertaining to primary fault logging),
1872	* the interrupt pending (IP) bit must be cleared.
1873	*
1874	* See Intel VT-d spec. 10.4.10 "Fault Event Control Register".
1875	*/
1876	uint32_t const fChanged = uPrev ^ uFstsReg;
1877	if (fChanged & ( VTD_BF_FSTS_REG_ICE_MASK \| VTD_BF_FSTS_REG_ITE_MASK
1878	\| VTD_BF_FSTS_REG_IQE_MASK \| VTD_BF_FSTS_REG_PFO_MASK))
1879	{
1880	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1881	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_FECTL_REG, ~VTD_BF_FECTL_REG_IP_MASK, 0 /* fOrMask */);
1882	}
1883	return VINF_SUCCESS;
1884	}
1885
1886
1887	/**
1888	* Handles writes to IQT_REG.
1889	*
1890	* @returns Strict VBox status code.
1891	* @param pDevIns The IOMMU device instance.
1892	* @param offReg The MMIO register offset.
1893	* @param uIqtReg The value written to IQT_REG.
1894	*/
1895	static VBOXSTRICTRC dmarIqtRegWrite(PPDMDEVINS pDevIns, uint16_t offReg, uint64_t uIqtReg)
1896	{
1897	/* We only care about the low 32-bits, high 32-bits are reserved. */
1898	Assert(offReg == VTD_MMIO_OFF_IQT_REG);
1899	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1900
1901	/* Paranoia. */
1902	Assert(!(uIqtReg & ~VTD_BF_IQT_REG_QT_MASK));
1903
1904	uint32_t const offQt = uIqtReg;
1905	uint64_t const uIqaReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IQA_REG);
1906	uint8_t const fDw = RT_BF_GET(uIqaReg, VTD_BF_IQA_REG_DW);
1907
1908	/* If the descriptor width is 256-bits, the queue tail offset must be aligned accordingly. */
1909	if ( fDw != VTD_IQA_REG_DW_256_BIT
1910	\|\| !(offQt & RT_BIT(4)))
1911	dmarInvQueueThreadWakeUpIfNeeded(pDevIns);
1912	else
1913	{
1914	/* Hardware treats bit 4 as RsvdZ in this situation, so clear it. */
1915	dmarRegChangeRaw32(pThis, offReg, ~RT_BIT(4), 0 /* fOrMask */);
1916	dmarIqeFaultRecord(pDevIns, kDmarDiag_IqtReg_Qt_Not_Aligned, VTDIQEI_QUEUE_TAIL_MISALIGNED);
1917	}
1918	return VINF_SUCCESS;
1919	}
1920
1921
1922	/**
1923	* Handles writes to IQA_REG.
1924	*
1925	* @returns Strict VBox status code.
1926	* @param pDevIns The IOMMU device instance.
1927	* @param offReg The MMIO register offset.
1928	* @param uIqaReg The value written to IQA_REG.
1929	*/
1930	static VBOXSTRICTRC dmarIqaRegWrite(PPDMDEVINS pDevIns, uint16_t offReg, uint64_t uIqaReg)
1931	{
1932	/* At present, we only care about the low 32-bits, high 32-bits are data. */
1933	Assert(offReg == VTD_MMIO_OFF_IQA_REG); NOREF(offReg);
1934
1935	/** @todo What happens if IQA_REG is written when dmarInvQueueCanProcessRequests
1936	* returns true? The Intel VT-d spec. doesn't state anywhere that it
1937	* cannot happen or that it's ignored when it does happen. */
1938
1939	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1940	uint8_t const fDw = RT_BF_GET(uIqaReg, VTD_BF_IQA_REG_DW);
1941	if (fDw == VTD_IQA_REG_DW_256_BIT)
1942	{
1943	bool const fSupports256BitDw = (pThis->fExtCapReg & (VTD_BF_ECAP_REG_SMTS_MASK \| VTD_BF_ECAP_REG_ADMS_MASK));
1944	if (fSupports256BitDw)
1945	{ /* likely */ }
1946	else
1947	dmarIqeFaultRecord(pDevIns, kDmarDiag_IqaReg_Dw_256_Invalid, VTDIQEI_INVALID_DESCRIPTOR_WIDTH);
1948	}
1949	/* else: 128-bit descriptor width is validated lazily, see explanation in dmarR3InvQueueProcessRequests. */
1950
1951	return VINF_SUCCESS;
1952	}
1953
1954
1955	/**
1956	* Handles writes to ICS_REG.
1957	*
1958	* @returns Strict VBox status code.
1959	* @param pDevIns The IOMMU device instance.
1960	* @param uIcsReg The value written to ICS_REG.
1961	*/
1962	static VBOXSTRICTRC dmarIcsRegWrite(PPDMDEVINS pDevIns, uint32_t uIcsReg)
1963	{
1964	/*
1965	* If the IP field is set when software services the interrupt condition,
1966	* (by clearing the IWC field), the IP field must be cleared.
1967	*/
1968	if (!(uIcsReg & VTD_BF_ICS_REG_IWC_MASK))
1969	{
1970	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1971	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_IECTL_REG, ~VTD_BF_IECTL_REG_IP_MASK, 0 /* fOrMask */);
1972	}
1973	return VINF_SUCCESS;
1974	}
1975
1976
1977	/**
1978	* Handles writes to IECTL_REG.
1979	*
1980	* @returns Strict VBox status code.
1981	* @param pDevIns The IOMMU device instance.
1982	* @param uIectlReg The value written to IECTL_REG.
1983	*/
1984	static VBOXSTRICTRC dmarIectlRegWrite(PPDMDEVINS pDevIns, uint32_t uIectlReg)
1985	{
1986	/*
1987	* If software unmasks the interrupt when the interrupt is pending, we must raise
1988	* the interrupt now (which will consequently clear the interrupt pending (IP) bit).
1989	*/
1990	if ( (uIectlReg & VTD_BF_IECTL_REG_IP_MASK)
1991	&& ~(uIectlReg & VTD_BF_IECTL_REG_IM_MASK))
1992	dmarEventRaiseInterrupt(pDevIns, DMAREVENTTYPE_INV_COMPLETE);
1993	return VINF_SUCCESS;
1994	}
1995
1996
1997	/**
1998	* Handles writes to FRCD_REG (High 64-bits).
1999	*
2000	* @returns Strict VBox status code.
2001	* @param pDevIns The IOMMU device instance.
2002	* @param offReg The MMIO register offset.
2003	* @param cbReg The size of the MMIO access (in bytes).
2004	* @param uFrcdHiReg The value written to FRCD_REG.
2005	* @param uPrev The value in FRCD_REG prior to writing it.
2006	*/
2007	static VBOXSTRICTRC dmarFrcdHiRegWrite(PPDMDEVINS pDevIns, uint16_t offReg, uint8_t cbReg, uint64_t uFrcdHiReg, uint64_t uPrev)
2008	{
2009	/* We only care about responding to high 32-bits, low 32-bits are read-only. */
2010	if (offReg + cbReg > DMAR_MMIO_OFF_FRCD_HI_REG + 4)
2011	{
2012	/*
2013	* If software cleared the RW1C F (fault) bit in all FRCD_REGs, hardware clears the
2014	* Primary Pending Fault (PPF) and the interrupt pending (IP) bits. Our implementation
2015	* has only 1 FRCD register.
2016	*
2017	* See Intel VT-d spec. 10.4.10 "Fault Event Control Register".
2018	*/
2019	AssertCompile(DMAR_FRCD_REG_COUNT == 1);
2020	uint64_t const fChanged = uPrev ^ uFrcdHiReg;
2021	if (fChanged & VTD_BF_1_FRCD_REG_F_MASK)
2022	{
2023	Assert(!(uFrcdHiReg & VTD_BF_1_FRCD_REG_F_MASK)); /* Software should only ever be able to clear this bit. */
2024	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
2025	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_FSTS_REG, ~VTD_BF_FSTS_REG_PPF_MASK, 0 /* fOrMask */);
2026	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_FECTL_REG, ~VTD_BF_FECTL_REG_IP_MASK, 0 /* fOrMask */);
2027	}
2028	}
2029	return VINF_SUCCESS;
2030	}
2031
2032
2033	/**
2034	* Performs a PCI target abort for a DMA remapping (DR) operation.
2035	*
2036	* @param pDevIns The IOMMU device instance.
2037	*/
2038	static void dmarDrTargetAbort(PPDMDEVINS pDevIns)
2039	{
2040	/** @todo r=ramshankar: I don't know for sure if a PCI target abort is caused or not
2041	* as the Intel VT-d spec. is vague. Wording seems to suggest it does, but
2042	* who knows. */
2043	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
2044	uint16_t const u16Status = PDMPciDevGetStatus(pPciDev) \| VBOX_PCI_STATUS_SIG_TARGET_ABORT;
2045	PDMPciDevSetStatus(pPciDev, u16Status);
2046	}
2047
2048
2049	/**
2050	* Checks whether the address width (AW) is supported by our hardware
2051	* implementation for legacy mode address translation.
2052	*
2053	* @returns @c true if it's supported, @c false otherwise.
2054	* @param pThis The shared DMAR device state.
2055	* @param pCtxEntry The context entry.
2056	* @param pcPagingLevel Where to store the paging level. Optional, can be NULL.
2057	*/
2058	static bool dmarDrLegacyModeIsAwValid(PCDMAR pThis, PCVTD_CONTEXT_ENTRY_T pCtxEntry, uint8_t *pcPagingLevel)
2059	{
2060	uint8_t const fTt = RT_BF_GET(pCtxEntry->au64[0], VTD_BF_0_CONTEXT_ENTRY_TT);
2061	uint8_t const fAw = RT_BF_GET(pCtxEntry->au64[1], VTD_BF_1_CONTEXT_ENTRY_AW);
2062	uint8_t const fAwMask = RT_BIT(fAw);
2063	uint8_t const fSagaw = RT_BF_GET(pThis->fCapReg, VTD_BF_CAP_REG_SAGAW);
2064	Assert(!(fSagaw & ~(RT_BIT(1) \| RT_BIT(2) \| RT_BIT(3))));
2065
2066	uint8_t const cPagingLevel = fAw + 2;
2067	if (pcPagingLevel)
2068	*pcPagingLevel = cPagingLevel;
2069
2070	/* With pass-through, the address width must be the largest AGAW supported by hardware. */
2071	if (fTt == VTD_TT_UNTRANSLATED_PT)
2072	{
2073	Assert(pThis->cMaxPagingLevel >= 3 && pThis->cMaxPagingLevel <= 5); /* Paranoia. */
2074	return cPagingLevel == pThis->cMaxPagingLevel;
2075	}
2076
2077	/* The address width must be any of the ones supported by hardware. */
2078	if (fAw < 4)
2079	return (fSagaw & fAwMask) != 0;
2080
2081	return false;
2082	}
2083
2084
2085	/**
2086	* Reads a root entry from guest memory.
2087	*
2088	* @returns VBox status code.
2089	* @param pDevIns The IOMMU device instance.
2090	* @param uRtaddrReg The current RTADDR_REG value.
2091	* @param idxRootEntry The index of the root entry to read.
2092	* @param pRootEntry Where to store the read root entry.
2093	*/
2094	static int dmarDrReadRootEntry(PPDMDEVINS pDevIns, uint64_t uRtaddrReg, uint8_t idxRootEntry, PVTD_ROOT_ENTRY_T pRootEntry)
2095	{
2096	size_t const cbRootEntry = sizeof(*pRootEntry);
2097	RTGCPHYS const GCPhysRootEntry = (uRtaddrReg & VTD_BF_RTADDR_REG_RTA_MASK) + (idxRootEntry * cbRootEntry);
2098	return PDMDevHlpPhysReadMeta(pDevIns, GCPhysRootEntry, pRootEntry, cbRootEntry);
2099	}
2100
2101
2102	/**
2103	* Reads a context entry from guest memory.
2104	*
2105	* @returns VBox status code.
2106	* @param pDevIns The IOMMU device instance.
2107	* @param GCPhysCtxTable The physical address of the context table.
2108	* @param idxCtxEntry The index of the context entry to read.
2109	* @param pCtxEntry Where to store the read context entry.
2110	*/
2111	static int dmarDrReadCtxEntry(PPDMDEVINS pDevIns, RTGCPHYS GCPhysCtxTable, uint8_t idxCtxEntry, PVTD_CONTEXT_ENTRY_T pCtxEntry)
2112	{
2113	/* We don't verify bits 63:HAW of GCPhysCtxTable is 0 since reading from such an address should fail anyway. */
2114	size_t const cbCtxEntry = sizeof(*pCtxEntry);
2115	RTGCPHYS const GCPhysCtxEntry = GCPhysCtxTable + (idxCtxEntry * cbCtxEntry);
2116	return PDMDevHlpPhysReadMeta(pDevIns, GCPhysCtxEntry, pCtxEntry, cbCtxEntry);
2117	}
2118
2119
2120	/**
2121	* Validates and updates the output I/O page of a translation.
2122	*
2123	* @returns VBox status code.
2124	* @param pDevIns The IOMMU device instance.
2125	* @param GCPhysBase The output address of the translation.
2126	* @param cShift The page shift of the translated address.
2127	* @param fPerm The permissions granted for the translated region.
2128	* @param pMemReqIn The DMA memory request input.
2129	* @param pMemReqAux The DMA memory request auxiliary info.
2130	* @param pIoPageOut Where to store the output of the translation.
2131	*/
2132	static int dmarDrUpdateIoPageOut(PPDMDEVINS pDevIns, RTGCPHYS GCPhysBase, uint8_t cShift, uint8_t fPerm,
2133	PCDMARMEMREQIN pMemReqIn, PCDMARMEMREQAUX pMemReqAux, PDMARIOPAGE pIoPageOut)
2134	{
2135	Assert(!(GCPhysBase & X86_PAGE_4K_OFFSET_MASK));
2136
2137	/* Ensure the output address is not in the interrupt address range. */
2138	if (GCPhysBase - VBOX_MSI_ADDR_BASE >= VBOX_MSI_ADDR_SIZE)
2139	{
2140	pIoPageOut->GCPhysBase = GCPhysBase;
2141	pIoPageOut->cShift = cShift;
2142	pIoPageOut->fPerm = fPerm;
2143	return VINF_SUCCESS;
2144	}
2145
2146	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Xm_AddrOut_Invalid, pMemReqIn, pMemReqAux);
2147	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2148	}
2149
2150
2151	/**
2152	* Performs second level translation by walking the I/O page tables.
2153	*
2154	* This is a DMA address-lookup callback function which performs the translation
2155	* (and access control) as part of the lookup.
2156	*
2157	* @returns VBox status code.
2158	* @param pDevIns The IOMMU device instance.
2159	* @param pMemReqIn The DMA memory request input.
2160	* @param pMemReqAux The DMA memory request auxiliary info.
2161	* @param pIoPageOut Where to store the output of the translation.
2162	*/
2163	static DECLCALLBACK(int) dmarDrSecondLevelTranslate(PPDMDEVINS pDevIns, PCDMARMEMREQIN pMemReqIn, PCDMARMEMREQAUX pMemReqAux,
2164	PDMARIOPAGE pIoPageOut)
2165	{
2166	PCDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PCDMAR);
2167
2168	/* Sanity. */
2169	Assert(pIoPageOut);
2170	Assert(pMemReqIn->AddrRange.fPerm & (DMAR_PERM_READ \| DMAR_PERM_WRITE));
2171	Assert( pMemReqAux->fTtm == VTD_TTM_LEGACY_MODE
2172	\|\| pMemReqAux->fTtm == VTD_TTM_SCALABLE_MODE);
2173	Assert(!(pMemReqAux->GCPhysSlPt & X86_PAGE_4K_OFFSET_MASK));
2174
2175	/* Mask of reserved paging entry bits. */
2176	static uint64_t const s_auPtEntityInvMasks[] = { ~VTD_SL_PTE_VALID_MASK,
2177	~VTD_SL_PDE_VALID_MASK,
2178	~VTD_SL_PDPE_VALID_MASK,
2179	~VTD_SL_PML4E_VALID_MASK,
2180	~VTD_SL_PML5E_VALID_MASK };
2181
2182	/* Paranoia. */
2183	Assert(pMemReqAux->cPagingLevel >= 3 && pMemReqAux->cPagingLevel <= 5);
2184	AssertCompile(RT_ELEMENTS(s_auPtEntityInvMasks) == 5);
2185
2186	/* Second-level translations restricts input address to an implementation-specific MGAW. */
2187	uint64_t const uAddrIn = pMemReqIn->AddrRange.uAddr;
2188	if (!(uAddrIn & pThis->fMgawInvMask))
2189	{ /* likely */ }
2190	else
2191	{
2192	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Xm_AddrIn_Invalid, pMemReqIn, pMemReqAux);
2193	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2194	}
2195
2196	/*
2197	* Traverse the I/O page table starting with the SLPTPTR (second-level page table pointer).
2198	* Unlike AMD IOMMU paging, here there is no feature for "skipping" levels.
2199	*/
2200	uint64_t uPtEntity = pMemReqAux->GCPhysSlPt;
2201	for (int8_t idxLevel = pMemReqAux->cPagingLevel - 1; idxLevel >= 0; idxLevel--)
2202	{
2203	/*
2204	* Read the paging entry for the current level.
2205	*/
2206	uint8_t const cLevelShift = X86_PAGE_4K_SHIFT + (idxLevel * 9);
2207	{
2208	uint16_t const idxPte = (uAddrIn >> cLevelShift) & UINT64_C(0x1ff);
2209	uint16_t const offPte = idxPte << 3;
2210	RTGCPHYS const GCPhysPtEntity = (uPtEntity & X86_PAGE_4K_BASE_MASK) \| offPte;
2211	int const rc = PDMDevHlpPhysReadMeta(pDevIns, GCPhysPtEntity, &uPtEntity, sizeof(uPtEntity));
2212	if (RT_SUCCESS(rc))
2213	{ /* likely */ }
2214	else
2215	{
2216	if ((GCPhysPtEntity & X86_PAGE_BASE_MASK) == pMemReqAux->GCPhysSlPt)
2217	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Xm_Slpptr_Read_Failed, pMemReqIn, pMemReqAux);
2218	else
2219	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Xm_Read_Pte_Failed, pMemReqIn, pMemReqAux);
2220	break;
2221	}
2222	}
2223
2224	/*
2225	* Check I/O permissions.
2226	* This must be done prior to check reserved bits for properly reporting errors SSL.2 and SSL.3.
2227	* See Intel spec. 7.1.3 "Fault conditions and Remapping hardware behavior for various request".
2228	*/
2229	uint8_t const fReqPerm = pMemReqIn->AddrRange.fPerm & pThis->fPermValidMask;
2230	uint8_t const fPtPerm = uPtEntity & pThis->fPermValidMask;
2231	Assert(!(fReqPerm & DMAR_PERM_EXE)); /* No Execute-requests support yet. */
2232	Assert(!(pThis->fExtCapReg & VTD_BF_ECAP_REG_SLADS_MASK)); /* No Second-level access/dirty support. */
2233	if ((fPtPerm & fReqPerm) == fReqPerm)
2234	{ /* likely */ }
2235	else
2236	{
2237	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Xm_Perm_Denied, pMemReqIn, pMemReqAux);
2238	break;
2239	}
2240
2241	/*
2242	* Validate reserved bits of the current paging entry.
2243	*/
2244	if (!(uPtEntity & s_auPtEntityInvMasks[idxLevel]))
2245	{ /* likely */ }
2246	else
2247	{
2248	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Xm_Pte_Rsvd, pMemReqIn, pMemReqAux);
2249	break;
2250	}
2251
2252	/*
2253	* Check if this is a 1GB page or a 2MB page.
2254	*/
2255	AssertCompile(VTD_BF_SL_PDE_PS_MASK == VTD_BF_SL_PDPE_PS_MASK);
2256	uint8_t const fLargePage = RT_BF_GET(uPtEntity, VTD_BF_SL_PDE_PS);
2257	if (fLargePage && idxLevel > 0)
2258	{
2259	Assert(idxLevel == 1 \|\| idxLevel == 2); /* Is guaranteed by the reserved bits check above. */
2260	uint8_t const fSllpsMask = RT_BF_GET(pThis->fCapReg, VTD_BF_CAP_REG_SLLPS);
2261	if (fSllpsMask & RT_BIT(idxLevel - 1))
2262	{
2263	/*
2264	* We don't support MTS (asserted below), hence IPAT and EMT fields of the paging entity are ignored.
2265	* All other reserved bits are identical to the regular page-size paging entity which we've already
2266	* checked above.
2267	*/
2268	Assert(!(pThis->fExtCapReg & VTD_BF_ECAP_REG_MTS_MASK));
2269
2270	RTGCPHYS const GCPhysBase = uPtEntity & X86_GET_PAGE_BASE_MASK(cLevelShift);
2271	return dmarDrUpdateIoPageOut(pDevIns, GCPhysBase, cLevelShift, fPtPerm, pMemReqIn, pMemReqAux, pIoPageOut);
2272	}
2273
2274	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Xm_Pte_Sllps_Invalid, pMemReqIn, pMemReqAux);
2275	break;
2276	}
2277
2278	/*
2279	* If this is the final PTE, compute the translation address and we're done.
2280	*/
2281	if (idxLevel == 0)
2282	{
2283	RTGCPHYS const GCPhysBase = uPtEntity & X86_GET_PAGE_BASE_MASK(cLevelShift);
2284	return dmarDrUpdateIoPageOut(pDevIns, GCPhysBase, cLevelShift, fPtPerm, pMemReqIn, pMemReqAux, pIoPageOut);
2285	}
2286	}
2287
2288	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2289	}
2290
2291
2292	/**
2293	* Checks whether two consecutive I/O page results of a DMA memory request
2294	* translates to a physically contiguous region.
2295	*
2296	* @returns @c true if the I/O pages are contiguous, @c false otherwise.
2297	* @param pIoPagePrev The previous I/O page.
2298	* @param pIoPage The current I/O page.
2299	*/
2300	static bool dmarIsIoPageAccessContig(PCDMARIOPAGE pIoPagePrev, PCDMARIOPAGE pIoPage)
2301	{
2302	/* Paranoia: Permissions for pages of a DMA memory request must be identical. */
2303	Assert(pIoPagePrev->fPerm == pIoPage->fPerm);
2304
2305	size_t const cbPrev = RT_BIT_64(pIoPagePrev->cShift);
2306	RTGCPHYS const GCPhysPrev = pIoPagePrev->GCPhysBase;
2307	RTGCPHYS const GCPhys = pIoPage->GCPhysBase;
2308	#ifdef RT_STRICT
2309	/* Paranoia: Ensure offset bits are 0. */
2310	{
2311	uint64_t const fOffMaskPrev = X86_GET_PAGE_OFFSET_MASK(pIoPagePrev->cShift);
2312	uint64_t const fOffMask = X86_GET_PAGE_OFFSET_MASK(pIoPage->cShift);
2313	Assert(!(GCPhysPrev & fOffMaskPrev));
2314	Assert(!(GCPhys & fOffMask));
2315	}
2316	#endif
2317	return GCPhysPrev + cbPrev == GCPhys;
2318	}
2319
2320
2321	/**
2322	* Looks up the range of addresses for a DMA memory request remapping.
2323	*
2324	* @returns VBox status code.
2325	* @param pDevIns The IOMMU device instance.
2326	* @param pfnLookup The DMA address lookup function.
2327	* @param pMemReqRemap The DMA memory request remapping info.
2328	*/
2329	static int dmarDrMemRangeLookup(PPDMDEVINS pDevIns, PFNDMADDRLOOKUP pfnLookup, PDMARMEMREQREMAP pMemReqRemap)
2330	{
2331	AssertPtr(pfnLookup);
2332
2333	RTGCPHYS GCPhysAddr = NIL_RTGCPHYS;
2334	DMARMEMREQIN MemReqIn = pMemReqRemap->In;
2335	uint64_t const uAddrIn = MemReqIn.AddrRange.uAddr;
2336	size_t const cbAddrIn = MemReqIn.AddrRange.cb;
2337	uint64_t uAddrInBase = MemReqIn.AddrRange.uAddr & X86_PAGE_4K_BASE_MASK;
2338	uint64_t offAddrIn = MemReqIn.AddrRange.uAddr & X86_PAGE_4K_OFFSET_MASK;
2339	size_t cbRemaining = cbAddrIn;
2340
2341	int rc;
2342	DMARIOPAGE IoPagePrev;
2343	RT_ZERO(IoPagePrev);
2344	for (;;)
2345	{
2346	/* Update the input memory request with the next address in our range that needs translation. */
2347	MemReqIn.AddrRange.uAddr = uAddrInBase;
2348	MemReqIn.AddrRange.cb = cbRemaining; /* Not currently accessed by pfnLookup, but keep things consistent. */
2349
2350	DMARIOPAGE IoPage;
2351	rc = pfnLookup(pDevIns, &MemReqIn, &pMemReqRemap->Aux, &IoPage);
2352	if (RT_SUCCESS(rc))
2353	{
2354	Assert(IoPage.cShift >= X86_PAGE_4K_SHIFT && IoPage.cShift <= X86_PAGE_1G_SHIFT);
2355
2356	/* Store the translated address before continuing to access more pages. */
2357	if (cbRemaining == cbAddrIn)
2358	{
2359	uint64_t const fOffMask = X86_GET_PAGE_OFFSET_MASK(IoPage.cShift);
2360	uint64_t const offAddrOut = uAddrIn & fOffMask;
2361	Assert(!(IoPage.GCPhysBase & fOffMask));
2362	GCPhysAddr = IoPage.GCPhysBase \| offAddrOut;
2363	}
2364	/* Check if addresses translated so far result in a physically contiguous region. */
2365	else if (!dmarIsIoPageAccessContig(&IoPagePrev, &IoPage))
2366	{
2367	rc = VERR_OUT_OF_RANGE;
2368	break;
2369	}
2370
2371	/* Store the I/O page lookup from the first/previous access. */
2372	IoPagePrev = IoPage;
2373
2374	/* Check if we need to access more pages. */
2375	size_t const cbPage = RT_BIT_64(IoPage.cShift);
2376	if (cbRemaining > cbPage - offAddrIn)
2377	{
2378	cbRemaining -= (cbPage - offAddrIn); /* Calculate how much more we need to access. */
2379	uAddrInBase += cbPage; /* Update address of the next access. */
2380	offAddrIn = 0; /* After first page, all pages are accessed from offset 0. */
2381	}
2382	else
2383	{
2384	/* Caller (PDM) doesn't expect more data accessed than what was requested. */
2385	cbRemaining = 0;
2386	break;
2387	}
2388	}
2389	else
2390	break;
2391	}
2392
2393	pMemReqRemap->Out.AddrRange.uAddr = GCPhysAddr;
2394	pMemReqRemap->Out.AddrRange.cb = cbAddrIn - cbRemaining;
2395	pMemReqRemap->Out.AddrRange.fPerm = IoPagePrev.fPerm;
2396	return rc;
2397	}
2398
2399
2400	/**
2401	* Handles legacy mode DMA address remapping.
2402	*
2403	* @returns VBox status code.
2404	* @param pDevIns The IOMMU device instance.
2405	* @param uRtaddrReg The current RTADDR_REG value.
2406	* @param pMemReqRemap The DMA memory request remapping info.
2407	*/
2408	static int dmarDrLegacyModeRemapAddr(PPDMDEVINS pDevIns, uint64_t uRtaddrReg, PDMARMEMREQREMAP pMemReqRemap)
2409	{
2410	PCDMARMEMREQIN pMemReqIn = &pMemReqRemap->In;
2411	PDMARMEMREQAUX pMemReqAux = &pMemReqRemap->Aux;
2412	PDMARMEMREQOUT pMemReqOut = &pMemReqRemap->Out;
2413	Assert(pMemReqAux->fTtm == VTD_TTM_LEGACY_MODE); /* Paranoia. */
2414
2415	/* Read the root-entry from guest memory. */
2416	uint8_t const idxRootEntry = RT_HI_U8(pMemReqIn->idDevice);
2417	VTD_ROOT_ENTRY_T RootEntry;
2418	int rc = dmarDrReadRootEntry(pDevIns, uRtaddrReg, idxRootEntry, &RootEntry);
2419	if (RT_SUCCESS(rc))
2420	{
2421	/* Check if the root entry is present (must be done before validating reserved bits). */
2422	uint64_t const uRootEntryQword0 = RootEntry.au64[0];
2423	uint64_t const uRootEntryQword1 = RootEntry.au64[1];
2424	bool const fRootEntryPresent = RT_BF_GET(uRootEntryQword0, VTD_BF_0_ROOT_ENTRY_P);
2425	if (fRootEntryPresent)
2426	{
2427	/* Validate reserved bits in the root entry. */
2428	if ( !(uRootEntryQword0 & ~VTD_ROOT_ENTRY_0_VALID_MASK)
2429	&& !(uRootEntryQword1 & ~VTD_ROOT_ENTRY_1_VALID_MASK))
2430	{
2431	/* Read the context-entry from guest memory. */
2432	RTGCPHYS const GCPhysCtxTable = uRootEntryQword0 & VTD_BF_0_ROOT_ENTRY_CTP_MASK;
2433	uint8_t const idxCtxEntry = RT_LO_U8(pMemReqIn->idDevice);
2434	VTD_CONTEXT_ENTRY_T CtxEntry;
2435	rc = dmarDrReadCtxEntry(pDevIns, GCPhysCtxTable, idxCtxEntry, &CtxEntry);
2436	if (RT_SUCCESS(rc))
2437	{
2438	uint64_t const uCtxEntryQword0 = CtxEntry.au64[0];
2439	uint64_t const uCtxEntryQword1 = CtxEntry.au64[1];
2440
2441	/* Note the FPD bit which software can use to supress translation faults from here on in. */
2442	pMemReqAux->fFpd = RT_BF_GET(uCtxEntryQword0, VTD_BF_0_CONTEXT_ENTRY_FPD);
2443
2444	/* Check if the context-entry is present (must be done before validating reserved bits). */
2445	bool const fCtxEntryPresent = RT_BF_GET(uCtxEntryQword0, VTD_BF_0_CONTEXT_ENTRY_P);
2446	if (fCtxEntryPresent)
2447	{
2448	/* Validate reserved bits in the context-entry. */
2449	PCDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PCDMAR);
2450	if ( !(uCtxEntryQword0 & ~VTD_CONTEXT_ENTRY_0_VALID_MASK)
2451	&& !(uCtxEntryQword1 & ~pThis->fCtxEntryQw1ValidMask))
2452	{
2453	/* Get the domain ID for this mapping. */
2454	pMemReqOut->idDomain = RT_BF_GET(uCtxEntryQword1, VTD_BF_1_CONTEXT_ENTRY_DID);
2455
2456	/* Validate the translation type (TT). */
2457	uint8_t const fTt = RT_BF_GET(uCtxEntryQword0, VTD_BF_0_CONTEXT_ENTRY_TT);
2458	switch (fTt)
2459	{
2460	case VTD_TT_UNTRANSLATED_SLP:
2461	{
2462	/*
2463	* Untranslated requests are translated using second-level paging structures referenced
2464	* through SLPTPTR. Translated requests and Translation Requests are blocked.
2465	*/
2466	if (pMemReqIn->enmAddrType == PCIADDRTYPE_UNTRANSLATED)
2467	{
2468	/* Validate the address width and get the paging level. */
2469	uint8_t cPagingLevel;
2470	if (dmarDrLegacyModeIsAwValid(pThis, &CtxEntry, &cPagingLevel))
2471	{
2472	/*
2473	* The second-level page table is located at the physical address specified
2474	* in the context entry with which we can finally perform second-level translation.
2475	*/
2476	pMemReqAux->cPagingLevel = cPagingLevel;
2477	pMemReqAux->GCPhysSlPt = uCtxEntryQword0 & VTD_BF_0_CONTEXT_ENTRY_SLPTPTR_MASK;
2478	return dmarDrMemRangeLookup(pDevIns, dmarDrSecondLevelTranslate, pMemReqRemap);
2479	}
2480	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Lm_Ut_Aw_Invalid, pMemReqIn, pMemReqAux);
2481	}
2482	else
2483	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Lm_Ut_At_Block, pMemReqIn, pMemReqAux);
2484	break;
2485	}
2486
2487	case VTD_TT_UNTRANSLATED_PT:
2488	{
2489	/*
2490	* Untranslated requests are processed as pass-through (PT) if PT is supported.
2491	* Translated and translation requests are blocked. If PT isn't supported this TT value
2492	* is reserved which I assume raises a fault (hence fallthru below).
2493	*/
2494	if (pThis->fExtCapReg & VTD_BF_ECAP_REG_PT_MASK)
2495	{
2496	if (pMemReqRemap->In.enmAddrType == PCIADDRTYPE_UNTRANSLATED)
2497	{
2498	if (dmarDrLegacyModeIsAwValid(pThis, &CtxEntry, NULL /* pcPagingLevel */))
2499	{
2500	PDMARMEMREQOUT pOut = &pMemReqRemap->Out;
2501	PCDMARMEMREQIN pIn = &pMemReqRemap->In;
2502	pOut->AddrRange.uAddr = pIn->AddrRange.uAddr;
2503	pOut->AddrRange.cb = pIn->AddrRange.cb;
2504	pOut->AddrRange.fPerm = DMAR_PERM_ALL;
2505	return VINF_SUCCESS;
2506	}
2507	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Lm_Pt_Aw_Invalid, pMemReqIn, pMemReqAux);
2508	}
2509	else
2510	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Lm_Pt_At_Block, pMemReqIn, pMemReqAux);
2511	break;
2512	}
2513	RT_FALL_THRU();
2514	}
2515
2516	case VTD_TT_UNTRANSLATED_DEV_TLB:
2517	{
2518	/*
2519	* Untranslated, translated and translation requests are supported but requires
2520	* device-TLB support. We don't support device-TLBs, so it's treated as reserved.
2521	*/
2522	Assert(!(pThis->fExtCapReg & VTD_BF_ECAP_REG_DT_MASK));
2523	RT_FALL_THRU();
2524	}
2525
2526	default:
2527	{
2528	/* Any other TT value is reserved. */
2529	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Lm_Tt_Invalid, pMemReqIn, pMemReqAux);
2530	break;
2531	}
2532	}
2533	}
2534	else
2535	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Lm_CtxEntry_Rsvd, pMemReqIn, pMemReqAux);
2536	}
2537	else
2538	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Lm_CtxEntry_Not_Present, pMemReqIn, pMemReqAux);
2539	}
2540	else
2541	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Lm_CtxEntry_Read_Failed, pMemReqIn, pMemReqAux);
2542	}
2543	else
2544	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Lm_RootEntry_Rsvd, pMemReqIn, pMemReqAux);
2545	}
2546	else
2547	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Lm_RootEntry_Not_Present, pMemReqIn, pMemReqAux);
2548	}
2549	else
2550	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Lm_RootEntry_Read_Failed, pMemReqIn, pMemReqAux);
2551	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2552	}
2553
2554
2555	/**
2556	* Handles remapping of DMA address requests in scalable mode.
2557	*
2558	* @returns VBox status code.
2559	* @param pDevIns The IOMMU device instance.
2560	* @param uRtaddrReg The current RTADDR_REG value.
2561	* @param pMemReqRemap The DMA memory request remapping info.
2562	*/
2563	static int dmarDrScalableModeRemapAddr(PPDMDEVINS pDevIns, uint64_t uRtaddrReg, PDMARMEMREQREMAP pMemReqRemap)
2564	{
2565	RT_NOREF3(pDevIns, uRtaddrReg, pMemReqRemap);
2566	return VERR_NOT_IMPLEMENTED;
2567	}
2568
2569
2570	/**
2571	* Gets the DMA access permissions and the address-translation request
2572	* type given the PDM IOMMU memory access flags.
2573	*
2574	* @param pDevIns The IOMMU device instance.
2575	* @param fFlags The access flags, see PDMIOMMU_MEM_F_XXX.
2576	* @param fBulk Whether this is a bulk memory access (used for
2577	* statistics).
2578	* @param penmReqType Where to store the address-translation request type.
2579	* @param pfReqPerm Where to store the DMA access permissions.
2580	*/
2581	static void dmarDrGetPermAndReqType(PPDMDEVINS pDevIns, uint32_t fFlags, bool fBulk, PVTDREQTYPE penmReqType, uint8_t *pfReqPerm)
2582	{
2583	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
2584	if (fFlags & PDMIOMMU_MEM_F_READ)
2585	{
2586	*penmReqType = VTDREQTYPE_READ;
2587	*pfReqPerm = DMAR_PERM_READ;
2588	#ifdef VBOX_WITH_STATISTICS
2589	if (!fBulk)
2590	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMemRead));
2591	else
2592	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMemBulkRead));
2593	#else
2594	RT_NOREF2(pThis, fBulk);
2595	#endif
2596	}
2597	else
2598	{
2599	*penmReqType = VTDREQTYPE_WRITE;
2600	*pfReqPerm = DMAR_PERM_WRITE;
2601	#ifdef VBOX_WITH_STATISTICS
2602	if (!fBulk)
2603	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMemWrite));
2604	else
2605	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMemBulkWrite));
2606	#else
2607	RT_NOREF2(pThis, fBulk);
2608	#endif
2609	}
2610	}
2611
2612
2613	/**
2614	* Handles DMA remapping based on the table translation mode (TTM).
2615	*
2616	* @returns VBox status code.
2617	* @param pDevIns The IOMMU device instance.
2618	* @param uRtaddrReg The current RTADDR_REG value.
2619	* @param pMemReqRemap The DMA memory request remapping info.
2620	*/
2621	static int dmarDrMemReqRemap(PPDMDEVINS pDevIns, uint64_t uRtaddrReg, PDMARMEMREQREMAP pMemReqRemap)
2622	{
2623	int rc;
2624	switch (pMemReqRemap->Aux.fTtm)
2625	{
2626	case VTD_TTM_LEGACY_MODE:
2627	{
2628	rc = dmarDrLegacyModeRemapAddr(pDevIns, uRtaddrReg, pMemReqRemap);
2629	break;
2630	}
2631
2632	case VTD_TTM_SCALABLE_MODE:
2633	{
2634	PCDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PCDMAR);
2635	if (pThis->fExtCapReg & VTD_BF_ECAP_REG_SMTS_MASK)
2636	rc = dmarDrScalableModeRemapAddr(pDevIns, uRtaddrReg, pMemReqRemap);
2637	else
2638	{
2639	rc = VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2640	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Rta_Smts_Not_Supported, &pMemReqRemap->In, &pMemReqRemap->Aux);
2641	}
2642	break;
2643	}
2644
2645	case VTD_TTM_ABORT_DMA_MODE:
2646	{
2647	PCDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PCDMAR);
2648	if (pThis->fExtCapReg & VTD_BF_ECAP_REG_ADMS_MASK)
2649	dmarDrTargetAbort(pDevIns);
2650	else
2651	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Rta_Adms_Not_Supported, &pMemReqRemap->In, &pMemReqRemap->Aux);
2652	rc = VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2653	break;
2654	}
2655
2656	default:
2657	{
2658	rc = VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2659	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Rta_Rsvd, &pMemReqRemap->In, &pMemReqRemap->Aux);
2660	break;
2661	}
2662	}
2663	return rc;
2664	}
2665
2666
2667	/**
2668	* Memory access bulk (one or more 4K pages) request from a device.
2669	*
2670	* @returns VBox status code.
2671	* @param pDevIns The IOMMU device instance.
2672	* @param idDevice The device ID (bus, device, function).
2673	* @param cIovas The number of addresses being accessed.
2674	* @param pauIovas The I/O virtual addresses for each page being accessed.
2675	* @param fFlags The access flags, see PDMIOMMU_MEM_F_XXX.
2676	* @param paGCPhysSpa Where to store the translated physical addresses.
2677	*
2678	* @thread Any.
2679	*/
2680	static DECLCALLBACK(int) iommuIntelMemBulkAccess(PPDMDEVINS pDevIns, uint16_t idDevice, size_t cIovas, uint64_t const *pauIovas,
2681	uint32_t fFlags, PRTGCPHYS paGCPhysSpa)
2682	{
2683	/* Validate. */
2684	AssertPtr(pDevIns);
2685	Assert(cIovas > 0);
2686	AssertPtr(pauIovas);
2687	AssertPtr(paGCPhysSpa);
2688	Assert(!(fFlags & ~PDMIOMMU_MEM_F_VALID_MASK));
2689
2690	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
2691	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
2692
2693	DMAR_LOCK(pDevIns, pThisCC);
2694	uint32_t const uGstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GSTS_REG);
2695	uint64_t const uRtaddrReg = pThis->uRtaddrReg;
2696	DMAR_UNLOCK(pDevIns, pThisCC);
2697
2698	if (uGstsReg & VTD_BF_GSTS_REG_TES_MASK)
2699	{
2700	VTDREQTYPE enmReqType;
2701	uint8_t fReqPerm;
2702	dmarDrGetPermAndReqType(pDevIns, fFlags, true /* fBulk */, &enmReqType, &fReqPerm);
2703
2704	DMARMEMREQREMAP MemReqRemap;
2705	RT_ZERO(MemReqRemap);
2706	MemReqRemap.In.AddrRange.cb = X86_PAGE_SIZE;
2707	MemReqRemap.In.AddrRange.fPerm = fReqPerm;
2708	MemReqRemap.In.idDevice = idDevice;
2709	MemReqRemap.In.Pasid = NIL_PCIPASID;
2710	MemReqRemap.In.enmAddrType = PCIADDRTYPE_UNTRANSLATED;
2711	MemReqRemap.In.enmReqType = enmReqType;
2712	MemReqRemap.Aux.fTtm = RT_BF_GET(uRtaddrReg, VTD_BF_RTADDR_REG_TTM);
2713	MemReqRemap.Out.AddrRange.uAddr = NIL_RTGCPHYS;
2714
2715	for (size_t i = 0; i < cIovas; i++)
2716	{
2717	MemReqRemap.In.AddrRange.uAddr = pauIovas[i] & X86_PAGE_BASE_MASK;
2718	int const rc = dmarDrMemReqRemap(pDevIns, uRtaddrReg, &MemReqRemap);
2719	if (RT_SUCCESS(rc))
2720	{
2721	paGCPhysSpa[i] = MemReqRemap.Out.AddrRange.uAddr \| (pauIovas[i] & X86_PAGE_OFFSET_MASK);
2722	Assert(MemReqRemap.Out.AddrRange.cb == MemReqRemap.In.AddrRange.cb);
2723	}
2724	else
2725	{
2726	LogFlowFunc(("idDevice=%#x uIova=%#RX64 fPerm=%#x rc=%Rrc\n", idDevice, pauIovas[i], fReqPerm, rc));
2727	return rc;
2728	}
2729	}
2730	}
2731	else
2732	{
2733	/* Addresses are forwarded without translation when the translation is disabled. */
2734	for (size_t i = 0; i < cIovas; i++)
2735	paGCPhysSpa[i] = pauIovas[i];
2736	}
2737
2738	return VINF_SUCCESS;
2739	}
2740
2741
2742	/**
2743	* Memory access transaction from a device.
2744	*
2745	* @returns VBox status code.
2746	* @param pDevIns The IOMMU device instance.
2747	* @param idDevice The device ID (bus, device, function).
2748	* @param uIova The I/O virtual address being accessed.
2749	* @param cbIova The size of the access.
2750	* @param fFlags The access flags, see PDMIOMMU_MEM_F_XXX.
2751	* @param pGCPhysSpa Where to store the translated system physical address.
2752	* @param pcbContiguous Where to store the number of contiguous bytes translated
2753	* and permission-checked.
2754	*
2755	* @thread Any.
2756	*/
2757	static DECLCALLBACK(int) iommuIntelMemAccess(PPDMDEVINS pDevIns, uint16_t idDevice, uint64_t uIova, size_t cbIova,
2758	uint32_t fFlags, PRTGCPHYS pGCPhysSpa, size_t *pcbContiguous)
2759	{
2760	/* Validate. */
2761	AssertPtr(pDevIns);
2762	AssertPtr(pGCPhysSpa);
2763	AssertPtr(pcbContiguous);
2764	Assert(cbIova > 0); /** @todo Are we going to support ZLR (zero-length reads to write-only pages)? */
2765	Assert(!(fFlags & ~PDMIOMMU_MEM_F_VALID_MASK));
2766
2767	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
2768	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
2769
2770	DMAR_LOCK(pDevIns, pThisCC);
2771	uint32_t const uGstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GSTS_REG);
2772	uint64_t const uRtaddrReg = pThis->uRtaddrReg;
2773	DMAR_UNLOCK(pDevIns, pThisCC);
2774
2775	if (uGstsReg & VTD_BF_GSTS_REG_TES_MASK)
2776	{
2777	VTDREQTYPE enmReqType;
2778	uint8_t fReqPerm;
2779	dmarDrGetPermAndReqType(pDevIns, fFlags, false /* fBulk */, &enmReqType, &fReqPerm);
2780
2781	DMARMEMREQREMAP MemReqRemap;
2782	RT_ZERO(MemReqRemap);
2783	MemReqRemap.In.AddrRange.uAddr = uIova;
2784	MemReqRemap.In.AddrRange.cb = cbIova;
2785	MemReqRemap.In.AddrRange.fPerm = fReqPerm;
2786	MemReqRemap.In.idDevice = idDevice;
2787	MemReqRemap.In.Pasid = NIL_PCIPASID;
2788	MemReqRemap.In.enmAddrType = PCIADDRTYPE_UNTRANSLATED;
2789	MemReqRemap.In.enmReqType = enmReqType;
2790	MemReqRemap.Aux.fTtm = RT_BF_GET(uRtaddrReg, VTD_BF_RTADDR_REG_TTM);
2791	MemReqRemap.Out.AddrRange.uAddr = NIL_RTGCPHYS;
2792
2793	int const rc = dmarDrMemReqRemap(pDevIns, uRtaddrReg, &MemReqRemap);
2794	*pGCPhysSpa = MemReqRemap.Out.AddrRange.uAddr;
2795	*pcbContiguous = MemReqRemap.Out.AddrRange.cb;
2796	return rc;
2797	}
2798
2799	*pGCPhysSpa = uIova;
2800	*pcbContiguous = cbIova;
2801	return VINF_SUCCESS;
2802	}
2803
2804
2805	/**
2806	* Reads an IRTE from guest memory.
2807	*
2808	* @returns VBox status code.
2809	* @param pDevIns The IOMMU device instance.
2810	* @param uIrtaReg The IRTA_REG.
2811	* @param idxIntr The interrupt index.
2812	* @param pIrte Where to store the read IRTE.
2813	*/
2814	static int dmarIrReadIrte(PPDMDEVINS pDevIns, uint64_t uIrtaReg, uint16_t idxIntr, PVTD_IRTE_T pIrte)
2815	{
2816	Assert(idxIntr < VTD_IRTA_REG_GET_ENTRY_COUNT(uIrtaReg));
2817
2818	size_t const cbIrte = sizeof(*pIrte);
2819	RTGCPHYS const GCPhysIrte = (uIrtaReg & VTD_BF_IRTA_REG_IRTA_MASK) + (idxIntr * cbIrte);
2820	return PDMDevHlpPhysReadMeta(pDevIns, GCPhysIrte, pIrte, cbIrte);
2821	}
2822
2823
2824	/**
2825	* Remaps the source MSI to the destination MSI given the IRTE.
2826	*
2827	* @param fExtIntrMode Whether extended interrupt mode is enabled (i.e
2828	* IRTA_REG.EIME).
2829	* @param pIrte The IRTE used for the remapping.
2830	* @param pMsiIn The source MSI (currently unused).
2831	* @param pMsiOut Where to store the remapped MSI.
2832	*/
2833	static void dmarIrRemapFromIrte(bool fExtIntrMode, PCVTD_IRTE_T pIrte, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
2834	{
2835	NOREF(pMsiIn);
2836	uint64_t const uIrteQword0 = pIrte->au64[0];
2837
2838	/*
2839	* Let's start with a clean slate and preserve unspecified bits if the need arises.
2840	* For instance, address bits 1:0 is supposed to be "ignored" by remapping hardware,
2841	* but it's not clear if hardware zeroes out these bits in the remapped MSI or if
2842	* it copies it from the source MSI.
2843	*/
2844	RT_ZERO(*pMsiOut);
2845	pMsiOut->Addr.n.u1DestMode = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_DM);
2846	pMsiOut->Addr.n.u1RedirHint = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_RH);
2847	pMsiOut->Addr.n.u12Addr = VBOX_MSI_ADDR_BASE >> VBOX_MSI_ADDR_SHIFT;
2848	if (fExtIntrMode)
2849	{
2850	/*
2851	* Apparently the DMAR stuffs the high 24-bits of the destination ID into the
2852	* high 24-bits of the upper 32-bits of the message address, see @bugref{9967#c22}.
2853	*/
2854	uint32_t const idDest = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_DST);
2855	pMsiOut->Addr.n.u8DestId = idDest;
2856	pMsiOut->Addr.n.u32Rsvd0 = idDest & UINT32_C(0xffffff00);
2857	}
2858	else
2859	pMsiOut->Addr.n.u8DestId = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_DST_XAPIC);
2860
2861	pMsiOut->Data.n.u8Vector = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_V);
2862	pMsiOut->Data.n.u3DeliveryMode = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_DLM);
2863	pMsiOut->Data.n.u1Level = 1;
2864	pMsiOut->Data.n.u1TriggerMode = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_TM);
2865	}
2866
2867
2868	/**
2869	* Handles remapping of interrupts in remappable interrupt format.
2870	*
2871	* @returns VBox status code.
2872	* @param pDevIns The IOMMU device instance.
2873	* @param uIrtaReg The IRTA_REG.
2874	* @param idDevice The device ID (bus, device, function).
2875	* @param pMsiIn The source MSI.
2876	* @param pMsiOut Where to store the remapped MSI.
2877	*/
2878	static int dmarIrRemapIntr(PPDMDEVINS pDevIns, uint64_t uIrtaReg, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
2879	{
2880	Assert(pMsiIn->Addr.dmar_remap.fIntrFormat == VTD_INTR_FORMAT_REMAPPABLE);
2881
2882	/* Validate reserved bits in the interrupt request. */
2883	AssertCompile(VTD_REMAPPABLE_MSI_ADDR_VALID_MASK == UINT32_MAX);
2884	if (!(pMsiIn->Data.u32 & ~VTD_REMAPPABLE_MSI_DATA_VALID_MASK))
2885	{
2886	/* Compute the index into the interrupt remap table. */
2887	uint16_t const uHandleHi = RT_BF_GET(pMsiIn->Addr.au32[0], VTD_BF_REMAPPABLE_MSI_ADDR_HANDLE_HI);
2888	uint16_t const uHandleLo = RT_BF_GET(pMsiIn->Addr.au32[0], VTD_BF_REMAPPABLE_MSI_ADDR_HANDLE_LO);
2889	uint16_t const uHandle = uHandleLo \| (uHandleHi << 15);
2890	bool const fSubHandleValid = RT_BF_GET(pMsiIn->Addr.au32[0], VTD_BF_REMAPPABLE_MSI_ADDR_SHV);
2891	uint16_t const idxIntr = fSubHandleValid
2892	? uHandle + RT_BF_GET(pMsiIn->Data.u32, VTD_BF_REMAPPABLE_MSI_DATA_SUBHANDLE)
2893	: uHandle;
2894
2895	/* Validate the index. */
2896	uint32_t const cEntries = VTD_IRTA_REG_GET_ENTRY_COUNT(uIrtaReg);
2897	if (idxIntr < cEntries)
2898	{
2899	/** @todo Implement and read IRTE from interrupt-entry cache here. */
2900
2901	/* Read the interrupt remap table entry (IRTE) at the index. */
2902	VTD_IRTE_T Irte;
2903	int rc = dmarIrReadIrte(pDevIns, uIrtaReg, idxIntr, &Irte);
2904	if (RT_SUCCESS(rc))
2905	{
2906	/* Check if the IRTE is present (this must be done -before- checking reserved bits). */
2907	uint64_t const uIrteQword0 = Irte.au64[0];
2908	uint64_t const uIrteQword1 = Irte.au64[1];
2909	bool const fPresent = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_P);
2910	if (fPresent)
2911	{
2912	/* Validate reserved bits in the IRTE. */
2913	bool const fExtIntrMode = RT_BF_GET(uIrtaReg, VTD_BF_IRTA_REG_EIME);
2914	uint64_t const fQw0ValidMask = fExtIntrMode ? VTD_IRTE_0_X2APIC_VALID_MASK : VTD_IRTE_0_XAPIC_VALID_MASK;
2915	if ( !(uIrteQword0 & ~fQw0ValidMask)
2916	&& !(uIrteQword1 & ~VTD_IRTE_1_VALID_MASK))
2917	{
2918	/* Validate requester id (the device ID) as configured in the IRTE. */
2919	bool fSrcValid;
2920	DMARDIAG enmIrDiag;
2921	uint8_t const fSvt = RT_BF_GET(uIrteQword1, VTD_BF_1_IRTE_SVT);
2922	switch (fSvt)
2923	{
2924	case VTD_IRTE_SVT_NONE:
2925	{
2926	fSrcValid = true;
2927	enmIrDiag = kDmarDiag_None;
2928	break;
2929	}
2930
2931	case VTD_IRTE_SVT_VALIDATE_MASK:
2932	{
2933	static uint16_t const s_afValidMasks[] = { 0xffff, 0xfffb, 0xfff9, 0xfff8 };
2934	uint8_t const idxMask = RT_BF_GET(uIrteQword1, VTD_BF_1_IRTE_SQ) & 3;
2935	uint16_t const fValidMask = s_afValidMasks[idxMask];
2936	uint16_t const idSource = RT_BF_GET(uIrteQword1, VTD_BF_1_IRTE_SID);
2937	fSrcValid = (idDevice & fValidMask) == (idSource & fValidMask);
2938	enmIrDiag = kDmarDiag_Ir_Rfi_Irte_Svt_Masked;
2939	break;
2940	}
2941
2942	case VTD_IRTE_SVT_VALIDATE_BUS_RANGE:
2943	{
2944	uint16_t const idSource = RT_BF_GET(uIrteQword1, VTD_BF_1_IRTE_SID);
2945	uint8_t const uBusFirst = RT_HI_U8(idSource);
2946	uint8_t const uBusLast = RT_LO_U8(idSource);
2947	uint8_t const idDeviceBus = idDevice >> VBOX_PCI_BUS_SHIFT;
2948	fSrcValid = (idDeviceBus >= uBusFirst && idDeviceBus <= uBusLast);
2949	enmIrDiag = kDmarDiag_Ir_Rfi_Irte_Svt_Bus;
2950	break;
2951	}
2952
2953	default:
2954	{
2955	fSrcValid = false;
2956	enmIrDiag = kDmarDiag_Ir_Rfi_Irte_Svt_Rsvd;
2957	break;
2958	}
2959	}
2960
2961	if (fSrcValid)
2962	{
2963	uint8_t const fPostedMode = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_IM);
2964	if (!fPostedMode)
2965	{
2966	dmarIrRemapFromIrte(fExtIntrMode, &Irte, pMsiIn, pMsiOut);
2967	return VINF_SUCCESS;
2968	}
2969	dmarIrFaultRecord(pDevIns, kDmarDiag_Ir_Rfi_Irte_Mode_Invalid, idDevice, idxIntr, &Irte);
2970	}
2971	else
2972	dmarIrFaultRecord(pDevIns, enmIrDiag, idDevice, idxIntr, &Irte);
2973	}
2974	else
2975	dmarIrFaultRecord(pDevIns, kDmarDiag_Ir_Rfi_Irte_Rsvd, idDevice, idxIntr, &Irte);
2976	}
2977	else
2978	dmarIrFaultRecord(pDevIns, kDmarDiag_Ir_Rfi_Irte_Not_Present, idDevice, idxIntr, &Irte);
2979	}
2980	else
2981	dmarIrFaultRecord(pDevIns, kDmarDiag_Ir_Rfi_Irte_Read_Failed, idDevice, idxIntr, NULL /* pIrte */);
2982	}
2983	else
2984	dmarIrFaultRecord(pDevIns, kDmarDiag_Ir_Rfi_Intr_Index_Invalid, idDevice, idxIntr, NULL /* pIrte */);
2985	}
2986	else
2987	dmarIrFaultRecord(pDevIns, kDmarDiag_Ir_Rfi_Rsvd, idDevice, 0 /* idxIntr /, NULL / pIrte */);
2988	return VERR_IOMMU_INTR_REMAP_DENIED;
2989	}
2990
2991
2992	/**
2993	* Interrupt remap request from a device.
2994	*
2995	* @returns VBox status code.
2996	* @param pDevIns The IOMMU device instance.
2997	* @param idDevice The device ID (bus, device, function).
2998	* @param pMsiIn The source MSI.
2999	* @param pMsiOut Where to store the remapped MSI.
3000	*/
3001	static DECLCALLBACK(int) iommuIntelMsiRemap(PPDMDEVINS pDevIns, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
3002	{
3003	/* Validate. */
3004	Assert(pDevIns);
3005	Assert(pMsiIn);
3006	Assert(pMsiOut);
3007	RT_NOREF1(idDevice);
3008
3009	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
3010	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
3011
3012	/* Lock and read all registers required for interrupt remapping up-front. */
3013	DMAR_LOCK(pDevIns, pThisCC);
3014	uint32_t const uGstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GSTS_REG);
3015	uint64_t const uIrtaReg = pThis->uIrtaReg;
3016	DMAR_UNLOCK(pDevIns, pThisCC);
3017
3018	/* Check if interrupt remapping is enabled. */
3019	if (uGstsReg & VTD_BF_GSTS_REG_IRES_MASK)
3020	{
3021	bool const fIsRemappable = RT_BF_GET(pMsiIn->Addr.au32[0], VTD_BF_REMAPPABLE_MSI_ADDR_INTR_FMT);
3022	if (!fIsRemappable)
3023	{
3024	/* Handle compatibility format interrupts. */
3025	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMsiRemapCfi));
3026
3027	/* If EIME is enabled or CFIs are disabled, block the interrupt. */
3028	if ( (uIrtaReg & VTD_BF_IRTA_REG_EIME_MASK)
3029	\|\| !(uGstsReg & VTD_BF_GSTS_REG_CFIS_MASK))
3030	{
3031	dmarIrFaultRecord(pDevIns, kDmarDiag_Ir_Cfi_Blocked, VTDIRFAULT_CFI_BLOCKED, idDevice, 0 /* idxIntr */);
3032	return VERR_IOMMU_INTR_REMAP_DENIED;
3033	}
3034
3035	/* Interrupt isn't subject to remapping, pass-through the interrupt. */
3036	pMsiOut = pMsiIn;
3037	return VINF_SUCCESS;
3038	}
3039
3040	/* Handle remappable format interrupts. */
3041	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMsiRemapRfi));
3042	return dmarIrRemapIntr(pDevIns, uIrtaReg, idDevice, pMsiIn, pMsiOut);
3043	}
3044
3045	/* Interrupt-remapping isn't enabled, all interrupts are pass-through. */
3046	pMsiOut = pMsiIn;
3047	return VINF_SUCCESS;
3048	}
3049
3050
3051	/**
3052	* @callback_method_impl{FNIOMMMIONEWWRITE}
3053	*/
3054	static DECLCALLBACK(VBOXSTRICTRC) dmarMmioWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS off, void const pv, unsigned cb)
3055	{
3056	RT_NOREF1(pvUser);
3057	DMAR_ASSERT_MMIO_ACCESS_RET(off, cb);
3058
3059	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
3060	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioWrite));
3061
3062	uint16_t const offReg = off;
3063	uint16_t const offLast = offReg + cb - 1;
3064	if (DMAR_IS_MMIO_OFF_VALID(offLast))
3065	{
3066	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
3067	DMAR_LOCK_RET(pDevIns, pThisCC, VINF_IOM_R3_MMIO_WRITE);
3068
3069	uint64_t uPrev = 0;
3070	uint64_t const uRegWritten = cb == 8 ? dmarRegWrite64(pThis, offReg, (uint64_t )pv, &uPrev)
3071	: dmarRegWrite32(pThis, offReg, (uint32_t )pv, (uint32_t *)&uPrev);
3072	VBOXSTRICTRC rcStrict = VINF_SUCCESS;
3073	switch (off)
3074	{
3075	case VTD_MMIO_OFF_GCMD_REG: /* 32-bit */
3076	{
3077	rcStrict = dmarGcmdRegWrite(pDevIns, uRegWritten);
3078	break;
3079	}
3080
3081	case VTD_MMIO_OFF_CCMD_REG: /* 64-bit */
3082	case VTD_MMIO_OFF_CCMD_REG + 4:
3083	{
3084	rcStrict = dmarCcmdRegWrite(pDevIns, offReg, cb, uRegWritten);
3085	break;
3086	}
3087
3088	case VTD_MMIO_OFF_FSTS_REG: /* 32-bit */
3089	{
3090	rcStrict = dmarFstsRegWrite(pDevIns, uRegWritten, uPrev);
3091	break;
3092	}
3093
3094	case VTD_MMIO_OFF_FECTL_REG: /* 32-bit */
3095	{
3096	rcStrict = dmarFectlRegWrite(pDevIns, uRegWritten);
3097	break;
3098	}
3099
3100	case VTD_MMIO_OFF_IQT_REG: /* 64-bit */
3101	/* VTD_MMIO_OFF_IQT_REG + 4: / / High 32-bits reserved. */
3102	{
3103	rcStrict = dmarIqtRegWrite(pDevIns, offReg, uRegWritten);
3104	break;
3105	}
3106
3107	case VTD_MMIO_OFF_IQA_REG: /* 64-bit */
3108	/* VTD_MMIO_OFF_IQA_REG + 4: / / High 32-bits data. */
3109	{
3110	rcStrict = dmarIqaRegWrite(pDevIns, offReg, uRegWritten);
3111	break;
3112	}
3113
3114	case VTD_MMIO_OFF_ICS_REG: /* 32-bit */
3115	{
3116	rcStrict = dmarIcsRegWrite(pDevIns, uRegWritten);
3117	break;
3118	}
3119
3120	case VTD_MMIO_OFF_IECTL_REG: /* 32-bit */
3121	{
3122	rcStrict = dmarIectlRegWrite(pDevIns, uRegWritten);
3123	break;
3124	}
3125
3126	case DMAR_MMIO_OFF_FRCD_HI_REG: /* 64-bit */
3127	case DMAR_MMIO_OFF_FRCD_HI_REG + 4:
3128	{
3129	rcStrict = dmarFrcdHiRegWrite(pDevIns, offReg, cb, uRegWritten, uPrev);
3130	break;
3131	}
3132	}
3133
3134	DMAR_UNLOCK(pDevIns, pThisCC);
3135	LogFlowFunc(("offReg=%#x uRegWritten=%#RX64 rc=%Rrc\n", offReg, uRegWritten, VBOXSTRICTRC_VAL(rcStrict)));
3136	return rcStrict;
3137	}
3138
3139	return VINF_IOM_MMIO_UNUSED_FF;
3140	}
3141
3142
3143	/**
3144	* @callback_method_impl{FNIOMMMIONEWREAD}
3145	*/
3146	static DECLCALLBACK(VBOXSTRICTRC) dmarMmioRead(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS off, void pv, unsigned cb)
3147	{
3148	RT_NOREF1(pvUser);
3149	DMAR_ASSERT_MMIO_ACCESS_RET(off, cb);
3150
3151	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
3152	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioRead));
3153
3154	uint16_t const offReg = off;
3155	uint16_t const offLast = offReg + cb - 1;
3156	if (DMAR_IS_MMIO_OFF_VALID(offLast))
3157	{
3158	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
3159	DMAR_LOCK_RET(pDevIns, pThisCC, VINF_IOM_R3_MMIO_READ);
3160
3161	if (cb == 8)
3162	{
3163	(uint64_t )pv = dmarRegRead64(pThis, offReg);
3164	LogFlowFunc(("offReg=%#x pv=%#RX64\n", offReg, (uint64_t )pv));
3165	}
3166	else
3167	{
3168	(uint32_t )pv = dmarRegRead32(pThis, offReg);
3169	LogFlowFunc(("offReg=%#x pv=%#RX32\n", offReg, (uint32_t )pv));
3170	}
3171
3172	DMAR_UNLOCK(pDevIns, pThisCC);
3173	return VINF_SUCCESS;
3174	}
3175
3176	return VINF_IOM_MMIO_UNUSED_FF;
3177	}
3178
3179
3180	#ifdef IN_RING3
3181	/**
3182	* Process requests in the invalidation queue.
3183	*
3184	* @param pDevIns The IOMMU device instance.
3185	* @param pvRequests The requests to process.
3186	* @param cbRequests The size of all requests (in bytes).
3187	* @param fDw The descriptor width (VTD_IQA_REG_DW_128_BIT or
3188	* VTD_IQA_REG_DW_256_BIT).
3189	* @param fTtm The table translation mode. Must not be VTD_TTM_RSVD.
3190	*/
3191	static void dmarR3InvQueueProcessRequests(PPDMDEVINS pDevIns, void const *pvRequests, uint32_t cbRequests, uint8_t fDw,
3192	uint8_t fTtm)
3193	{
3194	#define DMAR_IQE_FAULT_RECORD_RET(a_enmDiag, a_enmIqei) \
3195	do \
3196	{ \
3197	dmarIqeFaultRecord(pDevIns, (a_enmDiag), (a_enmIqei)); \
3198	return; \
3199	} while (0)
3200
3201	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
3202	PCDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARR3);
3203
3204	DMAR_ASSERT_LOCK_IS_NOT_OWNER(pDevIns, pThisR3);
3205	Assert(fTtm != VTD_TTM_RSVD); /* Should've beeen handled by caller. */
3206
3207	/*
3208	* The below check is redundant since we check both TTM and DW for each
3209	* descriptor type we process. However, the order of errors reported by hardware
3210	* may differ hence this is kept commented out but not removed if we need to
3211	* change this in the future.
3212	*
3213	* In our implementation, we would report the descriptor type as invalid,
3214	* while on real hardware it may report descriptor width as invalid.
3215	* The Intel VT-d spec. is not clear which error takes preceedence.
3216	*/
3217	#if 0
3218	/*
3219	* Verify that 128-bit descriptors are not used when operating in scalable mode.
3220	* We don't check this while software writes IQA_REG but defer it until now because
3221	* RTADDR_REG can be updated lazily (via GCMD_REG.SRTP). The 256-bit descriptor check
3222	* -IS- performed when software writes IQA_REG since it only requires checking against
3223	* immutable hardware features.
3224	*/
3225	if ( fTtm != VTD_TTM_SCALABLE_MODE
3226	\|\| fDw != VTD_IQA_REG_DW_128_BIT)
3227	{ /* likely */ }
3228	else
3229	DMAR_IQE_FAULT_RECORD_RET(kDmarDiag_IqaReg_Dw_128_Invalid, VTDIQEI_INVALID_DESCRIPTOR_WIDTH);
3230	#endif
3231
3232	/*
3233	* Process requests in FIFO order.
3234	*/
3235	uint8_t const cbDsc = fDw == VTD_IQA_REG_DW_256_BIT ? 32 : 16;
3236	for (uint32_t offDsc = 0; offDsc < cbRequests; offDsc += cbDsc)
3237	{
3238	uint64_t const puDscQwords = (uint64_t const )((uintptr_t)pvRequests + offDsc);
3239	uint64_t const uQword0 = puDscQwords[0];
3240	uint64_t const uQword1 = puDscQwords[1];
3241	uint8_t const fDscType = VTD_GENERIC_INV_DSC_GET_TYPE(uQword0);
3242	switch (fDscType)
3243	{
3244	case VTD_INV_WAIT_DSC_TYPE:
3245	{
3246	/* Validate descriptor type. */
3247	if ( fTtm == VTD_TTM_LEGACY_MODE
3248	\|\| fDw == VTD_IQA_REG_DW_256_BIT)
3249	{ /* likely */ }
3250	else
3251	DMAR_IQE_FAULT_RECORD_RET(kDmarDiag_Iqei_Inv_Wait_Dsc_Invalid, VTDIQEI_INVALID_DESCRIPTOR_TYPE);
3252
3253	/* Validate reserved bits. */
3254	uint64_t const fValidMask0 = !(pThis->fExtCapReg & VTD_BF_ECAP_REG_PDS_MASK)
3255	? VTD_INV_WAIT_DSC_0_VALID_MASK & ~VTD_BF_0_INV_WAIT_DSC_PD_MASK
3256	: VTD_INV_WAIT_DSC_0_VALID_MASK;
3257	if ( !(uQword0 & ~fValidMask0)
3258	&& !(uQword1 & ~VTD_INV_WAIT_DSC_1_VALID_MASK))
3259	{ /* likely */ }
3260	else
3261	DMAR_IQE_FAULT_RECORD_RET(kDmarDiag_Iqei_Inv_Wait_Dsc_0_1_Rsvd, VTDIQEI_RSVD_FIELD_VIOLATION);
3262
3263	if (fDw == VTD_IQA_REG_DW_256_BIT)
3264	{
3265	if ( !puDscQwords[2]
3266	&& !puDscQwords[3])
3267	{ /* likely */ }
3268	else
3269	DMAR_IQE_FAULT_RECORD_RET(kDmarDiag_Iqei_Inv_Wait_Dsc_2_3_Rsvd, VTDIQEI_RSVD_FIELD_VIOLATION);
3270	}
3271
3272	/* Perform status write (this must be done prior to generating the completion interrupt). */
3273	bool const fSw = RT_BF_GET(uQword0, VTD_BF_0_INV_WAIT_DSC_SW);
3274	if (fSw)
3275	{
3276	uint32_t const uStatus = RT_BF_GET(uQword0, VTD_BF_0_INV_WAIT_DSC_STDATA);
3277	RTGCPHYS const GCPhysStatus = uQword1 & VTD_BF_1_INV_WAIT_DSC_STADDR_MASK;
3278	int const rc = PDMDevHlpPhysWrite(pDevIns, GCPhysStatus, (void const*)&uStatus, sizeof(uStatus));
3279	AssertRC(rc);
3280	}
3281
3282	/* Generate invalidation event interrupt. */
3283	bool const fIf = RT_BF_GET(uQword0, VTD_BF_0_INV_WAIT_DSC_IF);
3284	if (fIf)
3285	{
3286	DMAR_LOCK(pDevIns, pThisR3);
3287	dmarR3InvEventRaiseInterrupt(pDevIns);
3288	DMAR_UNLOCK(pDevIns, pThisR3);
3289	}
3290
3291	STAM_COUNTER_INC(&pThis->StatInvWaitDsc);
3292	break;
3293	}
3294
3295	case VTD_CC_INV_DSC_TYPE: STAM_COUNTER_INC(&pThis->StatCcInvDsc); break;
3296	case VTD_IOTLB_INV_DSC_TYPE: STAM_COUNTER_INC(&pThis->StatIotlbInvDsc); break;
3297	case VTD_DEV_TLB_INV_DSC_TYPE: STAM_COUNTER_INC(&pThis->StatDevtlbInvDsc); break;
3298	case VTD_IEC_INV_DSC_TYPE: STAM_COUNTER_INC(&pThis->StatIecInvDsc); break;
3299	case VTD_P_IOTLB_INV_DSC_TYPE: STAM_COUNTER_INC(&pThis->StatPasidIotlbInvDsc); break;
3300	case VTD_PC_INV_DSC_TYPE: STAM_COUNTER_INC(&pThis->StatPasidCacheInvDsc); break;
3301	case VTD_P_DEV_TLB_INV_DSC_TYPE: STAM_COUNTER_INC(&pThis->StatPasidDevtlbInvDsc); break;
3302	default:
3303	{
3304	/* Stop processing further requests. */
3305	LogFunc(("Invalid descriptor type: %#x\n", fDscType));
3306	DMAR_IQE_FAULT_RECORD_RET(kDmarDiag_Iqei_Dsc_Type_Invalid, VTDIQEI_INVALID_DESCRIPTOR_TYPE);
3307	}
3308	}
3309	}
3310	#undef DMAR_IQE_FAULT_RECORD_RET
3311	}
3312
3313
3314	/**
3315	* The invalidation-queue thread.
3316	*
3317	* @returns VBox status code.
3318	* @param pDevIns The IOMMU device instance.
3319	* @param pThread The command thread.
3320	*/
3321	static DECLCALLBACK(int) dmarR3InvQueueThread(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
3322	{
3323	NOREF(pThread);
3324	LogFlowFunc(("\n"));
3325
3326	if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
3327	return VINF_SUCCESS;
3328
3329	/*
3330	* Pre-allocate the maximum size of the invalidation queue allowed by the spec.
3331	* This prevents trashing the heap as well as deal with out-of-memory situations
3332	* up-front while starting the VM. It also simplifies the code from having to
3333	* dynamically grow/shrink the allocation based on how software sizes the queue.
3334	* Guests normally don't alter the queue size all the time, but that's not an
3335	* assumption we can make.
3336	*/
3337	uint8_t const cMaxPages = 1 << VTD_BF_IQA_REG_QS_MASK;
3338	size_t const cbMaxQs = cMaxPages << X86_PAGE_SHIFT;
3339	void *pvRequests = RTMemAllocZ(cbMaxQs);
3340	AssertPtrReturn(pvRequests, VERR_NO_MEMORY);
3341
3342	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
3343	PCDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARR3);
3344
3345	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
3346	{
3347	/*
3348	* Sleep until we are woken up.
3349	*/
3350	{
3351	int const rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->hEvtInvQueue, RT_INDEFINITE_WAIT);
3352	AssertLogRelMsgReturn(RT_SUCCESS(rc) \|\| rc == VERR_INTERRUPTED, ("%Rrc\n", rc), rc);
3353	if (RT_UNLIKELY(pThread->enmState != PDMTHREADSTATE_RUNNING))
3354	break;
3355	}
3356
3357	DMAR_LOCK(pDevIns, pThisR3);
3358	if (dmarInvQueueCanProcessRequests(pThis))
3359	{
3360	uint32_t offQueueHead;
3361	uint32_t offQueueTail;
3362	bool const fIsEmpty = dmarInvQueueIsEmptyEx(pThis, &offQueueHead, &offQueueTail);
3363	if (!fIsEmpty)
3364	{
3365	/*
3366	* Get the current queue size, descriptor width, queue base address and the
3367	* table translation mode while the lock is still held.
3368	*/
3369	uint64_t const uIqaReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IQA_REG);
3370	uint8_t const cQueuePages = 1 << (uIqaReg & VTD_BF_IQA_REG_QS_MASK);
3371	uint32_t const cbQueue = cQueuePages << X86_PAGE_SHIFT;
3372	uint8_t const fDw = RT_BF_GET(uIqaReg, VTD_BF_IQA_REG_DW);
3373	uint8_t const fTtm = RT_BF_GET(pThis->uRtaddrReg, VTD_BF_RTADDR_REG_TTM);
3374	RTGCPHYS const GCPhysRequests = (uIqaReg & VTD_BF_IQA_REG_IQA_MASK) + offQueueHead;
3375
3376	/* Paranoia. */
3377	Assert(cbQueue <= cbMaxQs);
3378	Assert(!(offQueueTail & ~VTD_BF_IQT_REG_QT_MASK));
3379	Assert(!(offQueueHead & ~VTD_BF_IQH_REG_QH_MASK));
3380	Assert(fDw != VTD_IQA_REG_DW_256_BIT \|\| !(offQueueTail & RT_BIT(4)));
3381	Assert(fDw != VTD_IQA_REG_DW_256_BIT \|\| !(offQueueHead & RT_BIT(4)));
3382	Assert(offQueueHead < cbQueue);
3383
3384	/*
3385	* A table translation mode of "reserved" isn't valid for any descriptor type.
3386	* However, RTADDR_REG can be modified in parallel to invalidation-queue processing,
3387	* but if ESRTPS is support, we will perform a global invalidation when software
3388	* changes RTADDR_REG, or it's the responsibility of software to do it explicitly.
3389	* So caching TTM while reading all descriptors should not be a problem.
3390	*
3391	* Also, validate the queue tail offset as it's mutable by software.
3392	*/
3393	if ( fTtm != VTD_TTM_RSVD
3394	&& offQueueTail < cbQueue)
3395	{
3396	/* Don't hold the lock while reading (a potentially large amount of) requests */
3397	DMAR_UNLOCK(pDevIns, pThisR3);
3398
3399	int rc;
3400	uint32_t cbRequests;
3401	if (offQueueTail > offQueueHead)
3402	{
3403	/* The requests have not wrapped around, read them in one go. */
3404	cbRequests = offQueueTail - offQueueHead;
3405	rc = PDMDevHlpPhysReadMeta(pDevIns, GCPhysRequests, pvRequests, cbRequests);
3406	}
3407	else
3408	{
3409	/* The requests have wrapped around, read forward and wrapped-around. */
3410	uint32_t const cbForward = cbQueue - offQueueHead;
3411	rc = PDMDevHlpPhysReadMeta(pDevIns, GCPhysRequests, pvRequests, cbForward);
3412
3413	uint32_t const cbWrapped = offQueueTail;
3414	if ( RT_SUCCESS(rc)
3415	&& cbWrapped > 0)
3416	{
3417	rc = PDMDevHlpPhysReadMeta(pDevIns, GCPhysRequests + cbForward,
3418	(void *)((uintptr_t)pvRequests + cbForward), cbWrapped);
3419	}
3420	cbRequests = cbForward + cbWrapped;
3421	}
3422
3423	/* Re-acquire the lock since we need to update device state. */
3424	DMAR_LOCK(pDevIns, pThisR3);
3425
3426	if (RT_SUCCESS(rc))
3427	{
3428	/* Indicate to software we've fetched all requests. */
3429	dmarRegWriteRaw64(pThis, VTD_MMIO_OFF_IQH_REG, offQueueTail);
3430
3431	/* Don't hold the lock while processing requests. */
3432	DMAR_UNLOCK(pDevIns, pThisR3);
3433
3434	/* Process all requests. */
3435	Assert(cbRequests <= cbQueue);
3436	dmarR3InvQueueProcessRequests(pDevIns, pvRequests, cbRequests, fDw, fTtm);
3437
3438	/*
3439	* We've processed all requests and the lock shouldn't be held at this point.
3440	* Using 'continue' here allows us to skip re-acquiring the lock just to release
3441	* it again before going back to the thread loop. It's a bit ugly but it certainly
3442	* helps with performance.
3443	*/
3444	DMAR_ASSERT_LOCK_IS_NOT_OWNER(pDevIns, pThisR3);
3445	continue;
3446	}
3447	else
3448	dmarIqeFaultRecord(pDevIns, kDmarDiag_IqaReg_Dsc_Fetch_Error, VTDIQEI_FETCH_DESCRIPTOR_ERR);
3449	}
3450	else
3451	{
3452	if (fTtm == VTD_TTM_RSVD)
3453	dmarIqeFaultRecord(pDevIns, kDmarDiag_Iqei_Ttm_Rsvd, VTDIQEI_INVALID_TTM);
3454	else
3455	{
3456	Assert(offQueueTail >= cbQueue);
3457	dmarIqeFaultRecord(pDevIns, kDmarDiag_IqtReg_Qt_Invalid, VTDIQEI_INVALID_TAIL_PTR);
3458	}
3459	}
3460	}
3461	}
3462	DMAR_UNLOCK(pDevIns, pThisR3);
3463	}
3464
3465	RTMemFree(pvRequests);
3466	pvRequests = NULL;
3467
3468	LogFlowFunc(("Invalidation-queue thread terminating\n"));
3469	return VINF_SUCCESS;
3470	}
3471
3472
3473	/**
3474	* Wakes up the invalidation-queue thread so it can respond to a state
3475	* change.
3476	*
3477	* @returns VBox status code.
3478	* @param pDevIns The IOMMU device instance.
3479	* @param pThread The invalidation-queue thread.
3480	*
3481	* @thread EMT.
3482	*/
3483	static DECLCALLBACK(int) dmarR3InvQueueThreadWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
3484	{
3485	RT_NOREF(pThread);
3486	LogFlowFunc(("\n"));
3487	PCDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
3488	return PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEvtInvQueue);
3489	}
3490
3491
3492	/**
3493	* @callback_method_impl{FNDBGFHANDLERDEV}
3494	*/
3495	static DECLCALLBACK(void) dmarR3DbgInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
3496	{
3497	PCDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
3498	PCDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARR3);
3499	bool const fVerbose = RTStrCmp(pszArgs, "verbose") == 0;
3500
3501	/*
3502	* We lock the device to get a consistent register state as it is
3503	* ASSUMED pHlp->pfnPrintf is expensive, so we copy the registers (the
3504	* ones we care about here) into temporaries and release the lock ASAP.
3505	*
3506	* Order of register being read and outputted is in accordance with the
3507	* spec. for no particular reason.
3508	* See Intel VT-d spec. 10.4 "Register Descriptions".
3509	*/
3510	DMAR_LOCK(pDevIns, pThisR3);
3511
3512	DMARDIAG const enmDiag = pThis->enmDiag;
3513	uint32_t const uVerReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_VER_REG);
3514	uint64_t const uCapReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_CAP_REG);
3515	uint64_t const uEcapReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_ECAP_REG);
3516	uint32_t const uGcmdReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GCMD_REG);
3517	uint32_t const uGstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GSTS_REG);
3518	uint64_t const uRtaddrReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_RTADDR_REG);
3519	uint64_t const uCcmdReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_CCMD_REG);
3520	uint32_t const uFstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FSTS_REG);
3521	uint32_t const uFectlReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FECTL_REG);
3522	uint32_t const uFedataReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FEDATA_REG);
3523	uint32_t const uFeaddrReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FEADDR_REG);
3524	uint32_t const uFeuaddrReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FEUADDR_REG);
3525	uint64_t const uAflogReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_AFLOG_REG);
3526	uint32_t const uPmenReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PMEN_REG);
3527	uint32_t const uPlmbaseReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PLMBASE_REG);
3528	uint32_t const uPlmlimitReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PLMLIMIT_REG);
3529	uint64_t const uPhmbaseReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_PHMBASE_REG);
3530	uint64_t const uPhmlimitReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_PHMLIMIT_REG);
3531	uint64_t const uIqhReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IQH_REG);
3532	uint64_t const uIqtReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IQT_REG);
3533	uint64_t const uIqaReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IQA_REG);
3534	uint32_t const uIcsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_ICS_REG);
3535	uint32_t const uIectlReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IECTL_REG);
3536	uint32_t const uIedataReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IEDATA_REG);
3537	uint32_t const uIeaddrReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IEADDR_REG);
3538	uint32_t const uIeuaddrReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IEUADDR_REG);
3539	uint64_t const uIqercdReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IQERCD_REG);
3540	uint64_t const uIrtaReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IRTA_REG);
3541	uint64_t const uPqhReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_PQH_REG);
3542	uint64_t const uPqtReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_PQT_REG);
3543	uint64_t const uPqaReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_PQA_REG);
3544	uint32_t const uPrsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PRS_REG);
3545	uint32_t const uPectlReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PECTL_REG);
3546	uint32_t const uPedataReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PEDATA_REG);
3547	uint32_t const uPeaddrReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PEADDR_REG);
3548	uint32_t const uPeuaddrReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PEUADDR_REG);
3549	uint64_t const uMtrrcapReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_MTRRCAP_REG);
3550	uint64_t const uMtrrdefReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_MTRRDEF_REG);
3551
3552	DMAR_UNLOCK(pDevIns, pThisR3);
3553
3554	const char *const pszDiag = enmDiag < RT_ELEMENTS(g_apszDmarDiagDesc) ? g_apszDmarDiagDesc[enmDiag] : "(Unknown)";
3555	pHlp->pfnPrintf(pHlp, "Intel-IOMMU:\n");
3556	pHlp->pfnPrintf(pHlp, " Diag = %s\n", pszDiag);
3557
3558	/*
3559	* Non-verbose output.
3560	*/
3561	if (!fVerbose)
3562	{
3563	pHlp->pfnPrintf(pHlp, " VER_REG = %#RX32\n", uVerReg);
3564	pHlp->pfnPrintf(pHlp, " CAP_REG = %#RX64\n", uCapReg);
3565	pHlp->pfnPrintf(pHlp, " ECAP_REG = %#RX64\n", uEcapReg);
3566	pHlp->pfnPrintf(pHlp, " GCMD_REG = %#RX32\n", uGcmdReg);
3567	pHlp->pfnPrintf(pHlp, " GSTS_REG = %#RX32\n", uGstsReg);
3568	pHlp->pfnPrintf(pHlp, " RTADDR_REG = %#RX64\n", uRtaddrReg);
3569	pHlp->pfnPrintf(pHlp, " CCMD_REG = %#RX64\n", uCcmdReg);
3570	pHlp->pfnPrintf(pHlp, " FSTS_REG = %#RX32\n", uFstsReg);
3571	pHlp->pfnPrintf(pHlp, " FECTL_REG = %#RX32\n", uFectlReg);
3572	pHlp->pfnPrintf(pHlp, " FEDATA_REG = %#RX32\n", uFedataReg);
3573	pHlp->pfnPrintf(pHlp, " FEADDR_REG = %#RX32\n", uFeaddrReg);
3574	pHlp->pfnPrintf(pHlp, " FEUADDR_REG = %#RX32\n", uFeuaddrReg);
3575	pHlp->pfnPrintf(pHlp, " AFLOG_REG = %#RX64\n", uAflogReg);
3576	pHlp->pfnPrintf(pHlp, " PMEN_REG = %#RX32\n", uPmenReg);
3577	pHlp->pfnPrintf(pHlp, " PLMBASE_REG = %#RX32\n", uPlmbaseReg);
3578	pHlp->pfnPrintf(pHlp, " PLMLIMIT_REG = %#RX32\n", uPlmlimitReg);
3579	pHlp->pfnPrintf(pHlp, " PHMBASE_REG = %#RX64\n", uPhmbaseReg);
3580	pHlp->pfnPrintf(pHlp, " PHMLIMIT_REG = %#RX64\n", uPhmlimitReg);
3581	pHlp->pfnPrintf(pHlp, " IQH_REG = %#RX64\n", uIqhReg);
3582	pHlp->pfnPrintf(pHlp, " IQT_REG = %#RX64\n", uIqtReg);
3583	pHlp->pfnPrintf(pHlp, " IQA_REG = %#RX64\n", uIqaReg);
3584	pHlp->pfnPrintf(pHlp, " ICS_REG = %#RX32\n", uIcsReg);
3585	pHlp->pfnPrintf(pHlp, " IECTL_REG = %#RX32\n", uIectlReg);
3586	pHlp->pfnPrintf(pHlp, " IEDATA_REG = %#RX32\n", uIedataReg);
3587	pHlp->pfnPrintf(pHlp, " IEADDR_REG = %#RX32\n", uIeaddrReg);
3588	pHlp->pfnPrintf(pHlp, " IEUADDR_REG = %#RX32\n", uIeuaddrReg);
3589	pHlp->pfnPrintf(pHlp, " IQERCD_REG = %#RX64\n", uIqercdReg);
3590	pHlp->pfnPrintf(pHlp, " IRTA_REG = %#RX64\n", uIrtaReg);
3591	pHlp->pfnPrintf(pHlp, " PQH_REG = %#RX64\n", uPqhReg);
3592	pHlp->pfnPrintf(pHlp, " PQT_REG = %#RX64\n", uPqtReg);
3593	pHlp->pfnPrintf(pHlp, " PQA_REG = %#RX64\n", uPqaReg);
3594	pHlp->pfnPrintf(pHlp, " PRS_REG = %#RX32\n", uPrsReg);
3595	pHlp->pfnPrintf(pHlp, " PECTL_REG = %#RX32\n", uPectlReg);
3596	pHlp->pfnPrintf(pHlp, " PEDATA_REG = %#RX32\n", uPedataReg);
3597	pHlp->pfnPrintf(pHlp, " PEADDR_REG = %#RX32\n", uPeaddrReg);
3598	pHlp->pfnPrintf(pHlp, " PEUADDR_REG = %#RX32\n", uPeuaddrReg);
3599	pHlp->pfnPrintf(pHlp, " MTRRCAP_REG = %#RX64\n", uMtrrcapReg);
3600	pHlp->pfnPrintf(pHlp, " MTRRDEF_REG = %#RX64\n", uMtrrdefReg);
3601	pHlp->pfnPrintf(pHlp, "\n");
3602	return;
3603	}
3604
3605	/*
3606	* Verbose output.
3607	*/
3608	pHlp->pfnPrintf(pHlp, " VER_REG = %#RX32\n", uVerReg);
3609	{
3610	pHlp->pfnPrintf(pHlp, " MAJ = %#x\n", RT_BF_GET(uVerReg, VTD_BF_VER_REG_MAX));
3611	pHlp->pfnPrintf(pHlp, " MIN = %#x\n", RT_BF_GET(uVerReg, VTD_BF_VER_REG_MIN));
3612	}
3613	pHlp->pfnPrintf(pHlp, " CAP_REG = %#RX64\n", uCapReg);
3614	{
3615	uint8_t const uMgaw = RT_BF_GET(uCapReg, VTD_BF_CAP_REG_MGAW);
3616	uint8_t const uNfr = RT_BF_GET(uCapReg, VTD_BF_CAP_REG_NFR);
3617	pHlp->pfnPrintf(pHlp, " ND = %u\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_ND));
3618	pHlp->pfnPrintf(pHlp, " AFL = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_AFL));
3619	pHlp->pfnPrintf(pHlp, " RWBF = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_RWBF));
3620	pHlp->pfnPrintf(pHlp, " PLMR = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_PLMR));
3621	pHlp->pfnPrintf(pHlp, " PHMR = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_PHMR));
3622	pHlp->pfnPrintf(pHlp, " CM = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_CM));
3623	pHlp->pfnPrintf(pHlp, " SAGAW = %#x\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_SAGAW));
3624	pHlp->pfnPrintf(pHlp, " MGAW = %#x (%u bits)\n", uMgaw, uMgaw + 1);
3625	pHlp->pfnPrintf(pHlp, " ZLR = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_ZLR));
3626	pHlp->pfnPrintf(pHlp, " FRO = %#x bytes\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_FRO));
3627	pHlp->pfnPrintf(pHlp, " SLLPS = %#x\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_SLLPS));
3628	pHlp->pfnPrintf(pHlp, " PSI = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_PSI));
3629	pHlp->pfnPrintf(pHlp, " NFR = %u (%u FRCD register%s)\n", uNfr, uNfr + 1, uNfr > 0 ? "s" : "");
3630	pHlp->pfnPrintf(pHlp, " MAMV = %#x\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_MAMV));
3631	pHlp->pfnPrintf(pHlp, " DWD = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_DWD));
3632	pHlp->pfnPrintf(pHlp, " DRD = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_DRD));
3633	pHlp->pfnPrintf(pHlp, " FL1GP = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_FL1GP));
3634	pHlp->pfnPrintf(pHlp, " PI = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_PI));
3635	pHlp->pfnPrintf(pHlp, " FL5LP = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_FL5LP));
3636	pHlp->pfnPrintf(pHlp, " ESIRTPS = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_ESIRTPS));
3637	pHlp->pfnPrintf(pHlp, " ESRTPS = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_ESRTPS));
3638	}
3639	pHlp->pfnPrintf(pHlp, " ECAP_REG = %#RX64\n", uEcapReg);
3640	{
3641	uint8_t const uPss = RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_PSS);
3642	pHlp->pfnPrintf(pHlp, " C = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_C));
3643	pHlp->pfnPrintf(pHlp, " QI = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_QI));
3644	pHlp->pfnPrintf(pHlp, " DT = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_DT));
3645	pHlp->pfnPrintf(pHlp, " IR = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_IR));
3646	pHlp->pfnPrintf(pHlp, " EIM = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_EIM));
3647	pHlp->pfnPrintf(pHlp, " PT = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_PT));
3648	pHlp->pfnPrintf(pHlp, " SC = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_SC));
3649	pHlp->pfnPrintf(pHlp, " IRO = %#x bytes\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_IRO));
3650	pHlp->pfnPrintf(pHlp, " MHMV = %#x\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_MHMV));
3651	pHlp->pfnPrintf(pHlp, " MTS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_MTS));
3652	pHlp->pfnPrintf(pHlp, " NEST = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_NEST));
3653	pHlp->pfnPrintf(pHlp, " PRS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_PRS));
3654	pHlp->pfnPrintf(pHlp, " ERS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_ERS));
3655	pHlp->pfnPrintf(pHlp, " SRS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_SRS));
3656	pHlp->pfnPrintf(pHlp, " NWFS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_NWFS));
3657	pHlp->pfnPrintf(pHlp, " EAFS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_EAFS));
3658	pHlp->pfnPrintf(pHlp, " PSS = %u (%u bits)\n", uPss, uPss > 0 ? uPss + 1 : 0);
3659	pHlp->pfnPrintf(pHlp, " PASID = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_PASID));
3660	pHlp->pfnPrintf(pHlp, " DIT = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_DIT));
3661	pHlp->pfnPrintf(pHlp, " PDS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_PDS));
3662	pHlp->pfnPrintf(pHlp, " SMTS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_SMTS));
3663	pHlp->pfnPrintf(pHlp, " VCS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_VCS));
3664	pHlp->pfnPrintf(pHlp, " SLADS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_SLADS));
3665	pHlp->pfnPrintf(pHlp, " SLTS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_SLTS));
3666	pHlp->pfnPrintf(pHlp, " FLTS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_FLTS));
3667	pHlp->pfnPrintf(pHlp, " SMPWCS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_SMPWCS));
3668	pHlp->pfnPrintf(pHlp, " RPS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_RPS));
3669	pHlp->pfnPrintf(pHlp, " ADMS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_ADMS));
3670	pHlp->pfnPrintf(pHlp, " RPRIVS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_RPRIVS));
3671	}
3672	pHlp->pfnPrintf(pHlp, " GCMD_REG = %#RX32\n", uGcmdReg);
3673	{
3674	uint8_t const fCfi = RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_CFI);
3675	pHlp->pfnPrintf(pHlp, " CFI = %u (%s)\n", fCfi, fCfi ? "Passthrough" : "Blocked");
3676	pHlp->pfnPrintf(pHlp, " SIRTP = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_SIRTP));
3677	pHlp->pfnPrintf(pHlp, " IRE = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_IRE));
3678	pHlp->pfnPrintf(pHlp, " QIE = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_QIE));
3679	pHlp->pfnPrintf(pHlp, " WBF = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_WBF));
3680	pHlp->pfnPrintf(pHlp, " EAFL = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_SFL));
3681	pHlp->pfnPrintf(pHlp, " SFL = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_SFL));
3682	pHlp->pfnPrintf(pHlp, " SRTP = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_SRTP));
3683	pHlp->pfnPrintf(pHlp, " TE = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_TE));
3684	}
3685	pHlp->pfnPrintf(pHlp, " GSTS_REG = %#RX32\n", uGstsReg);
3686	{
3687	uint8_t const fCfis = RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_CFIS);
3688	pHlp->pfnPrintf(pHlp, " CFIS = %u (%s)\n", fCfis, fCfis ? "Passthrough" : "Blocked");
3689	pHlp->pfnPrintf(pHlp, " IRTPS = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_IRTPS));
3690	pHlp->pfnPrintf(pHlp, " IRES = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_IRES));
3691	pHlp->pfnPrintf(pHlp, " QIES = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_QIES));
3692	pHlp->pfnPrintf(pHlp, " WBFS = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_WBFS));
3693	pHlp->pfnPrintf(pHlp, " AFLS = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_AFLS));
3694	pHlp->pfnPrintf(pHlp, " FLS = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_FLS));
3695	pHlp->pfnPrintf(pHlp, " RTPS = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_RTPS));
3696	pHlp->pfnPrintf(pHlp, " TES = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_TES));
3697	}
3698	pHlp->pfnPrintf(pHlp, " RTADDR_REG = %#RX64\n", uRtaddrReg);
3699	{
3700	uint8_t const uTtm = RT_BF_GET(uRtaddrReg, VTD_BF_RTADDR_REG_TTM);
3701	pHlp->pfnPrintf(pHlp, " RTA = %#RX64\n", uRtaddrReg & VTD_BF_RTADDR_REG_RTA_MASK);
3702	pHlp->pfnPrintf(pHlp, " TTM = %u (%s)\n", uTtm, vtdRtaddrRegGetTtmDesc(uTtm));
3703	}
3704	pHlp->pfnPrintf(pHlp, " CCMD_REG = %#RX64\n", uCcmdReg);
3705	pHlp->pfnPrintf(pHlp, " FSTS_REG = %#RX32\n", uFstsReg);
3706	{
3707	pHlp->pfnPrintf(pHlp, " PFO = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_PFO));
3708	pHlp->pfnPrintf(pHlp, " PPF = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_PPF));
3709	pHlp->pfnPrintf(pHlp, " AFO = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_AFO));
3710	pHlp->pfnPrintf(pHlp, " APF = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_APF));
3711	pHlp->pfnPrintf(pHlp, " IQE = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_IQE));
3712	pHlp->pfnPrintf(pHlp, " ICS = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_ICE));
3713	pHlp->pfnPrintf(pHlp, " ITE = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_ITE));
3714	pHlp->pfnPrintf(pHlp, " FRI = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_FRI));
3715	}
3716	pHlp->pfnPrintf(pHlp, " FECTL_REG = %#RX32\n", uFectlReg);
3717	{
3718	pHlp->pfnPrintf(pHlp, " IM = %RTbool\n", RT_BF_GET(uFectlReg, VTD_BF_FECTL_REG_IM));
3719	pHlp->pfnPrintf(pHlp, " IP = %RTbool\n", RT_BF_GET(uFectlReg, VTD_BF_FECTL_REG_IP));
3720	}
3721	pHlp->pfnPrintf(pHlp, " FEDATA_REG = %#RX32\n", uFedataReg);
3722	pHlp->pfnPrintf(pHlp, " FEADDR_REG = %#RX32\n", uFeaddrReg);
3723	pHlp->pfnPrintf(pHlp, " FEUADDR_REG = %#RX32\n", uFeuaddrReg);
3724	pHlp->pfnPrintf(pHlp, " AFLOG_REG = %#RX64\n", uAflogReg);
3725	pHlp->pfnPrintf(pHlp, " PMEN_REG = %#RX32\n", uPmenReg);
3726	pHlp->pfnPrintf(pHlp, " PLMBASE_REG = %#RX32\n", uPlmbaseReg);
3727	pHlp->pfnPrintf(pHlp, " PLMLIMIT_REG = %#RX32\n", uPlmlimitReg);
3728	pHlp->pfnPrintf(pHlp, " PHMBASE_REG = %#RX64\n", uPhmbaseReg);
3729	pHlp->pfnPrintf(pHlp, " PHMLIMIT_REG = %#RX64\n", uPhmlimitReg);
3730	pHlp->pfnPrintf(pHlp, " IQH_REG = %#RX64\n", uIqhReg);
3731	pHlp->pfnPrintf(pHlp, " IQT_REG = %#RX64\n", uIqtReg);
3732	pHlp->pfnPrintf(pHlp, " IQA_REG = %#RX64\n", uIqaReg);
3733	{
3734	uint8_t const fDw = RT_BF_GET(uIqaReg, VTD_BF_IQA_REG_DW);
3735	uint8_t const fQs = RT_BF_GET(uIqaReg, VTD_BF_IQA_REG_QS);
3736	uint8_t const cQueuePages = 1 << fQs;
3737	pHlp->pfnPrintf(pHlp, " DW = %u (%s)\n", fDw, fDw == VTD_IQA_REG_DW_128_BIT ? "128-bit" : "256-bit");
3738	pHlp->pfnPrintf(pHlp, " QS = %u (%u page%s)\n", fQs, cQueuePages, cQueuePages > 1 ? "s" : "");
3739	}
3740	pHlp->pfnPrintf(pHlp, " ICS_REG = %#RX32\n", uIcsReg);
3741	{
3742	pHlp->pfnPrintf(pHlp, " IWC = %u\n", RT_BF_GET(uIcsReg, VTD_BF_ICS_REG_IWC));
3743	}
3744	pHlp->pfnPrintf(pHlp, " IECTL_REG = %#RX32\n", uIectlReg);
3745	{
3746	pHlp->pfnPrintf(pHlp, " IM = %RTbool\n", RT_BF_GET(uIectlReg, VTD_BF_IECTL_REG_IM));
3747	pHlp->pfnPrintf(pHlp, " IP = %RTbool\n", RT_BF_GET(uIectlReg, VTD_BF_IECTL_REG_IP));
3748	}
3749	pHlp->pfnPrintf(pHlp, " IEDATA_REG = %#RX32\n", uIedataReg);
3750	pHlp->pfnPrintf(pHlp, " IEADDR_REG = %#RX32\n", uIeaddrReg);
3751	pHlp->pfnPrintf(pHlp, " IEUADDR_REG = %#RX32\n", uIeuaddrReg);
3752	pHlp->pfnPrintf(pHlp, " IQERCD_REG = %#RX64\n", uIqercdReg);
3753	{
3754	pHlp->pfnPrintf(pHlp, " ICESID = %#RX32\n", RT_BF_GET(uIqercdReg, VTD_BF_IQERCD_REG_ICESID));
3755	pHlp->pfnPrintf(pHlp, " ITESID = %#RX32\n", RT_BF_GET(uIqercdReg, VTD_BF_IQERCD_REG_ITESID));
3756	pHlp->pfnPrintf(pHlp, " IQEI = %#RX32\n", RT_BF_GET(uIqercdReg, VTD_BF_IQERCD_REG_IQEI));
3757	}
3758	pHlp->pfnPrintf(pHlp, " IRTA_REG = %#RX64\n", uIrtaReg);
3759	{
3760	uint32_t const cIrtEntries = VTD_IRTA_REG_GET_ENTRY_COUNT(uIrtaReg);
3761	uint32_t const cbIrt = sizeof(VTD_IRTE_T) * cIrtEntries;
3762	pHlp->pfnPrintf(pHlp, " IRTA = %#RX64\n", uIrtaReg & VTD_BF_IRTA_REG_IRTA_MASK);
3763	pHlp->pfnPrintf(pHlp, " EIME = %RTbool\n", RT_BF_GET(uIrtaReg, VTD_BF_IRTA_REG_EIME));
3764	pHlp->pfnPrintf(pHlp, " S = %u entries (%u bytes)\n", cIrtEntries, cbIrt);
3765	}
3766	pHlp->pfnPrintf(pHlp, " PQH_REG = %#RX64\n", uPqhReg);
3767	pHlp->pfnPrintf(pHlp, " PQT_REG = %#RX64\n", uPqtReg);
3768	pHlp->pfnPrintf(pHlp, " PQA_REG = %#RX64\n", uPqaReg);
3769	pHlp->pfnPrintf(pHlp, " PRS_REG = %#RX32\n", uPrsReg);
3770	pHlp->pfnPrintf(pHlp, " PECTL_REG = %#RX32\n", uPectlReg);
3771	pHlp->pfnPrintf(pHlp, " PEDATA_REG = %#RX32\n", uPedataReg);
3772	pHlp->pfnPrintf(pHlp, " PEADDR_REG = %#RX32\n", uPeaddrReg);
3773	pHlp->pfnPrintf(pHlp, " PEUADDR_REG = %#RX32\n", uPeuaddrReg);
3774	pHlp->pfnPrintf(pHlp, " MTRRCAP_REG = %#RX64\n", uMtrrcapReg);
3775	pHlp->pfnPrintf(pHlp, " MTRRDEF_REG = %#RX64\n", uMtrrdefReg);
3776	pHlp->pfnPrintf(pHlp, "\n");
3777	}
3778
3779
3780	/**
3781	* Initializes all registers in the DMAR unit.
3782	*
3783	* @param pDevIns The IOMMU device instance.
3784	*/
3785	static void dmarR3RegsInit(PPDMDEVINS pDevIns)
3786	{
3787	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
3788	LogFlowFunc(("\n"));
3789
3790	/*
3791	* Wipe all registers (required on reset).
3792	*/
3793	RT_ZERO(pThis->abRegs0);
3794	RT_ZERO(pThis->abRegs1);
3795
3796	/*
3797	* Initialize registers not mutable by software prior to initializing other registers.
3798	*/
3799	/* VER_REG */
3800	{
3801	pThis->uVerReg = RT_BF_MAKE(VTD_BF_VER_REG_MIN, DMAR_VER_MINOR)
3802	\| RT_BF_MAKE(VTD_BF_VER_REG_MAX, DMAR_VER_MAJOR);
3803	dmarRegWriteRaw64(pThis, VTD_MMIO_OFF_VER_REG, pThis->uVerReg);
3804	}
3805
3806	uint8_t const fFlts = 0; /* First-level translation support. */
3807	uint8_t const fSlts = 1; /* Second-level translation support. */
3808	uint8_t const fPt = 1; /* Pass-Through support. */
3809	uint8_t const fSmts = fFlts & fSlts & fPt; /* Scalable mode translation support.*/
3810	uint8_t const fNest = 0; /* Nested translation support. */
3811
3812	/* CAP_REG */
3813	{
3814	uint8_t cGstPhysAddrBits;
3815	uint8_t cGstLinearAddrBits;
3816	PDMDevHlpCpuGetGuestAddrWidths(pDevIns, &cGstPhysAddrBits, &cGstLinearAddrBits);
3817
3818	uint8_t const fFl1gp = 1; /* First-level 1GB pages support. */
3819	uint8_t const fFl5lp = 1; /* First-level 5-level paging support (PML5E). */
3820	uint8_t const fSl2mp = 1; /* Second-level 2MB pages support. */
3821	uint8_t const fSl2gp = fSl2mp & 1; /* Second-level 1GB pages support. */
3822	uint8_t const fSllps = fSl2mp \| (fSl2gp << 1); /* Second-level large page support. */
3823	uint8_t const fMamv = (fSl2gp ? X86_PAGE_1G_SHIFT /* Maximum address mask value (for 2nd-level invalidations). */
3824	: X86_PAGE_2M_SHIFT)
3825	- X86_PAGE_4K_SHIFT;
3826	uint8_t const fNd = DMAR_ND; /* Number of domains supported. */
3827	uint8_t const fPsi = 1; /* Page selective invalidation. */
3828	uint8_t const uMgaw = cGstPhysAddrBits - 1; /* Maximum guest address width. */
3829	uint8_t const fSagaw = vtdCapRegGetSagaw(uMgaw); /* Supported adjust guest address width. */
3830	uint16_t const offFro = DMAR_MMIO_OFF_FRCD_LO_REG >> 4; /* MMIO offset of FRCD registers. */
3831	uint8_t const fEsrtps = 1; /* Enhanced SRTPS (auto invalidate cache on SRTP). */
3832	uint8_t const fEsirtps = 1; /* Enhanced SIRTPS (auto invalidate cache on SIRTP). */
3833
3834	pThis->fCapReg = RT_BF_MAKE(VTD_BF_CAP_REG_ND, fNd)
3835	\| RT_BF_MAKE(VTD_BF_CAP_REG_AFL, 0) /* Advanced fault logging not supported. */
3836	\| RT_BF_MAKE(VTD_BF_CAP_REG_RWBF, 0) /* Software need not flush write-buffers. */
3837	\| RT_BF_MAKE(VTD_BF_CAP_REG_PLMR, 0) /* Protected Low-Memory Region not supported. */
3838	\| RT_BF_MAKE(VTD_BF_CAP_REG_PHMR, 0) /* Protected High-Memory Region not supported. */
3839	\| RT_BF_MAKE(VTD_BF_CAP_REG_CM, 1) /* Software should invalidate on mapping structure changes. */
3840	\| RT_BF_MAKE(VTD_BF_CAP_REG_SAGAW, fSlts ? fSagaw : 0)
3841	\| RT_BF_MAKE(VTD_BF_CAP_REG_MGAW, uMgaw)
3842	\| RT_BF_MAKE(VTD_BF_CAP_REG_ZLR, 1) /** @todo Figure out if/how to support zero-length reads. */
3843	\| RT_BF_MAKE(VTD_BF_CAP_REG_FRO, offFro)
3844	\| RT_BF_MAKE(VTD_BF_CAP_REG_SLLPS, fSlts & fSllps)
3845	\| RT_BF_MAKE(VTD_BF_CAP_REG_PSI, fPsi)
3846	\| RT_BF_MAKE(VTD_BF_CAP_REG_NFR, DMAR_FRCD_REG_COUNT - 1)
3847	\| RT_BF_MAKE(VTD_BF_CAP_REG_MAMV, fPsi & fMamv)
3848	\| RT_BF_MAKE(VTD_BF_CAP_REG_DWD, 1)
3849	\| RT_BF_MAKE(VTD_BF_CAP_REG_DRD, 1)
3850	\| RT_BF_MAKE(VTD_BF_CAP_REG_FL1GP, fFlts & fFl1gp)
3851	\| RT_BF_MAKE(VTD_BF_CAP_REG_PI, 0) /* Posted Interrupts not supported. */
3852	\| RT_BF_MAKE(VTD_BF_CAP_REG_FL5LP, fFlts & fFl5lp)
3853	\| RT_BF_MAKE(VTD_BF_CAP_REG_ESIRTPS, fEsirtps)
3854	\| RT_BF_MAKE(VTD_BF_CAP_REG_ESRTPS, fEsrtps);
3855	dmarRegWriteRaw64(pThis, VTD_MMIO_OFF_CAP_REG, pThis->fCapReg);
3856
3857	AssertCompile(fNd <= RT_ELEMENTS(g_auNdMask));
3858	pThis->fHawBaseMask = ~(UINT64_MAX << cGstPhysAddrBits) & X86_PAGE_4K_BASE_MASK;
3859	pThis->fMgawInvMask = UINT64_MAX << cGstPhysAddrBits;
3860	pThis->cMaxPagingLevel = vtdCapRegGetMaxPagingLevel(fSagaw);
3861	pThis->fCtxEntryQw1ValidMask = VTD_BF_1_CONTEXT_ENTRY_AW_MASK
3862	\| VTD_BF_1_CONTEXT_ENTRY_IGN_6_3_MASK
3863	\| RT_BF_MAKE(VTD_BF_1_CONTEXT_ENTRY_DID, g_auNdMask[fNd]);
3864	}
3865
3866	/* ECAP_REG */
3867	{
3868	uint8_t const fQi = 1; /* Queued-invalidations. */
3869	uint8_t const fIr = !!(DMAR_ACPI_DMAR_FLAGS & ACPI_DMAR_F_INTR_REMAP); /* Interrupt remapping support. */
3870	uint8_t const fMhmv = 0xf; /* Maximum handle mask value. */
3871	uint16_t const offIro = DMAR_MMIO_OFF_IVA_REG >> 4; /* MMIO offset of IOTLB registers. */
3872	uint8_t const fEim = 1; /* Extended interrupt mode.*/
3873	uint8_t const fAdms = 1; /* Abort DMA mode support. */
3874	uint8_t const fErs = 0; /* Execute Request (not supported). */
3875
3876	pThis->fExtCapReg = RT_BF_MAKE(VTD_BF_ECAP_REG_C, 0) /* Accesses don't snoop CPU cache. */
3877	\| RT_BF_MAKE(VTD_BF_ECAP_REG_QI, fQi)
3878	\| RT_BF_MAKE(VTD_BF_ECAP_REG_DT, 0) /* Device-TLBs not supported. */
3879	\| RT_BF_MAKE(VTD_BF_ECAP_REG_IR, fQi & fIr)
3880	\| RT_BF_MAKE(VTD_BF_ECAP_REG_EIM, fIr & fEim)
3881	\| RT_BF_MAKE(VTD_BF_ECAP_REG_PT, fPt)
3882	\| RT_BF_MAKE(VTD_BF_ECAP_REG_SC, 0) /* Snoop control not supported. */
3883	\| RT_BF_MAKE(VTD_BF_ECAP_REG_IRO, offIro)
3884	\| RT_BF_MAKE(VTD_BF_ECAP_REG_MHMV, fIr & fMhmv)
3885	\| RT_BF_MAKE(VTD_BF_ECAP_REG_MTS, 0) /* Memory type not supported. */
3886	\| RT_BF_MAKE(VTD_BF_ECAP_REG_NEST, fNest)
3887	\| RT_BF_MAKE(VTD_BF_ECAP_REG_PRS, 0) /* 0 as DT not supported. */
3888	\| RT_BF_MAKE(VTD_BF_ECAP_REG_ERS, fErs)
3889	\| RT_BF_MAKE(VTD_BF_ECAP_REG_SRS, 0) /* Supervisor request not supported. */
3890	\| RT_BF_MAKE(VTD_BF_ECAP_REG_NWFS, 0) /* 0 as DT not supported. */
3891	\| RT_BF_MAKE(VTD_BF_ECAP_REG_EAFS, 0) /* 0 as SMPWCS not supported. */
3892	\| RT_BF_MAKE(VTD_BF_ECAP_REG_PSS, 0) /* 0 as PASID not supported. */
3893	\| RT_BF_MAKE(VTD_BF_ECAP_REG_PASID, 0) /* PASID not supported. */
3894	\| RT_BF_MAKE(VTD_BF_ECAP_REG_DIT, 0) /* 0 as DT not supported. */
3895	\| RT_BF_MAKE(VTD_BF_ECAP_REG_PDS, 0) /* 0 as DT not supported. */
3896	\| RT_BF_MAKE(VTD_BF_ECAP_REG_SMTS, fSmts)
3897	\| RT_BF_MAKE(VTD_BF_ECAP_REG_VCS, 0) /* 0 as PASID not supported (commands seem PASID specific). */
3898	\| RT_BF_MAKE(VTD_BF_ECAP_REG_SLADS, 0) /* Second-level accessed/dirty not supported. */
3899	\| RT_BF_MAKE(VTD_BF_ECAP_REG_SLTS, fSlts)
3900	\| RT_BF_MAKE(VTD_BF_ECAP_REG_FLTS, fFlts)
3901	\| RT_BF_MAKE(VTD_BF_ECAP_REG_SMPWCS, 0) /* 0 as PASID not supported. */
3902	\| RT_BF_MAKE(VTD_BF_ECAP_REG_RPS, 0) /* We don't support RID_PASID field in SM context entry. */
3903	\| RT_BF_MAKE(VTD_BF_ECAP_REG_ADMS, fAdms)
3904	\| RT_BF_MAKE(VTD_BF_ECAP_REG_RPRIVS, 0); /* 0 as SRS not supported. */
3905	dmarRegWriteRaw64(pThis, VTD_MMIO_OFF_ECAP_REG, pThis->fExtCapReg);
3906
3907	pThis->fPermValidMask = DMAR_PERM_READ \| DMAR_PERM_WRITE;
3908	if (fErs)
3909	pThis->fPermValidMask = DMAR_PERM_EXE;
3910	}
3911
3912	/*
3913	* Initialize registers mutable by software.
3914	*/
3915	/* FECTL_REG */
3916	{
3917	uint32_t const uCtl = RT_BF_MAKE(VTD_BF_FECTL_REG_IM, 1);
3918	dmarRegWriteRaw32(pThis, VTD_MMIO_OFF_FECTL_REG, uCtl);
3919	}
3920
3921	/* ICETL_REG */
3922	{
3923	uint32_t const uCtl = RT_BF_MAKE(VTD_BF_IECTL_REG_IM, 1);
3924	dmarRegWriteRaw32(pThis, VTD_MMIO_OFF_IECTL_REG, uCtl);
3925	}
3926
3927	#ifdef VBOX_STRICT
3928	Assert(!RT_BF_GET(pThis->fExtCapReg, VTD_BF_ECAP_REG_PRS)); /* PECTL_REG - Reserved if don't support PRS. */
3929	Assert(!RT_BF_GET(pThis->fExtCapReg, VTD_BF_ECAP_REG_MTS)); /* MTRRCAP_REG - Reserved if we don't support MTS. */
3930	#endif
3931	}
3932
3933
3934	/**
3935	* @callback_method_impl{FNSSMDEVSAVEEXEC}
3936	*/
3937	static DECLCALLBACK(int) dmarR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
3938	{
3939	PCDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PCDMAR);
3940	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
3941	LogFlowFunc(("\n"));
3942
3943	/* First, save software-immutable registers that we validate on state load. */
3944	pHlp->pfnSSMPutU32(pSSM, pThis->uVerReg);
3945	pHlp->pfnSSMPutU64(pSSM, pThis->fCapReg);
3946	pHlp->pfnSSMPutU64(pSSM, pThis->fExtCapReg);
3947
3948	/* Save MMIO registers. */
3949	pHlp->pfnSSMPutU32(pSSM, DMAR_MMIO_GROUP_COUNT);
3950	pHlp->pfnSSMPutU32(pSSM, sizeof(pThis->abRegs0));
3951	pHlp->pfnSSMPutMem(pSSM, &pThis->abRegs0[0], sizeof(pThis->abRegs0));
3952	pHlp->pfnSSMPutU32(pSSM, sizeof(pThis->abRegs1));
3953	pHlp->pfnSSMPutMem(pSSM, &pThis->abRegs1[0], sizeof(pThis->abRegs1));
3954
3955	/*
3956	* Save our implemention-defined MMIO registers offsets.
3957	* The register themselves are currently all part of group 1 (saved above).
3958	* We save these to ensure they're located where the code expects them while loading state.
3959	*/
3960	pHlp->pfnSSMPutU16(pSSM, DMAR_MMIO_OFF_IMPL_COUNT);
3961	AssertCompile(DMAR_MMIO_OFF_IMPL_COUNT == 2);
3962	pHlp->pfnSSMPutU16(pSSM, DMAR_MMIO_OFF_IVA_REG);
3963	pHlp->pfnSSMPutU16(pSSM, DMAR_MMIO_OFF_FRCD_LO_REG);
3964
3965	/* Save lazily activated registers. */
3966	pHlp->pfnSSMPutU64(pSSM, pThis->uIrtaReg);
3967	pHlp->pfnSSMPutU64(pSSM, pThis->uRtaddrReg);
3968
3969	/* Save terminator marker and return status. */
3970	return pHlp->pfnSSMPutU32(pSSM, UINT32_MAX);
3971	}
3972
3973
3974	/**
3975	* @callback_method_impl{FNSSMDEVLOADEXEC}
3976	*/
3977	static DECLCALLBACK(int) dmarR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
3978	{
3979	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
3980	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
3981	int const rcDataErr = VERR_SSM_UNEXPECTED_DATA;
3982	int const rcFmtErr = VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
3983	LogFlowFunc(("\n"));
3984
3985	/*
3986	* Validate saved-state version.
3987	*/
3988	AssertReturn(uPass == SSM_PASS_FINAL, VERR_WRONG_ORDER);
3989	if (uVersion != DMAR_SAVED_STATE_VERSION)
3990	{
3991	LogRel(("%s: Invalid saved-state version %#x\n", DMAR_LOG_PFX, uVersion));
3992	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
3993	}
3994
3995	/*
3996	* Load and validate software-immutable registers.
3997	* The features we had exposed to the guest (in the saved state) must be identical
3998	* to what is currently emulated.
3999	*/
4000	{
4001	/* VER_REG */
4002	uint32_t uVerReg = 0;
4003	int rc = pHlp->pfnSSMGetU32(pSSM, &uVerReg);
4004	AssertRCReturn(rc, rc);
4005	AssertLogRelMsgReturn(uVerReg == pThis->uVerReg,
4006	("%s: VER_REG mismatch (expected %#RX32 got %#RX32)\n", DMAR_LOG_PFX, pThis->uVerReg, uVerReg),
4007	rcDataErr);
4008	/* CAP_REG */
4009	uint64_t fCapReg = 0;
4010	pHlp->pfnSSMGetU64(pSSM, &fCapReg);
4011	AssertLogRelMsgReturn(fCapReg == pThis->fCapReg,
4012	("%s: CAP_REG mismatch (expected %#RX64 got %#RX64)\n", DMAR_LOG_PFX, pThis->fCapReg, fCapReg),
4013	rcDataErr);
4014	/* ECAP_REG */
4015	uint64_t fExtCapReg = 0;
4016	pHlp->pfnSSMGetU64(pSSM, &fExtCapReg);
4017	AssertLogRelMsgReturn(fExtCapReg == pThis->fExtCapReg,
4018	("%s: ECAP_REG mismatch (expected %#RX64 got %#RX64)\n", DMAR_LOG_PFX, pThis->fExtCapReg,
4019	fExtCapReg), rcDataErr);
4020	}
4021
4022	/*
4023	* Load MMIO registers.
4024	*/
4025	{
4026	/* Group count. */
4027	uint32_t cRegGroups = 0;
4028	pHlp->pfnSSMGetU32(pSSM, &cRegGroups);
4029	AssertLogRelMsgReturn(cRegGroups == DMAR_MMIO_GROUP_COUNT,
4030	("%s: MMIO group count mismatch (expected %u got %u)\n", DMAR_LOG_PFX, DMAR_MMIO_GROUP_COUNT,
4031	cRegGroups), rcFmtErr);
4032	/* Group 0. */
4033	uint32_t cbRegs0 = 0;
4034	pHlp->pfnSSMGetU32(pSSM, &cbRegs0);
4035	AssertLogRelMsgReturn(cbRegs0 == sizeof(pThis->abRegs0),
4036	("%s: MMIO group 0 size mismatch (expected %u got %u)\n", DMAR_LOG_PFX, sizeof(pThis->abRegs0),
4037	cbRegs0), rcFmtErr);
4038	pHlp->pfnSSMGetMem(pSSM, &pThis->abRegs0[0], cbRegs0);
4039	/* Group 1. */
4040	uint32_t cbRegs1 = 0;
4041	pHlp->pfnSSMGetU32(pSSM, &cbRegs1);
4042	AssertLogRelMsgReturn(cbRegs1 == sizeof(pThis->abRegs1),
4043	("%s: MMIO group 1 size mismatch (expected %u got %u)\n", DMAR_LOG_PFX, sizeof(pThis->abRegs1),
4044	cbRegs1), rcFmtErr);
4045	pHlp->pfnSSMGetMem(pSSM, &pThis->abRegs1[0], cbRegs1);
4046	}
4047
4048	/*
4049	* Validate implementation-defined MMIO register offsets.
4050	*/
4051	{
4052	/* Offset count. */
4053	uint16_t cOffsets = 0;
4054	pHlp->pfnSSMGetU16(pSSM, &cOffsets);
4055	AssertLogRelMsgReturn(cOffsets == DMAR_MMIO_OFF_IMPL_COUNT,
4056	("%s: MMIO offset count mismatch (expected %u got %u)\n", DMAR_LOG_PFX, DMAR_MMIO_OFF_IMPL_COUNT,
4057	cOffsets), rcFmtErr);
4058	/* IVA_REG. */
4059	uint16_t offReg = 0;
4060	pHlp->pfnSSMGetU16(pSSM, &offReg);
4061	AssertLogRelMsgReturn(offReg == DMAR_MMIO_OFF_IVA_REG,
4062	("%s: IVA_REG offset mismatch (expected %u got %u)\n", DMAR_LOG_PFX, DMAR_MMIO_OFF_IVA_REG,
4063	offReg), rcFmtErr);
4064	/* IOTLB_REG. */
4065	AssertLogRelMsgReturn(offReg + 8 == DMAR_MMIO_OFF_IOTLB_REG,
4066	("%s: IOTLB_REG offset mismatch (expected %u got %u)\n", DMAR_LOG_PFX, DMAR_MMIO_OFF_IOTLB_REG,
4067	offReg), rcFmtErr);
4068	/* FRCD_LO_REG. */
4069	pHlp->pfnSSMGetU16(pSSM, &offReg);
4070	AssertLogRelMsgReturn(offReg == DMAR_MMIO_OFF_FRCD_LO_REG,
4071	("%s: FRCD_LO_REG offset mismatch (expected %u got %u)\n", DMAR_LOG_PFX, DMAR_MMIO_OFF_FRCD_LO_REG,
4072	offReg), rcFmtErr);
4073	/* FRCD_HI_REG. */
4074	AssertLogRelMsgReturn(offReg + 8 == DMAR_MMIO_OFF_FRCD_HI_REG,
4075	("%s: FRCD_HI_REG offset mismatch (expected %u got %u)\n", DMAR_LOG_PFX, DMAR_MMIO_OFF_FRCD_HI_REG,
4076	offReg), rcFmtErr);
4077	}
4078
4079	/*
4080	* Load lazily activated registers.
4081	*/
4082	{
4083	/* Active IRTA_REG. */
4084	pHlp->pfnSSMGetU64(pSSM, &pThis->uIrtaReg);
4085	AssertLogRelMsgReturn(!(pThis->uIrtaReg & ~VTD_IRTA_REG_RW_MASK),
4086	("%s: IRTA_REG reserved bits set %#RX64\n", DMAR_LOG_PFX, pThis->uIrtaReg), rcDataErr);
4087	/* Active RTADDR_REG. */
4088	pHlp->pfnSSMGetU64(pSSM, &pThis->uRtaddrReg);
4089	AssertLogRelMsgReturn(!(pThis->uRtaddrReg & ~VTD_RTADDR_REG_RW_MASK),
4090	("%s: RTADDR_REG reserved bits set %#RX64\n", DMAR_LOG_PFX, pThis->uRtaddrReg), rcDataErr);
4091	}
4092
4093	/*
4094	* Verify terminator marker.
4095	*/
4096	{
4097	uint32_t uEndMarker = 0;
4098	int const rc = pHlp->pfnSSMGetU32(pSSM, &uEndMarker);
4099	AssertRCReturn(rc, rc);
4100	AssertLogRelMsgReturn(uEndMarker == UINT32_MAX,
4101	("%s: End marker mismatch (expected %#RX32 got %#RX32)\n", DMAR_LOG_PFX, UINT32_MAX, uEndMarker),
4102	rcFmtErr);
4103	}
4104	return VINF_SUCCESS;
4105	}
4106
4107
4108	/**
4109	* @callback_method_impl{FNSSMDEVLOADDONE}
4110	*/
4111	static DECLCALLBACK(int) dmarR3LoadDone(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
4112	{
4113	PDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PDMARR3);
4114	LogFlowFunc(("\n"));
4115	RT_NOREF(pSSM);
4116	AssertPtrReturn(pThisR3, VERR_INVALID_POINTER);
4117
4118	DMAR_LOCK(pDevIns, pThisR3);
4119	dmarInvQueueThreadWakeUpIfNeeded(pDevIns);
4120	DMAR_UNLOCK(pDevIns, pThisR3);
4121	return VINF_SUCCESS;
4122	}
4123
4124
4125	/**
4126	* @interface_method_impl{PDMDEVREG,pfnReset}
4127	*/
4128	static DECLCALLBACK(void) iommuIntelR3Reset(PPDMDEVINS pDevIns)
4129	{
4130	PCDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARR3);
4131	LogFlowFunc(("\n"));
4132
4133	DMAR_LOCK(pDevIns, pThisR3);
4134	dmarR3RegsInit(pDevIns);
4135	DMAR_UNLOCK(pDevIns, pThisR3);
4136	}
4137
4138
4139	/**
4140	* @interface_method_impl{PDMDEVREG,pfnDestruct}
4141	*/
4142	static DECLCALLBACK(int) iommuIntelR3Destruct(PPDMDEVINS pDevIns)
4143	{
4144	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
4145	PCDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARR3);
4146	LogFlowFunc(("\n"));
4147
4148	DMAR_LOCK(pDevIns, pThisR3);
4149
4150	if (pThis->hEvtInvQueue != NIL_SUPSEMEVENT)
4151	{
4152	PDMDevHlpSUPSemEventClose(pDevIns, pThis->hEvtInvQueue);
4153	pThis->hEvtInvQueue = NIL_SUPSEMEVENT;
4154	}
4155
4156	DMAR_UNLOCK(pDevIns, pThisR3);
4157	return VINF_SUCCESS;
4158	}
4159
4160
4161	/**
4162	* @interface_method_impl{PDMDEVREG,pfnConstruct}
4163	*/
4164	static DECLCALLBACK(int) iommuIntelR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
4165	{
4166	RT_NOREF(pCfg);
4167
4168	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
4169	PDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PDMARR3);
4170	pThisR3->pDevInsR3 = pDevIns;
4171
4172	LogFlowFunc(("iInstance=%d\n", iInstance));
4173	NOREF(iInstance);
4174
4175	/*
4176	* Register the IOMMU with PDM.
4177	*/
4178	PDMIOMMUREGR3 IommuReg;
4179	RT_ZERO(IommuReg);
4180	IommuReg.u32Version = PDM_IOMMUREGCC_VERSION;
4181	IommuReg.pfnMemAccess = iommuIntelMemAccess;
4182	IommuReg.pfnMemBulkAccess = iommuIntelMemBulkAccess;
4183	IommuReg.pfnMsiRemap = iommuIntelMsiRemap;
4184	IommuReg.u32TheEnd = PDM_IOMMUREGCC_VERSION;
4185	int rc = PDMDevHlpIommuRegister(pDevIns, &IommuReg, &pThisR3->CTX_SUFF(pIommuHlp), &pThis->idxIommu);
4186	if (RT_FAILURE(rc))
4187	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to register ourselves as an IOMMU device"));
4188	if (pThisR3->CTX_SUFF(pIommuHlp)->u32Version != PDM_IOMMUHLPR3_VERSION)
4189	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
4190	N_("IOMMU helper version mismatch; got %#x expected %#x"),
4191	pThisR3->CTX_SUFF(pIommuHlp)->u32Version, PDM_IOMMUHLPR3_VERSION);
4192	if (pThisR3->CTX_SUFF(pIommuHlp)->u32TheEnd != PDM_IOMMUHLPR3_VERSION)
4193	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
4194	N_("IOMMU helper end-version mismatch; got %#x expected %#x"),
4195	pThisR3->CTX_SUFF(pIommuHlp)->u32TheEnd, PDM_IOMMUHLPR3_VERSION);
4196	AssertPtr(pThisR3->pIommuHlpR3->pfnLock);
4197	AssertPtr(pThisR3->pIommuHlpR3->pfnUnlock);
4198	AssertPtr(pThisR3->pIommuHlpR3->pfnLockIsOwner);
4199	AssertPtr(pThisR3->pIommuHlpR3->pfnSendMsi);
4200
4201	/*
4202	* Use PDM's critical section (via helpers) for the IOMMU device.
4203	*/
4204	rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
4205	AssertRCReturn(rc, rc);
4206
4207	/*
4208	* Initialize PCI configuration registers.
4209	*/
4210	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
4211	PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
4212
4213	/* Header. */
4214	PDMPciDevSetVendorId(pPciDev, DMAR_PCI_VENDOR_ID); /* Intel */
4215	PDMPciDevSetDeviceId(pPciDev, DMAR_PCI_DEVICE_ID); /* VirtualBox DMAR device */
4216	PDMPciDevSetRevisionId(pPciDev, DMAR_PCI_REVISION_ID); /* VirtualBox specific device implementation revision */
4217	PDMPciDevSetClassBase(pPciDev, VBOX_PCI_CLASS_SYSTEM); /* System Base Peripheral */
4218	PDMPciDevSetClassSub(pPciDev, VBOX_PCI_SUB_SYSTEM_OTHER); /* Other */
4219	PDMPciDevSetHeaderType(pPciDev, 0); /* Single function, type 0 */
4220	PDMPciDevSetSubSystemId(pPciDev, DMAR_PCI_DEVICE_ID); /* VirtualBox DMAR device */
4221	PDMPciDevSetSubSystemVendorId(pPciDev, DMAR_PCI_VENDOR_ID); /* Intel */
4222
4223	/** @todo Chipset spec says PCI Express Capability Id. Relevant for us? */
4224	PDMPciDevSetStatus(pPciDev, 0);
4225	PDMPciDevSetCapabilityList(pPciDev, 0);
4226	/** @todo VTBAR at 0x180? */
4227
4228	/*
4229	* Register the PCI function with PDM.
4230	*/
4231	rc = PDMDevHlpPCIRegister(pDevIns, pPciDev);
4232	AssertLogRelRCReturn(rc, rc);
4233
4234	/*
4235	* Register MMIO region.
4236	*/
4237	AssertCompile(!(DMAR_MMIO_BASE_PHYSADDR & X86_PAGE_4K_OFFSET_MASK));
4238	rc = PDMDevHlpMmioCreateAndMap(pDevIns, DMAR_MMIO_BASE_PHYSADDR, DMAR_MMIO_SIZE, dmarMmioWrite, dmarMmioRead,
4239	IOMMMIO_FLAGS_READ_DWORD_QWORD \| IOMMMIO_FLAGS_WRITE_DWORD_QWORD_ZEROED, "Intel-IOMMU",
4240	&pThis->hMmio);
4241	AssertLogRelRCReturn(rc, rc);
4242
4243	/*
4244	* Register saved state handlers.
4245	*/
4246	rc = PDMDevHlpSSMRegisterEx(pDevIns, DMAR_SAVED_STATE_VERSION, sizeof(DMAR), NULL /* pszBefore */,
4247	NULL /* pfnLivePrep /, NULL / pfnLiveExec /, NULL / pfnLiveVote */,
4248	NULL /* pfnSavePrep /, dmarR3SaveExec, NULL / pfnSaveDone */,
4249	NULL /* pfnLoadPrep */, dmarR3LoadExec, dmarR3LoadDone);
4250	AssertLogRelRCReturn(rc, rc);
4251
4252	/*
4253	* Register debugger info items.
4254	*/
4255	rc = PDMDevHlpDBGFInfoRegister(pDevIns, "iommu", "Display IOMMU state.", dmarR3DbgInfo);
4256	AssertLogRelRCReturn(rc, rc);
4257
4258	#ifdef VBOX_WITH_STATISTICS
4259	/*
4260	* Statistics.
4261	*/
4262	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadR3, STAMTYPE_COUNTER, "R3/MmioRead", STAMUNIT_OCCURENCES, "Number of MMIO reads in R3");
4263	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadRZ, STAMTYPE_COUNTER, "RZ/MmioRead", STAMUNIT_OCCURENCES, "Number of MMIO reads in RZ.");
4264
4265	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteR3, STAMTYPE_COUNTER, "R3/MmioWrite", STAMUNIT_OCCURENCES, "Number of MMIO writes in R3.");
4266	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteRZ, STAMTYPE_COUNTER, "RZ/MmioWrite", STAMUNIT_OCCURENCES, "Number of MMIO writes in RZ.");
4267
4268	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapCfiR3, STAMTYPE_COUNTER, "R3/MsiRemapCfi", STAMUNIT_OCCURENCES, "Number of compatibility-format interrupt remap requests in R3.");
4269	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapCfiRZ, STAMTYPE_COUNTER, "RZ/MsiRemapCfi", STAMUNIT_OCCURENCES, "Number of compatibility-format interrupt remap requests in RZ.");
4270	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapRfiR3, STAMTYPE_COUNTER, "R3/MsiRemapRfi", STAMUNIT_OCCURENCES, "Number of remappable-format interrupt remap requests in R3.");
4271	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapRfiRZ, STAMTYPE_COUNTER, "RZ/MsiRemapRfi", STAMUNIT_OCCURENCES, "Number of remappable-format interrupt remap requests in RZ.");
4272
4273	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemReadR3, STAMTYPE_COUNTER, "R3/MemRead", STAMUNIT_OCCURENCES, "Number of memory read translation requests in R3.");
4274	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemReadRZ, STAMTYPE_COUNTER, "RZ/MemRead", STAMUNIT_OCCURENCES, "Number of memory read translation requests in RZ.");
4275
4276	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemWriteR3, STAMTYPE_COUNTER, "R3/MemWrite", STAMUNIT_OCCURENCES, "Number of memory write translation requests in R3.");
4277	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemWriteRZ, STAMTYPE_COUNTER, "RZ/MemWrite", STAMUNIT_OCCURENCES, "Number of memory write translation requests in RZ.");
4278
4279	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkReadR3, STAMTYPE_COUNTER, "R3/MemBulkRead", STAMUNIT_OCCURENCES, "Number of memory bulk read translation requests in R3.");
4280	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkReadRZ, STAMTYPE_COUNTER, "RZ/MemBulkRead", STAMUNIT_OCCURENCES, "Number of memory bulk read translation requests in RZ.");
4281
4282	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkWriteR3, STAMTYPE_COUNTER, "R3/MemBulkWrite", STAMUNIT_OCCURENCES, "Number of memory bulk write translation requests in R3.");
4283	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkWriteRZ, STAMTYPE_COUNTER, "RZ/MemBulkWrite", STAMUNIT_OCCURENCES, "Number of memory bulk write translation requests in RZ.");
4284
4285	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCcInvDsc, STAMTYPE_COUNTER, "R3/QI/CcInv", STAMUNIT_OCCURENCES, "Number of cc_inv_dsc processed.");
4286	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIotlbInvDsc, STAMTYPE_COUNTER, "R3/QI/IotlbInv", STAMUNIT_OCCURENCES, "Number of iotlb_inv_dsc processed.");
4287	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatDevtlbInvDsc, STAMTYPE_COUNTER, "R3/QI/DevtlbInv", STAMUNIT_OCCURENCES, "Number of dev_tlb_inv_dsc processed.");
4288	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIecInvDsc, STAMTYPE_COUNTER, "R3/QI/IecInv", STAMUNIT_OCCURENCES, "Number of iec_inv processed.");
4289	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatInvWaitDsc, STAMTYPE_COUNTER, "R3/QI/InvWait", STAMUNIT_OCCURENCES, "Number of inv_wait_dsc processed.");
4290	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatPasidIotlbInvDsc, STAMTYPE_COUNTER, "R3/QI/PasidIotlbInv", STAMUNIT_OCCURENCES, "Number of p_iotlb_inv_dsc processed.");
4291	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatPasidCacheInvDsc, STAMTYPE_COUNTER, "R3/QI/PasidCacheInv", STAMUNIT_OCCURENCES, "Number of pc_inv_dsc pprocessed.");
4292	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatPasidDevtlbInvDsc, STAMTYPE_COUNTER, "R3/QI/PasidDevtlbInv", STAMUNIT_OCCURENCES, "Number of p_dev_tlb_inv_dsc processed.");
4293	#endif
4294
4295	/*
4296	* Initialize registers.
4297	*/
4298	dmarR3RegsInit(pDevIns);
4299
4300	/*
4301	* Create invalidation-queue thread and semaphore.
4302	*/
4303	char szInvQueueThread[32];
4304	RT_ZERO(szInvQueueThread);
4305	RTStrPrintf(szInvQueueThread, sizeof(szInvQueueThread), "IOMMU-QI-%u", iInstance);
4306	rc = PDMDevHlpThreadCreate(pDevIns, &pThisR3->pInvQueueThread, pThis, dmarR3InvQueueThread, dmarR3InvQueueThreadWakeUp,
4307	0 /* cbStack */, RTTHREADTYPE_IO, szInvQueueThread);
4308	AssertLogRelRCReturn(rc, rc);
4309
4310	rc = PDMDevHlpSUPSemEventCreate(pDevIns, &pThis->hEvtInvQueue);
4311	AssertLogRelRCReturn(rc, rc);
4312
4313	/*
4314	* Log some of the features exposed to software.
4315	*/
4316	uint8_t const uVerMax = RT_BF_GET(pThis->uVerReg, VTD_BF_VER_REG_MAX);
4317	uint8_t const uVerMin = RT_BF_GET(pThis->uVerReg, VTD_BF_VER_REG_MIN);
4318	uint8_t const cMgawBits = RT_BF_GET(pThis->fCapReg, VTD_BF_CAP_REG_MGAW) + 1;
4319	uint8_t const fSagaw = RT_BF_GET(pThis->fCapReg, VTD_BF_CAP_REG_SAGAW);
4320	uint16_t const offFrcd = RT_BF_GET(pThis->fCapReg, VTD_BF_CAP_REG_FRO);
4321	uint16_t const offIva = RT_BF_GET(pThis->fExtCapReg, VTD_BF_ECAP_REG_IRO);
4322	LogRel(("%s: Mapped at %#RGp (%u-level page-table supported)\n",
4323	DMAR_LOG_PFX, DMAR_MMIO_BASE_PHYSADDR, pThis->cMaxPagingLevel));
4324	LogRel(("%s: Version=%u.%u Cap=%#RX64 ExtCap=%#RX64 Mgaw=%u bits Sagaw=%#x HawBaseMask=%#RX64 MgawInvMask=%#RX64 FRO=%#x IRO=%#x\n",
4325	DMAR_LOG_PFX, uVerMax, uVerMin, pThis->fCapReg, pThis->fExtCapReg, cMgawBits, fSagaw, pThis->fHawBaseMask,
4326	pThis->fMgawInvMask, offFrcd, offIva));
4327	return VINF_SUCCESS;
4328	}
4329
4330	#else
4331
4332	/**
4333	* @callback_method_impl{PDMDEVREGR0,pfnConstruct}
4334	*/
4335	static DECLCALLBACK(int) iommuIntelRZConstruct(PPDMDEVINS pDevIns)
4336	{
4337	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
4338	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
4339	PDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PDMARCC);
4340	pThisCC->CTX_SUFF(pDevIns) = pDevIns;
4341
4342	/* We will use PDM's critical section (via helpers) for the IOMMU device. */
4343	int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
4344	AssertRCReturn(rc, rc);
4345
4346	/* Set up the MMIO RZ handlers. */
4347	rc = PDMDevHlpMmioSetUpContext(pDevIns, pThis->hMmio, dmarMmioWrite, dmarMmioRead, NULL /* pvUser */);
4348	AssertRCReturn(rc, rc);
4349
4350	/* Set up the IOMMU RZ callbacks. */
4351	PDMIOMMUREGCC IommuReg;
4352	RT_ZERO(IommuReg);
4353	IommuReg.u32Version = PDM_IOMMUREGCC_VERSION;
4354	IommuReg.idxIommu = pThis->idxIommu;
4355	IommuReg.pfnMemAccess = iommuIntelMemAccess;
4356	IommuReg.pfnMemBulkAccess = iommuIntelMemBulkAccess;
4357	IommuReg.pfnMsiRemap = iommuIntelMsiRemap;
4358	IommuReg.u32TheEnd = PDM_IOMMUREGCC_VERSION;
4359
4360	rc = PDMDevHlpIommuSetUpContext(pDevIns, &IommuReg, &pThisCC->CTX_SUFF(pIommuHlp));
4361	AssertRCReturn(rc, rc);
4362	AssertPtrReturn(pThisCC->CTX_SUFF(pIommuHlp), VERR_IOMMU_IPE_1);
4363	AssertReturn(pThisCC->CTX_SUFF(pIommuHlp)->u32Version == CTX_MID(PDM_IOMMUHLP,_VERSION), VERR_VERSION_MISMATCH);
4364	AssertReturn(pThisCC->CTX_SUFF(pIommuHlp)->u32TheEnd == CTX_MID(PDM_IOMMUHLP,_VERSION), VERR_VERSION_MISMATCH);
4365	AssertPtr(pThisCC->CTX_SUFF(pIommuHlp)->pfnLock);
4366	AssertPtr(pThisCC->CTX_SUFF(pIommuHlp)->pfnUnlock);
4367	AssertPtr(pThisCC->CTX_SUFF(pIommuHlp)->pfnLockIsOwner);
4368	AssertPtr(pThisCC->CTX_SUFF(pIommuHlp)->pfnSendMsi);
4369
4370	return VINF_SUCCESS;
4371	}
4372
4373	#endif
4374
4375
4376	/**
4377	* The device registration structure.
4378	*/
4379	PDMDEVREG const g_DeviceIommuIntel =
4380	{
4381	/* .u32Version = */ PDM_DEVREG_VERSION,
4382	/* .uReserved0 = */ 0,
4383	/* .szName = */ "iommu-intel",
4384	/* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RZ \| PDM_DEVREG_FLAGS_NEW_STYLE,
4385	/* .fClass = */ PDM_DEVREG_CLASS_PCI_BUILTIN,
4386	/* .cMaxInstances = */ 1,
4387	/* .uSharedVersion = */ 42,
4388	/* .cbInstanceShared = */ sizeof(DMAR),
4389	/* .cbInstanceCC = */ sizeof(DMARCC),
4390	/* .cbInstanceRC = */ sizeof(DMARRC),
4391	/* .cMaxPciDevices = */ 1,
4392	/* .cMaxMsixVectors = */ 0,
4393	/* .pszDescription = */ "IOMMU (Intel)",
4394	#if defined(IN_RING3)
4395	/* .pszRCMod = */ "VBoxDDRC.rc",
4396	/* .pszR0Mod = */ "VBoxDDR0.r0",
4397	/* .pfnConstruct = */ iommuIntelR3Construct,
4398	/* .pfnDestruct = */ iommuIntelR3Destruct,
4399	/* .pfnRelocate = */ NULL,
4400	/* .pfnMemSetup = */ NULL,
4401	/* .pfnPowerOn = */ NULL,
4402	/* .pfnReset = */ iommuIntelR3Reset,
4403	/* .pfnSuspend = */ NULL,
4404	/* .pfnResume = */ NULL,
4405	/* .pfnAttach = */ NULL,
4406	/* .pfnDetach = */ NULL,
4407	/* .pfnQueryInterface = */ NULL,
4408	/* .pfnInitComplete = */ NULL,
4409	/* .pfnPowerOff = */ NULL,
4410	/* .pfnSoftReset = */ NULL,
4411	/* .pfnReserved0 = */ NULL,
4412	/* .pfnReserved1 = */ NULL,
4413	/* .pfnReserved2 = */ NULL,
4414	/* .pfnReserved3 = */ NULL,
4415	/* .pfnReserved4 = */ NULL,
4416	/* .pfnReserved5 = */ NULL,
4417	/* .pfnReserved6 = */ NULL,
4418	/* .pfnReserved7 = */ NULL,
4419	#elif defined(IN_RING0)
4420	/* .pfnEarlyConstruct = */ NULL,
4421	/* .pfnConstruct = */ iommuIntelRZConstruct,
4422	/* .pfnDestruct = */ NULL,
4423	/* .pfnFinalDestruct = */ NULL,
4424	/* .pfnRequest = */ NULL,
4425	/* .pfnReserved0 = */ NULL,
4426	/* .pfnReserved1 = */ NULL,
4427	/* .pfnReserved2 = */ NULL,
4428	/* .pfnReserved3 = */ NULL,
4429	/* .pfnReserved4 = */ NULL,
4430	/* .pfnReserved5 = */ NULL,
4431	/* .pfnReserved6 = */ NULL,
4432	/* .pfnReserved7 = */ NULL,
4433	#elif defined(IN_RC)
4434	/* .pfnConstruct = */ iommuIntelRZConstruct,
4435	/* .pfnReserved0 = */ NULL,
4436	/* .pfnReserved1 = */ NULL,
4437	/* .pfnReserved2 = */ NULL,
4438	/* .pfnReserved3 = */ NULL,
4439	/* .pfnReserved4 = */ NULL,
4440	/* .pfnReserved5 = */ NULL,
4441	/* .pfnReserved6 = */ NULL,
4442	/* .pfnReserved7 = */ NULL,
4443	#else
4444	# error "Not in IN_RING3, IN_RING0 or IN_RC!"
4445	#endif
4446	/* .u32VersionEnd = */ PDM_DEVREG_VERSION
4447	};
4448
4449	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
4450

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source: vbox/trunk/src/VBox/Devices/Bus/DevIommuIntel.cpp@ 89729

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