DevIommuIntel.cpp@ 90213

Last change on this file since 90213 was 90213, checked in by vboxsync, 3 years ago
Intel IOMMU: bugref:9967 PTE error reporting fix.
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1	/* $Id: DevIommuIntel.cpp 90213 2021-07-15 11:59:06Z vboxsync $ */
2	/** @file
3	* IOMMU - Input/Output Memory Management Unit - Intel implementation.
4	*/
5
6	/*
7	* Copyright (C) 2021 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_DEV_IOMMU
23	#include "VBoxDD.h"
24	#include "DevIommuIntel.h"
25
26	#include <VBox/iommu-intel.h>
27	#include <iprt/mem.h>
28	#include <iprt/string.h>
29
30
31	/*********************************************************************************************************************************
32	* Defined Constants And Macros *
33	*********************************************************************************************************************************/
34	/** Gets the low uint32_t of a uint64_t or something equivalent.
35	*
36	* This is suitable for casting constants outside code (since RT_LO_U32 can't be
37	* used as it asserts for correctness when compiling on certain compilers). */
38	#define DMAR_LO_U32(a) (uint32_t)(UINT32_MAX & (a))
39
40	/** Gets the high uint32_t of a uint64_t or something equivalent.
41	*
42	* This is suitable for casting constants outside code (since RT_HI_U32 can't be
43	* used as it asserts for correctness when compiling on certain compilers). */
44	#define DMAR_HI_U32(a) (uint32_t)((a) >> 32)
45
46	/** Asserts MMIO access' offset and size are valid or returns appropriate error
47	* code suitable for returning from MMIO access handlers. */
48	#define DMAR_ASSERT_MMIO_ACCESS_RET(a_off, a_cb) \
49	do { \
50	AssertReturn((a_cb) == 4 \|\| (a_cb) == 8, VINF_IOM_MMIO_UNUSED_FF); \
51	AssertReturn(!((a_off) & ((a_cb) - 1)), VINF_IOM_MMIO_UNUSED_FF); \
52	} while (0)
53
54	/** Checks if the MMIO offset is valid. */
55	#define DMAR_IS_MMIO_OFF_VALID(a_off) ( (a_off) < DMAR_MMIO_GROUP_0_OFF_END \
56	\|\| (a_off) - (uint16_t)DMAR_MMIO_GROUP_1_OFF_FIRST < (uint16_t)DMAR_MMIO_GROUP_1_SIZE)
57
58	/** Acquires the DMAR lock but returns with the given busy error code on failure. */
59	#define DMAR_LOCK_RET(a_pDevIns, a_pThisCC, a_rcBusy) \
60	do { \
61	if ((a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLock((a_pDevIns), (a_rcBusy)) == VINF_SUCCESS) \
62	{ /* likely */ } \
63	else \
64	return (a_rcBusy); \
65	} while (0)
66
67	/** Acquires the DMAR lock (not expected to fail). */
68	#ifdef IN_RING3
69	# define DMAR_LOCK(a_pDevIns, a_pThisCC) (a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLock((a_pDevIns), VERR_IGNORED)
70	#else
71	# define DMAR_LOCK(a_pDevIns, a_pThisCC) \
72	do { \
73	int const rcLock = (a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLock((a_pDevIns), VINF_SUCCESS); \
74	AssertRC(rcLock); \
75	} while (0)
76	#endif
77
78	/** Release the DMAR lock. */
79	#define DMAR_UNLOCK(a_pDevIns, a_pThisCC) (a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnUnlock(a_pDevIns)
80
81	/** Asserts that the calling thread owns the DMAR lock. */
82	#define DMAR_ASSERT_LOCK_IS_OWNER(a_pDevIns, a_pThisCC) \
83	do { \
84	Assert((a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLockIsOwner(a_pDevIns)); \
85	RT_NOREF1(a_pThisCC); \
86	} while (0)
87
88	/** Asserts that the calling thread does not own the DMAR lock. */
89	#define DMAR_ASSERT_LOCK_IS_NOT_OWNER(a_pDevIns, a_pThisCC) \
90	do { \
91	Assert((a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLockIsOwner(a_pDevIns) == false); \
92	RT_NOREF1(a_pThisCC); \
93	} while (0)
94
95	/** The number of fault recording registers our implementation supports.
96	* Normal guest operation shouldn't trigger faults anyway, so we only support the
97	* minimum number of registers (which is 1).
98	*
99	* See Intel VT-d spec. 10.4.2 "Capability Register" (CAP_REG.NFR). */
100	#define DMAR_FRCD_REG_COUNT UINT32_C(1)
101
102	/** Number of register groups (used in saved states). */
103	#define DMAR_MMIO_GROUP_COUNT 2
104	/** Offset of first register in group 0. */
105	#define DMAR_MMIO_GROUP_0_OFF_FIRST VTD_MMIO_OFF_VER_REG
106	/** Offset of last register in group 0 (inclusive). */
107	#define DMAR_MMIO_GROUP_0_OFF_LAST VTD_MMIO_OFF_MTRR_PHYSMASK9_REG
108	/** Last valid offset in group 0 (exclusive). */
109	#define DMAR_MMIO_GROUP_0_OFF_END (DMAR_MMIO_GROUP_0_OFF_LAST + 8 /* sizeof MTRR_PHYSMASK9_REG */)
110	/** Size of the group 0 (in bytes). */
111	#define DMAR_MMIO_GROUP_0_SIZE (DMAR_MMIO_GROUP_0_OFF_END - DMAR_MMIO_GROUP_0_OFF_FIRST)
112	/** Number of implementation-defined MMIO register offsets - IVA_REG and
113	* FRCD_LO_REG (used in saved state). IOTLB_REG and FRCD_HI_REG are derived from
114	* IVA_REG and FRCD_LO_REG respectively */
115	#define DMAR_MMIO_OFF_IMPL_COUNT 2
116	/** Implementation-specific MMIO offset of IVA_REG (used in saved state). */
117	#define DMAR_MMIO_OFF_IVA_REG 0xe50
118	/** Implementation-specific MMIO offset of IOTLB_REG. */
119	#define DMAR_MMIO_OFF_IOTLB_REG 0xe58
120	/** Implementation-specific MMIO offset of FRCD_LO_REG (used in saved state). */
121	#define DMAR_MMIO_OFF_FRCD_LO_REG 0xe70
122	/** Implementation-specific MMIO offset of FRCD_HI_REG. */
123	#define DMAR_MMIO_OFF_FRCD_HI_REG 0xe78
124	AssertCompile(!(DMAR_MMIO_OFF_FRCD_LO_REG & 0xf));
125	AssertCompile(DMAR_MMIO_OFF_IOTLB_REG == DMAR_MMIO_OFF_IVA_REG + 8);
126	AssertCompile(DMAR_MMIO_OFF_FRCD_HI_REG == DMAR_MMIO_OFF_FRCD_LO_REG + 8);
127
128	/** Offset of first register in group 1. */
129	#define DMAR_MMIO_GROUP_1_OFF_FIRST VTD_MMIO_OFF_VCCAP_REG
130	/** Offset of last register in group 1 (inclusive). */
131	#define DMAR_MMIO_GROUP_1_OFF_LAST (DMAR_MMIO_OFF_FRCD_LO_REG + 8) * DMAR_FRCD_REG_COUNT
132	/** Last valid offset in group 1 (exclusive). */
133	#define DMAR_MMIO_GROUP_1_OFF_END (DMAR_MMIO_GROUP_1_OFF_LAST + 8 /* sizeof FRCD_HI_REG */)
134	/** Size of the group 1 (in bytes). */
135	#define DMAR_MMIO_GROUP_1_SIZE (DMAR_MMIO_GROUP_1_OFF_END - DMAR_MMIO_GROUP_1_OFF_FIRST)
136
137	/** DMAR implementation's major version number (exposed to software).
138	* We report 6 as the major version since we support queued-invalidations as
139	* software may make assumptions based on that.
140	*
141	* See Intel VT-d spec. 10.4.7 "Context Command Register" (CCMD_REG.CAIG). */
142	#define DMAR_VER_MAJOR 6
143	/** DMAR implementation's minor version number (exposed to software). */
144	#define DMAR_VER_MINOR 0
145
146	/** Number of domain supported (0=16, 1=64, 2=256, 3=1K, 4=4K, 5=16K, 6=64K,
147	* 7=Reserved). */
148	#define DMAR_ND 6
149
150	/** @name DMAR_PERM_XXX: DMA request permissions.
151	* The order of R, W, X bits is important as it corresponds to those bits in
152	* page-table entries.
153	*
154	* @{ */
155	/** DMA request permission: Read. */
156	#define DMAR_PERM_READ RT_BIT(0)
157	/** DMA request permission: Write. */
158	#define DMAR_PERM_WRITE RT_BIT(1)
159	/** DMA request permission: Execute (ER). */
160	#define DMAR_PERM_EXE RT_BIT(2)
161	/** DMA request permission: Supervisor privilege (PR). */
162	#define DMAR_PERM_PRIV RT_BIT(3)
163	/** DMA request permissions: All. */
164	#define DMAR_PERM_ALL (DMAR_PERM_READ \| DMAR_PERM_WRITE \| DMAR_PERM_EXE \| DMAR_PERM_PRIV)
165	/** @} */
166
167	/** Release log prefix string. */
168	#define DMAR_LOG_PFX "Intel-IOMMU"
169	/** The current saved state version. */
170	#define DMAR_SAVED_STATE_VERSION 1
171
172
173	/*********************************************************************************************************************************
174	* Structures and Typedefs *
175	*********************************************************************************************************************************/
176	/**
177	* DMAR error diagnostics.
178	* Sorted alphabetically so it's easier to add and locate items, no other reason.
179	*
180	* @note Members of this enum are used as array indices, so no gaps in enum
181	* values are not allowed. Update g_apszDmarDiagDesc when you modify
182	* fields in this enum.
183	*/
184	typedef enum
185	{
186	/* No error, this must be zero! */
187	kDmarDiag_None = 0,
188
189	/* Address Translation Faults. */
190	kDmarDiag_At_Lm_CtxEntry_Not_Present,
191	kDmarDiag_At_Lm_CtxEntry_Read_Failed,
192	kDmarDiag_At_Lm_CtxEntry_Rsvd,
193	kDmarDiag_At_Lm_Pt_At_Block,
194	kDmarDiag_At_Lm_Pt_Aw_Invalid,
195	kDmarDiag_At_Lm_RootEntry_Not_Present,
196	kDmarDiag_At_Lm_RootEntry_Read_Failed,
197	kDmarDiag_At_Lm_RootEntry_Rsvd,
198	kDmarDiag_At_Lm_Tt_Invalid,
199	kDmarDiag_At_Lm_Ut_At_Block,
200	kDmarDiag_At_Lm_Ut_Aw_Invalid,
201	kDmarDiag_At_Rta_Adms_Not_Supported,
202	kDmarDiag_At_Rta_Rsvd,
203	kDmarDiag_At_Rta_Smts_Not_Supported,
204	kDmarDiag_At_Xm_AddrIn_Invalid,
205	kDmarDiag_At_Xm_AddrOut_Invalid,
206	kDmarDiag_At_Xm_Perm_Read_Denied,
207	kDmarDiag_At_Xm_Perm_Write_Denied,
208	kDmarDiag_At_Xm_Pte_Not_Present,
209	kDmarDiag_At_Xm_Pte_Rsvd,
210	kDmarDiag_At_Xm_Pte_Sllps_Invalid,
211	kDmarDiag_At_Xm_Read_Pte_Failed,
212	kDmarDiag_At_Xm_Slpptr_Read_Failed,
213
214	/* CCMD_REG faults. */
215	kDmarDiag_CcmdReg_Not_Supported,
216	kDmarDiag_CcmdReg_Qi_Enabled,
217	kDmarDiag_CcmdReg_Ttm_Invalid,
218
219	/* IQA_REG faults. */
220	kDmarDiag_IqaReg_Dsc_Fetch_Error,
221	kDmarDiag_IqaReg_Dw_128_Invalid,
222	kDmarDiag_IqaReg_Dw_256_Invalid,
223
224	/* Invalidation Queue Error Info. */
225	kDmarDiag_Iqei_Dsc_Type_Invalid,
226	kDmarDiag_Iqei_Inv_Wait_Dsc_0_1_Rsvd,
227	kDmarDiag_Iqei_Inv_Wait_Dsc_2_3_Rsvd,
228	kDmarDiag_Iqei_Inv_Wait_Dsc_Invalid,
229	kDmarDiag_Iqei_Ttm_Rsvd,
230
231	/* IQT_REG faults. */
232	kDmarDiag_IqtReg_Qt_Invalid,
233	kDmarDiag_IqtReg_Qt_Not_Aligned,
234
235	/* Interrupt Remapping Faults. */
236	kDmarDiag_Ir_Cfi_Blocked,
237	kDmarDiag_Ir_Rfi_Intr_Index_Invalid,
238	kDmarDiag_Ir_Rfi_Irte_Mode_Invalid,
239	kDmarDiag_Ir_Rfi_Irte_Not_Present,
240	kDmarDiag_Ir_Rfi_Irte_Read_Failed,
241	kDmarDiag_Ir_Rfi_Irte_Rsvd,
242	kDmarDiag_Ir_Rfi_Irte_Svt_Bus,
243	kDmarDiag_Ir_Rfi_Irte_Svt_Masked,
244	kDmarDiag_Ir_Rfi_Irte_Svt_Rsvd,
245	kDmarDiag_Ir_Rfi_Rsvd,
246
247	/* Member for determining array index limit. */
248	kDmarDiag_End,
249
250	/* Usual 32-bit type size hack. */
251	kDmarDiag_32Bit_Hack = 0x7fffffff
252	} DMARDIAG;
253	AssertCompileSize(DMARDIAG, 4);
254
255	#ifdef IN_RING3
256	/** DMAR diagnostic enum description expansion.
257	* The below construct ensures typos in the input to this macro are caught
258	* during compile time. */
259	# define DMARDIAG_DESC(a_Name) RT_CONCAT(kDmarDiag_, a_Name) < kDmarDiag_End ? RT_STR(a_Name) : "Ignored"
260
261	/** DMAR diagnostics description for members in DMARDIAG. */
262	static const char *const g_apszDmarDiagDesc[] =
263	{
264	DMARDIAG_DESC(None ),
265
266	/* Address Translation Faults. */
267	DMARDIAG_DESC(At_Lm_CtxEntry_Not_Present ),
268	DMARDIAG_DESC(At_Lm_CtxEntry_Read_Failed ),
269	DMARDIAG_DESC(At_Lm_CtxEntry_Rsvd ),
270	DMARDIAG_DESC(At_Lm_Pt_At_Block ),
271	DMARDIAG_DESC(At_Lm_Pt_Aw_Invalid ),
272	DMARDIAG_DESC(At_Lm_RootEntry_Not_Present),
273	DMARDIAG_DESC(At_Lm_RootEntry_Read_Failed),
274	DMARDIAG_DESC(At_Lm_RootEntry_Rsvd ),
275	DMARDIAG_DESC(At_Lm_Tt_Invalid ),
276	DMARDIAG_DESC(At_Lm_Ut_At_Block ),
277	DMARDIAG_DESC(At_Lm_Ut_Aw_Invalid ),
278	DMARDIAG_DESC(At_Rta_Adms_Not_Supported ),
279	DMARDIAG_DESC(At_Rta_Rsvd ),
280	DMARDIAG_DESC(At_Rta_Smts_Not_Supported ),
281	DMARDIAG_DESC(At_Xm_AddrIn_Invalid ),
282	DMARDIAG_DESC(At_Xm_AddrOut_Invalid ),
283	DMARDIAG_DESC(At_Xm_Perm_Read_Denied ),
284	DMARDIAG_DESC(At_Xm_Perm_Write_Denied ),
285	DMARDIAG_DESC(At_Xm_Pte_Not_Present ),
286	DMARDIAG_DESC(At_Xm_Pte_Rsvd ),
287	DMARDIAG_DESC(At_Xm_Pte_Sllps_Invalid ),
288	DMARDIAG_DESC(At_Xm_Read_Pte_Failed ),
289	DMARDIAG_DESC(At_Xm_Slpptr_Read_Failed ),
290
291	/* CCMD_REG faults. */
292	DMARDIAG_DESC(CcmdReg_Not_Supported ),
293	DMARDIAG_DESC(CcmdReg_Qi_Enabled ),
294	DMARDIAG_DESC(CcmdReg_Ttm_Invalid ),
295
296	/* IQA_REG faults. */
297	DMARDIAG_DESC(IqaReg_Dsc_Fetch_Error ),
298	DMARDIAG_DESC(IqaReg_Dw_128_Invalid ),
299	DMARDIAG_DESC(IqaReg_Dw_256_Invalid ),
300
301	/* Invalidation Queue Error Info. */
302	DMARDIAG_DESC(Iqei_Dsc_Type_Invalid ),
303	DMARDIAG_DESC(Iqei_Inv_Wait_Dsc_0_1_Rsvd ),
304	DMARDIAG_DESC(Iqei_Inv_Wait_Dsc_2_3_Rsvd ),
305	DMARDIAG_DESC(Iqei_Inv_Wait_Dsc_Invalid ),
306	DMARDIAG_DESC(Iqei_Ttm_Rsvd ),
307
308	/* IQT_REG faults. */
309	DMARDIAG_DESC(IqtReg_Qt_Invalid ),
310	DMARDIAG_DESC(IqtReg_Qt_Not_Aligned ),
311
312	/* Interrupt remapping faults. */
313	DMARDIAG_DESC(Ir_Cfi_Blocked ),
314	DMARDIAG_DESC(Ir_Rfi_Intr_Index_Invalid ),
315	DMARDIAG_DESC(Ir_Rfi_Irte_Mode_Invalid ),
316	DMARDIAG_DESC(Ir_Rfi_Irte_Not_Present ),
317	DMARDIAG_DESC(Ir_Rfi_Irte_Read_Failed ),
318	DMARDIAG_DESC(Ir_Rfi_Irte_Rsvd ),
319	DMARDIAG_DESC(Ir_Rfi_Irte_Svt_Bus ),
320	DMARDIAG_DESC(Ir_Rfi_Irte_Svt_Masked ),
321	DMARDIAG_DESC(Ir_Rfi_Irte_Svt_Rsvd ),
322	DMARDIAG_DESC(Ir_Rfi_Rsvd ),
323	/* kDmarDiag_End */
324	};
325	AssertCompile(RT_ELEMENTS(g_apszDmarDiagDesc) == kDmarDiag_End);
326	# undef DMARDIAG_DESC
327	#endif /* IN_RING3 */
328
329	/**
330	* The shared DMAR device state.
331	*/
332	typedef struct DMAR
333	{
334	/** IOMMU device index. */
335	uint32_t idxIommu;
336	/** Padding. */
337	uint32_t u32Padding0;
338
339	/** Registers (group 0). */
340	uint8_t abRegs0[DMAR_MMIO_GROUP_0_SIZE];
341	/** Registers (group 1). */
342	uint8_t abRegs1[DMAR_MMIO_GROUP_1_SIZE];
343
344	/** @name Lazily activated registers.
345	* These are the active values for lazily activated registers. Software is free to
346	* modify the actual register values while remapping/translation is enabled but they
347	* take effect only when explicitly signaled by software, hence we need to hold the
348	* active values separately.
349	* @{ */
350	/** Currently active IRTA_REG. */
351	uint64_t uIrtaReg;
352	/** Currently active RTADDR_REG. */
353	uint64_t uRtaddrReg;
354	/** @} */
355
356	/** @name Register copies for a tiny bit faster and more convenient access.
357	* @{ */
358	/** Copy of VER_REG. */
359	uint8_t uVerReg;
360	/** Alignment. */
361	uint8_t abPadding0[7];
362	/** Copy of CAP_REG. */
363	uint64_t fCapReg;
364	/** Copy of ECAP_REG. */
365	uint64_t fExtCapReg;
366	/** @} */
367
368	/** Host-address width (HAW) base address mask. */
369	uint64_t fHawBaseMask;
370	/** Maximum guest-address width (MGAW) invalid address mask. */
371	uint64_t fMgawInvMask;
372	/** Context-entry qword-1 valid mask. */
373	uint64_t fCtxEntryQw1ValidMask;
374	/** Maximum supported paging level (3, 4 or 5). */
375	uint8_t cMaxPagingLevel;
376	/** DMA request valid permissions mask. */
377	uint8_t fPermValidMask;
378	/** Alignment. */
379	uint8_t abPadding1[6];
380
381	/** The event semaphore the invalidation-queue thread waits on. */
382	SUPSEMEVENT hEvtInvQueue;
383	/** Error diagnostic. */
384	DMARDIAG enmDiag;
385	/** Padding. */
386	uint32_t uPadding0;
387	/** The MMIO handle. */
388	IOMMMIOHANDLE hMmio;
389
390	#ifdef VBOX_WITH_STATISTICS
391	STAMCOUNTER StatMmioReadR3; /*< Number of MMIO reads in R3. /
392	STAMCOUNTER StatMmioReadRZ; /*< Number of MMIO reads in RZ. /
393	STAMCOUNTER StatMmioWriteR3; /*< Number of MMIO writes in R3. /
394	STAMCOUNTER StatMmioWriteRZ; /*< Number of MMIO writes in RZ. /
395
396	STAMCOUNTER StatMsiRemapCfiR3; /*< Number of compatibility-format interrupts remap requests in R3. /
397	STAMCOUNTER StatMsiRemapCfiRZ; /*< Number of compatibility-format interrupts remap requests in RZ. /
398	STAMCOUNTER StatMsiRemapRfiR3; /*< Number of remappable-format interrupts remap requests in R3. /
399	STAMCOUNTER StatMsiRemapRfiRZ; /*< Number of remappable-format interrupts remap requests in RZ. /
400
401	STAMCOUNTER StatMemReadR3; /*< Number of memory read translation requests in R3. /
402	STAMCOUNTER StatMemReadRZ; /*< Number of memory read translation requests in RZ. /
403	STAMCOUNTER StatMemWriteR3; /*< Number of memory write translation requests in R3. /
404	STAMCOUNTER StatMemWriteRZ; /*< Number of memory write translation requests in RZ. /
405
406	STAMCOUNTER StatMemBulkReadR3; /*< Number of memory read bulk translation requests in R3. /
407	STAMCOUNTER StatMemBulkReadRZ; /*< Number of memory read bulk translation requests in RZ. /
408	STAMCOUNTER StatMemBulkWriteR3; /*< Number of memory write bulk translation requests in R3. /
409	STAMCOUNTER StatMemBulkWriteRZ; /*< Number of memory write bulk translation requests in RZ. /
410
411	STAMCOUNTER StatCcInvDsc; /*< Number of Context-cache descriptors processed. /
412	STAMCOUNTER StatIotlbInvDsc; /*< Number of IOTLB descriptors processed. /
413	STAMCOUNTER StatDevtlbInvDsc; /*< Number of Device-TLB descriptors processed. /
414	STAMCOUNTER StatIecInvDsc; /*< Number of Interrupt-Entry cache descriptors processed. /
415	STAMCOUNTER StatInvWaitDsc; /*< Number of Invalidation wait descriptors processed. /
416	STAMCOUNTER StatPasidIotlbInvDsc; /*< Number of PASID-based IOTLB descriptors processed. /
417	STAMCOUNTER StatPasidCacheInvDsc; /*< Number of PASID-cache descriptors processed. /
418	STAMCOUNTER StatPasidDevtlbInvDsc; /*< Number of PASID-based device-TLB descriptors processed. /
419	#endif
420	} DMAR;
421	/** Pointer to the DMAR device state. */
422	typedef DMAR *PDMAR;
423	/** Pointer to the const DMAR device state. */
424	typedef DMAR const *PCDMAR;
425	AssertCompileMemberAlignment(DMAR, abRegs0, 8);
426	AssertCompileMemberAlignment(DMAR, abRegs1, 8);
427
428	/**
429	* The ring-3 DMAR device state.
430	*/
431	typedef struct DMARR3
432	{
433	/** Device instance. */
434	PPDMDEVINSR3 pDevInsR3;
435	/** The IOMMU helper. */
436	R3PTRTYPE(PCPDMIOMMUHLPR3) pIommuHlpR3;
437	/** The invalidation-queue thread. */
438	R3PTRTYPE(PPDMTHREAD) pInvQueueThread;
439	} DMARR3;
440	/** Pointer to the ring-3 DMAR device state. */
441	typedef DMARR3 *PDMARR3;
442	/** Pointer to the const ring-3 DMAR device state. */
443	typedef DMARR3 const *PCDMARR3;
444
445	/**
446	* The ring-0 DMAR device state.
447	*/
448	typedef struct DMARR0
449	{
450	/** Device instance. */
451	PPDMDEVINSR0 pDevInsR0;
452	/** The IOMMU helper. */
453	R0PTRTYPE(PCPDMIOMMUHLPR0) pIommuHlpR0;
454	} DMARR0;
455	/** Pointer to the ring-0 IOMMU device state. */
456	typedef DMARR0 *PDMARR0;
457	/** Pointer to the const ring-0 IOMMU device state. */
458	typedef DMARR0 const *PCDMARR0;
459
460	/**
461	* The raw-mode DMAR device state.
462	*/
463	typedef struct DMARRC
464	{
465	/** Device instance. */
466	PPDMDEVINSRC pDevInsRC;
467	/** The IOMMU helper. */
468	RCPTRTYPE(PCPDMIOMMUHLPRC) pIommuHlpRC;
469	} DMARRC;
470	/** Pointer to the raw-mode DMAR device state. */
471	typedef DMARRC *PDMARRC;
472	/** Pointer to the const raw-mode DMAR device state. */
473	typedef DMARRC const *PCIDMARRC;
474
475	/** The DMAR device state for the current context. */
476	typedef CTX_SUFF(DMAR) DMARCC;
477	/** Pointer to the DMAR device state for the current context. */
478	typedef CTX_SUFF(PDMAR) PDMARCC;
479	/** Pointer to the const DMAR device state for the current context. */
480	typedef CTX_SUFF(PDMAR) const PCDMARCC;
481
482	/**
483	* DMAR originated events that generate interrupts.
484	*/
485	typedef enum DMAREVENTTYPE
486	{
487	/** Invalidation completion event. */
488	DMAREVENTTYPE_INV_COMPLETE = 0,
489	/** Fault event. */
490	DMAREVENTTYPE_FAULT
491	} DMAREVENTTYPE;
492
493	/**
494	* I/O Page.
495	*/
496	typedef struct DMARIOPAGE
497	{
498	/** The base DMA address of a page. */
499	RTGCPHYS GCPhysBase;
500	/** The page shift. */
501	uint8_t cShift;
502	/** The permissions of this page (DMAR_PERM_XXX). */
503	uint8_t fPerm;
504	} DMARIOPAGE;
505	/** Pointer to an I/O page. */
506	typedef DMARIOPAGE *PDMARIOPAGE;
507	/** Pointer to a const I/O address range. */
508	typedef DMARIOPAGE const *PCDMARIOPAGE;
509
510	/**
511	* I/O Address Range.
512	*/
513	typedef struct DMARIOADDRRANGE
514	{
515	/** The starting DMA address of this range. */
516	uint64_t uAddr;
517	/** The size of the range (in bytes). */
518	size_t cb;
519	/** The permissions of this range (DMAR_PERM_XXX). */
520	uint8_t fPerm;
521	} DMARIOADDRRANGE;
522	/** Pointer to an I/O address range. */
523	typedef DMARIOADDRRANGE *PDMARIOADDRRANGE;
524	/** Pointer to a const I/O address range. */
525	typedef DMARIOADDRRANGE const *PCDMARIOADDRRANGE;
526
527	/**
528	* DMA Memory Request (Input).
529	*/
530	typedef struct DMARMEMREQIN
531	{
532	/** The address range being accessed. */
533	DMARIOADDRRANGE AddrRange;
534	/** The source device ID (bus, device, function). */
535	uint16_t idDevice;
536	/** The PASID if present (can be NIL_PCIPASID). */
537	PCIPASID Pasid;
538	/* The address translation type. */
539	PCIADDRTYPE enmAddrType;
540	/** The request type. */
541	VTDREQTYPE enmReqType;
542	} DMARMEMREQIN;
543	/** Pointer to a DMA memory request input. */
544	typedef DMARMEMREQIN *PDMARMEMREQIN;
545	/** Pointer to a const DMA memory input. */
546	typedef DMARMEMREQIN const *PCDMARMEMREQIN;
547
548	/**
549	* DMA Memory Request (Output).
550	*/
551	typedef struct DMARMEMREQOUT
552	{
553	/** The address range of the translated region. */
554	DMARIOADDRRANGE AddrRange;
555	/** The domain ID of the translated region. */
556	uint16_t idDomain;
557	} DMARMEMREQOUT;
558	/** Pointer to a DMA memory request output. */
559	typedef DMARMEMREQOUT *PDMARMEMREQOUT;
560	/** Pointer to a const DMA memory request output. */
561	typedef DMARMEMREQOUT const *PCDMARMEMREQOUT;
562
563	/**
564	* DMA Memory Request (Auxiliary Info).
565	* These get updated and used as part of the translation process.
566	*/
567	typedef struct DMARMEMREQAUX
568	{
569	/** The table translation mode (VTD_TTM_XXX). */
570	uint8_t fTtm;
571	/** The fault processing disabled (FPD) bit. */
572	uint8_t fFpd;
573	/** The paging level of the translation. */
574	uint8_t cPagingLevel;
575	uint8_t abPadding[5];
576	/** The address of the first-level page-table. */
577	uint64_t GCPhysFlPt;
578	/** The address of second-level page-table. */
579	uint64_t GCPhysSlPt;
580	} DMARMEMREQAUX;
581	/** Pointer to a DMA memory request output. */
582	typedef DMARMEMREQAUX *PDMARMEMREQAUX;
583	/** Pointer to a const DMA memory request output. */
584	typedef DMARMEMREQAUX const *PCDMARMEMREQAUX;
585
586	/**
587	* DMA Memory Request Remapping Information.
588	*/
589	typedef struct DMARMEMREQREMAP
590	{
591	/** The DMA memory request input. */
592	DMARMEMREQIN In;
593	/** DMA memory request auxiliary information. */
594	DMARMEMREQAUX Aux;
595	/** The DMA memory request output. */
596	DMARMEMREQOUT Out;
597	} DMARMEMREQREMAP;
598	/** Pointer to a DMA remap info. */
599	typedef DMARMEMREQREMAP *PDMARMEMREQREMAP;
600	/** Pointer to a const DMA remap info. */
601	typedef DMARMEMREQREMAP const *PCDMARMEMREQREMAP;
602
603	/**
604	* Callback function to lookup a DMA address.
605	*
606	* @returns VBox status code.
607	* @param pDevIns The IOMMU device instance.
608	* @param pMemReqIn The DMA memory request input.
609	* @param pMemReqAux The DMA memory request auxiliary info.
610	* @param pIoPageOut Where to store the output of the lookup.
611	*/
612	typedef DECLCALLBACKTYPE(int, FNDMADDRLOOKUP,(PPDMDEVINS pDevIns, PCDMARMEMREQIN pMemReqIn, PCDMARMEMREQAUX pMemReqAux,
613	PDMARIOPAGE pIoPageOut));
614	/** Pointer to a DMA address-lookup function. */
615	typedef FNDMADDRLOOKUP *PFNDMADDRLOOKUP;
616
617
618	/*********************************************************************************************************************************
619	* Global Variables *
620	*********************************************************************************************************************************/
621	/**
622	* Read-write masks for DMAR registers (group 0).
623	*/
624	static uint32_t const g_au32RwMasks0[] =
625	{
626	/* Offset Register Low High */
627	/* 0x000 VER_REG */ VTD_VER_REG_RW_MASK,
628	/* 0x004 Reserved */ 0,
629	/* 0x008 CAP_REG */ DMAR_LO_U32(VTD_CAP_REG_RW_MASK), DMAR_HI_U32(VTD_CAP_REG_RW_MASK),
630	/* 0x010 ECAP_REG */ DMAR_LO_U32(VTD_ECAP_REG_RW_MASK), DMAR_HI_U32(VTD_ECAP_REG_RW_MASK),
631	/* 0x018 GCMD_REG */ VTD_GCMD_REG_RW_MASK,
632	/* 0x01c GSTS_REG */ VTD_GSTS_REG_RW_MASK,
633	/* 0x020 RTADDR_REG */ DMAR_LO_U32(VTD_RTADDR_REG_RW_MASK), DMAR_HI_U32(VTD_RTADDR_REG_RW_MASK),
634	/* 0x028 CCMD_REG */ DMAR_LO_U32(VTD_CCMD_REG_RW_MASK), DMAR_HI_U32(VTD_CCMD_REG_RW_MASK),
635	/* 0x030 Reserved */ 0,
636	/* 0x034 FSTS_REG */ VTD_FSTS_REG_RW_MASK,
637	/* 0x038 FECTL_REG */ VTD_FECTL_REG_RW_MASK,
638	/* 0x03c FEDATA_REG */ VTD_FEDATA_REG_RW_MASK,
639	/* 0x040 FEADDR_REG */ VTD_FEADDR_REG_RW_MASK,
640	/* 0x044 FEUADDR_REG */ VTD_FEUADDR_REG_RW_MASK,
641	/* 0x048 Reserved */ 0, 0,
642	/* 0x050 Reserved */ 0, 0,
643	/* 0x058 AFLOG_REG */ DMAR_LO_U32(VTD_AFLOG_REG_RW_MASK), DMAR_HI_U32(VTD_AFLOG_REG_RW_MASK),
644	/* 0x060 Reserved */ 0,
645	/* 0x064 PMEN_REG / 0, / RO as we don't support PLMR and PHMR. */
646	/* 0x068 PLMBASE_REG / 0, / RO as we don't support PLMR. */
647	/* 0x06c PLMLIMIT_REG / 0, / RO as we don't support PLMR. */
648	/* 0x070 PHMBASE_REG / 0, 0, / RO as we don't support PHMR. */
649	/* 0x078 PHMLIMIT_REG / 0, 0, / RO as we don't support PHMR. */
650	/* 0x080 IQH_REG */ DMAR_LO_U32(VTD_IQH_REG_RW_MASK), DMAR_HI_U32(VTD_IQH_REG_RW_MASK),
651	/* 0x088 IQT_REG */ DMAR_LO_U32(VTD_IQT_REG_RW_MASK), DMAR_HI_U32(VTD_IQT_REG_RW_MASK),
652	/* 0x090 IQA_REG */ DMAR_LO_U32(VTD_IQA_REG_RW_MASK), DMAR_HI_U32(VTD_IQA_REG_RW_MASK),
653	/* 0x098 Reserved */ 0,
654	/* 0x09c ICS_REG */ VTD_ICS_REG_RW_MASK,
655	/* 0x0a0 IECTL_REG */ VTD_IECTL_REG_RW_MASK,
656	/* 0x0a4 IEDATA_REG */ VTD_IEDATA_REG_RW_MASK,
657	/* 0x0a8 IEADDR_REG */ VTD_IEADDR_REG_RW_MASK,
658	/* 0x0ac IEUADDR_REG */ VTD_IEUADDR_REG_RW_MASK,
659	/* 0x0b0 IQERCD_REG */ DMAR_LO_U32(VTD_IQERCD_REG_RW_MASK), DMAR_HI_U32(VTD_IQERCD_REG_RW_MASK),
660	/* 0x0b8 IRTA_REG */ DMAR_LO_U32(VTD_IRTA_REG_RW_MASK), DMAR_HI_U32(VTD_IRTA_REG_RW_MASK),
661	/* 0x0c0 PQH_REG */ DMAR_LO_U32(VTD_PQH_REG_RW_MASK), DMAR_HI_U32(VTD_PQH_REG_RW_MASK),
662	/* 0x0c8 PQT_REG */ DMAR_LO_U32(VTD_PQT_REG_RW_MASK), DMAR_HI_U32(VTD_PQT_REG_RW_MASK),
663	/* 0x0d0 PQA_REG */ DMAR_LO_U32(VTD_PQA_REG_RW_MASK), DMAR_HI_U32(VTD_PQA_REG_RW_MASK),
664	/* 0x0d8 Reserved */ 0,
665	/* 0x0dc PRS_REG */ VTD_PRS_REG_RW_MASK,
666	/* 0x0e0 PECTL_REG */ VTD_PECTL_REG_RW_MASK,
667	/* 0x0e4 PEDATA_REG */ VTD_PEDATA_REG_RW_MASK,
668	/* 0x0e8 PEADDR_REG */ VTD_PEADDR_REG_RW_MASK,
669	/* 0x0ec PEUADDR_REG */ VTD_PEUADDR_REG_RW_MASK,
670	/* 0x0f0 Reserved */ 0, 0,
671	/* 0x0f8 Reserved */ 0, 0,
672	/* 0x100 MTRRCAP_REG */ DMAR_LO_U32(VTD_MTRRCAP_REG_RW_MASK), DMAR_HI_U32(VTD_MTRRCAP_REG_RW_MASK),
673	/* 0x108 MTRRDEF_REG / 0, 0, / RO as we don't support MTS. */
674	/* 0x110 Reserved */ 0, 0,
675	/* 0x118 Reserved */ 0, 0,
676	/* 0x120 MTRR_FIX64_00000_REG / 0, 0, / RO as we don't support MTS. */
677	/* 0x128 MTRR_FIX16K_80000_REG */ 0, 0,
678	/* 0x130 MTRR_FIX16K_A0000_REG */ 0, 0,
679	/* 0x138 MTRR_FIX4K_C0000_REG */ 0, 0,
680	/* 0x140 MTRR_FIX4K_C8000_REG */ 0, 0,
681	/* 0x148 MTRR_FIX4K_D0000_REG */ 0, 0,
682	/* 0x150 MTRR_FIX4K_D8000_REG */ 0, 0,
683	/* 0x158 MTRR_FIX4K_E0000_REG */ 0, 0,
684	/* 0x160 MTRR_FIX4K_E8000_REG */ 0, 0,
685	/* 0x168 MTRR_FIX4K_F0000_REG */ 0, 0,
686	/* 0x170 MTRR_FIX4K_F8000_REG */ 0, 0,
687	/* 0x178 Reserved */ 0, 0,
688	/* 0x180 MTRR_PHYSBASE0_REG / 0, 0, / RO as we don't support MTS. */
689	/* 0x188 MTRR_PHYSMASK0_REG */ 0, 0,
690	/* 0x190 MTRR_PHYSBASE1_REG */ 0, 0,
691	/* 0x198 MTRR_PHYSMASK1_REG */ 0, 0,
692	/* 0x1a0 MTRR_PHYSBASE2_REG */ 0, 0,
693	/* 0x1a8 MTRR_PHYSMASK2_REG */ 0, 0,
694	/* 0x1b0 MTRR_PHYSBASE3_REG */ 0, 0,
695	/* 0x1b8 MTRR_PHYSMASK3_REG */ 0, 0,
696	/* 0x1c0 MTRR_PHYSBASE4_REG */ 0, 0,
697	/* 0x1c8 MTRR_PHYSMASK4_REG */ 0, 0,
698	/* 0x1d0 MTRR_PHYSBASE5_REG */ 0, 0,
699	/* 0x1d8 MTRR_PHYSMASK5_REG */ 0, 0,
700	/* 0x1e0 MTRR_PHYSBASE6_REG */ 0, 0,
701	/* 0x1e8 MTRR_PHYSMASK6_REG */ 0, 0,
702	/* 0x1f0 MTRR_PHYSBASE7_REG */ 0, 0,
703	/* 0x1f8 MTRR_PHYSMASK7_REG */ 0, 0,
704	/* 0x200 MTRR_PHYSBASE8_REG */ 0, 0,
705	/* 0x208 MTRR_PHYSMASK8_REG */ 0, 0,
706	/* 0x210 MTRR_PHYSBASE9_REG */ 0, 0,
707	/* 0x218 MTRR_PHYSMASK9_REG */ 0, 0,
708	};
709	AssertCompile(sizeof(g_au32RwMasks0) == DMAR_MMIO_GROUP_0_SIZE);
710
711	/**
712	* Read-only Status, Write-1-to-clear masks for DMAR registers (group 0).
713	*/
714	static uint32_t const g_au32Rw1cMasks0[] =
715	{
716	/* Offset Register Low High */
717	/* 0x000 VER_REG */ 0,
718	/* 0x004 Reserved */ 0,
719	/* 0x008 CAP_REG */ 0, 0,
720	/* 0x010 ECAP_REG */ 0, 0,
721	/* 0x018 GCMD_REG */ 0,
722	/* 0x01c GSTS_REG */ 0,
723	/* 0x020 RTADDR_REG */ 0, 0,
724	/* 0x028 CCMD_REG */ 0, 0,
725	/* 0x030 Reserved */ 0,
726	/* 0x034 FSTS_REG */ VTD_FSTS_REG_RW1C_MASK,
727	/* 0x038 FECTL_REG */ 0,
728	/* 0x03c FEDATA_REG */ 0,
729	/* 0x040 FEADDR_REG */ 0,
730	/* 0x044 FEUADDR_REG */ 0,
731	/* 0x048 Reserved */ 0, 0,
732	/* 0x050 Reserved */ 0, 0,
733	/* 0x058 AFLOG_REG */ 0, 0,
734	/* 0x060 Reserved */ 0,
735	/* 0x064 PMEN_REG */ 0,
736	/* 0x068 PLMBASE_REG */ 0,
737	/* 0x06c PLMLIMIT_REG */ 0,
738	/* 0x070 PHMBASE_REG */ 0, 0,
739	/* 0x078 PHMLIMIT_REG */ 0, 0,
740	/* 0x080 IQH_REG */ 0, 0,
741	/* 0x088 IQT_REG */ 0, 0,
742	/* 0x090 IQA_REG */ 0, 0,
743	/* 0x098 Reserved */ 0,
744	/* 0x09c ICS_REG */ VTD_ICS_REG_RW1C_MASK,
745	/* 0x0a0 IECTL_REG */ 0,
746	/* 0x0a4 IEDATA_REG */ 0,
747	/* 0x0a8 IEADDR_REG */ 0,
748	/* 0x0ac IEUADDR_REG */ 0,
749	/* 0x0b0 IQERCD_REG */ 0, 0,
750	/* 0x0b8 IRTA_REG */ 0, 0,
751	/* 0x0c0 PQH_REG */ 0, 0,
752	/* 0x0c8 PQT_REG */ 0, 0,
753	/* 0x0d0 PQA_REG */ 0, 0,
754	/* 0x0d8 Reserved */ 0,
755	/* 0x0dc PRS_REG */ 0,
756	/* 0x0e0 PECTL_REG */ 0,
757	/* 0x0e4 PEDATA_REG */ 0,
758	/* 0x0e8 PEADDR_REG */ 0,
759	/* 0x0ec PEUADDR_REG */ 0,
760	/* 0x0f0 Reserved */ 0, 0,
761	/* 0x0f8 Reserved */ 0, 0,
762	/* 0x100 MTRRCAP_REG */ 0, 0,
763	/* 0x108 MTRRDEF_REG */ 0, 0,
764	/* 0x110 Reserved */ 0, 0,
765	/* 0x118 Reserved */ 0, 0,
766	/* 0x120 MTRR_FIX64_00000_REG */ 0, 0,
767	/* 0x128 MTRR_FIX16K_80000_REG */ 0, 0,
768	/* 0x130 MTRR_FIX16K_A0000_REG */ 0, 0,
769	/* 0x138 MTRR_FIX4K_C0000_REG */ 0, 0,
770	/* 0x140 MTRR_FIX4K_C8000_REG */ 0, 0,
771	/* 0x148 MTRR_FIX4K_D0000_REG */ 0, 0,
772	/* 0x150 MTRR_FIX4K_D8000_REG */ 0, 0,
773	/* 0x158 MTRR_FIX4K_E0000_REG */ 0, 0,
774	/* 0x160 MTRR_FIX4K_E8000_REG */ 0, 0,
775	/* 0x168 MTRR_FIX4K_F0000_REG */ 0, 0,
776	/* 0x170 MTRR_FIX4K_F8000_REG */ 0, 0,
777	/* 0x178 Reserved */ 0, 0,
778	/* 0x180 MTRR_PHYSBASE0_REG */ 0, 0,
779	/* 0x188 MTRR_PHYSMASK0_REG */ 0, 0,
780	/* 0x190 MTRR_PHYSBASE1_REG */ 0, 0,
781	/* 0x198 MTRR_PHYSMASK1_REG */ 0, 0,
782	/* 0x1a0 MTRR_PHYSBASE2_REG */ 0, 0,
783	/* 0x1a8 MTRR_PHYSMASK2_REG */ 0, 0,
784	/* 0x1b0 MTRR_PHYSBASE3_REG */ 0, 0,
785	/* 0x1b8 MTRR_PHYSMASK3_REG */ 0, 0,
786	/* 0x1c0 MTRR_PHYSBASE4_REG */ 0, 0,
787	/* 0x1c8 MTRR_PHYSMASK4_REG */ 0, 0,
788	/* 0x1d0 MTRR_PHYSBASE5_REG */ 0, 0,
789	/* 0x1d8 MTRR_PHYSMASK5_REG */ 0, 0,
790	/* 0x1e0 MTRR_PHYSBASE6_REG */ 0, 0,
791	/* 0x1e8 MTRR_PHYSMASK6_REG */ 0, 0,
792	/* 0x1f0 MTRR_PHYSBASE7_REG */ 0, 0,
793	/* 0x1f8 MTRR_PHYSMASK7_REG */ 0, 0,
794	/* 0x200 MTRR_PHYSBASE8_REG */ 0, 0,
795	/* 0x208 MTRR_PHYSMASK8_REG */ 0, 0,
796	/* 0x210 MTRR_PHYSBASE9_REG */ 0, 0,
797	/* 0x218 MTRR_PHYSMASK9_REG */ 0, 0,
798	};
799	AssertCompile(sizeof(g_au32Rw1cMasks0) == DMAR_MMIO_GROUP_0_SIZE);
800
801	/**
802	* Read-write masks for DMAR registers (group 1).
803	*/
804	static uint32_t const g_au32RwMasks1[] =
805	{
806	/* Offset Register Low High */
807	/* 0xe00 VCCAP_REG */ DMAR_LO_U32(VTD_VCCAP_REG_RW_MASK), DMAR_HI_U32(VTD_VCCAP_REG_RW_MASK),
808	/* 0xe08 VCMD_EO_REG */ DMAR_LO_U32(VTD_VCMD_EO_REG_RW_MASK), DMAR_HI_U32(VTD_VCMD_EO_REG_RW_MASK),
809	/* 0xe10 VCMD_REG / 0, 0, / RO: VCS not supported. */
810	/* 0xe18 VCMDRSVD_REG */ 0, 0,
811	/* 0xe20 VCRSP_REG / 0, 0, / RO: VCS not supported. */
812	/* 0xe28 VCRSPRSVD_REG */ 0, 0,
813	/* 0xe30 Reserved */ 0, 0,
814	/* 0xe38 Reserved */ 0, 0,
815	/* 0xe40 Reserved */ 0, 0,
816	/* 0xe48 Reserved */ 0, 0,
817	/* 0xe50 IVA_REG */ DMAR_LO_U32(VTD_IVA_REG_RW_MASK), DMAR_HI_U32(VTD_IVA_REG_RW_MASK),
818	/* 0xe58 IOTLB_REG */ DMAR_LO_U32(VTD_IOTLB_REG_RW_MASK), DMAR_HI_U32(VTD_IOTLB_REG_RW_MASK),
819	/* 0xe60 Reserved */ 0, 0,
820	/* 0xe68 Reserved */ 0, 0,
821	/* 0xe70 FRCD_REG_LO */ DMAR_LO_U32(VTD_FRCD_REG_LO_RW_MASK), DMAR_HI_U32(VTD_FRCD_REG_LO_RW_MASK),
822	/* 0xe78 FRCD_REG_HI */ DMAR_LO_U32(VTD_FRCD_REG_HI_RW_MASK), DMAR_HI_U32(VTD_FRCD_REG_HI_RW_MASK),
823	};
824	AssertCompile(sizeof(g_au32RwMasks1) == DMAR_MMIO_GROUP_1_SIZE);
825	AssertCompile((DMAR_MMIO_OFF_FRCD_LO_REG - DMAR_MMIO_GROUP_1_OFF_FIRST) + DMAR_FRCD_REG_COUNT * 2 * sizeof(uint64_t) );
826
827	/**
828	* Read-only Status, Write-1-to-clear masks for DMAR registers (group 1).
829	*/
830	static uint32_t const g_au32Rw1cMasks1[] =
831	{
832	/* Offset Register Low High */
833	/* 0xe00 VCCAP_REG */ 0, 0,
834	/* 0xe08 VCMD_EO_REG */ 0, 0,
835	/* 0xe10 VCMD_REG */ 0, 0,
836	/* 0xe18 VCMDRSVD_REG */ 0, 0,
837	/* 0xe20 VCRSP_REG */ 0, 0,
838	/* 0xe28 VCRSPRSVD_REG */ 0, 0,
839	/* 0xe30 Reserved */ 0, 0,
840	/* 0xe38 Reserved */ 0, 0,
841	/* 0xe40 Reserved */ 0, 0,
842	/* 0xe48 Reserved */ 0, 0,
843	/* 0xe50 IVA_REG */ 0, 0,
844	/* 0xe58 IOTLB_REG */ 0, 0,
845	/* 0xe60 Reserved */ 0, 0,
846	/* 0xe68 Reserved */ 0, 0,
847	/* 0xe70 FRCD_REG_LO */ DMAR_LO_U32(VTD_FRCD_REG_LO_RW1C_MASK), DMAR_HI_U32(VTD_FRCD_REG_LO_RW1C_MASK),
848	/* 0xe78 FRCD_REG_HI */ DMAR_LO_U32(VTD_FRCD_REG_HI_RW1C_MASK), DMAR_HI_U32(VTD_FRCD_REG_HI_RW1C_MASK),
849	};
850	AssertCompile(sizeof(g_au32Rw1cMasks1) == DMAR_MMIO_GROUP_1_SIZE);
851
852	/** Array of RW masks for each register group. */
853	static uint8_t const g_apbRwMasks[] = { (uint8_t )&g_au32RwMasks0[0], (uint8_t *)&g_au32RwMasks1[0] };
854
855	/** Array of RW1C masks for each register group. */
856	static uint8_t const g_apbRw1cMasks[] = { (uint8_t )&g_au32Rw1cMasks0[0], (uint8_t *)&g_au32Rw1cMasks1[0] };
857
858	/* Masks arrays must be identical in size (even bounds checking code assumes this). */
859	AssertCompile(sizeof(g_apbRw1cMasks) == sizeof(g_apbRwMasks));
860
861	#ifdef IN_RING3
862	/** Array of valid domain-ID bits. */
863	static uint16_t const g_auNdMask[] = { 0xf, 0x3f, 0xff, 0x3ff, 0xfff, 0x3fff, 0xffff, 0 };
864	AssertCompile(RT_ELEMENTS(g_auNdMask) >= DMAR_ND);
865	#endif
866
867
868	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
869	#ifdef IN_RING3
870	/**
871	* Returns the supported adjusted guest-address width (SAGAW) given the maximum
872	* guest address width (MGAW).
873	*
874	* @returns The CAP_REG.SAGAW value.
875	* @param uMgaw The CAP_REG.MGAW value.
876	*/
877	static uint8_t vtdCapRegGetSagaw(uint8_t uMgaw)
878	{
879	/*
880	* It doesn't make sense to me that a CPU (or IOMMU hardware) will ever support
881	* 5-level paging but not 4 or 3-level paging. So smaller page-table levels
882	* are always OR'ed in below.
883	*
884	* The bit values below (57, 48, 39 bits) represents the levels of page-table walks
885	* for 4KB base page size (5-level, 4-level and 3-level paging respectively).
886	*
887	* See Intel VT-d spec. 10.4.2 "Capability Register".
888	*/
889	++uMgaw;
890	uint8_t const fSagaw = uMgaw >= 57 ? RT_BIT(3) \| RT_BIT(2) \| RT_BIT(1)
891	: uMgaw >= 48 ? RT_BIT(2) \| RT_BIT(1)
892	: uMgaw >= 39 ? RT_BIT(1)
893	: 0;
894	return fSagaw;
895	}
896
897
898	/**
899	* Returns the maximum supported paging level given the supported adjusted
900	* guest-address width (SAGAW) field.
901	*
902	* @returns The highest paging level supported, 0 if invalid.
903	* @param fSagaw The CAP_REG.SAGAW value.
904	*/
905	static uint8_t vtdCapRegGetMaxPagingLevel(uint8_t fSagaw)
906	{
907	uint8_t const cMaxPagingLevel = fSagaw & RT_BIT(3) ? 5
908	: fSagaw & RT_BIT(2) ? 4
909	: fSagaw & RT_BIT(1) ? 3
910	: 0;
911	return cMaxPagingLevel;
912	}
913
914
915	/**
916	* Returns table translation mode's descriptive name.
917	*
918	* @returns The descriptive name.
919	* @param uTtm The RTADDR_REG.TTM value.
920	*/
921	static const char* vtdRtaddrRegGetTtmDesc(uint8_t uTtm)
922	{
923	Assert(!(uTtm & 3));
924	static const char* s_apszTtmNames[] =
925	{
926	"Legacy Mode",
927	"Scalable Mode",
928	"Reserved",
929	"Abort-DMA Mode"
930	};
931	return s_apszTtmNames[uTtm & (RT_ELEMENTS(s_apszTtmNames) - 1)];
932	}
933	#endif /* IN_RING3 */
934
935
936	/**
937	* Returns whether the interrupt remapping (IR) fault is qualified or not.
938	*
939	* @returns @c true if qualified, @c false otherwise.
940	* @param enmIrFault The interrupt remapping fault condition.
941	*/
942	static bool vtdIrFaultIsQualified(VTDIRFAULT enmIrFault)
943	{
944	switch (enmIrFault)
945	{
946	case VTDIRFAULT_IRTE_NOT_PRESENT:
947	case VTDIRFAULT_IRTE_PRESENT_RSVD:
948	case VTDIRFAULT_IRTE_PRESENT_INVALID:
949	case VTDIRFAULT_PID_READ_FAILED:
950	case VTDIRFAULT_PID_RSVD:
951	return true;
952	default:
953	return false;
954	}
955	}
956
957
958	/**
959	* Gets the index of the group the register belongs to given its MMIO offset.
960	*
961	* @returns The group index.
962	* @param offReg The MMIO offset of the register.
963	* @param cbReg The size of the access being made (for bounds checking on
964	* debug builds).
965	*/
966	DECLINLINE(uint8_t) dmarRegGetGroupIndex(uint16_t offReg, uint8_t cbReg)
967	{
968	uint16_t const offLast = offReg + cbReg - 1;
969	AssertCompile(DMAR_MMIO_GROUP_0_OFF_FIRST == 0);
970	AssertMsg(DMAR_IS_MMIO_OFF_VALID(offLast), ("off=%#x cb=%u\n", offReg, cbReg));
971	return !(offLast < DMAR_MMIO_GROUP_0_OFF_END);
972	}
973
974
975	/**
976	* Gets the group the register belongs to given its MMIO offset.
977	*
978	* @returns Pointer to the first element of the register group.
979	* @param pThis The shared DMAR device state.
980	* @param offReg The MMIO offset of the register.
981	* @param cbReg The size of the access being made (for bounds checking on
982	* debug builds).
983	* @param pIdxGroup Where to store the index of the register group the register
984	* belongs to.
985	*/
986	DECLINLINE(uint8_t ) dmarRegGetGroup(PDMAR pThis, uint16_t offReg, uint8_t cbReg, uint8_t pIdxGroup)
987	{
988	*pIdxGroup = dmarRegGetGroupIndex(offReg, cbReg);
989	uint8_t *apbRegs[] = { &pThis->abRegs0[0], &pThis->abRegs1[0] };
990	return apbRegs[*pIdxGroup];
991	}
992
993
994	/**
995	* Const/read-only version of dmarRegGetGroup.
996	*
997	* @copydoc dmarRegGetGroup
998	*/
999	DECLINLINE(uint8_t const) dmarRegGetGroupRo(PCDMAR pThis, uint16_t offReg, uint8_t cbReg, uint8_t pIdxGroup)
1000	{
1001	*pIdxGroup = dmarRegGetGroupIndex(offReg, cbReg);
1002	uint8_t const *apbRegs[] = { &pThis->abRegs0[0], &pThis->abRegs1[0] };
1003	return apbRegs[*pIdxGroup];
1004	}
1005
1006
1007	/**
1008	* Writes a 32-bit register with the exactly the supplied value.
1009	*
1010	* @param pThis The shared DMAR device state.
1011	* @param offReg The MMIO offset of the register.
1012	* @param uReg The 32-bit value to write.
1013	*/
1014	static void dmarRegWriteRaw32(PDMAR pThis, uint16_t offReg, uint32_t uReg)
1015	{
1016	uint8_t idxGroup;
1017	uint8_t *pabRegs = dmarRegGetGroup(pThis, offReg, sizeof(uint32_t), &idxGroup);
1018	NOREF(idxGroup);
1019	(uint32_t )(pabRegs + offReg) = uReg;
1020	}
1021
1022
1023	/**
1024	* Writes a 64-bit register with the exactly the supplied value.
1025	*
1026	* @param pThis The shared DMAR device state.
1027	* @param offReg The MMIO offset of the register.
1028	* @param uReg The 64-bit value to write.
1029	*/
1030	static void dmarRegWriteRaw64(PDMAR pThis, uint16_t offReg, uint64_t uReg)
1031	{
1032	uint8_t idxGroup;
1033	uint8_t *pabRegs = dmarRegGetGroup(pThis, offReg, sizeof(uint64_t), &idxGroup);
1034	NOREF(idxGroup);
1035	(uint64_t )(pabRegs + offReg) = uReg;
1036	}
1037
1038
1039	/**
1040	* Reads a 32-bit register with exactly the value it contains.
1041	*
1042	* @returns The raw register value.
1043	* @param pThis The shared DMAR device state.
1044	* @param offReg The MMIO offset of the register.
1045	*/
1046	static uint32_t dmarRegReadRaw32(PCDMAR pThis, uint16_t offReg)
1047	{
1048	uint8_t idxGroup;
1049	uint8_t const *pabRegs = dmarRegGetGroupRo(pThis, offReg, sizeof(uint32_t), &idxGroup);
1050	NOREF(idxGroup);
1051	return (uint32_t )(pabRegs + offReg);
1052	}
1053
1054
1055	/**
1056	* Reads a 64-bit register with exactly the value it contains.
1057	*
1058	* @returns The raw register value.
1059	* @param pThis The shared DMAR device state.
1060	* @param offReg The MMIO offset of the register.
1061	*/
1062	static uint64_t dmarRegReadRaw64(PCDMAR pThis, uint16_t offReg)
1063	{
1064	uint8_t idxGroup;
1065	uint8_t const *pabRegs = dmarRegGetGroupRo(pThis, offReg, sizeof(uint64_t), &idxGroup);
1066	NOREF(idxGroup);
1067	return (uint64_t )(pabRegs + offReg);
1068	}
1069
1070
1071	/**
1072	* Reads a 32-bit register with exactly the value it contains along with their
1073	* corresponding masks
1074	*
1075	* @param pThis The shared DMAR device state.
1076	* @param offReg The MMIO offset of the register.
1077	* @param puReg Where to store the raw 32-bit register value.
1078	* @param pfRwMask Where to store the RW mask corresponding to this register.
1079	* @param pfRw1cMask Where to store the RW1C mask corresponding to this register.
1080	*/
1081	static void dmarRegReadRaw32Ex(PCDMAR pThis, uint16_t offReg, uint32_t puReg, uint32_t pfRwMask, uint32_t *pfRw1cMask)
1082	{
1083	uint8_t idxGroup;
1084	uint8_t const *pabRegs = dmarRegGetGroupRo(pThis, offReg, sizeof(uint32_t), &idxGroup);
1085	Assert(idxGroup < RT_ELEMENTS(g_apbRwMasks));
1086	uint8_t const *pabRwMasks = g_apbRwMasks[idxGroup];
1087	uint8_t const *pabRw1cMasks = g_apbRw1cMasks[idxGroup];
1088	puReg = (uint32_t *)(pabRegs + offReg);
1089	pfRwMask = (uint32_t *)(pabRwMasks + offReg);
1090	pfRw1cMask = (uint32_t *)(pabRw1cMasks + offReg);
1091	}
1092
1093
1094	/**
1095	* Reads a 64-bit register with exactly the value it contains along with their
1096	* corresponding masks.
1097	*
1098	* @param pThis The shared DMAR device state.
1099	* @param offReg The MMIO offset of the register.
1100	* @param puReg Where to store the raw 64-bit register value.
1101	* @param pfRwMask Where to store the RW mask corresponding to this register.
1102	* @param pfRw1cMask Where to store the RW1C mask corresponding to this register.
1103	*/
1104	static void dmarRegReadRaw64Ex(PCDMAR pThis, uint16_t offReg, uint64_t puReg, uint64_t pfRwMask, uint64_t *pfRw1cMask)
1105	{
1106	uint8_t idxGroup;
1107	uint8_t const *pabRegs = dmarRegGetGroupRo(pThis, offReg, sizeof(uint64_t), &idxGroup);
1108	Assert(idxGroup < RT_ELEMENTS(g_apbRwMasks));
1109	uint8_t const *pabRwMasks = g_apbRwMasks[idxGroup];
1110	uint8_t const *pabRw1cMasks = g_apbRw1cMasks[idxGroup];
1111	puReg = (uint64_t *)(pabRegs + offReg);
1112	pfRwMask = (uint64_t *)(pabRwMasks + offReg);
1113	pfRw1cMask = (uint64_t *)(pabRw1cMasks + offReg);
1114	}
1115
1116
1117	/**
1118	* Writes a 32-bit register as it would be when written by software.
1119	* This will preserve read-only bits, mask off reserved bits and clear RW1C bits.
1120	*
1121	* @returns The value that's actually written to the register.
1122	* @param pThis The shared DMAR device state.
1123	* @param offReg The MMIO offset of the register.
1124	* @param uReg The 32-bit value to write.
1125	* @param puPrev Where to store the register value prior to writing.
1126	*/
1127	static uint32_t dmarRegWrite32(PDMAR pThis, uint16_t offReg, uint32_t uReg, uint32_t *puPrev)
1128	{
1129	/* Read current value from the 32-bit register. */
1130	uint32_t uCurReg;
1131	uint32_t fRwMask;
1132	uint32_t fRw1cMask;
1133	dmarRegReadRaw32Ex(pThis, offReg, &uCurReg, &fRwMask, &fRw1cMask);
1134	*puPrev = uCurReg;
1135
1136	uint32_t const fRoBits = uCurReg & ~fRwMask; /* Preserve current read-only and reserved bits. */
1137	uint32_t const fRwBits = uReg & fRwMask; /* Merge newly written read/write bits. */
1138	uint32_t const fRw1cBits = uReg & fRw1cMask; /* Clear 1s written to RW1C bits. */
1139	uint32_t const uNewReg = (fRoBits \| fRwBits) & ~fRw1cBits;
1140
1141	/* Write new value to the 32-bit register. */
1142	dmarRegWriteRaw32(pThis, offReg, uNewReg);
1143	return uNewReg;
1144	}
1145
1146
1147	/**
1148	* Writes a 64-bit register as it would be when written by software.
1149	* This will preserve read-only bits, mask off reserved bits and clear RW1C bits.
1150	*
1151	* @returns The value that's actually written to the register.
1152	* @param pThis The shared DMAR device state.
1153	* @param offReg The MMIO offset of the register.
1154	* @param uReg The 64-bit value to write.
1155	* @param puPrev Where to store the register value prior to writing.
1156	*/
1157	static uint64_t dmarRegWrite64(PDMAR pThis, uint16_t offReg, uint64_t uReg, uint64_t *puPrev)
1158	{
1159	/* Read current value from the 64-bit register. */
1160	uint64_t uCurReg;
1161	uint64_t fRwMask;
1162	uint64_t fRw1cMask;
1163	dmarRegReadRaw64Ex(pThis, offReg, &uCurReg, &fRwMask, &fRw1cMask);
1164	*puPrev = uCurReg;
1165
1166	uint64_t const fRoBits = uCurReg & ~fRwMask; /* Preserve current read-only and reserved bits. */
1167	uint64_t const fRwBits = uReg & fRwMask; /* Merge newly written read/write bits. */
1168	uint64_t const fRw1cBits = uReg & fRw1cMask; /* Clear 1s written to RW1C bits. */
1169	uint64_t const uNewReg = (fRoBits \| fRwBits) & ~fRw1cBits;
1170
1171	/* Write new value to the 64-bit register. */
1172	dmarRegWriteRaw64(pThis, offReg, uNewReg);
1173	return uNewReg;
1174	}
1175
1176
1177	/**
1178	* Reads a 32-bit register as it would be when read by software.
1179	*
1180	* @returns The register value.
1181	* @param pThis The shared DMAR device state.
1182	* @param offReg The MMIO offset of the register.
1183	*/
1184	static uint32_t dmarRegRead32(PCDMAR pThis, uint16_t offReg)
1185	{
1186	return dmarRegReadRaw32(pThis, offReg);
1187	}
1188
1189
1190	/**
1191	* Reads a 64-bit register as it would be when read by software.
1192	*
1193	* @returns The register value.
1194	* @param pThis The shared DMAR device state.
1195	* @param offReg The MMIO offset of the register.
1196	*/
1197	static uint64_t dmarRegRead64(PCDMAR pThis, uint16_t offReg)
1198	{
1199	return dmarRegReadRaw64(pThis, offReg);
1200	}
1201
1202
1203	/**
1204	* Modifies a 32-bit register.
1205	*
1206	* @param pThis The shared DMAR device state.
1207	* @param offReg The MMIO offset of the register.
1208	* @param fAndMask The AND mask (applied first).
1209	* @param fOrMask The OR mask.
1210	* @remarks This does NOT apply RO or RW1C masks while modifying the
1211	* register.
1212	*/
1213	static void dmarRegChangeRaw32(PDMAR pThis, uint16_t offReg, uint32_t fAndMask, uint32_t fOrMask)
1214	{
1215	uint32_t uReg = dmarRegReadRaw32(pThis, offReg);
1216	uReg = (uReg & fAndMask) \| fOrMask;
1217	dmarRegWriteRaw32(pThis, offReg, uReg);
1218	}
1219
1220
1221	/**
1222	* Modifies a 64-bit register.
1223	*
1224	* @param pThis The shared DMAR device state.
1225	* @param offReg The MMIO offset of the register.
1226	* @param fAndMask The AND mask (applied first).
1227	* @param fOrMask The OR mask.
1228	* @remarks This does NOT apply RO or RW1C masks while modifying the
1229	* register.
1230	*/
1231	static void dmarRegChangeRaw64(PDMAR pThis, uint16_t offReg, uint64_t fAndMask, uint64_t fOrMask)
1232	{
1233	uint64_t uReg = dmarRegReadRaw64(pThis, offReg);
1234	uReg = (uReg & fAndMask) \| fOrMask;
1235	dmarRegWriteRaw64(pThis, offReg, uReg);
1236	}
1237
1238
1239	/**
1240	* Checks if the invalidation-queue is empty.
1241	*
1242	* Extended version which optionally returns the current queue head and tail
1243	* offsets.
1244	*
1245	* @returns @c true if empty, @c false otherwise.
1246	* @param pThis The shared DMAR device state.
1247	* @param poffQh Where to store the queue head offset. Optional, can be NULL.
1248	* @param poffQt Where to store the queue tail offset. Optional, can be NULL.
1249	*/
1250	static bool dmarInvQueueIsEmptyEx(PCDMAR pThis, uint32_t poffQh, uint32_t poffQt)
1251	{
1252	/* Read only the low-32 bits of the queue head and queue tail as high bits are all RsvdZ.*/
1253	uint32_t const uIqtReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IQT_REG);
1254	uint32_t const uIqhReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IQH_REG);
1255
1256	/* Don't bother masking QT, QH since other bits are RsvdZ. */
1257	Assert(!(uIqtReg & ~VTD_BF_IQT_REG_QT_MASK));
1258	Assert(!(uIqhReg & ~VTD_BF_IQH_REG_QH_MASK));
1259	if (poffQh)
1260	*poffQh = uIqhReg;
1261	if (poffQt)
1262	*poffQt = uIqtReg;
1263	return uIqtReg == uIqhReg;
1264	}
1265
1266
1267	/**
1268	* Checks if the invalidation-queue is empty.
1269	*
1270	* @returns @c true if empty, @c false otherwise.
1271	* @param pThis The shared DMAR device state.
1272	*/
1273	static bool dmarInvQueueIsEmpty(PCDMAR pThis)
1274	{
1275	return dmarInvQueueIsEmptyEx(pThis, NULL /* poffQh /, NULL / poffQt */);
1276	}
1277
1278
1279	/**
1280	* Checks if the invalidation-queue is capable of processing requests.
1281	*
1282	* @returns @c true if the invalidation-queue can process requests, @c false
1283	* otherwise.
1284	* @param pThis The shared DMAR device state.
1285	*/
1286	static bool dmarInvQueueCanProcessRequests(PCDMAR pThis)
1287	{
1288	/* Check if queued-invalidation is enabled. */
1289	uint32_t const uGstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GSTS_REG);
1290	if (uGstsReg & VTD_BF_GSTS_REG_QIES_MASK)
1291	{
1292	/* Check if there are no invalidation-queue or timeout errors. */
1293	uint32_t const uFstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FSTS_REG);
1294	if (!(uFstsReg & (VTD_BF_FSTS_REG_IQE_MASK \| VTD_BF_FSTS_REG_ITE_MASK)))
1295	return true;
1296	}
1297	return false;
1298	}
1299
1300
1301	/**
1302	* Wakes up the invalidation-queue thread if there are requests to be processed.
1303	*
1304	* @param pDevIns The IOMMU device instance.
1305	*/
1306	static void dmarInvQueueThreadWakeUpIfNeeded(PPDMDEVINS pDevIns)
1307	{
1308	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1309	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1310	LogFlowFunc(("\n"));
1311
1312	DMAR_ASSERT_LOCK_IS_OWNER(pDevIns, pThisCC);
1313
1314	if ( dmarInvQueueCanProcessRequests(pThis)
1315	&& !dmarInvQueueIsEmpty(pThis))
1316	{
1317	Log4Func(("Signaling the invalidation-queue thread\n"));
1318	PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEvtInvQueue);
1319	}
1320	}
1321
1322
1323	/**
1324	* Raises an event on behalf of the DMAR.
1325	*
1326	* These are events that are generated by the DMAR itself (like faults and
1327	* invalidation completion notifications).
1328	*
1329	* @param pDevIns The IOMMU device instance.
1330	* @param enmEventType The DMAR event type.
1331	*
1332	* @remarks The DMAR lock must be held while calling this function.
1333	*/
1334	static void dmarEventRaiseInterrupt(PPDMDEVINS pDevIns, DMAREVENTTYPE enmEventType)
1335	{
1336	uint16_t offCtlReg;
1337	uint32_t fIntrMaskedMask;
1338	uint32_t fIntrPendingMask;
1339	uint16_t offMsiAddrLoReg;
1340	uint16_t offMsiAddrHiReg;
1341	uint16_t offMsiDataReg;
1342	switch (enmEventType)
1343	{
1344	case DMAREVENTTYPE_INV_COMPLETE:
1345	{
1346	offCtlReg = VTD_MMIO_OFF_IECTL_REG;
1347	fIntrMaskedMask = VTD_BF_IECTL_REG_IM_MASK;
1348	fIntrPendingMask = VTD_BF_IECTL_REG_IP_MASK;
1349	offMsiAddrLoReg = VTD_MMIO_OFF_IEADDR_REG;
1350	offMsiAddrHiReg = VTD_MMIO_OFF_IEUADDR_REG;
1351	offMsiDataReg = VTD_MMIO_OFF_IEDATA_REG;
1352	break;
1353	}
1354
1355	case DMAREVENTTYPE_FAULT:
1356	{
1357	offCtlReg = VTD_MMIO_OFF_FECTL_REG;
1358	fIntrMaskedMask = VTD_BF_FECTL_REG_IM_MASK;
1359	fIntrPendingMask = VTD_BF_FECTL_REG_IP_MASK;
1360	offMsiAddrLoReg = VTD_MMIO_OFF_FEADDR_REG;
1361	offMsiAddrHiReg = VTD_MMIO_OFF_FEUADDR_REG;
1362	offMsiDataReg = VTD_MMIO_OFF_FEDATA_REG;
1363	break;
1364	}
1365
1366	default:
1367	{
1368	/* Shouldn't ever happen. */
1369	AssertMsgFailedReturnVoid(("DMAR event type %#x unknown!\n", enmEventType));
1370	}
1371	}
1372
1373	/* Check if software has masked the interrupt. */
1374	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1375	uint32_t uCtlReg = dmarRegReadRaw32(pThis, offCtlReg);
1376	if (!(uCtlReg & fIntrMaskedMask))
1377	{
1378	/*
1379	* Interrupt is unmasked, raise it.
1380	* Interrupts generated by the DMAR have trigger mode and level as 0.
1381	* See Intel spec. 5.1.6 "Remapping Hardware Event Interrupt Programming".
1382	*/
1383	MSIMSG Msi;
1384	Msi.Addr.au32[0] = dmarRegReadRaw32(pThis, offMsiAddrLoReg);
1385	Msi.Addr.au32[1] = (pThis->fExtCapReg & VTD_BF_ECAP_REG_EIM_MASK) ? dmarRegReadRaw32(pThis, offMsiAddrHiReg) : 0;
1386	Msi.Data.u32 = dmarRegReadRaw32(pThis, offMsiDataReg);
1387	Assert(Msi.Data.n.u1Level == 0);
1388	Assert(Msi.Data.n.u1TriggerMode == 0);
1389
1390	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1391	pThisCC->CTX_SUFF(pIommuHlp)->pfnSendMsi(pDevIns, &Msi, 0 /* uTagSrc */);
1392
1393	/* Clear interrupt pending bit. */
1394	uCtlReg &= ~fIntrPendingMask;
1395	dmarRegWriteRaw32(pThis, offCtlReg, uCtlReg);
1396	}
1397	else
1398	{
1399	/* Interrupt is masked, set the interrupt pending bit. */
1400	uCtlReg \|= fIntrPendingMask;
1401	dmarRegWriteRaw32(pThis, offCtlReg, uCtlReg);
1402	}
1403	}
1404
1405
1406	/**
1407	* Raises an interrupt in response to a fault event.
1408	*
1409	* @param pDevIns The IOMMU device instance.
1410	*
1411	* @remarks This assumes the caller has already set the required status bits in the
1412	* FSTS_REG (namely one or more of PPF, PFO, IQE, ICE or ITE bits).
1413	*/
1414	static void dmarFaultEventRaiseInterrupt(PPDMDEVINS pDevIns)
1415	{
1416	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1417	DMAR_ASSERT_LOCK_IS_OWNER(pDevIns, pThisCC);
1418
1419	#ifdef RT_STRICT
1420	{
1421	PCDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PCDMAR);
1422	uint32_t const uFstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FSTS_REG);
1423	uint32_t const fFaultMask = VTD_BF_FSTS_REG_PPF_MASK \| VTD_BF_FSTS_REG_PFO_MASK
1424	/* \| VTD_BF_FSTS_REG_APF_MASK \| VTD_BF_FSTS_REG_AFO_MASK / / AFL not supported */
1425	/* \| VTD_BF_FSTS_REG_ICE_MASK \| VTD_BF_FSTS_REG_ITE_MASK / / Device-TLBs not supported */
1426	\| VTD_BF_FSTS_REG_IQE_MASK;
1427	Assert(uFstsReg & fFaultMask);
1428	}
1429	#endif
1430	dmarEventRaiseInterrupt(pDevIns, DMAREVENTTYPE_FAULT);
1431	}
1432
1433
1434	#ifdef IN_RING3
1435	/**
1436	* Raises an interrupt in response to an invalidation (complete) event.
1437	*
1438	* @param pDevIns The IOMMU device instance.
1439	*/
1440	static void dmarR3InvEventRaiseInterrupt(PPDMDEVINS pDevIns)
1441	{
1442	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1443	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1444	DMAR_ASSERT_LOCK_IS_OWNER(pDevIns, pThisCC);
1445
1446	uint32_t const uIcsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_ICS_REG);
1447	if (!(uIcsReg & VTD_BF_ICS_REG_IWC_MASK))
1448	{
1449	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_ICS_REG, UINT32_MAX, VTD_BF_ICS_REG_IWC_MASK);
1450	dmarEventRaiseInterrupt(pDevIns, DMAREVENTTYPE_INV_COMPLETE);
1451	}
1452	}
1453	#endif /* IN_RING3 */
1454
1455
1456	/**
1457	* Checks if a primary fault can be recorded.
1458	*
1459	* @returns @c true if the fault can be recorded, @c false otherwise.
1460	* @param pDevIns The IOMMU device instance.
1461	* @param pThis The shared DMAR device state.
1462	*
1463	* @remarks Warning: This function has side-effects wrt the DMAR register state. Do
1464	* NOT call it unless there is a fault condition!
1465	*/
1466	static bool dmarPrimaryFaultCanRecord(PPDMDEVINS pDevIns, PDMAR pThis)
1467	{
1468	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1469	DMAR_ASSERT_LOCK_IS_OWNER(pDevIns, pThisCC);
1470
1471	uint32_t uFstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FSTS_REG);
1472	if (uFstsReg & VTD_BF_FSTS_REG_PFO_MASK)
1473	return false;
1474
1475	/*
1476	* If we add more FRCD registers, we'll have to loop through them here.
1477	* Since we support only one FRCD_REG, we don't support "compression of multiple faults",
1478	* nor do we need to increment FRI.
1479	*
1480	* See Intel VT-d spec. 7.2.1 "Primary Fault Logging".
1481	*/
1482	AssertCompile(DMAR_FRCD_REG_COUNT == 1);
1483	uint64_t const uFrcdRegHi = dmarRegReadRaw64(pThis, DMAR_MMIO_OFF_FRCD_HI_REG);
1484	if (uFrcdRegHi & VTD_BF_1_FRCD_REG_F_MASK)
1485	{
1486	uFstsReg \|= VTD_BF_FSTS_REG_PFO_MASK;
1487	dmarRegWriteRaw32(pThis, VTD_MMIO_OFF_FSTS_REG, uFstsReg);
1488	return false;
1489	}
1490
1491	return true;
1492	}
1493
1494
1495	/**
1496	* Records a primary fault.
1497	*
1498	* @param pDevIns The IOMMU device instance.
1499	* @param uFrcdHi The FRCD_HI_REG value for this fault.
1500	* @param uFrcdLo The FRCD_LO_REG value for this fault.
1501	*/
1502	static void dmarPrimaryFaultRecord(PPDMDEVINS pDevIns, uint64_t uFrcdHi, uint64_t uFrcdLo)
1503	{
1504	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1505	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1506
1507	DMAR_LOCK(pDevIns, pThisCC);
1508
1509	/* We don't support advance fault logging. */
1510	Assert(!(dmarRegRead32(pThis, VTD_MMIO_OFF_GSTS_REG) & VTD_BF_GSTS_REG_AFLS_MASK));
1511
1512	if (dmarPrimaryFaultCanRecord(pDevIns, pThis))
1513	{
1514	/* Update the fault recording registers with the fault information. */
1515	dmarRegWriteRaw64(pThis, DMAR_MMIO_OFF_FRCD_HI_REG, uFrcdHi);
1516	dmarRegWriteRaw64(pThis, DMAR_MMIO_OFF_FRCD_LO_REG, uFrcdLo);
1517
1518	/* Set the Pending Primary Fault (PPF) field in the status register. */
1519	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_FSTS_REG, UINT32_MAX, VTD_BF_FSTS_REG_PPF_MASK);
1520
1521	/* Raise interrupt if necessary. */
1522	dmarFaultEventRaiseInterrupt(pDevIns);
1523	}
1524
1525	DMAR_UNLOCK(pDevIns, pThisCC);
1526	}
1527
1528
1529	/**
1530	* Records an interrupt request fault.
1531	*
1532	* @param pDevIns The IOMMU device instance.
1533	* @param enmDiag The diagnostic reason.
1534	* @param idDevice The device ID (bus, device, function).
1535	* @param idxIntr The interrupt index.
1536	* @param pIrte The IRTE that caused this fault. Can be NULL if the fault is
1537	* not qualified.
1538	*/
1539	static void dmarIrFaultRecord(PPDMDEVINS pDevIns, DMARDIAG enmDiag, uint16_t idDevice, uint16_t idxIntr, PCVTD_IRTE_T pIrte)
1540	{
1541	/*
1542	* Update the diagnostic reason (even if software wants to supress faults).
1543	*/
1544	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1545	pThis->enmDiag = enmDiag;
1546
1547	/*
1548	* Figure out the fault reason to report to software from our diagnostic code.
1549	* The case labels below are sorted alphabetically for convenience.
1550	*/
1551	VTDIRFAULT enmIrFault;
1552	switch (enmDiag)
1553	{
1554	case kDmarDiag_Ir_Cfi_Blocked: enmIrFault = VTDIRFAULT_CFI_BLOCKED; break;
1555	case kDmarDiag_Ir_Rfi_Intr_Index_Invalid: enmIrFault = VTDIRFAULT_INTR_INDEX_INVALID; break;
1556	case kDmarDiag_Ir_Rfi_Irte_Mode_Invalid: enmIrFault = VTDIRFAULT_IRTE_PRESENT_RSVD; break;
1557	case kDmarDiag_Ir_Rfi_Irte_Not_Present: enmIrFault = VTDIRFAULT_IRTE_NOT_PRESENT; break;
1558	case kDmarDiag_Ir_Rfi_Irte_Read_Failed: enmIrFault = VTDIRFAULT_IRTE_READ_FAILED; break;
1559	case kDmarDiag_Ir_Rfi_Irte_Rsvd:
1560	case kDmarDiag_Ir_Rfi_Irte_Svt_Bus:
1561	case kDmarDiag_Ir_Rfi_Irte_Svt_Masked:
1562	case kDmarDiag_Ir_Rfi_Irte_Svt_Rsvd: enmIrFault = VTDIRFAULT_IRTE_PRESENT_RSVD; break;
1563	case kDmarDiag_Ir_Rfi_Rsvd: enmIrFault = VTDIRFAULT_REMAPPABLE_INTR_RSVD; break;
1564
1565	/* Shouldn't ever happen. */
1566	default:
1567	{
1568	AssertLogRelMsgFailedReturnVoid(("%s: Invalid interrupt remapping fault diagnostic code %#x\n", DMAR_LOG_PFX,
1569	enmDiag));
1570	}
1571	}
1572
1573	/*
1574	* Qualified faults are those that can be suppressed by software using the FPD bit
1575	* in the interrupt-remapping table entry.
1576	*/
1577	bool fFpd;
1578	bool const fQualifiedFault = vtdIrFaultIsQualified(enmIrFault);
1579	if (fQualifiedFault)
1580	{
1581	AssertReturnVoid(pIrte);
1582	fFpd = RT_BOOL(pIrte->au64[0] & VTD_BF_0_IRTE_FPD_MASK);
1583	}
1584	else
1585	fFpd = false;
1586
1587	if (!fFpd)
1588	{
1589	/* Construct and record the error. */
1590	uint64_t const uFrcdHi = RT_BF_MAKE(VTD_BF_1_FRCD_REG_SID, idDevice)
1591	\| RT_BF_MAKE(VTD_BF_1_FRCD_REG_FR, enmIrFault)
1592	\| RT_BF_MAKE(VTD_BF_1_FRCD_REG_F, 1);
1593	uint64_t const uFrcdLo = (uint64_t)idxIntr << 48;
1594	dmarPrimaryFaultRecord(pDevIns, uFrcdHi, uFrcdLo);
1595	}
1596	}
1597
1598
1599	/**
1600	* Records an address translation fault.
1601	*
1602	* @param pDevIns The IOMMU device instance.
1603	* @param enmDiag The diagnostic reason.
1604	* @param pMemReqIn The DMA memory request input.
1605	* @param pMemReqAux The DMA memory request auxiliary info.
1606	*/
1607	static void dmarAtFaultRecord(PPDMDEVINS pDevIns, DMARDIAG enmDiag, PCDMARMEMREQIN pMemReqIn, PCDMARMEMREQAUX pMemReqAux)
1608	{
1609	/*
1610	* Update the diagnostic reason (even if software wants to supress faults).
1611	*/
1612	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1613	pThis->enmDiag = enmDiag;
1614
1615	/*
1616	* Qualified faults are those that can be suppressed by software using the FPD bit
1617	* in the context entry, scalable-mode context entry etc.
1618	*/
1619	if (!pMemReqAux->fFpd)
1620	{
1621	/*
1622	* Figure out the fault reason to report to software from our diagnostic code.
1623	* The case labels below are sorted alphabetically for convenience.
1624	*/
1625	VTDATFAULT enmAtFault;
1626	bool const fLm = pMemReqAux->fTtm == VTD_TTM_LEGACY_MODE;
1627	switch (enmDiag)
1628	{
1629	/* LM (Legacy Mode) faults. */
1630	case kDmarDiag_At_Lm_CtxEntry_Not_Present: enmAtFault = VTDATFAULT_LCT_2; break;
1631	case kDmarDiag_At_Lm_CtxEntry_Read_Failed: enmAtFault = VTDATFAULT_LCT_1; break;
1632	case kDmarDiag_At_Lm_CtxEntry_Rsvd: enmAtFault = VTDATFAULT_LCT_3; break;
1633	case kDmarDiag_At_Lm_Pt_At_Block: enmAtFault = VTDATFAULT_LCT_5; break;
1634	case kDmarDiag_At_Lm_Pt_Aw_Invalid: enmAtFault = VTDATFAULT_LGN_1_3; break;
1635	case kDmarDiag_At_Lm_RootEntry_Not_Present: enmAtFault = VTDATFAULT_LRT_2; break;
1636	case kDmarDiag_At_Lm_RootEntry_Read_Failed: enmAtFault = VTDATFAULT_LRT_1; break;
1637	case kDmarDiag_At_Lm_RootEntry_Rsvd: enmAtFault = VTDATFAULT_LRT_3; break;
1638	case kDmarDiag_At_Lm_Tt_Invalid: enmAtFault = VTDATFAULT_LCT_4_2; break;
1639	case kDmarDiag_At_Lm_Ut_At_Block: enmAtFault = VTDATFAULT_LCT_5; break;
1640	case kDmarDiag_At_Lm_Ut_Aw_Invalid: enmAtFault = VTDATFAULT_LCT_4_1; break;
1641
1642	/* RTA (Root Table Address) faults. */
1643	case kDmarDiag_At_Rta_Adms_Not_Supported: enmAtFault = VTDATFAULT_RTA_1_1; break;
1644	case kDmarDiag_At_Rta_Rsvd: enmAtFault = VTDATFAULT_RTA_1_2; break;
1645	case kDmarDiag_At_Rta_Smts_Not_Supported: enmAtFault = VTDATFAULT_RTA_1_3; break;
1646
1647	/* XM (Legacy mode or Scalable Mode) faults. */
1648	case kDmarDiag_At_Xm_AddrIn_Invalid: enmAtFault = fLm ? VTDATFAULT_LGN_1_1 : VTDATFAULT_SGN_5; break;
1649	case kDmarDiag_At_Xm_AddrOut_Invalid: enmAtFault = fLm ? VTDATFAULT_LGN_4 : VTDATFAULT_SGN_8; break;
1650	case kDmarDiag_At_Xm_Perm_Read_Denied: enmAtFault = fLm ? VTDATFAULT_LGN_3 : VTDATFAULT_SGN_7; break;
1651	case kDmarDiag_At_Xm_Perm_Write_Denied: enmAtFault = fLm ? VTDATFAULT_LGN_2 : VTDATFAULT_SGN_6; break;
1652	case kDmarDiag_At_Xm_Pte_Not_Present:
1653	case kDmarDiag_At_Xm_Pte_Rsvd: enmAtFault = fLm ? VTDATFAULT_LSL_2 : VTDATFAULT_SSL_2; break;
1654	case kDmarDiag_At_Xm_Pte_Sllps_Invalid: enmAtFault = fLm ? VTDATFAULT_LSL_2 : VTDATFAULT_SSL_3; break;
1655	case kDmarDiag_At_Xm_Read_Pte_Failed: enmAtFault = fLm ? VTDATFAULT_LSL_1 : VTDATFAULT_SSL_1; break;
1656	case kDmarDiag_At_Xm_Slpptr_Read_Failed: enmAtFault = fLm ? VTDATFAULT_LCT_4_3 : VTDATFAULT_SSL_4; break;
1657
1658	/* Shouldn't ever happen. */
1659	default:
1660	{
1661	AssertLogRelMsgFailedReturnVoid(("%s: Invalid address translation fault diagnostic code %#x\n",
1662	DMAR_LOG_PFX, enmDiag));
1663	}
1664	}
1665
1666	/* Construct and record the error. */
1667	uint16_t const idDevice = pMemReqIn->idDevice;
1668	uint8_t const fType1 = pMemReqIn->enmReqType & RT_BIT(1);
1669	uint8_t const fType2 = pMemReqIn->enmReqType & RT_BIT(0);
1670	uint8_t const fExec = pMemReqIn->AddrRange.fPerm & DMAR_PERM_EXE;
1671	uint8_t const fPriv = pMemReqIn->AddrRange.fPerm & DMAR_PERM_PRIV;
1672	bool const fHasPasid = PCIPASID_IS_VALID(pMemReqIn->Pasid);
1673	uint32_t const uPasid = PCIPASID_VAL(pMemReqIn->Pasid);
1674	PCIADDRTYPE const enmAt = pMemReqIn->enmAddrType;
1675
1676	uint64_t const uFrcdHi = RT_BF_MAKE(VTD_BF_1_FRCD_REG_SID, idDevice)
1677	\| RT_BF_MAKE(VTD_BF_1_FRCD_REG_T2, fType2)
1678	\| RT_BF_MAKE(VTD_BF_1_FRCD_REG_PP, fHasPasid)
1679	\| RT_BF_MAKE(VTD_BF_1_FRCD_REG_EXE, fExec)
1680	\| RT_BF_MAKE(VTD_BF_1_FRCD_REG_PRIV, fPriv)
1681	\| RT_BF_MAKE(VTD_BF_1_FRCD_REG_FR, enmAtFault)
1682	\| RT_BF_MAKE(VTD_BF_1_FRCD_REG_PV, uPasid)
1683	\| RT_BF_MAKE(VTD_BF_1_FRCD_REG_AT, enmAt)
1684	\| RT_BF_MAKE(VTD_BF_1_FRCD_REG_T1, fType1)
1685	\| RT_BF_MAKE(VTD_BF_1_FRCD_REG_F, 1);
1686	uint64_t const uFrcdLo = pMemReqIn->AddrRange.uAddr & X86_PAGE_BASE_MASK;
1687	dmarPrimaryFaultRecord(pDevIns, uFrcdHi, uFrcdLo);
1688	}
1689	}
1690
1691
1692	/**
1693	* Records an IQE fault.
1694	*
1695	* @param pDevIns The IOMMU device instance.
1696	* @param enmIqei The IQE information.
1697	* @param enmDiag The diagnostic reason.
1698	*/
1699	static void dmarIqeFaultRecord(PPDMDEVINS pDevIns, DMARDIAG enmDiag, VTDIQEI enmIqei)
1700	{
1701	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1702	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1703
1704	DMAR_LOCK(pDevIns, pThisCC);
1705
1706	/* Update the diagnostic reason. */
1707	pThis->enmDiag = enmDiag;
1708
1709	/* Set the error bit. */
1710	uint32_t const fIqe = RT_BF_MAKE(VTD_BF_FSTS_REG_IQE, 1);
1711	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_FSTS_REG, UINT32_MAX, fIqe);
1712
1713	/* Set the error information. */
1714	uint64_t const fIqei = RT_BF_MAKE(VTD_BF_IQERCD_REG_IQEI, enmIqei);
1715	dmarRegChangeRaw64(pThis, VTD_MMIO_OFF_IQERCD_REG, UINT64_MAX, fIqei);
1716
1717	dmarFaultEventRaiseInterrupt(pDevIns);
1718
1719	DMAR_UNLOCK(pDevIns, pThisCC);
1720	}
1721
1722
1723	/**
1724	* Handles writes to GCMD_REG.
1725	*
1726	* @returns Strict VBox status code.
1727	* @param pDevIns The IOMMU device instance.
1728	* @param uGcmdReg The value written to GCMD_REG.
1729	*/
1730	static VBOXSTRICTRC dmarGcmdRegWrite(PPDMDEVINS pDevIns, uint32_t uGcmdReg)
1731	{
1732	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1733	uint32_t const uGstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GSTS_REG);
1734	uint32_t const fChanged = uGstsReg ^ uGcmdReg;
1735	uint64_t const fExtCapReg = pThis->fExtCapReg;
1736
1737	/* Queued-invalidation. */
1738	if ( (fExtCapReg & VTD_BF_ECAP_REG_QI_MASK)
1739	&& (fChanged & VTD_BF_GCMD_REG_QIE_MASK))
1740	{
1741	if (uGcmdReg & VTD_BF_GCMD_REG_QIE_MASK)
1742	{
1743	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, UINT32_MAX, VTD_BF_GSTS_REG_QIES_MASK);
1744	dmarInvQueueThreadWakeUpIfNeeded(pDevIns);
1745	}
1746	else
1747	{
1748	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, ~VTD_BF_GSTS_REG_QIES_MASK, 0 /* fOrMask */);
1749	dmarRegWriteRaw32(pThis, VTD_MMIO_OFF_IQH_REG, 0);
1750	}
1751	}
1752
1753	if (fExtCapReg & VTD_BF_ECAP_REG_IR_MASK)
1754	{
1755	/* Set Interrupt Remapping Table Pointer (SIRTP). */
1756	if (uGcmdReg & VTD_BF_GCMD_REG_SIRTP_MASK)
1757	{
1758	/** @todo Perform global invalidation of all interrupt-entry cache when ESIRTPS is
1759	* supported. */
1760	pThis->uIrtaReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IRTA_REG);
1761	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, UINT32_MAX, VTD_BF_GSTS_REG_IRTPS_MASK);
1762	}
1763
1764	/* Interrupt remapping. */
1765	if (fChanged & VTD_BF_GCMD_REG_IRE_MASK)
1766	{
1767	if (uGcmdReg & VTD_BF_GCMD_REG_IRE_MASK)
1768	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, UINT32_MAX, VTD_BF_GSTS_REG_IRES_MASK);
1769	else
1770	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, ~VTD_BF_GSTS_REG_IRES_MASK, 0 /* fOrMask */);
1771	}
1772
1773	/* Compatibility format interrupts. */
1774	if (fChanged & VTD_BF_GCMD_REG_CFI_MASK)
1775	{
1776	if (uGcmdReg & VTD_BF_GCMD_REG_CFI_MASK)
1777	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, UINT32_MAX, VTD_BF_GSTS_REG_CFIS_MASK);
1778	else
1779	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, ~VTD_BF_GSTS_REG_CFIS_MASK, 0 /* fOrMask */);
1780	}
1781	}
1782
1783	/* Set Root Table Pointer (SRTP). */
1784	if (uGcmdReg & VTD_BF_GCMD_REG_SRTP_MASK)
1785	{
1786	/** @todo Perform global invalidation of all remapping translation caches when
1787	* ESRTPS is supported. */
1788	pThis->uRtaddrReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_RTADDR_REG);
1789	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, UINT32_MAX, VTD_BF_GSTS_REG_RTPS_MASK);
1790	}
1791
1792	/* Translation (DMA remapping). */
1793	if (fChanged & VTD_BF_GCMD_REG_TE_MASK)
1794	{
1795	if (uGcmdReg & VTD_BF_GCMD_REG_TE_MASK)
1796	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, UINT32_MAX, VTD_BF_GSTS_REG_TES_MASK);
1797	else
1798	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, ~VTD_BF_GSTS_REG_TES_MASK, 0 /* fOrMask */);
1799	}
1800
1801	return VINF_SUCCESS;
1802	}
1803
1804
1805	/**
1806	* Handles writes to CCMD_REG.
1807	*
1808	* @returns Strict VBox status code.
1809	* @param pDevIns The IOMMU device instance.
1810	* @param offReg The MMIO register offset.
1811	* @param cbReg The size of the MMIO access (in bytes).
1812	* @param uCcmdReg The value written to CCMD_REG.
1813	*/
1814	static VBOXSTRICTRC dmarCcmdRegWrite(PPDMDEVINS pDevIns, uint16_t offReg, uint8_t cbReg, uint64_t uCcmdReg)
1815	{
1816	/* At present, we only care about responding to high 32-bits writes, low 32-bits are data. */
1817	if (offReg + cbReg > VTD_MMIO_OFF_CCMD_REG + 4)
1818	{
1819	/* Check if we need to invalidate the context-context. */
1820	bool const fIcc = RT_BF_GET(uCcmdReg, VTD_BF_CCMD_REG_ICC);
1821	if (fIcc)
1822	{
1823	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1824	uint8_t const uMajorVersion = RT_BF_GET(pThis->uVerReg, VTD_BF_VER_REG_MAX);
1825	if (uMajorVersion < 6)
1826	{
1827	/* Register-based invalidation can only be used when queued-invalidations are not enabled. */
1828	uint32_t const uGstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GSTS_REG);
1829	if (!(uGstsReg & VTD_BF_GSTS_REG_QIES_MASK))
1830	{
1831	/* Verify table translation mode is legacy. */
1832	uint8_t const fTtm = RT_BF_GET(pThis->uRtaddrReg, VTD_BF_RTADDR_REG_TTM);
1833	if (fTtm == VTD_TTM_LEGACY_MODE)
1834	{
1835	/** @todo Invalidate. */
1836	return VINF_SUCCESS;
1837	}
1838	pThis->enmDiag = kDmarDiag_CcmdReg_Ttm_Invalid;
1839	}
1840	else
1841	pThis->enmDiag = kDmarDiag_CcmdReg_Qi_Enabled;
1842	}
1843	else
1844	pThis->enmDiag = kDmarDiag_CcmdReg_Not_Supported;
1845	dmarRegChangeRaw64(pThis, VTD_MMIO_OFF_GSTS_REG, ~VTD_BF_CCMD_REG_CAIG_MASK, 0 /* fOrMask */);
1846	}
1847	}
1848	return VINF_SUCCESS;
1849	}
1850
1851
1852	/**
1853	* Handles writes to FECTL_REG.
1854	*
1855	* @returns Strict VBox status code.
1856	* @param pDevIns The IOMMU device instance.
1857	* @param uFectlReg The value written to FECTL_REG.
1858	*/
1859	static VBOXSTRICTRC dmarFectlRegWrite(PPDMDEVINS pDevIns, uint32_t uFectlReg)
1860	{
1861	/*
1862	* If software unmasks the interrupt when the interrupt is pending, we must raise
1863	* the interrupt now (which will consequently clear the interrupt pending (IP) bit).
1864	*/
1865	if ( (uFectlReg & VTD_BF_FECTL_REG_IP_MASK)
1866	&& ~(uFectlReg & VTD_BF_FECTL_REG_IM_MASK))
1867	dmarEventRaiseInterrupt(pDevIns, DMAREVENTTYPE_FAULT);
1868	return VINF_SUCCESS;
1869	}
1870
1871
1872	/**
1873	* Handles writes to FSTS_REG.
1874	*
1875	* @returns Strict VBox status code.
1876	* @param pDevIns The IOMMU device instance.
1877	* @param uFstsReg The value written to FSTS_REG.
1878	* @param uPrev The value in FSTS_REG prior to writing it.
1879	*/
1880	static VBOXSTRICTRC dmarFstsRegWrite(PPDMDEVINS pDevIns, uint32_t uFstsReg, uint32_t uPrev)
1881	{
1882	/*
1883	* If software clears other status bits in FSTS_REG (pertaining to primary fault logging),
1884	* the interrupt pending (IP) bit must be cleared.
1885	*
1886	* See Intel VT-d spec. 10.4.10 "Fault Event Control Register".
1887	*/
1888	uint32_t const fChanged = uPrev ^ uFstsReg;
1889	if (fChanged & ( VTD_BF_FSTS_REG_ICE_MASK \| VTD_BF_FSTS_REG_ITE_MASK
1890	\| VTD_BF_FSTS_REG_IQE_MASK \| VTD_BF_FSTS_REG_PFO_MASK))
1891	{
1892	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1893	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_FECTL_REG, ~VTD_BF_FECTL_REG_IP_MASK, 0 /* fOrMask */);
1894	}
1895	return VINF_SUCCESS;
1896	}
1897
1898
1899	/**
1900	* Handles writes to IQT_REG.
1901	*
1902	* @returns Strict VBox status code.
1903	* @param pDevIns The IOMMU device instance.
1904	* @param offReg The MMIO register offset.
1905	* @param uIqtReg The value written to IQT_REG.
1906	*/
1907	static VBOXSTRICTRC dmarIqtRegWrite(PPDMDEVINS pDevIns, uint16_t offReg, uint64_t uIqtReg)
1908	{
1909	/* We only care about the low 32-bits, high 32-bits are reserved. */
1910	Assert(offReg == VTD_MMIO_OFF_IQT_REG);
1911	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1912
1913	/* Paranoia. */
1914	Assert(!(uIqtReg & ~VTD_BF_IQT_REG_QT_MASK));
1915
1916	uint32_t const offQt = uIqtReg;
1917	uint64_t const uIqaReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IQA_REG);
1918	uint8_t const fDw = RT_BF_GET(uIqaReg, VTD_BF_IQA_REG_DW);
1919
1920	/* If the descriptor width is 256-bits, the queue tail offset must be aligned accordingly. */
1921	if ( fDw != VTD_IQA_REG_DW_256_BIT
1922	\|\| !(offQt & RT_BIT(4)))
1923	dmarInvQueueThreadWakeUpIfNeeded(pDevIns);
1924	else
1925	{
1926	/* Hardware treats bit 4 as RsvdZ in this situation, so clear it. */
1927	dmarRegChangeRaw32(pThis, offReg, ~RT_BIT(4), 0 /* fOrMask */);
1928	dmarIqeFaultRecord(pDevIns, kDmarDiag_IqtReg_Qt_Not_Aligned, VTDIQEI_QUEUE_TAIL_MISALIGNED);
1929	}
1930	return VINF_SUCCESS;
1931	}
1932
1933
1934	/**
1935	* Handles writes to IQA_REG.
1936	*
1937	* @returns Strict VBox status code.
1938	* @param pDevIns The IOMMU device instance.
1939	* @param offReg The MMIO register offset.
1940	* @param uIqaReg The value written to IQA_REG.
1941	*/
1942	static VBOXSTRICTRC dmarIqaRegWrite(PPDMDEVINS pDevIns, uint16_t offReg, uint64_t uIqaReg)
1943	{
1944	/* At present, we only care about the low 32-bits, high 32-bits are data. */
1945	Assert(offReg == VTD_MMIO_OFF_IQA_REG); NOREF(offReg);
1946
1947	/** @todo What happens if IQA_REG is written when dmarInvQueueCanProcessRequests
1948	* returns true? The Intel VT-d spec. doesn't state anywhere that it
1949	* cannot happen or that it's ignored when it does happen. */
1950
1951	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1952	uint8_t const fDw = RT_BF_GET(uIqaReg, VTD_BF_IQA_REG_DW);
1953	if (fDw == VTD_IQA_REG_DW_256_BIT)
1954	{
1955	bool const fSupports256BitDw = (pThis->fExtCapReg & (VTD_BF_ECAP_REG_SMTS_MASK \| VTD_BF_ECAP_REG_ADMS_MASK));
1956	if (fSupports256BitDw)
1957	{ /* likely */ }
1958	else
1959	dmarIqeFaultRecord(pDevIns, kDmarDiag_IqaReg_Dw_256_Invalid, VTDIQEI_INVALID_DESCRIPTOR_WIDTH);
1960	}
1961	/* else: 128-bit descriptor width is validated lazily, see explanation in dmarR3InvQueueProcessRequests. */
1962
1963	return VINF_SUCCESS;
1964	}
1965
1966
1967	/**
1968	* Handles writes to ICS_REG.
1969	*
1970	* @returns Strict VBox status code.
1971	* @param pDevIns The IOMMU device instance.
1972	* @param uIcsReg The value written to ICS_REG.
1973	*/
1974	static VBOXSTRICTRC dmarIcsRegWrite(PPDMDEVINS pDevIns, uint32_t uIcsReg)
1975	{
1976	/*
1977	* If the IP field is set when software services the interrupt condition,
1978	* (by clearing the IWC field), the IP field must be cleared.
1979	*/
1980	if (!(uIcsReg & VTD_BF_ICS_REG_IWC_MASK))
1981	{
1982	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1983	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_IECTL_REG, ~VTD_BF_IECTL_REG_IP_MASK, 0 /* fOrMask */);
1984	}
1985	return VINF_SUCCESS;
1986	}
1987
1988
1989	/**
1990	* Handles writes to IECTL_REG.
1991	*
1992	* @returns Strict VBox status code.
1993	* @param pDevIns The IOMMU device instance.
1994	* @param uIectlReg The value written to IECTL_REG.
1995	*/
1996	static VBOXSTRICTRC dmarIectlRegWrite(PPDMDEVINS pDevIns, uint32_t uIectlReg)
1997	{
1998	/*
1999	* If software unmasks the interrupt when the interrupt is pending, we must raise
2000	* the interrupt now (which will consequently clear the interrupt pending (IP) bit).
2001	*/
2002	if ( (uIectlReg & VTD_BF_IECTL_REG_IP_MASK)
2003	&& ~(uIectlReg & VTD_BF_IECTL_REG_IM_MASK))
2004	dmarEventRaiseInterrupt(pDevIns, DMAREVENTTYPE_INV_COMPLETE);
2005	return VINF_SUCCESS;
2006	}
2007
2008
2009	/**
2010	* Handles writes to FRCD_REG (High 64-bits).
2011	*
2012	* @returns Strict VBox status code.
2013	* @param pDevIns The IOMMU device instance.
2014	* @param offReg The MMIO register offset.
2015	* @param cbReg The size of the MMIO access (in bytes).
2016	* @param uFrcdHiReg The value written to FRCD_REG.
2017	* @param uPrev The value in FRCD_REG prior to writing it.
2018	*/
2019	static VBOXSTRICTRC dmarFrcdHiRegWrite(PPDMDEVINS pDevIns, uint16_t offReg, uint8_t cbReg, uint64_t uFrcdHiReg, uint64_t uPrev)
2020	{
2021	/* We only care about responding to high 32-bits, low 32-bits are read-only. */
2022	if (offReg + cbReg > DMAR_MMIO_OFF_FRCD_HI_REG + 4)
2023	{
2024	/*
2025	* If software cleared the RW1C F (fault) bit in all FRCD_REGs, hardware clears the
2026	* Primary Pending Fault (PPF) and the interrupt pending (IP) bits. Our implementation
2027	* has only 1 FRCD register.
2028	*
2029	* See Intel VT-d spec. 10.4.10 "Fault Event Control Register".
2030	*/
2031	AssertCompile(DMAR_FRCD_REG_COUNT == 1);
2032	uint64_t const fChanged = uPrev ^ uFrcdHiReg;
2033	if (fChanged & VTD_BF_1_FRCD_REG_F_MASK)
2034	{
2035	Assert(!(uFrcdHiReg & VTD_BF_1_FRCD_REG_F_MASK)); /* Software should only ever be able to clear this bit. */
2036	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
2037	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_FSTS_REG, ~VTD_BF_FSTS_REG_PPF_MASK, 0 /* fOrMask */);
2038	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_FECTL_REG, ~VTD_BF_FECTL_REG_IP_MASK, 0 /* fOrMask */);
2039	}
2040	}
2041	return VINF_SUCCESS;
2042	}
2043
2044
2045	/**
2046	* Performs a PCI target abort for a DMA remapping (DR) operation.
2047	*
2048	* @param pDevIns The IOMMU device instance.
2049	*/
2050	static void dmarDrTargetAbort(PPDMDEVINS pDevIns)
2051	{
2052	/** @todo r=ramshankar: I don't know for sure if a PCI target abort is caused or not
2053	* as the Intel VT-d spec. is vague. Wording seems to suggest it does, but
2054	* who knows. */
2055	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
2056	uint16_t const u16Status = PDMPciDevGetStatus(pPciDev) \| VBOX_PCI_STATUS_SIG_TARGET_ABORT;
2057	PDMPciDevSetStatus(pPciDev, u16Status);
2058	}
2059
2060
2061	/**
2062	* Checks whether the address width (AW) is supported by our hardware
2063	* implementation for legacy mode address translation.
2064	*
2065	* @returns @c true if it's supported, @c false otherwise.
2066	* @param pThis The shared DMAR device state.
2067	* @param pCtxEntry The context entry.
2068	* @param pcPagingLevel Where to store the paging level. Optional, can be NULL.
2069	*/
2070	static bool dmarDrLegacyModeIsAwValid(PCDMAR pThis, PCVTD_CONTEXT_ENTRY_T pCtxEntry, uint8_t *pcPagingLevel)
2071	{
2072	uint8_t const fTt = RT_BF_GET(pCtxEntry->au64[0], VTD_BF_0_CONTEXT_ENTRY_TT);
2073	uint8_t const fAw = RT_BF_GET(pCtxEntry->au64[1], VTD_BF_1_CONTEXT_ENTRY_AW);
2074	uint8_t const fAwMask = RT_BIT(fAw);
2075	uint8_t const fSagaw = RT_BF_GET(pThis->fCapReg, VTD_BF_CAP_REG_SAGAW);
2076	Assert(!(fSagaw & ~(RT_BIT(1) \| RT_BIT(2) \| RT_BIT(3))));
2077
2078	uint8_t const cPagingLevel = fAw + 2;
2079	if (pcPagingLevel)
2080	*pcPagingLevel = cPagingLevel;
2081
2082	/* With pass-through, the address width must be the largest AGAW supported by hardware. */
2083	if (fTt == VTD_TT_UNTRANSLATED_PT)
2084	{
2085	Assert(pThis->cMaxPagingLevel >= 3 && pThis->cMaxPagingLevel <= 5); /* Paranoia. */
2086	return cPagingLevel == pThis->cMaxPagingLevel;
2087	}
2088
2089	/* The address width must be any of the ones supported by hardware. */
2090	if (fAw < 4)
2091	return (fSagaw & fAwMask) != 0;
2092
2093	return false;
2094	}
2095
2096
2097	/**
2098	* Reads a root entry from guest memory.
2099	*
2100	* @returns VBox status code.
2101	* @param pDevIns The IOMMU device instance.
2102	* @param uRtaddrReg The current RTADDR_REG value.
2103	* @param idxRootEntry The index of the root entry to read.
2104	* @param pRootEntry Where to store the read root entry.
2105	*/
2106	static int dmarDrReadRootEntry(PPDMDEVINS pDevIns, uint64_t uRtaddrReg, uint8_t idxRootEntry, PVTD_ROOT_ENTRY_T pRootEntry)
2107	{
2108	size_t const cbRootEntry = sizeof(*pRootEntry);
2109	RTGCPHYS const GCPhysRootEntry = (uRtaddrReg & VTD_BF_RTADDR_REG_RTA_MASK) + (idxRootEntry * cbRootEntry);
2110	return PDMDevHlpPhysReadMeta(pDevIns, GCPhysRootEntry, pRootEntry, cbRootEntry);
2111	}
2112
2113
2114	/**
2115	* Reads a context entry from guest memory.
2116	*
2117	* @returns VBox status code.
2118	* @param pDevIns The IOMMU device instance.
2119	* @param GCPhysCtxTable The physical address of the context table.
2120	* @param idxCtxEntry The index of the context entry to read.
2121	* @param pCtxEntry Where to store the read context entry.
2122	*/
2123	static int dmarDrReadCtxEntry(PPDMDEVINS pDevIns, RTGCPHYS GCPhysCtxTable, uint8_t idxCtxEntry, PVTD_CONTEXT_ENTRY_T pCtxEntry)
2124	{
2125	/* We don't verify bits 63:HAW of GCPhysCtxTable is 0 since reading from such an address should fail anyway. */
2126	size_t const cbCtxEntry = sizeof(*pCtxEntry);
2127	RTGCPHYS const GCPhysCtxEntry = GCPhysCtxTable + (idxCtxEntry * cbCtxEntry);
2128	return PDMDevHlpPhysReadMeta(pDevIns, GCPhysCtxEntry, pCtxEntry, cbCtxEntry);
2129	}
2130
2131
2132	/**
2133	* Validates and updates the output I/O page of a translation.
2134	*
2135	* @returns VBox status code.
2136	* @param pDevIns The IOMMU device instance.
2137	* @param GCPhysBase The output address of the translation.
2138	* @param cShift The page shift of the translated address.
2139	* @param fPerm The permissions granted for the translated region.
2140	* @param pMemReqIn The DMA memory request input.
2141	* @param pMemReqAux The DMA memory request auxiliary info.
2142	* @param pIoPageOut Where to store the output of the translation.
2143	*/
2144	static int dmarDrUpdateIoPageOut(PPDMDEVINS pDevIns, RTGCPHYS GCPhysBase, uint8_t cShift, uint8_t fPerm,
2145	PCDMARMEMREQIN pMemReqIn, PCDMARMEMREQAUX pMemReqAux, PDMARIOPAGE pIoPageOut)
2146	{
2147	Assert(!(GCPhysBase & X86_PAGE_4K_OFFSET_MASK));
2148
2149	/* Ensure the output address is not in the interrupt address range. */
2150	if (GCPhysBase - VBOX_MSI_ADDR_BASE >= VBOX_MSI_ADDR_SIZE)
2151	{
2152	pIoPageOut->GCPhysBase = GCPhysBase;
2153	pIoPageOut->cShift = cShift;
2154	pIoPageOut->fPerm = fPerm;
2155	return VINF_SUCCESS;
2156	}
2157
2158	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Xm_AddrOut_Invalid, pMemReqIn, pMemReqAux);
2159	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2160	}
2161
2162
2163	/**
2164	* Performs second level translation by walking the I/O page tables.
2165	*
2166	* This is a DMA address-lookup callback function which performs the translation
2167	* (and access control) as part of the lookup.
2168	*
2169	* @returns VBox status code.
2170	* @param pDevIns The IOMMU device instance.
2171	* @param pMemReqIn The DMA memory request input.
2172	* @param pMemReqAux The DMA memory request auxiliary info.
2173	* @param pIoPageOut Where to store the output of the translation.
2174	*/
2175	static DECLCALLBACK(int) dmarDrSecondLevelTranslate(PPDMDEVINS pDevIns, PCDMARMEMREQIN pMemReqIn, PCDMARMEMREQAUX pMemReqAux,
2176	PDMARIOPAGE pIoPageOut)
2177	{
2178	PCDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PCDMAR);
2179
2180	/* Sanity. */
2181	Assert(pIoPageOut);
2182	Assert(pMemReqIn->AddrRange.fPerm & (DMAR_PERM_READ \| DMAR_PERM_WRITE));
2183	Assert( pMemReqAux->fTtm == VTD_TTM_LEGACY_MODE
2184	\|\| pMemReqAux->fTtm == VTD_TTM_SCALABLE_MODE);
2185	Assert(!(pMemReqAux->GCPhysSlPt & X86_PAGE_4K_OFFSET_MASK));
2186
2187	/* Mask of reserved paging entry bits. */
2188	static uint64_t const s_auPtEntityInvMasks[] = { ~VTD_SL_PTE_VALID_MASK,
2189	~VTD_SL_PDE_VALID_MASK,
2190	~VTD_SL_PDPE_VALID_MASK,
2191	~VTD_SL_PML4E_VALID_MASK,
2192	~VTD_SL_PML5E_VALID_MASK };
2193
2194	/* Paranoia. */
2195	Assert(pMemReqAux->cPagingLevel >= 3 && pMemReqAux->cPagingLevel <= 5);
2196	AssertCompile(RT_ELEMENTS(s_auPtEntityInvMasks) == 5);
2197
2198	/* Second-level translations restricts input address to an implementation-specific MGAW. */
2199	uint64_t const uAddrIn = pMemReqIn->AddrRange.uAddr;
2200	if (!(uAddrIn & pThis->fMgawInvMask))
2201	{ /* likely */ }
2202	else
2203	{
2204	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Xm_AddrIn_Invalid, pMemReqIn, pMemReqAux);
2205	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2206	}
2207
2208	/*
2209	* Traverse the I/O page table starting with the SLPTPTR (second-level page table pointer).
2210	* Unlike AMD IOMMU paging, here there is no feature for "skipping" levels.
2211	*/
2212	uint64_t uPtEntity = pMemReqAux->GCPhysSlPt;
2213	for (int8_t idxLevel = pMemReqAux->cPagingLevel - 1; idxLevel >= 0; idxLevel--)
2214	{
2215	/*
2216	* Read the paging entry for the current level.
2217	*/
2218	uint8_t const cLevelShift = X86_PAGE_4K_SHIFT + (idxLevel * 9);
2219	{
2220	uint16_t const idxPte = (uAddrIn >> cLevelShift) & UINT64_C(0x1ff);
2221	uint16_t const offPte = idxPte << 3;
2222	RTGCPHYS const GCPhysPtEntity = (uPtEntity & X86_PAGE_4K_BASE_MASK) \| offPte;
2223	int const rc = PDMDevHlpPhysReadMeta(pDevIns, GCPhysPtEntity, &uPtEntity, sizeof(uPtEntity));
2224	if (RT_SUCCESS(rc))
2225	{ /* likely */ }
2226	else
2227	{
2228	if ((GCPhysPtEntity & X86_PAGE_BASE_MASK) == pMemReqAux->GCPhysSlPt)
2229	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Xm_Slpptr_Read_Failed, pMemReqIn, pMemReqAux);
2230	else
2231	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Xm_Read_Pte_Failed, pMemReqIn, pMemReqAux);
2232	break;
2233	}
2234	}
2235
2236	/*
2237	* Check I/O permissions.
2238	* This must be done prior to check reserved bits for properly reporting errors SSL.2 and SSL.3.
2239	* See Intel spec. 7.1.3 "Fault conditions and Remapping hardware behavior for various request".
2240	*/
2241	uint8_t const fReqPerm = pMemReqIn->AddrRange.fPerm & pThis->fPermValidMask;
2242	uint8_t const fPtPerm = uPtEntity & pThis->fPermValidMask;
2243	Assert(!(fReqPerm & DMAR_PERM_EXE)); /* No Execute-requests support yet. */
2244	Assert(!(pThis->fExtCapReg & VTD_BF_ECAP_REG_SLADS_MASK)); /* No Second-level access/dirty support. */
2245	if ((fPtPerm & fReqPerm) == fReqPerm)
2246	{ /* likely */ }
2247	else
2248	{
2249	if ((fPtPerm & (VTD_BF_SL_PTE_R_MASK \| VTD_BF_SL_PTE_W_MASK)) == 0)
2250	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Xm_Pte_Not_Present, pMemReqIn, pMemReqAux);
2251	else if ((pMemReqIn->AddrRange.fPerm & DMAR_PERM_READ) != (fPtPerm & VTD_BF_SL_PTE_R_MASK))
2252	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Xm_Perm_Read_Denied, pMemReqIn, pMemReqAux);
2253	else
2254	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Xm_Perm_Write_Denied, pMemReqIn, pMemReqAux);
2255	break;
2256	}
2257
2258	/*
2259	* Validate reserved bits of the current paging entry.
2260	*/
2261	if (!(uPtEntity & s_auPtEntityInvMasks[idxLevel]))
2262	{ /* likely */ }
2263	else
2264	{
2265	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Xm_Pte_Rsvd, pMemReqIn, pMemReqAux);
2266	break;
2267	}
2268
2269	/*
2270	* Check if this is a 1GB page or a 2MB page.
2271	*/
2272	AssertCompile(VTD_BF_SL_PDE_PS_MASK == VTD_BF_SL_PDPE_PS_MASK);
2273	uint8_t const fLargePage = RT_BF_GET(uPtEntity, VTD_BF_SL_PDE_PS);
2274	if (fLargePage && idxLevel > 0)
2275	{
2276	Assert(idxLevel == 1 \|\| idxLevel == 2); /* Is guaranteed by the reserved bits check above. */
2277	uint8_t const fSllpsMask = RT_BF_GET(pThis->fCapReg, VTD_BF_CAP_REG_SLLPS);
2278	if (fSllpsMask & RT_BIT(idxLevel - 1))
2279	{
2280	/*
2281	* We don't support MTS (asserted below), hence IPAT and EMT fields of the paging entity are ignored.
2282	* All other reserved bits are identical to the regular page-size paging entity which we've already
2283	* checked above.
2284	*/
2285	Assert(!(pThis->fExtCapReg & VTD_BF_ECAP_REG_MTS_MASK));
2286
2287	RTGCPHYS const GCPhysBase = uPtEntity & X86_GET_PAGE_BASE_MASK(cLevelShift);
2288	return dmarDrUpdateIoPageOut(pDevIns, GCPhysBase, cLevelShift, fPtPerm, pMemReqIn, pMemReqAux, pIoPageOut);
2289	}
2290
2291	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Xm_Pte_Sllps_Invalid, pMemReqIn, pMemReqAux);
2292	break;
2293	}
2294
2295	/*
2296	* If this is the final PTE, compute the translation address and we're done.
2297	*/
2298	if (idxLevel == 0)
2299	{
2300	RTGCPHYS const GCPhysBase = uPtEntity & X86_GET_PAGE_BASE_MASK(cLevelShift);
2301	return dmarDrUpdateIoPageOut(pDevIns, GCPhysBase, cLevelShift, fPtPerm, pMemReqIn, pMemReqAux, pIoPageOut);
2302	}
2303	}
2304
2305	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2306	}
2307
2308
2309	/**
2310	* Looks up the range of addresses for a DMA memory request remapping.
2311	*
2312	* @returns VBox status code.
2313	* @param pDevIns The IOMMU device instance.
2314	* @param pfnLookup The DMA address lookup function.
2315	* @param pMemReqRemap The DMA memory request remapping info.
2316	*/
2317	static int dmarDrMemRangeLookup(PPDMDEVINS pDevIns, PFNDMADDRLOOKUP pfnLookup, PDMARMEMREQREMAP pMemReqRemap)
2318	{
2319	AssertPtr(pfnLookup);
2320
2321	RTGCPHYS GCPhysAddrOut = NIL_RTGCPHYS;
2322	DMARMEMREQIN MemReqIn = pMemReqRemap->In;
2323	uint64_t const uAddrIn = MemReqIn.AddrRange.uAddr;
2324	size_t const cbAddrIn = MemReqIn.AddrRange.cb;
2325	uint64_t uAddrInBase = MemReqIn.AddrRange.uAddr & X86_PAGE_4K_BASE_MASK;
2326	uint64_t offAddrIn = MemReqIn.AddrRange.uAddr & X86_PAGE_4K_OFFSET_MASK;
2327	size_t cbRemaining = cbAddrIn;
2328	size_t const cbPage = X86_PAGE_4K_SIZE;
2329
2330	int rc;
2331	DMARIOPAGE IoPagePrev;
2332	RT_ZERO(IoPagePrev);
2333	for (;;)
2334	{
2335	/* Update the input memory request with the next address in our range that needs translation. */
2336	MemReqIn.AddrRange.uAddr = uAddrInBase;
2337	MemReqIn.AddrRange.cb = cbRemaining; /* Not currently accessed by pfnLookup, but keep things consistent. */
2338
2339	/* Lookup the physical page corresponding to the DMA virtual address. */
2340	DMARIOPAGE IoPage;
2341	rc = pfnLookup(pDevIns, &MemReqIn, &pMemReqRemap->Aux, &IoPage);
2342	if (RT_SUCCESS(rc))
2343	{
2344	/* Validate results of the translation. */
2345	Assert(IoPage.cShift >= X86_PAGE_4K_SHIFT && IoPage.cShift <= X86_PAGE_1G_SHIFT);
2346	Assert(!(IoPage.GCPhysBase & X86_GET_PAGE_OFFSET_MASK(IoPage.cShift)));
2347	Assert((IoPage.fPerm & MemReqIn.AddrRange.fPerm) == MemReqIn.AddrRange.fPerm);
2348
2349	/* Store the translated address and permissions before continuing to access more pages. */
2350	if (cbRemaining == cbAddrIn)
2351	{
2352	uint64_t const offAddrOut = uAddrIn & X86_GET_PAGE_OFFSET_MASK(IoPage.cShift);
2353	GCPhysAddrOut = IoPage.GCPhysBase \| offAddrOut;
2354	}
2355	/* Check if addresses translated so far result in a physically contiguous region. */
2356	/** @todo Ensure permissions are identical as well if we implementing IOTLB caching
2357	* that relies on it being so. */
2358	else if (IoPagePrev.GCPhysBase + cbPage == IoPage.GCPhysBase)
2359	{ /* likely */ }
2360	else
2361	{
2362	rc = VERR_OUT_OF_RANGE;
2363	break;
2364	}
2365
2366	/* Store the I/O page lookup from the first/previous access. */
2367	IoPagePrev = IoPage;
2368
2369	/* Check if we need to access more pages. */
2370	if (cbRemaining > cbPage - offAddrIn)
2371	{
2372	cbRemaining -= (cbPage - offAddrIn); /* Calculate how much more we need to access. */
2373	uAddrInBase += cbPage; /* Update address of the next access. */
2374	offAddrIn = 0; /* After the first page, remaining pages are accessed from offset 0. */
2375	}
2376	else
2377	{
2378	/* Caller (PDM) doesn't expect more data accessed than what was requested. */
2379	cbRemaining = 0;
2380	break;
2381	}
2382	}
2383	else
2384	break;
2385	}
2386
2387	pMemReqRemap->Out.AddrRange.uAddr = GCPhysAddrOut;
2388	pMemReqRemap->Out.AddrRange.cb = cbAddrIn - cbRemaining;
2389	pMemReqRemap->Out.AddrRange.fPerm = IoPagePrev.fPerm;
2390	return rc;
2391	}
2392
2393
2394	/**
2395	* Handles legacy mode DMA address remapping.
2396	*
2397	* @returns VBox status code.
2398	* @param pDevIns The IOMMU device instance.
2399	* @param uRtaddrReg The current RTADDR_REG value.
2400	* @param pMemReqRemap The DMA memory request remapping info.
2401	*/
2402	static int dmarDrLegacyModeRemapAddr(PPDMDEVINS pDevIns, uint64_t uRtaddrReg, PDMARMEMREQREMAP pMemReqRemap)
2403	{
2404	PCDMARMEMREQIN pMemReqIn = &pMemReqRemap->In;
2405	PDMARMEMREQAUX pMemReqAux = &pMemReqRemap->Aux;
2406	PDMARMEMREQOUT pMemReqOut = &pMemReqRemap->Out;
2407	Assert(pMemReqAux->fTtm == VTD_TTM_LEGACY_MODE); /* Paranoia. */
2408
2409	/* Read the root-entry from guest memory. */
2410	uint8_t const idxRootEntry = RT_HI_U8(pMemReqIn->idDevice);
2411	VTD_ROOT_ENTRY_T RootEntry;
2412	int rc = dmarDrReadRootEntry(pDevIns, uRtaddrReg, idxRootEntry, &RootEntry);
2413	if (RT_SUCCESS(rc))
2414	{
2415	/* Check if the root entry is present (must be done before validating reserved bits). */
2416	uint64_t const uRootEntryQword0 = RootEntry.au64[0];
2417	uint64_t const uRootEntryQword1 = RootEntry.au64[1];
2418	bool const fRootEntryPresent = RT_BF_GET(uRootEntryQword0, VTD_BF_0_ROOT_ENTRY_P);
2419	if (fRootEntryPresent)
2420	{
2421	/* Validate reserved bits in the root entry. */
2422	if ( !(uRootEntryQword0 & ~VTD_ROOT_ENTRY_0_VALID_MASK)
2423	&& !(uRootEntryQword1 & ~VTD_ROOT_ENTRY_1_VALID_MASK))
2424	{
2425	/* Read the context-entry from guest memory. */
2426	RTGCPHYS const GCPhysCtxTable = uRootEntryQword0 & VTD_BF_0_ROOT_ENTRY_CTP_MASK;
2427	uint8_t const idxCtxEntry = RT_LO_U8(pMemReqIn->idDevice);
2428	VTD_CONTEXT_ENTRY_T CtxEntry;
2429	rc = dmarDrReadCtxEntry(pDevIns, GCPhysCtxTable, idxCtxEntry, &CtxEntry);
2430	if (RT_SUCCESS(rc))
2431	{
2432	uint64_t const uCtxEntryQword0 = CtxEntry.au64[0];
2433	uint64_t const uCtxEntryQword1 = CtxEntry.au64[1];
2434
2435	/* Note the FPD bit which software can use to supress translation faults from here on in. */
2436	pMemReqAux->fFpd = RT_BF_GET(uCtxEntryQword0, VTD_BF_0_CONTEXT_ENTRY_FPD);
2437
2438	/* Check if the context-entry is present (must be done before validating reserved bits). */
2439	bool const fCtxEntryPresent = RT_BF_GET(uCtxEntryQword0, VTD_BF_0_CONTEXT_ENTRY_P);
2440	if (fCtxEntryPresent)
2441	{
2442	/* Validate reserved bits in the context-entry. */
2443	PCDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PCDMAR);
2444	if ( !(uCtxEntryQword0 & ~VTD_CONTEXT_ENTRY_0_VALID_MASK)
2445	&& !(uCtxEntryQword1 & ~pThis->fCtxEntryQw1ValidMask))
2446	{
2447	/* Get the domain ID for this mapping. */
2448	pMemReqOut->idDomain = RT_BF_GET(uCtxEntryQword1, VTD_BF_1_CONTEXT_ENTRY_DID);
2449
2450	/* Validate the translation type (TT). */
2451	uint8_t const fTt = RT_BF_GET(uCtxEntryQword0, VTD_BF_0_CONTEXT_ENTRY_TT);
2452	switch (fTt)
2453	{
2454	case VTD_TT_UNTRANSLATED_SLP:
2455	{
2456	/*
2457	* Untranslated requests are translated using second-level paging structures referenced
2458	* through SLPTPTR. Translated requests and Translation Requests are blocked.
2459	*/
2460	if (pMemReqIn->enmAddrType == PCIADDRTYPE_UNTRANSLATED)
2461	{
2462	/* Validate the address width and get the paging level. */
2463	uint8_t cPagingLevel;
2464	if (dmarDrLegacyModeIsAwValid(pThis, &CtxEntry, &cPagingLevel))
2465	{
2466	/*
2467	* The second-level page table is located at the physical address specified
2468	* in the context entry with which we can finally perform second-level translation.
2469	*/
2470	pMemReqAux->cPagingLevel = cPagingLevel;
2471	pMemReqAux->GCPhysSlPt = uCtxEntryQword0 & VTD_BF_0_CONTEXT_ENTRY_SLPTPTR_MASK;
2472	rc = dmarDrMemRangeLookup(pDevIns, dmarDrSecondLevelTranslate, pMemReqRemap);
2473	if (rc == VERR_OUT_OF_RANGE)
2474	rc = VINF_SUCCESS;
2475	return rc;
2476	}
2477	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Lm_Ut_Aw_Invalid, pMemReqIn, pMemReqAux);
2478	}
2479	else
2480	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Lm_Ut_At_Block, pMemReqIn, pMemReqAux);
2481	break;
2482	}
2483
2484	case VTD_TT_UNTRANSLATED_PT:
2485	{
2486	/*
2487	* Untranslated requests are processed as pass-through (PT) if PT is supported.
2488	* Translated and translation requests are blocked. If PT isn't supported this TT value
2489	* is reserved which I assume raises a fault (hence fallthru below).
2490	*/
2491	if (pThis->fExtCapReg & VTD_BF_ECAP_REG_PT_MASK)
2492	{
2493	if (pMemReqRemap->In.enmAddrType == PCIADDRTYPE_UNTRANSLATED)
2494	{
2495	if (dmarDrLegacyModeIsAwValid(pThis, &CtxEntry, NULL /* pcPagingLevel */))
2496	{
2497	PDMARMEMREQOUT pOut = &pMemReqRemap->Out;
2498	PCDMARMEMREQIN pIn = &pMemReqRemap->In;
2499	pOut->AddrRange.uAddr = pIn->AddrRange.uAddr;
2500	pOut->AddrRange.cb = pIn->AddrRange.cb;
2501	pOut->AddrRange.fPerm = DMAR_PERM_ALL;
2502	return VINF_SUCCESS;
2503	}
2504	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Lm_Pt_Aw_Invalid, pMemReqIn, pMemReqAux);
2505	}
2506	else
2507	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Lm_Pt_At_Block, pMemReqIn, pMemReqAux);
2508	break;
2509	}
2510	RT_FALL_THRU();
2511	}
2512
2513	case VTD_TT_UNTRANSLATED_DEV_TLB:
2514	{
2515	/*
2516	* Untranslated, translated and translation requests are supported but requires
2517	* device-TLB support. We don't support device-TLBs, so it's treated as reserved.
2518	*/
2519	Assert(!(pThis->fExtCapReg & VTD_BF_ECAP_REG_DT_MASK));
2520	RT_FALL_THRU();
2521	}
2522
2523	default:
2524	{
2525	/* Any other TT value is reserved. */
2526	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Lm_Tt_Invalid, pMemReqIn, pMemReqAux);
2527	break;
2528	}
2529	}
2530	}
2531	else
2532	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Lm_CtxEntry_Rsvd, pMemReqIn, pMemReqAux);
2533	}
2534	else
2535	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Lm_CtxEntry_Not_Present, pMemReqIn, pMemReqAux);
2536	}
2537	else
2538	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Lm_CtxEntry_Read_Failed, pMemReqIn, pMemReqAux);
2539	}
2540	else
2541	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Lm_RootEntry_Rsvd, pMemReqIn, pMemReqAux);
2542	}
2543	else
2544	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Lm_RootEntry_Not_Present, pMemReqIn, pMemReqAux);
2545	}
2546	else
2547	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Lm_RootEntry_Read_Failed, pMemReqIn, pMemReqAux);
2548	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2549	}
2550
2551
2552	/**
2553	* Handles remapping of DMA address requests in scalable mode.
2554	*
2555	* @returns VBox status code.
2556	* @param pDevIns The IOMMU device instance.
2557	* @param uRtaddrReg The current RTADDR_REG value.
2558	* @param pMemReqRemap The DMA memory request remapping info.
2559	*/
2560	static int dmarDrScalableModeRemapAddr(PPDMDEVINS pDevIns, uint64_t uRtaddrReg, PDMARMEMREQREMAP pMemReqRemap)
2561	{
2562	RT_NOREF3(pDevIns, uRtaddrReg, pMemReqRemap);
2563	return VERR_NOT_IMPLEMENTED;
2564	}
2565
2566
2567	/**
2568	* Gets the DMA access permissions and the address-translation request
2569	* type given the PDM IOMMU memory access flags.
2570	*
2571	* @param pDevIns The IOMMU device instance.
2572	* @param fFlags The access flags, see PDMIOMMU_MEM_F_XXX.
2573	* @param fBulk Whether this is a bulk memory access (used for
2574	* statistics).
2575	* @param penmReqType Where to store the address-translation request type.
2576	* @param pfReqPerm Where to store the DMA access permissions.
2577	*/
2578	static void dmarDrGetPermAndReqType(PPDMDEVINS pDevIns, uint32_t fFlags, bool fBulk, PVTDREQTYPE penmReqType, uint8_t *pfReqPerm)
2579	{
2580	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
2581	if (fFlags & PDMIOMMU_MEM_F_READ)
2582	{
2583	*penmReqType = VTDREQTYPE_READ;
2584	*pfReqPerm = DMAR_PERM_READ;
2585	#ifdef VBOX_WITH_STATISTICS
2586	if (!fBulk)
2587	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMemRead));
2588	else
2589	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMemBulkRead));
2590	#else
2591	RT_NOREF2(pThis, fBulk);
2592	#endif
2593	}
2594	else
2595	{
2596	*penmReqType = VTDREQTYPE_WRITE;
2597	*pfReqPerm = DMAR_PERM_WRITE;
2598	#ifdef VBOX_WITH_STATISTICS
2599	if (!fBulk)
2600	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMemWrite));
2601	else
2602	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMemBulkWrite));
2603	#else
2604	RT_NOREF2(pThis, fBulk);
2605	#endif
2606	}
2607	}
2608
2609
2610	/**
2611	* Handles DMA remapping based on the table translation mode (TTM).
2612	*
2613	* @returns VBox status code.
2614	* @param pDevIns The IOMMU device instance.
2615	* @param uRtaddrReg The current RTADDR_REG value.
2616	* @param pMemReqRemap The DMA memory request remapping info.
2617	*/
2618	static int dmarDrMemReqRemap(PPDMDEVINS pDevIns, uint64_t uRtaddrReg, PDMARMEMREQREMAP pMemReqRemap)
2619	{
2620	int rc;
2621	switch (pMemReqRemap->Aux.fTtm)
2622	{
2623	case VTD_TTM_LEGACY_MODE:
2624	{
2625	rc = dmarDrLegacyModeRemapAddr(pDevIns, uRtaddrReg, pMemReqRemap);
2626	break;
2627	}
2628
2629	case VTD_TTM_SCALABLE_MODE:
2630	{
2631	PCDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PCDMAR);
2632	if (pThis->fExtCapReg & VTD_BF_ECAP_REG_SMTS_MASK)
2633	rc = dmarDrScalableModeRemapAddr(pDevIns, uRtaddrReg, pMemReqRemap);
2634	else
2635	{
2636	rc = VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2637	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Rta_Smts_Not_Supported, &pMemReqRemap->In, &pMemReqRemap->Aux);
2638	}
2639	break;
2640	}
2641
2642	case VTD_TTM_ABORT_DMA_MODE:
2643	{
2644	PCDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PCDMAR);
2645	if (pThis->fExtCapReg & VTD_BF_ECAP_REG_ADMS_MASK)
2646	dmarDrTargetAbort(pDevIns);
2647	else
2648	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Rta_Adms_Not_Supported, &pMemReqRemap->In, &pMemReqRemap->Aux);
2649	rc = VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2650	break;
2651	}
2652
2653	default:
2654	{
2655	rc = VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2656	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Rta_Rsvd, &pMemReqRemap->In, &pMemReqRemap->Aux);
2657	break;
2658	}
2659	}
2660	return rc;
2661	}
2662
2663
2664	/**
2665	* Memory access bulk (one or more 4K pages) request from a device.
2666	*
2667	* @returns VBox status code.
2668	* @param pDevIns The IOMMU device instance.
2669	* @param idDevice The device ID (bus, device, function).
2670	* @param cIovas The number of addresses being accessed.
2671	* @param pauIovas The I/O virtual addresses for each page being accessed.
2672	* @param fFlags The access flags, see PDMIOMMU_MEM_F_XXX.
2673	* @param paGCPhysSpa Where to store the translated physical addresses.
2674	*
2675	* @thread Any.
2676	*/
2677	static DECLCALLBACK(int) iommuIntelMemBulkAccess(PPDMDEVINS pDevIns, uint16_t idDevice, size_t cIovas, uint64_t const *pauIovas,
2678	uint32_t fFlags, PRTGCPHYS paGCPhysSpa)
2679	{
2680	/* Validate. */
2681	AssertPtr(pDevIns);
2682	Assert(cIovas > 0);
2683	AssertPtr(pauIovas);
2684	AssertPtr(paGCPhysSpa);
2685	Assert(!(fFlags & ~PDMIOMMU_MEM_F_VALID_MASK));
2686
2687	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
2688	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
2689
2690	DMAR_LOCK(pDevIns, pThisCC);
2691	uint32_t const uGstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GSTS_REG);
2692	uint64_t const uRtaddrReg = pThis->uRtaddrReg;
2693	DMAR_UNLOCK(pDevIns, pThisCC);
2694
2695	if (uGstsReg & VTD_BF_GSTS_REG_TES_MASK)
2696	{
2697	VTDREQTYPE enmReqType;
2698	uint8_t fReqPerm;
2699	dmarDrGetPermAndReqType(pDevIns, fFlags, true /* fBulk */, &enmReqType, &fReqPerm);
2700
2701	DMARMEMREQREMAP MemReqRemap;
2702	RT_ZERO(MemReqRemap);
2703	MemReqRemap.In.AddrRange.cb = X86_PAGE_SIZE;
2704	MemReqRemap.In.AddrRange.fPerm = fReqPerm;
2705	MemReqRemap.In.idDevice = idDevice;
2706	MemReqRemap.In.Pasid = NIL_PCIPASID;
2707	MemReqRemap.In.enmAddrType = PCIADDRTYPE_UNTRANSLATED;
2708	MemReqRemap.In.enmReqType = enmReqType;
2709	MemReqRemap.Aux.fTtm = RT_BF_GET(uRtaddrReg, VTD_BF_RTADDR_REG_TTM);
2710	MemReqRemap.Out.AddrRange.uAddr = NIL_RTGCPHYS;
2711
2712	for (size_t i = 0; i < cIovas; i++)
2713	{
2714	MemReqRemap.In.AddrRange.uAddr = pauIovas[i] & X86_PAGE_BASE_MASK;
2715	int const rc = dmarDrMemReqRemap(pDevIns, uRtaddrReg, &MemReqRemap);
2716	if (RT_SUCCESS(rc))
2717	{
2718	paGCPhysSpa[i] = MemReqRemap.Out.AddrRange.uAddr \| (pauIovas[i] & X86_PAGE_OFFSET_MASK);
2719	Assert(MemReqRemap.Out.AddrRange.cb == MemReqRemap.In.AddrRange.cb);
2720	}
2721	else
2722	{
2723	LogFlowFunc(("idDevice=%#x uIova=%#RX64 fPerm=%#x rc=%Rrc\n", idDevice, pauIovas[i], fReqPerm, rc));
2724	return rc;
2725	}
2726	}
2727	}
2728	else
2729	{
2730	/* Addresses are forwarded without translation when the translation is disabled. */
2731	for (size_t i = 0; i < cIovas; i++)
2732	paGCPhysSpa[i] = pauIovas[i];
2733	}
2734
2735	return VINF_SUCCESS;
2736	}
2737
2738
2739	/**
2740	* Memory access transaction from a device.
2741	*
2742	* @returns VBox status code.
2743	* @param pDevIns The IOMMU device instance.
2744	* @param idDevice The device ID (bus, device, function).
2745	* @param uIova The I/O virtual address being accessed.
2746	* @param cbIova The size of the access.
2747	* @param fFlags The access flags, see PDMIOMMU_MEM_F_XXX.
2748	* @param pGCPhysSpa Where to store the translated system physical address.
2749	* @param pcbContiguous Where to store the number of contiguous bytes translated
2750	* and permission-checked.
2751	*
2752	* @thread Any.
2753	*/
2754	static DECLCALLBACK(int) iommuIntelMemAccess(PPDMDEVINS pDevIns, uint16_t idDevice, uint64_t uIova, size_t cbIova,
2755	uint32_t fFlags, PRTGCPHYS pGCPhysSpa, size_t *pcbContiguous)
2756	{
2757	/* Validate. */
2758	AssertPtr(pDevIns);
2759	AssertPtr(pGCPhysSpa);
2760	AssertPtr(pcbContiguous);
2761	Assert(cbIova > 0); /** @todo Are we going to support ZLR (zero-length reads to write-only pages)? */
2762	Assert(!(fFlags & ~PDMIOMMU_MEM_F_VALID_MASK));
2763
2764	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
2765	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
2766
2767	DMAR_LOCK(pDevIns, pThisCC);
2768	uint32_t const uGstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GSTS_REG);
2769	uint64_t const uRtaddrReg = pThis->uRtaddrReg;
2770	DMAR_UNLOCK(pDevIns, pThisCC);
2771
2772	if (uGstsReg & VTD_BF_GSTS_REG_TES_MASK)
2773	{
2774	VTDREQTYPE enmReqType;
2775	uint8_t fReqPerm;
2776	dmarDrGetPermAndReqType(pDevIns, fFlags, false /* fBulk */, &enmReqType, &fReqPerm);
2777
2778	DMARMEMREQREMAP MemReqRemap;
2779	RT_ZERO(MemReqRemap);
2780	MemReqRemap.In.AddrRange.uAddr = uIova;
2781	MemReqRemap.In.AddrRange.cb = cbIova;
2782	MemReqRemap.In.AddrRange.fPerm = fReqPerm;
2783	MemReqRemap.In.idDevice = idDevice;
2784	MemReqRemap.In.Pasid = NIL_PCIPASID;
2785	MemReqRemap.In.enmAddrType = PCIADDRTYPE_UNTRANSLATED;
2786	MemReqRemap.In.enmReqType = enmReqType;
2787	MemReqRemap.Aux.fTtm = RT_BF_GET(uRtaddrReg, VTD_BF_RTADDR_REG_TTM);
2788	MemReqRemap.Out.AddrRange.uAddr = NIL_RTGCPHYS;
2789
2790	int const rc = dmarDrMemReqRemap(pDevIns, uRtaddrReg, &MemReqRemap);
2791	*pGCPhysSpa = MemReqRemap.Out.AddrRange.uAddr;
2792	*pcbContiguous = MemReqRemap.Out.AddrRange.cb;
2793	return rc;
2794	}
2795
2796	*pGCPhysSpa = uIova;
2797	*pcbContiguous = cbIova;
2798	return VINF_SUCCESS;
2799	}
2800
2801
2802	/**
2803	* Reads an IRTE from guest memory.
2804	*
2805	* @returns VBox status code.
2806	* @param pDevIns The IOMMU device instance.
2807	* @param uIrtaReg The IRTA_REG.
2808	* @param idxIntr The interrupt index.
2809	* @param pIrte Where to store the read IRTE.
2810	*/
2811	static int dmarIrReadIrte(PPDMDEVINS pDevIns, uint64_t uIrtaReg, uint16_t idxIntr, PVTD_IRTE_T pIrte)
2812	{
2813	Assert(idxIntr < VTD_IRTA_REG_GET_ENTRY_COUNT(uIrtaReg));
2814
2815	size_t const cbIrte = sizeof(*pIrte);
2816	RTGCPHYS const GCPhysIrte = (uIrtaReg & VTD_BF_IRTA_REG_IRTA_MASK) + (idxIntr * cbIrte);
2817	return PDMDevHlpPhysReadMeta(pDevIns, GCPhysIrte, pIrte, cbIrte);
2818	}
2819
2820
2821	/**
2822	* Remaps the source MSI to the destination MSI given the IRTE.
2823	*
2824	* @param fExtIntrMode Whether extended interrupt mode is enabled (i.e
2825	* IRTA_REG.EIME).
2826	* @param pIrte The IRTE used for the remapping.
2827	* @param pMsiIn The source MSI (currently unused).
2828	* @param pMsiOut Where to store the remapped MSI.
2829	*/
2830	static void dmarIrRemapFromIrte(bool fExtIntrMode, PCVTD_IRTE_T pIrte, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
2831	{
2832	NOREF(pMsiIn);
2833	uint64_t const uIrteQword0 = pIrte->au64[0];
2834
2835	/*
2836	* Let's start with a clean slate and preserve unspecified bits if the need arises.
2837	* For instance, address bits 1:0 is supposed to be "ignored" by remapping hardware,
2838	* but it's not clear if hardware zeroes out these bits in the remapped MSI or if
2839	* it copies it from the source MSI.
2840	*/
2841	RT_ZERO(*pMsiOut);
2842	pMsiOut->Addr.n.u1DestMode = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_DM);
2843	pMsiOut->Addr.n.u1RedirHint = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_RH);
2844	pMsiOut->Addr.n.u12Addr = VBOX_MSI_ADDR_BASE >> VBOX_MSI_ADDR_SHIFT;
2845	if (fExtIntrMode)
2846	{
2847	/*
2848	* Apparently the DMAR stuffs the high 24-bits of the destination ID into the
2849	* high 24-bits of the upper 32-bits of the message address, see @bugref{9967#c22}.
2850	*/
2851	uint32_t const idDest = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_DST);
2852	pMsiOut->Addr.n.u8DestId = idDest;
2853	pMsiOut->Addr.n.u32Rsvd0 = idDest & UINT32_C(0xffffff00);
2854	}
2855	else
2856	pMsiOut->Addr.n.u8DestId = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_DST_XAPIC);
2857
2858	pMsiOut->Data.n.u8Vector = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_V);
2859	pMsiOut->Data.n.u3DeliveryMode = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_DLM);
2860	pMsiOut->Data.n.u1Level = 1;
2861	pMsiOut->Data.n.u1TriggerMode = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_TM);
2862	}
2863
2864
2865	/**
2866	* Handles remapping of interrupts in remappable interrupt format.
2867	*
2868	* @returns VBox status code.
2869	* @param pDevIns The IOMMU device instance.
2870	* @param uIrtaReg The IRTA_REG.
2871	* @param idDevice The device ID (bus, device, function).
2872	* @param pMsiIn The source MSI.
2873	* @param pMsiOut Where to store the remapped MSI.
2874	*/
2875	static int dmarIrRemapIntr(PPDMDEVINS pDevIns, uint64_t uIrtaReg, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
2876	{
2877	Assert(pMsiIn->Addr.dmar_remap.fIntrFormat == VTD_INTR_FORMAT_REMAPPABLE);
2878
2879	/* Validate reserved bits in the interrupt request. */
2880	AssertCompile(VTD_REMAPPABLE_MSI_ADDR_VALID_MASK == UINT32_MAX);
2881	if (!(pMsiIn->Data.u32 & ~VTD_REMAPPABLE_MSI_DATA_VALID_MASK))
2882	{
2883	/* Compute the index into the interrupt remap table. */
2884	uint16_t const uHandleHi = RT_BF_GET(pMsiIn->Addr.au32[0], VTD_BF_REMAPPABLE_MSI_ADDR_HANDLE_HI);
2885	uint16_t const uHandleLo = RT_BF_GET(pMsiIn->Addr.au32[0], VTD_BF_REMAPPABLE_MSI_ADDR_HANDLE_LO);
2886	uint16_t const uHandle = uHandleLo \| (uHandleHi << 15);
2887	bool const fSubHandleValid = RT_BF_GET(pMsiIn->Addr.au32[0], VTD_BF_REMAPPABLE_MSI_ADDR_SHV);
2888	uint16_t const idxIntr = fSubHandleValid
2889	? uHandle + RT_BF_GET(pMsiIn->Data.u32, VTD_BF_REMAPPABLE_MSI_DATA_SUBHANDLE)
2890	: uHandle;
2891
2892	/* Validate the index. */
2893	uint32_t const cEntries = VTD_IRTA_REG_GET_ENTRY_COUNT(uIrtaReg);
2894	if (idxIntr < cEntries)
2895	{
2896	/** @todo Implement and read IRTE from interrupt-entry cache here. */
2897
2898	/* Read the interrupt remap table entry (IRTE) at the index. */
2899	VTD_IRTE_T Irte;
2900	int rc = dmarIrReadIrte(pDevIns, uIrtaReg, idxIntr, &Irte);
2901	if (RT_SUCCESS(rc))
2902	{
2903	/* Check if the IRTE is present (this must be done -before- checking reserved bits). */
2904	uint64_t const uIrteQword0 = Irte.au64[0];
2905	uint64_t const uIrteQword1 = Irte.au64[1];
2906	bool const fPresent = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_P);
2907	if (fPresent)
2908	{
2909	/* Validate reserved bits in the IRTE. */
2910	bool const fExtIntrMode = RT_BF_GET(uIrtaReg, VTD_BF_IRTA_REG_EIME);
2911	uint64_t const fQw0ValidMask = fExtIntrMode ? VTD_IRTE_0_X2APIC_VALID_MASK : VTD_IRTE_0_XAPIC_VALID_MASK;
2912	if ( !(uIrteQword0 & ~fQw0ValidMask)
2913	&& !(uIrteQword1 & ~VTD_IRTE_1_VALID_MASK))
2914	{
2915	/* Validate requester id (the device ID) as configured in the IRTE. */
2916	bool fSrcValid;
2917	DMARDIAG enmIrDiag;
2918	uint8_t const fSvt = RT_BF_GET(uIrteQword1, VTD_BF_1_IRTE_SVT);
2919	switch (fSvt)
2920	{
2921	case VTD_IRTE_SVT_NONE:
2922	{
2923	fSrcValid = true;
2924	enmIrDiag = kDmarDiag_None;
2925	break;
2926	}
2927
2928	case VTD_IRTE_SVT_VALIDATE_MASK:
2929	{
2930	static uint16_t const s_afValidMasks[] = { 0xffff, 0xfffb, 0xfff9, 0xfff8 };
2931	uint8_t const idxMask = RT_BF_GET(uIrteQword1, VTD_BF_1_IRTE_SQ) & 3;
2932	uint16_t const fValidMask = s_afValidMasks[idxMask];
2933	uint16_t const idSource = RT_BF_GET(uIrteQword1, VTD_BF_1_IRTE_SID);
2934	fSrcValid = (idDevice & fValidMask) == (idSource & fValidMask);
2935	enmIrDiag = kDmarDiag_Ir_Rfi_Irte_Svt_Masked;
2936	break;
2937	}
2938
2939	case VTD_IRTE_SVT_VALIDATE_BUS_RANGE:
2940	{
2941	uint16_t const idSource = RT_BF_GET(uIrteQword1, VTD_BF_1_IRTE_SID);
2942	uint8_t const uBusFirst = RT_HI_U8(idSource);
2943	uint8_t const uBusLast = RT_LO_U8(idSource);
2944	uint8_t const idDeviceBus = idDevice >> VBOX_PCI_BUS_SHIFT;
2945	fSrcValid = (idDeviceBus >= uBusFirst && idDeviceBus <= uBusLast);
2946	enmIrDiag = kDmarDiag_Ir_Rfi_Irte_Svt_Bus;
2947	break;
2948	}
2949
2950	default:
2951	{
2952	fSrcValid = false;
2953	enmIrDiag = kDmarDiag_Ir_Rfi_Irte_Svt_Rsvd;
2954	break;
2955	}
2956	}
2957
2958	if (fSrcValid)
2959	{
2960	uint8_t const fPostedMode = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_IM);
2961	if (!fPostedMode)
2962	{
2963	dmarIrRemapFromIrte(fExtIntrMode, &Irte, pMsiIn, pMsiOut);
2964	return VINF_SUCCESS;
2965	}
2966	dmarIrFaultRecord(pDevIns, kDmarDiag_Ir_Rfi_Irte_Mode_Invalid, idDevice, idxIntr, &Irte);
2967	}
2968	else
2969	dmarIrFaultRecord(pDevIns, enmIrDiag, idDevice, idxIntr, &Irte);
2970	}
2971	else
2972	dmarIrFaultRecord(pDevIns, kDmarDiag_Ir_Rfi_Irte_Rsvd, idDevice, idxIntr, &Irte);
2973	}
2974	else
2975	dmarIrFaultRecord(pDevIns, kDmarDiag_Ir_Rfi_Irte_Not_Present, idDevice, idxIntr, &Irte);
2976	}
2977	else
2978	dmarIrFaultRecord(pDevIns, kDmarDiag_Ir_Rfi_Irte_Read_Failed, idDevice, idxIntr, NULL /* pIrte */);
2979	}
2980	else
2981	dmarIrFaultRecord(pDevIns, kDmarDiag_Ir_Rfi_Intr_Index_Invalid, idDevice, idxIntr, NULL /* pIrte */);
2982	}
2983	else
2984	dmarIrFaultRecord(pDevIns, kDmarDiag_Ir_Rfi_Rsvd, idDevice, 0 /* idxIntr /, NULL / pIrte */);
2985	return VERR_IOMMU_INTR_REMAP_DENIED;
2986	}
2987
2988
2989	/**
2990	* Interrupt remap request from a device.
2991	*
2992	* @returns VBox status code.
2993	* @param pDevIns The IOMMU device instance.
2994	* @param idDevice The device ID (bus, device, function).
2995	* @param pMsiIn The source MSI.
2996	* @param pMsiOut Where to store the remapped MSI.
2997	*/
2998	static DECLCALLBACK(int) iommuIntelMsiRemap(PPDMDEVINS pDevIns, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
2999	{
3000	/* Validate. */
3001	Assert(pDevIns);
3002	Assert(pMsiIn);
3003	Assert(pMsiOut);
3004	RT_NOREF1(idDevice);
3005
3006	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
3007	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
3008
3009	/* Lock and read all registers required for interrupt remapping up-front. */
3010	DMAR_LOCK(pDevIns, pThisCC);
3011	uint32_t const uGstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GSTS_REG);
3012	uint64_t const uIrtaReg = pThis->uIrtaReg;
3013	DMAR_UNLOCK(pDevIns, pThisCC);
3014
3015	/* Check if interrupt remapping is enabled. */
3016	if (uGstsReg & VTD_BF_GSTS_REG_IRES_MASK)
3017	{
3018	bool const fIsRemappable = RT_BF_GET(pMsiIn->Addr.au32[0], VTD_BF_REMAPPABLE_MSI_ADDR_INTR_FMT);
3019	if (!fIsRemappable)
3020	{
3021	/* Handle compatibility format interrupts. */
3022	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMsiRemapCfi));
3023
3024	/* If EIME is enabled or CFIs are disabled, block the interrupt. */
3025	if ( (uIrtaReg & VTD_BF_IRTA_REG_EIME_MASK)
3026	\|\| !(uGstsReg & VTD_BF_GSTS_REG_CFIS_MASK))
3027	{
3028	dmarIrFaultRecord(pDevIns, kDmarDiag_Ir_Cfi_Blocked, VTDIRFAULT_CFI_BLOCKED, idDevice, 0 /* idxIntr */);
3029	return VERR_IOMMU_INTR_REMAP_DENIED;
3030	}
3031
3032	/* Interrupt isn't subject to remapping, pass-through the interrupt. */
3033	pMsiOut = pMsiIn;
3034	return VINF_SUCCESS;
3035	}
3036
3037	/* Handle remappable format interrupts. */
3038	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMsiRemapRfi));
3039	return dmarIrRemapIntr(pDevIns, uIrtaReg, idDevice, pMsiIn, pMsiOut);
3040	}
3041
3042	/* Interrupt-remapping isn't enabled, all interrupts are pass-through. */
3043	pMsiOut = pMsiIn;
3044	return VINF_SUCCESS;
3045	}
3046
3047
3048	/**
3049	* @callback_method_impl{FNIOMMMIONEWWRITE}
3050	*/
3051	static DECLCALLBACK(VBOXSTRICTRC) dmarMmioWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS off, void const pv, unsigned cb)
3052	{
3053	RT_NOREF1(pvUser);
3054	DMAR_ASSERT_MMIO_ACCESS_RET(off, cb);
3055
3056	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
3057	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioWrite));
3058
3059	uint16_t const offReg = off;
3060	uint16_t const offLast = offReg + cb - 1;
3061	if (DMAR_IS_MMIO_OFF_VALID(offLast))
3062	{
3063	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
3064	DMAR_LOCK_RET(pDevIns, pThisCC, VINF_IOM_R3_MMIO_WRITE);
3065
3066	uint64_t uPrev = 0;
3067	uint64_t const uRegWritten = cb == 8 ? dmarRegWrite64(pThis, offReg, (uint64_t )pv, &uPrev)
3068	: dmarRegWrite32(pThis, offReg, (uint32_t )pv, (uint32_t *)&uPrev);
3069	VBOXSTRICTRC rcStrict = VINF_SUCCESS;
3070	switch (off)
3071	{
3072	case VTD_MMIO_OFF_GCMD_REG: /* 32-bit */
3073	{
3074	rcStrict = dmarGcmdRegWrite(pDevIns, uRegWritten);
3075	break;
3076	}
3077
3078	case VTD_MMIO_OFF_CCMD_REG: /* 64-bit */
3079	case VTD_MMIO_OFF_CCMD_REG + 4:
3080	{
3081	rcStrict = dmarCcmdRegWrite(pDevIns, offReg, cb, uRegWritten);
3082	break;
3083	}
3084
3085	case VTD_MMIO_OFF_FSTS_REG: /* 32-bit */
3086	{
3087	rcStrict = dmarFstsRegWrite(pDevIns, uRegWritten, uPrev);
3088	break;
3089	}
3090
3091	case VTD_MMIO_OFF_FECTL_REG: /* 32-bit */
3092	{
3093	rcStrict = dmarFectlRegWrite(pDevIns, uRegWritten);
3094	break;
3095	}
3096
3097	case VTD_MMIO_OFF_IQT_REG: /* 64-bit */
3098	/* VTD_MMIO_OFF_IQT_REG + 4: / / High 32-bits reserved. */
3099	{
3100	rcStrict = dmarIqtRegWrite(pDevIns, offReg, uRegWritten);
3101	break;
3102	}
3103
3104	case VTD_MMIO_OFF_IQA_REG: /* 64-bit */
3105	/* VTD_MMIO_OFF_IQA_REG + 4: / / High 32-bits data. */
3106	{
3107	rcStrict = dmarIqaRegWrite(pDevIns, offReg, uRegWritten);
3108	break;
3109	}
3110
3111	case VTD_MMIO_OFF_ICS_REG: /* 32-bit */
3112	{
3113	rcStrict = dmarIcsRegWrite(pDevIns, uRegWritten);
3114	break;
3115	}
3116
3117	case VTD_MMIO_OFF_IECTL_REG: /* 32-bit */
3118	{
3119	rcStrict = dmarIectlRegWrite(pDevIns, uRegWritten);
3120	break;
3121	}
3122
3123	case DMAR_MMIO_OFF_FRCD_HI_REG: /* 64-bit */
3124	case DMAR_MMIO_OFF_FRCD_HI_REG + 4:
3125	{
3126	rcStrict = dmarFrcdHiRegWrite(pDevIns, offReg, cb, uRegWritten, uPrev);
3127	break;
3128	}
3129	}
3130
3131	DMAR_UNLOCK(pDevIns, pThisCC);
3132	LogFlowFunc(("offReg=%#x uRegWritten=%#RX64 rc=%Rrc\n", offReg, uRegWritten, VBOXSTRICTRC_VAL(rcStrict)));
3133	return rcStrict;
3134	}
3135
3136	return VINF_IOM_MMIO_UNUSED_FF;
3137	}
3138
3139
3140	/**
3141	* @callback_method_impl{FNIOMMMIONEWREAD}
3142	*/
3143	static DECLCALLBACK(VBOXSTRICTRC) dmarMmioRead(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS off, void pv, unsigned cb)
3144	{
3145	RT_NOREF1(pvUser);
3146	DMAR_ASSERT_MMIO_ACCESS_RET(off, cb);
3147
3148	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
3149	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioRead));
3150
3151	uint16_t const offReg = off;
3152	uint16_t const offLast = offReg + cb - 1;
3153	if (DMAR_IS_MMIO_OFF_VALID(offLast))
3154	{
3155	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
3156	DMAR_LOCK_RET(pDevIns, pThisCC, VINF_IOM_R3_MMIO_READ);
3157
3158	if (cb == 8)
3159	{
3160	(uint64_t )pv = dmarRegRead64(pThis, offReg);
3161	LogFlowFunc(("offReg=%#x pv=%#RX64\n", offReg, (uint64_t )pv));
3162	}
3163	else
3164	{
3165	(uint32_t )pv = dmarRegRead32(pThis, offReg);
3166	LogFlowFunc(("offReg=%#x pv=%#RX32\n", offReg, (uint32_t )pv));
3167	}
3168
3169	DMAR_UNLOCK(pDevIns, pThisCC);
3170	return VINF_SUCCESS;
3171	}
3172
3173	return VINF_IOM_MMIO_UNUSED_FF;
3174	}
3175
3176
3177	#ifdef IN_RING3
3178	/**
3179	* Process requests in the invalidation queue.
3180	*
3181	* @param pDevIns The IOMMU device instance.
3182	* @param pvRequests The requests to process.
3183	* @param cbRequests The size of all requests (in bytes).
3184	* @param fDw The descriptor width (VTD_IQA_REG_DW_128_BIT or
3185	* VTD_IQA_REG_DW_256_BIT).
3186	* @param fTtm The table translation mode. Must not be VTD_TTM_RSVD.
3187	*/
3188	static void dmarR3InvQueueProcessRequests(PPDMDEVINS pDevIns, void const *pvRequests, uint32_t cbRequests, uint8_t fDw,
3189	uint8_t fTtm)
3190	{
3191	#define DMAR_IQE_FAULT_RECORD_RET(a_enmDiag, a_enmIqei) \
3192	do \
3193	{ \
3194	dmarIqeFaultRecord(pDevIns, (a_enmDiag), (a_enmIqei)); \
3195	return; \
3196	} while (0)
3197
3198	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
3199	PCDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARR3);
3200
3201	DMAR_ASSERT_LOCK_IS_NOT_OWNER(pDevIns, pThisR3);
3202	Assert(fTtm != VTD_TTM_RSVD); /* Should've beeen handled by caller. */
3203
3204	/*
3205	* The below check is redundant since we check both TTM and DW for each
3206	* descriptor type we process. However, the order of errors reported by hardware
3207	* may differ hence this is kept commented out but not removed if we need to
3208	* change this in the future.
3209	*
3210	* In our implementation, we would report the descriptor type as invalid,
3211	* while on real hardware it may report descriptor width as invalid.
3212	* The Intel VT-d spec. is not clear which error takes preceedence.
3213	*/
3214	#if 0
3215	/*
3216	* Verify that 128-bit descriptors are not used when operating in scalable mode.
3217	* We don't check this while software writes IQA_REG but defer it until now because
3218	* RTADDR_REG can be updated lazily (via GCMD_REG.SRTP). The 256-bit descriptor check
3219	* -IS- performed when software writes IQA_REG since it only requires checking against
3220	* immutable hardware features.
3221	*/
3222	if ( fTtm != VTD_TTM_SCALABLE_MODE
3223	\|\| fDw != VTD_IQA_REG_DW_128_BIT)
3224	{ /* likely */ }
3225	else
3226	DMAR_IQE_FAULT_RECORD_RET(kDmarDiag_IqaReg_Dw_128_Invalid, VTDIQEI_INVALID_DESCRIPTOR_WIDTH);
3227	#endif
3228
3229	/*
3230	* Process requests in FIFO order.
3231	*/
3232	uint8_t const cbDsc = fDw == VTD_IQA_REG_DW_256_BIT ? 32 : 16;
3233	for (uint32_t offDsc = 0; offDsc < cbRequests; offDsc += cbDsc)
3234	{
3235	uint64_t const puDscQwords = (uint64_t const )((uintptr_t)pvRequests + offDsc);
3236	uint64_t const uQword0 = puDscQwords[0];
3237	uint64_t const uQword1 = puDscQwords[1];
3238	uint8_t const fDscType = VTD_GENERIC_INV_DSC_GET_TYPE(uQword0);
3239	switch (fDscType)
3240	{
3241	case VTD_INV_WAIT_DSC_TYPE:
3242	{
3243	/* Validate descriptor type. */
3244	if ( fTtm == VTD_TTM_LEGACY_MODE
3245	\|\| fDw == VTD_IQA_REG_DW_256_BIT)
3246	{ /* likely */ }
3247	else
3248	DMAR_IQE_FAULT_RECORD_RET(kDmarDiag_Iqei_Inv_Wait_Dsc_Invalid, VTDIQEI_INVALID_DESCRIPTOR_TYPE);
3249
3250	/* Validate reserved bits. */
3251	uint64_t const fValidMask0 = !(pThis->fExtCapReg & VTD_BF_ECAP_REG_PDS_MASK)
3252	? VTD_INV_WAIT_DSC_0_VALID_MASK & ~VTD_BF_0_INV_WAIT_DSC_PD_MASK
3253	: VTD_INV_WAIT_DSC_0_VALID_MASK;
3254	if ( !(uQword0 & ~fValidMask0)
3255	&& !(uQword1 & ~VTD_INV_WAIT_DSC_1_VALID_MASK))
3256	{ /* likely */ }
3257	else
3258	DMAR_IQE_FAULT_RECORD_RET(kDmarDiag_Iqei_Inv_Wait_Dsc_0_1_Rsvd, VTDIQEI_RSVD_FIELD_VIOLATION);
3259
3260	if (fDw == VTD_IQA_REG_DW_256_BIT)
3261	{
3262	if ( !puDscQwords[2]
3263	&& !puDscQwords[3])
3264	{ /* likely */ }
3265	else
3266	DMAR_IQE_FAULT_RECORD_RET(kDmarDiag_Iqei_Inv_Wait_Dsc_2_3_Rsvd, VTDIQEI_RSVD_FIELD_VIOLATION);
3267	}
3268
3269	/* Perform status write (this must be done prior to generating the completion interrupt). */
3270	bool const fSw = RT_BF_GET(uQword0, VTD_BF_0_INV_WAIT_DSC_SW);
3271	if (fSw)
3272	{
3273	uint32_t const uStatus = RT_BF_GET(uQword0, VTD_BF_0_INV_WAIT_DSC_STDATA);
3274	RTGCPHYS const GCPhysStatus = uQword1 & VTD_BF_1_INV_WAIT_DSC_STADDR_MASK;
3275	int const rc = PDMDevHlpPhysWrite(pDevIns, GCPhysStatus, (void const*)&uStatus, sizeof(uStatus));
3276	AssertRC(rc);
3277	}
3278
3279	/* Generate invalidation event interrupt. */
3280	bool const fIf = RT_BF_GET(uQword0, VTD_BF_0_INV_WAIT_DSC_IF);
3281	if (fIf)
3282	{
3283	DMAR_LOCK(pDevIns, pThisR3);
3284	dmarR3InvEventRaiseInterrupt(pDevIns);
3285	DMAR_UNLOCK(pDevIns, pThisR3);
3286	}
3287
3288	STAM_COUNTER_INC(&pThis->StatInvWaitDsc);
3289	break;
3290	}
3291
3292	case VTD_CC_INV_DSC_TYPE: STAM_COUNTER_INC(&pThis->StatCcInvDsc); break;
3293	case VTD_IOTLB_INV_DSC_TYPE: STAM_COUNTER_INC(&pThis->StatIotlbInvDsc); break;
3294	case VTD_DEV_TLB_INV_DSC_TYPE: STAM_COUNTER_INC(&pThis->StatDevtlbInvDsc); break;
3295	case VTD_IEC_INV_DSC_TYPE: STAM_COUNTER_INC(&pThis->StatIecInvDsc); break;
3296	case VTD_P_IOTLB_INV_DSC_TYPE: STAM_COUNTER_INC(&pThis->StatPasidIotlbInvDsc); break;
3297	case VTD_PC_INV_DSC_TYPE: STAM_COUNTER_INC(&pThis->StatPasidCacheInvDsc); break;
3298	case VTD_P_DEV_TLB_INV_DSC_TYPE: STAM_COUNTER_INC(&pThis->StatPasidDevtlbInvDsc); break;
3299	default:
3300	{
3301	/* Stop processing further requests. */
3302	LogFunc(("Invalid descriptor type: %#x\n", fDscType));
3303	DMAR_IQE_FAULT_RECORD_RET(kDmarDiag_Iqei_Dsc_Type_Invalid, VTDIQEI_INVALID_DESCRIPTOR_TYPE);
3304	}
3305	}
3306	}
3307	#undef DMAR_IQE_FAULT_RECORD_RET
3308	}
3309
3310
3311	/**
3312	* The invalidation-queue thread.
3313	*
3314	* @returns VBox status code.
3315	* @param pDevIns The IOMMU device instance.
3316	* @param pThread The command thread.
3317	*/
3318	static DECLCALLBACK(int) dmarR3InvQueueThread(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
3319	{
3320	NOREF(pThread);
3321	LogFlowFunc(("\n"));
3322
3323	if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
3324	return VINF_SUCCESS;
3325
3326	/*
3327	* Pre-allocate the maximum size of the invalidation queue allowed by the spec.
3328	* This prevents trashing the heap as well as deal with out-of-memory situations
3329	* up-front while starting the VM. It also simplifies the code from having to
3330	* dynamically grow/shrink the allocation based on how software sizes the queue.
3331	* Guests normally don't alter the queue size all the time, but that's not an
3332	* assumption we can make.
3333	*/
3334	uint8_t const cMaxPages = 1 << VTD_BF_IQA_REG_QS_MASK;
3335	size_t const cbMaxQs = cMaxPages << X86_PAGE_SHIFT;
3336	void *pvRequests = RTMemAllocZ(cbMaxQs);
3337	AssertPtrReturn(pvRequests, VERR_NO_MEMORY);
3338
3339	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
3340	PCDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARR3);
3341
3342	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
3343	{
3344	/*
3345	* Sleep until we are woken up.
3346	*/
3347	{
3348	int const rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->hEvtInvQueue, RT_INDEFINITE_WAIT);
3349	AssertLogRelMsgReturn(RT_SUCCESS(rc) \|\| rc == VERR_INTERRUPTED, ("%Rrc\n", rc), rc);
3350	if (RT_UNLIKELY(pThread->enmState != PDMTHREADSTATE_RUNNING))
3351	break;
3352	}
3353
3354	DMAR_LOCK(pDevIns, pThisR3);
3355	if (dmarInvQueueCanProcessRequests(pThis))
3356	{
3357	uint32_t offQueueHead;
3358	uint32_t offQueueTail;
3359	bool const fIsEmpty = dmarInvQueueIsEmptyEx(pThis, &offQueueHead, &offQueueTail);
3360	if (!fIsEmpty)
3361	{
3362	/*
3363	* Get the current queue size, descriptor width, queue base address and the
3364	* table translation mode while the lock is still held.
3365	*/
3366	uint64_t const uIqaReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IQA_REG);
3367	uint8_t const cQueuePages = 1 << (uIqaReg & VTD_BF_IQA_REG_QS_MASK);
3368	uint32_t const cbQueue = cQueuePages << X86_PAGE_SHIFT;
3369	uint8_t const fDw = RT_BF_GET(uIqaReg, VTD_BF_IQA_REG_DW);
3370	uint8_t const fTtm = RT_BF_GET(pThis->uRtaddrReg, VTD_BF_RTADDR_REG_TTM);
3371	RTGCPHYS const GCPhysRequests = (uIqaReg & VTD_BF_IQA_REG_IQA_MASK) + offQueueHead;
3372
3373	/* Paranoia. */
3374	Assert(cbQueue <= cbMaxQs);
3375	Assert(!(offQueueTail & ~VTD_BF_IQT_REG_QT_MASK));
3376	Assert(!(offQueueHead & ~VTD_BF_IQH_REG_QH_MASK));
3377	Assert(fDw != VTD_IQA_REG_DW_256_BIT \|\| !(offQueueTail & RT_BIT(4)));
3378	Assert(fDw != VTD_IQA_REG_DW_256_BIT \|\| !(offQueueHead & RT_BIT(4)));
3379	Assert(offQueueHead < cbQueue);
3380
3381	/*
3382	* A table translation mode of "reserved" isn't valid for any descriptor type.
3383	* However, RTADDR_REG can be modified in parallel to invalidation-queue processing,
3384	* but if ESRTPS is support, we will perform a global invalidation when software
3385	* changes RTADDR_REG, or it's the responsibility of software to do it explicitly.
3386	* So caching TTM while reading all descriptors should not be a problem.
3387	*
3388	* Also, validate the queue tail offset as it's mutable by software.
3389	*/
3390	if ( fTtm != VTD_TTM_RSVD
3391	&& offQueueTail < cbQueue)
3392	{
3393	/* Don't hold the lock while reading (a potentially large amount of) requests */
3394	DMAR_UNLOCK(pDevIns, pThisR3);
3395
3396	int rc;
3397	uint32_t cbRequests;
3398	if (offQueueTail > offQueueHead)
3399	{
3400	/* The requests have not wrapped around, read them in one go. */
3401	cbRequests = offQueueTail - offQueueHead;
3402	rc = PDMDevHlpPhysReadMeta(pDevIns, GCPhysRequests, pvRequests, cbRequests);
3403	}
3404	else
3405	{
3406	/* The requests have wrapped around, read forward and wrapped-around. */
3407	uint32_t const cbForward = cbQueue - offQueueHead;
3408	rc = PDMDevHlpPhysReadMeta(pDevIns, GCPhysRequests, pvRequests, cbForward);
3409
3410	uint32_t const cbWrapped = offQueueTail;
3411	if ( RT_SUCCESS(rc)
3412	&& cbWrapped > 0)
3413	{
3414	rc = PDMDevHlpPhysReadMeta(pDevIns, GCPhysRequests + cbForward,
3415	(void *)((uintptr_t)pvRequests + cbForward), cbWrapped);
3416	}
3417	cbRequests = cbForward + cbWrapped;
3418	}
3419
3420	/* Re-acquire the lock since we need to update device state. */
3421	DMAR_LOCK(pDevIns, pThisR3);
3422
3423	if (RT_SUCCESS(rc))
3424	{
3425	/* Indicate to software we've fetched all requests. */
3426	dmarRegWriteRaw64(pThis, VTD_MMIO_OFF_IQH_REG, offQueueTail);
3427
3428	/* Don't hold the lock while processing requests. */
3429	DMAR_UNLOCK(pDevIns, pThisR3);
3430
3431	/* Process all requests. */
3432	Assert(cbRequests <= cbQueue);
3433	dmarR3InvQueueProcessRequests(pDevIns, pvRequests, cbRequests, fDw, fTtm);
3434
3435	/*
3436	* We've processed all requests and the lock shouldn't be held at this point.
3437	* Using 'continue' here allows us to skip re-acquiring the lock just to release
3438	* it again before going back to the thread loop. It's a bit ugly but it certainly
3439	* helps with performance.
3440	*/
3441	DMAR_ASSERT_LOCK_IS_NOT_OWNER(pDevIns, pThisR3);
3442	continue;
3443	}
3444	else
3445	dmarIqeFaultRecord(pDevIns, kDmarDiag_IqaReg_Dsc_Fetch_Error, VTDIQEI_FETCH_DESCRIPTOR_ERR);
3446	}
3447	else
3448	{
3449	if (fTtm == VTD_TTM_RSVD)
3450	dmarIqeFaultRecord(pDevIns, kDmarDiag_Iqei_Ttm_Rsvd, VTDIQEI_INVALID_TTM);
3451	else
3452	{
3453	Assert(offQueueTail >= cbQueue);
3454	dmarIqeFaultRecord(pDevIns, kDmarDiag_IqtReg_Qt_Invalid, VTDIQEI_INVALID_TAIL_PTR);
3455	}
3456	}
3457	}
3458	}
3459	DMAR_UNLOCK(pDevIns, pThisR3);
3460	}
3461
3462	RTMemFree(pvRequests);
3463	pvRequests = NULL;
3464
3465	LogFlowFunc(("Invalidation-queue thread terminating\n"));
3466	return VINF_SUCCESS;
3467	}
3468
3469
3470	/**
3471	* Wakes up the invalidation-queue thread so it can respond to a state
3472	* change.
3473	*
3474	* @returns VBox status code.
3475	* @param pDevIns The IOMMU device instance.
3476	* @param pThread The invalidation-queue thread.
3477	*
3478	* @thread EMT.
3479	*/
3480	static DECLCALLBACK(int) dmarR3InvQueueThreadWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
3481	{
3482	RT_NOREF(pThread);
3483	LogFlowFunc(("\n"));
3484	PCDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
3485	return PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEvtInvQueue);
3486	}
3487
3488
3489	/**
3490	* @callback_method_impl{FNDBGFHANDLERDEV}
3491	*/
3492	static DECLCALLBACK(void) dmarR3DbgInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
3493	{
3494	PCDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
3495	PCDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARR3);
3496	bool const fVerbose = RTStrCmp(pszArgs, "verbose") == 0;
3497
3498	/*
3499	* We lock the device to get a consistent register state as it is
3500	* ASSUMED pHlp->pfnPrintf is expensive, so we copy the registers (the
3501	* ones we care about here) into temporaries and release the lock ASAP.
3502	*
3503	* Order of register being read and outputted is in accordance with the
3504	* spec. for no particular reason.
3505	* See Intel VT-d spec. 10.4 "Register Descriptions".
3506	*/
3507	DMAR_LOCK(pDevIns, pThisR3);
3508
3509	DMARDIAG const enmDiag = pThis->enmDiag;
3510	uint32_t const uVerReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_VER_REG);
3511	uint64_t const uCapReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_CAP_REG);
3512	uint64_t const uEcapReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_ECAP_REG);
3513	uint32_t const uGcmdReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GCMD_REG);
3514	uint32_t const uGstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GSTS_REG);
3515	uint64_t const uRtaddrReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_RTADDR_REG);
3516	uint64_t const uCcmdReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_CCMD_REG);
3517	uint32_t const uFstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FSTS_REG);
3518	uint32_t const uFectlReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FECTL_REG);
3519	uint32_t const uFedataReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FEDATA_REG);
3520	uint32_t const uFeaddrReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FEADDR_REG);
3521	uint32_t const uFeuaddrReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FEUADDR_REG);
3522	uint64_t const uAflogReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_AFLOG_REG);
3523	uint32_t const uPmenReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PMEN_REG);
3524	uint32_t const uPlmbaseReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PLMBASE_REG);
3525	uint32_t const uPlmlimitReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PLMLIMIT_REG);
3526	uint64_t const uPhmbaseReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_PHMBASE_REG);
3527	uint64_t const uPhmlimitReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_PHMLIMIT_REG);
3528	uint64_t const uIqhReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IQH_REG);
3529	uint64_t const uIqtReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IQT_REG);
3530	uint64_t const uIqaReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IQA_REG);
3531	uint32_t const uIcsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_ICS_REG);
3532	uint32_t const uIectlReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IECTL_REG);
3533	uint32_t const uIedataReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IEDATA_REG);
3534	uint32_t const uIeaddrReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IEADDR_REG);
3535	uint32_t const uIeuaddrReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IEUADDR_REG);
3536	uint64_t const uIqercdReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IQERCD_REG);
3537	uint64_t const uIrtaReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IRTA_REG);
3538	uint64_t const uPqhReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_PQH_REG);
3539	uint64_t const uPqtReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_PQT_REG);
3540	uint64_t const uPqaReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_PQA_REG);
3541	uint32_t const uPrsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PRS_REG);
3542	uint32_t const uPectlReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PECTL_REG);
3543	uint32_t const uPedataReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PEDATA_REG);
3544	uint32_t const uPeaddrReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PEADDR_REG);
3545	uint32_t const uPeuaddrReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PEUADDR_REG);
3546	uint64_t const uMtrrcapReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_MTRRCAP_REG);
3547	uint64_t const uMtrrdefReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_MTRRDEF_REG);
3548
3549	DMAR_UNLOCK(pDevIns, pThisR3);
3550
3551	const char *const pszDiag = enmDiag < RT_ELEMENTS(g_apszDmarDiagDesc) ? g_apszDmarDiagDesc[enmDiag] : "(Unknown)";
3552	pHlp->pfnPrintf(pHlp, "Intel-IOMMU:\n");
3553	pHlp->pfnPrintf(pHlp, " Diag = %s\n", pszDiag);
3554
3555	/*
3556	* Non-verbose output.
3557	*/
3558	if (!fVerbose)
3559	{
3560	pHlp->pfnPrintf(pHlp, " VER_REG = %#RX32\n", uVerReg);
3561	pHlp->pfnPrintf(pHlp, " CAP_REG = %#RX64\n", uCapReg);
3562	pHlp->pfnPrintf(pHlp, " ECAP_REG = %#RX64\n", uEcapReg);
3563	pHlp->pfnPrintf(pHlp, " GCMD_REG = %#RX32\n", uGcmdReg);
3564	pHlp->pfnPrintf(pHlp, " GSTS_REG = %#RX32\n", uGstsReg);
3565	pHlp->pfnPrintf(pHlp, " RTADDR_REG = %#RX64\n", uRtaddrReg);
3566	pHlp->pfnPrintf(pHlp, " CCMD_REG = %#RX64\n", uCcmdReg);
3567	pHlp->pfnPrintf(pHlp, " FSTS_REG = %#RX32\n", uFstsReg);
3568	pHlp->pfnPrintf(pHlp, " FECTL_REG = %#RX32\n", uFectlReg);
3569	pHlp->pfnPrintf(pHlp, " FEDATA_REG = %#RX32\n", uFedataReg);
3570	pHlp->pfnPrintf(pHlp, " FEADDR_REG = %#RX32\n", uFeaddrReg);
3571	pHlp->pfnPrintf(pHlp, " FEUADDR_REG = %#RX32\n", uFeuaddrReg);
3572	pHlp->pfnPrintf(pHlp, " AFLOG_REG = %#RX64\n", uAflogReg);
3573	pHlp->pfnPrintf(pHlp, " PMEN_REG = %#RX32\n", uPmenReg);
3574	pHlp->pfnPrintf(pHlp, " PLMBASE_REG = %#RX32\n", uPlmbaseReg);
3575	pHlp->pfnPrintf(pHlp, " PLMLIMIT_REG = %#RX32\n", uPlmlimitReg);
3576	pHlp->pfnPrintf(pHlp, " PHMBASE_REG = %#RX64\n", uPhmbaseReg);
3577	pHlp->pfnPrintf(pHlp, " PHMLIMIT_REG = %#RX64\n", uPhmlimitReg);
3578	pHlp->pfnPrintf(pHlp, " IQH_REG = %#RX64\n", uIqhReg);
3579	pHlp->pfnPrintf(pHlp, " IQT_REG = %#RX64\n", uIqtReg);
3580	pHlp->pfnPrintf(pHlp, " IQA_REG = %#RX64\n", uIqaReg);
3581	pHlp->pfnPrintf(pHlp, " ICS_REG = %#RX32\n", uIcsReg);
3582	pHlp->pfnPrintf(pHlp, " IECTL_REG = %#RX32\n", uIectlReg);
3583	pHlp->pfnPrintf(pHlp, " IEDATA_REG = %#RX32\n", uIedataReg);
3584	pHlp->pfnPrintf(pHlp, " IEADDR_REG = %#RX32\n", uIeaddrReg);
3585	pHlp->pfnPrintf(pHlp, " IEUADDR_REG = %#RX32\n", uIeuaddrReg);
3586	pHlp->pfnPrintf(pHlp, " IQERCD_REG = %#RX64\n", uIqercdReg);
3587	pHlp->pfnPrintf(pHlp, " IRTA_REG = %#RX64\n", uIrtaReg);
3588	pHlp->pfnPrintf(pHlp, " PQH_REG = %#RX64\n", uPqhReg);
3589	pHlp->pfnPrintf(pHlp, " PQT_REG = %#RX64\n", uPqtReg);
3590	pHlp->pfnPrintf(pHlp, " PQA_REG = %#RX64\n", uPqaReg);
3591	pHlp->pfnPrintf(pHlp, " PRS_REG = %#RX32\n", uPrsReg);
3592	pHlp->pfnPrintf(pHlp, " PECTL_REG = %#RX32\n", uPectlReg);
3593	pHlp->pfnPrintf(pHlp, " PEDATA_REG = %#RX32\n", uPedataReg);
3594	pHlp->pfnPrintf(pHlp, " PEADDR_REG = %#RX32\n", uPeaddrReg);
3595	pHlp->pfnPrintf(pHlp, " PEUADDR_REG = %#RX32\n", uPeuaddrReg);
3596	pHlp->pfnPrintf(pHlp, " MTRRCAP_REG = %#RX64\n", uMtrrcapReg);
3597	pHlp->pfnPrintf(pHlp, " MTRRDEF_REG = %#RX64\n", uMtrrdefReg);
3598	pHlp->pfnPrintf(pHlp, "\n");
3599	return;
3600	}
3601
3602	/*
3603	* Verbose output.
3604	*/
3605	pHlp->pfnPrintf(pHlp, " VER_REG = %#RX32\n", uVerReg);
3606	{
3607	pHlp->pfnPrintf(pHlp, " MAJ = %#x\n", RT_BF_GET(uVerReg, VTD_BF_VER_REG_MAX));
3608	pHlp->pfnPrintf(pHlp, " MIN = %#x\n", RT_BF_GET(uVerReg, VTD_BF_VER_REG_MIN));
3609	}
3610	pHlp->pfnPrintf(pHlp, " CAP_REG = %#RX64\n", uCapReg);
3611	{
3612	uint8_t const uMgaw = RT_BF_GET(uCapReg, VTD_BF_CAP_REG_MGAW);
3613	uint8_t const uNfr = RT_BF_GET(uCapReg, VTD_BF_CAP_REG_NFR);
3614	pHlp->pfnPrintf(pHlp, " ND = %u\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_ND));
3615	pHlp->pfnPrintf(pHlp, " AFL = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_AFL));
3616	pHlp->pfnPrintf(pHlp, " RWBF = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_RWBF));
3617	pHlp->pfnPrintf(pHlp, " PLMR = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_PLMR));
3618	pHlp->pfnPrintf(pHlp, " PHMR = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_PHMR));
3619	pHlp->pfnPrintf(pHlp, " CM = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_CM));
3620	pHlp->pfnPrintf(pHlp, " SAGAW = %#x\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_SAGAW));
3621	pHlp->pfnPrintf(pHlp, " MGAW = %#x (%u bits)\n", uMgaw, uMgaw + 1);
3622	pHlp->pfnPrintf(pHlp, " ZLR = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_ZLR));
3623	pHlp->pfnPrintf(pHlp, " FRO = %#x bytes\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_FRO));
3624	pHlp->pfnPrintf(pHlp, " SLLPS = %#x\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_SLLPS));
3625	pHlp->pfnPrintf(pHlp, " PSI = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_PSI));
3626	pHlp->pfnPrintf(pHlp, " NFR = %u (%u FRCD register%s)\n", uNfr, uNfr + 1, uNfr > 0 ? "s" : "");
3627	pHlp->pfnPrintf(pHlp, " MAMV = %#x\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_MAMV));
3628	pHlp->pfnPrintf(pHlp, " DWD = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_DWD));
3629	pHlp->pfnPrintf(pHlp, " DRD = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_DRD));
3630	pHlp->pfnPrintf(pHlp, " FL1GP = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_FL1GP));
3631	pHlp->pfnPrintf(pHlp, " PI = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_PI));
3632	pHlp->pfnPrintf(pHlp, " FL5LP = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_FL5LP));
3633	pHlp->pfnPrintf(pHlp, " ESIRTPS = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_ESIRTPS));
3634	pHlp->pfnPrintf(pHlp, " ESRTPS = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_ESRTPS));
3635	}
3636	pHlp->pfnPrintf(pHlp, " ECAP_REG = %#RX64\n", uEcapReg);
3637	{
3638	uint8_t const uPss = RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_PSS);
3639	pHlp->pfnPrintf(pHlp, " C = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_C));
3640	pHlp->pfnPrintf(pHlp, " QI = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_QI));
3641	pHlp->pfnPrintf(pHlp, " DT = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_DT));
3642	pHlp->pfnPrintf(pHlp, " IR = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_IR));
3643	pHlp->pfnPrintf(pHlp, " EIM = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_EIM));
3644	pHlp->pfnPrintf(pHlp, " PT = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_PT));
3645	pHlp->pfnPrintf(pHlp, " SC = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_SC));
3646	pHlp->pfnPrintf(pHlp, " IRO = %#x bytes\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_IRO));
3647	pHlp->pfnPrintf(pHlp, " MHMV = %#x\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_MHMV));
3648	pHlp->pfnPrintf(pHlp, " MTS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_MTS));
3649	pHlp->pfnPrintf(pHlp, " NEST = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_NEST));
3650	pHlp->pfnPrintf(pHlp, " PRS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_PRS));
3651	pHlp->pfnPrintf(pHlp, " ERS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_ERS));
3652	pHlp->pfnPrintf(pHlp, " SRS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_SRS));
3653	pHlp->pfnPrintf(pHlp, " NWFS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_NWFS));
3654	pHlp->pfnPrintf(pHlp, " EAFS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_EAFS));
3655	pHlp->pfnPrintf(pHlp, " PSS = %u (%u bits)\n", uPss, uPss > 0 ? uPss + 1 : 0);
3656	pHlp->pfnPrintf(pHlp, " PASID = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_PASID));
3657	pHlp->pfnPrintf(pHlp, " DIT = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_DIT));
3658	pHlp->pfnPrintf(pHlp, " PDS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_PDS));
3659	pHlp->pfnPrintf(pHlp, " SMTS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_SMTS));
3660	pHlp->pfnPrintf(pHlp, " VCS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_VCS));
3661	pHlp->pfnPrintf(pHlp, " SLADS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_SLADS));
3662	pHlp->pfnPrintf(pHlp, " SLTS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_SLTS));
3663	pHlp->pfnPrintf(pHlp, " FLTS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_FLTS));
3664	pHlp->pfnPrintf(pHlp, " SMPWCS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_SMPWCS));
3665	pHlp->pfnPrintf(pHlp, " RPS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_RPS));
3666	pHlp->pfnPrintf(pHlp, " ADMS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_ADMS));
3667	pHlp->pfnPrintf(pHlp, " RPRIVS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_RPRIVS));
3668	}
3669	pHlp->pfnPrintf(pHlp, " GCMD_REG = %#RX32\n", uGcmdReg);
3670	{
3671	uint8_t const fCfi = RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_CFI);
3672	pHlp->pfnPrintf(pHlp, " CFI = %u (%s)\n", fCfi, fCfi ? "Passthrough" : "Blocked");
3673	pHlp->pfnPrintf(pHlp, " SIRTP = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_SIRTP));
3674	pHlp->pfnPrintf(pHlp, " IRE = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_IRE));
3675	pHlp->pfnPrintf(pHlp, " QIE = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_QIE));
3676	pHlp->pfnPrintf(pHlp, " WBF = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_WBF));
3677	pHlp->pfnPrintf(pHlp, " EAFL = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_SFL));
3678	pHlp->pfnPrintf(pHlp, " SFL = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_SFL));
3679	pHlp->pfnPrintf(pHlp, " SRTP = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_SRTP));
3680	pHlp->pfnPrintf(pHlp, " TE = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_TE));
3681	}
3682	pHlp->pfnPrintf(pHlp, " GSTS_REG = %#RX32\n", uGstsReg);
3683	{
3684	uint8_t const fCfis = RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_CFIS);
3685	pHlp->pfnPrintf(pHlp, " CFIS = %u (%s)\n", fCfis, fCfis ? "Passthrough" : "Blocked");
3686	pHlp->pfnPrintf(pHlp, " IRTPS = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_IRTPS));
3687	pHlp->pfnPrintf(pHlp, " IRES = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_IRES));
3688	pHlp->pfnPrintf(pHlp, " QIES = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_QIES));
3689	pHlp->pfnPrintf(pHlp, " WBFS = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_WBFS));
3690	pHlp->pfnPrintf(pHlp, " AFLS = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_AFLS));
3691	pHlp->pfnPrintf(pHlp, " FLS = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_FLS));
3692	pHlp->pfnPrintf(pHlp, " RTPS = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_RTPS));
3693	pHlp->pfnPrintf(pHlp, " TES = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_TES));
3694	}
3695	pHlp->pfnPrintf(pHlp, " RTADDR_REG = %#RX64\n", uRtaddrReg);
3696	{
3697	uint8_t const uTtm = RT_BF_GET(uRtaddrReg, VTD_BF_RTADDR_REG_TTM);
3698	pHlp->pfnPrintf(pHlp, " RTA = %#RX64\n", uRtaddrReg & VTD_BF_RTADDR_REG_RTA_MASK);
3699	pHlp->pfnPrintf(pHlp, " TTM = %u (%s)\n", uTtm, vtdRtaddrRegGetTtmDesc(uTtm));
3700	}
3701	pHlp->pfnPrintf(pHlp, " CCMD_REG = %#RX64\n", uCcmdReg);
3702	pHlp->pfnPrintf(pHlp, " FSTS_REG = %#RX32\n", uFstsReg);
3703	{
3704	pHlp->pfnPrintf(pHlp, " PFO = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_PFO));
3705	pHlp->pfnPrintf(pHlp, " PPF = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_PPF));
3706	pHlp->pfnPrintf(pHlp, " AFO = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_AFO));
3707	pHlp->pfnPrintf(pHlp, " APF = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_APF));
3708	pHlp->pfnPrintf(pHlp, " IQE = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_IQE));
3709	pHlp->pfnPrintf(pHlp, " ICS = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_ICE));
3710	pHlp->pfnPrintf(pHlp, " ITE = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_ITE));
3711	pHlp->pfnPrintf(pHlp, " FRI = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_FRI));
3712	}
3713	pHlp->pfnPrintf(pHlp, " FECTL_REG = %#RX32\n", uFectlReg);
3714	{
3715	pHlp->pfnPrintf(pHlp, " IM = %RTbool\n", RT_BF_GET(uFectlReg, VTD_BF_FECTL_REG_IM));
3716	pHlp->pfnPrintf(pHlp, " IP = %RTbool\n", RT_BF_GET(uFectlReg, VTD_BF_FECTL_REG_IP));
3717	}
3718	pHlp->pfnPrintf(pHlp, " FEDATA_REG = %#RX32\n", uFedataReg);
3719	pHlp->pfnPrintf(pHlp, " FEADDR_REG = %#RX32\n", uFeaddrReg);
3720	pHlp->pfnPrintf(pHlp, " FEUADDR_REG = %#RX32\n", uFeuaddrReg);
3721	pHlp->pfnPrintf(pHlp, " AFLOG_REG = %#RX64\n", uAflogReg);
3722	pHlp->pfnPrintf(pHlp, " PMEN_REG = %#RX32\n", uPmenReg);
3723	pHlp->pfnPrintf(pHlp, " PLMBASE_REG = %#RX32\n", uPlmbaseReg);
3724	pHlp->pfnPrintf(pHlp, " PLMLIMIT_REG = %#RX32\n", uPlmlimitReg);
3725	pHlp->pfnPrintf(pHlp, " PHMBASE_REG = %#RX64\n", uPhmbaseReg);
3726	pHlp->pfnPrintf(pHlp, " PHMLIMIT_REG = %#RX64\n", uPhmlimitReg);
3727	pHlp->pfnPrintf(pHlp, " IQH_REG = %#RX64\n", uIqhReg);
3728	pHlp->pfnPrintf(pHlp, " IQT_REG = %#RX64\n", uIqtReg);
3729	pHlp->pfnPrintf(pHlp, " IQA_REG = %#RX64\n", uIqaReg);
3730	{
3731	uint8_t const fDw = RT_BF_GET(uIqaReg, VTD_BF_IQA_REG_DW);
3732	uint8_t const fQs = RT_BF_GET(uIqaReg, VTD_BF_IQA_REG_QS);
3733	uint8_t const cQueuePages = 1 << fQs;
3734	pHlp->pfnPrintf(pHlp, " DW = %u (%s)\n", fDw, fDw == VTD_IQA_REG_DW_128_BIT ? "128-bit" : "256-bit");
3735	pHlp->pfnPrintf(pHlp, " QS = %u (%u page%s)\n", fQs, cQueuePages, cQueuePages > 1 ? "s" : "");
3736	}
3737	pHlp->pfnPrintf(pHlp, " ICS_REG = %#RX32\n", uIcsReg);
3738	{
3739	pHlp->pfnPrintf(pHlp, " IWC = %u\n", RT_BF_GET(uIcsReg, VTD_BF_ICS_REG_IWC));
3740	}
3741	pHlp->pfnPrintf(pHlp, " IECTL_REG = %#RX32\n", uIectlReg);
3742	{
3743	pHlp->pfnPrintf(pHlp, " IM = %RTbool\n", RT_BF_GET(uIectlReg, VTD_BF_IECTL_REG_IM));
3744	pHlp->pfnPrintf(pHlp, " IP = %RTbool\n", RT_BF_GET(uIectlReg, VTD_BF_IECTL_REG_IP));
3745	}
3746	pHlp->pfnPrintf(pHlp, " IEDATA_REG = %#RX32\n", uIedataReg);
3747	pHlp->pfnPrintf(pHlp, " IEADDR_REG = %#RX32\n", uIeaddrReg);
3748	pHlp->pfnPrintf(pHlp, " IEUADDR_REG = %#RX32\n", uIeuaddrReg);
3749	pHlp->pfnPrintf(pHlp, " IQERCD_REG = %#RX64\n", uIqercdReg);
3750	{
3751	pHlp->pfnPrintf(pHlp, " ICESID = %#RX32\n", RT_BF_GET(uIqercdReg, VTD_BF_IQERCD_REG_ICESID));
3752	pHlp->pfnPrintf(pHlp, " ITESID = %#RX32\n", RT_BF_GET(uIqercdReg, VTD_BF_IQERCD_REG_ITESID));
3753	pHlp->pfnPrintf(pHlp, " IQEI = %#RX32\n", RT_BF_GET(uIqercdReg, VTD_BF_IQERCD_REG_IQEI));
3754	}
3755	pHlp->pfnPrintf(pHlp, " IRTA_REG = %#RX64\n", uIrtaReg);
3756	{
3757	uint32_t const cIrtEntries = VTD_IRTA_REG_GET_ENTRY_COUNT(uIrtaReg);
3758	uint32_t const cbIrt = sizeof(VTD_IRTE_T) * cIrtEntries;
3759	pHlp->pfnPrintf(pHlp, " IRTA = %#RX64\n", uIrtaReg & VTD_BF_IRTA_REG_IRTA_MASK);
3760	pHlp->pfnPrintf(pHlp, " EIME = %RTbool\n", RT_BF_GET(uIrtaReg, VTD_BF_IRTA_REG_EIME));
3761	pHlp->pfnPrintf(pHlp, " S = %u entries (%u bytes)\n", cIrtEntries, cbIrt);
3762	}
3763	pHlp->pfnPrintf(pHlp, " PQH_REG = %#RX64\n", uPqhReg);
3764	pHlp->pfnPrintf(pHlp, " PQT_REG = %#RX64\n", uPqtReg);
3765	pHlp->pfnPrintf(pHlp, " PQA_REG = %#RX64\n", uPqaReg);
3766	pHlp->pfnPrintf(pHlp, " PRS_REG = %#RX32\n", uPrsReg);
3767	pHlp->pfnPrintf(pHlp, " PECTL_REG = %#RX32\n", uPectlReg);
3768	pHlp->pfnPrintf(pHlp, " PEDATA_REG = %#RX32\n", uPedataReg);
3769	pHlp->pfnPrintf(pHlp, " PEADDR_REG = %#RX32\n", uPeaddrReg);
3770	pHlp->pfnPrintf(pHlp, " PEUADDR_REG = %#RX32\n", uPeuaddrReg);
3771	pHlp->pfnPrintf(pHlp, " MTRRCAP_REG = %#RX64\n", uMtrrcapReg);
3772	pHlp->pfnPrintf(pHlp, " MTRRDEF_REG = %#RX64\n", uMtrrdefReg);
3773	pHlp->pfnPrintf(pHlp, "\n");
3774	}
3775
3776
3777	/**
3778	* Initializes all registers in the DMAR unit.
3779	*
3780	* @param pDevIns The IOMMU device instance.
3781	*/
3782	static void dmarR3RegsInit(PPDMDEVINS pDevIns)
3783	{
3784	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
3785	LogFlowFunc(("\n"));
3786
3787	/*
3788	* Wipe all registers (required on reset).
3789	*/
3790	RT_ZERO(pThis->abRegs0);
3791	RT_ZERO(pThis->abRegs1);
3792
3793	/*
3794	* Initialize registers not mutable by software prior to initializing other registers.
3795	*/
3796	/* VER_REG */
3797	{
3798	pThis->uVerReg = RT_BF_MAKE(VTD_BF_VER_REG_MIN, DMAR_VER_MINOR)
3799	\| RT_BF_MAKE(VTD_BF_VER_REG_MAX, DMAR_VER_MAJOR);
3800	dmarRegWriteRaw64(pThis, VTD_MMIO_OFF_VER_REG, pThis->uVerReg);
3801	}
3802
3803	uint8_t const fFlts = 0; /* First-level translation support. */
3804	uint8_t const fSlts = 1; /* Second-level translation support. */
3805	uint8_t const fPt = 1; /* Pass-Through support. */
3806	uint8_t const fSmts = fFlts & fSlts & fPt; /* Scalable mode translation support.*/
3807	uint8_t const fNest = 0; /* Nested translation support. */
3808
3809	/* CAP_REG */
3810	{
3811	uint8_t cGstPhysAddrBits;
3812	uint8_t cGstLinearAddrBits;
3813	PDMDevHlpCpuGetGuestAddrWidths(pDevIns, &cGstPhysAddrBits, &cGstLinearAddrBits);
3814
3815	uint8_t const fFl1gp = 1; /* First-level 1GB pages support. */
3816	uint8_t const fFl5lp = 1; /* First-level 5-level paging support (PML5E). */
3817	uint8_t const fSl2mp = 1; /* Second-level 2MB pages support. */
3818	uint8_t const fSl2gp = fSl2mp & 1; /* Second-level 1GB pages support. */
3819	uint8_t const fSllps = fSl2mp \| (fSl2gp << 1); /* Second-level large page support. */
3820	uint8_t const fMamv = (fSl2gp ? X86_PAGE_1G_SHIFT /* Maximum address mask value (for 2nd-level invalidations). */
3821	: X86_PAGE_2M_SHIFT)
3822	- X86_PAGE_4K_SHIFT;
3823	uint8_t const fNd = DMAR_ND; /* Number of domains supported. */
3824	uint8_t const fPsi = 1; /* Page selective invalidation. */
3825	uint8_t const uMgaw = cGstPhysAddrBits - 1; /* Maximum guest address width. */
3826	uint8_t const fSagaw = vtdCapRegGetSagaw(uMgaw); /* Supported adjust guest address width. */
3827	uint16_t const offFro = DMAR_MMIO_OFF_FRCD_LO_REG >> 4; /* MMIO offset of FRCD registers. */
3828	uint8_t const fEsrtps = 1; /* Enhanced SRTPS (auto invalidate cache on SRTP). */
3829	uint8_t const fEsirtps = 1; /* Enhanced SIRTPS (auto invalidate cache on SIRTP). */
3830
3831	pThis->fCapReg = RT_BF_MAKE(VTD_BF_CAP_REG_ND, fNd)
3832	\| RT_BF_MAKE(VTD_BF_CAP_REG_AFL, 0) /* Advanced fault logging not supported. */
3833	\| RT_BF_MAKE(VTD_BF_CAP_REG_RWBF, 0) /* Software need not flush write-buffers. */
3834	\| RT_BF_MAKE(VTD_BF_CAP_REG_PLMR, 0) /* Protected Low-Memory Region not supported. */
3835	\| RT_BF_MAKE(VTD_BF_CAP_REG_PHMR, 0) /* Protected High-Memory Region not supported. */
3836	\| RT_BF_MAKE(VTD_BF_CAP_REG_CM, 1) /* Software should invalidate on mapping structure changes. */
3837	\| RT_BF_MAKE(VTD_BF_CAP_REG_SAGAW, fSlts ? fSagaw : 0)
3838	\| RT_BF_MAKE(VTD_BF_CAP_REG_MGAW, uMgaw)
3839	\| RT_BF_MAKE(VTD_BF_CAP_REG_ZLR, 1) /** @todo Figure out if/how to support zero-length reads. */
3840	\| RT_BF_MAKE(VTD_BF_CAP_REG_FRO, offFro)
3841	\| RT_BF_MAKE(VTD_BF_CAP_REG_SLLPS, fSlts & fSllps)
3842	\| RT_BF_MAKE(VTD_BF_CAP_REG_PSI, fPsi)
3843	\| RT_BF_MAKE(VTD_BF_CAP_REG_NFR, DMAR_FRCD_REG_COUNT - 1)
3844	\| RT_BF_MAKE(VTD_BF_CAP_REG_MAMV, fPsi & fMamv)
3845	\| RT_BF_MAKE(VTD_BF_CAP_REG_DWD, 1)
3846	\| RT_BF_MAKE(VTD_BF_CAP_REG_DRD, 1)
3847	\| RT_BF_MAKE(VTD_BF_CAP_REG_FL1GP, fFlts & fFl1gp)
3848	\| RT_BF_MAKE(VTD_BF_CAP_REG_PI, 0) /* Posted Interrupts not supported. */
3849	\| RT_BF_MAKE(VTD_BF_CAP_REG_FL5LP, fFlts & fFl5lp)
3850	\| RT_BF_MAKE(VTD_BF_CAP_REG_ESIRTPS, fEsirtps)
3851	\| RT_BF_MAKE(VTD_BF_CAP_REG_ESRTPS, fEsrtps);
3852	dmarRegWriteRaw64(pThis, VTD_MMIO_OFF_CAP_REG, pThis->fCapReg);
3853
3854	AssertCompile(fNd <= RT_ELEMENTS(g_auNdMask));
3855	pThis->fHawBaseMask = ~(UINT64_MAX << cGstPhysAddrBits) & X86_PAGE_4K_BASE_MASK;
3856	pThis->fMgawInvMask = UINT64_MAX << cGstPhysAddrBits;
3857	pThis->cMaxPagingLevel = vtdCapRegGetMaxPagingLevel(fSagaw);
3858	pThis->fCtxEntryQw1ValidMask = VTD_BF_1_CONTEXT_ENTRY_AW_MASK
3859	\| VTD_BF_1_CONTEXT_ENTRY_IGN_6_3_MASK
3860	\| RT_BF_MAKE(VTD_BF_1_CONTEXT_ENTRY_DID, g_auNdMask[fNd]);
3861	}
3862
3863	/* ECAP_REG */
3864	{
3865	uint8_t const fQi = 1; /* Queued-invalidations. */
3866	uint8_t const fIr = !!(DMAR_ACPI_DMAR_FLAGS & ACPI_DMAR_F_INTR_REMAP); /* Interrupt remapping support. */
3867	uint8_t const fMhmv = 0xf; /* Maximum handle mask value. */
3868	uint16_t const offIro = DMAR_MMIO_OFF_IVA_REG >> 4; /* MMIO offset of IOTLB registers. */
3869	uint8_t const fEim = 1; /* Extended interrupt mode.*/
3870	uint8_t const fAdms = 1; /* Abort DMA mode support. */
3871	uint8_t const fErs = 0; /* Execute Request (not supported). */
3872
3873	pThis->fExtCapReg = RT_BF_MAKE(VTD_BF_ECAP_REG_C, 0) /* Accesses don't snoop CPU cache. */
3874	\| RT_BF_MAKE(VTD_BF_ECAP_REG_QI, fQi)
3875	\| RT_BF_MAKE(VTD_BF_ECAP_REG_DT, 0) /* Device-TLBs not supported. */
3876	\| RT_BF_MAKE(VTD_BF_ECAP_REG_IR, fQi & fIr)
3877	\| RT_BF_MAKE(VTD_BF_ECAP_REG_EIM, fIr & fEim)
3878	\| RT_BF_MAKE(VTD_BF_ECAP_REG_PT, fPt)
3879	\| RT_BF_MAKE(VTD_BF_ECAP_REG_SC, 0) /* Snoop control not supported. */
3880	\| RT_BF_MAKE(VTD_BF_ECAP_REG_IRO, offIro)
3881	\| RT_BF_MAKE(VTD_BF_ECAP_REG_MHMV, fIr & fMhmv)
3882	\| RT_BF_MAKE(VTD_BF_ECAP_REG_MTS, 0) /* Memory type not supported. */
3883	\| RT_BF_MAKE(VTD_BF_ECAP_REG_NEST, fNest)
3884	\| RT_BF_MAKE(VTD_BF_ECAP_REG_PRS, 0) /* 0 as DT not supported. */
3885	\| RT_BF_MAKE(VTD_BF_ECAP_REG_ERS, fErs)
3886	\| RT_BF_MAKE(VTD_BF_ECAP_REG_SRS, 0) /* Supervisor request not supported. */
3887	\| RT_BF_MAKE(VTD_BF_ECAP_REG_NWFS, 0) /* 0 as DT not supported. */
3888	\| RT_BF_MAKE(VTD_BF_ECAP_REG_EAFS, 0) /* 0 as SMPWCS not supported. */
3889	\| RT_BF_MAKE(VTD_BF_ECAP_REG_PSS, 0) /* 0 as PASID not supported. */
3890	\| RT_BF_MAKE(VTD_BF_ECAP_REG_PASID, 0) /* PASID not supported. */
3891	\| RT_BF_MAKE(VTD_BF_ECAP_REG_DIT, 0) /* 0 as DT not supported. */
3892	\| RT_BF_MAKE(VTD_BF_ECAP_REG_PDS, 0) /* 0 as DT not supported. */
3893	\| RT_BF_MAKE(VTD_BF_ECAP_REG_SMTS, fSmts)
3894	\| RT_BF_MAKE(VTD_BF_ECAP_REG_VCS, 0) /* 0 as PASID not supported (commands seem PASID specific). */
3895	\| RT_BF_MAKE(VTD_BF_ECAP_REG_SLADS, 0) /* Second-level accessed/dirty not supported. */
3896	\| RT_BF_MAKE(VTD_BF_ECAP_REG_SLTS, fSlts)
3897	\| RT_BF_MAKE(VTD_BF_ECAP_REG_FLTS, fFlts)
3898	\| RT_BF_MAKE(VTD_BF_ECAP_REG_SMPWCS, 0) /* 0 as PASID not supported. */
3899	\| RT_BF_MAKE(VTD_BF_ECAP_REG_RPS, 0) /* We don't support RID_PASID field in SM context entry. */
3900	\| RT_BF_MAKE(VTD_BF_ECAP_REG_ADMS, fAdms)
3901	\| RT_BF_MAKE(VTD_BF_ECAP_REG_RPRIVS, 0); /* 0 as SRS not supported. */
3902	dmarRegWriteRaw64(pThis, VTD_MMIO_OFF_ECAP_REG, pThis->fExtCapReg);
3903
3904	pThis->fPermValidMask = DMAR_PERM_READ \| DMAR_PERM_WRITE;
3905	if (fErs)
3906	pThis->fPermValidMask = DMAR_PERM_EXE;
3907	}
3908
3909	/*
3910	* Initialize registers mutable by software.
3911	*/
3912	/* FECTL_REG */
3913	{
3914	uint32_t const uCtl = RT_BF_MAKE(VTD_BF_FECTL_REG_IM, 1);
3915	dmarRegWriteRaw32(pThis, VTD_MMIO_OFF_FECTL_REG, uCtl);
3916	}
3917
3918	/* ICETL_REG */
3919	{
3920	uint32_t const uCtl = RT_BF_MAKE(VTD_BF_IECTL_REG_IM, 1);
3921	dmarRegWriteRaw32(pThis, VTD_MMIO_OFF_IECTL_REG, uCtl);
3922	}
3923
3924	#ifdef VBOX_STRICT
3925	Assert(!RT_BF_GET(pThis->fExtCapReg, VTD_BF_ECAP_REG_PRS)); /* PECTL_REG - Reserved if don't support PRS. */
3926	Assert(!RT_BF_GET(pThis->fExtCapReg, VTD_BF_ECAP_REG_MTS)); /* MTRRCAP_REG - Reserved if we don't support MTS. */
3927	#endif
3928	}
3929
3930
3931	/**
3932	* @callback_method_impl{FNSSMDEVSAVEEXEC}
3933	*/
3934	static DECLCALLBACK(int) dmarR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
3935	{
3936	PCDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PCDMAR);
3937	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
3938	LogFlowFunc(("\n"));
3939
3940	/* First, save software-immutable registers that we validate on state load. */
3941	pHlp->pfnSSMPutU32(pSSM, pThis->uVerReg);
3942	pHlp->pfnSSMPutU64(pSSM, pThis->fCapReg);
3943	pHlp->pfnSSMPutU64(pSSM, pThis->fExtCapReg);
3944
3945	/* Save MMIO registers. */
3946	pHlp->pfnSSMPutU32(pSSM, DMAR_MMIO_GROUP_COUNT);
3947	pHlp->pfnSSMPutU32(pSSM, sizeof(pThis->abRegs0));
3948	pHlp->pfnSSMPutMem(pSSM, &pThis->abRegs0[0], sizeof(pThis->abRegs0));
3949	pHlp->pfnSSMPutU32(pSSM, sizeof(pThis->abRegs1));
3950	pHlp->pfnSSMPutMem(pSSM, &pThis->abRegs1[0], sizeof(pThis->abRegs1));
3951
3952	/*
3953	* Save our implemention-defined MMIO registers offsets.
3954	* The register themselves are currently all part of group 1 (saved above).
3955	* We save these to ensure they're located where the code expects them while loading state.
3956	*/
3957	pHlp->pfnSSMPutU16(pSSM, DMAR_MMIO_OFF_IMPL_COUNT);
3958	AssertCompile(DMAR_MMIO_OFF_IMPL_COUNT == 2);
3959	pHlp->pfnSSMPutU16(pSSM, DMAR_MMIO_OFF_IVA_REG);
3960	pHlp->pfnSSMPutU16(pSSM, DMAR_MMIO_OFF_FRCD_LO_REG);
3961
3962	/* Save lazily activated registers. */
3963	pHlp->pfnSSMPutU64(pSSM, pThis->uIrtaReg);
3964	pHlp->pfnSSMPutU64(pSSM, pThis->uRtaddrReg);
3965
3966	/* Save terminator marker and return status. */
3967	return pHlp->pfnSSMPutU32(pSSM, UINT32_MAX);
3968	}
3969
3970
3971	/**
3972	* @callback_method_impl{FNSSMDEVLOADEXEC}
3973	*/
3974	static DECLCALLBACK(int) dmarR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
3975	{
3976	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
3977	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
3978	int const rcDataErr = VERR_SSM_UNEXPECTED_DATA;
3979	int const rcFmtErr = VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
3980	LogFlowFunc(("\n"));
3981
3982	/*
3983	* Validate saved-state version.
3984	*/
3985	AssertReturn(uPass == SSM_PASS_FINAL, VERR_WRONG_ORDER);
3986	if (uVersion != DMAR_SAVED_STATE_VERSION)
3987	{
3988	LogRel(("%s: Invalid saved-state version %#x\n", DMAR_LOG_PFX, uVersion));
3989	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
3990	}
3991
3992	/*
3993	* Load and validate software-immutable registers.
3994	* The features we had exposed to the guest (in the saved state) must be identical
3995	* to what is currently emulated.
3996	*/
3997	{
3998	/* VER_REG */
3999	uint32_t uVerReg = 0;
4000	int rc = pHlp->pfnSSMGetU32(pSSM, &uVerReg);
4001	AssertRCReturn(rc, rc);
4002	AssertLogRelMsgReturn(uVerReg == pThis->uVerReg,
4003	("%s: VER_REG mismatch (expected %#RX32 got %#RX32)\n", DMAR_LOG_PFX, pThis->uVerReg, uVerReg),
4004	rcDataErr);
4005	/* CAP_REG */
4006	uint64_t fCapReg = 0;
4007	pHlp->pfnSSMGetU64(pSSM, &fCapReg);
4008	AssertLogRelMsgReturn(fCapReg == pThis->fCapReg,
4009	("%s: CAP_REG mismatch (expected %#RX64 got %#RX64)\n", DMAR_LOG_PFX, pThis->fCapReg, fCapReg),
4010	rcDataErr);
4011	/* ECAP_REG */
4012	uint64_t fExtCapReg = 0;
4013	pHlp->pfnSSMGetU64(pSSM, &fExtCapReg);
4014	AssertLogRelMsgReturn(fExtCapReg == pThis->fExtCapReg,
4015	("%s: ECAP_REG mismatch (expected %#RX64 got %#RX64)\n", DMAR_LOG_PFX, pThis->fExtCapReg,
4016	fExtCapReg), rcDataErr);
4017	}
4018
4019	/*
4020	* Load MMIO registers.
4021	*/
4022	{
4023	/* Group count. */
4024	uint32_t cRegGroups = 0;
4025	pHlp->pfnSSMGetU32(pSSM, &cRegGroups);
4026	AssertLogRelMsgReturn(cRegGroups == DMAR_MMIO_GROUP_COUNT,
4027	("%s: MMIO group count mismatch (expected %u got %u)\n", DMAR_LOG_PFX, DMAR_MMIO_GROUP_COUNT,
4028	cRegGroups), rcFmtErr);
4029	/* Group 0. */
4030	uint32_t cbRegs0 = 0;
4031	pHlp->pfnSSMGetU32(pSSM, &cbRegs0);
4032	AssertLogRelMsgReturn(cbRegs0 == sizeof(pThis->abRegs0),
4033	("%s: MMIO group 0 size mismatch (expected %u got %u)\n", DMAR_LOG_PFX, sizeof(pThis->abRegs0),
4034	cbRegs0), rcFmtErr);
4035	pHlp->pfnSSMGetMem(pSSM, &pThis->abRegs0[0], cbRegs0);
4036	/* Group 1. */
4037	uint32_t cbRegs1 = 0;
4038	pHlp->pfnSSMGetU32(pSSM, &cbRegs1);
4039	AssertLogRelMsgReturn(cbRegs1 == sizeof(pThis->abRegs1),
4040	("%s: MMIO group 1 size mismatch (expected %u got %u)\n", DMAR_LOG_PFX, sizeof(pThis->abRegs1),
4041	cbRegs1), rcFmtErr);
4042	pHlp->pfnSSMGetMem(pSSM, &pThis->abRegs1[0], cbRegs1);
4043	}
4044
4045	/*
4046	* Validate implementation-defined MMIO register offsets.
4047	*/
4048	{
4049	/* Offset count. */
4050	uint16_t cOffsets = 0;
4051	pHlp->pfnSSMGetU16(pSSM, &cOffsets);
4052	AssertLogRelMsgReturn(cOffsets == DMAR_MMIO_OFF_IMPL_COUNT,
4053	("%s: MMIO offset count mismatch (expected %u got %u)\n", DMAR_LOG_PFX, DMAR_MMIO_OFF_IMPL_COUNT,
4054	cOffsets), rcFmtErr);
4055	/* IVA_REG. */
4056	uint16_t offReg = 0;
4057	pHlp->pfnSSMGetU16(pSSM, &offReg);
4058	AssertLogRelMsgReturn(offReg == DMAR_MMIO_OFF_IVA_REG,
4059	("%s: IVA_REG offset mismatch (expected %u got %u)\n", DMAR_LOG_PFX, DMAR_MMIO_OFF_IVA_REG,
4060	offReg), rcFmtErr);
4061	/* IOTLB_REG. */
4062	AssertLogRelMsgReturn(offReg + 8 == DMAR_MMIO_OFF_IOTLB_REG,
4063	("%s: IOTLB_REG offset mismatch (expected %u got %u)\n", DMAR_LOG_PFX, DMAR_MMIO_OFF_IOTLB_REG,
4064	offReg), rcFmtErr);
4065	/* FRCD_LO_REG. */
4066	pHlp->pfnSSMGetU16(pSSM, &offReg);
4067	AssertLogRelMsgReturn(offReg == DMAR_MMIO_OFF_FRCD_LO_REG,
4068	("%s: FRCD_LO_REG offset mismatch (expected %u got %u)\n", DMAR_LOG_PFX, DMAR_MMIO_OFF_FRCD_LO_REG,
4069	offReg), rcFmtErr);
4070	/* FRCD_HI_REG. */
4071	AssertLogRelMsgReturn(offReg + 8 == DMAR_MMIO_OFF_FRCD_HI_REG,
4072	("%s: FRCD_HI_REG offset mismatch (expected %u got %u)\n", DMAR_LOG_PFX, DMAR_MMIO_OFF_FRCD_HI_REG,
4073	offReg), rcFmtErr);
4074	}
4075
4076	/*
4077	* Load lazily activated registers.
4078	*/
4079	{
4080	/* Active IRTA_REG. */
4081	pHlp->pfnSSMGetU64(pSSM, &pThis->uIrtaReg);
4082	AssertLogRelMsgReturn(!(pThis->uIrtaReg & ~VTD_IRTA_REG_RW_MASK),
4083	("%s: IRTA_REG reserved bits set %#RX64\n", DMAR_LOG_PFX, pThis->uIrtaReg), rcDataErr);
4084	/* Active RTADDR_REG. */
4085	pHlp->pfnSSMGetU64(pSSM, &pThis->uRtaddrReg);
4086	AssertLogRelMsgReturn(!(pThis->uRtaddrReg & ~VTD_RTADDR_REG_RW_MASK),
4087	("%s: RTADDR_REG reserved bits set %#RX64\n", DMAR_LOG_PFX, pThis->uRtaddrReg), rcDataErr);
4088	}
4089
4090	/*
4091	* Verify terminator marker.
4092	*/
4093	{
4094	uint32_t uEndMarker = 0;
4095	int const rc = pHlp->pfnSSMGetU32(pSSM, &uEndMarker);
4096	AssertRCReturn(rc, rc);
4097	AssertLogRelMsgReturn(uEndMarker == UINT32_MAX,
4098	("%s: End marker mismatch (expected %#RX32 got %#RX32)\n", DMAR_LOG_PFX, UINT32_MAX, uEndMarker),
4099	rcFmtErr);
4100	}
4101	return VINF_SUCCESS;
4102	}
4103
4104
4105	/**
4106	* @callback_method_impl{FNSSMDEVLOADDONE}
4107	*/
4108	static DECLCALLBACK(int) dmarR3LoadDone(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
4109	{
4110	PDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PDMARR3);
4111	LogFlowFunc(("\n"));
4112	RT_NOREF(pSSM);
4113	AssertPtrReturn(pThisR3, VERR_INVALID_POINTER);
4114
4115	DMAR_LOCK(pDevIns, pThisR3);
4116	dmarInvQueueThreadWakeUpIfNeeded(pDevIns);
4117	DMAR_UNLOCK(pDevIns, pThisR3);
4118	return VINF_SUCCESS;
4119	}
4120
4121
4122	/**
4123	* @interface_method_impl{PDMDEVREG,pfnReset}
4124	*/
4125	static DECLCALLBACK(void) iommuIntelR3Reset(PPDMDEVINS pDevIns)
4126	{
4127	PCDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARR3);
4128	LogFlowFunc(("\n"));
4129
4130	DMAR_LOCK(pDevIns, pThisR3);
4131	dmarR3RegsInit(pDevIns);
4132	DMAR_UNLOCK(pDevIns, pThisR3);
4133	}
4134
4135
4136	/**
4137	* @interface_method_impl{PDMDEVREG,pfnDestruct}
4138	*/
4139	static DECLCALLBACK(int) iommuIntelR3Destruct(PPDMDEVINS pDevIns)
4140	{
4141	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
4142	PCDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARR3);
4143	LogFlowFunc(("\n"));
4144
4145	DMAR_LOCK(pDevIns, pThisR3);
4146
4147	if (pThis->hEvtInvQueue != NIL_SUPSEMEVENT)
4148	{
4149	PDMDevHlpSUPSemEventClose(pDevIns, pThis->hEvtInvQueue);
4150	pThis->hEvtInvQueue = NIL_SUPSEMEVENT;
4151	}
4152
4153	DMAR_UNLOCK(pDevIns, pThisR3);
4154	return VINF_SUCCESS;
4155	}
4156
4157
4158	/**
4159	* @interface_method_impl{PDMDEVREG,pfnConstruct}
4160	*/
4161	static DECLCALLBACK(int) iommuIntelR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
4162	{
4163	RT_NOREF(pCfg);
4164
4165	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
4166	PDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PDMARR3);
4167	pThisR3->pDevInsR3 = pDevIns;
4168
4169	LogFlowFunc(("iInstance=%d\n", iInstance));
4170	NOREF(iInstance);
4171
4172	/*
4173	* Register the IOMMU with PDM.
4174	*/
4175	PDMIOMMUREGR3 IommuReg;
4176	RT_ZERO(IommuReg);
4177	IommuReg.u32Version = PDM_IOMMUREGCC_VERSION;
4178	IommuReg.pfnMemAccess = iommuIntelMemAccess;
4179	IommuReg.pfnMemBulkAccess = iommuIntelMemBulkAccess;
4180	IommuReg.pfnMsiRemap = iommuIntelMsiRemap;
4181	IommuReg.u32TheEnd = PDM_IOMMUREGCC_VERSION;
4182	int rc = PDMDevHlpIommuRegister(pDevIns, &IommuReg, &pThisR3->CTX_SUFF(pIommuHlp), &pThis->idxIommu);
4183	if (RT_FAILURE(rc))
4184	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to register ourselves as an IOMMU device"));
4185	if (pThisR3->CTX_SUFF(pIommuHlp)->u32Version != PDM_IOMMUHLPR3_VERSION)
4186	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
4187	N_("IOMMU helper version mismatch; got %#x expected %#x"),
4188	pThisR3->CTX_SUFF(pIommuHlp)->u32Version, PDM_IOMMUHLPR3_VERSION);
4189	if (pThisR3->CTX_SUFF(pIommuHlp)->u32TheEnd != PDM_IOMMUHLPR3_VERSION)
4190	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
4191	N_("IOMMU helper end-version mismatch; got %#x expected %#x"),
4192	pThisR3->CTX_SUFF(pIommuHlp)->u32TheEnd, PDM_IOMMUHLPR3_VERSION);
4193	AssertPtr(pThisR3->pIommuHlpR3->pfnLock);
4194	AssertPtr(pThisR3->pIommuHlpR3->pfnUnlock);
4195	AssertPtr(pThisR3->pIommuHlpR3->pfnLockIsOwner);
4196	AssertPtr(pThisR3->pIommuHlpR3->pfnSendMsi);
4197
4198	/*
4199	* Use PDM's critical section (via helpers) for the IOMMU device.
4200	*/
4201	rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
4202	AssertRCReturn(rc, rc);
4203
4204	/*
4205	* Initialize PCI configuration registers.
4206	*/
4207	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
4208	PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
4209
4210	/* Header. */
4211	PDMPciDevSetVendorId(pPciDev, DMAR_PCI_VENDOR_ID); /* Intel */
4212	PDMPciDevSetDeviceId(pPciDev, DMAR_PCI_DEVICE_ID); /* VirtualBox DMAR device */
4213	PDMPciDevSetRevisionId(pPciDev, DMAR_PCI_REVISION_ID); /* VirtualBox specific device implementation revision */
4214	PDMPciDevSetClassBase(pPciDev, VBOX_PCI_CLASS_SYSTEM); /* System Base Peripheral */
4215	PDMPciDevSetClassSub(pPciDev, VBOX_PCI_SUB_SYSTEM_OTHER); /* Other */
4216	PDMPciDevSetHeaderType(pPciDev, 0); /* Single function, type 0 */
4217	PDMPciDevSetSubSystemId(pPciDev, DMAR_PCI_DEVICE_ID); /* VirtualBox DMAR device */
4218	PDMPciDevSetSubSystemVendorId(pPciDev, DMAR_PCI_VENDOR_ID); /* Intel */
4219
4220	/** @todo Chipset spec says PCI Express Capability Id. Relevant for us? */
4221	PDMPciDevSetStatus(pPciDev, 0);
4222	PDMPciDevSetCapabilityList(pPciDev, 0);
4223	/** @todo VTBAR at 0x180? */
4224
4225	/*
4226	* Register the PCI function with PDM.
4227	*/
4228	rc = PDMDevHlpPCIRegister(pDevIns, pPciDev);
4229	AssertLogRelRCReturn(rc, rc);
4230
4231	/*
4232	* Register MMIO region.
4233	*/
4234	AssertCompile(!(DMAR_MMIO_BASE_PHYSADDR & X86_PAGE_4K_OFFSET_MASK));
4235	rc = PDMDevHlpMmioCreateAndMap(pDevIns, DMAR_MMIO_BASE_PHYSADDR, DMAR_MMIO_SIZE, dmarMmioWrite, dmarMmioRead,
4236	IOMMMIO_FLAGS_READ_DWORD_QWORD \| IOMMMIO_FLAGS_WRITE_DWORD_QWORD_ZEROED, "Intel-IOMMU",
4237	&pThis->hMmio);
4238	AssertLogRelRCReturn(rc, rc);
4239
4240	/*
4241	* Register saved state handlers.
4242	*/
4243	rc = PDMDevHlpSSMRegisterEx(pDevIns, DMAR_SAVED_STATE_VERSION, sizeof(DMAR), NULL /* pszBefore */,
4244	NULL /* pfnLivePrep /, NULL / pfnLiveExec /, NULL / pfnLiveVote */,
4245	NULL /* pfnSavePrep /, dmarR3SaveExec, NULL / pfnSaveDone */,
4246	NULL /* pfnLoadPrep */, dmarR3LoadExec, dmarR3LoadDone);
4247	AssertLogRelRCReturn(rc, rc);
4248
4249	/*
4250	* Register debugger info items.
4251	*/
4252	rc = PDMDevHlpDBGFInfoRegister(pDevIns, "iommu", "Display IOMMU state.", dmarR3DbgInfo);
4253	AssertLogRelRCReturn(rc, rc);
4254
4255	#ifdef VBOX_WITH_STATISTICS
4256	/*
4257	* Statistics.
4258	*/
4259	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadR3, STAMTYPE_COUNTER, "R3/MmioRead", STAMUNIT_OCCURENCES, "Number of MMIO reads in R3");
4260	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadRZ, STAMTYPE_COUNTER, "RZ/MmioRead", STAMUNIT_OCCURENCES, "Number of MMIO reads in RZ.");
4261
4262	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteR3, STAMTYPE_COUNTER, "R3/MmioWrite", STAMUNIT_OCCURENCES, "Number of MMIO writes in R3.");
4263	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteRZ, STAMTYPE_COUNTER, "RZ/MmioWrite", STAMUNIT_OCCURENCES, "Number of MMIO writes in RZ.");
4264
4265	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapCfiR3, STAMTYPE_COUNTER, "R3/MsiRemapCfi", STAMUNIT_OCCURENCES, "Number of compatibility-format interrupt remap requests in R3.");
4266	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapCfiRZ, STAMTYPE_COUNTER, "RZ/MsiRemapCfi", STAMUNIT_OCCURENCES, "Number of compatibility-format interrupt remap requests in RZ.");
4267	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapRfiR3, STAMTYPE_COUNTER, "R3/MsiRemapRfi", STAMUNIT_OCCURENCES, "Number of remappable-format interrupt remap requests in R3.");
4268	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapRfiRZ, STAMTYPE_COUNTER, "RZ/MsiRemapRfi", STAMUNIT_OCCURENCES, "Number of remappable-format interrupt remap requests in RZ.");
4269
4270	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemReadR3, STAMTYPE_COUNTER, "R3/MemRead", STAMUNIT_OCCURENCES, "Number of memory read translation requests in R3.");
4271	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemReadRZ, STAMTYPE_COUNTER, "RZ/MemRead", STAMUNIT_OCCURENCES, "Number of memory read translation requests in RZ.");
4272
4273	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemWriteR3, STAMTYPE_COUNTER, "R3/MemWrite", STAMUNIT_OCCURENCES, "Number of memory write translation requests in R3.");
4274	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemWriteRZ, STAMTYPE_COUNTER, "RZ/MemWrite", STAMUNIT_OCCURENCES, "Number of memory write translation requests in RZ.");
4275
4276	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkReadR3, STAMTYPE_COUNTER, "R3/MemBulkRead", STAMUNIT_OCCURENCES, "Number of memory bulk read translation requests in R3.");
4277	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkReadRZ, STAMTYPE_COUNTER, "RZ/MemBulkRead", STAMUNIT_OCCURENCES, "Number of memory bulk read translation requests in RZ.");
4278
4279	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkWriteR3, STAMTYPE_COUNTER, "R3/MemBulkWrite", STAMUNIT_OCCURENCES, "Number of memory bulk write translation requests in R3.");
4280	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkWriteRZ, STAMTYPE_COUNTER, "RZ/MemBulkWrite", STAMUNIT_OCCURENCES, "Number of memory bulk write translation requests in RZ.");
4281
4282	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCcInvDsc, STAMTYPE_COUNTER, "R3/QI/CcInv", STAMUNIT_OCCURENCES, "Number of cc_inv_dsc processed.");
4283	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIotlbInvDsc, STAMTYPE_COUNTER, "R3/QI/IotlbInv", STAMUNIT_OCCURENCES, "Number of iotlb_inv_dsc processed.");
4284	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatDevtlbInvDsc, STAMTYPE_COUNTER, "R3/QI/DevtlbInv", STAMUNIT_OCCURENCES, "Number of dev_tlb_inv_dsc processed.");
4285	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIecInvDsc, STAMTYPE_COUNTER, "R3/QI/IecInv", STAMUNIT_OCCURENCES, "Number of iec_inv processed.");
4286	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatInvWaitDsc, STAMTYPE_COUNTER, "R3/QI/InvWait", STAMUNIT_OCCURENCES, "Number of inv_wait_dsc processed.");
4287	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatPasidIotlbInvDsc, STAMTYPE_COUNTER, "R3/QI/PasidIotlbInv", STAMUNIT_OCCURENCES, "Number of p_iotlb_inv_dsc processed.");
4288	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatPasidCacheInvDsc, STAMTYPE_COUNTER, "R3/QI/PasidCacheInv", STAMUNIT_OCCURENCES, "Number of pc_inv_dsc pprocessed.");
4289	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatPasidDevtlbInvDsc, STAMTYPE_COUNTER, "R3/QI/PasidDevtlbInv", STAMUNIT_OCCURENCES, "Number of p_dev_tlb_inv_dsc processed.");
4290	#endif
4291
4292	/*
4293	* Initialize registers.
4294	*/
4295	dmarR3RegsInit(pDevIns);
4296
4297	/*
4298	* Create invalidation-queue thread and semaphore.
4299	*/
4300	char szInvQueueThread[32];
4301	RT_ZERO(szInvQueueThread);
4302	RTStrPrintf(szInvQueueThread, sizeof(szInvQueueThread), "IOMMU-QI-%u", iInstance);
4303	rc = PDMDevHlpThreadCreate(pDevIns, &pThisR3->pInvQueueThread, pThis, dmarR3InvQueueThread, dmarR3InvQueueThreadWakeUp,
4304	0 /* cbStack */, RTTHREADTYPE_IO, szInvQueueThread);
4305	AssertLogRelRCReturn(rc, rc);
4306
4307	rc = PDMDevHlpSUPSemEventCreate(pDevIns, &pThis->hEvtInvQueue);
4308	AssertLogRelRCReturn(rc, rc);
4309
4310	/*
4311	* Log some of the features exposed to software.
4312	*/
4313	uint8_t const uVerMax = RT_BF_GET(pThis->uVerReg, VTD_BF_VER_REG_MAX);
4314	uint8_t const uVerMin = RT_BF_GET(pThis->uVerReg, VTD_BF_VER_REG_MIN);
4315	uint8_t const cMgawBits = RT_BF_GET(pThis->fCapReg, VTD_BF_CAP_REG_MGAW) + 1;
4316	uint8_t const fSagaw = RT_BF_GET(pThis->fCapReg, VTD_BF_CAP_REG_SAGAW);
4317	uint16_t const offFrcd = RT_BF_GET(pThis->fCapReg, VTD_BF_CAP_REG_FRO);
4318	uint16_t const offIva = RT_BF_GET(pThis->fExtCapReg, VTD_BF_ECAP_REG_IRO);
4319	LogRel(("%s: Mapped at %#RGp (%u-level page-table supported)\n",
4320	DMAR_LOG_PFX, DMAR_MMIO_BASE_PHYSADDR, pThis->cMaxPagingLevel));
4321	LogRel(("%s: Version=%u.%u Cap=%#RX64 ExtCap=%#RX64 Mgaw=%u bits Sagaw=%#x HawBaseMask=%#RX64 MgawInvMask=%#RX64 FRO=%#x IRO=%#x\n",
4322	DMAR_LOG_PFX, uVerMax, uVerMin, pThis->fCapReg, pThis->fExtCapReg, cMgawBits, fSagaw, pThis->fHawBaseMask,
4323	pThis->fMgawInvMask, offFrcd, offIva));
4324	return VINF_SUCCESS;
4325	}
4326
4327	#else
4328
4329	/**
4330	* @callback_method_impl{PDMDEVREGR0,pfnConstruct}
4331	*/
4332	static DECLCALLBACK(int) iommuIntelRZConstruct(PPDMDEVINS pDevIns)
4333	{
4334	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
4335	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
4336	PDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PDMARCC);
4337	pThisCC->CTX_SUFF(pDevIns) = pDevIns;
4338
4339	/* We will use PDM's critical section (via helpers) for the IOMMU device. */
4340	int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
4341	AssertRCReturn(rc, rc);
4342
4343	/* Set up the MMIO RZ handlers. */
4344	rc = PDMDevHlpMmioSetUpContext(pDevIns, pThis->hMmio, dmarMmioWrite, dmarMmioRead, NULL /* pvUser */);
4345	AssertRCReturn(rc, rc);
4346
4347	/* Set up the IOMMU RZ callbacks. */
4348	PDMIOMMUREGCC IommuReg;
4349	RT_ZERO(IommuReg);
4350	IommuReg.u32Version = PDM_IOMMUREGCC_VERSION;
4351	IommuReg.idxIommu = pThis->idxIommu;
4352	IommuReg.pfnMemAccess = iommuIntelMemAccess;
4353	IommuReg.pfnMemBulkAccess = iommuIntelMemBulkAccess;
4354	IommuReg.pfnMsiRemap = iommuIntelMsiRemap;
4355	IommuReg.u32TheEnd = PDM_IOMMUREGCC_VERSION;
4356
4357	rc = PDMDevHlpIommuSetUpContext(pDevIns, &IommuReg, &pThisCC->CTX_SUFF(pIommuHlp));
4358	AssertRCReturn(rc, rc);
4359	AssertPtrReturn(pThisCC->CTX_SUFF(pIommuHlp), VERR_IOMMU_IPE_1);
4360	AssertReturn(pThisCC->CTX_SUFF(pIommuHlp)->u32Version == CTX_MID(PDM_IOMMUHLP,_VERSION), VERR_VERSION_MISMATCH);
4361	AssertReturn(pThisCC->CTX_SUFF(pIommuHlp)->u32TheEnd == CTX_MID(PDM_IOMMUHLP,_VERSION), VERR_VERSION_MISMATCH);
4362	AssertPtr(pThisCC->CTX_SUFF(pIommuHlp)->pfnLock);
4363	AssertPtr(pThisCC->CTX_SUFF(pIommuHlp)->pfnUnlock);
4364	AssertPtr(pThisCC->CTX_SUFF(pIommuHlp)->pfnLockIsOwner);
4365	AssertPtr(pThisCC->CTX_SUFF(pIommuHlp)->pfnSendMsi);
4366
4367	return VINF_SUCCESS;
4368	}
4369
4370	#endif
4371
4372
4373	/**
4374	* The device registration structure.
4375	*/
4376	PDMDEVREG const g_DeviceIommuIntel =
4377	{
4378	/* .u32Version = */ PDM_DEVREG_VERSION,
4379	/* .uReserved0 = */ 0,
4380	/* .szName = */ "iommu-intel",
4381	/* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RZ \| PDM_DEVREG_FLAGS_NEW_STYLE,
4382	/* .fClass = */ PDM_DEVREG_CLASS_PCI_BUILTIN,
4383	/* .cMaxInstances = */ 1,
4384	/* .uSharedVersion = */ 42,
4385	/* .cbInstanceShared = */ sizeof(DMAR),
4386	/* .cbInstanceCC = */ sizeof(DMARCC),
4387	/* .cbInstanceRC = */ sizeof(DMARRC),
4388	/* .cMaxPciDevices = */ 1,
4389	/* .cMaxMsixVectors = */ 0,
4390	/* .pszDescription = */ "IOMMU (Intel)",
4391	#if defined(IN_RING3)
4392	/* .pszRCMod = */ "VBoxDDRC.rc",
4393	/* .pszR0Mod = */ "VBoxDDR0.r0",
4394	/* .pfnConstruct = */ iommuIntelR3Construct,
4395	/* .pfnDestruct = */ iommuIntelR3Destruct,
4396	/* .pfnRelocate = */ NULL,
4397	/* .pfnMemSetup = */ NULL,
4398	/* .pfnPowerOn = */ NULL,
4399	/* .pfnReset = */ iommuIntelR3Reset,
4400	/* .pfnSuspend = */ NULL,
4401	/* .pfnResume = */ NULL,
4402	/* .pfnAttach = */ NULL,
4403	/* .pfnDetach = */ NULL,
4404	/* .pfnQueryInterface = */ NULL,
4405	/* .pfnInitComplete = */ NULL,
4406	/* .pfnPowerOff = */ NULL,
4407	/* .pfnSoftReset = */ NULL,
4408	/* .pfnReserved0 = */ NULL,
4409	/* .pfnReserved1 = */ NULL,
4410	/* .pfnReserved2 = */ NULL,
4411	/* .pfnReserved3 = */ NULL,
4412	/* .pfnReserved4 = */ NULL,
4413	/* .pfnReserved5 = */ NULL,
4414	/* .pfnReserved6 = */ NULL,
4415	/* .pfnReserved7 = */ NULL,
4416	#elif defined(IN_RING0)
4417	/* .pfnEarlyConstruct = */ NULL,
4418	/* .pfnConstruct = */ iommuIntelRZConstruct,
4419	/* .pfnDestruct = */ NULL,
4420	/* .pfnFinalDestruct = */ NULL,
4421	/* .pfnRequest = */ NULL,
4422	/* .pfnReserved0 = */ NULL,
4423	/* .pfnReserved1 = */ NULL,
4424	/* .pfnReserved2 = */ NULL,
4425	/* .pfnReserved3 = */ NULL,
4426	/* .pfnReserved4 = */ NULL,
4427	/* .pfnReserved5 = */ NULL,
4428	/* .pfnReserved6 = */ NULL,
4429	/* .pfnReserved7 = */ NULL,
4430	#elif defined(IN_RC)
4431	/* .pfnConstruct = */ iommuIntelRZConstruct,
4432	/* .pfnReserved0 = */ NULL,
4433	/* .pfnReserved1 = */ NULL,
4434	/* .pfnReserved2 = */ NULL,
4435	/* .pfnReserved3 = */ NULL,
4436	/* .pfnReserved4 = */ NULL,
4437	/* .pfnReserved5 = */ NULL,
4438	/* .pfnReserved6 = */ NULL,
4439	/* .pfnReserved7 = */ NULL,
4440	#else
4441	# error "Not in IN_RING3, IN_RING0 or IN_RC!"
4442	#endif
4443	/* .u32VersionEnd = */ PDM_DEVREG_VERSION
4444	};
4445
4446	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
4447

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source: vbox/trunk/src/VBox/Devices/Bus/DevIommuIntel.cpp@ 90213

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