VirtualBox

source: vbox/trunk/src/VBox/Devices/Bus/DevPCI-new.cpp@ 31780

Last change on this file since 31780 was 31762, checked in by vboxsync, 15 years ago

PCI: new implementation placeholders
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 8.9 KB
Line 
1/* $Id: DevPCI-new.cpp 31762 2010-08-18 13:15:10Z vboxsync $ */
2/** @file
3 * DevPCI - PCI BUS Device.
4 */
5
6/*
7 * Copyright (C) 2010 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/*******************************************************************************
19 * Header Files *
20 *******************************************************************************/
21#define LOG_GROUP LOG_GROUP_DEV_PCI
22/* Hack to get PCIDEVICEINT declare at the right point - include "PCIInternal.h". */
23#define PCI_INCLUDE_PRIVATE
24#include <VBox/pci.h>
25#include <VBox/pdmdev.h>
26#include <iprt/asm.h>
27#include <iprt/assert.h>
28#include <iprt/string.h>
29
30#include "../Builtins.h"
31
32/**
33 * PCI Bus instance.
34 */
35typedef struct
36{
37 /** Bus number. */
38 int32_t iBus;
39 /** Number of bridges attached to the bus. */
40 uint32_t cBridges;
41
42 /** Array of PCI devices. */
43 R3PTRTYPE(PPCIDEVICE) devices[256];
44 /** Array of bridges attached to the bus. */
45 R3PTRTYPE(PPCIDEVICE *) papBridgesR3;
46
47 /** R3 pointer to the device instance. */
48 PPDMDEVINSR3 pDevInsR3;
49 /** Pointer to the PCI R3 helpers. */
50 PCPDMPCIHLPR3 pPciHlpR3;
51
52 /** R0 pointer to the device instance. */
53 PPDMDEVINSR0 pDevInsR0;
54 /** Pointer to the PCI R0 helpers. */
55 PCPDMPCIHLPR0 pPciHlpR0;
56
57 /** RC pointer to the device instance. */
58 PPDMDEVINSRC pDevInsRC;
59 /** Pointer to the PCI RC helpers. */
60 PCPDMPCIHLPRC pPciHlpRC;
61
62 /** The PCI device for the PCI bridge. */
63 PCIDEVICE PciDev;
64
65} PCIBUS, *PPCIBUS;
66
67/**
68 * PIIX3 ISA Bridge state.
69 */
70typedef struct
71{
72 /** The PCI device of the bridge. */
73 PCIDEVICE dev;
74} PIIX3, *PPIIX3;
75
76
77/** @def PCI_IRQ_PINS
78 * Number of pins for interrupts (PIRQ#0...PIRQ#3)
79 */
80#define PCI_IRQ_PINS 4
81
82/** @def PCI_APIC_IRQ_PINS
83 * Number of pins for interrupts if the APIC is used.
84 */
85#define PCI_APIC_IRQ_PINS 8
86
87/**
88 * PCI Globals - This is the host-to-pci bridge and the root bus.
89 */
90typedef struct PCIGLOBALS
91{
92 /** I/O APIC usage flag */
93 bool fUseIoApic;
94
95 /** R3 pointer to the device instance. */
96 PPDMDEVINSR3 pDevInsR3;
97 /** R0 pointer to the device instance. */
98 PPDMDEVINSR0 pDevInsR0;
99 /** RC pointer to the device instance. */
100 PPDMDEVINSRC pDevInsRC;
101
102#if HC_ARCH_BITS == 64
103 uint32_t Alignment0;
104#endif
105
106 /** ISA bridge state. */
107 PIIX3 PIIX3State;
108 /** PCI bus which is attached to the host-to-PCI bridge. */
109 PCIBUS PciBus;
110
111} PCIGLOBALS;
112/** Pointer to per VM data. */
113typedef PCIGLOBALS *PPCIGLOBALS;
114
115/*******************************************************************************
116 * Defined Constants And Macros *
117 *******************************************************************************/
118
119/** Converts a bus instance pointer to a device instance pointer. */
120#define PCIBUS_2_DEVINS(pPciBus) ((pPciBus)->CTX_SUFF(pDevIns))
121/** Converts a device instance pointer to a PCIGLOBALS pointer. */
122#define DEVINS_2_PCIGLOBALS(pDevIns) ((PPCIGLOBALS)(PDMINS_2_DATA(pDevIns, PPCIGLOBALS)))
123/** Converts a device instance pointer to a PCIBUS pointer. */
124#define DEVINS_2_PCIBUS(pDevIns) ((PPCIBUS)(&PDMINS_2_DATA(pDevIns, PPCIGLOBALS)->PciBus))
125
126#ifndef VBOX_DEVICE_STRUCT_TESTCASE
127
128#ifdef IN_RING3
129
130static DECLCALLBACK(int) pciConstruct(PPDMDEVINS pDevIns,
131 int iInstance,
132 PCFGMNODE pCfg)
133{
134 int rc;
135 Assert(iInstance == 0);
136
137 /*
138 * Validate and read configuration.
139 */
140 if (!CFGMR3AreValuesValid(pCfg, "IOAPIC\0" "GCEnabled\0" "R0Enabled\0"))
141 return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
142
143 /* query whether we got an IOAPIC */
144 bool fUseIoApic;
145 rc = CFGMR3QueryBoolDef(pCfg, "IOAPIC", &fUseIoApic, false);
146 if (RT_FAILURE(rc))
147 return PDMDEV_SET_ERROR(pDevIns, rc,
148 N_("Configuration error: Failed to query boolean value \"IOAPIC\""));
149
150 /* check if RC code is enabled. */
151 bool fGCEnabled;
152 rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
153 if (RT_FAILURE(rc))
154 return PDMDEV_SET_ERROR(pDevIns, rc,
155 N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
156
157 /* check if R0 code is enabled. */
158 bool fR0Enabled;
159 rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
160 if (RT_FAILURE(rc))
161 return PDMDEV_SET_ERROR(pDevIns, rc,
162 N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
163 Log(("PCI: fUseIoApic=%RTbool fGCEnabled=%RTbool fR0Enabled=%RTbool\n", fUseIoApic, fGCEnabled, fR0Enabled));
164
165 /*
166 * Init data and register the PCI bus.
167 */
168 PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
169 pGlobals->fUseIoApic = fUseIoApic;
170
171 return VINF_SUCCESS;
172}
173
174/**
175 * @copydoc FNPDMDEVRELOCATE
176 */
177static DECLCALLBACK(void) pciRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
178{
179}
180
181/**
182 * @interface_method_impl{PDMDEVREG,pfnConstruct}
183 */
184static DECLCALLBACK(int) pcibridgeConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
185{
186 int rc;
187
188 /*
189 * Validate and read configuration.
190 */
191 if (!CFGMR3AreValuesValid(pCfg, "GCEnabled\0" "R0Enabled\0"))
192 return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
193
194 /* check if RC code is enabled. */
195 bool fGCEnabled;
196 rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
197 if (RT_FAILURE(rc))
198 return PDMDEV_SET_ERROR(pDevIns, rc,
199 N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
200
201 /* check if R0 code is enabled. */
202 bool fR0Enabled;
203 rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
204 if (RT_FAILURE(rc))
205 return PDMDEV_SET_ERROR(pDevIns, rc,
206 N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
207 Log(("PCI: fGCEnabled=%RTbool fR0Enabled=%RTbool\n", fGCEnabled, fR0Enabled));
208
209 return VINF_SUCCESS;
210}
211
212/**
213 * @copydoc FNPDMDEVRESET
214 */
215static DECLCALLBACK(void) pcibridgeReset(PPDMDEVINS pDevIns)
216{
217}
218
219
220/**
221 * @copydoc FNPDMDEVRELOCATE
222 */
223static DECLCALLBACK(void) pcibridgeRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
224{
225}
226
227/**
228 * The PCI bus device registration structure.
229 */
230const PDMDEVREG g_DevicePCI =
231{
232 /* u32Version */
233 PDM_DEVREG_VERSION,
234 /* szName */
235 "pci",
236 /* szRCMod */
237 "VBoxDDGC.gc",
238 /* szR0Mod */
239 "VBoxDDR0.r0",
240 /* pszDescription */
241 "i440FX PCI bridge and PIIX3 ISA bridge.",
242 /* fFlags */
243 PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0,
244 /* fClass */
245 PDM_DEVREG_CLASS_BUS_PCI | PDM_DEVREG_CLASS_BUS_ISA,
246 /* cMaxInstances */
247 1,
248 /* cbInstance */
249 sizeof(PCIGLOBALS),
250 /* pfnConstruct */
251 pciConstruct,
252 /* pfnDestruct */
253 NULL,
254 /* pfnRelocate */
255 pciRelocate,
256 /* pfnIOCtl */
257 NULL,
258 /* pfnPowerOn */
259 NULL,
260 /* pfnReset */
261 NULL,
262 /* pfnSuspend */
263 NULL,
264 /* pfnResume */
265 NULL,
266 /* pfnAttach */
267 NULL,
268 /* pfnDetach */
269 NULL,
270 /* pfnQueryInterface */
271 NULL,
272 /* pfnInitComplete */
273 NULL,
274 /* pfnPowerOff */
275 NULL,
276 /* pfnSoftReset */
277 NULL,
278 /* u32VersionEnd */
279 PDM_DEVREG_VERSION
280};
281
282/**
283 * The device registration structure
284 * for the PCI-to-PCI bridge.
285 */
286const PDMDEVREG g_DevicePCIBridge =
287{
288 /* u32Version */
289 PDM_DEVREG_VERSION,
290 /* szName */
291 "pcibridge",
292 /* szRCMod */
293 "VBoxDDGC.gc",
294 /* szR0Mod */
295 "VBoxDDR0.r0",
296 /* pszDescription */
297 "82801 Mobile PCI to PCI bridge",
298 /* fFlags */
299 PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0,
300 /* fClass */
301 PDM_DEVREG_CLASS_BUS_PCI,
302 /* cMaxInstances */
303 ~0,
304 /* cbInstance */
305 sizeof(PCIBUS),
306 /* pfnConstruct */
307 pcibridgeConstruct,
308 /* pfnDestruct */
309 NULL,
310 /* pfnRelocate */
311 pcibridgeRelocate,
312 /* pfnIOCtl */
313 NULL,
314 /* pfnPowerOn */
315 NULL,
316 /* pfnReset */
317 pcibridgeReset,
318 /* pfnSuspend */
319 NULL,
320 /* pfnResume */
321 NULL,
322 /* pfnAttach */
323 NULL,
324 /* pfnDetach */
325 NULL,
326 /* pfnQueryInterface */
327 NULL,
328 /* pfnInitComplete */
329 NULL,
330 /* pfnPowerOff */
331 NULL,
332 /* pfnSoftReset */
333 NULL,
334 /* u32VersionEnd */
335 PDM_DEVREG_VERSION
336};
337
338#endif /* IN_RING3 */
339#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
Note: See TracBrowser for help on using the repository browser.

© 2025 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette