DevPCI.cpp@ 61541

Last change on this file since 61541 was 60167, checked in by vboxsync, 9 years ago
DevPCI: make Parfait happy
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1	/* $Id: DevPCI.cpp 60167 2016-03-23 13:40:22Z vboxsync $ */
2	/** @file
3	* DevPCI - PCI BUS Device.
4	*/
5
6	/*
7	* Copyright (C) 2006-2015 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	* --------------------------------------------------------------------
17	*
18	* This code is based on:
19	*
20	* QEMU PCI bus manager
21	*
22	* Copyright (c) 2004 Fabrice Bellard
23	*
24	* Permission is hereby granted, free of charge, to any person obtaining a copy
25	* of this software and associated documentation files (the "Software"), to deal
26	* in the Software without restriction, including without limitation the rights
27	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
28	* copies of the Software, and to permit persons to whom the Software is
29	* furnished to do so, subject to the following conditions:
30	*
31	* The above copyright notice and this permission notice shall be included in
32	* all copies or substantial portions of the Software.
33	*
34	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
35	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
36	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
37	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
38	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
39	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
40	* THE SOFTWARE.
41	*/
42
43
44	/*********************************************************************************************************************************
45	* Header Files *
46	*********************************************************************************************************************************/
47	#define LOG_GROUP LOG_GROUP_DEV_PCI
48	/* Hack to get PCIDEVICEINT declared at the right point - include "PCIInternal.h". */
49	#define PCI_INCLUDE_PRIVATE
50	#include <VBox/pci.h>
51	#include <VBox/vmm/pdmdev.h>
52	#include <iprt/asm.h>
53	#include <iprt/assert.h>
54	#include <iprt/string.h>
55
56	#include "VBoxDD.h"
57
58
59	/*********************************************************************************************************************************
60	* Structures and Typedefs *
61	*********************************************************************************************************************************/
62	/**
63	* PIIX3 ISA Bridge state.
64	*/
65	typedef struct PIIX3State
66	{
67	/** The PCI device of the bridge. */
68	PCIDEVICE dev;
69	} PIIX3State, PIIX3, *PPIIX3;
70
71	/**
72	* PCI Bus instance.
73	*/
74	typedef struct PCIBus
75	{
76	/** Bus number. */
77	int32_t iBus;
78	/** Start device number. */
79	int32_t iDevSearch;
80	/** Number of bridges attached to the bus. */
81	uint32_t cBridges;
82
83	uint32_t Alignment0;
84
85	/** Array of PCI devices. */
86	R3PTRTYPE(PPCIDEVICE) devices[256];
87	/** Array of bridges attached to the bus. */
88	R3PTRTYPE(PPCIDEVICE *) papBridgesR3;
89
90	/** R3 pointer to the device instance. */
91	PPDMDEVINSR3 pDevInsR3;
92	/** Pointer to the PCI R3 helpers. */
93	PCPDMPCIHLPR3 pPciHlpR3;
94
95	/** R0 pointer to the device instance. */
96	PPDMDEVINSR0 pDevInsR0;
97	/** Pointer to the PCI R0 helpers. */
98	PCPDMPCIHLPR0 pPciHlpR0;
99
100	/** RC pointer to the device instance. */
101	PPDMDEVINSRC pDevInsRC;
102	/** Pointer to the PCI RC helpers. */
103	PCPDMPCIHLPRC pPciHlpRC;
104
105	/** The PCI device for the PCI bridge. */
106	PCIDEVICE PciDev;
107
108	} PCIBUS;
109	/** Pointer to a PCIBUS instance. */
110	typedef PCIBUS *PPCIBUS;
111	typedef PCIBUS PCIBus;
112
113	/** @def PCI_IRQ_PINS
114	* Number of pins for interrupts (PIRQ#0...PIRQ#3)
115	*/
116	#define PCI_IRQ_PINS 4
117
118	/** @def PCI_APIC_IRQ_PINS
119	* Number of pins for interrupts if the APIC is used.
120	*/
121	#define PCI_APIC_IRQ_PINS 8
122
123	/**
124	* PCI Globals - This is the host-to-pci bridge and the root bus.
125	*/
126	typedef struct PCIGLOBALS
127	{
128	/** Irq levels for the four PCI Irqs.
129	* These count how many devices asserted
130	* the IRQ line. If greater 0 an IRQ is sent to the guest.
131	* If it drops to 0 the IRQ is deasserted.
132	*/
133	volatile uint32_t pci_irq_levels[PCI_IRQ_PINS];
134
135	#if 1 /* Will be moved into the BIOS soon. */
136	/** The next I/O port address which the PCI BIOS will use. */
137	uint32_t pci_bios_io_addr;
138	/** The next MMIO address which the PCI BIOS will use. */
139	uint32_t pci_bios_mem_addr;
140	/** Actual bus number. */
141	uint8_t uBus;
142	#endif
143
144	/** I/O APIC usage flag */
145	bool fUseIoApic;
146	/** I/O APIC irq levels */
147	volatile uint32_t pci_apic_irq_levels[PCI_APIC_IRQ_PINS];
148	/** ACPI IRQ level */
149	uint32_t acpi_irq_level;
150	/** ACPI PIC IRQ */
151	int acpi_irq;
152	/** Config register. */
153	uint32_t uConfigReg;
154
155	/** R3 pointer to the device instance. */
156	PPDMDEVINSR3 pDevInsR3;
157	/** R0 pointer to the device instance. */
158	PPDMDEVINSR0 pDevInsR0;
159	/** RC pointer to the device instance. */
160	PPDMDEVINSRC pDevInsRC;
161
162	#if HC_ARCH_BITS == 64
163	uint32_t Alignment0;
164	#endif
165
166	/** ISA bridge state. */
167	PIIX3 PIIX3State;
168	/** PCI bus which is attached to the host-to-PCI bridge. */
169	PCIBUS PciBus;
170
171	} PCIGLOBALS;
172	/** Pointer to per VM data. */
173	typedef PCIGLOBALS *PPCIGLOBALS;
174
175
176	/*********************************************************************************************************************************
177	* Defined Constants And Macros *
178	*********************************************************************************************************************************/
179
180	/** Converts a bus instance pointer to a device instance pointer. */
181	#define PCIBUS_2_DEVINS(pPciBus) ((pPciBus)->CTX_SUFF(pDevIns))
182	/** Converts a PCI bus device instance pointer to a PCIGLOBALS pointer. */
183	#define DEVINS_2_PCIGLOBALS(pDevIns) ((PPCIGLOBALS)(PDMINS_2_DATA(pDevIns, PPCIGLOBALS)))
184	/** Converts a PCI bus device instance pointer to a PCIBUS pointer. */
185	#define DEVINS_2_PCIBUS(pDevIns) ((PPCIBUS)(&PDMINS_2_DATA(pDevIns, PPCIGLOBALS)->PciBus))
186
187	/** Converts a pointer to a PCI bus instance to a PCIGLOBALS pointer.
188	* @note This works only if the bus number is 0!!!
189	*/
190	#define PCIBUS_2_PCIGLOBALS(pPciBus) RT_FROM_MEMBER(pPciBus, PCIGLOBALS, PciBus)
191
192	/** @def PCI_LOCK
193	* Acquires the PDM lock. This is a NOP if locking is disabled. */
194	/** @def PCI_UNLOCK
195	* Releases the PDM lock. This is a NOP if locking is disabled. */
196	#define PCI_LOCK(pDevIns, rc) \
197	do { \
198	int rc2 = DEVINS_2_PCIBUS(pDevIns)->CTX_SUFF(pPciHlp)->pfnLock((pDevIns), rc); \
199	if (rc2 != VINF_SUCCESS) \
200	return rc2; \
201	} while (0)
202	#define PCI_UNLOCK(pDevIns) \
203	DEVINS_2_PCIBUS(pDevIns)->CTX_SUFF(pPciHlp)->pfnUnlock(pDevIns)
204
205	/** @def VBOX_PCI_SAVED_STATE_VERSION
206	* Saved state version of the PCI bus device.
207	*/
208	#define VBOX_PCI_SAVED_STATE_VERSION 3
209
210
211	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
212
213
214	/*********************************************************************************************************************************
215	* Internal Functions *
216	*********************************************************************************************************************************/
217	RT_C_DECLS_BEGIN
218
219	PDMBOTHCBDECL(void) pciSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel, uint32_t uTag);
220	PDMBOTHCBDECL(void) pcibridgeSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel, uint32_t uTag);
221	PDMBOTHCBDECL(int) pciIOPortAddressWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
222	PDMBOTHCBDECL(int) pciIOPortAddressRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb);
223	PDMBOTHCBDECL(int) pciIOPortDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
224	PDMBOTHCBDECL(int) pciIOPortDataRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb);
225
226	#ifdef IN_RING3
227	DECLINLINE(PPCIDEVICE) pciR3FindBridge(PPCIBUS pBus, uint8_t iBus);
228	#endif
229
230	RT_C_DECLS_END
231
232	#define DEBUG_PCI
233
234	#define PCI_VENDOR_ID 0x00 /* 16 bits */
235	#define PCI_DEVICE_ID 0x02 /* 16 bits */
236	#define PCI_COMMAND 0x04 /* 16 bits */
237	#define PCI_COMMAND_IO 0x01 /* Enable response in I/O space */
238	#define PCI_COMMAND_MEMORY 0x02 /* Enable response in Memory space */
239	#define PCI_CLASS_DEVICE 0x0a /* Device class */
240	#define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
241	#define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
242	#define PCI_MIN_GNT 0x3e /* 8 bits */
243	#define PCI_MAX_LAT 0x3f /* 8 bits */
244
245
246	#ifdef IN_RING3
247
248	static void pci_update_mappings(PCIDevice *d)
249	{
250	PPCIBUS pBus = d->Int.s.CTX_SUFF(pBus);
251	PCIIORegion *r;
252	int cmd, i;
253	uint32_t last_addr, new_addr, config_ofs;
254
255	cmd = RT_LE2H_U16((uint16_t )(d->config + PCI_COMMAND));
256	for(i = 0; i < PCI_NUM_REGIONS; i++) {
257	r = &d->Int.s.aIORegions[i];
258	if (i == PCI_ROM_SLOT) {
259	config_ofs = 0x30;
260	} else {
261	config_ofs = 0x10 + i * 4;
262	}
263	if (r->size != 0) {
264	if (r->type & PCI_ADDRESS_SPACE_IO) {
265	if (cmd & PCI_COMMAND_IO) {
266	new_addr = RT_LE2H_U32((uint32_t )(d->config +
267	config_ofs));
268	new_addr = new_addr & ~(r->size - 1);
269	last_addr = new_addr + r->size - 1;
270	/* NOTE: we have only 64K ioports on PC */
271	if (last_addr <= new_addr \|\| new_addr == 0 \|\|
272	last_addr >= 0x10000) {
273	new_addr = ~0U;
274	}
275	} else {
276	new_addr = ~0U;
277	}
278	} else {
279	if (cmd & PCI_COMMAND_MEMORY) {
280	new_addr = RT_LE2H_U32((uint32_t )(d->config +
281	config_ofs));
282	/* the ROM slot has a specific enable bit */
283	if (i == PCI_ROM_SLOT && !(new_addr & 1))
284	goto no_mem_map;
285	new_addr = new_addr & ~(r->size - 1);
286	last_addr = new_addr + r->size - 1;
287	/* NOTE: we do not support wrapping */
288	/* XXX: as we cannot support really dynamic
289	mappings, we handle specific values as invalid
290	mappings. */
291	/* Unconditionally exclude I/O-APIC/HPET/ROM. Pessimistic, but better than causing a mess. */
292	if (last_addr <= new_addr \|\| new_addr == 0 \|\|
293	(new_addr <= ~0U && last_addr >= 0xfec00000U)) {
294	new_addr = ~0U;
295	}
296	} else {
297	no_mem_map:
298	new_addr = ~0U;
299	}
300	}
301	//LogRel(("PCI: config dev %u/%u BAR%i uOld=%#018llx uNew=%#018llx size=%llu\n", d->devfn >> 3, d->devfn & 7, i, r->addr, new_addr, r->size));
302	/* now do the real mapping */
303	if (new_addr != r->addr) {
304	if (r->addr != ~0U) {
305	if (r->type & PCI_ADDRESS_SPACE_IO) {
306	int devclass;
307	/* NOTE: specific hack for IDE in PC case:
308	only one byte must be mapped. */
309	devclass = d->config[0x0a] \| (d->config[0x0b] << 8);
310	if (devclass == 0x0101 && r->size == 4) {
311	int rc = PDMDevHlpIOPortDeregister(d->pDevIns, r->addr + 2, 1);
312	AssertRC(rc);
313	} else {
314	int rc = PDMDevHlpIOPortDeregister(d->pDevIns, r->addr, r->size);
315	AssertRC(rc);
316	}
317	} else {
318	RTGCPHYS GCPhysBase = r->addr;
319	int rc;
320	if (pBus->pPciHlpR3->pfnIsMMIO2Base(pBus->pDevInsR3, d->pDevIns, GCPhysBase))
321	{
322	/* unmap it. */
323	rc = r->map_func(d, i, NIL_RTGCPHYS, r->size, (PCIADDRESSSPACE)(r->type));
324	AssertRC(rc);
325	rc = PDMDevHlpMMIO2Unmap(d->pDevIns, i, GCPhysBase);
326	}
327	else
328	rc = PDMDevHlpMMIODeregister(d->pDevIns, GCPhysBase, r->size);
329	AssertMsgRC(rc, ("rc=%Rrc d=%s i=%d GCPhysBase=%RGp size=%#x\n", rc, d->name, i, GCPhysBase, r->size));
330	}
331	}
332	r->addr = new_addr;
333	if (r->addr != ~0U) {
334	int rc = r->map_func(d, i,
335	r->addr + (r->type & PCI_ADDRESS_SPACE_IO ? 0 : 0),
336	r->size, (PCIADDRESSSPACE)(r->type));
337	AssertRC(rc);
338	}
339	}
340	}
341	}
342	}
343
344
345	static DECLCALLBACK(uint32_t) pci_default_read_config(PCIDevice *d, uint32_t address, unsigned len)
346	{
347	uint32_t val;
348	switch(len) {
349	case 1:
350	val = d->config[address];
351	break;
352	case 2:
353	val = RT_LE2H_U16((uint16_t )(d->config + address));
354	break;
355	default:
356	case 4:
357	val = RT_LE2H_U32((uint32_t )(d->config + address));
358	break;
359	}
360	return val;
361	}
362
363	static DECLCALLBACK(void) pci_default_write_config(PCIDevice *d, uint32_t address, uint32_t val, unsigned len)
364	{
365	int can_write;
366	unsigned i;
367	uint32_t end, addr;
368
369	if (len == 4 && ((address >= 0x10 && address < 0x10 + 4 * 6) \|\|
370	(address >= 0x30 && address < 0x34))) {
371	PCIIORegion *r;
372	int reg;
373
374	if ( address >= 0x30 ) {
375	reg = PCI_ROM_SLOT;
376	}else{
377	reg = (address - 0x10) >> 2;
378	}
379	r = &d->Int.s.aIORegions[reg];
380	if (r->size == 0)
381	goto default_config;
382	/* compute the stored value */
383	if (reg == PCI_ROM_SLOT) {
384	/* keep ROM enable bit */
385	val &= (~(r->size - 1)) \| 1;
386	} else {
387	val &= ~(r->size - 1);
388	val \|= r->type;
389	}
390	(uint32_t )(d->config + address) = RT_H2LE_U32(val);
391	pci_update_mappings(d);
392	return;
393	}
394	default_config:
395	/* not efficient, but simple */
396	addr = address;
397	for(i = 0; i < len; i++) {
398	/* default read/write accesses */
399	switch(d->config[0x0e]) {
400	case 0x00: /* normal device */
401	case 0x80: /* multi-function device */
402	switch(addr) {
403	case 0x00:
404	case 0x01:
405	case 0x02:
406	case 0x03:
407	case 0x08:
408	case 0x09:
409	case 0x0a:
410	case 0x0b:
411	case 0x0e:
412	case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17: /* base */
413	case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f:
414	case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27:
415	case 0x2c: case 0x2d: /* subsystem ID */
416	case 0x2e: case 0x2f: /* vendor ID */
417	case 0x30: case 0x31: case 0x32: case 0x33: /* rom */
418	case 0x34: /* Capabilities pointer. */
419	case 0x3d: /* Interrupt pin. */
420	can_write = 0;
421	break;
422	default:
423	can_write = 1;
424	break;
425	}
426	break;
427	default:
428	case 0x01: /* bridge */
429	switch(addr) {
430	case 0x00:
431	case 0x01:
432	case 0x02:
433	case 0x03:
434	case 0x08:
435	case 0x09:
436	case 0x0a:
437	case 0x0b:
438	case 0x0e:
439	case 0x38: case 0x39: case 0x3a: case 0x3b: /* rom */
440	case 0x3d:
441	can_write = 0;
442	break;
443	default:
444	can_write = 1;
445	break;
446	}
447	break;
448	}
449	#ifdef VBOX
450	if (addr == 0x05) /* Command register, bits 8-15. */
451	{
452	/* don't change reserved bits (11-15) */
453	val &= UINT32_C(~0xf8);
454	d->config[addr] = val;
455	}
456	else if (addr == 0x06) /* Status register, bits 0-7. */
457	{
458	/* don't change read-only bits => actually all lower bits are read-only */
459	val &= UINT32_C(~0xff);
460	/* status register, low part: clear bits by writing a '1' to the corresponding bit */
461	d->config[addr] &= ~val;
462	}
463	else if (addr == 0x07) /* Status register, bits 8-15. */
464	{
465	/* don't change read-only bits */
466	val &= UINT32_C(~0x06);
467	/* status register, high part: clear bits by writing a '1' to the corresponding bit */
468	d->config[addr] &= ~val;
469	}
470	else
471	#endif
472	if (can_write) {
473	d->config[addr] = val;
474	}
475	addr++;
476	val >>= 8;
477	}
478
479	end = address + len;
480	if (end > PCI_COMMAND && address < (PCI_COMMAND + 2)) {
481	/* if the command register is modified, we must modify the mappings */
482	pci_update_mappings(d);
483	}
484	}
485
486	#endif /* IN_RING3 */
487
488	static int pci_data_write(PPCIGLOBALS pGlobals, uint32_t addr, uint32_t val, int len)
489	{
490	uint8_t iBus, iDevice;
491	uint32_t config_addr;
492
493	Log(("pci_data_write: addr=%08x val=%08x len=%d\n", pGlobals->uConfigReg, val, len));
494
495	if (!(pGlobals->uConfigReg & (1 << 31))) {
496	return VINF_SUCCESS;
497	}
498	if ((pGlobals->uConfigReg & 0x3) != 0) {
499	return VINF_SUCCESS;
500	}
501	iBus = (pGlobals->uConfigReg >> 16) & 0xff;
502	iDevice = (pGlobals->uConfigReg >> 8) & 0xff;
503	config_addr = (pGlobals->uConfigReg & 0xfc) \| (addr & 3);
504	if (iBus != 0)
505	{
506	if (pGlobals->PciBus.cBridges)
507	{
508	#ifdef IN_RING3 /** @todo do lookup in R0/RC too! */
509	PPCIDEVICE pBridgeDevice = pciR3FindBridge(&pGlobals->PciBus, iBus);
510	if (pBridgeDevice)
511	{
512	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigWrite);
513	pBridgeDevice->Int.s.pfnBridgeConfigWrite(pBridgeDevice->pDevIns, iBus, iDevice, config_addr, val, len);
514	}
515	#else
516	return VINF_IOM_R3_IOPORT_WRITE;
517	#endif
518	}
519	}
520	else
521	{
522	R3PTRTYPE(PCIDevice *) pci_dev = pGlobals->PciBus.devices[iDevice];
523	if (pci_dev)
524	{
525	#ifdef IN_RING3
526	Log(("pci_config_write: %s: addr=%02x val=%08x len=%d\n", pci_dev->name, config_addr, val, len));
527	pci_dev->Int.s.pfnConfigWrite(pci_dev, config_addr, val, len);
528	#else
529	return VINF_IOM_R3_IOPORT_WRITE;
530	#endif
531	}
532	}
533	return VINF_SUCCESS;
534	}
535
536	static int pci_data_read(PPCIGLOBALS pGlobals, uint32_t addr, int len, uint32_t *pu32)
537	{
538	uint8_t iBus, iDevice;
539	uint32_t config_addr;
540
541	*pu32 = 0xffffffff;
542
543	if (!(pGlobals->uConfigReg & (1 << 31)))
544	return VINF_SUCCESS;
545	if ((pGlobals->uConfigReg & 0x3) != 0)
546	return VINF_SUCCESS;
547	iBus = (pGlobals->uConfigReg >> 16) & 0xff;
548	iDevice = (pGlobals->uConfigReg >> 8) & 0xff;
549	config_addr = (pGlobals->uConfigReg & 0xfc) \| (addr & 3);
550	if (iBus != 0)
551	{
552	if (pGlobals->PciBus.cBridges)
553	{
554	#ifdef IN_RING3 /** @todo do lookup in R0/RC too! */
555	PPCIDEVICE pBridgeDevice = pciR3FindBridge(&pGlobals->PciBus, iBus);
556	if (pBridgeDevice)
557	{
558	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigRead);
559	*pu32 = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->pDevIns, iBus, iDevice, config_addr, len);
560	}
561	#else
562	NOREF(len);
563	return VINF_IOM_R3_IOPORT_READ;
564	#endif
565	}
566	}
567	else
568	{
569	R3PTRTYPE(PCIDevice *) pci_dev = pGlobals->PciBus.devices[iDevice];
570	if (pci_dev)
571	{
572	#ifdef IN_RING3
573	*pu32 = pci_dev->Int.s.pfnConfigRead(pci_dev, config_addr, len);
574	Log(("pci_config_read: %s: addr=%02x val=%08x len=%d\n", pci_dev->name, config_addr, *pu32, len));
575	#else
576	NOREF(len);
577	return VINF_IOM_R3_IOPORT_READ;
578	#endif
579	}
580	}
581
582	return VINF_SUCCESS;
583	}
584
585
586
587	/* return the global irq number corresponding to a given device irq
588	pin. We could also use the bus number to have a more precise
589	mapping.
590	This is the implementation note described in the PCI spec chapter 2.2.6 */
591	static inline int pci_slot_get_pirq(uint8_t uDevFn, int irq_num)
592	{
593	int slot_addend;
594	slot_addend = (uDevFn >> 3) - 1;
595	return (irq_num + slot_addend) & 3;
596	}
597
598	static inline int pci_slot_get_apic_pirq(uint8_t uDevFn, int irq_num)
599	{
600	return (irq_num + (uDevFn >> 3)) & 7;
601	}
602
603	static inline int get_pci_irq_apic_level(PPCIGLOBALS pGlobals, int irq_num)
604	{
605	return (pGlobals->pci_apic_irq_levels[irq_num] != 0);
606	}
607
608	static void apic_set_irq(PPCIBUS pBus, uint8_t uDevFn, PCIDevice *pPciDev, int irq_num1, int iLevel, int acpi_irq, uint32_t uTagSrc)
609	{
610	/* This is only allowed to be called with a pointer to the host bus. */
611	AssertMsg(pBus->iBus == 0, ("iBus=%u\n", pBus->iBus));
612
613	if (acpi_irq == -1) {
614	int apic_irq, apic_level;
615	PPCIGLOBALS pGlobals = PCIBUS_2_PCIGLOBALS(pBus);
616	int irq_num = pci_slot_get_apic_pirq(uDevFn, irq_num1);
617
618	if ((iLevel & PDM_IRQ_LEVEL_HIGH) == PDM_IRQ_LEVEL_HIGH)
619	ASMAtomicIncU32(&pGlobals->pci_apic_irq_levels[irq_num]);
620	else if ((iLevel & PDM_IRQ_LEVEL_HIGH) == PDM_IRQ_LEVEL_LOW)
621	ASMAtomicDecU32(&pGlobals->pci_apic_irq_levels[irq_num]);
622
623	apic_irq = irq_num + 0x10;
624	apic_level = get_pci_irq_apic_level(pGlobals, irq_num);
625	Log3(("apic_set_irq: %s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d\n",
626	R3STRING(pPciDev->name), irq_num1, iLevel, apic_irq, apic_level, irq_num));
627	pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), apic_irq, apic_level, uTagSrc);
628
629	if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP) {
630	ASMAtomicDecU32(&pGlobals->pci_apic_irq_levels[irq_num]);
631	pPciDev->Int.s.uIrqPinState = PDM_IRQ_LEVEL_LOW;
632	apic_level = get_pci_irq_apic_level(pGlobals, irq_num);
633	Log3(("apic_set_irq: %s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d (flop)\n",
634	R3STRING(pPciDev->name), irq_num1, iLevel, apic_irq, apic_level, irq_num));
635	pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), apic_irq, apic_level, uTagSrc);
636	}
637	} else {
638	Log3(("apic_set_irq: %s: irq_num1=%d level=%d acpi_irq=%d\n",
639	R3STRING(pPciDev->name), irq_num1, iLevel, acpi_irq));
640	pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), acpi_irq, iLevel, uTagSrc);
641	}
642	}
643
644	DECLINLINE(int) get_pci_irq_level(PPCIGLOBALS pGlobals, int irq_num)
645	{
646	return (pGlobals->pci_irq_levels[irq_num] != 0);
647	}
648
649	/**
650	* Set the IRQ for a PCI device on the host bus - shared by host bus and bridge.
651	*
652	* @param pDevIns Device instance of the host PCI Bus.
653	* @param uDevFn The device number on the host bus which will raise the IRQ
654	* @param pPciDev The PCI device structure which raised the interrupt.
655	* @param iIrq IRQ number to set.
656	* @param iLevel IRQ level.
657	* @param uTagSrc The IRQ tag and source ID (for tracing).
658	* @remark uDevFn and pPciDev->devfn are not the same if the device is behind a bridge.
659	* In that case uDevFn will be the slot of the bridge which is needed to calculate the
660	* PIRQ value.
661	*/
662	static void pciSetIrqInternal(PPCIGLOBALS pGlobals, uint8_t uDevFn, PPCIDEVICE pPciDev, int iIrq, int iLevel, uint32_t uTagSrc)
663	{
664	PPCIBUS pBus = &pGlobals->PciBus;
665	uint8_t *pbCfg = pGlobals->PIIX3State.dev.config;
666	const bool fIsAcpiDevice = pPciDev->config[2] == 0x13 && pPciDev->config[3] == 0x71;
667	/* If the two configuration space bytes at 0xde, 0xad are set to 0xbe, 0xef, a back door
668	* is opened to route PCI interrupts directly to the I/O APIC and bypass the PIC.
669	* See the \_SB_.PCI0._PRT method in vbox.dsl.
670	*/
671	const bool fIsApicEnabled = pGlobals->fUseIoApic && pbCfg[0xde] == 0xbe && pbCfg[0xad] == 0xef;
672	int pic_irq, pic_level;
673
674	/* Check if the state changed. */
675	if (pPciDev->Int.s.uIrqPinState != iLevel)
676	{
677	pPciDev->Int.s.uIrqPinState = (iLevel & PDM_IRQ_LEVEL_HIGH);
678
679	/* Send interrupt to I/O APIC only. */
680	if (fIsApicEnabled)
681	{
682	if (fIsAcpiDevice)
683	/*
684	* ACPI needs special treatment since SCI is hardwired and
685	* should not be affected by PCI IRQ routing tables at the
686	* same time SCI IRQ is shared in PCI sense hence this
687	* kludge (i.e. we fetch the hardwired value from ACPIs
688	* PCI device configuration space).
689	*/
690	apic_set_irq(pBus, uDevFn, pPciDev, -1, iLevel, pPciDev->config[PCI_INTERRUPT_LINE], uTagSrc);
691	else
692	apic_set_irq(pBus, uDevFn, pPciDev, iIrq, iLevel, -1, uTagSrc);
693	return;
694	}
695
696	if (fIsAcpiDevice)
697	{
698	/* As per above treat ACPI in a special way */
699	pic_irq = pPciDev->config[PCI_INTERRUPT_LINE];
700	pGlobals->acpi_irq = pic_irq;
701	pGlobals->acpi_irq_level = iLevel & PDM_IRQ_LEVEL_HIGH;
702	}
703	else
704	{
705	int irq_num;
706	irq_num = pci_slot_get_pirq(uDevFn, iIrq);
707
708	if (pPciDev->Int.s.uIrqPinState == PDM_IRQ_LEVEL_HIGH)
709	ASMAtomicIncU32(&pGlobals->pci_irq_levels[irq_num]);
710	else if (pPciDev->Int.s.uIrqPinState == PDM_IRQ_LEVEL_LOW)
711	ASMAtomicDecU32(&pGlobals->pci_irq_levels[irq_num]);
712
713	/* now we change the pic irq level according to the piix irq mappings */
714	pic_irq = pbCfg[0x60 + irq_num];
715	if (pic_irq >= 16)
716	{
717	if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP)
718	{
719	ASMAtomicDecU32(&pGlobals->pci_irq_levels[irq_num]);
720	pPciDev->Int.s.uIrqPinState = PDM_IRQ_LEVEL_LOW;
721	}
722
723	return;
724	}
725	}
726
727	/* the pic level is the logical OR of all the PCI irqs mapped to it */
728	pic_level = 0;
729	if (pic_irq == pbCfg[0x60])
730	pic_level \|= get_pci_irq_level(pGlobals, 0);
731	if (pic_irq == pbCfg[0x61])
732	pic_level \|= get_pci_irq_level(pGlobals, 1);
733	if (pic_irq == pbCfg[0x62])
734	pic_level \|= get_pci_irq_level(pGlobals, 2);
735	if (pic_irq == pbCfg[0x63])
736	pic_level \|= get_pci_irq_level(pGlobals, 3);
737	if (pic_irq == pGlobals->acpi_irq)
738	pic_level \|= pGlobals->acpi_irq_level;
739
740	Log3(("pciSetIrq: %s: iLevel=%d iIrq=%d pic_irq=%d pic_level=%d uTagSrc=%#x\n",
741	R3STRING(pPciDev->name), iLevel, iIrq, pic_irq, pic_level, uTagSrc));
742	pBus->CTX_SUFF(pPciHlp)->pfnIsaSetIrq(pBus->CTX_SUFF(pDevIns), pic_irq, pic_level, uTagSrc);
743
744	/** @todo optimize pci irq flip-flop some rainy day. */
745	if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP)
746	pciSetIrqInternal(pGlobals, uDevFn, pPciDev, iIrq, PDM_IRQ_LEVEL_LOW, uTagSrc);
747	}
748	}
749
750
751	/**
752	* @interface_method_impl{PDMPCIBUSREG,pfnSetIrqR3}
753	*/
754	PDMBOTHCBDECL(void) pciSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel, uint32_t uTagSrc)
755	{
756	pciSetIrqInternal(PDMINS_2_DATA(pDevIns, PPCIGLOBALS), pPciDev->devfn, pPciDev, iIrq, iLevel, uTagSrc);
757	}
758
759	#ifdef IN_RING3
760
761	/**
762	* Finds a bridge on the bus which contains the destination bus.
763	*
764	* @return Pointer to the device instance data of the bus or
765	* NULL if no bridge was found.
766	* @param pBus Pointer to the bus to search on.
767	* @param iBus Destination bus number.
768	*/
769	DECLINLINE(PPCIDEVICE) pciR3FindBridge(PPCIBUS pBus, uint8_t iBus)
770	{
771	/* Search for a fitting bridge. */
772	for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
773	{
774	/*
775	* Examine secondary and subordinate bus number.
776	* If the target bus is in the range we pass the request on to the bridge.
777	*/
778	PPCIDEVICE pBridgeTemp = pBus->papBridgesR3[iBridge];
779	AssertMsg(pBridgeTemp && pciDevIsPci2PciBridge(pBridgeTemp),
780	("Device is not a PCI bridge but on the list of PCI bridges\n"));
781
782	if ( iBus >= pBridgeTemp->config[VBOX_PCI_SECONDARY_BUS]
783	&& iBus <= pBridgeTemp->config[VBOX_PCI_SUBORDINATE_BUS])
784	return pBridgeTemp;
785	}
786
787	/* Nothing found. */
788	return NULL;
789	}
790
791	static void pciR3Piix3Reset(PIIX3State *d)
792	{
793	uint8_t *pci_conf = d->dev.config;
794
795	pci_conf[0x04] = 0x07; /* master, memory and I/O */
796	pci_conf[0x05] = 0x00;
797	pci_conf[0x06] = 0x00;
798	pci_conf[0x07] = 0x02; /* PCI_status_devsel_medium */
799	pci_conf[0x4c] = 0x4d;
800	pci_conf[0x4e] = 0x03;
801	pci_conf[0x4f] = 0x00;
802	pci_conf[0x60] = 0x80;
803	pci_conf[0x69] = 0x02;
804	pci_conf[0x70] = 0x80;
805	pci_conf[0x76] = 0x0c;
806	pci_conf[0x77] = 0x0c;
807	pci_conf[0x78] = 0x02;
808	pci_conf[0x79] = 0x00;
809	pci_conf[0x80] = 0x00;
810	pci_conf[0x82] = 0x02; /* Get rid of the Linux guest "Enabling Passive Release" PCI quirk warning. */
811	pci_conf[0xa0] = 0x08;
812	pci_conf[0xa2] = 0x00;
813	pci_conf[0xa3] = 0x00;
814	pci_conf[0xa4] = 0x00;
815	pci_conf[0xa5] = 0x00;
816	pci_conf[0xa6] = 0x00;
817	pci_conf[0xa7] = 0x00;
818	pci_conf[0xa8] = 0x0f;
819	pci_conf[0xaa] = 0x00;
820	pci_conf[0xab] = 0x00;
821	pci_conf[0xac] = 0x00;
822	pci_conf[0xae] = 0x00;
823	}
824
825	static void pci_config_writel(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t val)
826	{
827	pGlobals->uConfigReg = 0x80000000 \| (uBus << 16) \|
828	(uDevFn << 8) \| addr;
829	pci_data_write(pGlobals, 0, val, 4);
830	}
831
832	static void pci_config_writew(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t val)
833	{
834	pGlobals->uConfigReg = 0x80000000 \| (uBus << 16) \|
835	(uDevFn << 8) \| (addr & ~3);
836	pci_data_write(pGlobals, addr & 3, val, 2);
837	}
838
839	static void pci_config_writeb(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t val)
840	{
841	pGlobals->uConfigReg = 0x80000000 \| (uBus << 16) \|
842	(uDevFn << 8) \| (addr & ~3);
843	pci_data_write(pGlobals, addr & 3, val, 1);
844	}
845
846	static uint32_t pci_config_readl(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr)
847	{
848	pGlobals->uConfigReg = 0x80000000 \| (uBus << 16) \|
849	(uDevFn << 8) \| addr;
850	uint32_t u32Val;
851	int rc = pci_data_read(pGlobals, 0, 4, &u32Val);
852	AssertRC(rc);
853	return u32Val;
854	}
855
856	static uint32_t pci_config_readw(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr)
857	{
858	pGlobals->uConfigReg = 0x80000000 \| (uBus << 16) \|
859	(uDevFn << 8) \| (addr & ~3);
860	uint32_t u32Val;
861	int rc = pci_data_read(pGlobals, addr & 3, 2, &u32Val);
862	AssertRC(rc);
863	return u32Val;
864	}
865
866	static uint32_t pci_config_readb(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr)
867	{
868	pGlobals->uConfigReg = 0x80000000 \| (uBus << 16) \|
869	(uDevFn << 8) \| (addr & ~3);
870	uint32_t u32Val;
871	int rc = pci_data_read(pGlobals, addr & 3, 1, &u32Val);
872	AssertRC(rc);
873	return u32Val;
874	}
875
876	/* host irqs corresponding to PCI irqs A-D */
877	static const uint8_t pci_irqs[4] = { 11, 9, 11, 9 }; /* bird: added const */
878
879	static void pci_set_io_region_addr(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, int region_num, uint32_t addr)
880	{
881	uint32_t ofs;
882
883	if ( region_num == PCI_ROM_SLOT )
884	ofs = 0x30;
885	else
886	ofs = 0x10 + region_num * 4;
887
888	Log(("Set region address: %02x:%02x.%d region %d address=%lld\n",
889	uBus, uDevFn >> 3, uDevFn & 7, region_num, addr));
890
891	/* Write address of the device. */
892	pci_config_writel(pGlobals, uBus, uDevFn, ofs, addr);
893	}
894
895	static void pci_bios_init_device(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint8_t cBridgeDepth, uint8_t *paBridgePositions)
896	{
897	uint32_t *paddr;
898	int i, pin, pic_irq;
899	uint16_t devclass, vendor_id, device_id;
900
901	devclass = pci_config_readw(pGlobals, uBus, uDevFn, PCI_CLASS_DEVICE);
902	vendor_id = pci_config_readw(pGlobals, uBus, uDevFn, PCI_VENDOR_ID);
903	device_id = pci_config_readw(pGlobals, uBus, uDevFn, PCI_DEVICE_ID);
904
905	/* Check if device is present. */
906	if (vendor_id != 0xffff)
907	{
908	switch(devclass)
909	{
910	case 0x0101:
911	if ( (vendor_id == 0x8086)
912	&& (device_id == 0x7010 \|\| device_id == 0x7111 \|\| device_id == 0x269e))
913	{
914	/* PIIX3, PIIX4 or ICH6 IDE */
915	pci_config_writew(pGlobals, uBus, uDevFn, 0x40, 0x8000); /* enable IDE0 */
916	pci_config_writew(pGlobals, uBus, uDevFn, 0x42, 0x8000); /* enable IDE1 */
917	goto default_map;
918	}
919	else
920	{
921	/* IDE: we map it as in ISA mode */
922	pci_set_io_region_addr(pGlobals, uBus, uDevFn, 0, 0x1f0);
923	pci_set_io_region_addr(pGlobals, uBus, uDevFn, 1, 0x3f4);
924	pci_set_io_region_addr(pGlobals, uBus, uDevFn, 2, 0x170);
925	pci_set_io_region_addr(pGlobals, uBus, uDevFn, 3, 0x374);
926	pci_config_writeb(pGlobals, uBus, uDevFn, PCI_COMMAND,
927	pci_config_readb(pGlobals, uBus, uDevFn, PCI_COMMAND)
928	\| PCI_COMMAND_IOACCESS);
929	}
930	break;
931	case 0x0300:
932	if (vendor_id != 0x80ee)
933	goto default_map;
934	/* VGA: map frame buffer to default Bochs VBE address */
935	pci_set_io_region_addr(pGlobals, uBus, uDevFn, 0, 0xE0000000);
936	/*
937	* Legacy VGA I/O ports are implicitly decoded by a VGA class device. But
938	* only the framebuffer (i.e., a memory region) is explicitly registered via
939	* pci_set_io_region_addr, so don't forget to enable I/O decoding.
940	*/
941	pci_config_writeb(pGlobals, uBus, uDevFn, PCI_COMMAND,
942	pci_config_readb(pGlobals, uBus, uDevFn, PCI_COMMAND)
943	\| PCI_COMMAND_IOACCESS \| PCI_COMMAND_MEMACCESS);
944	break;
945	case 0x0800:
946	/* PIC */
947	vendor_id = pci_config_readw(pGlobals, uBus, uDevFn, PCI_VENDOR_ID);
948	device_id = pci_config_readw(pGlobals, uBus, uDevFn, PCI_DEVICE_ID);
949	if (vendor_id == 0x1014)
950	{
951	/* IBM */
952	if (device_id == 0x0046 \|\| device_id == 0xFFFF)
953	{
954	/* MPIC & MPIC2 */
955	pci_set_io_region_addr(pGlobals, uBus, uDevFn, 0, 0x80800000 + 0x00040000);
956	pci_config_writeb(pGlobals, uBus, uDevFn, PCI_COMMAND,
957	pci_config_readb(pGlobals, uBus, uDevFn, PCI_COMMAND)
958	\| PCI_COMMAND_MEMACCESS);
959	}
960	}
961	break;
962	case 0xff00:
963	if ( (vendor_id == 0x0106b)
964	&& (device_id == 0x0017 \|\| device_id == 0x0022))
965	{
966	/* macio bridge */
967	pci_set_io_region_addr(pGlobals, uBus, uDevFn, 0, 0x80800000);
968	pci_config_writeb(pGlobals, uBus, uDevFn, PCI_COMMAND,
969	pci_config_readb(pGlobals, uBus, uDevFn, PCI_COMMAND)
970	\| PCI_COMMAND_MEMACCESS);
971	}
972	break;
973	case 0x0604:
974	{
975	/* Init PCI-to-PCI bridge. */
976	pci_config_writeb(pGlobals, uBus, uDevFn, VBOX_PCI_PRIMARY_BUS, uBus);
977
978	AssertMsg(pGlobals->uBus < 255, ("Too many bridges on the bus\n"));
979	pGlobals->uBus++;
980	pci_config_writeb(pGlobals, uBus, uDevFn, VBOX_PCI_SECONDARY_BUS, pGlobals->uBus);
981	pci_config_writeb(pGlobals, uBus, uDevFn, VBOX_PCI_SUBORDINATE_BUS, 0xff); /* Temporary until we know how many other bridges are behind this one. */
982
983	/* Add position of this bridge into the array. */
984	paBridgePositions[cBridgeDepth+1] = (uDevFn >> 3);
985
986	/*
987	* The I/O range for the bridge must be aligned to a 4KB boundary.
988	* This does not change anything really as the access to the device is not going
989	* through the bridge but we want to be compliant to the spec.
990	*/
991	if ((pGlobals->pci_bios_io_addr % 4096) != 0)
992	pGlobals->pci_bios_io_addr = RT_ALIGN_32(pGlobals->pci_bios_io_addr, 4*1024);
993	Log(("%s: Aligned I/O start address. New address %#x\n", __FUNCTION__, pGlobals->pci_bios_io_addr));
994	pci_config_writeb(pGlobals, uBus, uDevFn, VBOX_PCI_IO_BASE, (pGlobals->pci_bios_io_addr >> 8) & 0xf0);
995
996	/* The MMIO range for the bridge must be aligned to a 1MB boundary. */
997	if ((pGlobals->pci_bios_mem_addr % (1024 * 1024)) != 0)
998	pGlobals->pci_bios_mem_addr = RT_ALIGN_32(pGlobals->pci_bios_mem_addr, 1024*1024);
999	Log(("%s: Aligned MMIO start address. New address %#x\n", __FUNCTION__, pGlobals->pci_bios_mem_addr));
1000	pci_config_writew(pGlobals, uBus, uDevFn, VBOX_PCI_MEMORY_BASE, (pGlobals->pci_bios_mem_addr >> 16) & UINT32_C(0xffff0));
1001
1002	/* Save values to compare later to. */
1003	uint32_t u32IoAddressBase = pGlobals->pci_bios_io_addr;
1004	uint32_t u32MMIOAddressBase = pGlobals->pci_bios_mem_addr;
1005
1006	/* Init devices behind the bridge and possibly other bridges as well. */
1007	for (int iDev = 0; iDev <= 255; iDev++)
1008	pci_bios_init_device(pGlobals, uBus + 1, iDev, cBridgeDepth + 1, paBridgePositions);
1009
1010	/* The number of bridges behind the this one is now available. */
1011	pci_config_writeb(pGlobals, uBus, uDevFn, VBOX_PCI_SUBORDINATE_BUS, pGlobals->uBus);
1012
1013	/*
1014	* Set I/O limit register. If there is no device with I/O space behind the bridge
1015	* we set a lower value than in the base register.
1016	* The result with a real bridge is that no I/O transactions are passed to the secondary
1017	* interface. Again this doesn't really matter here but we want to be compliant to the spec.
1018	*/
1019	if ((u32IoAddressBase != pGlobals->pci_bios_io_addr) && ((pGlobals->pci_bios_io_addr % 4096) != 0))
1020	{
1021	/* The upper boundary must be one byte less than a 4KB boundary. */
1022	pGlobals->pci_bios_io_addr = RT_ALIGN_32(pGlobals->pci_bios_io_addr, 4*1024);
1023	}
1024	pci_config_writeb(pGlobals, uBus, uDevFn, VBOX_PCI_IO_LIMIT, ((pGlobals->pci_bios_io_addr >> 8) & 0xf0) - 1);
1025
1026	/* Same with the MMIO limit register but with 1MB boundary here. */
1027	if ((u32MMIOAddressBase != pGlobals->pci_bios_mem_addr) && ((pGlobals->pci_bios_mem_addr % (1024 * 1024)) != 0))
1028	{
1029	/* The upper boundary must be one byte less than a 1MB boundary. */
1030	pGlobals->pci_bios_mem_addr = RT_ALIGN_32(pGlobals->pci_bios_mem_addr, 1024*1024);
1031	}
1032	pci_config_writew(pGlobals, uBus, uDevFn, VBOX_PCI_MEMORY_LIMIT, ((pGlobals->pci_bios_mem_addr >> 16) & UINT32_C(0xfff0)) - 1);
1033
1034	/*
1035	* Set the prefetch base and limit registers. We currently have no device with a prefetchable region
1036	* which may be behind a bridge. That's why it is unconditionally disabled here atm by writing a higher value into
1037	* the base register than in the limit register.
1038	*/
1039	pci_config_writew(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_MEMORY_BASE, 0xfff0);
1040	pci_config_writew(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_MEMORY_LIMIT, 0x0);
1041	pci_config_writel(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_BASE_UPPER32, 0x00);
1042	pci_config_writel(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_LIMIT_UPPER32, 0x00);
1043	break;
1044	}
1045	default:
1046	default_map:
1047	{
1048	/* default memory mappings */
1049	bool fActiveMemRegion = false;
1050	bool fActiveIORegion = false;
1051	/*
1052	* PCI_NUM_REGIONS is 7 because of the rom region but there are only 6 base address register defined by the PCI spec.
1053	* Leaving only PCI_NUM_REGIONS would cause reading another and enabling a memory region which does not exist.
1054	*/
1055	for(i = 0; i < (PCI_NUM_REGIONS-1); i++)
1056	{
1057	uint32_t u32Size;
1058	uint8_t u8RessourceType;
1059	uint32_t u32Address = 0x10 + i * 4;
1060
1061	/* Calculate size. */
1062	u8RessourceType = pci_config_readb(pGlobals, uBus, uDevFn, u32Address);
1063	pci_config_writel(pGlobals, uBus, uDevFn, u32Address, UINT32_C(0xffffffff));
1064	u32Size = pci_config_readl(pGlobals, uBus, uDevFn, u32Address);
1065	bool fIsPio = ((u8RessourceType & PCI_COMMAND_IOACCESS) == PCI_COMMAND_IOACCESS);
1066	/* Clear resource information depending on resource type. */
1067	if (fIsPio) /* I/O */
1068	u32Size &= ~(0x01);
1069	else /* MMIO */
1070	u32Size &= ~(0x0f);
1071
1072	/*
1073	* Invert all bits and add 1 to get size of the region.
1074	* (From PCI implementation note)
1075	*/
1076	if (fIsPio && (u32Size & UINT32_C(0xffff0000)) == 0)
1077	u32Size = (~(u32Size \| UINT32_C(0xffff0000))) + 1;
1078	else
1079	u32Size = (~u32Size) + 1;
1080
1081	Log2(("%s: Size of region %u for device %d on bus %d is %u\n", __FUNCTION__, i, uDevFn, uBus, u32Size));
1082
1083	if (u32Size)
1084	{
1085	if (fIsPio)
1086	paddr = &pGlobals->pci_bios_io_addr;
1087	else
1088	paddr = &pGlobals->pci_bios_mem_addr;
1089	uint32_t uNew = *paddr;
1090	uNew = (uNew + u32Size - 1) & ~(u32Size - 1);
1091	if (fIsPio)
1092	uNew &= UINT32_C(0xffff);
1093	/* Unconditionally exclude I/O-APIC/HPET/ROM. Pessimistic, but better than causing a mess. */
1094	if (!uNew \|\| (uNew <= UINT32_C(0xffffffff) && uNew + u32Size - 1 >= UINT32_C(0xfec00000)))
1095	{
1096	LogRel(("PCI: no space left for BAR%u of device %u/%u/%u (vendor=%#06x device=%#06x)\n",
1097	i, uBus, uDevFn >> 3, uDevFn & 7, vendor_id, device_id)); /** @todo make this a VM start failure later. */
1098	/* Undo the mapping mess caused by the size probing. */
1099	pci_config_writel(pGlobals, uBus, uDevFn, u32Address, UINT32_C(0));
1100	}
1101	else
1102	{
1103	Log(("%s: Start address of %s region %u is %#x\n", __FUNCTION__, (fIsPio ? "I/O" : "MMIO"), i, uNew));
1104	pci_set_io_region_addr(pGlobals, uBus, uDevFn, i, uNew);
1105	if (fIsPio)
1106	fActiveIORegion = true;
1107	else
1108	fActiveMemRegion = true;
1109	*paddr = uNew + u32Size;
1110	Log2(("%s: New address is %#x\n", __FUNCTION__, *paddr));
1111	}
1112	}
1113	}
1114
1115	/* Update the command word appropriately. */
1116	pci_config_writeb(pGlobals, uBus, uDevFn, PCI_COMMAND,
1117	pci_config_readb(pGlobals, uBus, uDevFn, PCI_COMMAND)
1118	\| (fActiveMemRegion ? PCI_COMMAND_MEMACCESS : 0)
1119	\| (fActiveIORegion ? PCI_COMMAND_IOACCESS : 0));
1120
1121	break;
1122	}
1123	}
1124
1125	/* map the interrupt */
1126	pin = pci_config_readb(pGlobals, uBus, uDevFn, PCI_INTERRUPT_PIN);
1127	if (pin != 0)
1128	{
1129	uint8_t uBridgeDevFn = uDevFn;
1130	pin--;
1131
1132	/* We need to go up to the host bus to see which irq this device will assert there. */
1133	while (cBridgeDepth != 0)
1134	{
1135	/* Get the pin the device would assert on the bridge. */
1136	pin = ((uBridgeDevFn >> 3) + pin) & 3;
1137	uBridgeDevFn = paBridgePositions[cBridgeDepth];
1138	cBridgeDepth--;
1139	}
1140
1141	pin = pci_slot_get_pirq(uDevFn, pin);
1142	pic_irq = pci_irqs[pin];
1143	pci_config_writeb(pGlobals, uBus, uDevFn, PCI_INTERRUPT_LINE, pic_irq);
1144	}
1145	}
1146	}
1147
1148	#endif /* IN_RING3 */
1149
1150
1151	/* -=-=-=-=-=- I/O ports -=-=-=-=-=- */
1152
1153	/**
1154	* @callback_method_impl{FNIOMIOPORTOUT, PCI address}
1155	*/
1156	PDMBOTHCBDECL(int) pciIOPortAddressWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1157	{
1158	Log(("pciIOPortAddressWrite: Port=%#x u32=%#x cb=%d\n", Port, u32, cb));
1159	NOREF(pvUser);
1160	if (cb == 4)
1161	{
1162	PPCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
1163	PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_WRITE);
1164	pThis->uConfigReg = u32 & ~3; /* Bits 0-1 are reserved and we silently clear them */
1165	PCI_UNLOCK(pDevIns);
1166	}
1167	/* else: 440FX does "pass through to the bus" for other writes, what ever that means.
1168	* Linux probes for cmd640 using byte writes/reads during ide init. We'll just ignore it. */
1169	return VINF_SUCCESS;
1170	}
1171
1172
1173	/**
1174	* @callback_method_impl{FNIOMIOPORTIN, PCI address}
1175	*/
1176	PDMBOTHCBDECL(int) pciIOPortAddressRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
1177	{
1178	NOREF(pvUser);
1179	if (cb == 4)
1180	{
1181	PPCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
1182	PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_READ);
1183	*pu32 = pThis->uConfigReg;
1184	PCI_UNLOCK(pDevIns);
1185	Log(("pciIOPortAddressRead: Port=%#x cb=%d -> %#x\n", Port, cb, *pu32));
1186	return VINF_SUCCESS;
1187	}
1188	/* else: 440FX does "pass through to the bus" for other writes, what ever that means.
1189	* Linux probes for cmd640 using byte writes/reads during ide init. We'll just ignore it. */
1190	Log(("pciIOPortAddressRead: Port=%#x cb=%d VERR_IOM_IOPORT_UNUSED\n", Port, cb));
1191	return VERR_IOM_IOPORT_UNUSED;
1192	}
1193
1194
1195	/**
1196	* @callback_method_impl{FNIOMIOPORTOUT, PCI data}
1197	*/
1198	PDMBOTHCBDECL(int) pciIOPortDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1199	{
1200	Log(("pciIOPortDataWrite: Port=%#x u32=%#x cb=%d\n", Port, u32, cb));
1201	NOREF(pvUser);
1202	int rc = VINF_SUCCESS;
1203	if (!(Port % cb))
1204	{
1205	PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_WRITE);
1206	rc = pci_data_write(PDMINS_2_DATA(pDevIns, PPCIGLOBALS), Port, u32, cb);
1207	PCI_UNLOCK(pDevIns);
1208	}
1209	else
1210	AssertMsgFailed(("Write to port %#x u32=%#x cb=%d\n", Port, u32, cb));
1211	return rc;
1212	}
1213
1214
1215	/**
1216	* @callback_method_impl{FNIOMIOPORTIN, PCI data}
1217	*/
1218	PDMBOTHCBDECL(int) pciIOPortDataRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
1219	{
1220	NOREF(pvUser);
1221	if (!(Port % cb))
1222	{
1223	PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_READ);
1224	int rc = pci_data_read(PDMINS_2_DATA(pDevIns, PPCIGLOBALS), Port, cb, pu32);
1225	PCI_UNLOCK(pDevIns);
1226	Log(("pciIOPortDataRead: Port=%#x cb=%#x -> %#x (%Rrc)\n", Port, cb, *pu32, rc));
1227	return rc;
1228	}
1229	AssertMsgFailed(("Read from port %#x cb=%d\n", Port, cb));
1230	return VERR_IOM_IOPORT_UNUSED;
1231	}
1232
1233	#ifdef IN_RING3
1234
1235	/* -=-=-=-=-=- Saved state -=-=-=-=-=- */
1236
1237	/**
1238	* Common worker for pciR3SaveExec and pcibridgeR3SaveExec.
1239	*
1240	* @returns VBox status code.
1241	* @param pBus The bus to save.
1242	* @param pSSM The saved state handle.
1243	*/
1244	static int pciR3CommonSaveExec(PPCIBUS pBus, PSSMHANDLE pSSM)
1245	{
1246	/*
1247	* Iterate thru all the devices.
1248	*/
1249	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->devices); i++)
1250	{
1251	PPCIDEVICE pDev = pBus->devices[i];
1252	if (pDev)
1253	{
1254	SSMR3PutU32(pSSM, i);
1255	SSMR3PutMem(pSSM, pDev->config, sizeof(pDev->config));
1256
1257	int rc = SSMR3PutS32(pSSM, pDev->Int.s.uIrqPinState);
1258	if (RT_FAILURE(rc))
1259	return rc;
1260	}
1261	}
1262	return SSMR3PutU32(pSSM, UINT32_MAX); /* terminator */
1263	}
1264
1265
1266	/**
1267	* @callback_method_impl{FNSSMDEVSAVEEXEC}
1268	*/
1269	static DECLCALLBACK(int) pciR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
1270	{
1271	uint32_t i;
1272	PPCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
1273
1274	/*
1275	* Bus state data.
1276	*/
1277	SSMR3PutU32(pSSM, pThis->uConfigReg);
1278	SSMR3PutBool(pSSM, pThis->fUseIoApic);
1279
1280	/*
1281	* Save IRQ states.
1282	*/
1283	for (i = 0; i < PCI_IRQ_PINS; i++)
1284	SSMR3PutU32(pSSM, pThis->pci_irq_levels[i]);
1285	for (i = 0; i < PCI_APIC_IRQ_PINS; i++)
1286	SSMR3PutU32(pSSM, pThis->pci_apic_irq_levels[i]);
1287
1288	SSMR3PutU32(pSSM, pThis->acpi_irq_level);
1289	SSMR3PutS32(pSSM, pThis->acpi_irq);
1290
1291	SSMR3PutU32(pSSM, ~0); /* separator */
1292
1293	/*
1294	* Join paths with pcibridgeR3SaveExec.
1295	*/
1296	return pciR3CommonSaveExec(&pThis->PciBus, pSSM);
1297	}
1298
1299
1300	/**
1301	* Common routine for restoring the config registers of a PCI device.
1302	*
1303	* @param pDev The PCI device.
1304	* @param pbSrcConfig The configuration register values to be loaded.
1305	* @param fIsBridge Whether this is a bridge device or not.
1306	*/
1307	static void pciR3CommonRestoreConfig(PPCIDEVICE pDev, uint8_t const *pbSrcConfig, bool fIsBridge)
1308	{
1309	/*
1310	* This table defines the fields for normal devices and bridge devices, and
1311	* the order in which they need to be restored.
1312	*/
1313	static const struct PciField
1314	{
1315	uint8_t off;
1316	uint8_t cb;
1317	uint8_t fWritable;
1318	uint8_t fBridge;
1319	const char *pszName;
1320	} s_aFields[] =
1321	{
1322	/* off,cb,fW,fB, pszName */
1323	{ 0x00, 2, 0, 3, "VENDOR_ID" },
1324	{ 0x02, 2, 0, 3, "DEVICE_ID" },
1325	{ 0x06, 2, 1, 3, "STATUS" },
1326	{ 0x08, 1, 0, 3, "REVISION_ID" },
1327	{ 0x09, 1, 0, 3, "CLASS_PROG" },
1328	{ 0x0a, 1, 0, 3, "CLASS_SUB" },
1329	{ 0x0b, 1, 0, 3, "CLASS_BASE" },
1330	{ 0x0c, 1, 1, 3, "CACHE_LINE_SIZE" },
1331	{ 0x0d, 1, 1, 3, "LATENCY_TIMER" },
1332	{ 0x0e, 1, 0, 3, "HEADER_TYPE" },
1333	{ 0x0f, 1, 1, 3, "BIST" },
1334	{ 0x10, 4, 1, 3, "BASE_ADDRESS_0" },
1335	{ 0x14, 4, 1, 3, "BASE_ADDRESS_1" },
1336	{ 0x18, 4, 1, 1, "BASE_ADDRESS_2" },
1337	{ 0x18, 1, 1, 2, "PRIMARY_BUS" }, // fWritable = ??
1338	{ 0x19, 1, 1, 2, "SECONDARY_BUS" }, // fWritable = ??
1339	{ 0x1a, 1, 1, 2, "SUBORDINATE_BUS" }, // fWritable = ??
1340	{ 0x1b, 1, 1, 2, "SEC_LATENCY_TIMER" }, // fWritable = ??
1341	{ 0x1c, 4, 1, 1, "BASE_ADDRESS_3" },
1342	{ 0x1c, 1, 1, 2, "IO_BASE" }, // fWritable = ??
1343	{ 0x1d, 1, 1, 2, "IO_LIMIT" }, // fWritable = ??
1344	{ 0x1e, 2, 1, 2, "SEC_STATUS" }, // fWritable = ??
1345	{ 0x20, 4, 1, 1, "BASE_ADDRESS_4" },
1346	{ 0x20, 2, 1, 2, "MEMORY_BASE" }, // fWritable = ??
1347	{ 0x22, 2, 1, 2, "MEMORY_LIMIT" }, // fWritable = ??
1348	{ 0x24, 4, 1, 1, "BASE_ADDRESS_5" },
1349	{ 0x24, 2, 1, 2, "PREF_MEMORY_BASE" }, // fWritable = ??
1350	{ 0x26, 2, 1, 2, "PREF_MEMORY_LIMIT" }, // fWritable = ??
1351	{ 0x28, 4, 1, 1, "CARDBUS_CIS" }, // fWritable = ??
1352	{ 0x28, 4, 1, 2, "PREF_BASE_UPPER32" }, // fWritable = ??
1353	{ 0x2c, 2, 0, 1, "SUBSYSTEM_VENDOR_ID" },// fWritable = !?
1354	{ 0x2c, 4, 1, 2, "PREF_LIMIT_UPPER32" },// fWritable = ??
1355	{ 0x2e, 2, 0, 1, "SUBSYSTEM_ID" }, // fWritable = !?
1356	{ 0x30, 4, 1, 1, "ROM_ADDRESS" }, // fWritable = ?!
1357	{ 0x30, 2, 1, 2, "IO_BASE_UPPER16" }, // fWritable = ?!
1358	{ 0x32, 2, 1, 2, "IO_LIMIT_UPPER16" }, // fWritable = ?!
1359	{ 0x34, 4, 0, 3, "CAPABILITY_LIST" }, // fWritable = !? cb=!?
1360	{ 0x38, 4, 1, 1, "RESERVED_38" }, // ???
1361	{ 0x38, 4, 1, 2, "ROM_ADDRESS_BR" }, // fWritable = !? cb=!? fBridge=!?
1362	{ 0x3c, 1, 1, 3, "INTERRUPT_LINE" }, // fBridge=??
1363	{ 0x3d, 1, 0, 3, "INTERRUPT_PIN" }, // fBridge=??
1364	{ 0x3e, 1, 0, 1, "MIN_GNT" },
1365	{ 0x3e, 2, 1, 2, "BRIDGE_CONTROL" }, // fWritable = !?
1366	{ 0x3f, 1, 0, 1, "MAX_LAT" },
1367	/* The COMMAND register must come last as it requires the ADDRESS
1368	registers to be restored before we pretent to change it from 0 to
1369	whatever value the guest assigned it. */
1370	{ 0x04, 2, 1, 3, "COMMAND" },
1371	};
1372
1373	#ifdef RT_STRICT
1374	/* Check that we've got full register coverage. */
1375	uint32_t bmDevice[0x40 / 32];
1376	uint32_t bmBridge[0x40 / 32];
1377	RT_ZERO(bmDevice);
1378	RT_ZERO(bmBridge);
1379	for (uint32_t i = 0; i < RT_ELEMENTS(s_aFields); i++)
1380	{
1381	uint8_t off = s_aFields[i].off;
1382	uint8_t cb = s_aFields[i].cb;
1383	uint8_t f = s_aFields[i].fBridge;
1384	while (cb-- > 0)
1385	{
1386	if (f & 1) AssertMsg(!ASMBitTest(bmDevice, off), ("%#x\n", off));
1387	if (f & 2) AssertMsg(!ASMBitTest(bmBridge, off), ("%#x\n", off));
1388	if (f & 1) ASMBitSet(bmDevice, off);
1389	if (f & 2) ASMBitSet(bmBridge, off);
1390	off++;
1391	}
1392	}
1393	for (uint32_t off = 0; off < 0x40; off++)
1394	{
1395	AssertMsg(ASMBitTest(bmDevice, off), ("%#x\n", off));
1396	AssertMsg(ASMBitTest(bmBridge, off), ("%#x\n", off));
1397	}
1398	#endif
1399
1400	/*
1401	* Loop thru the fields covering the 64 bytes of standard registers.
1402	*/
1403	uint8_t const fBridge = fIsBridge ? 2 : 1;
1404	uint8_t *pbDstConfig = &pDev->config[0];
1405	for (uint32_t i = 0; i < RT_ELEMENTS(s_aFields); i++)
1406	if (s_aFields[i].fBridge & fBridge)
1407	{
1408	uint8_t const off = s_aFields[i].off;
1409	uint8_t const cb = s_aFields[i].cb;
1410	uint32_t u32Src;
1411	uint32_t u32Dst;
1412	switch (cb)
1413	{
1414	case 1:
1415	u32Src = pbSrcConfig[off];
1416	u32Dst = pbDstConfig[off];
1417	break;
1418	case 2:
1419	u32Src = (uint16_t const )&pbSrcConfig[off];
1420	u32Dst = (uint16_t const )&pbDstConfig[off];
1421	break;
1422	case 4:
1423	u32Src = (uint32_t const )&pbSrcConfig[off];
1424	u32Dst = (uint32_t const )&pbDstConfig[off];
1425	break;
1426	default:
1427	AssertFailed();
1428	continue;
1429	}
1430
1431	if ( u32Src != u32Dst
1432	\|\| off == VBOX_PCI_COMMAND)
1433	{
1434	if (u32Src != u32Dst)
1435	{
1436	if (!s_aFields[i].fWritable)
1437	LogRel(("PCI: %8s/%u: %2u-bit field %s: %x -> %x - !READ ONLY!\n",
1438	pDev->name, pDev->pDevIns->iInstance, cb*8, s_aFields[i].pszName, u32Dst, u32Src));
1439	else
1440	LogRel(("PCI: %8s/%u: %2u-bit field %s: %x -> %x\n",
1441	pDev->name, pDev->pDevIns->iInstance, cb*8, s_aFields[i].pszName, u32Dst, u32Src));
1442	}
1443	if (off == VBOX_PCI_COMMAND)
1444	PCIDevSetCommand(pDev, 0); /* For remapping, see pciR3CommonLoadExec. */
1445	pDev->Int.s.pfnConfigWrite(pDev, off, u32Src, cb);
1446	}
1447	}
1448
1449	/*
1450	* The device dependent registers.
1451	*
1452	* We will not use ConfigWrite here as we have no clue about the size
1453	* of the registers, so the device is responsible for correctly
1454	* restoring functionality governed by these registers.
1455	*/
1456	for (uint32_t off = 0x40; off < sizeof(pDev->config); off++)
1457	if (pbDstConfig[off] != pbSrcConfig[off])
1458	{
1459	LogRel(("PCI: %8s/%u: register %02x: %02x -> %02x\n",
1460	pDev->name, pDev->pDevIns->iInstance, off, pbDstConfig[off], pbSrcConfig[off])); /** @todo make this Log() later. */
1461	pbDstConfig[off] = pbSrcConfig[off];
1462	}
1463	}
1464
1465
1466	/**
1467	* Common worker for pciR3LoadExec and pcibridgeR3LoadExec.
1468	*
1469	* @returns VBox status code.
1470	* @param pBus The bus which data is being loaded.
1471	* @param pSSM The saved state handle.
1472	* @param uVersion The data version.
1473	* @param uPass The pass.
1474	*/
1475	static DECLCALLBACK(int) pciR3CommonLoadExec(PPCIBUS pBus, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1476	{
1477	uint32_t u32;
1478	uint32_t i;
1479	int rc;
1480
1481	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
1482
1483	/*
1484	* Iterate thru all the devices and write 0 to the COMMAND register so
1485	* that all the memory is unmapped before we start restoring the saved
1486	* mapping locations.
1487	*
1488	* The register value is restored afterwards so we can do proper
1489	* LogRels in pciR3CommonRestoreConfig.
1490	*/
1491	for (i = 0; i < RT_ELEMENTS(pBus->devices); i++)
1492	{
1493	PPCIDEVICE pDev = pBus->devices[i];
1494	if (pDev)
1495	{
1496	uint16_t u16 = PCIDevGetCommand(pDev);
1497	pDev->Int.s.pfnConfigWrite(pDev, VBOX_PCI_COMMAND, 0, 2);
1498	PCIDevSetCommand(pDev, u16);
1499	Assert(PCIDevGetCommand(pDev) == u16);
1500	}
1501	}
1502
1503	/*
1504	* Iterate all the devices.
1505	*/
1506	for (i = 0;; i++)
1507	{
1508	PCIDEVICE DevTmp;
1509	PPCIDEVICE pDev;
1510
1511	/* index / terminator */
1512	rc = SSMR3GetU32(pSSM, &u32);
1513	if (RT_FAILURE(rc))
1514	return rc;
1515	if (u32 == (uint32_t)~0)
1516	break;
1517	if ( u32 >= RT_ELEMENTS(pBus->devices)
1518	\|\| u32 < i)
1519	{
1520	AssertMsgFailed(("u32=%#x i=%#x\n", u32, i));
1521	return rc;
1522	}
1523
1524	/* skip forward to the device checking that no new devices are present. */
1525	for (; i < u32; i++)
1526	{
1527	if (pBus->devices[i])
1528	{
1529	LogRel(("PCI: New device in slot %#x, %s (vendor=%#06x device=%#06x)\n", i, pBus->devices[i]->name,
1530	PCIDevGetVendorId(pBus->devices[i]), PCIDevGetDeviceId(pBus->devices[i])));
1531	if (SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT)
1532	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("New device in slot %#x, %s (vendor=%#06x device=%#06x)"),
1533	i, pBus->devices[i]->name, PCIDevGetVendorId(pBus->devices[i]), PCIDevGetDeviceId(pBus->devices[i]));
1534	}
1535	}
1536
1537	/* get the data */
1538	DevTmp.Int.s.uIrqPinState = ~0; /* Invalid value in case we have an older saved state to force a state change in pciSetIrq. */
1539	SSMR3GetMem(pSSM, DevTmp.config, sizeof(DevTmp.config));
1540	if (uVersion < 3)
1541	{
1542	int32_t i32Temp;
1543	/* Irq value not needed anymore. */
1544	rc = SSMR3GetS32(pSSM, &i32Temp);
1545	if (RT_FAILURE(rc))
1546	return rc;
1547	}
1548	else
1549	{
1550	rc = SSMR3GetS32(pSSM, &DevTmp.Int.s.uIrqPinState);
1551	if (RT_FAILURE(rc))
1552	return rc;
1553	}
1554
1555	/* check that it's still around. */
1556	pDev = pBus->devices[i];
1557	if (!pDev)
1558	{
1559	LogRel(("PCI: Device in slot %#x has been removed! vendor=%#06x device=%#06x\n", i,
1560	PCIDevGetVendorId(&DevTmp), PCIDevGetDeviceId(&DevTmp)));
1561	if (SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT)
1562	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Device in slot %#x has been removed! vendor=%#06x device=%#06x"),
1563	i, PCIDevGetVendorId(&DevTmp), PCIDevGetDeviceId(&DevTmp));
1564	continue;
1565	}
1566
1567	/* match the vendor id assuming that this will never be changed. */
1568	if ( DevTmp.config[0] != pDev->config[0]
1569	\|\| DevTmp.config[1] != pDev->config[1])
1570	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Device in slot %#x (%s) vendor id mismatch! saved=%.4Rhxs current=%.4Rhxs"),
1571	i, pDev->name, DevTmp.config, pDev->config);
1572
1573	/* commit the loaded device config. */
1574	pciR3CommonRestoreConfig(pDev, &DevTmp.config[0], false ); /** @todo fix bridge fun! */
1575
1576	pDev->Int.s.uIrqPinState = DevTmp.Int.s.uIrqPinState;
1577	}
1578
1579	return VINF_SUCCESS;
1580	}
1581
1582
1583	/**
1584	* @callback_method_impl{FNSSMDEVLOADEXEC}
1585	*/
1586	static DECLCALLBACK(int) pciR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1587	{
1588	PPCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
1589	PPCIBUS pBus = &pThis->PciBus;
1590	uint32_t u32;
1591	int rc;
1592
1593	/*
1594	* Check the version.
1595	*/
1596	if (uVersion > VBOX_PCI_SAVED_STATE_VERSION)
1597	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1598	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
1599
1600	/*
1601	* Bus state data.
1602	*/
1603	SSMR3GetU32(pSSM, &pThis->uConfigReg);
1604	if (uVersion > 1)
1605	SSMR3GetBool(pSSM, &pThis->fUseIoApic);
1606
1607	/* Load IRQ states. */
1608	if (uVersion > 2)
1609	{
1610	for (uint8_t i = 0; i < PCI_IRQ_PINS; i++)
1611	SSMR3GetU32(pSSM, (uint32_t *)&pThis->pci_irq_levels[i]);
1612	for (uint8_t i = 0; i < PCI_APIC_IRQ_PINS; i++)
1613	SSMR3GetU32(pSSM, (uint32_t *)&pThis->pci_apic_irq_levels[i]);
1614
1615	SSMR3GetU32(pSSM, &pThis->acpi_irq_level);
1616	SSMR3GetS32(pSSM, &pThis->acpi_irq);
1617	}
1618
1619	/* separator */
1620	rc = SSMR3GetU32(pSSM, &u32);
1621	if (RT_FAILURE(rc))
1622	return rc;
1623	if (u32 != (uint32_t)~0)
1624	AssertMsgFailedReturn(("u32=%#x\n", u32), rc);
1625
1626	/*
1627	* The devices.
1628	*/
1629	return pciR3CommonLoadExec(pBus, pSSM, uVersion, uPass);
1630	}
1631
1632
1633	/* -=-=-=-=-=- PCI Bus Interface Methods (PDMPCIBUSREG) -=-=-=-=-=- */
1634
1635	/**
1636	* Registers the device with the specified PCI bus.
1637	*
1638	* @returns VBox status code.
1639	* @param pBus The bus to register with.
1640	* @param iDev The PCI device ordinal.
1641	* @param pPciDev The PCI device structure.
1642	* @param pszName Pointer to device name (permanent, readonly). For debugging, not unique.
1643	*/
1644	static int pciR3RegisterDeviceInternal(PPCIBUS pBus, int iDev, PPCIDEVICE pPciDev, const char *pszName)
1645	{
1646	/*
1647	* Find device slot.
1648	*/
1649	if (iDev < 0)
1650	{
1651	/*
1652	* Special check for the IDE controller which is our function 1 device
1653	* before searching.
1654	*/
1655	if ( !strcmp(pszName, "piix3ide")
1656	&& !pBus->devices[9])
1657	iDev = 9;
1658	/* LPC bus expected to be there by some guests, better make an additional argument to PDM
1659	device helpers, but requires significant rewrite */
1660	else if (!strcmp(pszName, "lpc")
1661	&& !pBus->devices[0xf8])
1662	iDev = 0xf8;
1663	else
1664	{
1665	Assert(!(pBus->iDevSearch % 8));
1666	for (iDev = pBus->iDevSearch; iDev < (int)RT_ELEMENTS(pBus->devices)-7; iDev += 8)
1667	if ( !pBus->devices[iDev]
1668	&& !pBus->devices[iDev + 1]
1669	&& !pBus->devices[iDev + 2]
1670	&& !pBus->devices[iDev + 3]
1671	&& !pBus->devices[iDev + 4]
1672	&& !pBus->devices[iDev + 5]
1673	&& !pBus->devices[iDev + 6]
1674	&& !pBus->devices[iDev + 7])
1675	break;
1676	if (iDev >= (int)RT_ELEMENTS(pBus->devices))
1677	{
1678	AssertMsgFailed(("Couldn't find free spot!\n"));
1679	return VERR_PDM_TOO_PCI_MANY_DEVICES;
1680	}
1681	}
1682	pciDevClearRequestedDevfunc(pPciDev);
1683	}
1684	else
1685	{
1686	/*
1687	* An explicit request.
1688	*
1689	* If the slot is occupied we'll have to relocate the device
1690	* currently occupying it first. This can only be done if the
1691	* existing device wasn't explicitly assigned. Also we limit
1692	* ourselves to function 0 devices.
1693	*
1694	* If you start setting devices + function in the
1695	* config, do it for all pci devices!
1696	*/
1697	//AssertReleaseMsg(iDev > 8 \|\| pBus->iBus != 0, ("iDev=%d pszName=%s\n", iDev, pszName));
1698	if (pBus->devices[iDev])
1699	{
1700	int iDevRel;
1701	AssertReleaseMsg(!(iDev % 8), ("PCI Configuration Conflict! iDev=%d pszName=%s clashes with %s\n",
1702	iDev, pszName, pBus->devices[iDev]->name));
1703	if ( pciDevIsRequestedDevfunc(pBus->devices[iDev])
1704	\|\| (pBus->devices[iDev + 1] && pciDevIsRequestedDevfunc(pBus->devices[iDev + 1]))
1705	\|\| (pBus->devices[iDev + 2] && pciDevIsRequestedDevfunc(pBus->devices[iDev + 2]))
1706	\|\| (pBus->devices[iDev + 3] && pciDevIsRequestedDevfunc(pBus->devices[iDev + 3]))
1707	\|\| (pBus->devices[iDev + 4] && pciDevIsRequestedDevfunc(pBus->devices[iDev + 4]))
1708	\|\| (pBus->devices[iDev + 5] && pciDevIsRequestedDevfunc(pBus->devices[iDev + 5]))
1709	\|\| (pBus->devices[iDev + 6] && pciDevIsRequestedDevfunc(pBus->devices[iDev + 6]))
1710	\|\| (pBus->devices[iDev + 7] && pciDevIsRequestedDevfunc(pBus->devices[iDev + 7])))
1711	{
1712	AssertReleaseMsgFailed(("Configuration error:'%s' and '%s' are both configured as device %d\n",
1713	pszName, pBus->devices[iDev]->name, iDev));
1714	return VERR_INTERNAL_ERROR;
1715	}
1716
1717	/* Find free slot for the device(s) we're moving and move them. */
1718	for (iDevRel = pBus->iDevSearch; iDevRel < (int)RT_ELEMENTS(pBus->devices)-7; iDevRel += 8)
1719	{
1720	if ( !pBus->devices[iDevRel]
1721	&& !pBus->devices[iDevRel + 1]
1722	&& !pBus->devices[iDevRel + 2]
1723	&& !pBus->devices[iDevRel + 3]
1724	&& !pBus->devices[iDevRel + 4]
1725	&& !pBus->devices[iDevRel + 5]
1726	&& !pBus->devices[iDevRel + 6]
1727	&& !pBus->devices[iDevRel + 7])
1728	{
1729	int i = 0;
1730	for (i = 0; i < 8; i++)
1731	{
1732	if (!pBus->devices[iDev + i])
1733	continue;
1734	Log(("PCI: relocating '%s' from slot %#x to %#x\n", pBus->devices[iDev + i]->name, iDev + i, iDevRel + i));
1735	pBus->devices[iDevRel + i] = pBus->devices[iDev + i];
1736	pBus->devices[iDevRel + i]->devfn = iDevRel + i;
1737	pBus->devices[iDev + i] = NULL;
1738	}
1739	}
1740	}
1741	if (pBus->devices[iDev])
1742	{
1743	AssertMsgFailed(("Couldn't find free spot!\n"));
1744	return VERR_PDM_TOO_PCI_MANY_DEVICES;
1745	}
1746	} /* if conflict */
1747	pciDevSetRequestedDevfunc(pPciDev);
1748	}
1749
1750	Assert(!pBus->devices[iDev]);
1751	pPciDev->devfn = iDev;
1752	pPciDev->name = pszName;
1753	pPciDev->Int.s.pBusR3 = pBus;
1754	pPciDev->Int.s.pBusR0 = MMHyperR3ToR0(PDMDevHlpGetVM(pBus->CTX_SUFF(pDevIns)), pBus);
1755	pPciDev->Int.s.pBusRC = MMHyperR3ToRC(PDMDevHlpGetVM(pBus->CTX_SUFF(pDevIns)), pBus);
1756	pPciDev->Int.s.pfnConfigRead = pci_default_read_config;
1757	pPciDev->Int.s.pfnConfigWrite = pci_default_write_config;
1758	pBus->devices[iDev] = pPciDev;
1759	if (pciDevIsPci2PciBridge(pPciDev))
1760	{
1761	AssertMsg(pBus->cBridges < RT_ELEMENTS(pBus->devices), ("Number of bridges exceeds the number of possible devices on the bus\n"));
1762	AssertMsg(pPciDev->Int.s.pfnBridgeConfigRead && pPciDev->Int.s.pfnBridgeConfigWrite,
1763	("device is a bridge but does not implement read/write functions\n"));
1764	pBus->papBridgesR3[pBus->cBridges] = pPciDev;
1765	pBus->cBridges++;
1766	}
1767
1768	Log(("PCI: Registered device %d function %d (%#x) '%s'.\n",
1769	iDev >> 3, iDev & 7, 0x80000000 \| (iDev << 8), pszName));
1770
1771	return VINF_SUCCESS;
1772	}
1773
1774
1775	/**
1776	* @interface_method_impl{PDMPCIBUSREG,pfnRegisterR3}
1777	*/
1778	static DECLCALLBACK(int) pciR3Register(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, const char *pszName, int iDev)
1779	{
1780	PPCIBUS pBus = DEVINS_2_PCIBUS(pDevIns);
1781
1782	/*
1783	* Check input.
1784	*/
1785	if ( !pszName
1786	\|\| !pPciDev
1787	\|\| iDev >= (int)RT_ELEMENTS(pBus->devices)
1788	\|\| (iDev >= 0 && iDev <= 8))
1789	{
1790	AssertMsgFailed(("Invalid argument! pszName=%s pPciDev=%p iDev=%d\n", pszName, pPciDev, iDev));
1791	return VERR_INVALID_PARAMETER;
1792	}
1793
1794	/*
1795	* Register the device.
1796	*/
1797	return pciR3RegisterDeviceInternal(pBus, iDev, pPciDev, pszName);
1798	}
1799
1800
1801	/**
1802	* @interface_method_impl{PDMPCIBUSREG,pfnIORegionRegisterR3}
1803	*/
1804	static DECLCALLBACK(int) pciR3CommonIORegionRegister(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iRegion, uint32_t cbRegion,
1805	PCIADDRESSSPACE enmType, PFNPCIIOREGIONMAP pfnCallback)
1806	{
1807	NOREF(pDevIns);
1808
1809	/*
1810	* Validate.
1811	*/
1812	AssertMsgReturn( enmType == PCI_ADDRESS_SPACE_MEM
1813	\|\| enmType == PCI_ADDRESS_SPACE_IO
1814	\|\| enmType == PCI_ADDRESS_SPACE_MEM_PREFETCH,
1815	("Invalid enmType=%#x? Or was this a bitmask after all...\n", enmType),
1816	VERR_INVALID_PARAMETER);
1817	AssertMsgReturn((unsigned)iRegion < PCI_NUM_REGIONS,
1818	("Invalid iRegion=%d PCI_NUM_REGIONS=%d\n", iRegion, PCI_NUM_REGIONS),
1819	VERR_INVALID_PARAMETER);
1820	int iLastSet = ASMBitLastSetU32(cbRegion);
1821	AssertMsgReturn( iLastSet != 0
1822	&& RT_BIT_32(iLastSet - 1) == cbRegion,
1823	("Invalid cbRegion=%#x iLastSet=%#x (not a power of 2 or 0)\n", cbRegion, iLastSet),
1824	VERR_INVALID_PARAMETER);
1825
1826	/*
1827	* Register the I/O region.
1828	*/
1829	PPCIIOREGION pRegion = &pPciDev->Int.s.aIORegions[iRegion];
1830	pRegion->addr = ~0U;
1831	pRegion->size = cbRegion;
1832	pRegion->type = enmType;
1833	pRegion->map_func = pfnCallback;
1834
1835	/* Set type in the config space. */
1836	uint32_t u32Address = 0x10 + iRegion * 4;
1837	uint32_t u32Value = (enmType == PCI_ADDRESS_SPACE_MEM_PREFETCH ? (1 << 3) : 0)
1838	\| (enmType == PCI_ADDRESS_SPACE_IO ? 1 : 0);
1839	(uint32_t )(pPciDev->config + u32Address) = RT_H2LE_U32(u32Value);
1840
1841	return VINF_SUCCESS;
1842	}
1843
1844
1845	/**
1846	* @interface_method_impl{PDMPCIBUSREG,pfnSetConfigCallbacksR3}
1847	*/
1848	static DECLCALLBACK(void)
1849	pciR3CommonSetConfigCallbacks(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PFNPCICONFIGREAD pfnRead, PPFNPCICONFIGREAD ppfnReadOld,
1850	PFNPCICONFIGWRITE pfnWrite, PPFNPCICONFIGWRITE ppfnWriteOld)
1851	{
1852	NOREF(pDevIns);
1853
1854	if (ppfnReadOld)
1855	*ppfnReadOld = pPciDev->Int.s.pfnConfigRead;
1856	pPciDev->Int.s.pfnConfigRead = pfnRead;
1857
1858	if (ppfnWriteOld)
1859	*ppfnWriteOld = pPciDev->Int.s.pfnConfigWrite;
1860	pPciDev->Int.s.pfnConfigWrite = pfnWrite;
1861	}
1862
1863
1864	/**
1865	* @interface_method_impl{PDMPCIBUSREG,pfnFakePCIBIOSR3}
1866	*/
1867	static DECLCALLBACK(int) pciR3FakePCIBIOS(PPDMDEVINS pDevIns)
1868	{
1869	unsigned i;
1870	uint8_t elcr[2] = {0, 0};
1871	PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
1872	PVM pVM = PDMDevHlpGetVM(pDevIns); Assert(pVM);
1873	PVMCPU pVCpu = PDMDevHlpGetVMCPU(pDevIns); Assert(pVM);
1874
1875	/*
1876	* Set the start addresses.
1877	*/
1878	pGlobals->pci_bios_io_addr = 0xd000;
1879	pGlobals->pci_bios_mem_addr = UINT32_C(0xf0000000);
1880	pGlobals->uBus = 0;
1881
1882	/*
1883	* Activate IRQ mappings.
1884	*/
1885	for (i = 0; i < 4; i++)
1886	{
1887	uint8_t irq = pci_irqs[i];
1888	/* Set to trigger level. */
1889	elcr[irq >> 3] \|= (1 << (irq & 7));
1890	/* Activate irq remapping in PIIX3. */
1891	pci_config_writeb(pGlobals, 0, pGlobals->PIIX3State.dev.devfn, 0x60 + i, irq);
1892	}
1893
1894	/* Tell to the PIC. */
1895	VBOXSTRICTRC rcStrict = IOMIOPortWrite(pVM, pVCpu, 0x4d0, elcr[0], sizeof(uint8_t));
1896	if (rcStrict == VINF_SUCCESS)
1897	rcStrict = IOMIOPortWrite(pVM, pVCpu, 0x4d1, elcr[1], sizeof(uint8_t));
1898	if (rcStrict != VINF_SUCCESS)
1899	{
1900	AssertMsgFailed(("Writing to PIC failed! rcStrict=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
1901	return RT_SUCCESS(rcStrict) ? VERR_INTERNAL_ERROR : VBOXSTRICTRC_VAL(rcStrict);
1902	}
1903
1904	/*
1905	* Init the devices.
1906	*/
1907	for (i = 0; i < 256; i++)
1908	{
1909	uint8_t aBridgePositions[256];
1910
1911	memset(aBridgePositions, 0, sizeof(aBridgePositions));
1912	Log2(("PCI: Initializing device %d (%#x)\n",
1913	i, 0x80000000 \| (i << 8)));
1914	pci_bios_init_device(pGlobals, 0, i, 0, aBridgePositions);
1915	}
1916
1917	return VINF_SUCCESS;
1918	}
1919
1920
1921	/* -=-=-=-=-=- Debug Info Handlers -=-=-=-=-=- */
1922
1923	/**
1924	* @callback_method_impl{FNDBGFHANDLERDEV}
1925	*/
1926	static DECLCALLBACK(void) pciR3IrqInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
1927	{
1928	PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
1929	NOREF(pszArgs);
1930
1931	uint16_t router = pGlobals->PIIX3State.dev.devfn;
1932	pHlp->pfnPrintf(pHlp, "PCI interrupt router at: %02X:%02X:%X\n",
1933	router >> 8, (router >> 3) & 0x1f, router & 0x7);
1934
1935	for (int i = 0; i < 4; ++i)
1936	{
1937	uint8_t irq_map = pci_config_readb(pGlobals, 0, router, 0x60 + i);
1938	if (irq_map & 0x80)
1939	pHlp->pfnPrintf(pHlp, "PIRQ%c disabled\n", 'A' + i);
1940	else
1941	pHlp->pfnPrintf(pHlp, "PIRQ%c -> IRQ%d\n", 'A' + i, irq_map & 0xf);
1942	}
1943	}
1944
1945	/**
1946	* Outputs indent.
1947	*
1948	* @param pHlp Output helpers.
1949	* @param iIndent Indentation level.
1950	*/
1951	static void pciR3PrintIndent(PCDBGFINFOHLP pHlp, int iIndent)
1952	{
1953	while (iIndent-- > 0)
1954	pHlp->pfnPrintf(pHlp, " ");
1955	}
1956
1957	/**
1958	* Recursive worker for pciR3Info.
1959	*
1960	* @param pBus The bus to display.
1961	* @param pHlp Output helpers.
1962	* @param iIndent Indentation level.
1963	* @param fRegisters Whether to also display the PCI configuration registers
1964	* of each device on the bus.
1965	*/
1966	static void pciR3BusInfo(PPCIBUS pBus, PCDBGFINFOHLP pHlp, int iIndent, bool fRegisters)
1967	{
1968	for (uint32_t iDev = 0; iDev < RT_ELEMENTS(pBus->devices); iDev++)
1969	{
1970	PPCIDEVICE pPciDev = pBus->devices[iDev];
1971	if (pPciDev != NULL)
1972	{
1973	pciR3PrintIndent(pHlp, iIndent);
1974
1975	/*
1976	* For passthrough devices MSI/MSI-X mostly reflects the way interrupts delivered to the guest,
1977	* as host driver handles real devices interrupts.
1978	*/
1979	pHlp->pfnPrintf(pHlp, "%02x:%02x:%02x %s%s: %04x-%04x%s%s",
1980	pBus->iBus, (iDev >> 3) & 0xff, iDev & 0x7,
1981	pPciDev->name,
1982	pciDevIsPassthrough(pPciDev) ? " (PASSTHROUGH)" : "",
1983	PCIDevGetWord(pPciDev, VBOX_PCI_VENDOR_ID), PCIDevGetWord(pPciDev, VBOX_PCI_DEVICE_ID),
1984	pciDevIsMsiCapable(pPciDev) ? " MSI" : "",
1985	pciDevIsMsixCapable(pPciDev) ? " MSI-X" : ""
1986	);
1987	if (PCIDevGetByte(pPciDev, VBOX_PCI_INTERRUPT_PIN) != 0)
1988	pHlp->pfnPrintf(pHlp, " IRQ%d", PCIDevGetByte(pPciDev, VBOX_PCI_INTERRUPT_LINE));
1989
1990	pHlp->pfnPrintf(pHlp, "\n");
1991
1992	uint16_t iCmd = PCIDevGetWord(pPciDev, VBOX_PCI_COMMAND);
1993	if ((iCmd & (VBOX_PCI_COMMAND_IO \| VBOX_PCI_COMMAND_MEMORY)) != 0)
1994	{
1995	for (int iRegion = 0; iRegion < PCI_NUM_REGIONS; iRegion++)
1996	{
1997	PCIIORegion* pRegion = &pPciDev->Int.s.aIORegions[iRegion];
1998	uint64_t iRegionSize = pRegion->size;
1999
2000	if (iRegionSize == 0)
2001	continue;
2002
2003	uint32_t u32Addr = PCIDevGetDWord(pPciDev, PCIDevGetRegionReg(iRegion));
2004	const char * pszDesc;
2005	char szDescBuf[128];
2006
2007	bool f64Bit = !!(pRegion->type & PCI_ADDRESS_SPACE_BAR64);
2008	if (pRegion->type & PCI_ADDRESS_SPACE_IO)
2009	{
2010	pszDesc = "IO";
2011	u32Addr &= ~0x3;
2012	}
2013	else
2014	{
2015	RTStrPrintf(szDescBuf, sizeof(szDescBuf), "MMIO%s%s",
2016	f64Bit ? "64" : "32",
2017	(pRegion->type & PCI_ADDRESS_SPACE_MEM_PREFETCH) ? " PREFETCH" : "");
2018	pszDesc = szDescBuf;
2019	u32Addr &= ~0xf;
2020	}
2021
2022	pciR3PrintIndent(pHlp, iIndent + 2);
2023	pHlp->pfnPrintf(pHlp, "%s region #%d: %x..%x\n",
2024	pszDesc, iRegion, u32Addr, u32Addr+iRegionSize);
2025	if (f64Bit)
2026	iRegion++;
2027	}
2028	}
2029
2030	pciR3PrintIndent(pHlp, iIndent + 2);
2031	uint16_t iStatus = PCIDevGetWord(pPciDev, VBOX_PCI_STATUS);
2032	pHlp->pfnPrintf(pHlp, "Command: %.Rhxs, Status: %.Rhxs\n",
2033	sizeof(uint16_t), &iCmd, sizeof(uint16_t), &iStatus);
2034	pciR3PrintIndent(pHlp, iIndent + 2);
2035	pHlp->pfnPrintf(pHlp, "Bus master: %s\n",
2036	iCmd & VBOX_PCI_COMMAND_MASTER ? "Yes" : "No");
2037
2038	if (fRegisters)
2039	{
2040	pciR3PrintIndent(pHlp, iIndent + 2);
2041	pHlp->pfnPrintf(pHlp, "PCI registers:\n");
2042	for (int iReg = 0; iReg < 0x100; )
2043	{
2044	int iPerLine = 0x10;
2045	Assert (0x100 % iPerLine == 0);
2046	pciR3PrintIndent(pHlp, iIndent + 3);
2047
2048	while (iPerLine-- > 0)
2049	{
2050	pHlp->pfnPrintf(pHlp, "%02x ", PCIDevGetByte(pPciDev, iReg++));
2051	}
2052	pHlp->pfnPrintf(pHlp, "\n");
2053	}
2054	}
2055	}
2056	}
2057
2058	if (pBus->cBridges > 0)
2059	{
2060	pciR3PrintIndent(pHlp, iIndent);
2061	pHlp->pfnPrintf(pHlp, "Registered %d bridges, subordinate buses info follows\n", pBus->cBridges);
2062	for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
2063	{
2064	PPCIBUS pBusSub = PDMINS_2_DATA(pBus->papBridgesR3[iBridge]->pDevIns, PPCIBUS);
2065	pciR3BusInfo(pBusSub, pHlp, iIndent + 1, fRegisters);
2066	}
2067	}
2068	}
2069
2070
2071	/**
2072	* @callback_method_impl{FNDBGFHANDLERDEV}
2073	*/
2074	static DECLCALLBACK(void) pciR3Info(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
2075	{
2076	PPCIBUS pBus = DEVINS_2_PCIBUS(pDevIns);
2077
2078	if (pszArgs == NULL \|\| !*pszArgs \|\| !strcmp(pszArgs, "basic"))
2079	pciR3BusInfo(pBus, pHlp, 0, false);
2080	else if (!strcmp(pszArgs, "verbose"))
2081	pciR3BusInfo(pBus, pHlp, 0, true);
2082	else
2083	pHlp->pfnPrintf(pHlp, "Invalid argument. Recognized arguments are 'basic', 'verbose'.\n");
2084	}
2085
2086
2087	/* -=-=-=-=-=- PDMDEVREG -=-=-=-=-=- */
2088
2089	/**
2090	* @interface_method_impl{PDMDEVREG,pfnRelocate}
2091	*/
2092	static DECLCALLBACK(void) pciR3Relocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
2093	{
2094	PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
2095	PPCIBUS pBus = &pGlobals->PciBus;
2096	pGlobals->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2097
2098	pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
2099	pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2100
2101	/* Relocate RC pointers for the attached pci devices. */
2102	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->devices); i++)
2103	{
2104	if (pBus->devices[i])
2105	pBus->devices[i]->Int.s.pBusRC += offDelta;
2106	}
2107	}
2108
2109
2110	/**
2111	* @interface_method_impl{PDMDEVREG,pfnReset}
2112	*/
2113	static DECLCALLBACK(void) pciR3Reset(PPDMDEVINS pDevIns)
2114	{
2115	pciR3FakePCIBIOS(pDevIns);
2116	}
2117
2118
2119	/**
2120	* @interface_method_impl{PDMDEVREG,pfnConstruct}
2121	*/
2122	static DECLCALLBACK(int) pciR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
2123	{
2124	Assert(iInstance == 0);
2125	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
2126
2127	/*
2128	* Validate and read configuration.
2129	*/
2130	if (!CFGMR3AreValuesValid(pCfg, "IOAPIC\0" "GCEnabled\0" "R0Enabled\0"))
2131	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
2132
2133	/* query whether we got an IOAPIC */
2134	bool fUseIoApic;
2135	int rc = CFGMR3QueryBoolDef(pCfg, "IOAPIC", &fUseIoApic, false);
2136	if (RT_FAILURE(rc))
2137	return PDMDEV_SET_ERROR(pDevIns, rc,
2138	N_("Configuration error: Failed to query boolean value \"IOAPIC\""));
2139
2140	/* check if RC code is enabled. */
2141	bool fGCEnabled;
2142	rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
2143	if (RT_FAILURE(rc))
2144	return PDMDEV_SET_ERROR(pDevIns, rc,
2145	N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
2146
2147	/* check if R0 code is enabled. */
2148	bool fR0Enabled;
2149	rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
2150	if (RT_FAILURE(rc))
2151	return PDMDEV_SET_ERROR(pDevIns, rc,
2152	N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
2153	Log(("PCI: fUseIoApic=%RTbool fGCEnabled=%RTbool fR0Enabled=%RTbool\n", fUseIoApic, fGCEnabled, fR0Enabled));
2154
2155	/*
2156	* Init data and register the PCI bus.
2157	*/
2158	PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
2159	pGlobals->pci_bios_io_addr = 0xc000;
2160	pGlobals->pci_bios_mem_addr = 0xf0000000;
2161	memset((void *)&pGlobals->pci_irq_levels, 0, sizeof(pGlobals->pci_irq_levels));
2162	pGlobals->fUseIoApic = fUseIoApic;
2163	memset((void *)&pGlobals->pci_apic_irq_levels, 0, sizeof(pGlobals->pci_apic_irq_levels));
2164
2165	pGlobals->pDevInsR3 = pDevIns;
2166	pGlobals->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2167	pGlobals->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2168
2169	pGlobals->PciBus.pDevInsR3 = pDevIns;
2170	pGlobals->PciBus.pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2171	pGlobals->PciBus.pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2172	pGlobals->PciBus.papBridgesR3 = (PPCIDEVICE *)PDMDevHlpMMHeapAllocZ(pDevIns, sizeof(PPCIDEVICE)
2173	* RT_ELEMENTS(pGlobals->PciBus.devices));
2174
2175	PDMPCIBUSREG PciBusReg;
2176	PPCIBUS pBus = &pGlobals->PciBus;
2177	PciBusReg.u32Version = PDM_PCIBUSREG_VERSION;
2178	PciBusReg.pfnRegisterR3 = pciR3Register;
2179	PciBusReg.pfnRegisterMsiR3 = NULL;
2180	PciBusReg.pfnIORegionRegisterR3 = pciR3CommonIORegionRegister;
2181	PciBusReg.pfnSetConfigCallbacksR3 = pciR3CommonSetConfigCallbacks;
2182	PciBusReg.pfnSetIrqR3 = pciSetIrq;
2183	PciBusReg.pfnFakePCIBIOSR3 = pciR3FakePCIBIOS;
2184	PciBusReg.pszSetIrqRC = fGCEnabled ? "pciSetIrq" : NULL;
2185	PciBusReg.pszSetIrqR0 = fR0Enabled ? "pciSetIrq" : NULL;
2186	rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBus->pPciHlpR3);
2187	if (RT_FAILURE(rc))
2188	return PDMDEV_SET_ERROR(pDevIns, rc,
2189	N_("Failed to register ourselves as a PCI Bus"));
2190	if (pBus->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
2191	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
2192	N_("PCI helper version mismatch; got %#x expected %#x"),
2193	pBus->pPciHlpR3->u32Version, PDM_PCIHLPR3_VERSION);
2194
2195	pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
2196	pBus->pPciHlpR0 = pBus->pPciHlpR3->pfnGetR0Helpers(pDevIns);
2197
2198	/* Disable default device locking. */
2199	rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
2200	AssertRCReturn(rc, rc);
2201
2202	/*
2203	* Fill in PCI configs and add them to the bus.
2204	*/
2205	/* i440FX */
2206	PCIDevSetVendorId( &pBus->PciDev, 0x8086); /* Intel */
2207	PCIDevSetDeviceId( &pBus->PciDev, 0x1237);
2208	PCIDevSetRevisionId(&pBus->PciDev, 0x02);
2209	PCIDevSetClassSub( &pBus->PciDev, 0x00); /* host2pci */
2210	PCIDevSetClassBase( &pBus->PciDev, 0x06); /* PCI_bridge */
2211	PCIDevSetHeaderType(&pBus->PciDev, 0x00);
2212
2213	pBus->PciDev.pDevIns = pDevIns;
2214	pciDevSetRequestedDevfunc(&pBus->PciDev);
2215	pciR3RegisterDeviceInternal(pBus, 0, &pBus->PciDev, "i440FX");
2216
2217	/* PIIX3 */
2218	PCIDevSetVendorId( &pGlobals->PIIX3State.dev, 0x8086); /* Intel */
2219	PCIDevSetDeviceId( &pGlobals->PIIX3State.dev, 0x7000); /* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */
2220	PCIDevSetClassSub( &pGlobals->PIIX3State.dev, 0x01); /* PCI_ISA */
2221	PCIDevSetClassBase( &pGlobals->PIIX3State.dev, 0x06); /* PCI_bridge */
2222	PCIDevSetHeaderType(&pGlobals->PIIX3State.dev, 0x80); /* PCI_multifunction, generic */
2223
2224	pGlobals->PIIX3State.dev.pDevIns = pDevIns;
2225	pciDevSetRequestedDevfunc(&pGlobals->PIIX3State.dev);
2226	pciR3RegisterDeviceInternal(pBus, 8, &pGlobals->PIIX3State.dev, "PIIX3");
2227	pciR3Piix3Reset(&pGlobals->PIIX3State);
2228
2229	pBus->iDevSearch = 16;
2230
2231	/*
2232	* Register I/O ports and save state.
2233	*/
2234	rc = PDMDevHlpIOPortRegister(pDevIns, 0x0cf8, 1, NULL, pciIOPortAddressWrite, pciIOPortAddressRead, NULL, NULL, "i440FX (PCI)");
2235	if (RT_FAILURE(rc))
2236	return rc;
2237	rc = PDMDevHlpIOPortRegister(pDevIns, 0x0cfc, 4, NULL, pciIOPortDataWrite, pciIOPortDataRead, NULL, NULL, "i440FX (PCI)");
2238	if (RT_FAILURE(rc))
2239	return rc;
2240	if (fGCEnabled)
2241	{
2242	rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x0cf8, 1, NIL_RTGCPTR, "pciIOPortAddressWrite", "pciIOPortAddressRead", NULL, NULL, "i440FX (PCI)");
2243	if (RT_FAILURE(rc))
2244	return rc;
2245	rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x0cfc, 4, NIL_RTGCPTR, "pciIOPortDataWrite", "pciIOPortDataRead", NULL, NULL, "i440FX (PCI)");
2246	if (RT_FAILURE(rc))
2247	return rc;
2248	}
2249	if (fR0Enabled)
2250	{
2251	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x0cf8, 1, NIL_RTR0PTR, "pciIOPortAddressWrite", "pciIOPortAddressRead", NULL, NULL, "i440FX (PCI)");
2252	if (RT_FAILURE(rc))
2253	return rc;
2254	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x0cfc, 4, NIL_RTR0PTR, "pciIOPortDataWrite", "pciIOPortDataRead", NULL, NULL, "i440FX (PCI)");
2255	if (RT_FAILURE(rc))
2256	return rc;
2257	}
2258
2259	rc = PDMDevHlpSSMRegisterEx(pDevIns, VBOX_PCI_SAVED_STATE_VERSION, sizeof(pBus) + 16128, "pgm",
2260	NULL, NULL, NULL,
2261	NULL, pciR3SaveExec, NULL,
2262	NULL, pciR3LoadExec, NULL);
2263	if (RT_FAILURE(rc))
2264	return rc;
2265
2266	PDMDevHlpDBGFInfoRegister(pDevIns, "pci",
2267	"Display PCI bus status. Recognizes 'basic' or 'verbose' as arguments, defaults to 'basic'.",
2268	pciR3Info);
2269	PDMDevHlpDBGFInfoRegister(pDevIns, "pciirq", "Display PCI IRQ routing state. (no arguments)", pciR3IrqInfo);
2270
2271	return VINF_SUCCESS;
2272	}
2273
2274
2275	/**
2276	* The device registration structure.
2277	*/
2278	const PDMDEVREG g_DevicePCI =
2279	{
2280	/* u32Version */
2281	PDM_DEVREG_VERSION,
2282	/* szName */
2283	"pci",
2284	/* szRCMod */
2285	"VBoxDDRC.rc",
2286	/* szR0Mod */
2287	"VBoxDDR0.r0",
2288	/* pszDescription */
2289	"i440FX PCI bridge and PIIX3 ISA bridge.",
2290	/* fFlags */
2291	PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
2292	/* fClass */
2293	PDM_DEVREG_CLASS_BUS_PCI \| PDM_DEVREG_CLASS_BUS_ISA,
2294	/* cMaxInstances */
2295	1,
2296	/* cbInstance */
2297	sizeof(PCIGLOBALS),
2298	/* pfnConstruct */
2299	pciR3Construct,
2300	/* pfnDestruct */
2301	NULL,
2302	/* pfnRelocate */
2303	pciR3Relocate,
2304	/* pfnMemSetup */
2305	NULL,
2306	/* pfnPowerOn */
2307	NULL,
2308	/* pfnReset */
2309	pciR3Reset,
2310	/* pfnSuspend */
2311	NULL,
2312	/* pfnResume */
2313	NULL,
2314	/* pfnAttach */
2315	NULL,
2316	/* pfnDetach */
2317	NULL,
2318	/* pfnQueryInterface */
2319	NULL,
2320	/* pfnInitComplete */
2321	NULL,
2322	/* pfnPowerOff */
2323	NULL,
2324	/* pfnSoftReset */
2325	NULL,
2326	/* u32VersionEnd */
2327	PDM_DEVREG_VERSION
2328
2329	};
2330	#endif /* IN_RING3 */
2331
2332
2333
2334	/* -=-=-=-=-=- The PCI bridge specific bits -=-=-=-=-=- */
2335
2336	/**
2337	* @interface_method_impl{PDMPCIBUSREG,pfnSetIrqR3}
2338	*/
2339	PDMBOTHCBDECL(void) pcibridgeSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel, uint32_t uTagSrc)
2340	{
2341	/*
2342	* The PCI-to-PCI bridge specification defines how the interrupt pins
2343	* are routed from the secondary to the primary bus (see chapter 9).
2344	* iIrq gives the interrupt pin the pci device asserted.
2345	* We change iIrq here according to the spec and call the SetIrq function
2346	* of our parent passing the device which asserted the interrupt instead of the device of the bridge.
2347	*/
2348	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
2349	PPCIDEVICE pPciDevBus = pPciDev;
2350	int iIrqPinBridge = iIrq;
2351	uint8_t uDevFnBridge = 0;
2352
2353	/* Walk the chain until we reach the host bus. */
2354	do
2355	{
2356	uDevFnBridge = pBus->PciDev.devfn;
2357	iIrqPinBridge = ((pPciDevBus->devfn >> 3) + iIrqPinBridge) & 3;
2358
2359	/* Get the parent. */
2360	pBus = pBus->PciDev.Int.s.CTX_SUFF(pBus);
2361	pPciDevBus = &pBus->PciDev;
2362	} while (pBus->iBus != 0);
2363
2364	AssertMsg(pBus->iBus == 0, ("This is not the host pci bus iBus=%d\n", pBus->iBus));
2365	pciSetIrqInternal(PCIBUS_2_PCIGLOBALS(pBus), uDevFnBridge, pPciDev, iIrqPinBridge, iLevel, uTagSrc);
2366	}
2367
2368	#ifdef IN_RING3
2369
2370	/**
2371	* @callback_method_impl{FNPCIBRIDGECONFIGWRITE}
2372	*/
2373	static DECLCALLBACK(void) pcibridgeR3ConfigWrite(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice, uint32_t u32Address, uint32_t u32Value, unsigned cb)
2374	{
2375	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
2376
2377	LogFlowFunc(("pDevIns=%p iBus=%d iDevice=%d u32Address=%u u32Value=%u cb=%d\n", pDevIns, iBus, iDevice, u32Address, u32Value, cb));
2378
2379	/* If the current bus is not the target bus search for the bus which contains the device. */
2380	if (iBus != pBus->PciDev.config[VBOX_PCI_SECONDARY_BUS])
2381	{
2382	PPCIDEVICE pBridgeDevice = pciR3FindBridge(pBus, iBus);
2383	if (pBridgeDevice)
2384	{
2385	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigWrite);
2386	pBridgeDevice->Int.s.pfnBridgeConfigWrite(pBridgeDevice->pDevIns, iBus, iDevice, u32Address, u32Value, cb);
2387	}
2388	}
2389	else
2390	{
2391	/* This is the target bus, pass the write to the device. */
2392	PPCIDEVICE pPciDev = pBus->devices[iDevice];
2393	if (pPciDev)
2394	{
2395	Log(("%s: %s: addr=%02x val=%08x len=%d\n", __FUNCTION__, pPciDev->name, u32Address, u32Value, cb));
2396	pPciDev->Int.s.pfnConfigWrite(pPciDev, u32Address, u32Value, cb);
2397	}
2398	}
2399	}
2400
2401
2402	/**
2403	* @callback_method_impl{FNPCIBRIDGECONFIGREAD}
2404	*/
2405	static DECLCALLBACK(uint32_t) pcibridgeR3ConfigRead(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice, uint32_t u32Address, unsigned cb)
2406	{
2407	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
2408	uint32_t u32Value = 0xffffffff; /* Return value in case there is no device. */
2409
2410	LogFlowFunc(("pDevIns=%p iBus=%d iDevice=%d u32Address=%u cb=%d\n", pDevIns, iBus, iDevice, u32Address, cb));
2411
2412	/* If the current bus is not the target bus search for the bus which contains the device. */
2413	if (iBus != pBus->PciDev.config[VBOX_PCI_SECONDARY_BUS])
2414	{
2415	PPCIDEVICE pBridgeDevice = pciR3FindBridge(pBus, iBus);
2416	if (pBridgeDevice)
2417	{
2418	AssertPtr( pBridgeDevice->Int.s.pfnBridgeConfigRead);
2419	u32Value = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->pDevIns, iBus, iDevice, u32Address, cb);
2420	}
2421	}
2422	else
2423	{
2424	/* This is the target bus, pass the read to the device. */
2425	PPCIDEVICE pPciDev = pBus->devices[iDevice];
2426	if (pPciDev)
2427	{
2428	u32Value = pPciDev->Int.s.pfnConfigRead(pPciDev, u32Address, cb);
2429	Log(("%s: %s: u32Address=%02x u32Value=%08x cb=%d\n", __FUNCTION__, pPciDev->name, u32Address, u32Value, cb));
2430	}
2431	}
2432
2433	return u32Value;
2434	}
2435
2436
2437	/**
2438	* @callback_method_impl{FNSSMDEVSAVEEXEC}
2439	*/
2440	static DECLCALLBACK(int) pcibridgeR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
2441	{
2442	PPCIBUS pThis = PDMINS_2_DATA(pDevIns, PPCIBUS);
2443	return pciR3CommonSaveExec(pThis, pSSM);
2444	}
2445
2446
2447	/**
2448	* @callback_method_impl{FNSSMDEVLOADEXEC}
2449	*/
2450	static DECLCALLBACK(int) pcibridgeR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2451	{
2452	PPCIBUS pThis = PDMINS_2_DATA(pDevIns, PPCIBUS);
2453	if (uVersion > VBOX_PCI_SAVED_STATE_VERSION)
2454	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2455	return pciR3CommonLoadExec(pThis, pSSM, uVersion, uPass);
2456	}
2457
2458
2459	/**
2460	* @interface_method_impl{PDMPCIBUSREG,pfnRegisterR3}
2461	*/
2462	static DECLCALLBACK(int) pcibridgeR3RegisterDevice(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, const char *pszName, int iDev)
2463	{
2464	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
2465
2466	/*
2467	* Check input.
2468	*/
2469	if ( !pszName
2470	\|\| !pPciDev
2471	\|\| iDev >= (int)RT_ELEMENTS(pBus->devices))
2472	{
2473	AssertMsgFailed(("Invalid argument! pszName=%s pPciDev=%p iDev=%d\n", pszName, pPciDev, iDev));
2474	return VERR_INVALID_PARAMETER;
2475	}
2476
2477	/*
2478	* Register the device.
2479	*/
2480	return pciR3RegisterDeviceInternal(pBus, iDev, pPciDev, pszName);
2481	}
2482
2483
2484	/**
2485	* @interface_method_impl{PDMDEVREG,pfnReset}
2486	*/
2487	static DECLCALLBACK(void) pcibridgeR3Reset(PPDMDEVINS pDevIns)
2488	{
2489	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
2490
2491	/* Reset config space to default values. */
2492	pBus->PciDev.config[VBOX_PCI_PRIMARY_BUS] = 0;
2493	pBus->PciDev.config[VBOX_PCI_SECONDARY_BUS] = 0;
2494	pBus->PciDev.config[VBOX_PCI_SUBORDINATE_BUS] = 0;
2495	}
2496
2497
2498	/**
2499	* @interface_method_impl{PDMDEVREG,pfnRelocate}
2500	*/
2501	static DECLCALLBACK(void) pcibridgeR3Relocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
2502	{
2503	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
2504	pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2505
2506	/* Relocate RC pointers for the attached pci devices. */
2507	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->devices); i++)
2508	{
2509	if (pBus->devices[i])
2510	pBus->devices[i]->Int.s.pBusRC += offDelta;
2511	}
2512	}
2513
2514
2515	/**
2516	* @interface_method_impl{PDMDEVREG,pfnConstruct}
2517	*/
2518	static DECLCALLBACK(int) pcibridgeR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
2519	{
2520	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
2521
2522	/*
2523	* Validate and read configuration.
2524	*/
2525	if (!CFGMR3AreValuesValid(pCfg, "GCEnabled\0" "R0Enabled\0"))
2526	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
2527
2528	/* check if RC code is enabled. */
2529	bool fGCEnabled;
2530	int rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
2531	if (RT_FAILURE(rc))
2532	return PDMDEV_SET_ERROR(pDevIns, rc,
2533	N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
2534
2535	/* check if R0 code is enabled. */
2536	bool fR0Enabled;
2537	rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
2538	if (RT_FAILURE(rc))
2539	return PDMDEV_SET_ERROR(pDevIns, rc,
2540	N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
2541	Log(("PCI: fGCEnabled=%RTbool fR0Enabled=%RTbool\n", fGCEnabled, fR0Enabled));
2542
2543	/*
2544	* Init data and register the PCI bus.
2545	*/
2546	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
2547	pBus->pDevInsR3 = pDevIns;
2548	pBus->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2549	pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2550	pBus->papBridgesR3 = (PPCIDEVICE )PDMDevHlpMMHeapAllocZ(pDevIns, sizeof(PPCIDEVICE) RT_ELEMENTS(pBus->devices));
2551
2552	PDMPCIBUSREG PciBusReg;
2553	PciBusReg.u32Version = PDM_PCIBUSREG_VERSION;
2554	PciBusReg.pfnRegisterR3 = pcibridgeR3RegisterDevice;
2555	PciBusReg.pfnRegisterMsiR3 = NULL;
2556	PciBusReg.pfnIORegionRegisterR3 = pciR3CommonIORegionRegister;
2557	PciBusReg.pfnSetConfigCallbacksR3 = pciR3CommonSetConfigCallbacks;
2558	PciBusReg.pfnSetIrqR3 = pcibridgeSetIrq;
2559	PciBusReg.pfnFakePCIBIOSR3 = NULL; /* Only needed for the first bus. */
2560	PciBusReg.pszSetIrqRC = fGCEnabled ? "pcibridgeSetIrq" : NULL;
2561	PciBusReg.pszSetIrqR0 = fR0Enabled ? "pcibridgeSetIrq" : NULL;
2562	rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBus->pPciHlpR3);
2563	if (RT_FAILURE(rc))
2564	return PDMDEV_SET_ERROR(pDevIns, rc,
2565	N_("Failed to register ourselves as a PCI Bus"));
2566	if (pBus->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
2567	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
2568	N_("PCI helper version mismatch; got %#x expected %#x"),
2569	pBus->pPciHlpR3->u32Version, PDM_PCIHLPR3_VERSION);
2570
2571	pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
2572	pBus->pPciHlpR0 = pBus->pPciHlpR3->pfnGetR0Helpers(pDevIns);
2573
2574	/*
2575	* Fill in PCI configs and add them to the bus.
2576	*/
2577	PCIDevSetVendorId( &pBus->PciDev, 0x8086); /* Intel */
2578	PCIDevSetDeviceId( &pBus->PciDev, 0x2448); /* 82801 Mobile PCI bridge. */
2579	PCIDevSetRevisionId(&pBus->PciDev, 0xf2);
2580	PCIDevSetClassSub( &pBus->PciDev, 0x04); /* pci2pci */
2581	PCIDevSetClassBase( &pBus->PciDev, 0x06); /* PCI_bridge */
2582	PCIDevSetClassProg( &pBus->PciDev, 0x01); /* Supports subtractive decoding. */
2583	PCIDevSetHeaderType(&pBus->PciDev, 0x01); /* Single function device which adheres to the PCI-to-PCI bridge spec. */
2584	PCIDevSetCommand( &pBus->PciDev, 0x00);
2585	PCIDevSetStatus( &pBus->PciDev, 0x20); /* 66MHz Capable. */
2586	PCIDevSetInterruptLine(&pBus->PciDev, 0x00); /* This device does not assert interrupts. */
2587
2588	/*
2589	* This device does not generate interrupts. Interrupt delivery from
2590	* devices attached to the bus is unaffected.
2591	*/
2592	PCIDevSetInterruptPin(&pBus->PciDev, 0x00);
2593
2594	pBus->PciDev.pDevIns = pDevIns;
2595
2596	/* Bridge-specific data */
2597	pciDevSetPci2PciBridge(&pBus->PciDev);
2598	pBus->PciDev.Int.s.pfnBridgeConfigRead = pcibridgeR3ConfigRead;
2599	pBus->PciDev.Int.s.pfnBridgeConfigWrite = pcibridgeR3ConfigWrite;
2600
2601	/*
2602	* Register this PCI bridge. The called function will take care on which bus we will get registered.
2603	*/
2604	rc = PDMDevHlpPCIRegister(pDevIns, &pBus->PciDev);
2605	if (RT_FAILURE(rc))
2606	return rc;
2607
2608	pBus->iDevSearch = 0;
2609	/*
2610	* The iBus property doesn't really represent the bus number
2611	* because the guest and the BIOS can choose different bus numbers
2612	* for them.
2613	* The bus number is mainly for the setIrq function to indicate
2614	* when the host bus is reached which will have iBus = 0.
2615	* That's why the + 1.
2616	*/
2617	pBus->iBus = iInstance + 1;
2618
2619	/*
2620	* Register SSM handlers. We use the same saved state version as for the host bridge
2621	* to make changes easier.
2622	*/
2623	rc = PDMDevHlpSSMRegisterEx(pDevIns, VBOX_PCI_SAVED_STATE_VERSION, sizeof(pBus) + 16128, "pgm",
2624	NULL, NULL, NULL,
2625	NULL, pcibridgeR3SaveExec, NULL,
2626	NULL, pcibridgeR3LoadExec, NULL);
2627	if (RT_FAILURE(rc))
2628	return rc;
2629
2630	return VINF_SUCCESS;
2631	}
2632
2633
2634	/**
2635	* The device registration structure
2636	* for the PCI-to-PCI bridge.
2637	*/
2638	const PDMDEVREG g_DevicePCIBridge =
2639	{
2640	/* u32Version */
2641	PDM_DEVREG_VERSION,
2642	/* szName */
2643	"pcibridge",
2644	/* szRCMod */
2645	"VBoxDDRC.rc",
2646	/* szR0Mod */
2647	"VBoxDDR0.r0",
2648	/* pszDescription */
2649	"82801 Mobile PCI to PCI bridge",
2650	/* fFlags */
2651	PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
2652	/* fClass */
2653	PDM_DEVREG_CLASS_BUS_PCI,
2654	/* cMaxInstances */
2655	~0U,
2656	/* cbInstance */
2657	sizeof(PCIBUS),
2658	/* pfnConstruct */
2659	pcibridgeR3Construct,
2660	/* pfnDestruct */
2661	NULL,
2662	/* pfnRelocate */
2663	pcibridgeR3Relocate,
2664	/* pfnMemSetup */
2665	NULL,
2666	/* pfnPowerOn */
2667	NULL,
2668	/* pfnReset */
2669	pcibridgeR3Reset,
2670	/* pfnSuspend */
2671	NULL,
2672	/* pfnResume */
2673	NULL,
2674	/* pfnAttach */
2675	NULL,
2676	/* pfnDetach */
2677	NULL,
2678	/* pfnQueryInterface */
2679	NULL,
2680	/* pfnInitComplete */
2681	NULL,
2682	/* pfnPowerOff */
2683	NULL,
2684	/* pfnSoftReset */
2685	NULL,
2686	/* u32VersionEnd */
2687	PDM_DEVREG_VERSION
2688	};
2689
2690	#endif /* IN_RING3 */
2691	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */

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source: vbox/trunk/src/VBox/Devices/Bus/DevPCI.cpp@ 61541

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