VirtualBox

source: vbox/trunk/src/VBox/Devices/Bus/DevPCI.cpp@ 11118

Last change on this file since 11118 was 10202, checked in by vboxsync, 16 years ago

removed VBOX_WITH_PDM_LOCK
  • Property svn:eol-style set to native
File size: 54.6 KB
Line 
1/* $Id: $ */
2/** @file
3 * PCI BUS Device.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 * --------------------------------------------------------------------
21 *
22 * This code is based on:
23 *
24 * QEMU PCI bus manager
25 *
26 * Copyright (c) 2004 Fabrice Bellard
27 *
28 * Permission is hereby granted, free of charge, to any person obtaining a copy
29 * of this software and associated documentation files (the "Software"), to deal
30 * in the Software without restriction, including without limitation the rights
31 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
32 * copies of the Software, and to permit persons to whom the Software is
33 * furnished to do so, subject to the following conditions:
34 *
35 * The above copyright notice and this permission notice shall be included in
36 * all copies or substantial portions of the Software.
37 *
38 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
39 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
40 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
41 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
42 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
43 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
44 * THE SOFTWARE.
45 */
46
47/*******************************************************************************
48* Header Files *
49*******************************************************************************/
50#define LOG_GROUP LOG_GROUP_DEV_PCI
51/* Hack to get PCIDEVICEINT declare at the right point - include "PCIInternal.h". */
52#define PCI_INCLUDE_PRIVATE
53#include <VBox/pci.h>
54#include <VBox/pdmdev.h>
55#include <iprt/assert.h>
56#include <iprt/string.h>
57
58#include "Builtins.h"
59
60
61/*******************************************************************************
62* Defined Constants And Macros *
63*******************************************************************************/
64/** @def PCI_LOCK
65 * Acquires the PDM lock. This is a NOP if locking is disabled. */
66/** @def PCI_UNLOCK
67 * Releases the PDM lock. This is a NOP if locking is disabled. */
68#define PCI_LOCK(pDevIns, rc) \
69 do { \
70 int rc2 = PDMINS2DATA(pDevIns, PCIBus *)->CTXALLSUFF(pPciHlp)->pfnLock((pDevIns), rc); \
71 if (rc2 != VINF_SUCCESS) \
72 return rc2; \
73 } while (0)
74#define PCI_UNLOCK(pDevIns) \
75 PDMINS2DATA(pDevIns, PCIBus *)->CTXALLSUFF(pPciHlp)->pfnUnlock(pDevIns)
76
77
78/*******************************************************************************
79* Structures and Typedefs *
80*******************************************************************************/
81/**
82 * PIIX3 ISA Bridge state.
83 */
84typedef struct PIIX3State
85{
86 /** The PCI device of the bridge. */
87 PCIDEVICE dev;
88} PIIX3State, PIIX3, *PPIIX3;
89
90
91/** Maximum number of PCI devices.
92 * Defined like this to make interrupt handling simple. */
93#define PCI_DEVICES_MAX 64
94/** Number of uint32_t entries needed make a bitmask of the interrupts. */
95#define PCI_IRQ_WORDS ((PCI_DEVICES_MAX + 31) / 32)
96
97/**
98 * PCI Globals.
99 *
100 * @remark
101 * These are currently put in the PCIBus structure since we've
102 * only got one PCI bus in the current VM configurations. This
103 * makes life somewhat simpler in GC.
104 */
105typedef struct PCIGLOBALS
106{
107 /** Irq levels for the four PCI Irqs. */
108 uint32_t pci_irq_levels[4][PCI_IRQ_WORDS];
109 /** The base address for PCI assigned MMIO addresses. */
110 RTGCPHYS32 pci_mem_base;
111 /** The next I/O port address which the PCI BIOS will use. */
112 uint32_t pci_bios_io_addr;
113 /** The next MMIO address which the PCI BIOS will use. */
114 uint32_t pci_bios_mem_addr;
115 /** I/O APIC usage flag */
116 bool fUseIoApic;
117 /** I/O APIC irq levels */
118 uint32_t pci_apic_irq_levels[8][PCI_IRQ_WORDS];
119 /** ACPI IRQ level */
120 uint32_t acpi_irq_level;
121 /** ACPI PIC IRQ */
122 int acpi_irq;
123} PCIGLOBALS;
124/** Pointer to per VM data. */
125typedef PCIGLOBALS *PPCIGLOBALS;
126
127
128/**
129 * PCI Bus instance.
130 */
131typedef struct PCIBus
132{
133 /** IRQ index */
134 uint32_t uIrqIndex;
135 /** Bus number. */
136 int32_t iBus;
137 /** Start device number. */
138 int32_t iDevSearch;
139 /** Config register. */
140 uint32_t uConfigReg;
141 /** Array of PCI devices. */
142 R3PTRTYPE(PPCIDEVICE) devices[256];
143
144 /** HC pointer to the device instance. */
145 R3R0PTRTYPE(PPDMDEVINS) pDevInsHC;
146 /** Pointer to the PCI R3 helpers. */
147 PCPDMPCIHLPR3 pPciHlpR3;
148
149 /** GC pointer to the device instance. */
150 PPDMDEVINSGC pDevInsGC;
151 /** Pointer to the PCI GC helpers. */
152 PCPDMPCIHLPGC pPciHlpGC;
153 /** Pointer to the PCI R0 helpers. */
154 PCPDMPCIHLPR0 pPciHlpR0;
155
156 /** The PCI device for the PCI bridge. */
157 PCIDEVICE PciDev;
158 /** ISA bridge state. */
159 PIIX3 PIIX3State;
160 /** The global data.
161 * Since we've only got one bus at present, we put it here to keep things simple. */
162 PCIGLOBALS Globals;
163} PCIBUS;
164/** Pointer to a PCIBUS instance. */
165typedef PCIBUS *PPCIBUS;
166typedef PCIBUS PCIBus;
167
168
169/** Converts a bus instance pointer to a device instance pointer. */
170#define PCIBUS2DEVINS(pPciBus) ((pPciBus)->CTXSUFF(pDevIns))
171/** Converts a device instance pointer to a PCIGLOBALS pointer. */
172#define DEVINS2PCIGLOBALS(pDevIns) ((PPCIGLOBALS)(&PDMINS2DATA(pDevIns, PPCIBUS)->Globals))
173/** Converts a bus instance pointer to a PCIGLOBALS pointer. */
174#define PCIBUS2PCIGLOBALS(pPciBus) ((PPCIGLOBALS)(&pPciBus->Globals))
175
176
177#ifndef VBOX_DEVICE_STRUCT_TESTCASE
178/*******************************************************************************
179* Internal Functions *
180*******************************************************************************/
181__BEGIN_DECLS
182
183PDMBOTHCBDECL(void) pciSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel);
184
185__END_DECLS
186
187
188#define DEBUG_PCI
189
190#define PCI_VENDOR_ID 0x00 /* 16 bits */
191#define PCI_DEVICE_ID 0x02 /* 16 bits */
192#define PCI_COMMAND 0x04 /* 16 bits */
193#define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
194#define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
195#define PCI_CLASS_DEVICE 0x0a /* Device class */
196#define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
197#define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
198#define PCI_MIN_GNT 0x3e /* 8 bits */
199#define PCI_MAX_LAT 0x3f /* 8 bits */
200
201#ifdef IN_RING3
202
203static void pci_addr_writel(PCIBus *s, uint32_t addr, uint32_t val)
204{
205 s->uConfigReg = val;
206}
207
208static uint32_t pci_addr_readl(PCIBus *s, uint32_t addr)
209{
210 return s->uConfigReg;
211}
212
213static void pci_update_mappings(PCIDevice *d)
214{
215 PPCIBUS pBus = d->Int.s.pBus;
216 PCIIORegion *r;
217 int cmd, i;
218 uint32_t last_addr, new_addr, config_ofs;
219
220 cmd = RT_LE2H_U16(*(uint16_t *)(d->config + PCI_COMMAND));
221 for(i = 0; i < PCI_NUM_REGIONS; i++) {
222 r = &d->Int.s.aIORegions[i];
223 if (i == PCI_ROM_SLOT) {
224 config_ofs = 0x30;
225 } else {
226 config_ofs = 0x10 + i * 4;
227 }
228 if (r->size != 0) {
229 if (r->type & PCI_ADDRESS_SPACE_IO) {
230 if (cmd & PCI_COMMAND_IO) {
231 new_addr = RT_LE2H_U32(*(uint32_t *)(d->config +
232 config_ofs));
233 new_addr = new_addr & ~(r->size - 1);
234 last_addr = new_addr + r->size - 1;
235 /* NOTE: we have only 64K ioports on PC */
236 if (last_addr <= new_addr || new_addr == 0 ||
237 last_addr >= 0x10000) {
238 new_addr = ~0U;
239 }
240 } else {
241 new_addr = ~0U;
242 }
243 } else {
244 if (cmd & PCI_COMMAND_MEMORY) {
245 new_addr = RT_LE2H_U32(*(uint32_t *)(d->config +
246 config_ofs));
247 /* the ROM slot has a specific enable bit */
248 if (i == PCI_ROM_SLOT && !(new_addr & 1))
249 goto no_mem_map;
250 new_addr = new_addr & ~(r->size - 1);
251 last_addr = new_addr + r->size - 1;
252 /* NOTE: we do not support wrapping */
253 /* XXX: as we cannot support really dynamic
254 mappings, we handle specific values as invalid
255 mappings. */
256 if (last_addr <= new_addr || new_addr == 0 ||
257 last_addr == ~0U) {
258 new_addr = ~0U;
259 }
260 } else {
261 no_mem_map:
262 new_addr = ~0U;
263 }
264 }
265 /* now do the real mapping */
266 if (new_addr != r->addr) {
267 if (r->addr != ~0U) {
268 if (r->type & PCI_ADDRESS_SPACE_IO) {
269 int devclass;
270 /* NOTE: specific hack for IDE in PC case:
271 only one byte must be mapped. */
272 devclass = d->config[0x0a] | (d->config[0x0b] << 8);
273 if (devclass == 0x0101 && r->size == 4) {
274 int rc = d->pDevIns->pDevHlp->pfnIOPortDeregister(d->pDevIns, r->addr + 2, 1);
275 AssertRC(rc);
276 } else {
277 int rc = d->pDevIns->pDevHlp->pfnIOPortDeregister(d->pDevIns, r->addr, r->size);
278 AssertRC(rc);
279 }
280 } else {
281 RTGCPHYS GCPhysBase = r->addr + PCIBUS2PCIGLOBALS(pBus)->pci_mem_base;
282 int rc;
283 if (pBus->pPciHlpR3->pfnIsMMIO2Base(pBus->pDevInsHC, d->pDevIns, GCPhysBase))
284 {
285 /* unmap it. */
286 rc = r->map_func(d, i, NIL_RTGCPHYS, r->size, (PCIADDRESSSPACE)(r->type));
287 AssertRC(rc);
288 rc = PDMDevHlpMMIO2Unmap(d->pDevIns, i, GCPhysBase);
289 }
290 else
291 rc = d->pDevIns->pDevHlp->pfnMMIODeregister(d->pDevIns, GCPhysBase, r->size);
292 AssertMsgRC(rc, ("rc=%Rrc d=%s i=%d GCPhysBase=%RGp size=%#x\n", rc, d->name, i, GCPhysBase, r->size));
293 }
294 }
295 r->addr = new_addr;
296 if (r->addr != ~0U) {
297 int rc = r->map_func(d, i,
298 r->addr + (r->type & PCI_ADDRESS_SPACE_IO ? 0 : PCIBUS2PCIGLOBALS(pBus)->pci_mem_base),
299 r->size, (PCIADDRESSSPACE)(r->type));
300 AssertRC(rc);
301 }
302 }
303 }
304 }
305}
306
307
308static DECLCALLBACK(uint32_t) pci_default_read_config(PCIDevice *d, uint32_t address, unsigned len)
309{
310 uint32_t val;
311 switch(len) {
312 case 1:
313 val = d->config[address];
314 break;
315 case 2:
316 val = RT_LE2H_U16(*(uint16_t *)(d->config + address));
317 break;
318 default:
319 case 4:
320 val = RT_LE2H_U32(*(uint32_t *)(d->config + address));
321 break;
322 }
323 return val;
324}
325
326static DECLCALLBACK(void) pci_default_write_config(PCIDevice *d, uint32_t address, uint32_t val, unsigned len)
327{
328 int can_write;
329 unsigned i;
330 uint32_t end, addr;
331
332 if (len == 4 && ((address >= 0x10 && address < 0x10 + 4 * 6) ||
333 (address >= 0x30 && address < 0x34))) {
334 PCIIORegion *r;
335 int reg;
336
337 if ( address >= 0x30 ) {
338 reg = PCI_ROM_SLOT;
339 }else{
340 reg = (address - 0x10) >> 2;
341 }
342 r = &d->Int.s.aIORegions[reg];
343 if (r->size == 0)
344 goto default_config;
345 /* compute the stored value */
346 if (reg == PCI_ROM_SLOT) {
347 /* keep ROM enable bit */
348 val &= (~(r->size - 1)) | 1;
349 } else {
350 val &= ~(r->size - 1);
351 val |= r->type;
352 }
353 *(uint32_t *)(d->config + address) = RT_H2LE_U32(val);
354 pci_update_mappings(d);
355 return;
356 }
357 default_config:
358 /* not efficient, but simple */
359 addr = address;
360 for(i = 0; i < len; i++) {
361 /* default read/write accesses */
362 switch(d->config[0x0e]) {
363 case 0x00:
364 case 0x80:
365 switch(addr) {
366 case 0x00:
367 case 0x01:
368 case 0x02:
369 case 0x03:
370 case 0x08:
371 case 0x09:
372 case 0x0a:
373 case 0x0b:
374 case 0x0e:
375 case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17: /* base */
376 case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f:
377 case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27:
378 case 0x30: case 0x31: case 0x32: case 0x33: /* rom */
379 case 0x3d:
380 can_write = 0;
381 break;
382 default:
383 can_write = 1;
384 break;
385 }
386 break;
387 default:
388 case 0x01:
389 switch(addr) {
390 case 0x00:
391 case 0x01:
392 case 0x02:
393 case 0x03:
394 case 0x08:
395 case 0x09:
396 case 0x0a:
397 case 0x0b:
398 case 0x0e:
399 case 0x38: case 0x39: case 0x3a: case 0x3b: /* rom */
400 case 0x3d:
401 can_write = 0;
402 break;
403 default:
404 can_write = 1;
405 break;
406 }
407 break;
408 }
409#ifdef VBOX
410 /* status register: only clear bits by writing a '1' at the corresponding bit */
411 if (addr == 0x06)
412 {
413 d->config[addr] &= ~val;
414 d->config[addr] |= 0x08; /* interrupt status */
415 }
416 else if (addr == 0x07)
417 {
418 d->config[addr] &= ~val;
419 }
420 else
421#endif
422 if (can_write) {
423 d->config[addr] = val;
424 }
425 addr++;
426 val >>= 8;
427 }
428
429 end = address + len;
430 if (end > PCI_COMMAND && address < (PCI_COMMAND + 2)) {
431 /* if the command register is modified, we must modify the mappings */
432 pci_update_mappings(d);
433 }
434}
435
436static void pci_data_write(PCIBus *s, uint32_t addr, uint32_t val, int len)
437{
438 PCIDevice *pci_dev;
439 int config_addr, iBus;
440
441 Log(("pci_data_write: addr=%08x val=%08x len=%d\n", s->uConfigReg, val, len));
442
443 if (!(s->uConfigReg & (1 << 31))) {
444 return;
445 }
446 if ((s->uConfigReg & 0x3) != 0) {
447 return;
448 }
449 iBus = (s->uConfigReg >> 16) & 0xff;
450 if (iBus != 0)
451 return;
452 pci_dev = s->devices[(s->uConfigReg >> 8) & 0xff];
453 if (!pci_dev)
454 return;
455 config_addr = (s->uConfigReg & 0xfc) | (addr & 3);
456 Log(("pci_config_write: %s: addr=%02x val=%08x len=%d\n", pci_dev->name, config_addr, val, len));
457 pci_dev->Int.s.pfnConfigWrite(pci_dev, config_addr, val, len);
458}
459
460static uint32_t pci_data_read(PCIBus *s, uint32_t addr, int len)
461{
462 PCIDevice *pci_dev;
463 int config_addr, iBus;
464 uint32_t val;
465
466 if (!(s->uConfigReg & (1 << 31)))
467 goto fail;
468 if ((s->uConfigReg & 0x3) != 0)
469 goto fail;
470 iBus = (s->uConfigReg >> 16) & 0xff;
471 if (iBus != 0)
472 goto fail;
473 pci_dev = s->devices[(s->uConfigReg >> 8) & 0xff];
474 if (!pci_dev) {
475 fail:
476 switch(len) {
477 case 1:
478 val = 0xff;
479 break;
480 case 2:
481 val = 0xffff;
482 break;
483 default:
484 case 4:
485 val = 0xffffffff;
486 break;
487 }
488 goto the_end;
489 }
490 config_addr = (s->uConfigReg & 0xfc) | (addr & 3);
491 val = pci_dev->Int.s.pfnConfigRead(pci_dev, config_addr, len);
492 Log(("pci_config_read: %s: addr=%02x val=%08x len=%d\n", pci_dev->name, config_addr, val, len));
493 the_end:
494 return val;
495}
496
497#endif /* IN_RING3 */
498
499
500/* return the global irq number corresponding to a given device irq
501 pin. We could also use the bus number to have a more precise
502 mapping. */
503static inline int pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num)
504{
505 int slot_addend;
506 slot_addend = (pci_dev->devfn >> 3) - 1;
507 return (irq_num + slot_addend) & 3;
508}
509
510static inline int pci_slot_get_apic_pirq(PCIDevice *pci_dev, int irq_num)
511{
512 return (irq_num + (pci_dev->devfn >> 3)) & 7;
513}
514
515static inline int get_pci_irq_apic_level(PPCIGLOBALS pGlobals, int irq_num)
516{
517 int apic_level;
518 apic_level = ((pGlobals->pci_apic_irq_levels[irq_num][0] |
519 pGlobals->pci_apic_irq_levels[irq_num][1]) != 0);
520 return apic_level;
521}
522
523static void apic_set_irq(PPCIBUS pBus, PCIDevice *pci_dev, int irq_num1, int level, int acpi_irq)
524{
525 if (acpi_irq == -1) {
526 int shift, apic_irq, apic_level;
527 uint32_t *p;
528 PPCIGLOBALS pGlobals = PCIBUS2PCIGLOBALS(pBus);
529 int uIrqIndex = pci_dev->Int.s.iIrq;
530 int irq_num = pci_slot_get_apic_pirq(pci_dev, irq_num1);
531
532 p = &pGlobals->pci_apic_irq_levels[irq_num][uIrqIndex >> 5];
533 shift = (uIrqIndex & 0x1f);
534 *p = (*p & ~(1 << shift)) | ((level & PDM_IRQ_LEVEL_HIGH) << shift);
535 apic_irq = irq_num + 0x10;
536 apic_level = get_pci_irq_apic_level(pGlobals, irq_num);
537 Log3(("apic_set_irq: %s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d\n",
538 HCSTRING(pci_dev->name), irq_num1, level, apic_irq, apic_level, irq_num));
539 pBus->CTXALLSUFF(pPciHlp)->pfnIoApicSetIrq(CTXSUFF(pBus->pDevIns), apic_irq, apic_level);
540
541 if ((level & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP) {
542 *p = (*p & ~(1 << shift));
543 apic_level = get_pci_irq_apic_level(pGlobals, irq_num);
544 Log3(("apic_set_irq: %s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d (flop)\n",
545 HCSTRING(pci_dev->name), irq_num1, level, apic_irq, apic_level, irq_num));
546 pBus->CTXALLSUFF(pPciHlp)->pfnIoApicSetIrq(CTXSUFF(pBus->pDevIns), apic_irq, apic_level);
547 }
548 } else {
549 Log3(("apic_set_irq: %s: irq_num1=%d level=%d acpi_irq=%d\n",
550 HCSTRING(pci_dev->name), irq_num1, level, acpi_irq));
551 pBus->CTXALLSUFF(pPciHlp)->pfnIoApicSetIrq(CTXSUFF(pBus->pDevIns), acpi_irq, level);
552 }
553}
554
555static inline int get_pci_irq_level(PPCIGLOBALS pGlobals, int irq_num)
556{
557 int pic_level;
558#if (PCI_IRQ_WORDS == 2)
559 pic_level = ((pGlobals->pci_irq_levels[irq_num][0] |
560 pGlobals->pci_irq_levels[irq_num][1]) != 0);
561#else
562 {
563 int i;
564 pic_level = 0;
565 for(i = 0; i < PCI_IRQ_WORDS; i++) {
566 if (pGlobals->pci_irq_levels[irq_num][i]) {
567 pic_level = 1;
568 break;
569 }
570 }
571 }
572#endif
573 return pic_level;
574}
575
576/**
577 * Set the IRQ for a PCI device.
578 *
579 * @param pDevIns Device instance of the PCI Bus.
580 * @param pPciDev The PCI device structure.
581 * @param iIrq IRQ number to set.
582 * @param iLevel IRQ level.
583 */
584PDMBOTHCBDECL(void) pciSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel)
585{
586 PPCIBUS pBus = PDMINS2DATA(pDevIns, PPCIBUS);
587 PPCIGLOBALS pGlobals = PCIBUS2PCIGLOBALS(pBus);
588 uint8_t *pbCfg = pBus->PIIX3State.dev.config;
589 const bool fIsAcpiDevice = pPciDev->config[2] == 0x13 && pPciDev->config[3] == 0x71;
590 const bool fIsApicEnabled = pGlobals->fUseIoApic && pbCfg[0xde] == 0xbe && pbCfg[0xad] == 0xef;
591 int pic_irq, pic_level;
592 uint32_t *p;
593
594 /* apic only */
595 if (fIsApicEnabled)
596 {
597 if (fIsAcpiDevice)
598 /*
599 * ACPI needs special treatment since SCI is hardwired and
600 * should not be affected by PCI IRQ routing tables at the
601 * same time SCI IRQ is shared in PCI sense hence this
602 * kludge (i.e. we fetch the hardwired value from ACPIs
603 * PCI device configuration space).
604 */
605 apic_set_irq(pBus, pPciDev, -1, iLevel, pPciDev->config[0x3c]);
606 else
607 apic_set_irq(pBus, pPciDev, iIrq, iLevel, -1);
608 return;
609 }
610
611 if (fIsAcpiDevice)
612 {
613 /* As per above treat ACPI in a special way */
614 pic_irq = pPciDev->config[0x3c];
615 pGlobals->acpi_irq = pic_irq;
616 pGlobals->acpi_irq_level = iLevel & PDM_IRQ_LEVEL_HIGH;
617 }
618 else
619 {
620 int shift, irq_num, uIrqIndex;
621 irq_num = pci_slot_get_pirq(pPciDev, iIrq);
622 uIrqIndex = pPciDev->Int.s.iIrq;
623 p = &pGlobals->pci_irq_levels[irq_num][uIrqIndex >> 5];
624 shift = (uIrqIndex & 0x1f);
625 *p = (*p & ~(1 << shift)) | ((iLevel & PDM_IRQ_LEVEL_HIGH) << shift);
626
627 /* now we change the pic irq level according to the piix irq mappings */
628 pic_irq = pbCfg[0x60 + irq_num];
629 if (pic_irq >= 16)
630 {
631 if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP)
632 *p = (*p & ~(1 << shift));
633 return;
634 }
635 }
636
637 /* the pic level is the logical OR of all the PCI irqs mapped to it */
638 pic_level = 0;
639 if (pic_irq == pbCfg[0x60])
640 pic_level |= get_pci_irq_level(pGlobals, 0);
641 if (pic_irq == pbCfg[0x61])
642 pic_level |= get_pci_irq_level(pGlobals, 1);
643 if (pic_irq == pbCfg[0x62])
644 pic_level |= get_pci_irq_level(pGlobals, 2);
645 if (pic_irq == pbCfg[0x63])
646 pic_level |= get_pci_irq_level(pGlobals, 3);
647 if (pic_irq == pGlobals->acpi_irq)
648 pic_level |= pGlobals->acpi_irq_level;
649
650 Log3(("piix3_set_irq: %s: iLevel=%d iIrq=%d pic_irq=%d pic_level=%d\n",
651 HCSTRING(pPciDev->name), iLevel, iIrq, pic_irq, pic_level));
652 pBus->CTXALLSUFF(pPciHlp)->pfnIsaSetIrq(CTXSUFF(pBus->pDevIns), pic_irq, pic_level);
653
654 /** @todo optimize pci irq flip-flop some rainy day. */
655 if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP)
656 pciSetIrq(pDevIns, pPciDev, iIrq, PDM_IRQ_LEVEL_LOW);
657}
658
659#ifdef IN_RING3
660
661static void piix3_reset(PIIX3State *d)
662{
663 uint8_t *pci_conf = d->dev.config;
664
665 pci_conf[0x04] = 0x07; /* master, memory and I/O */
666 pci_conf[0x05] = 0x00;
667 pci_conf[0x06] = 0x00;
668 pci_conf[0x07] = 0x02; /* PCI_status_devsel_medium */
669 pci_conf[0x4c] = 0x4d;
670 pci_conf[0x4e] = 0x03;
671 pci_conf[0x4f] = 0x00;
672 pci_conf[0x60] = 0x80;
673 pci_conf[0x69] = 0x02;
674 pci_conf[0x70] = 0x80;
675 pci_conf[0x76] = 0x0c;
676 pci_conf[0x77] = 0x0c;
677 pci_conf[0x78] = 0x02;
678 pci_conf[0x79] = 0x00;
679 pci_conf[0x80] = 0x00;
680 pci_conf[0x82] = 0x02; /* Get rid of the Linux guest "Enabling Passive Release" PCI quirk warning. */
681 pci_conf[0xa0] = 0x08;
682 pci_conf[0xa0] = 0x08;
683 pci_conf[0xa2] = 0x00;
684 pci_conf[0xa3] = 0x00;
685 pci_conf[0xa4] = 0x00;
686 pci_conf[0xa5] = 0x00;
687 pci_conf[0xa6] = 0x00;
688 pci_conf[0xa7] = 0x00;
689 pci_conf[0xa8] = 0x0f;
690 pci_conf[0xaa] = 0x00;
691 pci_conf[0xab] = 0x00;
692 pci_conf[0xac] = 0x00;
693 pci_conf[0xae] = 0x00;
694}
695
696static void pci_config_writel(PCIDevice *d, uint32_t addr, uint32_t val)
697{
698 PCIBus *s = d->Int.s.pBus;
699 s->uConfigReg = 0x80000000 | (s->iBus << 16) |
700 (d->devfn << 8) | addr;
701 pci_data_write(s, 0, val, 4);
702}
703
704static void pci_config_writew(PCIDevice *d, uint32_t addr, uint32_t val)
705{
706 PCIBus *s = d->Int.s.pBus;
707 s->uConfigReg = 0x80000000 | (s->iBus << 16) |
708 (d->devfn << 8) | (addr & ~3);
709 pci_data_write(s, addr & 3, val, 2);
710}
711
712static void pci_config_writeb(PCIDevice *d, uint32_t addr, uint32_t val)
713{
714 PCIBus *s = d->Int.s.pBus;
715 s->uConfigReg = 0x80000000 | (s->iBus << 16) |
716 (d->devfn << 8) | (addr & ~3);
717 pci_data_write(s, addr & 3, val, 1);
718}
719
720static uint32_t pci_config_readw(PCIDevice *d, uint32_t addr)
721{
722 PCIBus *s = d->Int.s.pBus;
723 s->uConfigReg = 0x80000000 | (s->iBus << 16) |
724 (d->devfn << 8) | (addr & ~3);
725 return pci_data_read(s, addr & 3, 2);
726}
727
728static uint32_t pci_config_readb(PCIDevice *d, uint32_t addr)
729{
730 PCIBus *s = d->Int.s.pBus;
731 s->uConfigReg = 0x80000000 | (s->iBus << 16) |
732 (d->devfn << 8) | (addr & ~3);
733 return pci_data_read(s, addr & 3, 1);
734}
735
736/* host irqs corresponding to PCI irqs A-D */
737static const uint8_t pci_irqs[4] = { 11, 9, 11, 9 }; /* bird: added const */
738
739static void pci_set_io_region_addr(PCIDevice *d, int region_num, uint32_t addr)
740{
741 PCIIORegion *r;
742 uint16_t cmd;
743 uint32_t ofs;
744
745 if ( region_num == PCI_ROM_SLOT ) {
746 ofs = 0x30;
747 }else{
748 ofs = 0x10 + region_num * 4;
749 }
750
751 pci_config_writel(d, ofs, addr);
752 r = &d->Int.s.aIORegions[region_num];
753
754 /* enable memory mappings */
755 cmd = pci_config_readw(d, PCI_COMMAND);
756 if ( region_num == PCI_ROM_SLOT )
757 cmd |= 2;
758 else if (r->type & PCI_ADDRESS_SPACE_IO)
759 cmd |= 1;
760 else
761 cmd |= 2;
762 pci_config_writew(d, PCI_COMMAND, cmd);
763}
764
765static void pci_bios_init_device(PCIDevice *d)
766{
767 int devclass;
768 PCIIORegion *r;
769 uint32_t *paddr;
770 int i, pin, pic_irq, vendor_id, device_id;
771
772 devclass = pci_config_readw(d, PCI_CLASS_DEVICE);
773 vendor_id = pci_config_readw(d, PCI_VENDOR_ID);
774 device_id = pci_config_readw(d, PCI_DEVICE_ID);
775 switch(devclass)
776 {
777 case 0x0101:
778 if (vendor_id == 0x8086 &&
779 (device_id == 0x7010 || device_id == 0x7111)) {
780 /* PIIX3 or PIIX4 IDE */
781 pci_config_writew(d, 0x40, 0x8000); /* enable IDE0 */
782 pci_config_writew(d, 0x42, 0x8000); /* enable IDE1 */
783 goto default_map;
784 } else {
785 /* IDE: we map it as in ISA mode */
786 pci_set_io_region_addr(d, 0, 0x1f0);
787 pci_set_io_region_addr(d, 1, 0x3f4);
788 pci_set_io_region_addr(d, 2, 0x170);
789 pci_set_io_region_addr(d, 3, 0x374);
790 }
791 break;
792 case 0x0300:
793 if (vendor_id != 0x80ee)
794 goto default_map;
795 /* VGA: map frame buffer to default Bochs VBE address */
796 pci_set_io_region_addr(d, 0, 0xE0000000);
797 break;
798 case 0x0800:
799 /* PIC */
800 vendor_id = pci_config_readw(d, PCI_VENDOR_ID);
801 device_id = pci_config_readw(d, PCI_DEVICE_ID);
802 if (vendor_id == 0x1014) {
803 /* IBM */
804 if (device_id == 0x0046 || device_id == 0xFFFF) {
805 /* MPIC & MPIC2 */
806 pci_set_io_region_addr(d, 0, 0x80800000 + 0x00040000);
807 }
808 }
809 break;
810 case 0xff00:
811 if (vendor_id == 0x0106b &&
812 (device_id == 0x0017 || device_id == 0x0022)) {
813 /* macio bridge */
814 pci_set_io_region_addr(d, 0, 0x80800000);
815 }
816 break;
817 default:
818 default_map:
819 /* default memory mappings */
820 for(i = 0; i < PCI_NUM_REGIONS; i++) {
821 r = &d->Int.s.aIORegions[i];
822
823 if (r->size) {
824 if (r->type & PCI_ADDRESS_SPACE_IO)
825 paddr = &PCIBUS2PCIGLOBALS(d->Int.s.pBus)->pci_bios_io_addr;
826 else
827 paddr = &PCIBUS2PCIGLOBALS(d->Int.s.pBus)->pci_bios_mem_addr;
828 *paddr = (*paddr + r->size - 1) & ~(r->size - 1);
829 pci_set_io_region_addr(d, i, *paddr);
830 *paddr += r->size;
831 }
832 }
833 break;
834 }
835
836 /* map the interrupt */
837 pin = pci_config_readb(d, PCI_INTERRUPT_PIN);
838 if (pin != 0) {
839 pin = pci_slot_get_pirq(d, pin - 1);
840 pic_irq = pci_irqs[pin];
841 pci_config_writeb(d, PCI_INTERRUPT_LINE, pic_irq);
842 }
843}
844
845/* -=-=-=-=-=- wrappers -=-=-=-=-=- */
846
847/**
848 * Port I/O Handler for PCI address OUT operations.
849 *
850 * @returns VBox status code.
851 *
852 * @param pDevIns The device instance.
853 * @param pvUser User argument - ignored.
854 * @param uPort Port number used for the IN operation.
855 * @param u32 The value to output.
856 * @param cb The value size in bytes.
857 */
858static DECLCALLBACK(int) pciIOPortAddressWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
859{
860 Log(("pciIOPortAddressWrite: Port=%#x u32=%#x cb=%d\n", Port, u32, cb));
861 NOREF(pvUser);
862 if (cb == 4)
863 {
864 PCI_LOCK(pDevIns, VINF_IOM_HC_IOPORT_WRITE);
865 pci_addr_writel(PDMINS2DATA(pDevIns, PCIBus *), Port, u32);
866 PCI_UNLOCK(pDevIns);
867 }
868 /* else: 440FX does "pass through to the bus" for other writes, what ever that means.
869 * Linux probes for cmd640 using byte writes/reads during ide init. We'll just ignore it. */
870 return VINF_SUCCESS;
871}
872
873/**
874 * Port I/O Handler for PCI address IN operations.
875 *
876 * @returns VBox status code.
877 *
878 * @param pDevIns The device instance.
879 * @param pvUser User argument - ignored.
880 * @param uPort Port number used for the IN operation.
881 * @param pu32 Where to store the result.
882 * @param cb Number of bytes read.
883 */
884static DECLCALLBACK(int) pciIOPortAddressRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
885{
886 NOREF(pvUser);
887 if (cb == 4)
888 {
889 PCI_LOCK(pDevIns, VINF_IOM_HC_IOPORT_READ);
890 *pu32 = pci_addr_readl(PDMINS2DATA(pDevIns, PCIBus *), Port);
891 PCI_UNLOCK(pDevIns);
892 Log(("pciIOPortAddressRead: Port=%#x cb=%d -> %#x\n", Port, cb, *pu32));
893 return VINF_SUCCESS;
894 }
895 /* else: 440FX does "pass through to the bus" for other writes, what ever that means.
896 * Linux probes for cmd640 using byte writes/reads during ide init. We'll just ignore it. */
897 Log(("pciIOPortAddressRead: Port=%#x cb=%d VERR_IOM_IOPORT_UNUSED\n", Port, cb));
898 return VERR_IOM_IOPORT_UNUSED;
899}
900
901
902/**
903 * Port I/O Handler for PCI data OUT operations.
904 *
905 * @returns VBox status code.
906 *
907 * @param pDevIns The device instance.
908 * @param pvUser User argument - ignored.
909 * @param uPort Port number used for the IN operation.
910 * @param u32 The value to output.
911 * @param cb The value size in bytes.
912 */
913static DECLCALLBACK(int) pciIOPortDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
914{
915 Log(("pciIOPortDataWrite: Port=%#x u32=%#x cb=%d\n", Port, u32, cb));
916 NOREF(pvUser);
917 if (!(Port % cb))
918 {
919 PCI_LOCK(pDevIns, VINF_IOM_HC_IOPORT_WRITE);
920 pci_data_write(PDMINS2DATA(pDevIns, PCIBus *), Port, u32, cb);
921 PCI_UNLOCK(pDevIns);
922 }
923 else
924 AssertMsgFailed(("Write to port %#x u32=%#x cb=%d\n", Port, u32, cb));
925 return VINF_SUCCESS;
926}
927
928
929/**
930 * Port I/O Handler for PCI data IN operations.
931 *
932 * @returns VBox status code.
933 *
934 * @param pDevIns The device instance.
935 * @param pvUser User argument - ignored.
936 * @param uPort Port number used for the IN operation.
937 * @param pu32 Where to store the result.
938 * @param cb Number of bytes read.
939 */
940static DECLCALLBACK(int) pciIOPortDataRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
941{
942 NOREF(pvUser);
943 if (!(Port % cb))
944 {
945 PCI_LOCK(pDevIns, VINF_IOM_HC_IOPORT_READ);
946 *pu32 = pci_data_read(PDMINS2DATA(pDevIns, PCIBus *), Port, cb);
947 PCI_UNLOCK(pDevIns);
948 Log(("pciIOPortDataRead: Port=%#x cb=%#x -> %#x\n", Port, cb, *pu32));
949 return VINF_SUCCESS;
950 }
951 AssertMsgFailed(("Read from port %#x cb=%d\n", Port, cb));
952 return VERR_IOM_IOPORT_UNUSED;
953}
954
955
956/**
957 * Saves a state of the PCI device.
958 *
959 * @returns VBox status code.
960 * @param pDevIns Device instance of the PCI Bus.
961 * @param pPciDev Pointer to PCI device.
962 * @param pSSMHandle The handle to save the state to.
963 */
964static DECLCALLBACK(int) pciGenericSaveExec(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PSSMHANDLE pSSMHandle)
965{
966 return SSMR3PutMem(pSSMHandle, &pPciDev->config[0], sizeof(pPciDev->config));
967}
968
969
970/**
971 * Loads a saved PCI device state.
972 *
973 * @returns VBox status code.
974 * @param pDevIns Device instance of the PCI Bus.
975 * @param pPciDev Pointer to PCI device.
976 * @param pSSMHandle The handle to the saved state.
977 */
978static DECLCALLBACK(int) pciGenericLoadExec(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PSSMHANDLE pSSMHandle)
979{
980 return SSMR3GetMem(pSSMHandle, &pPciDev->config[0], sizeof(pPciDev->config));
981}
982
983
984/**
985 * Saves a state of the PCI device.
986 *
987 * @returns VBox status code.
988 * @param pDevIns The device instance.
989 * @param pPciDev Pointer to PCI device.
990 * @param pSSMHandle The handle to save the state to.
991 */
992static DECLCALLBACK(int) pciSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle)
993{
994 uint32_t i;
995 PPCIBUS pData = PDMINS2DATA(pDevIns, PPCIBUS);
996 PPCIGLOBALS pGlobals = PCIBUS2PCIGLOBALS(pData);
997
998 /*
999 * Bus state data.
1000 */
1001 SSMR3PutU32(pSSMHandle, pData->uConfigReg);
1002 SSMR3PutBool(pSSMHandle, pGlobals->fUseIoApic);
1003 SSMR3PutU32(pSSMHandle, ~0); /* separator */
1004
1005 /*
1006 * Iterate all the devices.
1007 */
1008 for (i = 0; i < ELEMENTS(pData->devices); i++)
1009 {
1010 PPCIDEVICE pDev = pData->devices[i];
1011 if (pDev)
1012 {
1013 int rc;
1014 SSMR3PutU32(pSSMHandle, i);
1015 SSMR3PutMem(pSSMHandle, pDev->config, sizeof(pDev->config));
1016 rc = SSMR3PutS32(pSSMHandle, pDev->Int.s.iIrq);
1017 if (VBOX_FAILURE(rc))
1018 return rc;
1019 }
1020 }
1021 return SSMR3PutU32(pSSMHandle, ~0); /* terminator */
1022}
1023
1024/**
1025 * Loads a saved PCI device state.
1026 *
1027 * @returns VBox status code.
1028 * @param pDevIns The device instance.
1029 * @param pSSMHandle The handle to the saved state.
1030 * @param u32Version The data unit version number.
1031 */
1032static DECLCALLBACK(int) pciLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle, uint32_t u32Version)
1033{
1034 PPCIBUS pData = PDMINS2DATA(pDevIns, PPCIBUS);
1035 PPCIGLOBALS pGlobals = PCIBUS2PCIGLOBALS(pData);
1036 uint32_t u32;
1037 uint32_t i;
1038 int rc;
1039
1040 /*
1041 * Check the version.
1042 */
1043 if (u32Version > 2)
1044 {
1045 AssertFailed();
1046 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1047 }
1048
1049 /*
1050 * Bus state data.
1051 */
1052 SSMR3GetU32(pSSMHandle, &pData->uConfigReg);
1053 if (u32Version > 1)
1054 SSMR3GetBool(pSSMHandle, &pGlobals->fUseIoApic);
1055
1056 /* separator */
1057 rc = SSMR3GetU32(pSSMHandle, &u32);
1058 if (VBOX_FAILURE(rc))
1059 return rc;
1060 if (u32 != (uint32_t)~0)
1061 AssertMsgFailedReturn(("u32=%#x\n", u32), rc);
1062
1063 /*
1064 * Iterate all the devices.
1065 */
1066 for (i = 0;; i++)
1067 {
1068 PCIDEVICE DevTmp;
1069 PPCIDEVICE pDev;
1070
1071 /* index / terminator */
1072 rc = SSMR3GetU32(pSSMHandle, &u32);
1073 if (VBOX_FAILURE(rc))
1074 return rc;
1075 if (u32 == (uint32_t)~0)
1076 break;
1077 if ( u32 >= ELEMENTS(pData->devices)
1078 || u32 < i)
1079 {
1080 AssertMsgFailed(("u32=%#x i=%#x\n", u32, i));
1081 return rc;
1082 }
1083
1084 /* skip forward to the device checking that no new devices are present. */
1085 for (; i < u32; i++)
1086 {
1087 if (pData->devices[i])
1088 {
1089 LogRel(("New device in slot %#x, %s (vendor=%#06x device=%#06x)\n", i, pData->devices[i]->name,
1090 PCIDevGetVendorId(pData->devices[i]), PCIDevGetDeviceId(pData->devices[i])));
1091 if (SSMR3HandleGetAfter(pSSMHandle) != SSMAFTER_DEBUG_IT)
1092 AssertFailedReturn(VERR_SSM_LOAD_CONFIG_MISMATCH);
1093 }
1094 }
1095
1096 /* get the data */
1097 SSMR3GetMem(pSSMHandle, DevTmp.config, sizeof(DevTmp.config));
1098 rc = SSMR3GetS32(pSSMHandle, &DevTmp.Int.s.iIrq);
1099 if (VBOX_FAILURE(rc))
1100 return rc;
1101
1102 /* check that it's still around. */
1103 pDev = pData->devices[i];
1104 if (!pDev)
1105 {
1106 LogRel(("Device in slot %#x has been removed! vendor=%#06x device=%#06x\n", i,
1107 PCIDevGetVendorId(&DevTmp), PCIDevGetDeviceId(&DevTmp)));
1108 if (SSMR3HandleGetAfter(pSSMHandle) != SSMAFTER_DEBUG_IT)
1109 AssertFailedReturn(VERR_SSM_LOAD_CONFIG_MISMATCH);
1110 continue;
1111 }
1112
1113 /* match the vendor id assuming that this will never be changed. */
1114 if ( DevTmp.config[0] != pDev->config[0]
1115 || DevTmp.config[1] != pDev->config[1])
1116 {
1117 LogRel(("Device in slot %#x (%s) vendor id mismatch! saved=%.4Vhxs current=%.4Vhxs\n",
1118 i, pDev->name, DevTmp.config, pDev->config));
1119 AssertFailedReturn(VERR_SSM_LOAD_CONFIG_MISMATCH);
1120 }
1121
1122 /* commit the loaded device config. */
1123 memcpy(pDev->config, DevTmp.config, sizeof(pDev->config));
1124 if (DevTmp.Int.s.iIrq >= PCI_DEVICES_MAX)
1125 {
1126 LogRel(("Device %s: Too many devices %d (max=%d)\n", pDev->name, DevTmp.Int.s.iIrq, PCI_DEVICES_MAX));
1127 AssertFailedReturn(VERR_TOO_MUCH_DATA);
1128 }
1129
1130 pDev->Int.s.iIrq = DevTmp.Int.s.iIrq;
1131 }
1132 return VINF_SUCCESS;
1133}
1134
1135
1136/* -=-=-=-=-=- real code -=-=-=-=-=- */
1137
1138
1139/**
1140 * Registers the device with the default PCI bus.
1141 *
1142 * @returns VBox status code.
1143 * @param pBus The bus to register with.
1144 * @param iDev The PCI device ordinal.
1145 * @param pPciDev The PCI device structure.
1146 * @param pszName Pointer to device name (permanent, readonly). For debugging, not unique.
1147 */
1148static void pciRegisterInternal(PPCIBUS pBus, int iDev, PPCIDEVICE pPciDev, const char *pszName)
1149{
1150 Assert(!pBus->devices[iDev]);
1151 pPciDev->devfn = iDev;
1152 pPciDev->name = pszName;
1153 pPciDev->Int.s.pBus = pBus;
1154 pPciDev->Int.s.pfnConfigRead = pci_default_read_config;
1155 pPciDev->Int.s.pfnConfigWrite = pci_default_write_config;
1156 AssertMsg(pBus->uIrqIndex < PCI_DEVICES_MAX,
1157 ("Device %s: Too many devices %d (max=%d)\n",
1158 pszName, pBus->uIrqIndex, PCI_DEVICES_MAX));
1159 pPciDev->Int.s.iIrq = pBus->uIrqIndex++;
1160 pBus->devices[iDev] = pPciDev;
1161 Log(("PCI: Registered device %d function %d (%#x) '%s'.\n",
1162 iDev >> 3, iDev & 7, 0x80000000 | (iDev << 8), pszName));
1163}
1164
1165
1166/**
1167 * Registers the device with the default PCI bus.
1168 *
1169 * @returns VBox status code.
1170 * @param pDevIns Device instance of the PCI Bus.
1171 * @param pPciDev The PCI device structure.
1172 * Any PCI enabled device must keep this in it's instance data!
1173 * Fill in the PCI data config before registration, please.
1174 * @param pszName Pointer to device name (permanent, readonly). For debugging, not unique.
1175 * @param iDev The PCI device number. Use a negative value for auto assigning one.
1176 */
1177static DECLCALLBACK(int) pciRegister(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, const char *pszName, int iDev)
1178{
1179 PPCIBUS pBus = PDMINS2DATA(pDevIns, PPCIBUS);
1180
1181 /*
1182 * Check input.
1183 */
1184 if ( !pszName
1185 || !pPciDev
1186 || iDev >= (int)ELEMENTS(pBus->devices)
1187 || (iDev >= 0 && iDev <= 8))
1188 {
1189 AssertMsgFailed(("Invalid argument! pszName=%s pPciDev=%p iDev=%d\n", pszName, pPciDev, iDev));
1190 return VERR_INVALID_PARAMETER;
1191 }
1192
1193 /*
1194 * Find device slot.
1195 */
1196 if (iDev < 0)
1197 {
1198 /*
1199 * Special check for the IDE controller which is our function 1 device
1200 * before searching.
1201 */
1202 if ( !strcmp(pszName, "piix3ide")
1203 && !pBus->devices[9])
1204 iDev = 9;
1205 else
1206 {
1207 Assert(!(pBus->iDevSearch % 8));
1208 for (iDev = pBus->iDevSearch; iDev < (int)ELEMENTS(pBus->devices); iDev += 8)
1209 if ( !pBus->devices[iDev]
1210 && !pBus->devices[iDev + 1]
1211 && !pBus->devices[iDev + 2]
1212 && !pBus->devices[iDev + 3]
1213 && !pBus->devices[iDev + 4]
1214 && !pBus->devices[iDev + 5]
1215 && !pBus->devices[iDev + 6]
1216 && !pBus->devices[iDev + 7])
1217 break;
1218 if (iDev >= (int)ELEMENTS(pBus->devices))
1219 {
1220 AssertMsgFailed(("Couldn't find free spot!\n"));
1221 return VERR_PDM_TOO_PCI_MANY_DEVICES;
1222 }
1223 }
1224 pPciDev->Int.s.fRequestedDevFn = false;
1225 }
1226 else
1227 {
1228 /*
1229 * An explicit request.
1230 *
1231 * If the slot is occupied we'll have to relocate the device
1232 * currently occupying it first. This can only be done if the
1233 * existing device wasn't explicitly assigned. Also we limit
1234 * ourselves to function 0 devices.
1235 *
1236 * If you start setting devices + function in the
1237 * config, do it for all pci devices!
1238 */
1239 AssertReleaseMsg(iDev > 8, ("iDev=%d pszName=%s\n", iDev, pszName));
1240 if (pBus->devices[iDev])
1241 {
1242 int iDevRel;
1243 AssertReleaseMsg(!(iDev % 8), ("PCI Configuration Conflict! iDev=%d pszName=%s clashes with %s\n",
1244 iDev, pszName, pBus->devices[iDev]->name));
1245 if ( pBus->devices[iDev]->Int.s.fRequestedDevFn
1246 || (pBus->devices[iDev + 1] && pBus->devices[iDev + 1]->Int.s.fRequestedDevFn)
1247 || (pBus->devices[iDev + 2] && pBus->devices[iDev + 2]->Int.s.fRequestedDevFn)
1248 || (pBus->devices[iDev + 3] && pBus->devices[iDev + 3]->Int.s.fRequestedDevFn)
1249 || (pBus->devices[iDev + 4] && pBus->devices[iDev + 4]->Int.s.fRequestedDevFn)
1250 || (pBus->devices[iDev + 5] && pBus->devices[iDev + 5]->Int.s.fRequestedDevFn)
1251 || (pBus->devices[iDev + 6] && pBus->devices[iDev + 6]->Int.s.fRequestedDevFn)
1252 || (pBus->devices[iDev + 7] && pBus->devices[iDev + 7]->Int.s.fRequestedDevFn))
1253 {
1254 AssertReleaseMsgFailed(("Configuration error:'%s' and '%s' are both configured as device %d\n",
1255 pszName, pBus->devices[iDev]->name, iDev));
1256 return VERR_INTERNAL_ERROR;
1257 }
1258
1259 /* Find free slot for the device(s) we're moving and move them. */
1260 for (iDevRel = pBus->iDevSearch; iDevRel < (int)ELEMENTS(pBus->devices); iDevRel += 8)
1261 {
1262 if ( !pBus->devices[iDevRel]
1263 && !pBus->devices[iDevRel + 1]
1264 && !pBus->devices[iDevRel + 2]
1265 && !pBus->devices[iDevRel + 3]
1266 && !pBus->devices[iDevRel + 4]
1267 && !pBus->devices[iDevRel + 5]
1268 && !pBus->devices[iDevRel + 6]
1269 && !pBus->devices[iDevRel + 7])
1270 {
1271 int i = 0;
1272 for (i = 0; i < 8; i++)
1273 {
1274 if (!pBus->devices[iDev + i])
1275 continue;
1276 Log(("PCI: relocating '%s' from slot %#x to %#x\n", pBus->devices[iDev + i]->name, iDev + i, iDevRel + i));
1277 pBus->devices[iDevRel + i] = pBus->devices[iDev + i];
1278 pBus->devices[iDevRel + i]->devfn = i;
1279 pBus->devices[iDev + i] = NULL;
1280 }
1281 }
1282 }
1283 if (pBus->devices[iDev])
1284 {
1285 AssertMsgFailed(("Couldn't find free spot!\n"));
1286 return VERR_PDM_TOO_PCI_MANY_DEVICES;
1287 }
1288 } /* if conflict */
1289 pPciDev->Int.s.fRequestedDevFn = true;
1290 }
1291
1292 /*
1293 * Register the device.
1294 */
1295 pciRegisterInternal(pBus, iDev, pPciDev, pszName);
1296 return VINF_SUCCESS;
1297}
1298
1299
1300static DECLCALLBACK(int) pciIORegionRegister(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iRegion, uint32_t cbRegion, PCIADDRESSSPACE enmType, PFNPCIIOREGIONMAP pfnCallback)
1301{
1302 PPCIIOREGION pRegion;
1303
1304 /*
1305 * Validate.
1306 */
1307 if ( enmType != PCI_ADDRESS_SPACE_MEM
1308 && enmType != PCI_ADDRESS_SPACE_IO
1309 && enmType != PCI_ADDRESS_SPACE_MEM_PREFETCH)
1310 {
1311 AssertMsgFailed(("Invalid enmType=%#x? Or was this a bitmask after all...\n", enmType));
1312 return VERR_INVALID_PARAMETER;
1313 }
1314 if ((unsigned)iRegion >= PCI_NUM_REGIONS)
1315 {
1316 AssertMsgFailed(("Invalid iRegion=%d PCI_NUM_REGIONS=%d\n", iRegion, PCI_NUM_REGIONS));
1317 return VERR_INVALID_PARAMETER;
1318 }
1319
1320 /*
1321 * Register the I/O region.
1322 */
1323 pRegion = &pPciDev->Int.s.aIORegions[iRegion];
1324 pRegion->addr = ~0U;
1325 pRegion->size = cbRegion;
1326 pRegion->type = enmType;
1327 pRegion->map_func = pfnCallback;
1328 return VINF_SUCCESS;
1329}
1330
1331
1332/**
1333 * @copydoc PDMPCIBUSREG::pfnSetConfigCallbacksHC
1334 */
1335static DECLCALLBACK(void) pciSetConfigCallbacks(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PFNPCICONFIGREAD pfnRead, PPFNPCICONFIGREAD ppfnReadOld,
1336 PFNPCICONFIGWRITE pfnWrite, PPFNPCICONFIGWRITE ppfnWriteOld)
1337{
1338 if (ppfnReadOld)
1339 *ppfnReadOld = pPciDev->Int.s.pfnConfigRead;
1340 pPciDev->Int.s.pfnConfigRead = pfnRead;
1341
1342 if (ppfnWriteOld)
1343 *ppfnWriteOld = pPciDev->Int.s.pfnConfigWrite;
1344 pPciDev->Int.s.pfnConfigWrite = pfnWrite;
1345}
1346
1347
1348/**
1349 * Called to perform the job of the bios.
1350 *
1351 * @returns VBox status.
1352 * @param pDevIns Device instance of the first bus.
1353 */
1354static DECLCALLBACK(int) pciFakePCIBIOS(PPDMDEVINS pDevIns)
1355{
1356 int rc;
1357 unsigned i;
1358 uint8_t elcr[2] = {0, 0};
1359 PPCIGLOBALS pGlobals = DEVINS2PCIGLOBALS(pDevIns);
1360 PPCIBUS pBus = PDMINS2DATA(pDevIns, PPCIBUS);
1361 PVM pVM = PDMDevHlpGetVM(pDevIns);
1362 Assert(pVM);
1363
1364 /*
1365 * Set the start addresses.
1366 */
1367 pGlobals->pci_bios_io_addr = 0xc000;
1368 pGlobals->pci_bios_mem_addr = 0xf0000000;
1369
1370 /*
1371 * Activate IRQ mappings.
1372 */
1373 for (i = 0; i < 4; i++)
1374 {
1375 uint8_t irq = pci_irqs[i];
1376 /* Set to trigger level. */
1377 elcr[irq >> 3] |= (1 << (irq & 7));
1378 /* Activate irq remapping in PIIX3. */
1379 pci_config_writeb(&pBus->PIIX3State.dev, 0x60 + i, irq);
1380 }
1381
1382 /* Tell to the PIC. */
1383 rc = IOMIOPortWrite(pVM, 0x4d0, elcr[0], sizeof(uint8_t));
1384 if (rc == VINF_SUCCESS)
1385 rc = IOMIOPortWrite(pVM, 0x4d1, elcr[1], sizeof(uint8_t));
1386 if (rc != VINF_SUCCESS)
1387 {
1388 AssertMsgFailed(("Writing to PIC failed!\n"));
1389 return VBOX_SUCCESS(rc) ? VERR_INTERNAL_ERROR : rc;
1390 }
1391
1392 /*
1393 * Init the devices.
1394 */
1395 for (i = 0; i < ELEMENTS(pBus->devices); i++)
1396 {
1397 if (pBus->devices[i])
1398 {
1399 Log2(("PCI: Initializing device %d (%#x) '%s'\n",
1400 i, 0x80000000 | (i << 8), pBus->devices[i]->name));
1401 pci_bios_init_device(pBus->devices[i]);
1402 }
1403 }
1404 return VINF_SUCCESS;
1405}
1406
1407/**
1408 * @copydoc FNPDMDEVRELOCATE
1409 */
1410static DECLCALLBACK(void) pciRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
1411{
1412 PPCIBUS pBus = PDMINS2DATA(pDevIns, PPCIBUS);
1413 pBus->pDevInsGC = PDMDEVINS_2_GCPTR(pDevIns);
1414 pBus->pPciHlpGC = pBus->pPciHlpR3->pfnGetGCHelpers(pDevIns);
1415}
1416
1417
1418/**
1419 * Construct a PCI Bus device instance for a VM.
1420 *
1421 * @returns VBox status.
1422 * @param pDevIns The device instance data.
1423 * If the registration structure is needed, pDevIns->pDevReg points to it.
1424 * @param iInstance Instance number. Use this to figure out which registers and such to use.
1425 * The device number is also found in pDevIns->iInstance, but since it's
1426 * likely to be freqently used PDM passes it as parameter.
1427 * @param pCfgHandle Configuration node handle for the device. Use this to obtain the configuration
1428 * of the device instance. It's also found in pDevIns->pCfgHandle, but like
1429 * iInstance it's expected to be used a bit in this function.
1430 */
1431static DECLCALLBACK(int) pciConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfgHandle)
1432{
1433 PPCIGLOBALS pGlobals = DEVINS2PCIGLOBALS(pDevIns);
1434 PPCIBUS pBus = PDMINS2DATA(pDevIns, PPCIBUS);
1435 PDMPCIBUSREG PciBusReg;
1436 int rc;
1437 bool fGCEnabled;
1438 bool fR0Enabled;
1439 bool fUseIoApic;
1440 Assert(iInstance == 0);
1441
1442 /*
1443 * Validate and read configuration.
1444 */
1445 if (!CFGMR3AreValuesValid(pCfgHandle, "IOAPIC\0" "GCEnabled\0R0Enabled\0"))
1446 return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
1447
1448 /* query whether we got an IOAPIC */
1449 rc = CFGMR3QueryBool(pCfgHandle, "IOAPIC", &fUseIoApic);
1450 if (rc == VERR_CFGM_VALUE_NOT_FOUND)
1451 fUseIoApic = false;
1452 else if (VBOX_FAILURE(rc))
1453 return PDMDEV_SET_ERROR(pDevIns, rc,
1454 N_("Configuration error: Failed to query boolean value \"IOAPIC\""));
1455
1456 /* check if GC code is enabled. */
1457 rc = CFGMR3QueryBool(pCfgHandle, "GCEnabled", &fGCEnabled);
1458 if (rc == VERR_CFGM_VALUE_NOT_FOUND)
1459 fGCEnabled = true;
1460 else if (VBOX_FAILURE(rc))
1461 return PDMDEV_SET_ERROR(pDevIns, rc,
1462 N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
1463 Log(("PCI: fGCEnabled=%d\n", fGCEnabled));
1464
1465 /* check if R0 code is enabled. */
1466 rc = CFGMR3QueryBool(pCfgHandle, "R0Enabled", &fR0Enabled);
1467 if (rc == VERR_CFGM_VALUE_NOT_FOUND)
1468 fR0Enabled = true;
1469 else if (VBOX_FAILURE(rc))
1470 return PDMDEV_SET_ERROR(pDevIns, rc,
1471 N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
1472 Log(("PCI: fR0Enabled=%d\n", fR0Enabled));
1473
1474 /*
1475 * Init data and register the PCI bus.
1476 */
1477 pGlobals->pci_mem_base = 0;
1478 pGlobals->pci_bios_io_addr = 0xc000;
1479 pGlobals->pci_bios_mem_addr = 0xf0000000;
1480 memset(&pGlobals->pci_irq_levels, 0, sizeof(pGlobals->pci_irq_levels));
1481 pGlobals->fUseIoApic = fUseIoApic;
1482 memset(&pGlobals->pci_apic_irq_levels, 0, sizeof(pGlobals->pci_apic_irq_levels));
1483
1484 pBus->pDevInsHC = pDevIns;
1485 pBus->pDevInsGC = PDMDEVINS_2_GCPTR(pDevIns);
1486
1487 PciBusReg.u32Version = PDM_PCIBUSREG_VERSION;
1488 PciBusReg.pfnRegisterHC = pciRegister;
1489 PciBusReg.pfnIORegionRegisterHC = pciIORegionRegister;
1490 PciBusReg.pfnSetConfigCallbacksHC = pciSetConfigCallbacks;
1491 PciBusReg.pfnSetIrqHC = pciSetIrq;
1492 PciBusReg.pfnSaveExecHC = pciGenericSaveExec;
1493 PciBusReg.pfnLoadExecHC = pciGenericLoadExec;
1494 PciBusReg.pfnFakePCIBIOSHC = pciFakePCIBIOS;
1495 PciBusReg.pszSetIrqGC = fGCEnabled ? "pciSetIrq" : NULL;
1496 PciBusReg.pszSetIrqR0 = fR0Enabled ? "pciSetIrq" : NULL;
1497 rc = pDevIns->pDevHlp->pfnPCIBusRegister(pDevIns, &PciBusReg, &pBus->pPciHlpR3);
1498 if (VBOX_FAILURE(rc))
1499 return PDMDEV_SET_ERROR(pDevIns, rc,
1500 N_("Failed to register ourselves as a PCI Bus"));
1501 if (pBus->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
1502 return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
1503 N_("PCI helper version mismatch; got %#x expected %#x"),
1504 pBus->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION);
1505
1506 pBus->pPciHlpGC = pBus->pPciHlpR3->pfnGetGCHelpers(pDevIns);
1507 pBus->pPciHlpR0 = pBus->pPciHlpR3->pfnGetR0Helpers(pDevIns);
1508
1509 /*
1510 * Fill in PCI configs and add them to the bus.
1511 */
1512 /* i440FX */
1513 pBus->PciDev.config[0x00] = 0x86; /* vendor_id: Intel */
1514 pBus->PciDev.config[0x01] = 0x80;
1515 pBus->PciDev.config[0x02] = 0x37; /* device_id: */
1516 pBus->PciDev.config[0x03] = 0x12;
1517 pBus->PciDev.config[0x08] = 0x02; /* revision */
1518 pBus->PciDev.config[0x0a] = 0x00; /* class_sub = host2pci */
1519 pBus->PciDev.config[0x0b] = 0x06; /* class_base = PCI_bridge */
1520 pBus->PciDev.config[0x0e] = 0x00; /* header_type */
1521 pBus->PciDev.pDevIns = pDevIns;
1522 pBus->PciDev.Int.s.fRequestedDevFn= true;
1523 pciRegisterInternal(pBus, 0, &pBus->PciDev, "i440FX");
1524
1525 /* PIIX3 */
1526 pBus->PIIX3State.dev.config[0x00] = 0x86; /* vendor: Intel */
1527 pBus->PIIX3State.dev.config[0x01] = 0x80;
1528 pBus->PIIX3State.dev.config[0x02] = 0x00; /* device_id: 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */
1529 pBus->PIIX3State.dev.config[0x03] = 0x70;
1530 pBus->PIIX3State.dev.config[0x0a] = 0x01; /* class_sub = PCI_ISA */
1531 pBus->PIIX3State.dev.config[0x0b] = 0x06; /* class_base = PCI_bridge */
1532 pBus->PIIX3State.dev.config[0x0e] = 0x80; /* header_type = PCI_multifunction, generic */
1533 pBus->PIIX3State.dev.pDevIns = pDevIns;
1534 pBus->PciDev.Int.s.fRequestedDevFn= true;
1535 pciRegisterInternal(pBus, 8, &pBus->PIIX3State.dev, "PIIX3");
1536 piix3_reset(&pBus->PIIX3State);
1537
1538 pBus->iDevSearch = 16;
1539
1540 /*
1541 * Register I/O ports and save state.
1542 */
1543 rc = PDMDevHlpIOPortRegister(pDevIns, 0xcf8, 1, NULL, pciIOPortAddressWrite, pciIOPortAddressRead, NULL, NULL, "i440FX (PCI)");
1544 if (VBOX_FAILURE(rc))
1545 return rc;
1546 rc = PDMDevHlpIOPortRegister(pDevIns, 0xcfc, 4, NULL, pciIOPortDataWrite, pciIOPortDataRead, NULL, NULL, "i440FX (PCI)");
1547 if (VBOX_FAILURE(rc))
1548 return rc;
1549 rc = PDMDevHlpSSMRegister(pDevIns, "pci", iInstance, 2, sizeof(*pBus),
1550 NULL, pciSaveExec, NULL, NULL, pciLoadExec, NULL);
1551 if (VBOX_FAILURE(rc))
1552 return rc;
1553
1554 return VINF_SUCCESS;
1555}
1556
1557
1558/**
1559 * The device registration structure.
1560 */
1561const PDMDEVREG g_DevicePCI =
1562{
1563 /* u32Version */
1564 PDM_DEVREG_VERSION,
1565 /* szDeviceName */
1566 "pci",
1567 /* szGCMod */
1568 "VBoxDDGC.gc",
1569 /* szR0Mod */
1570 "VBoxDDR0.r0",
1571 /* pszDescription */
1572 "i440FX PCI bridge and PIIX3 ISA bridge.",
1573 /* fFlags */
1574 PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT | PDM_DEVREG_FLAGS_GUEST_BITS_32 | PDM_DEVREG_FLAGS_GC | PDM_DEVREG_FLAGS_R0,
1575 /* fClass */
1576 PDM_DEVREG_CLASS_BUS_PCI | PDM_DEVREG_CLASS_BUS_ISA,
1577 /* cMaxInstances */
1578 1,
1579 /* cbInstance */
1580 sizeof(PCIBUS),
1581 /* pfnConstruct */
1582 pciConstruct,
1583 /* pfnDestruct */
1584 NULL,
1585 /* pfnRelocate */
1586 pciRelocate,
1587 /* pfnIOCtl */
1588 NULL,
1589 /* pfnPowerOn */
1590 NULL,
1591 /* pfnReset */
1592 NULL,
1593 /* pfnSuspend */
1594 NULL,
1595 /* pfnResume */
1596 NULL,
1597 /* pfnAttach */
1598 NULL,
1599 /* pfnDetach */
1600 NULL,
1601 /* pfnQueryInterface */
1602 NULL,
1603 /* pfnInitComplete */
1604 NULL
1605};
1606#endif /* IN_RING3 */
1607#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
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