VirtualBox

source: vbox/trunk/src/VBox/Devices/Bus/DevPCI.cpp@ 11730

Last change on this file since 11730 was 11309, checked in by vboxsync, 16 years ago

iprt: Retired HCSTRING, replaced by R3STRING.
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  • Property svn:keywords set to Author Date Id Revision
File size: 54.3 KB
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1/* $Id: DevPCI.cpp 11309 2008-08-08 23:25:08Z vboxsync $ */
2/** @file
3 * DevPCI - PCI BUS Device.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 * --------------------------------------------------------------------
21 *
22 * This code is based on:
23 *
24 * QEMU PCI bus manager
25 *
26 * Copyright (c) 2004 Fabrice Bellard
27 *
28 * Permission is hereby granted, free of charge, to any person obtaining a copy
29 * of this software and associated documentation files (the "Software"), to deal
30 * in the Software without restriction, including without limitation the rights
31 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
32 * copies of the Software, and to permit persons to whom the Software is
33 * furnished to do so, subject to the following conditions:
34 *
35 * The above copyright notice and this permission notice shall be included in
36 * all copies or substantial portions of the Software.
37 *
38 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
39 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
40 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
41 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
42 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
43 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
44 * THE SOFTWARE.
45 */
46
47/*******************************************************************************
48* Header Files *
49*******************************************************************************/
50#define LOG_GROUP LOG_GROUP_DEV_PCI
51/* Hack to get PCIDEVICEINT declare at the right point - include "PCIInternal.h". */
52#define PCI_INCLUDE_PRIVATE
53#include <VBox/pci.h>
54#include <VBox/pdmdev.h>
55#include <iprt/assert.h>
56#include <iprt/string.h>
57
58#include "../Builtins.h"
59
60
61/*******************************************************************************
62* Defined Constants And Macros *
63*******************************************************************************/
64/** @def PCI_LOCK
65 * Acquires the PDM lock. This is a NOP if locking is disabled. */
66/** @def PCI_UNLOCK
67 * Releases the PDM lock. This is a NOP if locking is disabled. */
68#define PCI_LOCK(pDevIns, rc) \
69 do { \
70 int rc2 = PDMINS_2_DATA(pDevIns, PCIBus *)->CTX_SUFF(pPciHlp)->pfnLock((pDevIns), rc); \
71 if (rc2 != VINF_SUCCESS) \
72 return rc2; \
73 } while (0)
74#define PCI_UNLOCK(pDevIns) \
75 PDMINS_2_DATA(pDevIns, PCIBus *)->CTX_SUFF(pPciHlp)->pfnUnlock(pDevIns)
76
77
78/*******************************************************************************
79* Structures and Typedefs *
80*******************************************************************************/
81/**
82 * PIIX3 ISA Bridge state.
83 */
84typedef struct PIIX3State
85{
86 /** The PCI device of the bridge. */
87 PCIDEVICE dev;
88} PIIX3State, PIIX3, *PPIIX3;
89
90
91/** Maximum number of PCI devices.
92 * Defined like this to make interrupt handling simple. */
93#define PCI_DEVICES_MAX 64
94/** Number of uint32_t entries needed make a bitmask of the interrupts. */
95#define PCI_IRQ_WORDS ((PCI_DEVICES_MAX + 31) / 32)
96
97/**
98 * PCI Globals.
99 *
100 * @remark
101 * These are currently put in the PCIBus structure since we've
102 * only got one PCI bus in the current VM configurations. This
103 * makes life somewhat simpler in RC.
104 */
105typedef struct PCIGLOBALS
106{
107 /** Irq levels for the four PCI Irqs. */
108 uint32_t pci_irq_levels[4][PCI_IRQ_WORDS];
109 /** The base address for PCI assigned MMIO addresses. */
110 RTGCPHYS32 pci_mem_base;
111 /** The next I/O port address which the PCI BIOS will use. */
112 uint32_t pci_bios_io_addr;
113 /** The next MMIO address which the PCI BIOS will use. */
114 uint32_t pci_bios_mem_addr;
115 /** I/O APIC usage flag */
116 bool fUseIoApic;
117 /** I/O APIC irq levels */
118 uint32_t pci_apic_irq_levels[8][PCI_IRQ_WORDS];
119 /** ACPI IRQ level */
120 uint32_t acpi_irq_level;
121 /** ACPI PIC IRQ */
122 int acpi_irq;
123} PCIGLOBALS;
124/** Pointer to per VM data. */
125typedef PCIGLOBALS *PPCIGLOBALS;
126
127
128/**
129 * PCI Bus instance.
130 */
131typedef struct PCIBus
132{
133 /** IRQ index */
134 uint32_t uIrqIndex;
135 /** Bus number. */
136 int32_t iBus;
137 /** Start device number. */
138 int32_t iDevSearch;
139 /** Config register. */
140 uint32_t uConfigReg;
141 /** Array of PCI devices. */
142 R3PTRTYPE(PPCIDEVICE) devices[256];
143
144 /** R3 pointer to the device instance. */
145 PPDMDEVINSR3 pDevInsR3;
146 /** Pointer to the PCI R3 helpers. */
147 PCPDMPCIHLPR3 pPciHlpR3;
148
149 /** R0 pointer to the device instance. */
150 PPDMDEVINSR0 pDevInsR0;
151 /** Pointer to the PCI R0 helpers. */
152 PCPDMPCIHLPR0 pPciHlpR0;
153
154 /** RC pointer to the device instance. */
155 PPDMDEVINSRC pDevInsRC;
156 /** Pointer to the PCI RC helpers. */
157 PCPDMPCIHLPRC pPciHlpRC;
158
159 /** The PCI device for the PCI bridge. */
160 PCIDEVICE PciDev;
161 /** ISA bridge state. */
162 PIIX3 PIIX3State;
163 /** The global data.
164 * Since we've only got one bus at present, we put it here to keep things simple. */
165 PCIGLOBALS Globals;
166} PCIBUS;
167/** Pointer to a PCIBUS instance. */
168typedef PCIBUS *PPCIBUS;
169typedef PCIBUS PCIBus;
170
171
172/** Converts a bus instance pointer to a device instance pointer. */
173#define PCIBUS_2_DEVINS(pPciBus) ((pPciBus)->CTX_SUFF(pDevIns))
174/** Converts a device instance pointer to a PCIGLOBALS pointer. */
175#define DEVINS_2_PCIGLOBALS(pDevIns) ((PPCIGLOBALS)(&PDMINS_2_DATA(pDevIns, PPCIBUS)->Globals))
176/** Converts a bus instance pointer to a PCIGLOBALS pointer. */
177#define PCIBUS_2_PCIGLOBALS(pPciBus) ((PPCIGLOBALS)(&pPciBus->Globals))
178
179
180#ifndef VBOX_DEVICE_STRUCT_TESTCASE
181/*******************************************************************************
182* Internal Functions *
183*******************************************************************************/
184__BEGIN_DECLS
185
186PDMBOTHCBDECL(void) pciSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel);
187
188__END_DECLS
189
190
191#define DEBUG_PCI
192
193#define PCI_VENDOR_ID 0x00 /* 16 bits */
194#define PCI_DEVICE_ID 0x02 /* 16 bits */
195#define PCI_COMMAND 0x04 /* 16 bits */
196#define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
197#define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
198#define PCI_CLASS_DEVICE 0x0a /* Device class */
199#define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
200#define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
201#define PCI_MIN_GNT 0x3e /* 8 bits */
202#define PCI_MAX_LAT 0x3f /* 8 bits */
203
204#ifdef IN_RING3
205
206static void pci_addr_writel(PCIBus *s, uint32_t addr, uint32_t val)
207{
208 s->uConfigReg = val;
209}
210
211static uint32_t pci_addr_readl(PCIBus *s, uint32_t addr)
212{
213 return s->uConfigReg;
214}
215
216static void pci_update_mappings(PCIDevice *d)
217{
218 PPCIBUS pBus = d->Int.s.pBus;
219 PCIIORegion *r;
220 int cmd, i;
221 uint32_t last_addr, new_addr, config_ofs;
222
223 cmd = RT_LE2H_U16(*(uint16_t *)(d->config + PCI_COMMAND));
224 for(i = 0; i < PCI_NUM_REGIONS; i++) {
225 r = &d->Int.s.aIORegions[i];
226 if (i == PCI_ROM_SLOT) {
227 config_ofs = 0x30;
228 } else {
229 config_ofs = 0x10 + i * 4;
230 }
231 if (r->size != 0) {
232 if (r->type & PCI_ADDRESS_SPACE_IO) {
233 if (cmd & PCI_COMMAND_IO) {
234 new_addr = RT_LE2H_U32(*(uint32_t *)(d->config +
235 config_ofs));
236 new_addr = new_addr & ~(r->size - 1);
237 last_addr = new_addr + r->size - 1;
238 /* NOTE: we have only 64K ioports on PC */
239 if (last_addr <= new_addr || new_addr == 0 ||
240 last_addr >= 0x10000) {
241 new_addr = ~0U;
242 }
243 } else {
244 new_addr = ~0U;
245 }
246 } else {
247 if (cmd & PCI_COMMAND_MEMORY) {
248 new_addr = RT_LE2H_U32(*(uint32_t *)(d->config +
249 config_ofs));
250 /* the ROM slot has a specific enable bit */
251 if (i == PCI_ROM_SLOT && !(new_addr & 1))
252 goto no_mem_map;
253 new_addr = new_addr & ~(r->size - 1);
254 last_addr = new_addr + r->size - 1;
255 /* NOTE: we do not support wrapping */
256 /* XXX: as we cannot support really dynamic
257 mappings, we handle specific values as invalid
258 mappings. */
259 if (last_addr <= new_addr || new_addr == 0 ||
260 last_addr == ~0U) {
261 new_addr = ~0U;
262 }
263 } else {
264 no_mem_map:
265 new_addr = ~0U;
266 }
267 }
268 /* now do the real mapping */
269 if (new_addr != r->addr) {
270 if (r->addr != ~0U) {
271 if (r->type & PCI_ADDRESS_SPACE_IO) {
272 int devclass;
273 /* NOTE: specific hack for IDE in PC case:
274 only one byte must be mapped. */
275 devclass = d->config[0x0a] | (d->config[0x0b] << 8);
276 if (devclass == 0x0101 && r->size == 4) {
277 int rc = d->pDevIns->pDevHlp->pfnIOPortDeregister(d->pDevIns, r->addr + 2, 1);
278 AssertRC(rc);
279 } else {
280 int rc = d->pDevIns->pDevHlp->pfnIOPortDeregister(d->pDevIns, r->addr, r->size);
281 AssertRC(rc);
282 }
283 } else {
284 RTGCPHYS GCPhysBase = r->addr + PCIBUS_2_PCIGLOBALS(pBus)->pci_mem_base;
285 int rc;
286 if (pBus->pPciHlpR3->pfnIsMMIO2Base(pBus->pDevInsR3, d->pDevIns, GCPhysBase))
287 {
288 /* unmap it. */
289 rc = r->map_func(d, i, NIL_RTGCPHYS, r->size, (PCIADDRESSSPACE)(r->type));
290 AssertRC(rc);
291 rc = PDMDevHlpMMIO2Unmap(d->pDevIns, i, GCPhysBase);
292 }
293 else
294 rc = d->pDevIns->pDevHlp->pfnMMIODeregister(d->pDevIns, GCPhysBase, r->size);
295 AssertMsgRC(rc, ("rc=%Rrc d=%s i=%d GCPhysBase=%RGp size=%#x\n", rc, d->name, i, GCPhysBase, r->size));
296 }
297 }
298 r->addr = new_addr;
299 if (r->addr != ~0U) {
300 int rc = r->map_func(d, i,
301 r->addr + (r->type & PCI_ADDRESS_SPACE_IO ? 0 : PCIBUS_2_PCIGLOBALS(pBus)->pci_mem_base),
302 r->size, (PCIADDRESSSPACE)(r->type));
303 AssertRC(rc);
304 }
305 }
306 }
307 }
308}
309
310
311static DECLCALLBACK(uint32_t) pci_default_read_config(PCIDevice *d, uint32_t address, unsigned len)
312{
313 uint32_t val;
314 switch(len) {
315 case 1:
316 val = d->config[address];
317 break;
318 case 2:
319 val = RT_LE2H_U16(*(uint16_t *)(d->config + address));
320 break;
321 default:
322 case 4:
323 val = RT_LE2H_U32(*(uint32_t *)(d->config + address));
324 break;
325 }
326 return val;
327}
328
329static DECLCALLBACK(void) pci_default_write_config(PCIDevice *d, uint32_t address, uint32_t val, unsigned len)
330{
331 int can_write;
332 unsigned i;
333 uint32_t end, addr;
334
335 if (len == 4 && ((address >= 0x10 && address < 0x10 + 4 * 6) ||
336 (address >= 0x30 && address < 0x34))) {
337 PCIIORegion *r;
338 int reg;
339
340 if ( address >= 0x30 ) {
341 reg = PCI_ROM_SLOT;
342 }else{
343 reg = (address - 0x10) >> 2;
344 }
345 r = &d->Int.s.aIORegions[reg];
346 if (r->size == 0)
347 goto default_config;
348 /* compute the stored value */
349 if (reg == PCI_ROM_SLOT) {
350 /* keep ROM enable bit */
351 val &= (~(r->size - 1)) | 1;
352 } else {
353 val &= ~(r->size - 1);
354 val |= r->type;
355 }
356 *(uint32_t *)(d->config + address) = RT_H2LE_U32(val);
357 pci_update_mappings(d);
358 return;
359 }
360 default_config:
361 /* not efficient, but simple */
362 addr = address;
363 for(i = 0; i < len; i++) {
364 /* default read/write accesses */
365 switch(d->config[0x0e]) {
366 case 0x00:
367 case 0x80:
368 switch(addr) {
369 case 0x00:
370 case 0x01:
371 case 0x02:
372 case 0x03:
373 case 0x08:
374 case 0x09:
375 case 0x0a:
376 case 0x0b:
377 case 0x0e:
378 case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17: /* base */
379 case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f:
380 case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27:
381 case 0x30: case 0x31: case 0x32: case 0x33: /* rom */
382 case 0x3d:
383 can_write = 0;
384 break;
385 default:
386 can_write = 1;
387 break;
388 }
389 break;
390 default:
391 case 0x01:
392 switch(addr) {
393 case 0x00:
394 case 0x01:
395 case 0x02:
396 case 0x03:
397 case 0x08:
398 case 0x09:
399 case 0x0a:
400 case 0x0b:
401 case 0x0e:
402 case 0x38: case 0x39: case 0x3a: case 0x3b: /* rom */
403 case 0x3d:
404 can_write = 0;
405 break;
406 default:
407 can_write = 1;
408 break;
409 }
410 break;
411 }
412#ifdef VBOX
413 /* status register: only clear bits by writing a '1' at the corresponding bit */
414 if (addr == 0x06)
415 {
416 d->config[addr] &= ~val;
417 d->config[addr] |= 0x08; /* interrupt status */
418 }
419 else if (addr == 0x07)
420 {
421 d->config[addr] &= ~val;
422 }
423 else
424#endif
425 if (can_write) {
426 d->config[addr] = val;
427 }
428 addr++;
429 val >>= 8;
430 }
431
432 end = address + len;
433 if (end > PCI_COMMAND && address < (PCI_COMMAND + 2)) {
434 /* if the command register is modified, we must modify the mappings */
435 pci_update_mappings(d);
436 }
437}
438
439static void pci_data_write(PCIBus *s, uint32_t addr, uint32_t val, int len)
440{
441 PCIDevice *pci_dev;
442 int config_addr, iBus;
443
444 Log(("pci_data_write: addr=%08x val=%08x len=%d\n", s->uConfigReg, val, len));
445
446 if (!(s->uConfigReg & (1 << 31))) {
447 return;
448 }
449 if ((s->uConfigReg & 0x3) != 0) {
450 return;
451 }
452 iBus = (s->uConfigReg >> 16) & 0xff;
453 if (iBus != 0)
454 return;
455 pci_dev = s->devices[(s->uConfigReg >> 8) & 0xff];
456 if (!pci_dev)
457 return;
458 config_addr = (s->uConfigReg & 0xfc) | (addr & 3);
459 Log(("pci_config_write: %s: addr=%02x val=%08x len=%d\n", pci_dev->name, config_addr, val, len));
460 pci_dev->Int.s.pfnConfigWrite(pci_dev, config_addr, val, len);
461}
462
463static uint32_t pci_data_read(PCIBus *s, uint32_t addr, int len)
464{
465 PCIDevice *pci_dev;
466 int config_addr, iBus;
467 uint32_t val;
468
469 if (!(s->uConfigReg & (1 << 31)))
470 goto fail;
471 if ((s->uConfigReg & 0x3) != 0)
472 goto fail;
473 iBus = (s->uConfigReg >> 16) & 0xff;
474 if (iBus != 0)
475 goto fail;
476 pci_dev = s->devices[(s->uConfigReg >> 8) & 0xff];
477 if (!pci_dev) {
478 fail:
479 switch(len) {
480 case 1:
481 val = 0xff;
482 break;
483 case 2:
484 val = 0xffff;
485 break;
486 default:
487 case 4:
488 val = 0xffffffff;
489 break;
490 }
491 goto the_end;
492 }
493 config_addr = (s->uConfigReg & 0xfc) | (addr & 3);
494 val = pci_dev->Int.s.pfnConfigRead(pci_dev, config_addr, len);
495 Log(("pci_config_read: %s: addr=%02x val=%08x len=%d\n", pci_dev->name, config_addr, val, len));
496 the_end:
497 return val;
498}
499
500#endif /* IN_RING3 */
501
502
503/* return the global irq number corresponding to a given device irq
504 pin. We could also use the bus number to have a more precise
505 mapping. */
506static inline int pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num)
507{
508 int slot_addend;
509 slot_addend = (pci_dev->devfn >> 3) - 1;
510 return (irq_num + slot_addend) & 3;
511}
512
513static inline int pci_slot_get_apic_pirq(PCIDevice *pci_dev, int irq_num)
514{
515 return (irq_num + (pci_dev->devfn >> 3)) & 7;
516}
517
518static inline int get_pci_irq_apic_level(PPCIGLOBALS pGlobals, int irq_num)
519{
520 int apic_level;
521 apic_level = ((pGlobals->pci_apic_irq_levels[irq_num][0] |
522 pGlobals->pci_apic_irq_levels[irq_num][1]) != 0);
523 return apic_level;
524}
525
526static void apic_set_irq(PPCIBUS pBus, PCIDevice *pci_dev, int irq_num1, int level, int acpi_irq)
527{
528 if (acpi_irq == -1) {
529 int shift, apic_irq, apic_level;
530 uint32_t *p;
531 PPCIGLOBALS pGlobals = PCIBUS_2_PCIGLOBALS(pBus);
532 int uIrqIndex = pci_dev->Int.s.iIrq;
533 int irq_num = pci_slot_get_apic_pirq(pci_dev, irq_num1);
534
535 p = &pGlobals->pci_apic_irq_levels[irq_num][uIrqIndex >> 5];
536 shift = (uIrqIndex & 0x1f);
537 *p = (*p & ~(1 << shift)) | ((level & PDM_IRQ_LEVEL_HIGH) << shift);
538 apic_irq = irq_num + 0x10;
539 apic_level = get_pci_irq_apic_level(pGlobals, irq_num);
540 Log3(("apic_set_irq: %s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d\n",
541 R3STRING(pci_dev->name), irq_num1, level, apic_irq, apic_level, irq_num));
542 pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), apic_irq, apic_level);
543
544 if ((level & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP) {
545 *p = (*p & ~(1 << shift));
546 apic_level = get_pci_irq_apic_level(pGlobals, irq_num);
547 Log3(("apic_set_irq: %s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d (flop)\n",
548 R3STRING(pci_dev->name), irq_num1, level, apic_irq, apic_level, irq_num));
549 pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), apic_irq, apic_level);
550 }
551 } else {
552 Log3(("apic_set_irq: %s: irq_num1=%d level=%d acpi_irq=%d\n",
553 R3STRING(pci_dev->name), irq_num1, level, acpi_irq));
554 pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), acpi_irq, level);
555 }
556}
557
558static inline int get_pci_irq_level(PPCIGLOBALS pGlobals, int irq_num)
559{
560 int pic_level;
561#if (PCI_IRQ_WORDS == 2)
562 pic_level = ((pGlobals->pci_irq_levels[irq_num][0] |
563 pGlobals->pci_irq_levels[irq_num][1]) != 0);
564#else
565 {
566 int i;
567 pic_level = 0;
568 for(i = 0; i < PCI_IRQ_WORDS; i++) {
569 if (pGlobals->pci_irq_levels[irq_num][i]) {
570 pic_level = 1;
571 break;
572 }
573 }
574 }
575#endif
576 return pic_level;
577}
578
579/**
580 * Set the IRQ for a PCI device.
581 *
582 * @param pDevIns Device instance of the PCI Bus.
583 * @param pPciDev The PCI device structure.
584 * @param iIrq IRQ number to set.
585 * @param iLevel IRQ level.
586 */
587PDMBOTHCBDECL(void) pciSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel)
588{
589 PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
590 PPCIGLOBALS pGlobals = PCIBUS_2_PCIGLOBALS(pBus);
591 uint8_t *pbCfg = pBus->PIIX3State.dev.config;
592 const bool fIsAcpiDevice = pPciDev->config[2] == 0x13 && pPciDev->config[3] == 0x71;
593 const bool fIsApicEnabled = pGlobals->fUseIoApic && pbCfg[0xde] == 0xbe && pbCfg[0xad] == 0xef;
594 int pic_irq, pic_level;
595 uint32_t *p;
596
597 /* apic only */
598 if (fIsApicEnabled)
599 {
600 if (fIsAcpiDevice)
601 /*
602 * ACPI needs special treatment since SCI is hardwired and
603 * should not be affected by PCI IRQ routing tables at the
604 * same time SCI IRQ is shared in PCI sense hence this
605 * kludge (i.e. we fetch the hardwired value from ACPIs
606 * PCI device configuration space).
607 */
608 apic_set_irq(pBus, pPciDev, -1, iLevel, pPciDev->config[0x3c]);
609 else
610 apic_set_irq(pBus, pPciDev, iIrq, iLevel, -1);
611 return;
612 }
613
614 if (fIsAcpiDevice)
615 {
616 /* As per above treat ACPI in a special way */
617 pic_irq = pPciDev->config[0x3c];
618 pGlobals->acpi_irq = pic_irq;
619 pGlobals->acpi_irq_level = iLevel & PDM_IRQ_LEVEL_HIGH;
620 }
621 else
622 {
623 int shift, irq_num, uIrqIndex;
624 irq_num = pci_slot_get_pirq(pPciDev, iIrq);
625 uIrqIndex = pPciDev->Int.s.iIrq;
626 p = &pGlobals->pci_irq_levels[irq_num][uIrqIndex >> 5];
627 shift = (uIrqIndex & 0x1f);
628 *p = (*p & ~(1 << shift)) | ((iLevel & PDM_IRQ_LEVEL_HIGH) << shift);
629
630 /* now we change the pic irq level according to the piix irq mappings */
631 pic_irq = pbCfg[0x60 + irq_num];
632 if (pic_irq >= 16)
633 {
634 if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP)
635 *p = (*p & ~(1 << shift));
636 return;
637 }
638 }
639
640 /* the pic level is the logical OR of all the PCI irqs mapped to it */
641 pic_level = 0;
642 if (pic_irq == pbCfg[0x60])
643 pic_level |= get_pci_irq_level(pGlobals, 0);
644 if (pic_irq == pbCfg[0x61])
645 pic_level |= get_pci_irq_level(pGlobals, 1);
646 if (pic_irq == pbCfg[0x62])
647 pic_level |= get_pci_irq_level(pGlobals, 2);
648 if (pic_irq == pbCfg[0x63])
649 pic_level |= get_pci_irq_level(pGlobals, 3);
650 if (pic_irq == pGlobals->acpi_irq)
651 pic_level |= pGlobals->acpi_irq_level;
652
653 Log3(("piix3_set_irq: %s: iLevel=%d iIrq=%d pic_irq=%d pic_level=%d\n",
654 R3STRING(pPciDev->name), iLevel, iIrq, pic_irq, pic_level));
655 pBus->CTX_SUFF(pPciHlp)->pfnIsaSetIrq(pBus->CTX_SUFF(pDevIns), pic_irq, pic_level);
656
657 /** @todo optimize pci irq flip-flop some rainy day. */
658 if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP)
659 pciSetIrq(pDevIns, pPciDev, iIrq, PDM_IRQ_LEVEL_LOW);
660}
661
662#ifdef IN_RING3
663
664static void piix3_reset(PIIX3State *d)
665{
666 uint8_t *pci_conf = d->dev.config;
667
668 pci_conf[0x04] = 0x07; /* master, memory and I/O */
669 pci_conf[0x05] = 0x00;
670 pci_conf[0x06] = 0x00;
671 pci_conf[0x07] = 0x02; /* PCI_status_devsel_medium */
672 pci_conf[0x4c] = 0x4d;
673 pci_conf[0x4e] = 0x03;
674 pci_conf[0x4f] = 0x00;
675 pci_conf[0x60] = 0x80;
676 pci_conf[0x69] = 0x02;
677 pci_conf[0x70] = 0x80;
678 pci_conf[0x76] = 0x0c;
679 pci_conf[0x77] = 0x0c;
680 pci_conf[0x78] = 0x02;
681 pci_conf[0x79] = 0x00;
682 pci_conf[0x80] = 0x00;
683 pci_conf[0x82] = 0x02; /* Get rid of the Linux guest "Enabling Passive Release" PCI quirk warning. */
684 pci_conf[0xa0] = 0x08;
685 pci_conf[0xa0] = 0x08;
686 pci_conf[0xa2] = 0x00;
687 pci_conf[0xa3] = 0x00;
688 pci_conf[0xa4] = 0x00;
689 pci_conf[0xa5] = 0x00;
690 pci_conf[0xa6] = 0x00;
691 pci_conf[0xa7] = 0x00;
692 pci_conf[0xa8] = 0x0f;
693 pci_conf[0xaa] = 0x00;
694 pci_conf[0xab] = 0x00;
695 pci_conf[0xac] = 0x00;
696 pci_conf[0xae] = 0x00;
697}
698
699static void pci_config_writel(PCIDevice *d, uint32_t addr, uint32_t val)
700{
701 PCIBus *s = d->Int.s.pBus;
702 s->uConfigReg = 0x80000000 | (s->iBus << 16) |
703 (d->devfn << 8) | addr;
704 pci_data_write(s, 0, val, 4);
705}
706
707static void pci_config_writew(PCIDevice *d, uint32_t addr, uint32_t val)
708{
709 PCIBus *s = d->Int.s.pBus;
710 s->uConfigReg = 0x80000000 | (s->iBus << 16) |
711 (d->devfn << 8) | (addr & ~3);
712 pci_data_write(s, addr & 3, val, 2);
713}
714
715static void pci_config_writeb(PCIDevice *d, uint32_t addr, uint32_t val)
716{
717 PCIBus *s = d->Int.s.pBus;
718 s->uConfigReg = 0x80000000 | (s->iBus << 16) |
719 (d->devfn << 8) | (addr & ~3);
720 pci_data_write(s, addr & 3, val, 1);
721}
722
723static uint32_t pci_config_readw(PCIDevice *d, uint32_t addr)
724{
725 PCIBus *s = d->Int.s.pBus;
726 s->uConfigReg = 0x80000000 | (s->iBus << 16) |
727 (d->devfn << 8) | (addr & ~3);
728 return pci_data_read(s, addr & 3, 2);
729}
730
731static uint32_t pci_config_readb(PCIDevice *d, uint32_t addr)
732{
733 PCIBus *s = d->Int.s.pBus;
734 s->uConfigReg = 0x80000000 | (s->iBus << 16) |
735 (d->devfn << 8) | (addr & ~3);
736 return pci_data_read(s, addr & 3, 1);
737}
738
739/* host irqs corresponding to PCI irqs A-D */
740static const uint8_t pci_irqs[4] = { 11, 9, 11, 9 }; /* bird: added const */
741
742static void pci_set_io_region_addr(PCIDevice *d, int region_num, uint32_t addr)
743{
744 PCIIORegion *r;
745 uint16_t cmd;
746 uint32_t ofs;
747
748 if ( region_num == PCI_ROM_SLOT ) {
749 ofs = 0x30;
750 }else{
751 ofs = 0x10 + region_num * 4;
752 }
753
754 pci_config_writel(d, ofs, addr);
755 r = &d->Int.s.aIORegions[region_num];
756
757 /* enable memory mappings */
758 cmd = pci_config_readw(d, PCI_COMMAND);
759 if ( region_num == PCI_ROM_SLOT )
760 cmd |= 2;
761 else if (r->type & PCI_ADDRESS_SPACE_IO)
762 cmd |= 1;
763 else
764 cmd |= 2;
765 pci_config_writew(d, PCI_COMMAND, cmd);
766}
767
768static void pci_bios_init_device(PCIDevice *d)
769{
770 int devclass;
771 PCIIORegion *r;
772 uint32_t *paddr;
773 int i, pin, pic_irq, vendor_id, device_id;
774
775 devclass = pci_config_readw(d, PCI_CLASS_DEVICE);
776 vendor_id = pci_config_readw(d, PCI_VENDOR_ID);
777 device_id = pci_config_readw(d, PCI_DEVICE_ID);
778 switch(devclass)
779 {
780 case 0x0101:
781 if (vendor_id == 0x8086 &&
782 (device_id == 0x7010 || device_id == 0x7111)) {
783 /* PIIX3 or PIIX4 IDE */
784 pci_config_writew(d, 0x40, 0x8000); /* enable IDE0 */
785 pci_config_writew(d, 0x42, 0x8000); /* enable IDE1 */
786 goto default_map;
787 } else {
788 /* IDE: we map it as in ISA mode */
789 pci_set_io_region_addr(d, 0, 0x1f0);
790 pci_set_io_region_addr(d, 1, 0x3f4);
791 pci_set_io_region_addr(d, 2, 0x170);
792 pci_set_io_region_addr(d, 3, 0x374);
793 }
794 break;
795 case 0x0300:
796 if (vendor_id != 0x80ee)
797 goto default_map;
798 /* VGA: map frame buffer to default Bochs VBE address */
799 pci_set_io_region_addr(d, 0, 0xE0000000);
800 break;
801 case 0x0800:
802 /* PIC */
803 vendor_id = pci_config_readw(d, PCI_VENDOR_ID);
804 device_id = pci_config_readw(d, PCI_DEVICE_ID);
805 if (vendor_id == 0x1014) {
806 /* IBM */
807 if (device_id == 0x0046 || device_id == 0xFFFF) {
808 /* MPIC & MPIC2 */
809 pci_set_io_region_addr(d, 0, 0x80800000 + 0x00040000);
810 }
811 }
812 break;
813 case 0xff00:
814 if (vendor_id == 0x0106b &&
815 (device_id == 0x0017 || device_id == 0x0022)) {
816 /* macio bridge */
817 pci_set_io_region_addr(d, 0, 0x80800000);
818 }
819 break;
820 default:
821 default_map:
822 /* default memory mappings */
823 for(i = 0; i < PCI_NUM_REGIONS; i++) {
824 r = &d->Int.s.aIORegions[i];
825
826 if (r->size) {
827 if (r->type & PCI_ADDRESS_SPACE_IO)
828 paddr = &PCIBUS_2_PCIGLOBALS(d->Int.s.pBus)->pci_bios_io_addr;
829 else
830 paddr = &PCIBUS_2_PCIGLOBALS(d->Int.s.pBus)->pci_bios_mem_addr;
831 *paddr = (*paddr + r->size - 1) & ~(r->size - 1);
832 pci_set_io_region_addr(d, i, *paddr);
833 *paddr += r->size;
834 }
835 }
836 break;
837 }
838
839 /* map the interrupt */
840 pin = pci_config_readb(d, PCI_INTERRUPT_PIN);
841 if (pin != 0) {
842 pin = pci_slot_get_pirq(d, pin - 1);
843 pic_irq = pci_irqs[pin];
844 pci_config_writeb(d, PCI_INTERRUPT_LINE, pic_irq);
845 }
846}
847
848/* -=-=-=-=-=- wrappers -=-=-=-=-=- */
849
850/**
851 * Port I/O Handler for PCI address OUT operations.
852 *
853 * @returns VBox status code.
854 *
855 * @param pDevIns The device instance.
856 * @param pvUser User argument - ignored.
857 * @param uPort Port number used for the IN operation.
858 * @param u32 The value to output.
859 * @param cb The value size in bytes.
860 */
861static DECLCALLBACK(int) pciIOPortAddressWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
862{
863 Log(("pciIOPortAddressWrite: Port=%#x u32=%#x cb=%d\n", Port, u32, cb));
864 NOREF(pvUser);
865 if (cb == 4)
866 {
867 PCI_LOCK(pDevIns, VINF_IOM_HC_IOPORT_WRITE);
868 pci_addr_writel(PDMINS_2_DATA(pDevIns, PCIBus *), Port, u32);
869 PCI_UNLOCK(pDevIns);
870 }
871 /* else: 440FX does "pass through to the bus" for other writes, what ever that means.
872 * Linux probes for cmd640 using byte writes/reads during ide init. We'll just ignore it. */
873 return VINF_SUCCESS;
874}
875
876/**
877 * Port I/O Handler for PCI address IN operations.
878 *
879 * @returns VBox status code.
880 *
881 * @param pDevIns The device instance.
882 * @param pvUser User argument - ignored.
883 * @param uPort Port number used for the IN operation.
884 * @param pu32 Where to store the result.
885 * @param cb Number of bytes read.
886 */
887static DECLCALLBACK(int) pciIOPortAddressRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
888{
889 NOREF(pvUser);
890 if (cb == 4)
891 {
892 PCI_LOCK(pDevIns, VINF_IOM_HC_IOPORT_READ);
893 *pu32 = pci_addr_readl(PDMINS_2_DATA(pDevIns, PCIBus *), Port);
894 PCI_UNLOCK(pDevIns);
895 Log(("pciIOPortAddressRead: Port=%#x cb=%d -> %#x\n", Port, cb, *pu32));
896 return VINF_SUCCESS;
897 }
898 /* else: 440FX does "pass through to the bus" for other writes, what ever that means.
899 * Linux probes for cmd640 using byte writes/reads during ide init. We'll just ignore it. */
900 Log(("pciIOPortAddressRead: Port=%#x cb=%d VERR_IOM_IOPORT_UNUSED\n", Port, cb));
901 return VERR_IOM_IOPORT_UNUSED;
902}
903
904
905/**
906 * Port I/O Handler for PCI data OUT operations.
907 *
908 * @returns VBox status code.
909 *
910 * @param pDevIns The device instance.
911 * @param pvUser User argument - ignored.
912 * @param uPort Port number used for the IN operation.
913 * @param u32 The value to output.
914 * @param cb The value size in bytes.
915 */
916static DECLCALLBACK(int) pciIOPortDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
917{
918 Log(("pciIOPortDataWrite: Port=%#x u32=%#x cb=%d\n", Port, u32, cb));
919 NOREF(pvUser);
920 if (!(Port % cb))
921 {
922 PCI_LOCK(pDevIns, VINF_IOM_HC_IOPORT_WRITE);
923 pci_data_write(PDMINS_2_DATA(pDevIns, PCIBus *), Port, u32, cb);
924 PCI_UNLOCK(pDevIns);
925 }
926 else
927 AssertMsgFailed(("Write to port %#x u32=%#x cb=%d\n", Port, u32, cb));
928 return VINF_SUCCESS;
929}
930
931
932/**
933 * Port I/O Handler for PCI data IN operations.
934 *
935 * @returns VBox status code.
936 *
937 * @param pDevIns The device instance.
938 * @param pvUser User argument - ignored.
939 * @param uPort Port number used for the IN operation.
940 * @param pu32 Where to store the result.
941 * @param cb Number of bytes read.
942 */
943static DECLCALLBACK(int) pciIOPortDataRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
944{
945 NOREF(pvUser);
946 if (!(Port % cb))
947 {
948 PCI_LOCK(pDevIns, VINF_IOM_HC_IOPORT_READ);
949 *pu32 = pci_data_read(PDMINS_2_DATA(pDevIns, PCIBus *), Port, cb);
950 PCI_UNLOCK(pDevIns);
951 Log(("pciIOPortDataRead: Port=%#x cb=%#x -> %#x\n", Port, cb, *pu32));
952 return VINF_SUCCESS;
953 }
954 AssertMsgFailed(("Read from port %#x cb=%d\n", Port, cb));
955 return VERR_IOM_IOPORT_UNUSED;
956}
957
958
959/**
960 * Saves a state of the PCI device.
961 *
962 * @returns VBox status code.
963 * @param pDevIns Device instance of the PCI Bus.
964 * @param pPciDev Pointer to PCI device.
965 * @param pSSMHandle The handle to save the state to.
966 */
967static DECLCALLBACK(int) pciGenericSaveExec(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PSSMHANDLE pSSMHandle)
968{
969 return SSMR3PutMem(pSSMHandle, &pPciDev->config[0], sizeof(pPciDev->config));
970}
971
972
973/**
974 * Loads a saved PCI device state.
975 *
976 * @returns VBox status code.
977 * @param pDevIns Device instance of the PCI Bus.
978 * @param pPciDev Pointer to PCI device.
979 * @param pSSMHandle The handle to the saved state.
980 */
981static DECLCALLBACK(int) pciGenericLoadExec(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PSSMHANDLE pSSMHandle)
982{
983 return SSMR3GetMem(pSSMHandle, &pPciDev->config[0], sizeof(pPciDev->config));
984}
985
986
987/**
988 * Saves a state of the PCI device.
989 *
990 * @returns VBox status code.
991 * @param pDevIns The device instance.
992 * @param pPciDev Pointer to PCI device.
993 * @param pSSMHandle The handle to save the state to.
994 */
995static DECLCALLBACK(int) pciSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle)
996{
997 uint32_t i;
998 PPCIBUS pThis = PDMINS_2_DATA(pDevIns, PPCIBUS);
999 PPCIGLOBALS pGlobals = PCIBUS_2_PCIGLOBALS(pThis);
1000
1001 /*
1002 * Bus state data.
1003 */
1004 SSMR3PutU32(pSSMHandle, pThis->uConfigReg);
1005 SSMR3PutBool(pSSMHandle, pGlobals->fUseIoApic);
1006 SSMR3PutU32(pSSMHandle, ~0); /* separator */
1007
1008 /*
1009 * Iterate all the devices.
1010 */
1011 for (i = 0; i < RT_ELEMENTS(pThis->devices); i++)
1012 {
1013 PPCIDEVICE pDev = pThis->devices[i];
1014 if (pDev)
1015 {
1016 int rc;
1017 SSMR3PutU32(pSSMHandle, i);
1018 SSMR3PutMem(pSSMHandle, pDev->config, sizeof(pDev->config));
1019 rc = SSMR3PutS32(pSSMHandle, pDev->Int.s.iIrq);
1020 if (RT_FAILURE(rc))
1021 return rc;
1022 }
1023 }
1024 return SSMR3PutU32(pSSMHandle, ~0); /* terminator */
1025}
1026
1027/**
1028 * Loads a saved PCI device state.
1029 *
1030 * @returns VBox status code.
1031 * @param pDevIns The device instance.
1032 * @param pSSMHandle The handle to the saved state.
1033 * @param u32Version The data unit version number.
1034 */
1035static DECLCALLBACK(int) pciLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle, uint32_t u32Version)
1036{
1037 PPCIBUS pThis = PDMINS_2_DATA(pDevIns, PPCIBUS);
1038 PPCIGLOBALS pGlobals = PCIBUS_2_PCIGLOBALS(pThis);
1039 uint32_t u32;
1040 uint32_t i;
1041 int rc;
1042
1043 /*
1044 * Check the version.
1045 */
1046 if (u32Version > 2)
1047 {
1048 AssertFailed();
1049 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1050 }
1051
1052 /*
1053 * Bus state data.
1054 */
1055 SSMR3GetU32(pSSMHandle, &pThis->uConfigReg);
1056 if (u32Version > 1)
1057 SSMR3GetBool(pSSMHandle, &pGlobals->fUseIoApic);
1058
1059 /* separator */
1060 rc = SSMR3GetU32(pSSMHandle, &u32);
1061 if (RT_FAILURE(rc))
1062 return rc;
1063 if (u32 != (uint32_t)~0)
1064 AssertMsgFailedReturn(("u32=%#x\n", u32), rc);
1065
1066 /*
1067 * Iterate all the devices.
1068 */
1069 for (i = 0;; i++)
1070 {
1071 PCIDEVICE DevTmp;
1072 PPCIDEVICE pDev;
1073
1074 /* index / terminator */
1075 rc = SSMR3GetU32(pSSMHandle, &u32);
1076 if (RT_FAILURE(rc))
1077 return rc;
1078 if (u32 == (uint32_t)~0)
1079 break;
1080 if ( u32 >= RT_ELEMENTS(pThis->devices)
1081 || u32 < i)
1082 {
1083 AssertMsgFailed(("u32=%#x i=%#x\n", u32, i));
1084 return rc;
1085 }
1086
1087 /* skip forward to the device checking that no new devices are present. */
1088 for (; i < u32; i++)
1089 {
1090 if (pThis->devices[i])
1091 {
1092 LogRel(("New device in slot %#x, %s (vendor=%#06x device=%#06x)\n", i, pThis->devices[i]->name,
1093 PCIDevGetVendorId(pThis->devices[i]), PCIDevGetDeviceId(pThis->devices[i])));
1094 if (SSMR3HandleGetAfter(pSSMHandle) != SSMAFTER_DEBUG_IT)
1095 AssertFailedReturn(VERR_SSM_LOAD_CONFIG_MISMATCH);
1096 }
1097 }
1098
1099 /* get the data */
1100 SSMR3GetMem(pSSMHandle, DevTmp.config, sizeof(DevTmp.config));
1101 rc = SSMR3GetS32(pSSMHandle, &DevTmp.Int.s.iIrq);
1102 if (RT_FAILURE(rc))
1103 return rc;
1104
1105 /* check that it's still around. */
1106 pDev = pThis->devices[i];
1107 if (!pDev)
1108 {
1109 LogRel(("Device in slot %#x has been removed! vendor=%#06x device=%#06x\n", i,
1110 PCIDevGetVendorId(&DevTmp), PCIDevGetDeviceId(&DevTmp)));
1111 if (SSMR3HandleGetAfter(pSSMHandle) != SSMAFTER_DEBUG_IT)
1112 AssertFailedReturn(VERR_SSM_LOAD_CONFIG_MISMATCH);
1113 continue;
1114 }
1115
1116 /* match the vendor id assuming that this will never be changed. */
1117 if ( DevTmp.config[0] != pDev->config[0]
1118 || DevTmp.config[1] != pDev->config[1])
1119 {
1120 LogRel(("Device in slot %#x (%s) vendor id mismatch! saved=%.4Vhxs current=%.4Vhxs\n",
1121 i, pDev->name, DevTmp.config, pDev->config));
1122 AssertFailedReturn(VERR_SSM_LOAD_CONFIG_MISMATCH);
1123 }
1124
1125 /* commit the loaded device config. */
1126 memcpy(pDev->config, DevTmp.config, sizeof(pDev->config));
1127 if (DevTmp.Int.s.iIrq >= PCI_DEVICES_MAX)
1128 {
1129 LogRel(("Device %s: Too many devices %d (max=%d)\n", pDev->name, DevTmp.Int.s.iIrq, PCI_DEVICES_MAX));
1130 AssertFailedReturn(VERR_TOO_MUCH_DATA);
1131 }
1132
1133 pDev->Int.s.iIrq = DevTmp.Int.s.iIrq;
1134 }
1135 return VINF_SUCCESS;
1136}
1137
1138
1139/* -=-=-=-=-=- real code -=-=-=-=-=- */
1140
1141
1142/**
1143 * Registers the device with the default PCI bus.
1144 *
1145 * @returns VBox status code.
1146 * @param pBus The bus to register with.
1147 * @param iDev The PCI device ordinal.
1148 * @param pPciDev The PCI device structure.
1149 * @param pszName Pointer to device name (permanent, readonly). For debugging, not unique.
1150 */
1151static void pciRegisterInternal(PPCIBUS pBus, int iDev, PPCIDEVICE pPciDev, const char *pszName)
1152{
1153 Assert(!pBus->devices[iDev]);
1154 pPciDev->devfn = iDev;
1155 pPciDev->name = pszName;
1156 pPciDev->Int.s.pBus = pBus;
1157 pPciDev->Int.s.pfnConfigRead = pci_default_read_config;
1158 pPciDev->Int.s.pfnConfigWrite = pci_default_write_config;
1159 AssertMsg(pBus->uIrqIndex < PCI_DEVICES_MAX,
1160 ("Device %s: Too many devices %d (max=%d)\n",
1161 pszName, pBus->uIrqIndex, PCI_DEVICES_MAX));
1162 pPciDev->Int.s.iIrq = pBus->uIrqIndex++;
1163 pBus->devices[iDev] = pPciDev;
1164 Log(("PCI: Registered device %d function %d (%#x) '%s'.\n",
1165 iDev >> 3, iDev & 7, 0x80000000 | (iDev << 8), pszName));
1166}
1167
1168
1169/**
1170 * Registers the device with the default PCI bus.
1171 *
1172 * @returns VBox status code.
1173 * @param pDevIns Device instance of the PCI Bus.
1174 * @param pPciDev The PCI device structure.
1175 * Any PCI enabled device must keep this in it's instance data!
1176 * Fill in the PCI data config before registration, please.
1177 * @param pszName Pointer to device name (permanent, readonly). For debugging, not unique.
1178 * @param iDev The PCI device number. Use a negative value for auto assigning one.
1179 */
1180static DECLCALLBACK(int) pciRegister(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, const char *pszName, int iDev)
1181{
1182 PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
1183
1184 /*
1185 * Check input.
1186 */
1187 if ( !pszName
1188 || !pPciDev
1189 || iDev >= (int)RT_ELEMENTS(pBus->devices)
1190 || (iDev >= 0 && iDev <= 8))
1191 {
1192 AssertMsgFailed(("Invalid argument! pszName=%s pPciDev=%p iDev=%d\n", pszName, pPciDev, iDev));
1193 return VERR_INVALID_PARAMETER;
1194 }
1195
1196 /*
1197 * Find device slot.
1198 */
1199 if (iDev < 0)
1200 {
1201 /*
1202 * Special check for the IDE controller which is our function 1 device
1203 * before searching.
1204 */
1205 if ( !strcmp(pszName, "piix3ide")
1206 && !pBus->devices[9])
1207 iDev = 9;
1208 else
1209 {
1210 Assert(!(pBus->iDevSearch % 8));
1211 for (iDev = pBus->iDevSearch; iDev < (int)RT_ELEMENTS(pBus->devices); iDev += 8)
1212 if ( !pBus->devices[iDev]
1213 && !pBus->devices[iDev + 1]
1214 && !pBus->devices[iDev + 2]
1215 && !pBus->devices[iDev + 3]
1216 && !pBus->devices[iDev + 4]
1217 && !pBus->devices[iDev + 5]
1218 && !pBus->devices[iDev + 6]
1219 && !pBus->devices[iDev + 7])
1220 break;
1221 if (iDev >= (int)RT_ELEMENTS(pBus->devices))
1222 {
1223 AssertMsgFailed(("Couldn't find free spot!\n"));
1224 return VERR_PDM_TOO_PCI_MANY_DEVICES;
1225 }
1226 }
1227 pPciDev->Int.s.fRequestedDevFn = false;
1228 }
1229 else
1230 {
1231 /*
1232 * An explicit request.
1233 *
1234 * If the slot is occupied we'll have to relocate the device
1235 * currently occupying it first. This can only be done if the
1236 * existing device wasn't explicitly assigned. Also we limit
1237 * ourselves to function 0 devices.
1238 *
1239 * If you start setting devices + function in the
1240 * config, do it for all pci devices!
1241 */
1242 AssertReleaseMsg(iDev > 8, ("iDev=%d pszName=%s\n", iDev, pszName));
1243 if (pBus->devices[iDev])
1244 {
1245 int iDevRel;
1246 AssertReleaseMsg(!(iDev % 8), ("PCI Configuration Conflict! iDev=%d pszName=%s clashes with %s\n",
1247 iDev, pszName, pBus->devices[iDev]->name));
1248 if ( pBus->devices[iDev]->Int.s.fRequestedDevFn
1249 || (pBus->devices[iDev + 1] && pBus->devices[iDev + 1]->Int.s.fRequestedDevFn)
1250 || (pBus->devices[iDev + 2] && pBus->devices[iDev + 2]->Int.s.fRequestedDevFn)
1251 || (pBus->devices[iDev + 3] && pBus->devices[iDev + 3]->Int.s.fRequestedDevFn)
1252 || (pBus->devices[iDev + 4] && pBus->devices[iDev + 4]->Int.s.fRequestedDevFn)
1253 || (pBus->devices[iDev + 5] && pBus->devices[iDev + 5]->Int.s.fRequestedDevFn)
1254 || (pBus->devices[iDev + 6] && pBus->devices[iDev + 6]->Int.s.fRequestedDevFn)
1255 || (pBus->devices[iDev + 7] && pBus->devices[iDev + 7]->Int.s.fRequestedDevFn))
1256 {
1257 AssertReleaseMsgFailed(("Configuration error:'%s' and '%s' are both configured as device %d\n",
1258 pszName, pBus->devices[iDev]->name, iDev));
1259 return VERR_INTERNAL_ERROR;
1260 }
1261
1262 /* Find free slot for the device(s) we're moving and move them. */
1263 for (iDevRel = pBus->iDevSearch; iDevRel < (int)RT_ELEMENTS(pBus->devices); iDevRel += 8)
1264 {
1265 if ( !pBus->devices[iDevRel]
1266 && !pBus->devices[iDevRel + 1]
1267 && !pBus->devices[iDevRel + 2]
1268 && !pBus->devices[iDevRel + 3]
1269 && !pBus->devices[iDevRel + 4]
1270 && !pBus->devices[iDevRel + 5]
1271 && !pBus->devices[iDevRel + 6]
1272 && !pBus->devices[iDevRel + 7])
1273 {
1274 int i = 0;
1275 for (i = 0; i < 8; i++)
1276 {
1277 if (!pBus->devices[iDev + i])
1278 continue;
1279 Log(("PCI: relocating '%s' from slot %#x to %#x\n", pBus->devices[iDev + i]->name, iDev + i, iDevRel + i));
1280 pBus->devices[iDevRel + i] = pBus->devices[iDev + i];
1281 pBus->devices[iDevRel + i]->devfn = i;
1282 pBus->devices[iDev + i] = NULL;
1283 }
1284 }
1285 }
1286 if (pBus->devices[iDev])
1287 {
1288 AssertMsgFailed(("Couldn't find free spot!\n"));
1289 return VERR_PDM_TOO_PCI_MANY_DEVICES;
1290 }
1291 } /* if conflict */
1292 pPciDev->Int.s.fRequestedDevFn = true;
1293 }
1294
1295 /*
1296 * Register the device.
1297 */
1298 pciRegisterInternal(pBus, iDev, pPciDev, pszName);
1299 return VINF_SUCCESS;
1300}
1301
1302
1303static DECLCALLBACK(int) pciIORegionRegister(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iRegion, uint32_t cbRegion, PCIADDRESSSPACE enmType, PFNPCIIOREGIONMAP pfnCallback)
1304{
1305
1306 /*
1307 * Validate.
1308 */
1309 if ( enmType != PCI_ADDRESS_SPACE_MEM
1310 && enmType != PCI_ADDRESS_SPACE_IO
1311 && enmType != PCI_ADDRESS_SPACE_MEM_PREFETCH)
1312 {
1313 AssertMsgFailed(("Invalid enmType=%#x? Or was this a bitmask after all...\n", enmType));
1314 return VERR_INVALID_PARAMETER;
1315 }
1316 if ((unsigned)iRegion >= PCI_NUM_REGIONS)
1317 {
1318 AssertMsgFailed(("Invalid iRegion=%d PCI_NUM_REGIONS=%d\n", iRegion, PCI_NUM_REGIONS));
1319 return VERR_INVALID_PARAMETER;
1320 }
1321
1322 /*
1323 * Register the I/O region.
1324 */
1325 PPCIIOREGION pRegion = &pPciDev->Int.s.aIORegions[iRegion];
1326 pRegion->addr = ~0U;
1327 pRegion->size = cbRegion;
1328 pRegion->type = enmType;
1329 pRegion->map_func = pfnCallback;
1330 return VINF_SUCCESS;
1331}
1332
1333
1334/**
1335 * @copydoc PDMPCIBUSREG::pfnSetConfigCallbacksHC
1336 */
1337static DECLCALLBACK(void) pciSetConfigCallbacks(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PFNPCICONFIGREAD pfnRead, PPFNPCICONFIGREAD ppfnReadOld,
1338 PFNPCICONFIGWRITE pfnWrite, PPFNPCICONFIGWRITE ppfnWriteOld)
1339{
1340 if (ppfnReadOld)
1341 *ppfnReadOld = pPciDev->Int.s.pfnConfigRead;
1342 pPciDev->Int.s.pfnConfigRead = pfnRead;
1343
1344 if (ppfnWriteOld)
1345 *ppfnWriteOld = pPciDev->Int.s.pfnConfigWrite;
1346 pPciDev->Int.s.pfnConfigWrite = pfnWrite;
1347}
1348
1349
1350/**
1351 * Called to perform the job of the bios.
1352 *
1353 * @returns VBox status.
1354 * @param pDevIns Device instance of the first bus.
1355 */
1356static DECLCALLBACK(int) pciFakePCIBIOS(PPDMDEVINS pDevIns)
1357{
1358 int rc;
1359 unsigned i;
1360 uint8_t elcr[2] = {0, 0};
1361 PPCIGLOBALS pGlobals = DEVINS_2_PCIGLOBALS(pDevIns);
1362 PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
1363 PVM pVM = PDMDevHlpGetVM(pDevIns);
1364 Assert(pVM);
1365
1366 /*
1367 * Set the start addresses.
1368 */
1369 pGlobals->pci_bios_io_addr = 0xc000;
1370 pGlobals->pci_bios_mem_addr = UINT32_C(0xf0000000);
1371
1372 /*
1373 * Activate IRQ mappings.
1374 */
1375 for (i = 0; i < 4; i++)
1376 {
1377 uint8_t irq = pci_irqs[i];
1378 /* Set to trigger level. */
1379 elcr[irq >> 3] |= (1 << (irq & 7));
1380 /* Activate irq remapping in PIIX3. */
1381 pci_config_writeb(&pBus->PIIX3State.dev, 0x60 + i, irq);
1382 }
1383
1384 /* Tell to the PIC. */
1385 rc = IOMIOPortWrite(pVM, 0x4d0, elcr[0], sizeof(uint8_t));
1386 if (rc == VINF_SUCCESS)
1387 rc = IOMIOPortWrite(pVM, 0x4d1, elcr[1], sizeof(uint8_t));
1388 if (rc != VINF_SUCCESS)
1389 {
1390 AssertMsgFailed(("Writing to PIC failed!\n"));
1391 return RT_SUCCESS(rc) ? VERR_INTERNAL_ERROR : rc;
1392 }
1393
1394 /*
1395 * Init the devices.
1396 */
1397 for (i = 0; i < RT_ELEMENTS(pBus->devices); i++)
1398 {
1399 if (pBus->devices[i])
1400 {
1401 Log2(("PCI: Initializing device %d (%#x) '%s'\n",
1402 i, 0x80000000 | (i << 8), pBus->devices[i]->name));
1403 pci_bios_init_device(pBus->devices[i]);
1404 }
1405 }
1406 return VINF_SUCCESS;
1407}
1408
1409/**
1410 * @copydoc FNPDMDEVRELOCATE
1411 */
1412static DECLCALLBACK(void) pciRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
1413{
1414 PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
1415 pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
1416 pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
1417}
1418
1419
1420/**
1421 * Construct a PCI Bus device instance for a VM.
1422 *
1423 * @returns VBox status.
1424 * @param pDevIns The device instance data.
1425 * If the registration structure is needed, pDevIns->pDevReg points to it.
1426 * @param iInstance Instance number. Use this to figure out which registers and such to use.
1427 * The device number is also found in pDevIns->iInstance, but since it's
1428 * likely to be freqently used PDM passes it as parameter.
1429 * @param pCfgHandle Configuration node handle for the device. Use this to obtain the configuration
1430 * of the device instance. It's also found in pDevIns->pCfgHandle, but like
1431 * iInstance it's expected to be used a bit in this function.
1432 */
1433static DECLCALLBACK(int) pciConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfgHandle)
1434{
1435 int rc;
1436 Assert(iInstance == 0);
1437
1438 /*
1439 * Validate and read configuration.
1440 */
1441 if (!CFGMR3AreValuesValid(pCfgHandle, "IOAPIC\0" "GCEnabled\0" "R0Enabled\0"))
1442 return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
1443
1444 /* query whether we got an IOAPIC */
1445 bool fUseIoApic;
1446 rc = CFGMR3QueryBoolDef(pCfgHandle, "IOAPIC", &fUseIoApic, false);
1447 if (RT_FAILURE(rc))
1448 return PDMDEV_SET_ERROR(pDevIns, rc,
1449 N_("Configuration error: Failed to query boolean value \"IOAPIC\""));
1450
1451 /* check if RC code is enabled. */
1452 bool fGCEnabled;
1453 rc = CFGMR3QueryBoolDef(pCfgHandle, "GCEnabled", &fGCEnabled, true);
1454 if (RT_FAILURE(rc))
1455 return PDMDEV_SET_ERROR(pDevIns, rc,
1456 N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
1457
1458 /* check if R0 code is enabled. */
1459 bool fR0Enabled;
1460 rc = CFGMR3QueryBoolDef(pCfgHandle, "R0Enabled", &fR0Enabled, true);
1461 if (RT_FAILURE(rc))
1462 return PDMDEV_SET_ERROR(pDevIns, rc,
1463 N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
1464 Log(("PCI: fUseIoApic=%RTbool fGCEnabled=%RTbool fR0Enabled=%RTbool\n", fUseIoApic, fGCEnabled, fR0Enabled));
1465
1466 /*
1467 * Init data and register the PCI bus.
1468 */
1469 PPCIGLOBALS pGlobals = DEVINS_2_PCIGLOBALS(pDevIns);
1470 pGlobals->pci_mem_base = 0;
1471 pGlobals->pci_bios_io_addr = 0xc000;
1472 pGlobals->pci_bios_mem_addr = 0xf0000000;
1473 memset(&pGlobals->pci_irq_levels, 0, sizeof(pGlobals->pci_irq_levels));
1474 pGlobals->fUseIoApic = fUseIoApic;
1475 memset(&pGlobals->pci_apic_irq_levels, 0, sizeof(pGlobals->pci_apic_irq_levels));
1476
1477 PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
1478 pBus->pDevInsR3 = pDevIns;
1479 pBus->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
1480 pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
1481
1482 PDMPCIBUSREG PciBusReg;
1483 PciBusReg.u32Version = PDM_PCIBUSREG_VERSION;
1484 PciBusReg.pfnRegisterR3 = pciRegister;
1485 PciBusReg.pfnIORegionRegisterR3 = pciIORegionRegister;
1486 PciBusReg.pfnSetConfigCallbacksR3 = pciSetConfigCallbacks;
1487 PciBusReg.pfnSetIrqR3 = pciSetIrq;
1488 PciBusReg.pfnSaveExecR3 = pciGenericSaveExec;
1489 PciBusReg.pfnLoadExecR3 = pciGenericLoadExec;
1490 PciBusReg.pfnFakePCIBIOSR3 = pciFakePCIBIOS;
1491 PciBusReg.pszSetIrqRC = fGCEnabled ? "pciSetIrq" : NULL;
1492 PciBusReg.pszSetIrqR0 = fR0Enabled ? "pciSetIrq" : NULL;
1493 rc = pDevIns->pDevHlp->pfnPCIBusRegister(pDevIns, &PciBusReg, &pBus->pPciHlpR3);
1494 if (RT_FAILURE(rc))
1495 return PDMDEV_SET_ERROR(pDevIns, rc,
1496 N_("Failed to register ourselves as a PCI Bus"));
1497 if (pBus->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
1498 return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
1499 N_("PCI helper version mismatch; got %#x expected %#x"),
1500 pBus->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION);
1501
1502 pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
1503 pBus->pPciHlpR0 = pBus->pPciHlpR3->pfnGetR0Helpers(pDevIns);
1504
1505 /*
1506 * Fill in PCI configs and add them to the bus.
1507 */
1508 /* i440FX */
1509 PCIDevSetVendorId( &pBus->PciDev, 0x8086); /* Intel */
1510 PCIDevSetDeviceId( &pBus->PciDev, 0x1237);
1511 PCIDevSetRevisionId(&pBus->PciDev, 0x02);
1512 PCIDevSetClassSub( &pBus->PciDev, 0x00); /* host2pci */
1513 PCIDevSetClassBase( &pBus->PciDev, 0x06); /* PCI_bridge */
1514 PCIDevSetHeaderType(&pBus->PciDev, 0x00);
1515
1516 pBus->PciDev.pDevIns = pDevIns;
1517 pBus->PciDev.Int.s.fRequestedDevFn= true;
1518 pciRegisterInternal(pBus, 0, &pBus->PciDev, "i440FX");
1519
1520 /* PIIX3 */
1521 PCIDevSetVendorId( &pBus->PIIX3State.dev, 0x8086); /* Intel */
1522 PCIDevSetDeviceId( &pBus->PIIX3State.dev, 0x7000); /* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */
1523 PCIDevSetClassSub( &pBus->PIIX3State.dev, 0x01); /* PCI_ISA */
1524 PCIDevSetClassBase( &pBus->PIIX3State.dev, 0x06); /* PCI_bridge */
1525 PCIDevSetHeaderType(&pBus->PIIX3State.dev, 0x80); /* PCI_multifunction, generic */
1526
1527 pBus->PIIX3State.dev.pDevIns = pDevIns;
1528 pBus->PciDev.Int.s.fRequestedDevFn= true;
1529 pciRegisterInternal(pBus, 8, &pBus->PIIX3State.dev, "PIIX3");
1530 piix3_reset(&pBus->PIIX3State);
1531
1532 pBus->iDevSearch = 16;
1533
1534 /*
1535 * Register I/O ports and save state.
1536 */
1537 rc = PDMDevHlpIOPortRegister(pDevIns, 0x0cf8, 1, NULL, pciIOPortAddressWrite, pciIOPortAddressRead, NULL, NULL, "i440FX (PCI)");
1538 if (RT_FAILURE(rc))
1539 return rc;
1540 rc = PDMDevHlpIOPortRegister(pDevIns, 0x0cfc, 4, NULL, pciIOPortDataWrite, pciIOPortDataRead, NULL, NULL, "i440FX (PCI)");
1541 if (RT_FAILURE(rc))
1542 return rc;
1543 rc = PDMDevHlpSSMRegister(pDevIns, "pci", iInstance, 2, sizeof(*pBus),
1544 NULL, pciSaveExec, NULL, NULL, pciLoadExec, NULL);
1545 if (RT_FAILURE(rc))
1546 return rc;
1547
1548 return VINF_SUCCESS;
1549}
1550
1551
1552/**
1553 * The device registration structure.
1554 */
1555const PDMDEVREG g_DevicePCI =
1556{
1557 /* u32Version */
1558 PDM_DEVREG_VERSION,
1559 /* szDeviceName */
1560 "pci",
1561 /* szGCMod */
1562 "VBoxDDGC.gc",
1563 /* szR0Mod */
1564 "VBoxDDR0.r0",
1565 /* pszDescription */
1566 "i440FX PCI bridge and PIIX3 ISA bridge.",
1567 /* fFlags */
1568 PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT | PDM_DEVREG_FLAGS_GUEST_BITS_32 | PDM_DEVREG_FLAGS_GC | PDM_DEVREG_FLAGS_R0,
1569 /* fClass */
1570 PDM_DEVREG_CLASS_BUS_PCI | PDM_DEVREG_CLASS_BUS_ISA,
1571 /* cMaxInstances */
1572 1,
1573 /* cbInstance */
1574 sizeof(PCIBUS),
1575 /* pfnConstruct */
1576 pciConstruct,
1577 /* pfnDestruct */
1578 NULL,
1579 /* pfnRelocate */
1580 pciRelocate,
1581 /* pfnIOCtl */
1582 NULL,
1583 /* pfnPowerOn */
1584 NULL,
1585 /* pfnReset */
1586 NULL,
1587 /* pfnSuspend */
1588 NULL,
1589 /* pfnResume */
1590 NULL,
1591 /* pfnAttach */
1592 NULL,
1593 /* pfnDetach */
1594 NULL,
1595 /* pfnQueryInterface */
1596 NULL,
1597 /* pfnInitComplete */
1598 NULL
1599};
1600#endif /* IN_RING3 */
1601#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
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