DevPCI.cpp@ 1959

Last change on this file since 1959 was 486, checked in by vboxsync, 18 years ago
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1	/** @file
2	*
3	* PCI Device.
4	*/
5
6	/*
7	* Copyright (C) 2006 InnoTek Systemberatung GmbH
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License as published by the Free Software Foundation,
13	* in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
14	* distribution. VirtualBox OSE is distributed in the hope that it will
15	* be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* If you received this file as part of a commercial VirtualBox
18	* distribution, then only the terms of your commercial VirtualBox
19	* license agreement apply instead of the previous paragraph.
20	*
21	* --------------------------------------------------------------------
22	*
23	* This code is based on:
24	*
25	* QEMU PCI bus manager
26	*
27	* Copyright (c) 2004 Fabrice Bellard
28	*
29	* Permission is hereby granted, free of charge, to any person obtaining a copy
30	* of this software and associated documentation files (the "Software"), to deal
31	* in the Software without restriction, including without limitation the rights
32	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
33	* copies of the Software, and to permit persons to whom the Software is
34	* furnished to do so, subject to the following conditions:
35	*
36	* The above copyright notice and this permission notice shall be included in
37	* all copies or substantial portions of the Software.
38	*
39	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
40	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
41	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
42	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
43	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
44	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
45	* THE SOFTWARE.
46	*/
47
48	/*******************************************************************************
49	* Header Files *
50	*******************************************************************************/
51	#define LOG_GROUP LOG_GROUP_DEV_PCI
52	/* Hack to get PCIDEVICEINT declare at the right point - include "PCIInternal.h". */
53	#define PCI_INCLUDE_PRIVATE
54	#include "vl_vbox.h"
55	#include <VBox/pci.h>
56	#include <VBox/pdm.h>
57	#include <VBox/err.h>
58
59	#include <VBox/log.h>
60	#include <iprt/assert.h>
61
62	#include "Builtins.h"
63
64
65	/*******************************************************************************
66	* Defined Constants And Macros *
67	*******************************************************************************/
68	/** @def PCI_LOCK
69	* Acquires the PDM lock. This is a NOP if locking is disabled. */
70	/** @def PCI_UNLOCK
71	* Releases the PDM lock. This is a NOP if locking is disabled. */
72	#ifdef VBOX_WITH_PDM_LOCK
73	# define PCI_LOCK(pDevIns, rc) \
74	do { \
75	int rc2 = PDMINS2DATA(pDevIns, PCIBus *)->CTXALLSUFF(pPciHlp)->pfnLock((pDevIns), rc); \
76	if (rc2 != VINF_SUCCESS) \
77	return rc2; \
78	} while (0)
79	# define PCI_UNLOCK(pDevIns) \
80	PDMINS2DATA(pDevIns, PCIBus *)->CTXALLSUFF(pPciHlp)->pfnUnlock(pDevIns)
81	#else /* !VBOX_WITH_PDM_LOCK */
82	# define PCI_LOCK(pThis, rc) do { } while (0)
83	# define PCI_UNLOCK(pThis) do { } while (0)
84	#endif /* !VBOX_WITH_PDM_LOCK */
85
86
87	/*******************************************************************************
88	* Structures and Typedefs *
89	*******************************************************************************/
90	/**
91	* PIIX3 ISA Bridge state.
92	*/
93	typedef struct PIIX3State
94	{
95	/** The PCI device of the bridge. */
96	PCIDEVICE dev;
97	} PIIX3State, PIIX3, *PPIIX3;
98
99
100	/** Maximum number of PCI devices.
101	* Defined like this to make interrupt handling simple. */
102	#define PCI_DEVICES_MAX 64
103	/** Number of uint32_t entries needed make a bitmask of the interrupts. */
104	#define PCI_IRQ_WORDS ((PCI_DEVICES_MAX + 31) / 32)
105
106	/**
107	* PCI Globals.
108	*
109	* @remark
110	* These are currently put in the PCIBus structure since we've
111	* only got one PCI bus in the current VM configurations. This
112	* makes life somewhat simpler in GC.
113	*/
114	typedef struct PCIGLOBALS
115	{
116	/** Irq levels for the four PCI Irqs. */
117	uint32_t pci_irq_levels[4][PCI_IRQ_WORDS];
118	/** The base address for PCI assigned MMIO addresses. */
119	RTGCPHYS pci_mem_base;
120	/** The next I/O port address which the PCI BIOS will use. */
121	uint32_t pci_bios_io_addr;
122	/** The next MMIO address which the PCI BIOS will use. */
123	uint32_t pci_bios_mem_addr;
124	/** I/O APIC usage flag */
125	bool fUseIoApic;
126	/** I/O APIC irq levels */
127	uint32_t pci_apic_irq_levels[8][PCI_IRQ_WORDS];
128	/** ACPI IRQ level */
129	uint32_t acpi_irq_level;
130	/** ACPI PIC IRQ */
131	int acpi_irq;
132	} PCIGLOBALS;
133	/** Pointer to per VM data. */
134	typedef PCIGLOBALS *PPCIGLOBALS;
135
136
137	/**
138	* PCI Bus instance.
139	*/
140	typedef struct PCIBus
141	{
142	/** IRQ index */
143	uint32_t uIrqIndex;
144	/** Bus number. */
145	int32_t iBus;
146	/** Start device number. */
147	int32_t iDevSearch;
148	/** Config register. */
149	uint32_t uConfigReg;
150	/** Array of PCI devices. */
151	HCPTRTYPE(PPCIDEVICE) devices[256];
152
153	/** HC pointer to the device instance. */
154	PPDMDEVINSHC pDevInsHC;
155	/** Pointer to the PCI R3 helpers. */
156	PCPDMPCIHLPR3 pPciHlpR3;
157
158	/** GC pointer to the device instance. */
159	PPDMDEVINSGC pDevInsGC;
160	/** Pointer to the PCI GC helpers. */
161	PCPDMPCIHLPGC pPciHlpGC;
162	/** Pointer to the PCI R0 helpers. */
163	PCPDMPCIHLPR0 pPciHlpR0;
164
165	/** The PCI device for the PCI bridge. */
166	PCIDEVICE PciDev;
167	/** ISA bridge state. */
168	PIIX3 PIIX3State;
169	/** The global data.
170	* Since we've only got one bus at present, we put it here to keep things simple. */
171	PCIGLOBALS Globals;
172	} PCIBUS;
173	/** Pointer to a PCIBUS instance. */
174	typedef PCIBUS *PPCIBUS;
175	typedef PCIBUS PCIBus;
176
177
178	/** Converts a bus instance pointer to a device instance pointer. */
179	#define PCIBUS2DEVINS(pPciBus) ((pPciBus)->CTXSUFF(pDevIns))
180	/** Converts a device instance pointer to a PCIGLOBALS pointer. */
181	#define DEVINS2PCIGLOBALS(pDevIns) ((PPCIGLOBALS)(&PDMINS2DATA(pDevIns, PPCIBUS)->Globals))
182	/** Converts a bus instance pointer to a PCIGLOBALS pointer. */
183	#define PCIBUS2PCIGLOBALS(pPciBus) ((PPCIGLOBALS)(&pPciBus->Globals))
184
185
186	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
187	/*******************************************************************************
188	* Internal Functions *
189	*******************************************************************************/
190	__BEGIN_DECLS
191
192	PDMBOTHCBDECL(void) pciSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel);
193
194	__END_DECLS
195
196
197	#define DEBUG_PCI
198
199	#define PCI_VENDOR_ID 0x00 /* 16 bits */
200	#define PCI_DEVICE_ID 0x02 /* 16 bits */
201	#define PCI_COMMAND 0x04 /* 16 bits */
202	#define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
203	#define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
204	#define PCI_CLASS_DEVICE 0x0a /* Device class */
205	#define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
206	#define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
207	#define PCI_MIN_GNT 0x3e /* 8 bits */
208	#define PCI_MAX_LAT 0x3f /* 8 bits */
209
210	#ifdef IN_RING3
211
212	static void pci_addr_writel(PCIBus *s, uint32_t addr, uint32_t val)
213	{
214	s->uConfigReg = val;
215	}
216
217	static uint32_t pci_addr_readl(PCIBus *s, uint32_t addr)
218	{
219	return s->uConfigReg;
220	}
221
222	static void pci_update_mappings(PCIDevice *d)
223	{
224	PCIIORegion *r;
225	int cmd, i;
226	uint32_t last_addr, new_addr, config_ofs;
227
228	cmd = le16_to_cpu((uint16_t )(d->config + PCI_COMMAND));
229	for(i = 0; i < PCI_NUM_REGIONS; i++) {
230	r = &d->Int.s.aIORegions[i];
231	if (i == PCI_ROM_SLOT) {
232	config_ofs = 0x30;
233	} else {
234	config_ofs = 0x10 + i * 4;
235	}
236	if (r->size != 0) {
237	if (r->type & PCI_ADDRESS_SPACE_IO) {
238	if (cmd & PCI_COMMAND_IO) {
239	new_addr = le32_to_cpu((uint32_t )(d->config +
240	config_ofs));
241	new_addr = new_addr & ~(r->size - 1);
242	last_addr = new_addr + r->size - 1;
243	/* NOTE: we have only 64K ioports on PC */
244	if (last_addr <= new_addr \|\| new_addr == 0 \|\|
245	last_addr >= 0x10000) {
246	new_addr = ~0U;
247	}
248	} else {
249	new_addr = ~0U;
250	}
251	} else {
252	if (cmd & PCI_COMMAND_MEMORY) {
253	new_addr = le32_to_cpu((uint32_t )(d->config +
254	config_ofs));
255	/* the ROM slot has a specific enable bit */
256	if (i == PCI_ROM_SLOT && !(new_addr & 1))
257	goto no_mem_map;
258	new_addr = new_addr & ~(r->size - 1);
259	last_addr = new_addr + r->size - 1;
260	/* NOTE: we do not support wrapping */
261	/* XXX: as we cannot support really dynamic
262	mappings, we handle specific values as invalid
263	mappings. */
264	if (last_addr <= new_addr \|\| new_addr == 0 \|\|
265	last_addr == ~0U) {
266	new_addr = ~0U;
267	}
268	} else {
269	no_mem_map:
270	new_addr = ~0U;
271	}
272	}
273	/* now do the real mapping */
274	if (new_addr != r->addr) {
275	if (r->addr != ~0U) {
276	if (r->type & PCI_ADDRESS_SPACE_IO) {
277	int devclass;
278	/* NOTE: specific hack for IDE in PC case:
279	only one byte must be mapped. */
280	devclass = d->config[0x0a] \| (d->config[0x0b] << 8);
281	if (devclass == 0x0101 && r->size == 4) {
282	int rc = d->pDevIns->pDevHlp->pfnIOPortDeregister(d->pDevIns, r->addr + 2, 1);
283	AssertRC(rc);
284	} else {
285	int rc = d->pDevIns->pDevHlp->pfnIOPortDeregister(d->pDevIns, r->addr, r->size);
286	AssertRC(rc);
287	}
288	} else {
289	int rc = d->pDevIns->pDevHlp->pfnMMIODeregister(d->pDevIns,
290	r->addr + PCIBUS2PCIGLOBALS(d->Int.s.pBus)->pci_mem_base,
291	r->size);
292	AssertMsg(VBOX_SUCCESS(rc) \|\| !strcmp(d->name, "vga") \|\| !strcmp(d->name, "VMMDev"), ("rc=%Vrc d=%s\n", rc, d->name)); NOREF(rc);
293	}
294	}
295	r->addr = new_addr;
296	if (r->addr != ~0U) {
297	int rc = r->map_func(d, i,
298	r->addr + (r->type & PCI_ADDRESS_SPACE_IO ? 0 : PCIBUS2PCIGLOBALS(d->Int.s.pBus)->pci_mem_base),
299	r->size, (PCIADDRESSSPACE)(r->type));
300	AssertRC(rc);
301	}
302	}
303	}
304	}
305	}
306
307	static uint32_t pci_default_read_config(PCIDevice *d,
308	uint32_t address, int len)
309	{
310	uint32_t val;
311	switch(len) {
312	case 1:
313	val = d->config[address];
314	break;
315	case 2:
316	val = le16_to_cpu((uint16_t )(d->config + address));
317	break;
318	default:
319	case 4:
320	val = le32_to_cpu((uint32_t )(d->config + address));
321	break;
322	}
323	return val;
324	}
325
326	static void pci_default_write_config(PCIDevice *d,
327	uint32_t address, uint32_t val, int len)
328	{
329	int can_write, i;
330	uint32_t end, addr;
331
332	if (len == 4 && ((address >= 0x10 && address < 0x10 + 4 * 6) \|\|
333	(address >= 0x30 && address < 0x34))) {
334	PCIIORegion *r;
335	int reg;
336
337	if ( address >= 0x30 ) {
338	reg = PCI_ROM_SLOT;
339	}else{
340	reg = (address - 0x10) >> 2;
341	}
342	r = &d->Int.s.aIORegions[reg];
343	if (r->size == 0)
344	goto default_config;
345	/* compute the stored value */
346	if (reg == PCI_ROM_SLOT) {
347	/* keep ROM enable bit */
348	val &= (~(r->size - 1)) \| 1;
349	} else {
350	val &= ~(r->size - 1);
351	val \|= r->type;
352	}
353	(uint32_t )(d->config + address) = cpu_to_le32(val);
354	pci_update_mappings(d);
355	return;
356	}
357	default_config:
358	/* not efficient, but simple */
359	addr = address;
360	for(i = 0; i < len; i++) {
361	/* default read/write accesses */
362	switch(d->config[0x0e]) {
363	case 0x00:
364	case 0x80:
365	switch(addr) {
366	case 0x00:
367	case 0x01:
368	case 0x02:
369	case 0x03:
370	case 0x08:
371	case 0x09:
372	case 0x0a:
373	case 0x0b:
374	case 0x0e:
375	case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17: /* base */
376	case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f:
377	case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27:
378	case 0x30: case 0x31: case 0x32: case 0x33: /* rom */
379	case 0x3d:
380	can_write = 0;
381	break;
382	default:
383	can_write = 1;
384	break;
385	}
386	break;
387	default:
388	case 0x01:
389	switch(addr) {
390	case 0x00:
391	case 0x01:
392	case 0x02:
393	case 0x03:
394	case 0x08:
395	case 0x09:
396	case 0x0a:
397	case 0x0b:
398	case 0x0e:
399	case 0x38: case 0x39: case 0x3a: case 0x3b: /* rom */
400	case 0x3d:
401	can_write = 0;
402	break;
403	default:
404	can_write = 1;
405	break;
406	}
407	break;
408	}
409	if (can_write) {
410	d->config[addr] = val;
411	}
412	addr++;
413	val >>= 8;
414	}
415
416	end = address + len;
417	if (end > PCI_COMMAND && address < (PCI_COMMAND + 2)) {
418	/* if the command register is modified, we must modify the mappings */
419	pci_update_mappings(d);
420	}
421	}
422
423	static void pci_data_write(PCIBus *s, uint32_t addr, uint32_t val, int len)
424	{
425	PCIDevice *pci_dev;
426	int config_addr, iBus;
427
428	Log(("pci_data_write: addr=%08x val=%08x len=%d\n", s->uConfigReg, val, len));
429
430	if (!(s->uConfigReg & (1 << 31))) {
431	return;
432	}
433	if ((s->uConfigReg & 0x3) != 0) {
434	return;
435	}
436	iBus = (s->uConfigReg >> 16) & 0xff;
437	if (iBus != 0)
438	return;
439	pci_dev = s->devices[(s->uConfigReg >> 8) & 0xff];
440	if (!pci_dev)
441	return;
442	config_addr = (s->uConfigReg & 0xfc) \| (addr & 3);
443	Log(("pci_config_write: %s: addr=%02x val=%08x len=%d\n", pci_dev->name, config_addr, val, len));
444	pci_dev->Int.s.pfnConfigWrite(pci_dev, config_addr, val, len);
445	}
446
447	static uint32_t pci_data_read(PCIBus *s, uint32_t addr, int len)
448	{
449	PCIDevice *pci_dev;
450	int config_addr, iBus;
451	uint32_t val;
452
453	if (!(s->uConfigReg & (1 << 31)))
454	goto fail;
455	if ((s->uConfigReg & 0x3) != 0)
456	goto fail;
457	iBus = (s->uConfigReg >> 16) & 0xff;
458	if (iBus != 0)
459	goto fail;
460	pci_dev = s->devices[(s->uConfigReg >> 8) & 0xff];
461	if (!pci_dev) {
462	fail:
463	switch(len) {
464	case 1:
465	val = 0xff;
466	break;
467	case 2:
468	val = 0xffff;
469	break;
470	default:
471	case 4:
472	val = 0xffffffff;
473	break;
474	}
475	goto the_end;
476	}
477	config_addr = (s->uConfigReg & 0xfc) \| (addr & 3);
478	val = pci_dev->Int.s.pfnConfigRead(pci_dev, config_addr, len);
479	Log(("pci_config_read: %s: addr=%02x val=%08x len=%d\n", pci_dev->name, config_addr, val, len));
480	the_end:
481	return val;
482	}
483
484	#endif /* IN_RING3 */
485
486
487	/* return the global irq number corresponding to a given device irq
488	pin. We could also use the bus number to have a more precise
489	mapping. */
490	static inline int pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num)
491	{
492	int slot_addend;
493	slot_addend = (pci_dev->devfn >> 3) - 1;
494	return (irq_num + slot_addend) & 3;
495	}
496
497	static inline int pci_slot_get_apic_pirq(PCIDevice *pci_dev, int irq_num)
498	{
499	return (irq_num + (pci_dev->devfn >> 3)) & 7;
500	}
501
502	static inline int get_pci_irq_apic_level(PPCIGLOBALS pGlobals, int irq_num)
503	{
504	int apic_level;
505	apic_level = ((pGlobals->pci_apic_irq_levels[irq_num][0] \|
506	pGlobals->pci_apic_irq_levels[irq_num][1]) != 0);
507	return apic_level;
508	}
509
510	static void apic_set_irq(PPCIBUS pBus, PCIDevice *pci_dev, int irq_num1, int level, int acpi_irq)
511	{
512	PPCIGLOBALS pGlobals = PCIBUS2PCIGLOBALS(pBus);
513	int shift, apic_irq, apic_level;
514	uint32_t *p;
515
516	if (acpi_irq == -1) {
517	int uIrqIndex = pci_dev->Int.s.iIrq;
518	int irq_num = pci_slot_get_apic_pirq(pci_dev, irq_num1);
519	p = &pGlobals->pci_apic_irq_levels[irq_num][uIrqIndex >> 5];
520	shift = (uIrqIndex & 0x1f);
521	p = (p & ~(1 << shift)) \| (level << shift);
522	apic_irq = irq_num + 0x10;
523	apic_level = get_pci_irq_apic_level(pGlobals, irq_num);
524	Log3(("apic_set_irq: %s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d\n",
525	HCSTRING(pci_dev->name), irq_num1, level, apic_irq, apic_level, irq_num));
526	} else {
527	apic_irq = acpi_irq;
528	apic_level = level;
529	Log3(("apic_set_irq: %s: irq_num1=%d level=%d apic_irq=%d apic_level=%d\n",
530	HCSTRING(pci_dev->name), irq_num1, level, apic_irq, apic_level));
531	}
532
533	pBus->CTXALLSUFF(pPciHlp)->pfnIoApicSetIrq(CTXSUFF(pBus->pDevIns), apic_irq, apic_level);
534	}
535
536	static inline int get_pci_irq_level(PPCIGLOBALS pGlobals, int irq_num)
537	{
538	int pic_level;
539	#if (PCI_IRQ_WORDS == 2)
540	pic_level = ((pGlobals->pci_irq_levels[irq_num][0] \|
541	pGlobals->pci_irq_levels[irq_num][1]) != 0);
542	#else
543	{
544	int i;
545	pic_level = 0;
546	for(i = 0; i < PCI_IRQ_WORDS; i++) {
547	if (pGlobals->pci_irq_levels[irq_num][i]) {
548	pic_level = 1;
549	break;
550	}
551	}
552	}
553	#endif
554	return pic_level;
555	}
556
557	/**
558	* Set the IRQ for a PCI device.
559	*
560	* @param pDevIns Device instance of the PCI Bus.
561	* @param pPciDev The PCI device structure.
562	* @param iIrq IRQ number to set.
563	* @param iLevel IRQ level.
564	*/
565	PDMBOTHCBDECL(void) pciSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel)
566	{
567	PPCIBUS pBus = PDMINS2DATA(pDevIns, PPCIBUS);
568	PPCIGLOBALS pGlobals = PCIBUS2PCIGLOBALS(pBus);
569	uint8_t *pbCfg = pBus->PIIX3State.dev.config;
570	const bool fIsAcpiDevice = pPciDev->config[2] == 0x13 && pPciDev->config[3] == 0x71;
571	const bool fIsApicEnabled = pGlobals->fUseIoApic && pbCfg[0xde] == 0xbe && pbCfg[0xad] == 0xef;
572	int pic_irq, pic_level;
573	uint32_t *p;
574
575	/* apic only */
576	if (fIsApicEnabled)
577	{
578	if (fIsAcpiDevice)
579	/*
580	* ACPI needs special treatment since SCI is hardwired and
581	* should not be affected by PCI IRQ routing tables at the
582	* same time SCI IRQ is shared in PCI sense hence this
583	* kludge (i.e. we fetch the hardwired value from ACPIs
584	* PCI device configuration space).
585	*/
586	apic_set_irq(pBus, pPciDev, -1, iLevel, pPciDev->config[0x3c]);
587	else
588	apic_set_irq(pBus, pPciDev, iIrq, iLevel, -1);
589	return;
590	}
591
592	if (fIsAcpiDevice)
593	{
594	/* As per above treat ACPI in a special way */
595	pic_irq = pPciDev->config[0x3c];
596	pGlobals->acpi_irq = pic_irq;
597	pGlobals->acpi_irq_level = iLevel;
598	}
599	else
600	{
601	int shift, irq_num, uIrqIndex;
602	irq_num = pci_slot_get_pirq(pPciDev, iIrq);
603	uIrqIndex = pPciDev->Int.s.iIrq;
604	p = &pGlobals->pci_irq_levels[irq_num][uIrqIndex >> 5];
605	shift = (uIrqIndex & 0x1f);
606	p = (p & ~(1 << shift)) \| (iLevel << shift);
607
608	/* now we change the pic irq level according to the piix irq mappings */
609	pic_irq = pbCfg[0x60 + irq_num];
610	if (pic_irq >= 16)
611	return;
612	}
613
614	/* the pic level is the logical OR of all the PCI irqs mapped to it */
615	pic_level = 0;
616	if (pic_irq == pbCfg[0x60])
617	pic_level \|= get_pci_irq_level(pGlobals, 0);
618	if (pic_irq == pbCfg[0x61])
619	pic_level \|= get_pci_irq_level(pGlobals, 1);
620	if (pic_irq == pbCfg[0x62])
621	pic_level \|= get_pci_irq_level(pGlobals, 2);
622	if (pic_irq == pbCfg[0x63])
623	pic_level \|= get_pci_irq_level(pGlobals, 3);
624	if (pic_irq == pGlobals->acpi_irq)
625	pic_level \|= pGlobals->acpi_irq_level;
626
627	Log3(("piix3_set_irq: %s: iLevel=%d iIrq=%d pic_irq=%d pic_level=%d\n",
628	HCSTRING(pPciDev->name), iLevel, iIrq, pic_irq, pic_level));
629	pBus->CTXALLSUFF(pPciHlp)->pfnIsaSetIrq(CTXSUFF(pBus->pDevIns), pic_irq, pic_level);
630	}
631
632	#ifdef IN_RING3
633
634	static void piix3_reset(PIIX3State *d)
635	{
636	uint8_t *pci_conf = d->dev.config;
637
638	pci_conf[0x04] = 0x07; /* master, memory and I/O */
639	pci_conf[0x05] = 0x00;
640	pci_conf[0x06] = 0x00;
641	pci_conf[0x07] = 0x02; /* PCI_status_devsel_medium */
642	pci_conf[0x4c] = 0x4d;
643	pci_conf[0x4e] = 0x03;
644	pci_conf[0x4f] = 0x00;
645	pci_conf[0x60] = 0x80;
646	pci_conf[0x69] = 0x02;
647	pci_conf[0x70] = 0x80;
648	pci_conf[0x76] = 0x0c;
649	pci_conf[0x77] = 0x0c;
650	pci_conf[0x78] = 0x02;
651	pci_conf[0x79] = 0x00;
652	pci_conf[0x80] = 0x00;
653	pci_conf[0x82] = 0x02; /* Get rid of the Linux guest "Enabling Passive Release" PCI quirk warning. */
654	pci_conf[0xa0] = 0x08;
655	pci_conf[0xa0] = 0x08;
656	pci_conf[0xa2] = 0x00;
657	pci_conf[0xa3] = 0x00;
658	pci_conf[0xa4] = 0x00;
659	pci_conf[0xa5] = 0x00;
660	pci_conf[0xa6] = 0x00;
661	pci_conf[0xa7] = 0x00;
662	pci_conf[0xa8] = 0x0f;
663	pci_conf[0xaa] = 0x00;
664	pci_conf[0xab] = 0x00;
665	pci_conf[0xac] = 0x00;
666	pci_conf[0xae] = 0x00;
667	}
668
669	static void pci_config_writel(PCIDevice *d, uint32_t addr, uint32_t val)
670	{
671	PCIBus *s = d->Int.s.pBus;
672	s->uConfigReg = 0x80000000 \| (s->iBus << 16) \|
673	(d->devfn << 8) \| addr;
674	pci_data_write(s, 0, val, 4);
675	}
676
677	static void pci_config_writew(PCIDevice *d, uint32_t addr, uint32_t val)
678	{
679	PCIBus *s = d->Int.s.pBus;
680	s->uConfigReg = 0x80000000 \| (s->iBus << 16) \|
681	(d->devfn << 8) \| (addr & ~3);
682	pci_data_write(s, addr & 3, val, 2);
683	}
684
685	static void pci_config_writeb(PCIDevice *d, uint32_t addr, uint32_t val)
686	{
687	PCIBus *s = d->Int.s.pBus;
688	s->uConfigReg = 0x80000000 \| (s->iBus << 16) \|
689	(d->devfn << 8) \| (addr & ~3);
690	pci_data_write(s, addr & 3, val, 1);
691	}
692
693	static uint32_t pci_config_readw(PCIDevice *d, uint32_t addr)
694	{
695	PCIBus *s = d->Int.s.pBus;
696	s->uConfigReg = 0x80000000 \| (s->iBus << 16) \|
697	(d->devfn << 8) \| (addr & ~3);
698	return pci_data_read(s, addr & 3, 2);
699	}
700
701	static uint32_t pci_config_readb(PCIDevice *d, uint32_t addr)
702	{
703	PCIBus *s = d->Int.s.pBus;
704	s->uConfigReg = 0x80000000 \| (s->iBus << 16) \|
705	(d->devfn << 8) \| (addr & ~3);
706	return pci_data_read(s, addr & 3, 1);
707	}
708
709	/* host irqs corresponding to PCI irqs A-D */
710	static const uint8_t pci_irqs[4] = { 11, 9, 11, 9 }; /* bird: added const */
711
712	static void pci_set_io_region_addr(PCIDevice *d, int region_num, uint32_t addr)
713	{
714	PCIIORegion *r;
715	uint16_t cmd;
716	uint32_t ofs;
717
718	if ( region_num == PCI_ROM_SLOT ) {
719	ofs = 0x30;
720	}else{
721	ofs = 0x10 + region_num * 4;
722	}
723
724	pci_config_writel(d, ofs, addr);
725	r = &d->Int.s.aIORegions[region_num];
726
727	/* enable memory mappings */
728	cmd = pci_config_readw(d, PCI_COMMAND);
729	if ( region_num == PCI_ROM_SLOT )
730	cmd \|= 2;
731	else if (r->type & PCI_ADDRESS_SPACE_IO)
732	cmd \|= 1;
733	else
734	cmd \|= 2;
735	pci_config_writew(d, PCI_COMMAND, cmd);
736	}
737
738	static void pci_bios_init_device(PCIDevice *d)
739	{
740	int devclass;
741	PCIIORegion *r;
742	uint32_t *paddr;
743	int i, pin, pic_irq, vendor_id, device_id;
744
745	devclass = pci_config_readw(d, PCI_CLASS_DEVICE);
746	vendor_id = pci_config_readw(d, PCI_VENDOR_ID);
747	device_id = pci_config_readw(d, PCI_DEVICE_ID);
748	switch(devclass)
749	{
750	case 0x0101:
751	if (vendor_id == 0x8086 && device_id == 0x7010) {
752	/* PIIX3 IDE */
753	pci_config_writew(d, 0x40, 0x8000); /* enable IDE0 */
754	pci_config_writew(d, 0x42, 0x8000); /* enable IDE1 */
755	goto default_map;
756	} else {
757	/* IDE: we map it as in ISA mode */
758	pci_set_io_region_addr(d, 0, 0x1f0);
759	pci_set_io_region_addr(d, 1, 0x3f4);
760	pci_set_io_region_addr(d, 2, 0x170);
761	pci_set_io_region_addr(d, 3, 0x374);
762	}
763	break;
764	case 0x0300:
765	if (vendor_id != 0x80ee)
766	goto default_map;
767	/* VGA: map frame buffer to default Bochs VBE address */
768	pci_set_io_region_addr(d, 0, 0xE0000000);
769	break;
770	case 0x0800:
771	/* PIC */
772	vendor_id = pci_config_readw(d, PCI_VENDOR_ID);
773	device_id = pci_config_readw(d, PCI_DEVICE_ID);
774	if (vendor_id == 0x1014) {
775	/* IBM */
776	if (device_id == 0x0046 \|\| device_id == 0xFFFF) {
777	/* MPIC & MPIC2 */
778	pci_set_io_region_addr(d, 0, 0x80800000 + 0x00040000);
779	}
780	}
781	break;
782	case 0xff00:
783	if (vendor_id == 0x0106b &&
784	(device_id == 0x0017 \|\| device_id == 0x0022)) {
785	/* macio bridge */
786	pci_set_io_region_addr(d, 0, 0x80800000);
787	}
788	break;
789	default:
790	default_map:
791	/* default memory mappings */
792	for(i = 0; i < PCI_NUM_REGIONS; i++) {
793	r = &d->Int.s.aIORegions[i];
794
795	if (r->size) {
796	if (r->type & PCI_ADDRESS_SPACE_IO)
797	paddr = &PCIBUS2PCIGLOBALS(d->Int.s.pBus)->pci_bios_io_addr;
798	else
799	paddr = &PCIBUS2PCIGLOBALS(d->Int.s.pBus)->pci_bios_mem_addr;
800	paddr = (paddr + r->size - 1) & ~(r->size - 1);
801	pci_set_io_region_addr(d, i, *paddr);
802	*paddr += r->size;
803	}
804	}
805	break;
806	}
807
808	/* map the interrupt */
809	pin = pci_config_readb(d, PCI_INTERRUPT_PIN);
810	if (pin != 0) {
811	pin = pci_slot_get_pirq(d, pin - 1);
812	pic_irq = pci_irqs[pin];
813	pci_config_writeb(d, PCI_INTERRUPT_LINE, pic_irq);
814	}
815	}
816
817	/* -=-=-=-=-=- wrappers -=-=-=-=-=- */
818
819	/**
820	* Port I/O Handler for PCI address OUT operations.
821	*
822	* @returns VBox status code.
823	*
824	* @param pDevIns The device instance.
825	* @param pvUser User argument - ignored.
826	* @param uPort Port number used for the IN operation.
827	* @param u32 The value to output.
828	* @param cb The value size in bytes.
829	*/
830	static DECLCALLBACK(int) pciIOPortAddressWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
831	{
832	Log(("pciIOPortAddressWrite: Port=%#x u32=%#x cb=%d\n", Port, u32, cb));
833	NOREF(pvUser);
834	if (cb == 4)
835	{
836	PCI_LOCK(pDevIns, VINF_IOM_HC_IOPORT_WRITE);
837	pci_addr_writel(PDMINS2DATA(pDevIns, PCIBus *), Port, u32);
838	PCI_UNLOCK(pDevIns);
839	}
840	/* else: 440FX does "pass through to the bus" for other writes, what ever that means.
841	* Linux probes for cmd640 using byte writes/reads during ide init. We'll just ignore it. */
842	return VINF_SUCCESS;
843	}
844
845	/**
846	* Port I/O Handler for PCI address IN operations.
847	*
848	* @returns VBox status code.
849	*
850	* @param pDevIns The device instance.
851	* @param pvUser User argument - ignored.
852	* @param uPort Port number used for the IN operation.
853	* @param pu32 Where to store the result.
854	* @param cb Number of bytes read.
855	*/
856	static DECLCALLBACK(int) pciIOPortAddressRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
857	{
858	NOREF(pvUser);
859	if (cb == 4)
860	{
861	PCI_LOCK(pDevIns, VINF_IOM_HC_IOPORT_READ);
862	pu32 = pci_addr_readl(PDMINS2DATA(pDevIns, PCIBus ), Port);
863	PCI_UNLOCK(pDevIns);
864	Log(("pciIOPortAddressRead: Port=%#x cb=%d -> %#x\n", Port, cb, *pu32));
865	return VINF_SUCCESS;
866	}
867	/* else: 440FX does "pass through to the bus" for other writes, what ever that means.
868	* Linux probes for cmd640 using byte writes/reads during ide init. We'll just ignore it. */
869	Log(("pciIOPortAddressRead: Port=%#x cb=%d VERR_IOM_IOPORT_UNUSED\n", Port, cb));
870	return VERR_IOM_IOPORT_UNUSED;
871	}
872
873
874	/**
875	* Port I/O Handler for PCI data OUT operations.
876	*
877	* @returns VBox status code.
878	*
879	* @param pDevIns The device instance.
880	* @param pvUser User argument - ignored.
881	* @param uPort Port number used for the IN operation.
882	* @param u32 The value to output.
883	* @param cb The value size in bytes.
884	*/
885	static DECLCALLBACK(int) pciIOPortDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
886	{
887	Log(("pciIOPortDataWrite: Port=%#x u32=%#x cb=%d\n", Port, u32, cb));
888	NOREF(pvUser);
889	if (!(Port % cb))
890	{
891	PCI_LOCK(pDevIns, VINF_IOM_HC_IOPORT_WRITE);
892	pci_data_write(PDMINS2DATA(pDevIns, PCIBus *), Port, u32, cb);
893	PCI_UNLOCK(pDevIns);
894	}
895	else
896	AssertMsgFailed(("Write to port %#x u32=%#x cb=%d\n", Port, u32, cb));
897	return VINF_SUCCESS;
898	}
899
900
901	/**
902	* Port I/O Handler for PCI data IN operations.
903	*
904	* @returns VBox status code.
905	*
906	* @param pDevIns The device instance.
907	* @param pvUser User argument - ignored.
908	* @param uPort Port number used for the IN operation.
909	* @param pu32 Where to store the result.
910	* @param cb Number of bytes read.
911	*/
912	static DECLCALLBACK(int) pciIOPortDataRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
913	{
914	NOREF(pvUser);
915	if (!(Port % cb))
916	{
917	PCI_LOCK(pDevIns, VINF_IOM_HC_IOPORT_READ);
918	pu32 = pci_data_read(PDMINS2DATA(pDevIns, PCIBus ), Port, cb);
919	PCI_UNLOCK(pDevIns);
920	Log(("pciIOPortDataRead: Port=%#x cb=%#x -> %#x\n", Port, cb, *pu32));
921	return VINF_SUCCESS;
922	}
923	AssertMsgFailed(("Read from port %#x cb=%d\n", Port, cb));
924	return VERR_IOM_IOPORT_UNUSED;
925	}
926
927
928	/**
929	* Saves a state of the PCI device.
930	*
931	* @returns VBox status code.
932	* @param pDevIns Device instance of the PCI Bus.
933	* @param pPciDev Pointer to PCI device.
934	* @param pSSMHandle The handle to save the state to.
935	*/
936	static DECLCALLBACK(int) pciGenericSaveExec(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PSSMHANDLE pSSMHandle)
937	{
938	return SSMR3PutMem(pSSMHandle, &pPciDev->config[0], sizeof(pPciDev->config));
939	}
940
941
942	/**
943	* Loads a saved PCI device state.
944	*
945	* @returns VBox status code.
946	* @param pDevIns Device instance of the PCI Bus.
947	* @param pPciDev Pointer to PCI device.
948	* @param pSSMHandle The handle to the saved state.
949	*/
950	static DECLCALLBACK(int) pciGenericLoadExec(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PSSMHANDLE pSSMHandle)
951	{
952	return SSMR3GetMem(pSSMHandle, &pPciDev->config[0], sizeof(pPciDev->config));
953	}
954
955
956	/**
957	* Saves a state of the PCI device.
958	*
959	* @returns VBox status code.
960	* @param pDevIns The device instance.
961	* @param pPciDev Pointer to PCI device.
962	* @param pSSMHandle The handle to save the state to.
963	*/
964	static DECLCALLBACK(int) pciSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle)
965	{
966	uint32_t i;
967	PPCIBUS pData = PDMINS2DATA(pDevIns, PPCIBUS);
968	PPCIGLOBALS pGlobals = PCIBUS2PCIGLOBALS(pData);
969
970	/*
971	* Bus state data.
972	*/
973	SSMR3PutU32(pSSMHandle, pData->uConfigReg);
974	SSMR3PutBool(pSSMHandle, pGlobals->fUseIoApic);
975	SSMR3PutU32(pSSMHandle, ~0); /* separator */
976
977	/*
978	* Iterate all the devices.
979	*/
980	for (i = 0; i < ELEMENTS(pData->devices); i++)
981	{
982	PPCIDEVICE pDev = pData->devices[i];
983	if (pDev)
984	{
985	int rc;
986	SSMR3PutU32(pSSMHandle, i);
987	SSMR3PutMem(pSSMHandle, pDev->config, sizeof(pDev->config));
988	rc = SSMR3PutS32(pSSMHandle, pDev->Int.s.iIrq);
989	if (VBOX_FAILURE(rc))
990	return rc;
991	}
992	}
993	return SSMR3PutU32(pSSMHandle, ~0); /* terminator */
994	}
995
996	/**
997	* Loads a saved PCI device state.
998	*
999	* @returns VBox status code.
1000	* @param pDevIns The device instance.
1001	* @param pSSMHandle The handle to the saved state.
1002	* @param u32Version The data unit version number.
1003	*/
1004	static DECLCALLBACK(int) pciLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle, uint32_t u32Version)
1005	{
1006	PPCIBUS pData = PDMINS2DATA(pDevIns, PPCIBUS);
1007	PPCIGLOBALS pGlobals = PCIBUS2PCIGLOBALS(pData);
1008	uint32_t u32;
1009	uint32_t i;
1010	int rc;
1011
1012	/*
1013	* Check the version.
1014	*/
1015	if (u32Version > 2)
1016	{
1017	AssertFailed();
1018	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1019	}
1020
1021	/*
1022	* Bus state data.
1023	*/
1024	SSMR3GetU32(pSSMHandle, &pData->uConfigReg);
1025	if (u32Version > 1)
1026	SSMR3GetBool(pSSMHandle, &pGlobals->fUseIoApic);
1027
1028	/* separator */
1029	rc = SSMR3GetU32(pSSMHandle, &u32);
1030	if (VBOX_FAILURE(rc))
1031	return rc;
1032	if (u32 != (uint32_t)~0)
1033	{
1034	AssertMsgFailed(("u32=%#x\n", u32));
1035	return rc;
1036	}
1037
1038	/*
1039	* Iterate all the devices.
1040	*/
1041	for (i = 0;; i++)
1042	{
1043	PCIDEVICE DevTmp;
1044	PPCIDEVICE pDev;
1045
1046	/* index / terminator */
1047	rc = SSMR3GetU32(pSSMHandle, &u32);
1048	if (VBOX_FAILURE(rc))
1049	return rc;
1050	if (u32 == (uint32_t)~0)
1051	break;
1052	if ( u32 >= ELEMENTS(pData->devices)
1053	\|\| u32 < i)
1054	{
1055	AssertMsgFailed(("u32=%#x i=%#x\n", u32, i));
1056	return rc;
1057	}
1058
1059	/* skip forward to the device checking that no new devices are present. */
1060	for (; i < u32; i++)
1061	{
1062	if (pData->devices[i])
1063	{
1064	LogRel(("New device in slot %#x, %s\n", i, pData->devices[i]->name));
1065	AssertFailed();
1066	return VERR_SSM_LOAD_CONFIG_MISMATCH;
1067	}
1068	}
1069
1070	/* check that it's still around. */
1071	pDev = pData->devices[i];
1072	if (!pDev)
1073	{
1074	LogRel(("Device in slot %#x has been removed!\n", i, pDev->name));
1075	AssertFailed();
1076	return VERR_SSM_LOAD_CONFIG_MISMATCH;
1077	}
1078
1079	/* restore it */
1080	SSMR3GetMem(pSSMHandle, DevTmp.config, sizeof(DevTmp.config));
1081	rc = SSMR3GetS32(pSSMHandle, &DevTmp.Int.s.iIrq);
1082	if (VBOX_FAILURE(rc))
1083	return rc;
1084
1085	/* match the vendor id assuming that this will never be changed. */
1086	if ( DevTmp.config[0] != pDev->config[0]
1087	\|\| DevTmp.config[1] != pDev->config[1])
1088	{
1089	LogRel(("Device in slot %#x (%s) vendor id mismatch! saved=%.4Vhxs current=%.4Vhxs\n",
1090	i, pDev->name, DevTmp.config, pDev->config));
1091	AssertFailed();
1092	return VERR_SSM_LOAD_CONFIG_MISMATCH;
1093	}
1094
1095	/* commit the loaded device config. */
1096	memcpy(pDev->config, DevTmp.config, sizeof(pDev->config));
1097	if (DevTmp.Int.s.iIrq >= PCI_DEVICES_MAX) {
1098	AssertMsgFailed (("Device %s: Too many devices %d (max=%d)\n",
1099	pDev->name, DevTmp.Int.s.iIrq, PCI_DEVICES_MAX));
1100	return VERR_TOO_MUCH_DATA;
1101	}
1102
1103	pDev->Int.s.iIrq = DevTmp.Int.s.iIrq;
1104	}
1105	return VINF_SUCCESS;
1106	}
1107
1108
1109	/* -=-=-=-=-=- real code -=-=-=-=-=- */
1110
1111
1112	/**
1113	* Registers the device with the default PCI bus.
1114	*
1115	* @returns VBox status code.
1116	* @param pBus The bus to register with.
1117	* @param iDev The PCI device ordinal.
1118	* @param pPciDev The PCI device structure.
1119	* @param pszName Pointer to device name (permanent, readonly). For debugging, not unique.
1120	*/
1121	static void pciRegisterInternal(PPCIBUS pBus, int iDev, PPCIDEVICE pPciDev, const char *pszName)
1122	{
1123	Assert(!pBus->devices[iDev]);
1124	pPciDev->devfn = iDev;
1125	pPciDev->name = pszName;
1126	pPciDev->Int.s.pBus = pBus;
1127	pPciDev->Int.s.pfnConfigRead = pci_default_read_config;
1128	pPciDev->Int.s.pfnConfigWrite = pci_default_write_config;
1129	AssertMsg(pBus->uIrqIndex < PCI_DEVICES_MAX,
1130	("Device %s: Too many devices %d (max=%d)\n",
1131	pszName, pBus->uIrqIndex, PCI_DEVICES_MAX));
1132	pPciDev->Int.s.iIrq = pBus->uIrqIndex++;
1133	pBus->devices[iDev] = pPciDev;
1134	Log(("PCI: Registered device %d function %d (%#x) '%s'.\n",
1135	iDev >> 3, iDev & 7, 0x80000000 \| (iDev << 8), pszName));
1136	}
1137
1138
1139	/**
1140	* Registers the device with the default PCI bus.
1141	*
1142	* @returns VBox status code.
1143	* @param pDevIns Device instance of the PCI Bus.
1144	* @param pPciDev The PCI device structure.
1145	* Any PCI enabled device must keep this in it's instance data!
1146	* Fill in the PCI data config before registration, please.
1147	* @param pszName Pointer to device name (permanent, readonly). For debugging, not unique.
1148	* @param iDev The PCI device number. Use a negative value for auto assigning one.
1149	*/
1150	static DECLCALLBACK(int) pciRegister(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, const char *pszName, int iDev)
1151	{
1152	PPCIBUS pBus = PDMINS2DATA(pDevIns, PPCIBUS);
1153
1154	/*
1155	* Check input.
1156	*/
1157	if ( !pszName
1158	\|\| !pPciDev
1159	\|\| iDev >= (int)ELEMENTS(pBus->devices)
1160	\|\| (iDev >= 0 && iDev <= 8))
1161	{
1162	AssertMsgFailed(("Invalid argument! pszName=%s pPciDev=%p iDev=%d\n", pszName, pPciDev, iDev));
1163	return VERR_INVALID_PARAMETER;
1164	}
1165
1166	/*
1167	* Find device slot.
1168	*/
1169	if (iDev < 0)
1170	{
1171	/*
1172	* Special check for the IDE controller which is our function 1 device
1173	* before searching.
1174	*/
1175	if ( !strcmp(pszName, "piix3ide")
1176	&& !pBus->devices[9])
1177	iDev = 9;
1178	else
1179	{
1180	Assert(!(pBus->iDevSearch % 8));
1181	for (iDev = pBus->iDevSearch; iDev < (int)ELEMENTS(pBus->devices); iDev += 8)
1182	if ( !pBus->devices[iDev]
1183	&& !pBus->devices[iDev + 1]
1184	&& !pBus->devices[iDev + 2]
1185	&& !pBus->devices[iDev + 3]
1186	&& !pBus->devices[iDev + 4]
1187	&& !pBus->devices[iDev + 5]
1188	&& !pBus->devices[iDev + 6]
1189	&& !pBus->devices[iDev + 7])
1190	break;
1191	if (iDev >= (int)ELEMENTS(pBus->devices))
1192	{
1193	AssertMsgFailed(("Couldn't find free spot!\n"));
1194	return VERR_PDM_TOO_PCI_MANY_DEVICES;
1195	}
1196	}
1197	pPciDev->Int.s.fRequestedDevFn = false;
1198	}
1199	else
1200	{
1201	/*
1202	* An explicit request.
1203	*
1204	* If the slot is occupied we'll have to relocate the device
1205	* currently occupying it first. This can only be done if the
1206	* existing device wasn't explicitly assigned. Also we limit
1207	* ourselves to function 0 devices.
1208	*
1209	* If you start setting devices + function in the
1210	* config, do it for all pci devices!
1211	*/
1212	AssertReleaseMsg(iDev > 8, ("iDev=%d pszName=%s\n", iDev, pszName));
1213	if (pBus->devices[iDev])
1214	{
1215	int iDevRel;
1216	AssertReleaseMsg(!(iDev % 8), ("PCI Configuration Conflict! iDev=%d pszName=%s clashes with %s\n",
1217	iDev, pszName, pBus->devices[iDev]->name));
1218	if ( pBus->devices[iDev]->Int.s.fRequestedDevFn
1219	\|\| (pBus->devices[iDev + 1] && pBus->devices[iDev + 1]->Int.s.fRequestedDevFn)
1220	\|\| (pBus->devices[iDev + 2] && pBus->devices[iDev + 2]->Int.s.fRequestedDevFn)
1221	\|\| (pBus->devices[iDev + 3] && pBus->devices[iDev + 3]->Int.s.fRequestedDevFn)
1222	\|\| (pBus->devices[iDev + 4] && pBus->devices[iDev + 4]->Int.s.fRequestedDevFn)
1223	\|\| (pBus->devices[iDev + 5] && pBus->devices[iDev + 5]->Int.s.fRequestedDevFn)
1224	\|\| (pBus->devices[iDev + 6] && pBus->devices[iDev + 6]->Int.s.fRequestedDevFn)
1225	\|\| (pBus->devices[iDev + 7] && pBus->devices[iDev + 7]->Int.s.fRequestedDevFn))
1226	{
1227	AssertReleaseMsgFailed(("Configuration error:'%s' and '%s' are both configured as device %d\n",
1228	pszName, pBus->devices[iDev]->name, iDev));
1229	return VERR_INTERNAL_ERROR;
1230	}
1231
1232	/* Find free slot for the device(s) we're moving and move them. */
1233	for (iDevRel = pBus->iDevSearch; iDevRel < (int)ELEMENTS(pBus->devices); iDevRel += 8)
1234	{
1235	if ( !pBus->devices[iDevRel]
1236	&& !pBus->devices[iDevRel + 1]
1237	&& !pBus->devices[iDevRel + 2]
1238	&& !pBus->devices[iDevRel + 3]
1239	&& !pBus->devices[iDevRel + 4]
1240	&& !pBus->devices[iDevRel + 5]
1241	&& !pBus->devices[iDevRel + 6]
1242	&& !pBus->devices[iDevRel + 7])
1243	{
1244	int i = 0;
1245	for (i = 0; i < 8; i++)
1246	{
1247	if (!pBus->devices[iDev + i])
1248	continue;
1249	Log(("PCI: relocating '%s' from slot %#x to %#x\n", pBus->devices[iDev + i]->name, iDev + i, iDevRel + i));
1250	pBus->devices[iDevRel + i] = pBus->devices[iDev + i];
1251	pBus->devices[iDevRel + i]->devfn = i;
1252	pBus->devices[iDev + i] = NULL;
1253	}
1254	}
1255	}
1256	if (pBus->devices[iDev])
1257	{
1258	AssertMsgFailed(("Couldn't find free spot!\n"));
1259	return VERR_PDM_TOO_PCI_MANY_DEVICES;
1260	}
1261	} /* if conflict */
1262	pPciDev->Int.s.fRequestedDevFn = true;
1263	}
1264
1265	/*
1266	* Register the device.
1267	*/
1268	pciRegisterInternal(pBus, iDev, pPciDev, pszName);
1269	return VINF_SUCCESS;
1270	}
1271
1272
1273	static DECLCALLBACK(int) pciIORegionRegister(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iRegion, uint32_t cbRegion, PCIADDRESSSPACE enmType, PFNPCIIOREGIONMAP pfnCallback)
1274	{
1275	PPCIIOREGION pRegion;
1276
1277	/*
1278	* Validate.
1279	*/
1280	if ( enmType != PCI_ADDRESS_SPACE_MEM
1281	&& enmType != PCI_ADDRESS_SPACE_IO
1282	&& enmType != PCI_ADDRESS_SPACE_MEM_PREFETCH)
1283	{
1284	AssertMsgFailed(("Invalid enmType=%#x? Or was this a bitmask after all...\n", enmType));
1285	return VERR_INVALID_PARAMETER;
1286	}
1287	if ((unsigned)iRegion >= PCI_NUM_REGIONS)
1288	{
1289	AssertMsgFailed(("Invalid iRegion=%d PCI_NUM_REGIONS=%d\n", iRegion, PCI_NUM_REGIONS));
1290	return VERR_INVALID_PARAMETER;
1291	}
1292
1293	/*
1294	* Register the I/O region.
1295	*/
1296	pRegion = &pPciDev->Int.s.aIORegions[iRegion];
1297	pRegion->addr = ~0U;
1298	pRegion->size = cbRegion;
1299	pRegion->type = enmType;
1300	pRegion->map_func = pfnCallback;
1301	return VINF_SUCCESS;
1302	}
1303
1304
1305	/**
1306	* Called to perform the job of the bios.
1307	*
1308	* @returns VBox status.
1309	* @param pDevIns Device instance of the first bus.
1310	*/
1311	static DECLCALLBACK(int) pciFakePCIBIOS(PPDMDEVINS pDevIns)
1312	{
1313	int rc;
1314	unsigned i;
1315	uint8_t elcr[2] = {0, 0};
1316	PPCIGLOBALS pGlobals = DEVINS2PCIGLOBALS(pDevIns);
1317	PPCIBUS pBus = PDMINS2DATA(pDevIns, PPCIBUS);
1318	PVM pVM = PDMDevHlpGetVM(pDevIns);
1319	Assert(pVM);
1320
1321	/*
1322	* Set the start addresses.
1323	*/
1324	pGlobals->pci_bios_io_addr = 0xc000;
1325	pGlobals->pci_bios_mem_addr = 0xf0000000;
1326
1327	/*
1328	* Activate IRQ mappings.
1329	*/
1330	for (i = 0; i < 4; i++)
1331	{
1332	uint8_t irq = pci_irqs[i];
1333	/* Set to trigger level. */
1334	elcr[irq >> 3] \|= (1 << (irq & 7));
1335	/* Activate irq remapping in PIIX3. */
1336	pci_config_writeb(&pBus->PIIX3State.dev, 0x60 + i, irq);
1337	}
1338
1339	/* Tell to the PIC. */
1340	rc = IOMIOPortWrite(pVM, 0x4d0, elcr[0], sizeof(uint8_t));
1341	if (rc == VINF_SUCCESS)
1342	rc = IOMIOPortWrite(pVM, 0x4d1, elcr[1], sizeof(uint8_t));
1343	if (rc != VINF_SUCCESS)
1344	{
1345	AssertMsgFailed(("Writing to PIC failed!\n"));
1346	return VBOX_SUCCESS(rc) ? VERR_INTERNAL_ERROR : rc;
1347	}
1348
1349	/*
1350	* Init the devices.
1351	*/
1352	for (i = 0; i < ELEMENTS(pBus->devices); i++)
1353	{
1354	if (pBus->devices[i])
1355	{
1356	Log2(("PCI: Initializing device %d (%#x) '%s'\n",
1357	i, 0x80000000 \| (i << 8), pBus->devices[i]->name));
1358	pci_bios_init_device(pBus->devices[i]);
1359	}
1360	}
1361	return VINF_SUCCESS;
1362	}
1363
1364
1365	/**
1366	* @copydoc FNPDMDEVRELOCATE
1367	*/
1368	static DECLCALLBACK(void) pciRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
1369	{
1370	PPCIBUS pBus = PDMINS2DATA(pDevIns, PPCIBUS);
1371	pBus->pDevInsGC = PDMDEVINS_2_GCPTR(pDevIns);
1372	pBus->pPciHlpGC = pBus->pPciHlpR3->pfnGetGCHelpers(pDevIns);
1373	}
1374
1375
1376	/**
1377	* Construct a PCI Bus device instance for a VM.
1378	*
1379	* @returns VBox status.
1380	* @param pDevIns The device instance data.
1381	* If the registration structure is needed, pDevIns->pDevReg points to it.
1382	* @param iInstance Instance number. Use this to figure out which registers and such to use.
1383	* The device number is also found in pDevIns->iInstance, but since it's
1384	* likely to be freqently used PDM passes it as parameter.
1385	* @param pCfgHandle Configuration node handle for the device. Use this to obtain the configuration
1386	* of the device instance. It's also found in pDevIns->pCfgHandle, but like
1387	* iInstance it's expected to be used a bit in this function.
1388	*/
1389	static DECLCALLBACK(int) pciConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfgHandle)
1390	{
1391	PPCIGLOBALS pGlobals = DEVINS2PCIGLOBALS(pDevIns);
1392	PPCIBUS pBus = PDMINS2DATA(pDevIns, PPCIBUS);
1393	PDMPCIBUSREG PciBusReg;
1394	int rc;
1395	bool fGCEnabled;
1396	bool fR0Enabled;
1397	bool fUseIoApic;
1398	Assert(iInstance == 0);
1399
1400	/*
1401	* Validate and read configuration.
1402	*/
1403	if (!CFGMR3AreValuesValid(pCfgHandle, "IOAPIC\0" "GCEnabled\0R0Enabled\0"))
1404	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
1405
1406	/* query whether we got an IOAPIC */
1407	rc = CFGMR3QueryBool(pCfgHandle, "IOAPIC", &fUseIoApic);
1408	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
1409	fUseIoApic = false;
1410	else if (VBOX_FAILURE(rc))
1411	return PDMDEV_SET_ERROR(pDevIns, rc,
1412	N_("Configuration error: Failed to query boolean value \"IOAPIC\"."));
1413
1414	/* check if GC code is enabled. */
1415	rc = CFGMR3QueryBool(pCfgHandle, "GCEnabled", &fGCEnabled);
1416	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
1417	fGCEnabled = true;
1418	else if (VBOX_FAILURE(rc))
1419	return PDMDEV_SET_ERROR(pDevIns, rc,
1420	N_("Configuration error: Failed to query boolean value \"GCEnabled\"."));
1421	Log(("PCI: fGCEnabled=%d\n", fGCEnabled));
1422
1423	/* check if R0 code is enabled. */
1424	rc = CFGMR3QueryBool(pCfgHandle, "R0Enabled", &fR0Enabled);
1425	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
1426	fR0Enabled = true;
1427	else if (VBOX_FAILURE(rc))
1428	return PDMDEV_SET_ERROR(pDevIns, rc,
1429	N_("Configuration error: Failed to query boolean value \"R0Enabled\"."));
1430	Log(("PCI: fR0Enabled=%d\n", fR0Enabled));
1431
1432	/*
1433	* Init data and register the PCI bus.
1434	*/
1435	pGlobals->pci_mem_base = 0;
1436	pGlobals->pci_bios_io_addr = 0xc000;
1437	pGlobals->pci_bios_mem_addr = 0xf0000000;
1438	memset(&pGlobals->pci_irq_levels, 0, sizeof(pGlobals->pci_irq_levels));
1439	pGlobals->fUseIoApic = fUseIoApic;
1440	memset(&pGlobals->pci_apic_irq_levels, 0, sizeof(pGlobals->pci_apic_irq_levels));
1441
1442	pBus->pDevInsHC = pDevIns;
1443	pBus->pDevInsGC = PDMDEVINS_2_GCPTR(pDevIns);
1444
1445	PciBusReg.u32Version = PDM_PCIBUSREG_VERSION;
1446	PciBusReg.pfnRegisterHC = pciRegister;
1447	PciBusReg.pfnIORegionRegisterHC = pciIORegionRegister;
1448	PciBusReg.pfnSetIrqHC = pciSetIrq;
1449	PciBusReg.pfnSaveExecHC = pciGenericSaveExec;
1450	PciBusReg.pfnLoadExecHC = pciGenericLoadExec;
1451	PciBusReg.pfnFakePCIBIOSHC = pciFakePCIBIOS;
1452	PciBusReg.pszSetIrqGC = fGCEnabled ? "pciSetIrq" : NULL;
1453	PciBusReg.pszSetIrqR0 = fR0Enabled ? "pciSetIrq" : NULL;
1454	rc = pDevIns->pDevHlp->pfnPCIBusRegister(pDevIns, &PciBusReg, &pBus->pPciHlpR3);
1455	if (VBOX_FAILURE(rc))
1456	return PDMDEV_SET_ERROR(pDevIns, rc,
1457	N_("Failed to register ourselves as a PCI Bus"));
1458
1459	pBus->pPciHlpGC = pBus->pPciHlpR3->pfnGetGCHelpers(pDevIns);
1460	pBus->pPciHlpR0 = pBus->pPciHlpR3->pfnGetR0Helpers(pDevIns);
1461
1462	/*
1463	* Fill in PCI configs and add them to the bus.
1464	*/
1465	/* i440FX */
1466	pBus->PciDev.config[0x00] = 0x86; /* vendor_id: Intel */
1467	pBus->PciDev.config[0x01] = 0x80;
1468	pBus->PciDev.config[0x02] = 0x37; /* device_id: */
1469	pBus->PciDev.config[0x03] = 0x12;
1470	pBus->PciDev.config[0x08] = 0x02; /* revision */
1471	pBus->PciDev.config[0x0a] = 0x00; /* class_sub = host2pci */
1472	pBus->PciDev.config[0x0b] = 0x06; /* class_base = PCI_bridge */
1473	pBus->PciDev.config[0x0e] = 0x00; /* header_type */
1474	pBus->PciDev.pDevIns = pDevIns;
1475	pBus->PciDev.Int.s.fRequestedDevFn= true;
1476	pciRegisterInternal(pBus, 0, &pBus->PciDev, "i440FX");
1477
1478	/* PIIX3 */
1479	pBus->PIIX3State.dev.config[0x00] = 0x86; /* vendor: Intel */
1480	pBus->PIIX3State.dev.config[0x01] = 0x80;
1481	pBus->PIIX3State.dev.config[0x02] = 0x00; /* device_id: 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */
1482	pBus->PIIX3State.dev.config[0x03] = 0x70;
1483	pBus->PIIX3State.dev.config[0x0a] = 0x01; /* class_sub = PCI_ISA */
1484	pBus->PIIX3State.dev.config[0x0b] = 0x06; /* class_base = PCI_bridge */
1485	pBus->PIIX3State.dev.config[0x0e] = 0x80; /* header_type = PCI_multifunction, generic */
1486	pBus->PIIX3State.dev.pDevIns = pDevIns;
1487	pBus->PciDev.Int.s.fRequestedDevFn= true;
1488	pciRegisterInternal(pBus, 8, &pBus->PIIX3State.dev, "PIIX3");
1489	piix3_reset(&pBus->PIIX3State);
1490
1491	pBus->iDevSearch = 16;
1492
1493	/*
1494	* Register I/O ports and save state.
1495	*/
1496	rc = PDMDevHlpIOPortRegister(pDevIns, 0xcf8, 1, NULL, pciIOPortAddressWrite, pciIOPortAddressRead, NULL, NULL, "i440FX (PCI)");
1497	if (VBOX_FAILURE(rc))
1498	return rc;
1499	rc = PDMDevHlpIOPortRegister(pDevIns, 0xcfc, 4, NULL, pciIOPortDataWrite, pciIOPortDataRead, NULL, NULL, "i440FX (PCI)");
1500	if (VBOX_FAILURE(rc))
1501	return rc;
1502	rc = PDMDevHlpSSMRegister(pDevIns, "pci", iInstance, 2, sizeof(*pBus),
1503	NULL, pciSaveExec, NULL, NULL, pciLoadExec, NULL);
1504	if (VBOX_FAILURE(rc))
1505	return rc;
1506
1507	return VINF_SUCCESS;
1508	}
1509
1510
1511	/**
1512	* The device registration structure.
1513	*/
1514	const PDMDEVREG g_DevicePCI =
1515	{
1516	/* u32Version */
1517	PDM_DEVREG_VERSION,
1518	/* szDeviceName */
1519	"pci",
1520	/* szGCMod */
1521	"VBoxDDGC.gc",
1522	/* szR0Mod */
1523	"VBoxDDR0.r0",
1524	/* pszDescription */
1525	"i440FX PCI bridge and PIIX3 ISA bridge.",
1526	/* fFlags */
1527	PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT \| PDM_DEVREG_FLAGS_GUEST_BITS_32 \| PDM_DEVREG_FLAGS_GC \| PDM_DEVREG_FLAGS_R0,
1528	/* fClass */
1529	PDM_DEVREG_CLASS_BUS_PCI \| PDM_DEVREG_CLASS_BUS_ISA,
1530	/* cMaxInstances */
1531	1,
1532	/* cbInstance */
1533	sizeof(PCIBUS),
1534	/* pfnConstruct */
1535	pciConstruct,
1536	/* pfnDestruct */
1537	NULL,
1538	/* pfnRelocate */
1539	pciRelocate,
1540	/* pfnIOCtl */
1541	NULL,
1542	/* pfnPowerOn */
1543	NULL,
1544	/* pfnReset */
1545	NULL,
1546	/* pfnSuspend */
1547	NULL,
1548	/* pfnResume */
1549	NULL,
1550	/* pfnAttach */
1551	NULL,
1552	/* pfnDetach */
1553	NULL,
1554	/* pfnQueryInterface */
1555	NULL,
1556	/* pfnInitComplete */
1557	NULL
1558	};
1559	#endif /* IN_RING3 */
1560	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */

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source: vbox/trunk/src/VBox/Devices/Bus/DevPCI.cpp@ 1959

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