DevPCI.cpp@ 23973

Last change on this file since 23973 was 23253, checked in by vboxsync, 15 years ago
DevPCI: Some save state and double underscore cleanup.
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1	/* $Id: DevPCI.cpp 23253 2009-09-23 11:56:01Z vboxsync $ */
2	/** @file
3	* DevPCI - PCI BUS Device.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	* --------------------------------------------------------------------
21	*
22	* This code is based on:
23	*
24	* QEMU PCI bus manager
25	*
26	* Copyright (c) 2004 Fabrice Bellard
27	*
28	* Permission is hereby granted, free of charge, to any person obtaining a copy
29	* of this software and associated documentation files (the "Software"), to deal
30	* in the Software without restriction, including without limitation the rights
31	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
32	* copies of the Software, and to permit persons to whom the Software is
33	* furnished to do so, subject to the following conditions:
34	*
35	* The above copyright notice and this permission notice shall be included in
36	* all copies or substantial portions of the Software.
37	*
38	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
39	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
40	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
41	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
42	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
43	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
44	* THE SOFTWARE.
45	*/
46
47	/*******************************************************************************
48	* Header Files *
49	*******************************************************************************/
50	#define LOG_GROUP LOG_GROUP_DEV_PCI
51	/* Hack to get PCIDEVICEINT declare at the right point - include "PCIInternal.h". */
52	#define PCI_INCLUDE_PRIVATE
53	#include <VBox/pci.h>
54	#include <VBox/pdmdev.h>
55	#include <iprt/assert.h>
56	#include <iprt/string.h>
57
58	#include "../Builtins.h"
59
60
61	/*******************************************************************************
62	* Structures and Typedefs *
63	*******************************************************************************/
64	/**
65	* PIIX3 ISA Bridge state.
66	*/
67	typedef struct PIIX3State
68	{
69	/** The PCI device of the bridge. */
70	PCIDEVICE dev;
71	} PIIX3State, PIIX3, *PPIIX3;
72
73	/**
74	* PCI Bus instance.
75	*/
76	typedef struct PCIBus
77	{
78	/** Bus number. */
79	int32_t iBus;
80	/** Start device number. */
81	int32_t iDevSearch;
82	/** Number of bridges attached to the bus. */
83	uint32_t cBridges;
84
85	uint32_t Alignment0;
86
87	/** Array of PCI devices. */
88	R3PTRTYPE(PPCIDEVICE) devices[256];
89	/** Array of bridges attached to the bus. */
90	R3PTRTYPE(PPCIDEVICE *) papBridgesR3;
91
92	/** R3 pointer to the device instance. */
93	PPDMDEVINSR3 pDevInsR3;
94	/** Pointer to the PCI R3 helpers. */
95	PCPDMPCIHLPR3 pPciHlpR3;
96
97	/** R0 pointer to the device instance. */
98	PPDMDEVINSR0 pDevInsR0;
99	/** Pointer to the PCI R0 helpers. */
100	PCPDMPCIHLPR0 pPciHlpR0;
101
102	/** RC pointer to the device instance. */
103	PPDMDEVINSRC pDevInsRC;
104	/** Pointer to the PCI RC helpers. */
105	PCPDMPCIHLPRC pPciHlpRC;
106
107	/** The PCI device for the PCI bridge. */
108	PCIDEVICE PciDev;
109
110	} PCIBUS;
111	/** Pointer to a PCIBUS instance. */
112	typedef PCIBUS *PPCIBUS;
113	typedef PCIBUS PCIBus;
114
115	/** @def PCI_IRQ_PINS
116	* Number of pins for interrupts (PIRQ#0...PIRQ#3)
117	*/
118	#define PCI_IRQ_PINS 4
119
120	/** @def PCI_APIC_IRQ_PINS
121	* Number of pins for interrupts if the APIC is used.
122	*/
123	#define PCI_APIC_IRQ_PINS 8
124
125	/**
126	* PCI Globals - This is the host-to-pci bridge and the root bus.
127	*/
128	typedef struct PCIGLOBALS
129	{
130	/** Irq levels for the four PCI Irqs.
131	* These count how many devices asserted
132	* the IRQ line. If greater 0 an IRQ is sent to the guest.
133	* If it drops to 0 the IRQ is deasserted.
134	*/
135	volatile uint32_t pci_irq_levels[PCI_IRQ_PINS];
136
137	#if 1 /* Will be moved into the BIOS soon. */
138	/** The next I/O port address which the PCI BIOS will use. */
139	uint32_t pci_bios_io_addr;
140	/** The next MMIO address which the PCI BIOS will use. */
141	uint32_t pci_bios_mem_addr;
142	/** Actual bus number. */
143	uint8_t uBus;
144	#endif
145
146	/** I/O APIC usage flag */
147	bool fUseIoApic;
148	/** I/O APIC irq levels */
149	volatile uint32_t pci_apic_irq_levels[PCI_APIC_IRQ_PINS];
150	/** ACPI IRQ level */
151	uint32_t acpi_irq_level;
152	/** ACPI PIC IRQ */
153	int acpi_irq;
154	/** Config register. */
155	uint32_t uConfigReg;
156
157	/** R3 pointer to the device instance. */
158	PPDMDEVINSR3 pDevInsR3;
159	/** R0 pointer to the device instance. */
160	PPDMDEVINSR0 pDevInsR0;
161	/** RC pointer to the device instance. */
162	PPDMDEVINSRC pDevInsRC;
163
164	#if HC_ARCH_BITS == 64
165	uint32_t Alignment0;
166	#endif
167
168	/** ISA bridge state. */
169	PIIX3 PIIX3State;
170	/** PCI bus which is attached to the host-to-PCI bridge. */
171	PCIBUS PciBus;
172
173	} PCIGLOBALS;
174	/** Pointer to per VM data. */
175	typedef PCIGLOBALS *PPCIGLOBALS;
176
177
178	/*******************************************************************************
179	* Defined Constants And Macros *
180	*******************************************************************************/
181
182	/** Converts a bus instance pointer to a device instance pointer. */
183	#define PCIBUS_2_DEVINS(pPciBus) ((pPciBus)->CTX_SUFF(pDevIns))
184	/** Converts a device instance pointer to a PCIGLOBALS pointer. */
185	#define DEVINS_2_PCIGLOBALS(pDevIns) ((PPCIGLOBALS)(PDMINS_2_DATA(pDevIns, PPCIGLOBALS)))
186	/** Converts a device instance pointer to a PCIBUS pointer. */
187	#define DEVINS_2_PCIBUS(pDevIns) ((PPCIBUS)(&PDMINS_2_DATA(pDevIns, PPCIGLOBALS)->PciBus))
188
189	/** Converts a pointer to a PCI bus instance to a PCIGLOBALS pointer.
190	* @note This works only if the bus number is 0!!!
191	*/
192	#define PCIBUS_2_PCIGLOBALS(pPciBus) ( (PPCIGLOBALS)((uintptr_t)(pPciBus) - RT_OFFSETOF(PCIGLOBALS, PciBus)) )
193
194	/** @def PCI_LOCK
195	* Acquires the PDM lock. This is a NOP if locking is disabled. */
196	/** @def PCI_UNLOCK
197	* Releases the PDM lock. This is a NOP if locking is disabled. */
198	#define PCI_LOCK(pDevIns, rc) \
199	do { \
200	int rc2 = DEVINS_2_PCIBUS(pDevIns)->CTX_SUFF(pPciHlp)->pfnLock((pDevIns), rc); \
201	if (rc2 != VINF_SUCCESS) \
202	return rc2; \
203	} while (0)
204	#define PCI_UNLOCK(pDevIns) \
205	DEVINS_2_PCIBUS(pDevIns)->CTX_SUFF(pPciHlp)->pfnUnlock(pDevIns)
206
207	/** @def VBOX_PCI_SAVED_STATE_VERSION
208	* Saved state version of the PCI bus device.
209	*/
210	#define VBOX_PCI_SAVED_STATE_VERSION 3
211
212
213	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
214	/*******************************************************************************
215	* Internal Functions *
216	*******************************************************************************/
217	RT_C_DECLS_BEGIN
218
219	PDMBOTHCBDECL(void) pciSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel);
220	PDMBOTHCBDECL(void) pcibridgeSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel);
221	PDMBOTHCBDECL(int) pciIOPortAddressWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
222	PDMBOTHCBDECL(int) pciIOPortAddressRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb);
223	PDMBOTHCBDECL(int) pciIOPortDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
224	PDMBOTHCBDECL(int) pciIOPortDataRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb);
225
226	#ifdef IN_RING3
227	DECLINLINE(PPCIDEVICE) pciFindBridge(PPCIBUS pBus, uint8_t iBus);
228	#endif
229
230	RT_C_DECLS_END
231
232	#define DEBUG_PCI
233
234	#define PCI_VENDOR_ID 0x00 /* 16 bits */
235	#define PCI_DEVICE_ID 0x02 /* 16 bits */
236	#define PCI_COMMAND 0x04 /* 16 bits */
237	#define PCI_COMMAND_IO 0x01 /* Enable response in I/O space */
238	#define PCI_COMMAND_MEMORY 0x02 /* Enable response in Memory space */
239	#define PCI_CLASS_DEVICE 0x0a /* Device class */
240	#define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
241	#define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
242	#define PCI_MIN_GNT 0x3e /* 8 bits */
243	#define PCI_MAX_LAT 0x3f /* 8 bits */
244
245
246	#ifdef IN_RING3
247
248	static void pci_update_mappings(PCIDevice *d)
249	{
250	PPCIBUS pBus = d->Int.s.CTX_SUFF(pBus);
251	PCIIORegion *r;
252	int cmd, i;
253	uint32_t last_addr, new_addr, config_ofs;
254
255	cmd = RT_LE2H_U16((uint16_t )(d->config + PCI_COMMAND));
256	for(i = 0; i < PCI_NUM_REGIONS; i++) {
257	r = &d->Int.s.aIORegions[i];
258	if (i == PCI_ROM_SLOT) {
259	config_ofs = 0x30;
260	} else {
261	config_ofs = 0x10 + i * 4;
262	}
263	if (r->size != 0) {
264	if (r->type & PCI_ADDRESS_SPACE_IO) {
265	if (cmd & PCI_COMMAND_IO) {
266	new_addr = RT_LE2H_U32((uint32_t )(d->config +
267	config_ofs));
268	new_addr = new_addr & ~(r->size - 1);
269	last_addr = new_addr + r->size - 1;
270	/* NOTE: we have only 64K ioports on PC */
271	if (last_addr <= new_addr \|\| new_addr == 0 \|\|
272	last_addr >= 0x10000) {
273	new_addr = ~0U;
274	}
275	} else {
276	new_addr = ~0U;
277	}
278	} else {
279	if (cmd & PCI_COMMAND_MEMORY) {
280	new_addr = RT_LE2H_U32((uint32_t )(d->config +
281	config_ofs));
282	/* the ROM slot has a specific enable bit */
283	if (i == PCI_ROM_SLOT && !(new_addr & 1))
284	goto no_mem_map;
285	new_addr = new_addr & ~(r->size - 1);
286	last_addr = new_addr + r->size - 1;
287	/* NOTE: we do not support wrapping */
288	/* XXX: as we cannot support really dynamic
289	mappings, we handle specific values as invalid
290	mappings. */
291	if (last_addr <= new_addr \|\| new_addr == 0 \|\|
292	last_addr == ~0U) {
293	new_addr = ~0U;
294	}
295	} else {
296	no_mem_map:
297	new_addr = ~0U;
298	}
299	}
300	/* now do the real mapping */
301	if (new_addr != r->addr) {
302	if (r->addr != ~0U) {
303	if (r->type & PCI_ADDRESS_SPACE_IO) {
304	int devclass;
305	/* NOTE: specific hack for IDE in PC case:
306	only one byte must be mapped. */
307	devclass = d->config[0x0a] \| (d->config[0x0b] << 8);
308	if (devclass == 0x0101 && r->size == 4) {
309	int rc = d->pDevIns->pDevHlpR3->pfnIOPortDeregister(d->pDevIns, r->addr + 2, 1);
310	AssertRC(rc);
311	} else {
312	int rc = d->pDevIns->pDevHlpR3->pfnIOPortDeregister(d->pDevIns, r->addr, r->size);
313	AssertRC(rc);
314	}
315	} else {
316	RTGCPHYS GCPhysBase = r->addr;
317	int rc;
318	if (pBus->pPciHlpR3->pfnIsMMIO2Base(pBus->pDevInsR3, d->pDevIns, GCPhysBase))
319	{
320	/* unmap it. */
321	rc = r->map_func(d, i, NIL_RTGCPHYS, r->size, (PCIADDRESSSPACE)(r->type));
322	AssertRC(rc);
323	rc = PDMDevHlpMMIO2Unmap(d->pDevIns, i, GCPhysBase);
324	}
325	else
326	rc = d->pDevIns->pDevHlpR3->pfnMMIODeregister(d->pDevIns, GCPhysBase, r->size);
327	AssertMsgRC(rc, ("rc=%Rrc d=%s i=%d GCPhysBase=%RGp size=%#x\n", rc, d->name, i, GCPhysBase, r->size));
328	}
329	}
330	r->addr = new_addr;
331	if (r->addr != ~0U) {
332	int rc = r->map_func(d, i,
333	r->addr + (r->type & PCI_ADDRESS_SPACE_IO ? 0 : 0),
334	r->size, (PCIADDRESSSPACE)(r->type));
335	AssertRC(rc);
336	}
337	}
338	}
339	}
340	}
341
342
343	static DECLCALLBACK(uint32_t) pci_default_read_config(PCIDevice *d, uint32_t address, unsigned len)
344	{
345	uint32_t val;
346	switch(len) {
347	case 1:
348	val = d->config[address];
349	break;
350	case 2:
351	val = RT_LE2H_U16((uint16_t )(d->config + address));
352	break;
353	default:
354	case 4:
355	val = RT_LE2H_U32((uint32_t )(d->config + address));
356	break;
357	}
358	return val;
359	}
360
361	static DECLCALLBACK(void) pci_default_write_config(PCIDevice *d, uint32_t address, uint32_t val, unsigned len)
362	{
363	int can_write;
364	unsigned i;
365	uint32_t end, addr;
366
367	if (len == 4 && ((address >= 0x10 && address < 0x10 + 4 * 6) \|\|
368	(address >= 0x30 && address < 0x34))) {
369	PCIIORegion *r;
370	int reg;
371
372	if ( address >= 0x30 ) {
373	reg = PCI_ROM_SLOT;
374	}else{
375	reg = (address - 0x10) >> 2;
376	}
377	r = &d->Int.s.aIORegions[reg];
378	if (r->size == 0)
379	goto default_config;
380	/* compute the stored value */
381	if (reg == PCI_ROM_SLOT) {
382	/* keep ROM enable bit */
383	val &= (~(r->size - 1)) \| 1;
384	} else {
385	val &= ~(r->size - 1);
386	val \|= r->type;
387	}
388	(uint32_t )(d->config + address) = RT_H2LE_U32(val);
389	pci_update_mappings(d);
390	return;
391	}
392	default_config:
393	/* not efficient, but simple */
394	addr = address;
395	for(i = 0; i < len; i++) {
396	/* default read/write accesses */
397	switch(d->config[0x0e]) {
398	case 0x00: /* normal device */
399	case 0x80: /* multi-function device */
400	switch(addr) {
401	case 0x00:
402	case 0x01:
403	case 0x02:
404	case 0x03:
405	case 0x08:
406	case 0x09:
407	case 0x0a:
408	case 0x0b:
409	case 0x0e:
410	case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17: /* base */
411	case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f:
412	case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27:
413	case 0x2c: case 0x2d: /* subsystem ID */
414	case 0x2e: case 0x2f: /* vendor ID */
415	case 0x30: case 0x31: case 0x32: case 0x33: /* rom */
416	case 0x3d:
417	can_write = 0;
418	break;
419	default:
420	can_write = 1;
421	break;
422	}
423	break;
424	default:
425	case 0x01: /* bridge */
426	switch(addr) {
427	case 0x00:
428	case 0x01:
429	case 0x02:
430	case 0x03:
431	case 0x08:
432	case 0x09:
433	case 0x0a:
434	case 0x0b:
435	case 0x0e:
436	case 0x38: case 0x39: case 0x3a: case 0x3b: /* rom */
437	case 0x3d:
438	can_write = 0;
439	break;
440	default:
441	can_write = 1;
442	break;
443	}
444	break;
445	}
446	#ifdef VBOX
447	if (addr == 0x06)
448	{
449	/* don't change read-only bits => actually all lower bits are read-only */
450	val &= UINT32_C(~0xff);
451	/* status register, low part: clear bits by writing a '1' to the corresponding bit */
452	d->config[addr] &= ~val;
453	}
454	else if (addr == 0x07)
455	{
456	/* don't change read-only bits */
457	val &= UINT32_C(~0x06);
458	/* status register, high part: clear bits by writing a '1' to the corresponding bit */
459	d->config[addr] &= ~val;
460	}
461	else
462	#endif
463	if (can_write) {
464	d->config[addr] = val;
465	}
466	addr++;
467	val >>= 8;
468	}
469
470	end = address + len;
471	if (end > PCI_COMMAND && address < (PCI_COMMAND + 2)) {
472	/* if the command register is modified, we must modify the mappings */
473	pci_update_mappings(d);
474	}
475	}
476
477	#endif /* IN_RING3 */
478
479	static int pci_data_write(PPCIGLOBALS pGlobals, uint32_t addr, uint32_t val, int len)
480	{
481	uint8_t iBus, iDevice;
482	uint32_t config_addr;
483
484	Log(("pci_data_write: addr=%08x val=%08x len=%d\n", pGlobals->uConfigReg, val, len));
485
486	if (!(pGlobals->uConfigReg & (1 << 31))) {
487	return VINF_SUCCESS;
488	}
489	if ((pGlobals->uConfigReg & 0x3) != 0) {
490	return VINF_SUCCESS;
491	}
492	iBus = (pGlobals->uConfigReg >> 16) & 0xff;
493	iDevice = (pGlobals->uConfigReg >> 8) & 0xff;
494	config_addr = (pGlobals->uConfigReg & 0xfc) \| (addr & 3);
495	if (iBus != 0)
496	{
497	if (pGlobals->PciBus.cBridges)
498	{
499	#ifdef IN_RING3 /** @todo do lookup in R0/RC too! */
500	PPCIDEVICE pBridgeDevice = pciFindBridge(&pGlobals->PciBus, iBus);
501	if (pBridgeDevice)
502	{
503	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigWrite);
504	pBridgeDevice->Int.s.pfnBridgeConfigWrite(pBridgeDevice->pDevIns, iBus, iDevice, config_addr, val, len);
505	}
506	#else
507	return VINF_IOM_HC_IOPORT_WRITE;
508	#endif
509	}
510	}
511	else
512	{
513	R3PTRTYPE(PCIDevice *) pci_dev = pGlobals->PciBus.devices[iDevice];
514	if (pci_dev)
515	{
516	#ifdef IN_RING3
517	Log(("pci_config_write: %s: addr=%02x val=%08x len=%d\n", pci_dev->name, config_addr, val, len));
518	pci_dev->Int.s.pfnConfigWrite(pci_dev, config_addr, val, len);
519	#else
520	return VINF_IOM_HC_IOPORT_WRITE;
521	#endif
522	}
523	}
524	return VINF_SUCCESS;
525	}
526
527	static int pci_data_read(PPCIGLOBALS pGlobals, uint32_t addr, int len, uint32_t *pu32)
528	{
529	uint8_t iBus, iDevice;
530	uint32_t config_addr;
531
532	*pu32 = 0xffffffff;
533
534	if (!(pGlobals->uConfigReg & (1 << 31)))
535	return VINF_SUCCESS;
536	if ((pGlobals->uConfigReg & 0x3) != 0)
537	return VINF_SUCCESS;
538	iBus = (pGlobals->uConfigReg >> 16) & 0xff;
539	iDevice = (pGlobals->uConfigReg >> 8) & 0xff;
540	config_addr = (pGlobals->uConfigReg & 0xfc) \| (addr & 3);
541	if (iBus != 0)
542	{
543	if (pGlobals->PciBus.cBridges)
544	{
545	#ifdef IN_RING3 /** @todo do lookup in R0/RC too! */
546	PPCIDEVICE pBridgeDevice = pciFindBridge(&pGlobals->PciBus, iBus);
547	if (pBridgeDevice)
548	{
549	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigRead);
550	*pu32 = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->pDevIns, iBus, iDevice, config_addr, len);
551	}
552	#else
553	return VINF_IOM_HC_IOPORT_READ;
554	#endif
555	}
556	}
557	else
558	{
559	R3PTRTYPE(PCIDevice *) pci_dev = pGlobals->PciBus.devices[iDevice];
560	if (pci_dev)
561	{
562	#ifdef IN_RING3
563	*pu32 = pci_dev->Int.s.pfnConfigRead(pci_dev, config_addr, len);
564	Log(("pci_config_read: %s: addr=%02x val=%08x len=%d\n", pci_dev->name, config_addr, *pu32, len));
565	#else
566	return VINF_IOM_HC_IOPORT_READ;
567	#endif
568	}
569	}
570
571	return VINF_SUCCESS;
572	}
573
574
575
576	/* return the global irq number corresponding to a given device irq
577	pin. We could also use the bus number to have a more precise
578	mapping.
579	This is the implementation note described in the PCI spec chapter 2.2.6 */
580	static inline int pci_slot_get_pirq(uint8_t uDevFn, int irq_num)
581	{
582	int slot_addend;
583	slot_addend = (uDevFn >> 3) - 1;
584	return (irq_num + slot_addend) & 3;
585	}
586
587	static inline int pci_slot_get_apic_pirq(uint8_t uDevFn, int irq_num)
588	{
589	return (irq_num + (uDevFn >> 3)) & 7;
590	}
591
592	static inline int get_pci_irq_apic_level(PPCIGLOBALS pGlobals, int irq_num)
593	{
594	return (pGlobals->pci_apic_irq_levels[irq_num] != 0);
595	}
596
597	static void apic_set_irq(PPCIBUS pBus, uint8_t uDevFn, PCIDevice *pPciDev, int irq_num1, int iLevel, int acpi_irq)
598	{
599	/* This is only allowed to be called with a pointer to the host bus. */
600	AssertMsg(pBus->iBus == 0, ("iBus=%u\n", pBus->iBus));
601
602	if (acpi_irq == -1) {
603	int apic_irq, apic_level;
604	PPCIGLOBALS pGlobals = PCIBUS_2_PCIGLOBALS(pBus);
605	int irq_num = pci_slot_get_apic_pirq(uDevFn, irq_num1);
606
607	if ((iLevel & PDM_IRQ_LEVEL_HIGH) == PDM_IRQ_LEVEL_HIGH)
608	ASMAtomicIncU32(&pGlobals->pci_apic_irq_levels[irq_num]);
609	else if ((iLevel & PDM_IRQ_LEVEL_HIGH) == PDM_IRQ_LEVEL_LOW)
610	ASMAtomicDecU32(&pGlobals->pci_apic_irq_levels[irq_num]);
611
612	apic_irq = irq_num + 0x10;
613	apic_level = get_pci_irq_apic_level(pGlobals, irq_num);
614	Log3(("apic_set_irq: %s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d\n",
615	R3STRING(pPciDev->name), irq_num1, iLevel, apic_irq, apic_level, irq_num));
616	pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), apic_irq, apic_level);
617
618	if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP) {
619	ASMAtomicDecU32(&pGlobals->pci_apic_irq_levels[irq_num]);
620	pPciDev->Int.s.uIrqPinState = PDM_IRQ_LEVEL_LOW;
621	apic_level = get_pci_irq_apic_level(pGlobals, irq_num);
622	Log3(("apic_set_irq: %s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d (flop)\n",
623	R3STRING(pPciDev->name), irq_num1, iLevel, apic_irq, apic_level, irq_num));
624	pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), apic_irq, apic_level);
625	}
626	} else {
627	Log3(("apic_set_irq: %s: irq_num1=%d level=%d acpi_irq=%d\n",
628	R3STRING(pPciDev->name), irq_num1, iLevel, acpi_irq));
629	pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), acpi_irq, iLevel);
630	}
631	}
632
633	DECLINLINE(int) get_pci_irq_level(PPCIGLOBALS pGlobals, int irq_num)
634	{
635	return (pGlobals->pci_irq_levels[irq_num] != 0);
636	}
637
638	/**
639	* Set the IRQ for a PCI device on the host bus - shared by host bus and bridge.
640	*
641	* @param pDevIns Device instance of the host PCI Bus.
642	* @param uDevFn The device number on the host bus which will raise the IRQ
643	* @param pPciDev The PCI device structure which raised the interrupt.
644	* @param iIrq IRQ number to set.
645	* @param iLevel IRQ level.
646	* @remark uDevFn and pPciDev->devfn are not the same if the device is behind a bridge.
647	* In that case uDevFn will be the slot of the bridge which is needed to calculate the
648	* PIRQ value.
649	*/
650	static void pciSetIrqInternal(PPCIGLOBALS pGlobals, uint8_t uDevFn, PPCIDEVICE pPciDev, int iIrq, int iLevel)
651	{
652	PPCIBUS pBus = &pGlobals->PciBus;
653	uint8_t *pbCfg = pGlobals->PIIX3State.dev.config;
654	const bool fIsAcpiDevice = pPciDev->config[2] == 0x13 && pPciDev->config[3] == 0x71;
655	const bool fIsApicEnabled = pGlobals->fUseIoApic && pbCfg[0xde] == 0xbe && pbCfg[0xad] == 0xef;
656	int pic_irq, pic_level;
657
658	/* Check if the state changed. */
659	if (pPciDev->Int.s.uIrqPinState != iLevel)
660	{
661	pPciDev->Int.s.uIrqPinState = (iLevel & PDM_IRQ_LEVEL_HIGH);
662
663	/* apic only */
664	if (fIsApicEnabled)
665	{
666	if (fIsAcpiDevice)
667	/*
668	* ACPI needs special treatment since SCI is hardwired and
669	* should not be affected by PCI IRQ routing tables at the
670	* same time SCI IRQ is shared in PCI sense hence this
671	* kludge (i.e. we fetch the hardwired value from ACPIs
672	* PCI device configuration space).
673	*/
674	apic_set_irq(pBus, uDevFn, pPciDev, -1, iLevel, pPciDev->config[PCI_INTERRUPT_LINE]);
675	else
676	apic_set_irq(pBus, uDevFn, pPciDev, iIrq, iLevel, -1);
677	return;
678	}
679
680	if (fIsAcpiDevice)
681	{
682	/* As per above treat ACPI in a special way */
683	pic_irq = pPciDev->config[PCI_INTERRUPT_LINE];
684	pGlobals->acpi_irq = pic_irq;
685	pGlobals->acpi_irq_level = iLevel & PDM_IRQ_LEVEL_HIGH;
686	}
687	else
688	{
689	int irq_num;
690	irq_num = pci_slot_get_pirq(uDevFn, iIrq);
691
692	if (pPciDev->Int.s.uIrqPinState == PDM_IRQ_LEVEL_HIGH)
693	ASMAtomicIncU32(&pGlobals->pci_irq_levels[irq_num]);
694	else if (pPciDev->Int.s.uIrqPinState == PDM_IRQ_LEVEL_LOW)
695	ASMAtomicDecU32(&pGlobals->pci_irq_levels[irq_num]);
696
697	/* now we change the pic irq level according to the piix irq mappings */
698	pic_irq = pbCfg[0x60 + irq_num];
699	if (pic_irq >= 16)
700	{
701	if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP)
702	{
703	ASMAtomicDecU32(&pGlobals->pci_irq_levels[irq_num]);
704	pPciDev->Int.s.uIrqPinState = PDM_IRQ_LEVEL_LOW;
705	}
706
707	return;
708	}
709	}
710
711	/* the pic level is the logical OR of all the PCI irqs mapped to it */
712	pic_level = 0;
713	if (pic_irq == pbCfg[0x60])
714	pic_level \|= get_pci_irq_level(pGlobals, 0);
715	if (pic_irq == pbCfg[0x61])
716	pic_level \|= get_pci_irq_level(pGlobals, 1);
717	if (pic_irq == pbCfg[0x62])
718	pic_level \|= get_pci_irq_level(pGlobals, 2);
719	if (pic_irq == pbCfg[0x63])
720	pic_level \|= get_pci_irq_level(pGlobals, 3);
721	if (pic_irq == pGlobals->acpi_irq)
722	pic_level \|= pGlobals->acpi_irq_level;
723
724	Log3(("pciSetIrq: %s: iLevel=%d iIrq=%d pic_irq=%d pic_level=%d\n",
725	R3STRING(pPciDev->name), iLevel, iIrq, pic_irq, pic_level));
726	pBus->CTX_SUFF(pPciHlp)->pfnIsaSetIrq(pBus->CTX_SUFF(pDevIns), pic_irq, pic_level);
727
728	/** @todo optimize pci irq flip-flop some rainy day. */
729	if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP)
730	pciSetIrqInternal(pGlobals, uDevFn, pPciDev, iIrq, PDM_IRQ_LEVEL_LOW);
731	}
732	}
733
734	/**
735	* Set the IRQ for a PCI device on the host bus.
736	*
737	* @param pDevIns Device instance of the PCI Bus.
738	* @param pPciDev The PCI device structure.
739	* @param iIrq IRQ number to set.
740	* @param iLevel IRQ level.
741	*/
742	PDMBOTHCBDECL(void) pciSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel)
743	{
744	pciSetIrqInternal(PDMINS_2_DATA(pDevIns, PPCIGLOBALS), pPciDev->devfn, pPciDev, iIrq, iLevel);
745	}
746
747	#ifdef IN_RING3
748
749	/**
750	* Finds a bridge on the bus which contains the destination bus.
751	*
752	* @return Pointer to the device instance data of the bus or
753	* NULL if no bridge was found.
754	* @param pBus Pointer to the bus to search on.
755	* @param iBus Destination bus number.
756	*/
757	DECLINLINE(PPCIDEVICE) pciFindBridge(PPCIBUS pBus, uint8_t iBus)
758	{
759	/* Search for a fitting bridge. */
760	for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
761	{
762	/*
763	* Examine secondary and subordinate bus number.
764	* If the target bus is in the range we pass the request on to the bridge.
765	*/
766	PPCIDEVICE pBridgeTemp = pBus->papBridgesR3[iBridge];
767	AssertMsg(pBridgeTemp && pBridgeTemp->Int.s.fPciToPciBridge,
768	("Device is not a PCI bridge but on the list of PCI bridges\n"));
769
770	if ( iBus >= pBridgeTemp->config[VBOX_PCI_SECONDARY_BUS]
771	&& iBus <= pBridgeTemp->config[VBOX_PCI_SUBORDINATE_BUS])
772	return pBridgeTemp;
773	}
774
775	/* Nothing found. */
776	return NULL;
777	}
778
779	static void piix3_reset(PIIX3State *d)
780	{
781	uint8_t *pci_conf = d->dev.config;
782
783	pci_conf[0x04] = 0x07; /* master, memory and I/O */
784	pci_conf[0x05] = 0x00;
785	pci_conf[0x06] = 0x00;
786	pci_conf[0x07] = 0x02; /* PCI_status_devsel_medium */
787	pci_conf[0x4c] = 0x4d;
788	pci_conf[0x4e] = 0x03;
789	pci_conf[0x4f] = 0x00;
790	pci_conf[0x60] = 0x80;
791	pci_conf[0x69] = 0x02;
792	pci_conf[0x70] = 0x80;
793	pci_conf[0x76] = 0x0c;
794	pci_conf[0x77] = 0x0c;
795	pci_conf[0x78] = 0x02;
796	pci_conf[0x79] = 0x00;
797	pci_conf[0x80] = 0x00;
798	pci_conf[0x82] = 0x02; /* Get rid of the Linux guest "Enabling Passive Release" PCI quirk warning. */
799	pci_conf[0xa0] = 0x08;
800	pci_conf[0xa0] = 0x08;
801	pci_conf[0xa2] = 0x00;
802	pci_conf[0xa3] = 0x00;
803	pci_conf[0xa4] = 0x00;
804	pci_conf[0xa5] = 0x00;
805	pci_conf[0xa6] = 0x00;
806	pci_conf[0xa7] = 0x00;
807	pci_conf[0xa8] = 0x0f;
808	pci_conf[0xaa] = 0x00;
809	pci_conf[0xab] = 0x00;
810	pci_conf[0xac] = 0x00;
811	pci_conf[0xae] = 0x00;
812	}
813
814	static void pci_config_writel(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t val)
815	{
816	pGlobals->uConfigReg = 0x80000000 \| (uBus << 16) \|
817	(uDevFn << 8) \| addr;
818	pci_data_write(pGlobals, 0, val, 4);
819	}
820
821	static void pci_config_writew(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t val)
822	{
823	pGlobals->uConfigReg = 0x80000000 \| (uBus << 16) \|
824	(uDevFn << 8) \| (addr & ~3);
825	pci_data_write(pGlobals, addr & 3, val, 2);
826	}
827
828	static void pci_config_writeb(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t val)
829	{
830	pGlobals->uConfigReg = 0x80000000 \| (uBus << 16) \|
831	(uDevFn << 8) \| (addr & ~3);
832	pci_data_write(pGlobals, addr & 3, val, 1);
833	}
834
835	static uint32_t pci_config_readl(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr)
836	{
837	pGlobals->uConfigReg = 0x80000000 \| (uBus << 16) \|
838	(uDevFn << 8) \| addr;
839	uint32_t u32Val;
840	int rc = pci_data_read(pGlobals, 0, 4, &u32Val);
841	AssertRC(rc);
842	return u32Val;
843	}
844
845	static uint32_t pci_config_readw(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr)
846	{
847	pGlobals->uConfigReg = 0x80000000 \| (uBus << 16) \|
848	(uDevFn << 8) \| (addr & ~3);
849	uint32_t u32Val;
850	int rc = pci_data_read(pGlobals, addr & 3, 2, &u32Val);
851	AssertRC(rc);
852	return u32Val;
853	}
854
855	static uint32_t pci_config_readb(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr)
856	{
857	pGlobals->uConfigReg = 0x80000000 \| (uBus << 16) \|
858	(uDevFn << 8) \| (addr & ~3);
859	uint32_t u32Val;
860	int rc = pci_data_read(pGlobals, addr & 3, 1, &u32Val);
861	AssertRC(rc);
862	return u32Val;
863	}
864
865	/* host irqs corresponding to PCI irqs A-D */
866	static const uint8_t pci_irqs[4] = { 11, 9, 11, 9 }; /* bird: added const */
867
868	static void pci_set_io_region_addr(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, int region_num, uint32_t addr)
869	{
870	uint16_t cmd;
871	uint32_t ofs;
872
873	if ( region_num == PCI_ROM_SLOT )
874	ofs = 0x30;
875	else
876	ofs = 0x10 + region_num * 4;
877
878	/* Read memory type first. */
879	uint8_t uRessourceType = pci_config_readb(pGlobals, uBus, uDevFn, ofs);
880
881	/* Read command register. */
882	cmd = pci_config_readw(pGlobals, uBus, uDevFn, PCI_COMMAND);
883	if ( region_num == PCI_ROM_SLOT )
884	cmd \|= 2;
885	else if ((uRessourceType & 0x01) == 1) /* Test if region is I/O space. */
886	cmd \|= 1; /* Enable I/O space access. */
887	else /* The region is MMIO. */
888	cmd \|= 2; /* Enable MMIO access. */
889
890	/* Write address of the device. */
891	pci_config_writel(pGlobals, uBus, uDevFn, ofs, addr);
892
893	/* enable memory mappings */
894	pci_config_writew(pGlobals, uBus, uDevFn, PCI_COMMAND, cmd);
895	}
896
897	static void pci_bios_init_device(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint8_t cBridgeDepth, uint8_t *paBridgePositions)
898	{
899	uint32_t *paddr;
900	int i, pin, pic_irq;
901	uint16_t devclass, vendor_id, device_id;
902
903	devclass = pci_config_readw(pGlobals, uBus, uDevFn, PCI_CLASS_DEVICE);
904	vendor_id = pci_config_readw(pGlobals, uBus, uDevFn, PCI_VENDOR_ID);
905	device_id = pci_config_readw(pGlobals, uBus, uDevFn, PCI_DEVICE_ID);
906
907	/* Check if device is present. */
908	if (vendor_id != 0xffff)
909	{
910	switch(devclass)
911	{
912	case 0x0101:
913	if ( (vendor_id == 0x8086)
914	&& (device_id == 0x7010 \|\| device_id == 0x7111 \|\| device_id == 0x269e))
915	{
916	/* PIIX3, PIIX4 or ICH6 IDE */
917	pci_config_writew(pGlobals, uBus, uDevFn, 0x40, 0x8000); /* enable IDE0 */
918	pci_config_writew(pGlobals, uBus, uDevFn, 0x42, 0x8000); /* enable IDE1 */
919	goto default_map;
920	}
921	else
922	{
923	/* IDE: we map it as in ISA mode */
924	pci_set_io_region_addr(pGlobals, uBus, uDevFn, 0, 0x1f0);
925	pci_set_io_region_addr(pGlobals, uBus, uDevFn, 1, 0x3f4);
926	pci_set_io_region_addr(pGlobals, uBus, uDevFn, 2, 0x170);
927	pci_set_io_region_addr(pGlobals, uBus, uDevFn, 3, 0x374);
928	}
929	break;
930	case 0x0300:
931	if (vendor_id != 0x80ee)
932	goto default_map;
933	/* VGA: map frame buffer to default Bochs VBE address */
934	pci_set_io_region_addr(pGlobals, uBus, uDevFn, 0, 0xE0000000);
935	/*
936	* Legacy VGA I/O ports are implicitly decoded by a VGA class device. But
937	* only the framebuffer (i.e., a memory region) is explicitly registered via
938	* pci_set_io_region_addr, so I/O decoding must be enabled manually.
939	*/
940	pci_config_writeb(pGlobals, uBus, uDevFn, PCI_COMMAND,
941	pci_config_readb(pGlobals, uBus, uDevFn, PCI_COMMAND)
942	\| 1 /* Enable I/O space access. */);
943	break;
944	case 0x0800:
945	/* PIC */
946	vendor_id = pci_config_readw(pGlobals, uBus, uDevFn, PCI_VENDOR_ID);
947	device_id = pci_config_readw(pGlobals, uBus, uDevFn, PCI_DEVICE_ID);
948	if (vendor_id == 0x1014)
949	{
950	/* IBM */
951	if (device_id == 0x0046 \|\| device_id == 0xFFFF)
952	{
953	/* MPIC & MPIC2 */
954	pci_set_io_region_addr(pGlobals, uBus, uDevFn, 0, 0x80800000 + 0x00040000);
955	}
956	}
957	break;
958	case 0xff00:
959	if ( (vendor_id == 0x0106b)
960	&& (device_id == 0x0017 \|\| device_id == 0x0022))
961	{
962	/* macio bridge */
963	pci_set_io_region_addr(pGlobals, uBus, uDevFn, 0, 0x80800000);
964	}
965	break;
966	case 0x0604:
967	{
968	/* Init PCI-to-PCI bridge. */
969	pci_config_writeb(pGlobals, uBus, uDevFn, VBOX_PCI_PRIMARY_BUS, uBus);
970
971	AssertMsg(pGlobals->uBus < 255, ("Too many bridges on the bus\n"));
972	pGlobals->uBus++;
973	pci_config_writeb(pGlobals, uBus, uDevFn, VBOX_PCI_SECONDARY_BUS, pGlobals->uBus);
974	pci_config_writeb(pGlobals, uBus, uDevFn, VBOX_PCI_SUBORDINATE_BUS, 0xff); /* Temporary until we know how many other bridges are behind this one. */
975
976	/* Add position of this bridge into the array. */
977	paBridgePositions[cBridgeDepth+1] = (uDevFn >> 3);
978
979	/*
980	* The I/O range for the bridge must be aligned to a 4KB boundary.
981	* This does not change anything really as the access to the device is not going
982	* through the bridge but we want to be compliant to the spec.
983	*/
984	if ((pGlobals->pci_bios_io_addr % 4096) != 0)
985	pGlobals->pci_bios_io_addr = RT_ALIGN_32(pGlobals->pci_bios_io_addr, 4*1024);
986	Log(("%s: Aligned I/O start address. New address %#x\n", __FUNCTION__, pGlobals->pci_bios_io_addr));
987	pci_config_writeb(pGlobals, uBus, uDevFn, VBOX_PCI_IO_BASE, (pGlobals->pci_bios_io_addr >> 8) & 0xf0);
988
989	/* The MMIO range for the bridge must be aligned to a 1MB boundary. */
990	if ((pGlobals->pci_bios_mem_addr % (1024 * 1024)) != 0)
991	pGlobals->pci_bios_mem_addr = RT_ALIGN_32(pGlobals->pci_bios_mem_addr, 1024*1024);
992	Log(("%s: Aligned MMIO start address. New address %#x\n", __FUNCTION__, pGlobals->pci_bios_mem_addr));
993	pci_config_writew(pGlobals, uBus, uDevFn, VBOX_PCI_MEMORY_BASE, (pGlobals->pci_bios_mem_addr >> 16) & UINT32_C(0xffff0));
994
995	/* Save values to compare later to. */
996	uint32_t u32IoAddressBase = pGlobals->pci_bios_io_addr;
997	uint32_t u32MMIOAddressBase = pGlobals->pci_bios_mem_addr;
998
999	/* Init devices behind the bridge and possibly other bridges as well. */
1000	for (int i = 0; i <= 255; i++)
1001	pci_bios_init_device(pGlobals, uBus + 1, i, cBridgeDepth + 1, paBridgePositions);
1002
1003	/* The number of bridges behind the this one is now available. */
1004	pci_config_writeb(pGlobals, uBus, uDevFn, VBOX_PCI_SUBORDINATE_BUS, pGlobals->uBus);
1005
1006	/*
1007	* Set I/O limit register. If there is no device with I/O space behind the bridge
1008	* we set a lower value than in the base register.
1009	* The result with a real bridge is that no I/O transactions are passed to the secondary
1010	* interface. Again this doesn't really matter here but we want to be compliant to the spec.
1011	*/
1012	if ((u32IoAddressBase != pGlobals->pci_bios_io_addr) && ((pGlobals->pci_bios_io_addr % 4096) != 0))
1013	{
1014	/* The upper boundary must be one byte less than a 4KB boundary. */
1015	pGlobals->pci_bios_io_addr = RT_ALIGN_32(pGlobals->pci_bios_io_addr, 4*1024);
1016	}
1017	pci_config_writeb(pGlobals, uBus, uDevFn, VBOX_PCI_IO_LIMIT, ((pGlobals->pci_bios_io_addr >> 8) & 0xf0) - 1);
1018
1019	/* Same with the MMIO limit register but with 1MB boundary here. */
1020	if ((u32MMIOAddressBase != pGlobals->pci_bios_mem_addr) && ((pGlobals->pci_bios_mem_addr % (1024 * 1024)) != 0))
1021	{
1022	/* The upper boundary must be one byte less than a 1MB boundary. */
1023	pGlobals->pci_bios_mem_addr = RT_ALIGN_32(pGlobals->pci_bios_mem_addr, 1024*1024);
1024	}
1025	pci_config_writew(pGlobals, uBus, uDevFn, VBOX_PCI_MEMORY_LIMIT, ((pGlobals->pci_bios_mem_addr >> 16) & UINT32_C(0xfff0)) - 1);
1026
1027	/*
1028	* Set the prefetch base and limit registers. We currently have no device with a prefetchable region
1029	* which may be behind a bridge. Thatswhy it is unconditionally disabled here atm by writing a higher value into
1030	* the base register than in the limit register.
1031	*/
1032	pci_config_writew(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_MEMORY_BASE, 0xfff0);
1033	pci_config_writew(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_MEMORY_LIMIT, 0x0);
1034	pci_config_writel(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_BASE_UPPER32, 0x00);
1035	pci_config_writel(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_LIMIT_UPPER32, 0x00);
1036	break;
1037	}
1038	default:
1039	default_map:
1040	{
1041	/* default memory mappings */
1042	/*
1043	* PCI_NUM_REGIONS is 7 because of the rom region but there are only 6 base address register defined by the PCI spec.
1044	* Leaving only PCI_NUM_REGIONS would cause reading another and enabling a memory region which does not exist.
1045	*/
1046	for(i = 0; i < (PCI_NUM_REGIONS-1); i++)
1047	{
1048	uint32_t u32Size;
1049	uint8_t u8RessourceType;
1050	uint32_t u32Address = 0x10 + i * 4;
1051
1052	/* Calculate size. */
1053	u8RessourceType = pci_config_readb(pGlobals, uBus, uDevFn, u32Address);
1054	pci_config_writel(pGlobals, uBus, uDevFn, u32Address, UINT32_C(0xffffffff));
1055	u32Size = pci_config_readl(pGlobals, uBus, uDevFn, u32Address);
1056	/* Clear ressource information depending on ressource type. */
1057	if ((u8RessourceType & 0x01) == 1) /* I/O */
1058	u32Size &= ~(0x01);
1059	else /* MMIO */
1060	u32Size &= ~(0x0f);
1061
1062	/*
1063	* Invert all bits and add 1 to get size of the region.
1064	* (From PCI implementation note)
1065	*/
1066	if (((u8RessourceType & 0x01) == 1) && (u32Size & UINT32_C(0xffff0000)) == 0)
1067	u32Size = (~(u32Size \| UINT32_C(0xffff0000))) + 1;
1068	else
1069	u32Size = (~u32Size) + 1;
1070
1071	Log(("%s: Size of region %u for device %d on bus %d is %u\n", __FUNCTION__, i, uDevFn, uBus, u32Size));
1072
1073	if (u32Size)
1074	{
1075	if ((u8RessourceType & 0x01) == 1)
1076	paddr = &pGlobals->pci_bios_io_addr;
1077	else
1078	paddr = &pGlobals->pci_bios_mem_addr;
1079	paddr = (paddr + u32Size - 1) & ~(u32Size - 1);
1080	Log(("%s: Start address of %s region %u is %#x\n", __FUNCTION__, ((u8RessourceType & 0x01) == 1 ? "I/O" : "MMIO"), i, *paddr));
1081	pci_set_io_region_addr(pGlobals, uBus, uDevFn, i, *paddr);
1082	*paddr += u32Size;
1083	Log(("%s: New address is %#x\n", __FUNCTION__, *paddr));
1084	}
1085	}
1086	break;
1087	}
1088	}
1089
1090	/* map the interrupt */
1091	pin = pci_config_readb(pGlobals, uBus, uDevFn, PCI_INTERRUPT_PIN);
1092	if (pin != 0)
1093	{
1094	uint8_t uBridgeDevFn = uDevFn;
1095	pin--;
1096
1097	/* We need to go up to the host bus to see which irq this device will assert there. */
1098	while (cBridgeDepth != 0)
1099	{
1100	/* Get the pin the device would assert on the bridge. */
1101	pin = ((uBridgeDevFn >> 3) + pin) & 3;
1102	uBridgeDevFn = paBridgePositions[cBridgeDepth];
1103	cBridgeDepth--;
1104	}
1105
1106	pin = pci_slot_get_pirq(uDevFn, pin);
1107	pic_irq = pci_irqs[pin];
1108	pci_config_writeb(pGlobals, uBus, uDevFn, PCI_INTERRUPT_LINE, pic_irq);
1109	}
1110	}
1111	}
1112
1113	#endif /* IN_RING3 */
1114
1115	/* -=-=-=-=-=- wrappers -=-=-=-=-=- */
1116
1117	/**
1118	* Port I/O Handler for PCI address OUT operations.
1119	*
1120	* @returns VBox status code.
1121	*
1122	* @param pDevIns The device instance.
1123	* @param pvUser User argument - ignored.
1124	* @param uPort Port number used for the IN operation.
1125	* @param u32 The value to output.
1126	* @param cb The value size in bytes.
1127	*/
1128	PDMBOTHCBDECL(int) pciIOPortAddressWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1129	{
1130	Log(("pciIOPortAddressWrite: Port=%#x u32=%#x cb=%d\n", Port, u32, cb));
1131	NOREF(pvUser);
1132	if (cb == 4)
1133	{
1134	PPCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
1135	PCI_LOCK(pDevIns, VINF_IOM_HC_IOPORT_WRITE);
1136	pThis->uConfigReg = u32;
1137	PCI_UNLOCK(pDevIns);
1138	}
1139	/* else: 440FX does "pass through to the bus" for other writes, what ever that means.
1140	* Linux probes for cmd640 using byte writes/reads during ide init. We'll just ignore it. */
1141	return VINF_SUCCESS;
1142	}
1143
1144
1145	/**
1146	* Port I/O Handler for PCI address IN operations.
1147	*
1148	* @returns VBox status code.
1149	*
1150	* @param pDevIns The device instance.
1151	* @param pvUser User argument - ignored.
1152	* @param uPort Port number used for the IN operation.
1153	* @param pu32 Where to store the result.
1154	* @param cb Number of bytes read.
1155	*/
1156	PDMBOTHCBDECL(int) pciIOPortAddressRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
1157	{
1158	NOREF(pvUser);
1159	if (cb == 4)
1160	{
1161	PPCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
1162	PCI_LOCK(pDevIns, VINF_IOM_HC_IOPORT_READ);
1163	*pu32 = pThis->uConfigReg;
1164	PCI_UNLOCK(pDevIns);
1165	Log(("pciIOPortAddressRead: Port=%#x cb=%d -> %#x\n", Port, cb, *pu32));
1166	return VINF_SUCCESS;
1167	}
1168	/* else: 440FX does "pass through to the bus" for other writes, what ever that means.
1169	* Linux probes for cmd640 using byte writes/reads during ide init. We'll just ignore it. */
1170	Log(("pciIOPortAddressRead: Port=%#x cb=%d VERR_IOM_IOPORT_UNUSED\n", Port, cb));
1171	return VERR_IOM_IOPORT_UNUSED;
1172	}
1173
1174
1175	/**
1176	* Port I/O Handler for PCI data OUT operations.
1177	*
1178	* @returns VBox status code.
1179	*
1180	* @param pDevIns The device instance.
1181	* @param pvUser User argument - ignored.
1182	* @param uPort Port number used for the IN operation.
1183	* @param u32 The value to output.
1184	* @param cb The value size in bytes.
1185	*/
1186	PDMBOTHCBDECL(int) pciIOPortDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1187	{
1188	Log(("pciIOPortDataWrite: Port=%#x u32=%#x cb=%d\n", Port, u32, cb));
1189	NOREF(pvUser);
1190	int rc = VINF_SUCCESS;
1191	if (!(Port % cb))
1192	{
1193	PCI_LOCK(pDevIns, VINF_IOM_HC_IOPORT_WRITE);
1194	rc = pci_data_write(PDMINS_2_DATA(pDevIns, PPCIGLOBALS), Port, u32, cb);
1195	PCI_UNLOCK(pDevIns);
1196	}
1197	else
1198	AssertMsgFailed(("Write to port %#x u32=%#x cb=%d\n", Port, u32, cb));
1199	return rc;
1200	}
1201
1202
1203	/**
1204	* Port I/O Handler for PCI data IN operations.
1205	*
1206	* @returns VBox status code.
1207	*
1208	* @param pDevIns The device instance.
1209	* @param pvUser User argument - ignored.
1210	* @param uPort Port number used for the IN operation.
1211	* @param pu32 Where to store the result.
1212	* @param cb Number of bytes read.
1213	*/
1214	PDMBOTHCBDECL(int) pciIOPortDataRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
1215	{
1216	NOREF(pvUser);
1217	if (!(Port % cb))
1218	{
1219	PCI_LOCK(pDevIns, VINF_IOM_HC_IOPORT_READ);
1220	int rc = pci_data_read(PDMINS_2_DATA(pDevIns, PPCIGLOBALS), Port, cb, pu32);
1221	PCI_UNLOCK(pDevIns);
1222	Log(("pciIOPortDataRead: Port=%#x cb=%#x -> %#x (%Rrc)\n", Port, cb, *pu32, rc));
1223	return rc;
1224	}
1225	AssertMsgFailed(("Read from port %#x cb=%d\n", Port, cb));
1226	return VERR_IOM_IOPORT_UNUSED;
1227	}
1228
1229	#ifdef IN_RING3
1230
1231	/**
1232	* Saves a state of the PCI device.
1233	*
1234	* @returns VBox status code.
1235	* @param pDevIns Device instance of the PCI Bus.
1236	* @param pPciDev Pointer to PCI device.
1237	* @param pSSMHandle The handle to save the state to.
1238	*/
1239	static DECLCALLBACK(int) pciGenericSaveExec(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PSSMHANDLE pSSMHandle)
1240	{
1241	return SSMR3PutMem(pSSMHandle, &pPciDev->config[0], sizeof(pPciDev->config));
1242	}
1243
1244
1245	/**
1246	* Loads a saved PCI device state.
1247	*
1248	* @returns VBox status code.
1249	* @param pDevIns Device instance of the PCI Bus.
1250	* @param pPciDev Pointer to PCI device.
1251	* @param pSSMHandle The handle to the saved state.
1252	*/
1253	static DECLCALLBACK(int) pciGenericLoadExec(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PSSMHANDLE pSSMHandle)
1254	{
1255	return SSMR3GetMem(pSSMHandle, &pPciDev->config[0], sizeof(pPciDev->config));
1256	}
1257
1258
1259	/**
1260	* Common worker for pciR3SaveExec and pcibridgeR3SaveExec.
1261	*
1262	* @returns VBox status code.
1263	* @param pBus The bus to save.
1264	* @param pSSM The saved state handle.
1265	*/
1266	static int pciR3CommonSaveExec(PPCIBUS pBus, PSSMHANDLE pSSM)
1267	{
1268	/*
1269	* Iterate thru all the devices.
1270	*/
1271	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->devices); i++)
1272	{
1273	PPCIDEVICE pDev = pBus->devices[i];
1274	if (pDev)
1275	{
1276	SSMR3PutU32(pSSM, i);
1277	SSMR3PutMem(pSSM, pDev->config, sizeof(pDev->config));
1278
1279	int rc = SSMR3PutS32(pSSM, pDev->Int.s.uIrqPinState);
1280	if (RT_FAILURE(rc))
1281	return rc;
1282	}
1283	}
1284	return SSMR3PutU32(pSSM, UINT32_MAX); /* terminator */
1285	}
1286
1287
1288	/**
1289	* Saves a state of the PCI device.
1290	*
1291	* @returns VBox status code.
1292	* @param pDevIns The device instance.
1293	* @param pPciDev Pointer to PCI device.
1294	* @param pSSMHandle The handle to save the state to.
1295	*/
1296	static DECLCALLBACK(int) pciR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle)
1297	{
1298	uint32_t i;
1299	PPCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
1300
1301	/*
1302	* Bus state data.
1303	*/
1304	SSMR3PutU32(pSSMHandle, pThis->uConfigReg);
1305	SSMR3PutBool(pSSMHandle, pThis->fUseIoApic);
1306
1307	/*
1308	* Save IRQ states.
1309	*/
1310	for (i = 0; i < PCI_IRQ_PINS; i++)
1311	SSMR3PutU32(pSSMHandle, pThis->pci_irq_levels[i]);
1312	for (i = 0; i < PCI_APIC_IRQ_PINS; i++)
1313	SSMR3PutU32(pSSMHandle, pThis->pci_apic_irq_levels[i]);
1314
1315	SSMR3PutU32(pSSMHandle, pThis->acpi_irq_level);
1316	SSMR3PutS32(pSSMHandle, pThis->acpi_irq);
1317
1318	SSMR3PutU32(pSSMHandle, ~0); /* separator */
1319
1320	/*
1321	* Join paths with pcibridgeR3SaveExec.
1322	*/
1323	return pciR3CommonSaveExec(&pThis->PciBus, pSSMHandle);
1324	}
1325
1326
1327	/**
1328	* Disables all PCI devices prior to state loading.
1329	*
1330	* @returns VINF_SUCCESS.
1331	* @param pBus The PCI bus instance.
1332	*/
1333	static int pciR3CommonLoadPrep(PPCIBUS pBus)
1334	{
1335	/*
1336	* Iterate thru all the devices and write 0 to the COMMAND register.
1337	* The register value is restored afterwards so we can do proper
1338	* LogRels in pciR3CommonRestoreConfig.
1339	*/
1340	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->devices); i++)
1341	{
1342	PPCIDEVICE pDev = pBus->devices[i];
1343	if (pDev)
1344	{
1345	uint16_t u16 = PCIDevGetCommand(pDev);
1346	pDev->Int.s.pfnConfigWrite(pDev, VBOX_PCI_COMMAND, 0, 2);
1347	PCIDevSetCommand(pDev, u16);
1348	Assert(PCIDevGetCommand(pDev) == u16);
1349	}
1350	}
1351	return VINF_SUCCESS;
1352	}
1353
1354
1355	/**
1356	* Prepares a state load.
1357	*
1358	* This will disable all the device so that the I/O regions gets unmapped.
1359	*
1360	* @returns VINF_SUCCESS
1361	* @param pDevIns The device instance.
1362	* @param pSSMHandle The saved state handle.
1363	*/
1364	static DECLCALLBACK(int) pciR3LoadPrep(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle)
1365	{
1366	PPCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
1367	return pciR3CommonLoadPrep(&pThis->PciBus);
1368	}
1369
1370
1371	/**
1372	* Common routine for restoring the config registers of a PCI device.
1373	*
1374	* @param pDev The PCI device.
1375	* @param pbSrcConfig The configuration register values to be loaded.
1376	* @param fIsBridge Whether this is a bridge device or not.
1377	*/
1378	static void pciR3CommonRestoreConfig(PPCIDEVICE pDev, uint8_t const *pbSrcConfig, bool fIsBridge)
1379	{
1380	/*
1381	* This table defines the fields for normal devices and bridge devices, and
1382	* the order in which they need to be restored.
1383	*/
1384	static const struct PciField
1385	{
1386	uint8_t off;
1387	uint8_t cb;
1388	uint8_t fWritable;
1389	uint8_t fBridge;
1390	const char *pszName;
1391	} s_aFields[] =
1392	{
1393	/* off,cb,fW,fB, pszName */
1394	{ 0x00, 2, 0, 3, "VENDOR_ID" },
1395	{ 0x02, 2, 0, 3, "DEVICE_ID" },
1396	{ 0x06, 2, 1, 3, "STATUS" },
1397	{ 0x08, 1, 0, 3, "REVISION_ID" },
1398	{ 0x09, 1, 0, 3, "CLASS_PROG" },
1399	{ 0x0a, 1, 0, 3, "CLASS_SUB" },
1400	{ 0x0b, 1, 0, 3, "CLASS_BASE" },
1401	{ 0x0c, 1, 0, 3, "CACHE_LINE_SIZE" }, // fWritable = ??
1402	{ 0x0d, 1, 0, 3, "LATENCY_TIMER" }, // fWritable = ??
1403	{ 0x0e, 1, 0, 3, "HEADER_TYPE" }, // fWritable = ??
1404	{ 0x0f, 1, 0, 3, "BIST" }, // fWritable = ??
1405	{ 0x10, 4, 1, 3, "BASE_ADDRESS_0" },
1406	{ 0x14, 4, 1, 3, "BASE_ADDRESS_1" },
1407	{ 0x18, 4, 1, 1, "BASE_ADDRESS_2" },
1408	{ 0x18, 1, 1, 2, "PRIMARY_BUS" }, // fWritable = ??
1409	{ 0x19, 1, 1, 2, "SECONDARY_BUS" }, // fWritable = ??
1410	{ 0x1a, 1, 1, 2, "SUBORDINATE_BUS" }, // fWritable = ??
1411	{ 0x1b, 1, 1, 2, "SEC_LATENCY_TIMER" }, // fWritable = ??
1412	{ 0x1c, 4, 1, 1, "BASE_ADDRESS_3" },
1413	{ 0x1c, 1, 1, 2, "IO_BASE" }, // fWritable = ??
1414	{ 0x1d, 1, 1, 2, "IO_LIMIT" }, // fWritable = ??
1415	{ 0x1e, 2, 1, 2, "SEC_STATUS" }, // fWritable = ??
1416	{ 0x20, 4, 1, 1, "BASE_ADDRESS_4" },
1417	{ 0x20, 2, 1, 2, "MEMORY_BASE" }, // fWritable = ??
1418	{ 0x22, 2, 1, 2, "MEMORY_LIMIT" }, // fWritable = ??
1419	{ 0x24, 4, 1, 1, "BASE_ADDRESS_4" },
1420	{ 0x24, 2, 1, 2, "PREF_MEMORY_BASE" }, // fWritable = ??
1421	{ 0x26, 2, 1, 2, "PREF_MEMORY_LIMIT" }, // fWritable = ??
1422	{ 0x28, 4, 1, 1, "CARDBUS_CIS" }, // fWritable = ??
1423	{ 0x28, 4, 1, 2, "PREF_BASE_UPPER32" }, // fWritable = ??
1424	{ 0x2c, 2, 0, 1, "SUBSYSTEM_VENDOR_ID" },// fWritable = !?
1425	{ 0x2c, 4, 1, 2, "PREF_LIMIT_UPPER32" },// fWritable = ??
1426	{ 0x2e, 2, 0, 1, "SUBSYSTEM_ID" }, // fWritable = !?
1427	{ 0x30, 4, 1, 1, "ROM_ADDRESS" }, // fWritable = ?!
1428	{ 0x30, 2, 1, 2, "IO_BASE_UPPER16" }, // fWritable = ?!
1429	{ 0x32, 2, 1, 2, "IO_LIMIT_UPPER16" }, // fWritable = ?!
1430	{ 0x34, 4, 0, 3, "CAPABILITY_LIST" }, // fWritable = !? cb=!?
1431	{ 0x38, 4, 1, 1, "???" }, // ???
1432	{ 0x38, 4, 1, 2, "ROM_ADDRESS_BR" }, // fWritable = !? cb=!? fBridge=!?
1433	{ 0x3c, 1, 1, 3, "INTERRUPT_LINE" }, // fBridge=??
1434	{ 0x3d, 1, 0, 3, "INTERRUPT_PIN" }, // fBridge=??
1435	{ 0x3e, 1, 0, 1, "MIN_GNT" }, // fWritable = !?
1436	{ 0x3e, 1, 1, 2, "BRIDGE_CONTROL" }, // fWritable = !? cb=!?
1437	{ 0x3f, 1, 1, 3, "MAX_LAT" }, // fWritable = !? fBridge=!?
1438	/* The COMMAND register must come last as it requires the ADDRESS
1439	registers to be restored before we pretent to change it from 0 to
1440	whatever value the guest assigned it. */
1441	{ 0x04, 2, 1, 3, "COMMAND" },
1442	};
1443
1444	#ifdef RT_STRICT
1445	/* Check that we've got full register coverage. */
1446	uint32_t bmDevice[0x40 / 32];
1447	uint32_t bmBridge[0x40 / 32];
1448	RT_ZERO(bmDevice);
1449	RT_ZERO(bmBridge);
1450	for (uint32_t i = 0; i < RT_ELEMENTS(s_aFields); i++)
1451	{
1452	uint8_t off = s_aFields[i].off;
1453	uint8_t cb = s_aFields[i].cb;
1454	uint8_t f = s_aFields[i].fBridge;
1455	while (cb-- > 0)
1456	{
1457	if (f & 1) AssertMsg(!ASMBitTest(bmDevice, off), ("%#x\n", off));
1458	if (f & 2) AssertMsg(!ASMBitTest(bmBridge, off), ("%#x\n", off));
1459	if (f & 1) ASMBitSet(bmDevice, off);
1460	if (f & 2) ASMBitSet(bmBridge, off);
1461	off++;
1462	}
1463	}
1464	for (uint32_t off = 0; off < 0x40; off++)
1465	{
1466	AssertMsg(ASMBitTest(bmDevice, off), ("%#x\n", off));
1467	AssertMsg(ASMBitTest(bmBridge, off), ("%#x\n", off));
1468	}
1469	#endif
1470
1471	/*
1472	* Loop thru the fields covering the 64 bytes of standard registers.
1473	*/
1474	uint8_t const fBridge = fIsBridge ? 2 : 1;
1475	uint8_t *pbDstConfig = &pDev->config[0];
1476	for (uint32_t i = 0; i < RT_ELEMENTS(s_aFields); i++)
1477	if (s_aFields[i].fBridge & fBridge)
1478	{
1479	uint8_t const off = s_aFields[i].off;
1480	uint8_t const cb = s_aFields[i].cb;
1481	uint32_t u32Src;
1482	uint32_t u32Dst;
1483	switch (cb)
1484	{
1485	case 1:
1486	u32Src = pbSrcConfig[off];
1487	u32Dst = pbDstConfig[off];
1488	break;
1489	case 2:
1490	u32Src = (uint16_t const )&pbSrcConfig[off];
1491	u32Dst = (uint16_t const )&pbDstConfig[off];
1492	break;
1493	case 4:
1494	u32Src = (uint32_t const )&pbSrcConfig[off];
1495	u32Dst = (uint32_t const )&pbDstConfig[off];
1496	break;
1497	default:
1498	AssertFailed();
1499	continue;
1500	}
1501
1502	if ( u32Src != u32Dst
1503	\|\| off == VBOX_PCI_COMMAND)
1504	{
1505	if (u32Src != u32Dst)
1506	{
1507	if (!s_aFields[i].fWritable)
1508	LogRel(("PCI: %8s/%u: %2u-bit field %s: %x -> %x - !READ ONLY!\n",
1509	pDev->name, pDev->pDevIns->iInstance, cb*8, s_aFields[i].pszName, u32Dst, u32Src));
1510	else
1511	LogRel(("PCI: %8s/%u: %2u-bit field %s: %x -> %x\n",
1512	pDev->name, pDev->pDevIns->iInstance, cb*8, s_aFields[i].pszName, u32Dst, u32Src));
1513	}
1514	if (off == VBOX_PCI_COMMAND)
1515	PCIDevSetCommand(pDev, 0); /* For remapping, see pciR3CommonLoadPrep. */
1516	pDev->Int.s.pfnConfigWrite(pDev, off, u32Src, cb);
1517	}
1518	}
1519
1520	/*
1521	* The device dependent registers.
1522	*
1523	* We will not use ConfigWrite here as we have no clue about the size
1524	* of the registers, so the device is responsible for correctly
1525	* restoring functionality governed by these registers.
1526	*/
1527	for (uint32_t off = 0x40; off < sizeof(pDev->config); off++)
1528	if (pbDstConfig[off] != pbSrcConfig[off])
1529	{
1530	LogRel(("PCI: %8s/%u: register %02x: %02x -> %02x\n",
1531	pDev->name, pDev->pDevIns->iInstance, off, pbDstConfig[off], pbSrcConfig[off])); /** @todo make this Log() later. */
1532	pbDstConfig[off] = pbSrcConfig[off];
1533	}
1534	}
1535
1536
1537	/**
1538	* Common worker for pciR3LoadExec and pcibridgeR3LoadExec.
1539	*
1540	* @returns VBox status code.
1541	* @param pBus The bus which data is being loaded.
1542	* @param pSSMHandle The saved state handle.
1543	* @param uVersion The data version.
1544	* @param uPass The pass.
1545	*/
1546	static DECLCALLBACK(int) pciR3CommonLoadExec(PPCIBUS pBus, PSSMHANDLE pSSMHandle, uint32_t uVersion, uint32_t uPass)
1547	{
1548	uint32_t u32;
1549	uint32_t i;
1550	int rc;
1551
1552	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
1553
1554	/*
1555	* Iterate all the devices.
1556	*/
1557	for (i = 0;; i++)
1558	{
1559	PCIDEVICE DevTmp;
1560	PPCIDEVICE pDev;
1561
1562	/* index / terminator */
1563	rc = SSMR3GetU32(pSSMHandle, &u32);
1564	if (RT_FAILURE(rc))
1565	return rc;
1566	if (u32 == (uint32_t)~0)
1567	break;
1568	if ( u32 >= RT_ELEMENTS(pBus->devices)
1569	\|\| u32 < i)
1570	{
1571	AssertMsgFailed(("u32=%#x i=%#x\n", u32, i));
1572	return rc;
1573	}
1574
1575	/* skip forward to the device checking that no new devices are present. */
1576	for (; i < u32; i++)
1577	{
1578	if (pBus->devices[i])
1579	{
1580	LogRel(("New device in slot %#x, %s (vendor=%#06x device=%#06x)\n", i, pBus->devices[i]->name,
1581	PCIDevGetVendorId(pBus->devices[i]), PCIDevGetDeviceId(pBus->devices[i])));
1582	if (SSMR3HandleGetAfter(pSSMHandle) != SSMAFTER_DEBUG_IT)
1583	AssertFailedReturn(VERR_SSM_LOAD_CONFIG_MISMATCH);
1584	}
1585	}
1586
1587	/* get the data */
1588	DevTmp.Int.s.uIrqPinState = ~0; /* Invalid value in case we have an older saved state to force a state change in pciSetIrq. */
1589	SSMR3GetMem(pSSMHandle, DevTmp.config, sizeof(DevTmp.config));
1590	if (uVersion < 3)
1591	{
1592	int32_t i32Temp;
1593	/* Irq value not needed anymore. */
1594	rc = SSMR3GetS32(pSSMHandle, &i32Temp);
1595	if (RT_FAILURE(rc))
1596	return rc;
1597	}
1598	else
1599	{
1600	rc = SSMR3GetS32(pSSMHandle, &DevTmp.Int.s.uIrqPinState);
1601	if (RT_FAILURE(rc))
1602	return rc;
1603	}
1604
1605	/* check that it's still around. */
1606	pDev = pBus->devices[i];
1607	if (!pDev)
1608	{
1609	LogRel(("Device in slot %#x has been removed! vendor=%#06x device=%#06x\n", i,
1610	PCIDevGetVendorId(&DevTmp), PCIDevGetDeviceId(&DevTmp)));
1611	if (SSMR3HandleGetAfter(pSSMHandle) != SSMAFTER_DEBUG_IT)
1612	AssertFailedReturn(VERR_SSM_LOAD_CONFIG_MISMATCH);
1613	continue;
1614	}
1615
1616	/* match the vendor id assuming that this will never be changed. */
1617	if ( DevTmp.config[0] != pDev->config[0]
1618	\|\| DevTmp.config[1] != pDev->config[1])
1619	{
1620	LogRel(("Device in slot %#x (%s) vendor id mismatch! saved=%.4Rhxs current=%.4Rhxs\n",
1621	i, pDev->name, DevTmp.config, pDev->config));
1622	AssertFailedReturn(VERR_SSM_LOAD_CONFIG_MISMATCH);
1623	}
1624
1625	/* commit the loaded device config. */
1626	pciR3CommonRestoreConfig(pDev, &DevTmp.config[0], false ); /** @todo fix bridge fun! */
1627
1628	pDev->Int.s.uIrqPinState = DevTmp.Int.s.uIrqPinState;
1629	}
1630
1631	return VINF_SUCCESS;
1632	}
1633
1634
1635	/**
1636	* Loads a saved PCI device state.
1637	*
1638	* @returns VBox status code.
1639	* @param pDevIns The device instance.
1640	* @param pSSMHandle The handle to the saved state.
1641	* @param uVersion The data unit version number.
1642	* @param uPass The data pass.
1643	*/
1644	static DECLCALLBACK(int) pciR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle, uint32_t uVersion, uint32_t uPass)
1645	{
1646	PPCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
1647	PPCIBUS pBus = &pThis->PciBus;
1648	uint32_t u32;
1649	uint32_t i;
1650	int rc;
1651
1652	/*
1653	* Check the version.
1654	*/
1655	if (uVersion > VBOX_PCI_SAVED_STATE_VERSION)
1656	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1657	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
1658
1659	/*
1660	* Bus state data.
1661	*/
1662	SSMR3GetU32(pSSMHandle, &pThis->uConfigReg);
1663	if (uVersion > 1)
1664	SSMR3GetBool(pSSMHandle, &pThis->fUseIoApic);
1665
1666	/* Load IRQ states. */
1667	if (uVersion > 2)
1668	{
1669	for (uint8_t i = 0; i < PCI_IRQ_PINS; i++)
1670	SSMR3GetU32(pSSMHandle, (uint32_t *)&pThis->pci_irq_levels[i]);
1671	for (uint8_t i = 0; i < PCI_APIC_IRQ_PINS; i++)
1672	SSMR3GetU32(pSSMHandle, (uint32_t *)&pThis->pci_apic_irq_levels[i]);
1673
1674	SSMR3GetU32(pSSMHandle, &pThis->acpi_irq_level);
1675	SSMR3GetS32(pSSMHandle, &pThis->acpi_irq);
1676	}
1677
1678	/* separator */
1679	rc = SSMR3GetU32(pSSMHandle, &u32);
1680	if (RT_FAILURE(rc))
1681	return rc;
1682	if (u32 != (uint32_t)~0)
1683	AssertMsgFailedReturn(("u32=%#x\n", u32), rc);
1684
1685	/*
1686	* The devices.
1687	*/
1688	return pciR3CommonLoadExec(pBus, pSSMHandle, uVersion, uPass);
1689	}
1690
1691
1692	/* -=-=-=-=-=- real code -=-=-=-=-=- */
1693
1694	/**
1695	* Registers the device with the specified PCI bus.
1696	*
1697	* @returns VBox status code.
1698	* @param pBus The bus to register with.
1699	* @param iDev The PCI device ordinal.
1700	* @param pPciDev The PCI device structure.
1701	* @param pszName Pointer to device name (permanent, readonly). For debugging, not unique.
1702	*/
1703	static int pciRegisterInternal(PPCIBUS pBus, int iDev, PPCIDEVICE pPciDev, const char *pszName)
1704	{
1705	/*
1706	* Find device slot.
1707	*/
1708	if (iDev < 0)
1709	{
1710	/*
1711	* Special check for the IDE controller which is our function 1 device
1712	* before searching.
1713	*/
1714	if ( !strcmp(pszName, "piix3ide")
1715	&& !pBus->devices[9])
1716	iDev = 9;
1717	#ifdef VBOX_WITH_LPC
1718	/* LPC bus expected to be there by some guests, better make an additional argument to PDM
1719	device helpers, but requires significant rewrite */
1720	else if (!strcmp(pszName, "lpc")
1721	&& !pBus->devices[0xf8])
1722	iDev = 0xf8;
1723	#endif
1724	else
1725	{
1726	Assert(!(pBus->iDevSearch % 8));
1727	for (iDev = pBus->iDevSearch; iDev < (int)RT_ELEMENTS(pBus->devices); iDev += 8)
1728	if ( !pBus->devices[iDev]
1729	&& !pBus->devices[iDev + 1]
1730	&& !pBus->devices[iDev + 2]
1731	&& !pBus->devices[iDev + 3]
1732	&& !pBus->devices[iDev + 4]
1733	&& !pBus->devices[iDev + 5]
1734	&& !pBus->devices[iDev + 6]
1735	&& !pBus->devices[iDev + 7])
1736	break;
1737	if (iDev >= (int)RT_ELEMENTS(pBus->devices))
1738	{
1739	AssertMsgFailed(("Couldn't find free spot!\n"));
1740	return VERR_PDM_TOO_PCI_MANY_DEVICES;
1741	}
1742	}
1743	pPciDev->Int.s.fRequestedDevFn = false;
1744	}
1745	else
1746	{
1747	/*
1748	* An explicit request.
1749	*
1750	* If the slot is occupied we'll have to relocate the device
1751	* currently occupying it first. This can only be done if the
1752	* existing device wasn't explicitly assigned. Also we limit
1753	* ourselves to function 0 devices.
1754	*
1755	* If you start setting devices + function in the
1756	* config, do it for all pci devices!
1757	*/
1758	//AssertReleaseMsg(iDev > 8 \|\| pBus->iBus != 0, ("iDev=%d pszName=%s\n", iDev, pszName));
1759	if (pBus->devices[iDev])
1760	{
1761	int iDevRel;
1762	AssertReleaseMsg(!(iDev % 8), ("PCI Configuration Conflict! iDev=%d pszName=%s clashes with %s\n",
1763	iDev, pszName, pBus->devices[iDev]->name));
1764	if ( pBus->devices[iDev]->Int.s.fRequestedDevFn
1765	\|\| (pBus->devices[iDev + 1] && pBus->devices[iDev + 1]->Int.s.fRequestedDevFn)
1766	\|\| (pBus->devices[iDev + 2] && pBus->devices[iDev + 2]->Int.s.fRequestedDevFn)
1767	\|\| (pBus->devices[iDev + 3] && pBus->devices[iDev + 3]->Int.s.fRequestedDevFn)
1768	\|\| (pBus->devices[iDev + 4] && pBus->devices[iDev + 4]->Int.s.fRequestedDevFn)
1769	\|\| (pBus->devices[iDev + 5] && pBus->devices[iDev + 5]->Int.s.fRequestedDevFn)
1770	\|\| (pBus->devices[iDev + 6] && pBus->devices[iDev + 6]->Int.s.fRequestedDevFn)
1771	\|\| (pBus->devices[iDev + 7] && pBus->devices[iDev + 7]->Int.s.fRequestedDevFn))
1772	{
1773	AssertReleaseMsgFailed(("Configuration error:'%s' and '%s' are both configured as device %d\n",
1774	pszName, pBus->devices[iDev]->name, iDev));
1775	return VERR_INTERNAL_ERROR;
1776	}
1777
1778	/* Find free slot for the device(s) we're moving and move them. */
1779	for (iDevRel = pBus->iDevSearch; iDevRel < (int)RT_ELEMENTS(pBus->devices); iDevRel += 8)
1780	{
1781	if ( !pBus->devices[iDevRel]
1782	&& !pBus->devices[iDevRel + 1]
1783	&& !pBus->devices[iDevRel + 2]
1784	&& !pBus->devices[iDevRel + 3]
1785	&& !pBus->devices[iDevRel + 4]
1786	&& !pBus->devices[iDevRel + 5]
1787	&& !pBus->devices[iDevRel + 6]
1788	&& !pBus->devices[iDevRel + 7])
1789	{
1790	int i = 0;
1791	for (i = 0; i < 8; i++)
1792	{
1793	if (!pBus->devices[iDev + i])
1794	continue;
1795	Log(("PCI: relocating '%s' from slot %#x to %#x\n", pBus->devices[iDev + i]->name, iDev + i, iDevRel + i));
1796	pBus->devices[iDevRel + i] = pBus->devices[iDev + i];
1797	pBus->devices[iDevRel + i]->devfn = i;
1798	pBus->devices[iDev + i] = NULL;
1799	}
1800	}
1801	}
1802	if (pBus->devices[iDev])
1803	{
1804	AssertMsgFailed(("Couldn't find free spot!\n"));
1805	return VERR_PDM_TOO_PCI_MANY_DEVICES;
1806	}
1807	} /* if conflict */
1808	pPciDev->Int.s.fRequestedDevFn = true;
1809	}
1810
1811	Assert(!pBus->devices[iDev]);
1812	pPciDev->devfn = iDev;
1813	pPciDev->name = pszName;
1814	pPciDev->Int.s.pBusR3 = pBus;
1815	pPciDev->Int.s.pBusR0 = MMHyperR3ToR0(PDMDevHlpGetVM(pBus->CTX_SUFF(pDevIns)), pBus);
1816	pPciDev->Int.s.pBusRC = MMHyperR3ToRC(PDMDevHlpGetVM(pBus->CTX_SUFF(pDevIns)), pBus);
1817	pPciDev->Int.s.pfnConfigRead = pci_default_read_config;
1818	pPciDev->Int.s.pfnConfigWrite = pci_default_write_config;
1819	pBus->devices[iDev] = pPciDev;
1820	if (pPciDev->Int.s.fPciToPciBridge)
1821	{
1822	AssertMsg(pBus->cBridges < RT_ELEMENTS(pBus->devices), ("Number of bridges exceeds the number of possible devices on the bus\n"));
1823	AssertMsg(pPciDev->Int.s.pfnBridgeConfigRead && pPciDev->Int.s.pfnBridgeConfigWrite,
1824	("device is a bridge but does not implement read/write functions\n"));
1825	pBus->papBridgesR3[pBus->cBridges] = pPciDev;
1826	pBus->cBridges++;
1827	}
1828
1829	Log(("PCI: Registered device %d function %d (%#x) '%s'.\n",
1830	iDev >> 3, iDev & 7, 0x80000000 \| (iDev << 8), pszName));
1831
1832	return VINF_SUCCESS;
1833	}
1834
1835
1836	/**
1837	* Registers the device with the default PCI bus.
1838	*
1839	* @returns VBox status code.
1840	* @param pDevIns Device instance of the PCI Bus.
1841	* @param pPciDev The PCI device structure.
1842	* Any PCI enabled device must keep this in it's instance data!
1843	* Fill in the PCI data config before registration, please.
1844	* @param pszName Pointer to device name (permanent, readonly). For debugging, not unique.
1845	* @param iDev The PCI device number. Use a negative value for auto assigning one.
1846	*/
1847	static DECLCALLBACK(int) pciRegister(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, const char *pszName, int iDev)
1848	{
1849	PPCIBUS pBus = DEVINS_2_PCIBUS(pDevIns);
1850
1851	/*
1852	* Check input.
1853	*/
1854	if ( !pszName
1855	\|\| !pPciDev
1856	\|\| iDev >= (int)RT_ELEMENTS(pBus->devices)
1857	\|\| (iDev >= 0 && iDev <= 8))
1858	{
1859	AssertMsgFailed(("Invalid argument! pszName=%s pPciDev=%p iDev=%d\n", pszName, pPciDev, iDev));
1860	return VERR_INVALID_PARAMETER;
1861	}
1862
1863	/*
1864	* Register the device.
1865	*/
1866	return pciRegisterInternal(pBus, iDev, pPciDev, pszName);
1867	}
1868
1869
1870	static DECLCALLBACK(int) pciIORegionRegister(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iRegion, uint32_t cbRegion, PCIADDRESSSPACE enmType, PFNPCIIOREGIONMAP pfnCallback)
1871	{
1872	/*
1873	* Validate.
1874	*/
1875	AssertMsgReturn( enmType == PCI_ADDRESS_SPACE_MEM
1876	\|\| enmType == PCI_ADDRESS_SPACE_IO
1877	\|\| enmType == PCI_ADDRESS_SPACE_MEM_PREFETCH,
1878	("Invalid enmType=%#x? Or was this a bitmask after all...\n", enmType),
1879	VERR_INVALID_PARAMETER);
1880	AssertMsgReturn((unsigned)iRegion < PCI_NUM_REGIONS,
1881	("Invalid iRegion=%d PCI_NUM_REGIONS=%d\n", iRegion, PCI_NUM_REGIONS),
1882	VERR_INVALID_PARAMETER);
1883	int iLastSet = ASMBitLastSetU32(cbRegion);
1884	AssertMsgReturn( iLastSet != 0
1885	&& RT_BIT_32(iLastSet - 1) == cbRegion,
1886	("Invalid cbRegion=%#x iLastSet=%#x (not a power of 2 or 0)\n", cbRegion, iLastSet),
1887	VERR_INVALID_PARAMETER);
1888
1889	/*
1890	* Register the I/O region.
1891	*/
1892	PPCIIOREGION pRegion = &pPciDev->Int.s.aIORegions[iRegion];
1893	pRegion->addr = ~0U;
1894	pRegion->size = cbRegion;
1895	pRegion->type = enmType;
1896	pRegion->map_func = pfnCallback;
1897
1898	/* Set type in the config space. */
1899	uint32_t u32Address = 0x10 + iRegion * 4;
1900	uint32_t u32Value = (enmType == PCI_ADDRESS_SPACE_MEM_PREFETCH ? (1 << 3) : 0)
1901	\| (enmType == PCI_ADDRESS_SPACE_IO ? 1 : 0);
1902	(uint32_t )(pPciDev->config + u32Address) = RT_H2LE_U32(u32Value);
1903
1904	return VINF_SUCCESS;
1905	}
1906
1907
1908	/**
1909	* @copydoc PDMPCIBUSREG::pfnSetConfigCallbacksR3
1910	*/
1911	static DECLCALLBACK(void) pciSetConfigCallbacks(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PFNPCICONFIGREAD pfnRead, PPFNPCICONFIGREAD ppfnReadOld,
1912	PFNPCICONFIGWRITE pfnWrite, PPFNPCICONFIGWRITE ppfnWriteOld)
1913	{
1914	if (ppfnReadOld)
1915	*ppfnReadOld = pPciDev->Int.s.pfnConfigRead;
1916	pPciDev->Int.s.pfnConfigRead = pfnRead;
1917
1918	if (ppfnWriteOld)
1919	*ppfnWriteOld = pPciDev->Int.s.pfnConfigWrite;
1920	pPciDev->Int.s.pfnConfigWrite = pfnWrite;
1921	}
1922
1923
1924	/**
1925	* Called to perform the job of the bios.
1926	*
1927	* @returns VBox status.
1928	* @param pDevIns Device instance of the first bus.
1929	*/
1930	static DECLCALLBACK(int) pciFakePCIBIOS(PPDMDEVINS pDevIns)
1931	{
1932	int rc;
1933	unsigned i;
1934	uint8_t elcr[2] = {0, 0};
1935	PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
1936	PVM pVM = PDMDevHlpGetVM(pDevIns);
1937	Assert(pVM);
1938
1939	/*
1940	* Set the start addresses.
1941	*/
1942	pGlobals->pci_bios_io_addr = 0xd000;
1943	pGlobals->pci_bios_mem_addr = UINT32_C(0xf0000000);
1944	pGlobals->uBus = 0;
1945
1946	/*
1947	* Activate IRQ mappings.
1948	*/
1949	for (i = 0; i < 4; i++)
1950	{
1951	uint8_t irq = pci_irqs[i];
1952	/* Set to trigger level. */
1953	elcr[irq >> 3] \|= (1 << (irq & 7));
1954	/* Activate irq remapping in PIIX3. */
1955	pci_config_writeb(pGlobals, 0, pGlobals->PIIX3State.dev.devfn, 0x60 + i, irq);
1956	}
1957
1958	/* Tell to the PIC. */
1959	VBOXSTRICTRC rcStrict = IOMIOPortWrite(pVM, 0x4d0, elcr[0], sizeof(uint8_t));
1960	if (rcStrict == VINF_SUCCESS)
1961	rcStrict = IOMIOPortWrite(pVM, 0x4d1, elcr[1], sizeof(uint8_t));
1962	if (rcStrict != VINF_SUCCESS)
1963	{
1964	AssertMsgFailed(("Writing to PIC failed! rcStrict=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
1965	return RT_SUCCESS(rcStrict) ? VERR_INTERNAL_ERROR : VBOXSTRICTRC_VAL(rcStrict);
1966	}
1967
1968	/*
1969	* Init the devices.
1970	*/
1971	for (i = 0; i < 256; i++)
1972	{
1973	uint8_t aBridgePositions[256];
1974
1975	memset(aBridgePositions, 0, sizeof(aBridgePositions));
1976	Log2(("PCI: Initializing device %d (%#x)\n",
1977	i, 0x80000000 \| (i << 8)));
1978	pci_bios_init_device(pGlobals, 0, i, 0, aBridgePositions);
1979	}
1980
1981	return VINF_SUCCESS;
1982	}
1983
1984	/**
1985	* @copydoc FNPDMDEVRELOCATE
1986	*/
1987	static DECLCALLBACK(void) pciRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
1988	{
1989	PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
1990	PPCIBUS pBus = &pGlobals->PciBus;
1991	pGlobals->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
1992
1993	pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
1994	pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
1995
1996	/* Relocate RC pointers for the attached pci devices. */
1997	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->devices); i++)
1998	{
1999	if (pBus->devices[i])
2000	pBus->devices[i]->Int.s.pBusRC += offDelta;
2001	}
2002	}
2003
2004
2005	/**
2006	* Construct a host to PCI Bus device instance for a VM.
2007	*
2008	* @returns VBox status.
2009	* @param pDevIns The device instance data.
2010	* If the registration structure is needed, pDevIns->pDevReg points to it.
2011	* @param iInstance Instance number. Use this to figure out which registers and such to use.
2012	* The device number is also found in pDevIns->iInstance, but since it's
2013	* likely to be freqently used PDM passes it as parameter.
2014	* @param pCfgHandle Configuration node handle for the device. Use this to obtain the configuration
2015	* of the device instance. It's also found in pDevIns->pCfgHandle, but like
2016	* iInstance it's expected to be used a bit in this function.
2017	*/
2018	static DECLCALLBACK(int) pciConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfgHandle)
2019	{
2020	int rc;
2021	Assert(iInstance == 0);
2022
2023	/*
2024	* Validate and read configuration.
2025	*/
2026	if (!CFGMR3AreValuesValid(pCfgHandle, "IOAPIC\0" "GCEnabled\0" "R0Enabled\0"))
2027	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
2028
2029	/* query whether we got an IOAPIC */
2030	bool fUseIoApic;
2031	rc = CFGMR3QueryBoolDef(pCfgHandle, "IOAPIC", &fUseIoApic, false);
2032	if (RT_FAILURE(rc))
2033	return PDMDEV_SET_ERROR(pDevIns, rc,
2034	N_("Configuration error: Failed to query boolean value \"IOAPIC\""));
2035
2036	/* check if RC code is enabled. */
2037	bool fGCEnabled;
2038	rc = CFGMR3QueryBoolDef(pCfgHandle, "GCEnabled", &fGCEnabled, true);
2039	if (RT_FAILURE(rc))
2040	return PDMDEV_SET_ERROR(pDevIns, rc,
2041	N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
2042
2043	/* check if R0 code is enabled. */
2044	bool fR0Enabled;
2045	rc = CFGMR3QueryBoolDef(pCfgHandle, "R0Enabled", &fR0Enabled, true);
2046	if (RT_FAILURE(rc))
2047	return PDMDEV_SET_ERROR(pDevIns, rc,
2048	N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
2049	Log(("PCI: fUseIoApic=%RTbool fGCEnabled=%RTbool fR0Enabled=%RTbool\n", fUseIoApic, fGCEnabled, fR0Enabled));
2050
2051	/*
2052	* Init data and register the PCI bus.
2053	*/
2054	PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
2055	pGlobals->pci_bios_io_addr = 0xc000;
2056	pGlobals->pci_bios_mem_addr = 0xf0000000;
2057	memset((void *)&pGlobals->pci_irq_levels, 0, sizeof(pGlobals->pci_irq_levels));
2058	pGlobals->fUseIoApic = fUseIoApic;
2059	memset((void *)&pGlobals->pci_apic_irq_levels, 0, sizeof(pGlobals->pci_apic_irq_levels));
2060
2061	pGlobals->pDevInsR3 = pDevIns;
2062	pGlobals->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2063	pGlobals->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2064
2065	pGlobals->PciBus.pDevInsR3 = pDevIns;
2066	pGlobals->PciBus.pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2067	pGlobals->PciBus.pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2068	pGlobals->PciBus.papBridgesR3 = (PPCIDEVICE )PDMDevHlpMMHeapAllocZ(pDevIns, sizeof(PPCIDEVICE) RT_ELEMENTS(pGlobals->PciBus.devices));
2069
2070	PDMPCIBUSREG PciBusReg;
2071	PPCIBUS pBus = &pGlobals->PciBus;
2072	PciBusReg.u32Version = PDM_PCIBUSREG_VERSION;
2073	PciBusReg.pfnRegisterR3 = pciRegister;
2074	PciBusReg.pfnIORegionRegisterR3 = pciIORegionRegister;
2075	PciBusReg.pfnSetConfigCallbacksR3 = pciSetConfigCallbacks;
2076	PciBusReg.pfnSetIrqR3 = pciSetIrq;
2077	PciBusReg.pfnSaveExecR3 = pciGenericSaveExec;
2078	PciBusReg.pfnLoadExecR3 = pciGenericLoadExec;
2079	PciBusReg.pfnFakePCIBIOSR3 = pciFakePCIBIOS;
2080	PciBusReg.pszSetIrqRC = fGCEnabled ? "pciSetIrq" : NULL;
2081	PciBusReg.pszSetIrqR0 = fR0Enabled ? "pciSetIrq" : NULL;
2082	rc = pDevIns->pDevHlpR3->pfnPCIBusRegister(pDevIns, &PciBusReg, &pBus->pPciHlpR3);
2083	if (RT_FAILURE(rc))
2084	return PDMDEV_SET_ERROR(pDevIns, rc,
2085	N_("Failed to register ourselves as a PCI Bus"));
2086	if (pBus->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
2087	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
2088	N_("PCI helper version mismatch; got %#x expected %#x"),
2089	pBus->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION);
2090
2091	pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
2092	pBus->pPciHlpR0 = pBus->pPciHlpR3->pfnGetR0Helpers(pDevIns);
2093
2094	/*
2095	* Fill in PCI configs and add them to the bus.
2096	*/
2097	/* i440FX */
2098	PCIDevSetVendorId( &pBus->PciDev, 0x8086); /* Intel */
2099	PCIDevSetDeviceId( &pBus->PciDev, 0x1237);
2100	PCIDevSetRevisionId(&pBus->PciDev, 0x02);
2101	PCIDevSetClassSub( &pBus->PciDev, 0x00); /* host2pci */
2102	PCIDevSetClassBase( &pBus->PciDev, 0x06); /* PCI_bridge */
2103	PCIDevSetHeaderType(&pBus->PciDev, 0x00);
2104
2105	pBus->PciDev.pDevIns = pDevIns;
2106	pBus->PciDev.Int.s.fRequestedDevFn= true;
2107	pciRegisterInternal(pBus, 0, &pBus->PciDev, "i440FX");
2108
2109	/* PIIX3 */
2110	PCIDevSetVendorId( &pGlobals->PIIX3State.dev, 0x8086); /* Intel */
2111	PCIDevSetDeviceId( &pGlobals->PIIX3State.dev, 0x7000); /* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */
2112	PCIDevSetClassSub( &pGlobals->PIIX3State.dev, 0x01); /* PCI_ISA */
2113	PCIDevSetClassBase( &pGlobals->PIIX3State.dev, 0x06); /* PCI_bridge */
2114	PCIDevSetHeaderType(&pGlobals->PIIX3State.dev, 0x80); /* PCI_multifunction, generic */
2115
2116	pGlobals->PIIX3State.dev.pDevIns = pDevIns;
2117	pGlobals->PIIX3State.dev.Int.s.fRequestedDevFn= true;
2118	pciRegisterInternal(pBus, 8, &pGlobals->PIIX3State.dev, "PIIX3");
2119	piix3_reset(&pGlobals->PIIX3State);
2120
2121	pBus->iDevSearch = 16;
2122
2123	/*
2124	* Register I/O ports and save state.
2125	*/
2126	rc = PDMDevHlpIOPortRegister(pDevIns, 0x0cf8, 1, NULL, pciIOPortAddressWrite, pciIOPortAddressRead, NULL, NULL, "i440FX (PCI)");
2127	if (RT_FAILURE(rc))
2128	return rc;
2129	rc = PDMDevHlpIOPortRegister(pDevIns, 0x0cfc, 4, NULL, pciIOPortDataWrite, pciIOPortDataRead, NULL, NULL, "i440FX (PCI)");
2130	if (RT_FAILURE(rc))
2131	return rc;
2132	if (fGCEnabled)
2133	{
2134	rc = PDMDevHlpIOPortRegisterGC(pDevIns, 0x0cf8, 1, NIL_RTGCPTR, "pciIOPortAddressWrite", "pciIOPortAddressRead", NULL, NULL, "i440FX (PCI)");
2135	if (RT_FAILURE(rc))
2136	return rc;
2137	rc = PDMDevHlpIOPortRegisterGC(pDevIns, 0x0cfc, 4, NIL_RTGCPTR, "pciIOPortDataWrite", "pciIOPortDataRead", NULL, NULL, "i440FX (PCI)");
2138	if (RT_FAILURE(rc))
2139	return rc;
2140	}
2141	if (fR0Enabled)
2142	{
2143	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x0cf8, 1, NIL_RTR0PTR, "pciIOPortAddressWrite", "pciIOPortAddressRead", NULL, NULL, "i440FX (PCI)");
2144	if (RT_FAILURE(rc))
2145	return rc;
2146	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x0cfc, 4, NIL_RTR0PTR, "pciIOPortDataWrite", "pciIOPortDataRead", NULL, NULL, "i440FX (PCI)");
2147	if (RT_FAILURE(rc))
2148	return rc;
2149	}
2150
2151	rc = PDMDevHlpSSMRegisterEx(pDevIns, VBOX_PCI_SAVED_STATE_VERSION, sizeof(pBus) + 16128, "pgm",
2152	NULL, NULL, NULL,
2153	NULL, pciR3SaveExec, NULL,
2154	pciR3LoadPrep, pciR3LoadExec, NULL);
2155	if (RT_FAILURE(rc))
2156	return rc;
2157
2158	return VINF_SUCCESS;
2159	}
2160
2161
2162	/**
2163	* The device registration structure.
2164	*/
2165	const PDMDEVREG g_DevicePCI =
2166	{
2167	/* u32Version */
2168	PDM_DEVREG_VERSION,
2169	/* szDeviceName */
2170	"pci",
2171	/* szRCMod */
2172	"VBoxDDGC.gc",
2173	/* szR0Mod */
2174	"VBoxDDR0.r0",
2175	/* pszDescription */
2176	"i440FX PCI bridge and PIIX3 ISA bridge.",
2177	/* fFlags */
2178	PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
2179	/* fClass */
2180	PDM_DEVREG_CLASS_BUS_PCI \| PDM_DEVREG_CLASS_BUS_ISA,
2181	/* cMaxInstances */
2182	1,
2183	/* cbInstance */
2184	sizeof(PCIGLOBALS),
2185	/* pfnConstruct */
2186	pciConstruct,
2187	/* pfnDestruct */
2188	NULL,
2189	/* pfnRelocate */
2190	pciRelocate,
2191	/* pfnIOCtl */
2192	NULL,
2193	/* pfnPowerOn */
2194	NULL,
2195	/* pfnReset */
2196	NULL,
2197	/* pfnSuspend */
2198	NULL,
2199	/* pfnResume */
2200	NULL,
2201	/* pfnAttach */
2202	NULL,
2203	/* pfnDetach */
2204	NULL,
2205	/* pfnQueryInterface */
2206	NULL,
2207	/* pfnInitComplete */
2208	NULL,
2209	/* pfnPowerOff */
2210	NULL,
2211	/* pfnSoftReset */
2212	NULL,
2213	/* u32VersionEnd */
2214	PDM_DEVREG_VERSION
2215
2216	};
2217	#endif /* IN_RING3 */
2218
2219	/**
2220	* Set the IRQ for a PCI device on a secondary bus.
2221	*
2222	* @param pDevIns Device instance of the PCI Bus.
2223	* @param pPciDev The PCI device structure.
2224	* @param iIrq IRQ number to set.
2225	* @param iLevel IRQ level.
2226	*/
2227	PDMBOTHCBDECL(void) pcibridgeSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel)
2228	{
2229	/*
2230	* The PCI-to-PCI bridge specification defines how the interrupt pins
2231	* are routed from the secondary to the primary bus (see chapter 9).
2232	* iIrq gives the interrupt pin the pci device asserted.
2233	* We change iIrq here according to the spec and call the SetIrq function
2234	* of our parent passing the device which asserted the interrupt instead of the device of the bridge.
2235	*/
2236	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
2237	int iIrqPinBridge = 0;
2238	uint8_t uDevFnBridge = pPciDev->devfn;
2239
2240	/* Walk the chain until we reach the host bus. */
2241	while (pBus->iBus != 0)
2242	{
2243	uDevFnBridge = pBus->PciDev.devfn;
2244	iIrqPinBridge = ((uDevFnBridge >> 3) + iIrqPinBridge) & 3;
2245	/* Get the parent. */
2246	pBus = pBus->PciDev.Int.s.CTX_SUFF(pBus);
2247	}
2248
2249	AssertMsg(pBus->iBus == 0, ("This is not the host pci bus iBus=%d\n", pBus->iBus));
2250	pciSetIrqInternal(PCIBUS_2_PCIGLOBALS(pBus), uDevFnBridge, pPciDev, iIrqPinBridge, iLevel);
2251	}
2252
2253	#ifdef IN_RING3
2254
2255	static void pcibridgeConfigWrite(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice, uint32_t u32Address, uint32_t u32Value, unsigned cb)
2256	{
2257	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
2258
2259	LogFlowFunc((": pDevIns=%p iBus=%d iDevice=%d u32Address=%u u32Value=%u cb=%d\n", pDevIns, iBus, iDevice, u32Address, u32Value, cb));
2260
2261	/* If the current bus is not the target bus search for the bus which contains the device. */
2262	if (iBus != pBus->PciDev.config[VBOX_PCI_SECONDARY_BUS])
2263	{
2264	PPCIDEVICE pBridgeDevice = pciFindBridge(pBus, iBus);
2265	if (pBridgeDevice)
2266	{
2267	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigWrite);
2268	pBridgeDevice->Int.s.pfnBridgeConfigWrite(pBridgeDevice->pDevIns, iBus, iDevice, u32Address, u32Value, cb);
2269	}
2270	}
2271	else
2272	{
2273	/* This is the target bus, pass the write to the device. */
2274	PPCIDEVICE pPciDev = pBus->devices[iDevice];
2275	if (pPciDev)
2276	{
2277	Log(("%s: %s: addr=%02x val=%08x len=%d\n", __FUNCTION__, pPciDev->name, u32Address, u32Value, cb));
2278	pPciDev->Int.s.pfnConfigWrite(pPciDev, u32Address, u32Value, cb);
2279	}
2280	}
2281	}
2282
2283	static uint32_t pcibridgeConfigRead(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice, uint32_t u32Address, unsigned cb)
2284	{
2285	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
2286	uint32_t u32Value = 0xffffffff; /* Return value in case there is no device. */
2287
2288	LogFlowFunc((": pDevIns=%p iBus=%d iDevice=%d u32Address=%u cb=%d\n", pDevIns, iBus, iDevice, u32Address, cb));
2289
2290	/* If the current bus is not the target bus search for the bus which contains the device. */
2291	if (iBus != pBus->PciDev.config[VBOX_PCI_SECONDARY_BUS])
2292	{
2293	PPCIDEVICE pBridgeDevice = pciFindBridge(pBus, iBus);
2294	if (pBridgeDevice)
2295	{
2296	AssertPtr( pBridgeDevice->Int.s.pfnBridgeConfigRead);
2297	u32Value = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->pDevIns, iBus, iDevice, u32Address, cb);
2298	}
2299	}
2300	else
2301	{
2302	/* This is the target bus, pass the read to the device. */
2303	PPCIDEVICE pPciDev = pBus->devices[iDevice];
2304	if (pPciDev)
2305	{
2306	u32Value = pPciDev->Int.s.pfnConfigRead(pPciDev, u32Address, cb);
2307	Log(("%s: %s: u32Address=%02x u32Value=%08x cb=%d\n", __FUNCTION__, pPciDev->name, u32Address, u32Value, cb));
2308	}
2309	}
2310
2311	return u32Value;
2312	}
2313
2314	/**
2315	* Saves a state of a PCI bridge device.
2316	*
2317	* @returns VBox status code.
2318	* @param pDevIns The device instance.
2319	* @param pPciDev Pointer to PCI device.
2320	* @param pSSMHandle The handle to save the state to.
2321	*/
2322	static DECLCALLBACK(int) pcibridgeR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle)
2323	{
2324	PPCIBUS pThis = PDMINS_2_DATA(pDevIns, PPCIBUS);
2325	return pciR3CommonSaveExec(pThis, pSSMHandle);
2326	}
2327
2328
2329	/**
2330	* Prepares a state load.
2331	*
2332	* This will disable all the device so that the I/O regions gets unmapped.
2333	*
2334	* @returns VINF_SUCCESS
2335	* @param pDevIns The device instance.
2336	* @param pSSMHandle The saved state handle.
2337	*/
2338	static DECLCALLBACK(int) pcibridgeR3LoadPrep(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle)
2339	{
2340	PPCIBUS pThis = PDMINS_2_DATA(pDevIns, PPCIBUS);
2341	return pciR3CommonLoadPrep(pThis);
2342	}
2343
2344
2345	/**
2346	* Loads a saved PCI bridge device state.
2347	*
2348	* @returns VBox status code.
2349	* @param pDevIns The device instance.
2350	* @param pSSMHandle The handle to the saved state.
2351	* @param uVersion The data unit version number.
2352	* @param uPass The data pass.
2353	*/
2354	static DECLCALLBACK(int) pcibridgeR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle, uint32_t uVersion, uint32_t uPass)
2355	{
2356	PPCIBUS pThis = PDMINS_2_DATA(pDevIns, PPCIBUS);
2357	if (uVersion > VBOX_PCI_SAVED_STATE_VERSION)
2358	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2359	return pciR3CommonLoadExec(pThis, pSSMHandle, uVersion, uPass);
2360	}
2361
2362	/**
2363	* @copydoc FNPDMDEVRESET
2364	*/
2365	static DECLCALLBACK(void) pcibridgeReset(PPDMDEVINS pDevIns)
2366	{
2367	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
2368
2369	/* Reset config space to default values. */
2370	pBus->PciDev.config[VBOX_PCI_PRIMARY_BUS] = 0;
2371	pBus->PciDev.config[VBOX_PCI_SECONDARY_BUS] = 0;
2372	pBus->PciDev.config[VBOX_PCI_SUBORDINATE_BUS] = 0;
2373	}
2374
2375	/**
2376	* @copydoc FNPDMDEVRELOCATE
2377	*/
2378	static DECLCALLBACK(void) pcibridgeRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
2379	{
2380	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
2381	pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2382
2383	/* Relocate RC pointers for the attached pci devices. */
2384	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->devices); i++)
2385	{
2386	if (pBus->devices[i])
2387	pBus->devices[i]->Int.s.pBusRC += offDelta;
2388	}
2389	}
2390
2391	/**
2392	* Registers the device with the default PCI bus.
2393	*
2394	* @returns VBox status code.
2395	* @param pDevIns Device instance of the PCI Bus.
2396	* @param pPciDev The PCI device structure.
2397	* Any PCI enabled device must keep this in it's instance data!
2398	* Fill in the PCI data config before registration, please.
2399	* @param pszName Pointer to device name (permanent, readonly). For debugging, not unique.
2400	* @param iDev The PCI device number. Use a negative value for auto assigning one.
2401	*/
2402	static DECLCALLBACK(int) pcibridgeRegister(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, const char *pszName, int iDev)
2403	{
2404	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
2405
2406	/*
2407	* Check input.
2408	*/
2409	if ( !pszName
2410	\|\| !pPciDev
2411	\|\| iDev >= (int)RT_ELEMENTS(pBus->devices))
2412	{
2413	AssertMsgFailed(("Invalid argument! pszName=%s pPciDev=%p iDev=%d\n", pszName, pPciDev, iDev));
2414	return VERR_INVALID_PARAMETER;
2415	}
2416
2417	/*
2418	* Register the device.
2419	*/
2420	return pciRegisterInternal(pBus, iDev, pPciDev, pszName);
2421	}
2422
2423	/**
2424	* Construct a PCI bridge device instance for a VM.
2425	*
2426	* @returns VBox status.
2427	* @param pDevIns The device instance data.
2428	* If the registration structure is needed, pDevIns->pDevReg points to it.
2429	* @param iInstance Instance number. Use this to figure out which registers and such to use.
2430	* The device number is also found in pDevIns->iInstance, but since it's
2431	* likely to be freqently used PDM passes it as parameter.
2432	* @param pCfgHandle Configuration node handle for the device. Use this to obtain the configuration
2433	* of the device instance. It's also found in pDevIns->pCfgHandle, but like
2434	* iInstance it's expected to be used a bit in this function.
2435	*/
2436	static DECLCALLBACK(int) pcibridgeConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfgHandle)
2437	{
2438	int rc;
2439
2440	/*
2441	* Validate and read configuration.
2442	*/
2443	if (!CFGMR3AreValuesValid(pCfgHandle, "GCEnabled\0" "R0Enabled\0"))
2444	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
2445
2446	/* check if RC code is enabled. */
2447	bool fGCEnabled;
2448	rc = CFGMR3QueryBoolDef(pCfgHandle, "GCEnabled", &fGCEnabled, true);
2449	if (RT_FAILURE(rc))
2450	return PDMDEV_SET_ERROR(pDevIns, rc,
2451	N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
2452
2453	/* check if R0 code is enabled. */
2454	bool fR0Enabled;
2455	rc = CFGMR3QueryBoolDef(pCfgHandle, "R0Enabled", &fR0Enabled, true);
2456	if (RT_FAILURE(rc))
2457	return PDMDEV_SET_ERROR(pDevIns, rc,
2458	N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
2459	Log(("PCI: fGCEnabled=%RTbool fR0Enabled=%RTbool\n", fGCEnabled, fR0Enabled));
2460
2461	/*
2462	* Init data and register the PCI bus.
2463	*/
2464	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
2465	pBus->pDevInsR3 = pDevIns;
2466	pBus->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2467	pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2468	pBus->papBridgesR3 = (PPCIDEVICE )PDMDevHlpMMHeapAllocZ(pDevIns, sizeof(PPCIDEVICE) RT_ELEMENTS(pBus->devices));
2469
2470	PDMPCIBUSREG PciBusReg;
2471	PciBusReg.u32Version = PDM_PCIBUSREG_VERSION;
2472	PciBusReg.pfnRegisterR3 = pcibridgeRegister;
2473	PciBusReg.pfnIORegionRegisterR3 = pciIORegionRegister;
2474	PciBusReg.pfnSetConfigCallbacksR3 = pciSetConfigCallbacks;
2475	PciBusReg.pfnSetIrqR3 = pcibridgeSetIrq;
2476	PciBusReg.pfnSaveExecR3 = pciGenericSaveExec;
2477	PciBusReg.pfnLoadExecR3 = pciGenericLoadExec;
2478	PciBusReg.pfnFakePCIBIOSR3 = NULL; /* Only needed for the first bus. */
2479	PciBusReg.pszSetIrqRC = fGCEnabled ? "pcibridgeSetIrq" : NULL;
2480	PciBusReg.pszSetIrqR0 = fR0Enabled ? "pcibridgeSetIrq" : NULL;
2481	rc = pDevIns->pDevHlpR3->pfnPCIBusRegister(pDevIns, &PciBusReg, &pBus->pPciHlpR3);
2482	if (RT_FAILURE(rc))
2483	return PDMDEV_SET_ERROR(pDevIns, rc,
2484	N_("Failed to register ourselves as a PCI Bus"));
2485	if (pBus->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
2486	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
2487	N_("PCI helper version mismatch; got %#x expected %#x"),
2488	pBus->pPciHlpR3->u32Version, PDM_PCIHLPR3_VERSION);
2489
2490	pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
2491	pBus->pPciHlpR0 = pBus->pPciHlpR3->pfnGetR0Helpers(pDevIns);
2492
2493	/*
2494	* Fill in PCI configs and add them to the bus.
2495	*/
2496	PCIDevSetVendorId( &pBus->PciDev, 0x8086); /* Intel */
2497	PCIDevSetDeviceId( &pBus->PciDev, 0x2448); /* 82801 Mobile PCI bridge. */
2498	PCIDevSetRevisionId(&pBus->PciDev, 0xf2);
2499	PCIDevSetClassSub( &pBus->PciDev, 0x04); /* pci2pci */
2500	PCIDevSetClassBase( &pBus->PciDev, 0x06); /* PCI_bridge */
2501	PCIDevSetClassProg( &pBus->PciDev, 0x01); /* Supports subtractive decoding. */
2502	PCIDevSetHeaderType(&pBus->PciDev, 0x01); /* Single function device which adheres to the PCI-to-PCI bridge spec. */
2503	PCIDevSetCommand( &pBus->PciDev, 0x00);
2504	PCIDevSetStatus( &pBus->PciDev, 0x20); /* 66MHz Capable. */
2505	PCIDevSetInterruptLine(&pBus->PciDev, 0x00); /* This device does not assert interrupts. */
2506
2507	/*
2508	* This device does not generate interrupts. Interrupt delivery from
2509	* devices attached to the bus is unaffected.
2510	*/
2511	PCIDevSetInterruptPin (&pBus->PciDev, 0x00);
2512
2513	pBus->PciDev.pDevIns = pDevIns;
2514	pBus->PciDev.Int.s.fPciToPciBridge = true;
2515	pBus->PciDev.Int.s.pfnBridgeConfigRead = pcibridgeConfigRead;
2516	pBus->PciDev.Int.s.pfnBridgeConfigWrite = pcibridgeConfigWrite;
2517
2518	/*
2519	* Register this PCI bridge. The called function will take care on which bus we will get registered.
2520	*/
2521	rc = PDMDevHlpPCIRegister (pDevIns, &pBus->PciDev);
2522	if (RT_FAILURE(rc))
2523	return rc;
2524
2525	pBus->iDevSearch = 0;
2526	/*
2527	* The iBus property doesn't really represent the bus number
2528	* because the guest and the BIOS can choose different bus numbers
2529	* for them.
2530	* The bus number is mainly for the setIrq function to indicate
2531	* when the host bus is reached which will have iBus = 0.
2532	* Thathswhy the + 1.
2533	*/
2534	pBus->iBus = iInstance + 1;
2535
2536	/*
2537	* Register SSM handlers. We use the same saved state version as for the host bridge
2538	* to make changes easier.
2539	*/
2540	rc = PDMDevHlpSSMRegisterEx(pDevIns, VBOX_PCI_SAVED_STATE_VERSION, sizeof(pBus) + 16128, "pgm",
2541	NULL, NULL, NULL,
2542	NULL, pcibridgeR3SaveExec, NULL,
2543	pcibridgeR3LoadPrep, pcibridgeR3LoadExec, NULL);
2544	if (RT_FAILURE(rc))
2545	return rc;
2546
2547	return VINF_SUCCESS;
2548	}
2549
2550	/**
2551	* The device registration structure
2552	* for the PCI-to-PCI bridge.
2553	*/
2554	const PDMDEVREG g_DevicePCIBridge =
2555	{
2556	/* u32Version */
2557	PDM_DEVREG_VERSION,
2558	/* szDeviceName */
2559	"pcibridge",
2560	/* szRCMod */
2561	"VBoxDDGC.gc",
2562	/* szR0Mod */
2563	"VBoxDDR0.r0",
2564	/* pszDescription */
2565	"82801 Mobile PCI to PCI bridge",
2566	/* fFlags */
2567	PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
2568	/* fClass */
2569	PDM_DEVREG_CLASS_BUS_PCI,
2570	/* cMaxInstances */
2571	~0,
2572	/* cbInstance */
2573	sizeof(PCIBUS),
2574	/* pfnConstruct */
2575	pcibridgeConstruct,
2576	/* pfnDestruct */
2577	NULL,
2578	/* pfnRelocate */
2579	pcibridgeRelocate,
2580	/* pfnIOCtl */
2581	NULL,
2582	/* pfnPowerOn */
2583	NULL,
2584	/* pfnReset */
2585	pcibridgeReset,
2586	/* pfnSuspend */
2587	NULL,
2588	/* pfnResume */
2589	NULL,
2590	/* pfnAttach */
2591	NULL,
2592	/* pfnDetach */
2593	NULL,
2594	/* pfnQueryInterface */
2595	NULL,
2596	/* pfnInitComplete */
2597	NULL,
2598	/* pfnPowerOff */
2599	NULL,
2600	/* pfnSoftReset */
2601	NULL,
2602	/* u32VersionEnd */
2603	PDM_DEVREG_VERSION
2604	};
2605
2606	#endif /* IN_RING3 */
2607	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */

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source: vbox/trunk/src/VBox/Devices/Bus/DevPCI.cpp@ 23973

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