DevPCI.cpp@ 28185

Last change on this file since 28185 was 27079, checked in by vboxsync, 15 years ago
Added comments about PCI/ACPI/IOAPIC interrupt routing backdoor.
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 93.8 KB

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1	/* $Id: DevPCI.cpp 27079 2010-03-05 12:19:45Z vboxsync $ */
2	/** @file
3	* DevPCI - PCI BUS Device.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	* --------------------------------------------------------------------
21	*
22	* This code is based on:
23	*
24	* QEMU PCI bus manager
25	*
26	* Copyright (c) 2004 Fabrice Bellard
27	*
28	* Permission is hereby granted, free of charge, to any person obtaining a copy
29	* of this software and associated documentation files (the "Software"), to deal
30	* in the Software without restriction, including without limitation the rights
31	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
32	* copies of the Software, and to permit persons to whom the Software is
33	* furnished to do so, subject to the following conditions:
34	*
35	* The above copyright notice and this permission notice shall be included in
36	* all copies or substantial portions of the Software.
37	*
38	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
39	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
40	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
41	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
42	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
43	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
44	* THE SOFTWARE.
45	*/
46
47	/*******************************************************************************
48	* Header Files *
49	*******************************************************************************/
50	#define LOG_GROUP LOG_GROUP_DEV_PCI
51	/* Hack to get PCIDEVICEINT declare at the right point - include "PCIInternal.h". */
52	#define PCI_INCLUDE_PRIVATE
53	#include <VBox/pci.h>
54	#include <VBox/pdmdev.h>
55	#include <iprt/assert.h>
56	#include <iprt/string.h>
57
58	#include "../Builtins.h"
59
60
61	/*******************************************************************************
62	* Structures and Typedefs *
63	*******************************************************************************/
64	/**
65	* PIIX3 ISA Bridge state.
66	*/
67	typedef struct PIIX3State
68	{
69	/** The PCI device of the bridge. */
70	PCIDEVICE dev;
71	} PIIX3State, PIIX3, *PPIIX3;
72
73	/**
74	* PCI Bus instance.
75	*/
76	typedef struct PCIBus
77	{
78	/** Bus number. */
79	int32_t iBus;
80	/** Start device number. */
81	int32_t iDevSearch;
82	/** Number of bridges attached to the bus. */
83	uint32_t cBridges;
84
85	uint32_t Alignment0;
86
87	/** Array of PCI devices. */
88	R3PTRTYPE(PPCIDEVICE) devices[256];
89	/** Array of bridges attached to the bus. */
90	R3PTRTYPE(PPCIDEVICE *) papBridgesR3;
91
92	/** R3 pointer to the device instance. */
93	PPDMDEVINSR3 pDevInsR3;
94	/** Pointer to the PCI R3 helpers. */
95	PCPDMPCIHLPR3 pPciHlpR3;
96
97	/** R0 pointer to the device instance. */
98	PPDMDEVINSR0 pDevInsR0;
99	/** Pointer to the PCI R0 helpers. */
100	PCPDMPCIHLPR0 pPciHlpR0;
101
102	/** RC pointer to the device instance. */
103	PPDMDEVINSRC pDevInsRC;
104	/** Pointer to the PCI RC helpers. */
105	PCPDMPCIHLPRC pPciHlpRC;
106
107	/** The PCI device for the PCI bridge. */
108	PCIDEVICE PciDev;
109
110	} PCIBUS;
111	/** Pointer to a PCIBUS instance. */
112	typedef PCIBUS *PPCIBUS;
113	typedef PCIBUS PCIBus;
114
115	/** @def PCI_IRQ_PINS
116	* Number of pins for interrupts (PIRQ#0...PIRQ#3)
117	*/
118	#define PCI_IRQ_PINS 4
119
120	/** @def PCI_APIC_IRQ_PINS
121	* Number of pins for interrupts if the APIC is used.
122	*/
123	#define PCI_APIC_IRQ_PINS 8
124
125	/**
126	* PCI Globals - This is the host-to-pci bridge and the root bus.
127	*/
128	typedef struct PCIGLOBALS
129	{
130	/** Irq levels for the four PCI Irqs.
131	* These count how many devices asserted
132	* the IRQ line. If greater 0 an IRQ is sent to the guest.
133	* If it drops to 0 the IRQ is deasserted.
134	*/
135	volatile uint32_t pci_irq_levels[PCI_IRQ_PINS];
136
137	#if 1 /* Will be moved into the BIOS soon. */
138	/** The next I/O port address which the PCI BIOS will use. */
139	uint32_t pci_bios_io_addr;
140	/** The next MMIO address which the PCI BIOS will use. */
141	uint32_t pci_bios_mem_addr;
142	/** Actual bus number. */
143	uint8_t uBus;
144	#endif
145
146	/** I/O APIC usage flag */
147	bool fUseIoApic;
148	/** I/O APIC irq levels */
149	volatile uint32_t pci_apic_irq_levels[PCI_APIC_IRQ_PINS];
150	/** ACPI IRQ level */
151	uint32_t acpi_irq_level;
152	/** ACPI PIC IRQ */
153	int acpi_irq;
154	/** Config register. */
155	uint32_t uConfigReg;
156
157	/** R3 pointer to the device instance. */
158	PPDMDEVINSR3 pDevInsR3;
159	/** R0 pointer to the device instance. */
160	PPDMDEVINSR0 pDevInsR0;
161	/** RC pointer to the device instance. */
162	PPDMDEVINSRC pDevInsRC;
163
164	#if HC_ARCH_BITS == 64
165	uint32_t Alignment0;
166	#endif
167
168	/** ISA bridge state. */
169	PIIX3 PIIX3State;
170	/** PCI bus which is attached to the host-to-PCI bridge. */
171	PCIBUS PciBus;
172
173	} PCIGLOBALS;
174	/** Pointer to per VM data. */
175	typedef PCIGLOBALS *PPCIGLOBALS;
176
177
178	/*******************************************************************************
179	* Defined Constants And Macros *
180	*******************************************************************************/
181
182	/** Converts a bus instance pointer to a device instance pointer. */
183	#define PCIBUS_2_DEVINS(pPciBus) ((pPciBus)->CTX_SUFF(pDevIns))
184	/** Converts a device instance pointer to a PCIGLOBALS pointer. */
185	#define DEVINS_2_PCIGLOBALS(pDevIns) ((PPCIGLOBALS)(PDMINS_2_DATA(pDevIns, PPCIGLOBALS)))
186	/** Converts a device instance pointer to a PCIBUS pointer. */
187	#define DEVINS_2_PCIBUS(pDevIns) ((PPCIBUS)(&PDMINS_2_DATA(pDevIns, PPCIGLOBALS)->PciBus))
188
189	/** Converts a pointer to a PCI bus instance to a PCIGLOBALS pointer.
190	* @note This works only if the bus number is 0!!!
191	*/
192	#define PCIBUS_2_PCIGLOBALS(pPciBus) ( (PPCIGLOBALS)((uintptr_t)(pPciBus) - RT_OFFSETOF(PCIGLOBALS, PciBus)) )
193
194	/** @def PCI_LOCK
195	* Acquires the PDM lock. This is a NOP if locking is disabled. */
196	/** @def PCI_UNLOCK
197	* Releases the PDM lock. This is a NOP if locking is disabled. */
198	#define PCI_LOCK(pDevIns, rc) \
199	do { \
200	int rc2 = DEVINS_2_PCIBUS(pDevIns)->CTX_SUFF(pPciHlp)->pfnLock((pDevIns), rc); \
201	if (rc2 != VINF_SUCCESS) \
202	return rc2; \
203	} while (0)
204	#define PCI_UNLOCK(pDevIns) \
205	DEVINS_2_PCIBUS(pDevIns)->CTX_SUFF(pPciHlp)->pfnUnlock(pDevIns)
206
207	/** @def VBOX_PCI_SAVED_STATE_VERSION
208	* Saved state version of the PCI bus device.
209	*/
210	#define VBOX_PCI_SAVED_STATE_VERSION 3
211
212
213	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
214	/*******************************************************************************
215	* Internal Functions *
216	*******************************************************************************/
217	RT_C_DECLS_BEGIN
218
219	PDMBOTHCBDECL(void) pciSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel);
220	PDMBOTHCBDECL(void) pcibridgeSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel);
221	PDMBOTHCBDECL(int) pciIOPortAddressWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
222	PDMBOTHCBDECL(int) pciIOPortAddressRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb);
223	PDMBOTHCBDECL(int) pciIOPortDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
224	PDMBOTHCBDECL(int) pciIOPortDataRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb);
225
226	#ifdef IN_RING3
227	DECLINLINE(PPCIDEVICE) pciFindBridge(PPCIBUS pBus, uint8_t iBus);
228	#endif
229
230	RT_C_DECLS_END
231
232	#define DEBUG_PCI
233
234	#define PCI_VENDOR_ID 0x00 /* 16 bits */
235	#define PCI_DEVICE_ID 0x02 /* 16 bits */
236	#define PCI_COMMAND 0x04 /* 16 bits */
237	#define PCI_COMMAND_IO 0x01 /* Enable response in I/O space */
238	#define PCI_COMMAND_MEMORY 0x02 /* Enable response in Memory space */
239	#define PCI_CLASS_DEVICE 0x0a /* Device class */
240	#define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
241	#define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
242	#define PCI_MIN_GNT 0x3e /* 8 bits */
243	#define PCI_MAX_LAT 0x3f /* 8 bits */
244
245
246	#ifdef IN_RING3
247
248	static void pci_update_mappings(PCIDevice *d)
249	{
250	PPCIBUS pBus = d->Int.s.CTX_SUFF(pBus);
251	PCIIORegion *r;
252	int cmd, i;
253	uint32_t last_addr, new_addr, config_ofs;
254
255	cmd = RT_LE2H_U16((uint16_t )(d->config + PCI_COMMAND));
256	for(i = 0; i < PCI_NUM_REGIONS; i++) {
257	r = &d->Int.s.aIORegions[i];
258	if (i == PCI_ROM_SLOT) {
259	config_ofs = 0x30;
260	} else {
261	config_ofs = 0x10 + i * 4;
262	}
263	if (r->size != 0) {
264	if (r->type & PCI_ADDRESS_SPACE_IO) {
265	if (cmd & PCI_COMMAND_IO) {
266	new_addr = RT_LE2H_U32((uint32_t )(d->config +
267	config_ofs));
268	new_addr = new_addr & ~(r->size - 1);
269	last_addr = new_addr + r->size - 1;
270	/* NOTE: we have only 64K ioports on PC */
271	if (last_addr <= new_addr \|\| new_addr == 0 \|\|
272	last_addr >= 0x10000) {
273	new_addr = ~0U;
274	}
275	} else {
276	new_addr = ~0U;
277	}
278	} else {
279	if (cmd & PCI_COMMAND_MEMORY) {
280	new_addr = RT_LE2H_U32((uint32_t )(d->config +
281	config_ofs));
282	/* the ROM slot has a specific enable bit */
283	if (i == PCI_ROM_SLOT && !(new_addr & 1))
284	goto no_mem_map;
285	new_addr = new_addr & ~(r->size - 1);
286	last_addr = new_addr + r->size - 1;
287	/* NOTE: we do not support wrapping */
288	/* XXX: as we cannot support really dynamic
289	mappings, we handle specific values as invalid
290	mappings. */
291	if (last_addr <= new_addr \|\| new_addr == 0 \|\|
292	last_addr == ~0U) {
293	new_addr = ~0U;
294	}
295	} else {
296	no_mem_map:
297	new_addr = ~0U;
298	}
299	}
300	/* now do the real mapping */
301	if (new_addr != r->addr) {
302	if (r->addr != ~0U) {
303	if (r->type & PCI_ADDRESS_SPACE_IO) {
304	int devclass;
305	/* NOTE: specific hack for IDE in PC case:
306	only one byte must be mapped. */
307	devclass = d->config[0x0a] \| (d->config[0x0b] << 8);
308	if (devclass == 0x0101 && r->size == 4) {
309	int rc = PDMDevHlpIOPortDeregister(d->pDevIns, r->addr + 2, 1);
310	AssertRC(rc);
311	} else {
312	int rc = PDMDevHlpIOPortDeregister(d->pDevIns, r->addr, r->size);
313	AssertRC(rc);
314	}
315	} else {
316	RTGCPHYS GCPhysBase = r->addr;
317	int rc;
318	if (pBus->pPciHlpR3->pfnIsMMIO2Base(pBus->pDevInsR3, d->pDevIns, GCPhysBase))
319	{
320	/* unmap it. */
321	rc = r->map_func(d, i, NIL_RTGCPHYS, r->size, (PCIADDRESSSPACE)(r->type));
322	AssertRC(rc);
323	rc = PDMDevHlpMMIO2Unmap(d->pDevIns, i, GCPhysBase);
324	}
325	else
326	rc = PDMDevHlpMMIODeregister(d->pDevIns, GCPhysBase, r->size);
327	AssertMsgRC(rc, ("rc=%Rrc d=%s i=%d GCPhysBase=%RGp size=%#x\n", rc, d->name, i, GCPhysBase, r->size));
328	}
329	}
330	r->addr = new_addr;
331	if (r->addr != ~0U) {
332	int rc = r->map_func(d, i,
333	r->addr + (r->type & PCI_ADDRESS_SPACE_IO ? 0 : 0),
334	r->size, (PCIADDRESSSPACE)(r->type));
335	AssertRC(rc);
336	}
337	}
338	}
339	}
340	}
341
342
343	static DECLCALLBACK(uint32_t) pci_default_read_config(PCIDevice *d, uint32_t address, unsigned len)
344	{
345	uint32_t val;
346	switch(len) {
347	case 1:
348	val = d->config[address];
349	break;
350	case 2:
351	val = RT_LE2H_U16((uint16_t )(d->config + address));
352	break;
353	default:
354	case 4:
355	val = RT_LE2H_U32((uint32_t )(d->config + address));
356	break;
357	}
358	return val;
359	}
360
361	static DECLCALLBACK(void) pci_default_write_config(PCIDevice *d, uint32_t address, uint32_t val, unsigned len)
362	{
363	int can_write;
364	unsigned i;
365	uint32_t end, addr;
366
367	if (len == 4 && ((address >= 0x10 && address < 0x10 + 4 * 6) \|\|
368	(address >= 0x30 && address < 0x34))) {
369	PCIIORegion *r;
370	int reg;
371
372	if ( address >= 0x30 ) {
373	reg = PCI_ROM_SLOT;
374	}else{
375	reg = (address - 0x10) >> 2;
376	}
377	r = &d->Int.s.aIORegions[reg];
378	if (r->size == 0)
379	goto default_config;
380	/* compute the stored value */
381	if (reg == PCI_ROM_SLOT) {
382	/* keep ROM enable bit */
383	val &= (~(r->size - 1)) \| 1;
384	} else {
385	val &= ~(r->size - 1);
386	val \|= r->type;
387	}
388	(uint32_t )(d->config + address) = RT_H2LE_U32(val);
389	pci_update_mappings(d);
390	return;
391	}
392	default_config:
393	/* not efficient, but simple */
394	addr = address;
395	for(i = 0; i < len; i++) {
396	/* default read/write accesses */
397	switch(d->config[0x0e]) {
398	case 0x00: /* normal device */
399	case 0x80: /* multi-function device */
400	switch(addr) {
401	case 0x00:
402	case 0x01:
403	case 0x02:
404	case 0x03:
405	case 0x08:
406	case 0x09:
407	case 0x0a:
408	case 0x0b:
409	case 0x0e:
410	case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17: /* base */
411	case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f:
412	case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27:
413	case 0x2c: case 0x2d: /* subsystem ID */
414	case 0x2e: case 0x2f: /* vendor ID */
415	case 0x30: case 0x31: case 0x32: case 0x33: /* rom */
416	case 0x3d:
417	can_write = 0;
418	break;
419	default:
420	can_write = 1;
421	break;
422	}
423	break;
424	default:
425	case 0x01: /* bridge */
426	switch(addr) {
427	case 0x00:
428	case 0x01:
429	case 0x02:
430	case 0x03:
431	case 0x08:
432	case 0x09:
433	case 0x0a:
434	case 0x0b:
435	case 0x0e:
436	case 0x38: case 0x39: case 0x3a: case 0x3b: /* rom */
437	case 0x3d:
438	can_write = 0;
439	break;
440	default:
441	can_write = 1;
442	break;
443	}
444	break;
445	}
446	#ifdef VBOX
447	if (addr == 0x06)
448	{
449	/* don't change read-only bits => actually all lower bits are read-only */
450	val &= UINT32_C(~0xff);
451	/* status register, low part: clear bits by writing a '1' to the corresponding bit */
452	d->config[addr] &= ~val;
453	}
454	else if (addr == 0x07)
455	{
456	/* don't change read-only bits */
457	val &= UINT32_C(~0x06);
458	/* status register, high part: clear bits by writing a '1' to the corresponding bit */
459	d->config[addr] &= ~val;
460	}
461	else
462	#endif
463	if (can_write) {
464	d->config[addr] = val;
465	}
466	addr++;
467	val >>= 8;
468	}
469
470	end = address + len;
471	if (end > PCI_COMMAND && address < (PCI_COMMAND + 2)) {
472	/* if the command register is modified, we must modify the mappings */
473	pci_update_mappings(d);
474	}
475	}
476
477	#endif /* IN_RING3 */
478
479	static int pci_data_write(PPCIGLOBALS pGlobals, uint32_t addr, uint32_t val, int len)
480	{
481	uint8_t iBus, iDevice;
482	uint32_t config_addr;
483
484	Log(("pci_data_write: addr=%08x val=%08x len=%d\n", pGlobals->uConfigReg, val, len));
485
486	if (!(pGlobals->uConfigReg & (1 << 31))) {
487	return VINF_SUCCESS;
488	}
489	if ((pGlobals->uConfigReg & 0x3) != 0) {
490	return VINF_SUCCESS;
491	}
492	iBus = (pGlobals->uConfigReg >> 16) & 0xff;
493	iDevice = (pGlobals->uConfigReg >> 8) & 0xff;
494	config_addr = (pGlobals->uConfigReg & 0xfc) \| (addr & 3);
495	if (iBus != 0)
496	{
497	if (pGlobals->PciBus.cBridges)
498	{
499	#ifdef IN_RING3 /** @todo do lookup in R0/RC too! */
500	PPCIDEVICE pBridgeDevice = pciFindBridge(&pGlobals->PciBus, iBus);
501	if (pBridgeDevice)
502	{
503	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigWrite);
504	pBridgeDevice->Int.s.pfnBridgeConfigWrite(pBridgeDevice->pDevIns, iBus, iDevice, config_addr, val, len);
505	}
506	#else
507	return VINF_IOM_HC_IOPORT_WRITE;
508	#endif
509	}
510	}
511	else
512	{
513	R3PTRTYPE(PCIDevice *) pci_dev = pGlobals->PciBus.devices[iDevice];
514	if (pci_dev)
515	{
516	#ifdef IN_RING3
517	Log(("pci_config_write: %s: addr=%02x val=%08x len=%d\n", pci_dev->name, config_addr, val, len));
518	pci_dev->Int.s.pfnConfigWrite(pci_dev, config_addr, val, len);
519	#else
520	return VINF_IOM_HC_IOPORT_WRITE;
521	#endif
522	}
523	}
524	return VINF_SUCCESS;
525	}
526
527	static int pci_data_read(PPCIGLOBALS pGlobals, uint32_t addr, int len, uint32_t *pu32)
528	{
529	uint8_t iBus, iDevice;
530	uint32_t config_addr;
531
532	*pu32 = 0xffffffff;
533
534	if (!(pGlobals->uConfigReg & (1 << 31)))
535	return VINF_SUCCESS;
536	if ((pGlobals->uConfigReg & 0x3) != 0)
537	return VINF_SUCCESS;
538	iBus = (pGlobals->uConfigReg >> 16) & 0xff;
539	iDevice = (pGlobals->uConfigReg >> 8) & 0xff;
540	config_addr = (pGlobals->uConfigReg & 0xfc) \| (addr & 3);
541	if (iBus != 0)
542	{
543	if (pGlobals->PciBus.cBridges)
544	{
545	#ifdef IN_RING3 /** @todo do lookup in R0/RC too! */
546	PPCIDEVICE pBridgeDevice = pciFindBridge(&pGlobals->PciBus, iBus);
547	if (pBridgeDevice)
548	{
549	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigRead);
550	*pu32 = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->pDevIns, iBus, iDevice, config_addr, len);
551	}
552	#else
553	return VINF_IOM_HC_IOPORT_READ;
554	#endif
555	}
556	}
557	else
558	{
559	R3PTRTYPE(PCIDevice *) pci_dev = pGlobals->PciBus.devices[iDevice];
560	if (pci_dev)
561	{
562	#ifdef IN_RING3
563	*pu32 = pci_dev->Int.s.pfnConfigRead(pci_dev, config_addr, len);
564	Log(("pci_config_read: %s: addr=%02x val=%08x len=%d\n", pci_dev->name, config_addr, *pu32, len));
565	#else
566	return VINF_IOM_HC_IOPORT_READ;
567	#endif
568	}
569	}
570
571	return VINF_SUCCESS;
572	}
573
574
575
576	/* return the global irq number corresponding to a given device irq
577	pin. We could also use the bus number to have a more precise
578	mapping.
579	This is the implementation note described in the PCI spec chapter 2.2.6 */
580	static inline int pci_slot_get_pirq(uint8_t uDevFn, int irq_num)
581	{
582	int slot_addend;
583	slot_addend = (uDevFn >> 3) - 1;
584	return (irq_num + slot_addend) & 3;
585	}
586
587	static inline int pci_slot_get_apic_pirq(uint8_t uDevFn, int irq_num)
588	{
589	return (irq_num + (uDevFn >> 3)) & 7;
590	}
591
592	static inline int get_pci_irq_apic_level(PPCIGLOBALS pGlobals, int irq_num)
593	{
594	return (pGlobals->pci_apic_irq_levels[irq_num] != 0);
595	}
596
597	static void apic_set_irq(PPCIBUS pBus, uint8_t uDevFn, PCIDevice *pPciDev, int irq_num1, int iLevel, int acpi_irq)
598	{
599	/* This is only allowed to be called with a pointer to the host bus. */
600	AssertMsg(pBus->iBus == 0, ("iBus=%u\n", pBus->iBus));
601
602	if (acpi_irq == -1) {
603	int apic_irq, apic_level;
604	PPCIGLOBALS pGlobals = PCIBUS_2_PCIGLOBALS(pBus);
605	int irq_num = pci_slot_get_apic_pirq(uDevFn, irq_num1);
606
607	if ((iLevel & PDM_IRQ_LEVEL_HIGH) == PDM_IRQ_LEVEL_HIGH)
608	ASMAtomicIncU32(&pGlobals->pci_apic_irq_levels[irq_num]);
609	else if ((iLevel & PDM_IRQ_LEVEL_HIGH) == PDM_IRQ_LEVEL_LOW)
610	ASMAtomicDecU32(&pGlobals->pci_apic_irq_levels[irq_num]);
611
612	apic_irq = irq_num + 0x10;
613	apic_level = get_pci_irq_apic_level(pGlobals, irq_num);
614	Log3(("apic_set_irq: %s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d\n",
615	R3STRING(pPciDev->name), irq_num1, iLevel, apic_irq, apic_level, irq_num));
616	pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), apic_irq, apic_level);
617
618	if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP) {
619	ASMAtomicDecU32(&pGlobals->pci_apic_irq_levels[irq_num]);
620	pPciDev->Int.s.uIrqPinState = PDM_IRQ_LEVEL_LOW;
621	apic_level = get_pci_irq_apic_level(pGlobals, irq_num);
622	Log3(("apic_set_irq: %s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d (flop)\n",
623	R3STRING(pPciDev->name), irq_num1, iLevel, apic_irq, apic_level, irq_num));
624	pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), apic_irq, apic_level);
625	}
626	} else {
627	Log3(("apic_set_irq: %s: irq_num1=%d level=%d acpi_irq=%d\n",
628	R3STRING(pPciDev->name), irq_num1, iLevel, acpi_irq));
629	pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), acpi_irq, iLevel);
630	}
631	}
632
633	DECLINLINE(int) get_pci_irq_level(PPCIGLOBALS pGlobals, int irq_num)
634	{
635	return (pGlobals->pci_irq_levels[irq_num] != 0);
636	}
637
638	/**
639	* Set the IRQ for a PCI device on the host bus - shared by host bus and bridge.
640	*
641	* @param pDevIns Device instance of the host PCI Bus.
642	* @param uDevFn The device number on the host bus which will raise the IRQ
643	* @param pPciDev The PCI device structure which raised the interrupt.
644	* @param iIrq IRQ number to set.
645	* @param iLevel IRQ level.
646	* @remark uDevFn and pPciDev->devfn are not the same if the device is behind a bridge.
647	* In that case uDevFn will be the slot of the bridge which is needed to calculate the
648	* PIRQ value.
649	*/
650	static void pciSetIrqInternal(PPCIGLOBALS pGlobals, uint8_t uDevFn, PPCIDEVICE pPciDev, int iIrq, int iLevel)
651	{
652	PPCIBUS pBus = &pGlobals->PciBus;
653	uint8_t *pbCfg = pGlobals->PIIX3State.dev.config;
654	const bool fIsAcpiDevice = pPciDev->config[2] == 0x13 && pPciDev->config[3] == 0x71;
655	/* If the two configuration space bytes at 0xde, 0xad are set to 0xbe, 0xef, a back door
656	* is opened to route PCI interrupts directly to the I/O APIC and bypass the PIC.
657	* See the \_SB_.PCI0._PRT method in vbox.dsl.
658	*/
659	const bool fIsApicEnabled = pGlobals->fUseIoApic && pbCfg[0xde] == 0xbe && pbCfg[0xad] == 0xef;
660	int pic_irq, pic_level;
661
662	/* Check if the state changed. */
663	if (pPciDev->Int.s.uIrqPinState != iLevel)
664	{
665	pPciDev->Int.s.uIrqPinState = (iLevel & PDM_IRQ_LEVEL_HIGH);
666
667	/* Send interrupt to I/O APIC only. */
668	if (fIsApicEnabled)
669	{
670	if (fIsAcpiDevice)
671	/*
672	* ACPI needs special treatment since SCI is hardwired and
673	* should not be affected by PCI IRQ routing tables at the
674	* same time SCI IRQ is shared in PCI sense hence this
675	* kludge (i.e. we fetch the hardwired value from ACPIs
676	* PCI device configuration space).
677	*/
678	apic_set_irq(pBus, uDevFn, pPciDev, -1, iLevel, pPciDev->config[PCI_INTERRUPT_LINE]);
679	else
680	apic_set_irq(pBus, uDevFn, pPciDev, iIrq, iLevel, -1);
681	return;
682	}
683
684	if (fIsAcpiDevice)
685	{
686	/* As per above treat ACPI in a special way */
687	pic_irq = pPciDev->config[PCI_INTERRUPT_LINE];
688	pGlobals->acpi_irq = pic_irq;
689	pGlobals->acpi_irq_level = iLevel & PDM_IRQ_LEVEL_HIGH;
690	}
691	else
692	{
693	int irq_num;
694	irq_num = pci_slot_get_pirq(uDevFn, iIrq);
695
696	if (pPciDev->Int.s.uIrqPinState == PDM_IRQ_LEVEL_HIGH)
697	ASMAtomicIncU32(&pGlobals->pci_irq_levels[irq_num]);
698	else if (pPciDev->Int.s.uIrqPinState == PDM_IRQ_LEVEL_LOW)
699	ASMAtomicDecU32(&pGlobals->pci_irq_levels[irq_num]);
700
701	/* now we change the pic irq level according to the piix irq mappings */
702	pic_irq = pbCfg[0x60 + irq_num];
703	if (pic_irq >= 16)
704	{
705	if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP)
706	{
707	ASMAtomicDecU32(&pGlobals->pci_irq_levels[irq_num]);
708	pPciDev->Int.s.uIrqPinState = PDM_IRQ_LEVEL_LOW;
709	}
710
711	return;
712	}
713	}
714
715	/* the pic level is the logical OR of all the PCI irqs mapped to it */
716	pic_level = 0;
717	if (pic_irq == pbCfg[0x60])
718	pic_level \|= get_pci_irq_level(pGlobals, 0);
719	if (pic_irq == pbCfg[0x61])
720	pic_level \|= get_pci_irq_level(pGlobals, 1);
721	if (pic_irq == pbCfg[0x62])
722	pic_level \|= get_pci_irq_level(pGlobals, 2);
723	if (pic_irq == pbCfg[0x63])
724	pic_level \|= get_pci_irq_level(pGlobals, 3);
725	if (pic_irq == pGlobals->acpi_irq)
726	pic_level \|= pGlobals->acpi_irq_level;
727
728	Log3(("pciSetIrq: %s: iLevel=%d iIrq=%d pic_irq=%d pic_level=%d\n",
729	R3STRING(pPciDev->name), iLevel, iIrq, pic_irq, pic_level));
730	pBus->CTX_SUFF(pPciHlp)->pfnIsaSetIrq(pBus->CTX_SUFF(pDevIns), pic_irq, pic_level);
731
732	/** @todo optimize pci irq flip-flop some rainy day. */
733	if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP)
734	pciSetIrqInternal(pGlobals, uDevFn, pPciDev, iIrq, PDM_IRQ_LEVEL_LOW);
735	}
736	}
737
738	/**
739	* Set the IRQ for a PCI device on the host bus.
740	*
741	* @param pDevIns Device instance of the PCI Bus.
742	* @param pPciDev The PCI device structure.
743	* @param iIrq IRQ number to set.
744	* @param iLevel IRQ level.
745	*/
746	PDMBOTHCBDECL(void) pciSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel)
747	{
748	pciSetIrqInternal(PDMINS_2_DATA(pDevIns, PPCIGLOBALS), pPciDev->devfn, pPciDev, iIrq, iLevel);
749	}
750
751	#ifdef IN_RING3
752
753	/**
754	* Finds a bridge on the bus which contains the destination bus.
755	*
756	* @return Pointer to the device instance data of the bus or
757	* NULL if no bridge was found.
758	* @param pBus Pointer to the bus to search on.
759	* @param iBus Destination bus number.
760	*/
761	DECLINLINE(PPCIDEVICE) pciFindBridge(PPCIBUS pBus, uint8_t iBus)
762	{
763	/* Search for a fitting bridge. */
764	for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
765	{
766	/*
767	* Examine secondary and subordinate bus number.
768	* If the target bus is in the range we pass the request on to the bridge.
769	*/
770	PPCIDEVICE pBridgeTemp = pBus->papBridgesR3[iBridge];
771	AssertMsg(pBridgeTemp && pBridgeTemp->Int.s.fPciToPciBridge,
772	("Device is not a PCI bridge but on the list of PCI bridges\n"));
773
774	if ( iBus >= pBridgeTemp->config[VBOX_PCI_SECONDARY_BUS]
775	&& iBus <= pBridgeTemp->config[VBOX_PCI_SUBORDINATE_BUS])
776	return pBridgeTemp;
777	}
778
779	/* Nothing found. */
780	return NULL;
781	}
782
783	static void piix3_reset(PIIX3State *d)
784	{
785	uint8_t *pci_conf = d->dev.config;
786
787	pci_conf[0x04] = 0x07; /* master, memory and I/O */
788	pci_conf[0x05] = 0x00;
789	pci_conf[0x06] = 0x00;
790	pci_conf[0x07] = 0x02; /* PCI_status_devsel_medium */
791	pci_conf[0x4c] = 0x4d;
792	pci_conf[0x4e] = 0x03;
793	pci_conf[0x4f] = 0x00;
794	pci_conf[0x60] = 0x80;
795	pci_conf[0x69] = 0x02;
796	pci_conf[0x70] = 0x80;
797	pci_conf[0x76] = 0x0c;
798	pci_conf[0x77] = 0x0c;
799	pci_conf[0x78] = 0x02;
800	pci_conf[0x79] = 0x00;
801	pci_conf[0x80] = 0x00;
802	pci_conf[0x82] = 0x02; /* Get rid of the Linux guest "Enabling Passive Release" PCI quirk warning. */
803	pci_conf[0xa0] = 0x08;
804	pci_conf[0xa0] = 0x08;
805	pci_conf[0xa2] = 0x00;
806	pci_conf[0xa3] = 0x00;
807	pci_conf[0xa4] = 0x00;
808	pci_conf[0xa5] = 0x00;
809	pci_conf[0xa6] = 0x00;
810	pci_conf[0xa7] = 0x00;
811	pci_conf[0xa8] = 0x0f;
812	pci_conf[0xaa] = 0x00;
813	pci_conf[0xab] = 0x00;
814	pci_conf[0xac] = 0x00;
815	pci_conf[0xae] = 0x00;
816	}
817
818	static void pci_config_writel(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t val)
819	{
820	pGlobals->uConfigReg = 0x80000000 \| (uBus << 16) \|
821	(uDevFn << 8) \| addr;
822	pci_data_write(pGlobals, 0, val, 4);
823	}
824
825	static void pci_config_writew(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t val)
826	{
827	pGlobals->uConfigReg = 0x80000000 \| (uBus << 16) \|
828	(uDevFn << 8) \| (addr & ~3);
829	pci_data_write(pGlobals, addr & 3, val, 2);
830	}
831
832	static void pci_config_writeb(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t val)
833	{
834	pGlobals->uConfigReg = 0x80000000 \| (uBus << 16) \|
835	(uDevFn << 8) \| (addr & ~3);
836	pci_data_write(pGlobals, addr & 3, val, 1);
837	}
838
839	static uint32_t pci_config_readl(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr)
840	{
841	pGlobals->uConfigReg = 0x80000000 \| (uBus << 16) \|
842	(uDevFn << 8) \| addr;
843	uint32_t u32Val;
844	int rc = pci_data_read(pGlobals, 0, 4, &u32Val);
845	AssertRC(rc);
846	return u32Val;
847	}
848
849	static uint32_t pci_config_readw(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr)
850	{
851	pGlobals->uConfigReg = 0x80000000 \| (uBus << 16) \|
852	(uDevFn << 8) \| (addr & ~3);
853	uint32_t u32Val;
854	int rc = pci_data_read(pGlobals, addr & 3, 2, &u32Val);
855	AssertRC(rc);
856	return u32Val;
857	}
858
859	static uint32_t pci_config_readb(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr)
860	{
861	pGlobals->uConfigReg = 0x80000000 \| (uBus << 16) \|
862	(uDevFn << 8) \| (addr & ~3);
863	uint32_t u32Val;
864	int rc = pci_data_read(pGlobals, addr & 3, 1, &u32Val);
865	AssertRC(rc);
866	return u32Val;
867	}
868
869	/* host irqs corresponding to PCI irqs A-D */
870	static const uint8_t pci_irqs[4] = { 11, 9, 11, 9 }; /* bird: added const */
871
872	static void pci_set_io_region_addr(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, int region_num, uint32_t addr)
873	{
874	uint16_t cmd;
875	uint32_t ofs;
876
877	if ( region_num == PCI_ROM_SLOT )
878	ofs = 0x30;
879	else
880	ofs = 0x10 + region_num * 4;
881
882	/* Read memory type first. */
883	uint8_t uRessourceType = pci_config_readb(pGlobals, uBus, uDevFn, ofs);
884
885	/* Read command register. */
886	cmd = pci_config_readw(pGlobals, uBus, uDevFn, PCI_COMMAND);
887	if ( region_num == PCI_ROM_SLOT )
888	cmd \|= 2;
889	else if ((uRessourceType & 0x01) == 1) /* Test if region is I/O space. */
890	cmd \|= 1; /* Enable I/O space access. */
891	else /* The region is MMIO. */
892	cmd \|= 2; /* Enable MMIO access. */
893
894	/* Write address of the device. */
895	pci_config_writel(pGlobals, uBus, uDevFn, ofs, addr);
896
897	/* enable memory mappings */
898	pci_config_writew(pGlobals, uBus, uDevFn, PCI_COMMAND, cmd);
899	}
900
901	static void pci_bios_init_device(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint8_t cBridgeDepth, uint8_t *paBridgePositions)
902	{
903	uint32_t *paddr;
904	int i, pin, pic_irq;
905	uint16_t devclass, vendor_id, device_id;
906
907	devclass = pci_config_readw(pGlobals, uBus, uDevFn, PCI_CLASS_DEVICE);
908	vendor_id = pci_config_readw(pGlobals, uBus, uDevFn, PCI_VENDOR_ID);
909	device_id = pci_config_readw(pGlobals, uBus, uDevFn, PCI_DEVICE_ID);
910
911	/* Check if device is present. */
912	if (vendor_id != 0xffff)
913	{
914	switch(devclass)
915	{
916	case 0x0101:
917	if ( (vendor_id == 0x8086)
918	&& (device_id == 0x7010 \|\| device_id == 0x7111 \|\| device_id == 0x269e))
919	{
920	/* PIIX3, PIIX4 or ICH6 IDE */
921	pci_config_writew(pGlobals, uBus, uDevFn, 0x40, 0x8000); /* enable IDE0 */
922	pci_config_writew(pGlobals, uBus, uDevFn, 0x42, 0x8000); /* enable IDE1 */
923	goto default_map;
924	}
925	else
926	{
927	/* IDE: we map it as in ISA mode */
928	pci_set_io_region_addr(pGlobals, uBus, uDevFn, 0, 0x1f0);
929	pci_set_io_region_addr(pGlobals, uBus, uDevFn, 1, 0x3f4);
930	pci_set_io_region_addr(pGlobals, uBus, uDevFn, 2, 0x170);
931	pci_set_io_region_addr(pGlobals, uBus, uDevFn, 3, 0x374);
932	}
933	break;
934	case 0x0300:
935	if (vendor_id != 0x80ee)
936	goto default_map;
937	/* VGA: map frame buffer to default Bochs VBE address */
938	pci_set_io_region_addr(pGlobals, uBus, uDevFn, 0, 0xE0000000);
939	/*
940	* Legacy VGA I/O ports are implicitly decoded by a VGA class device. But
941	* only the framebuffer (i.e., a memory region) is explicitly registered via
942	* pci_set_io_region_addr, so I/O decoding must be enabled manually.
943	*/
944	pci_config_writeb(pGlobals, uBus, uDevFn, PCI_COMMAND,
945	pci_config_readb(pGlobals, uBus, uDevFn, PCI_COMMAND)
946	\| 1 /* Enable I/O space access. */);
947	break;
948	case 0x0800:
949	/* PIC */
950	vendor_id = pci_config_readw(pGlobals, uBus, uDevFn, PCI_VENDOR_ID);
951	device_id = pci_config_readw(pGlobals, uBus, uDevFn, PCI_DEVICE_ID);
952	if (vendor_id == 0x1014)
953	{
954	/* IBM */
955	if (device_id == 0x0046 \|\| device_id == 0xFFFF)
956	{
957	/* MPIC & MPIC2 */
958	pci_set_io_region_addr(pGlobals, uBus, uDevFn, 0, 0x80800000 + 0x00040000);
959	}
960	}
961	break;
962	case 0xff00:
963	if ( (vendor_id == 0x0106b)
964	&& (device_id == 0x0017 \|\| device_id == 0x0022))
965	{
966	/* macio bridge */
967	pci_set_io_region_addr(pGlobals, uBus, uDevFn, 0, 0x80800000);
968	}
969	break;
970	case 0x0604:
971	{
972	/* Init PCI-to-PCI bridge. */
973	pci_config_writeb(pGlobals, uBus, uDevFn, VBOX_PCI_PRIMARY_BUS, uBus);
974
975	AssertMsg(pGlobals->uBus < 255, ("Too many bridges on the bus\n"));
976	pGlobals->uBus++;
977	pci_config_writeb(pGlobals, uBus, uDevFn, VBOX_PCI_SECONDARY_BUS, pGlobals->uBus);
978	pci_config_writeb(pGlobals, uBus, uDevFn, VBOX_PCI_SUBORDINATE_BUS, 0xff); /* Temporary until we know how many other bridges are behind this one. */
979
980	/* Add position of this bridge into the array. */
981	paBridgePositions[cBridgeDepth+1] = (uDevFn >> 3);
982
983	/*
984	* The I/O range for the bridge must be aligned to a 4KB boundary.
985	* This does not change anything really as the access to the device is not going
986	* through the bridge but we want to be compliant to the spec.
987	*/
988	if ((pGlobals->pci_bios_io_addr % 4096) != 0)
989	pGlobals->pci_bios_io_addr = RT_ALIGN_32(pGlobals->pci_bios_io_addr, 4*1024);
990	Log(("%s: Aligned I/O start address. New address %#x\n", __FUNCTION__, pGlobals->pci_bios_io_addr));
991	pci_config_writeb(pGlobals, uBus, uDevFn, VBOX_PCI_IO_BASE, (pGlobals->pci_bios_io_addr >> 8) & 0xf0);
992
993	/* The MMIO range for the bridge must be aligned to a 1MB boundary. */
994	if ((pGlobals->pci_bios_mem_addr % (1024 * 1024)) != 0)
995	pGlobals->pci_bios_mem_addr = RT_ALIGN_32(pGlobals->pci_bios_mem_addr, 1024*1024);
996	Log(("%s: Aligned MMIO start address. New address %#x\n", __FUNCTION__, pGlobals->pci_bios_mem_addr));
997	pci_config_writew(pGlobals, uBus, uDevFn, VBOX_PCI_MEMORY_BASE, (pGlobals->pci_bios_mem_addr >> 16) & UINT32_C(0xffff0));
998
999	/* Save values to compare later to. */
1000	uint32_t u32IoAddressBase = pGlobals->pci_bios_io_addr;
1001	uint32_t u32MMIOAddressBase = pGlobals->pci_bios_mem_addr;
1002
1003	/* Init devices behind the bridge and possibly other bridges as well. */
1004	for (int iDev = 0; iDev <= 255; iDev++)
1005	pci_bios_init_device(pGlobals, uBus + 1, iDev, cBridgeDepth + 1, paBridgePositions);
1006
1007	/* The number of bridges behind the this one is now available. */
1008	pci_config_writeb(pGlobals, uBus, uDevFn, VBOX_PCI_SUBORDINATE_BUS, pGlobals->uBus);
1009
1010	/*
1011	* Set I/O limit register. If there is no device with I/O space behind the bridge
1012	* we set a lower value than in the base register.
1013	* The result with a real bridge is that no I/O transactions are passed to the secondary
1014	* interface. Again this doesn't really matter here but we want to be compliant to the spec.
1015	*/
1016	if ((u32IoAddressBase != pGlobals->pci_bios_io_addr) && ((pGlobals->pci_bios_io_addr % 4096) != 0))
1017	{
1018	/* The upper boundary must be one byte less than a 4KB boundary. */
1019	pGlobals->pci_bios_io_addr = RT_ALIGN_32(pGlobals->pci_bios_io_addr, 4*1024);
1020	}
1021	pci_config_writeb(pGlobals, uBus, uDevFn, VBOX_PCI_IO_LIMIT, ((pGlobals->pci_bios_io_addr >> 8) & 0xf0) - 1);
1022
1023	/* Same with the MMIO limit register but with 1MB boundary here. */
1024	if ((u32MMIOAddressBase != pGlobals->pci_bios_mem_addr) && ((pGlobals->pci_bios_mem_addr % (1024 * 1024)) != 0))
1025	{
1026	/* The upper boundary must be one byte less than a 1MB boundary. */
1027	pGlobals->pci_bios_mem_addr = RT_ALIGN_32(pGlobals->pci_bios_mem_addr, 1024*1024);
1028	}
1029	pci_config_writew(pGlobals, uBus, uDevFn, VBOX_PCI_MEMORY_LIMIT, ((pGlobals->pci_bios_mem_addr >> 16) & UINT32_C(0xfff0)) - 1);
1030
1031	/*
1032	* Set the prefetch base and limit registers. We currently have no device with a prefetchable region
1033	* which may be behind a bridge. Thatswhy it is unconditionally disabled here atm by writing a higher value into
1034	* the base register than in the limit register.
1035	*/
1036	pci_config_writew(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_MEMORY_BASE, 0xfff0);
1037	pci_config_writew(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_MEMORY_LIMIT, 0x0);
1038	pci_config_writel(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_BASE_UPPER32, 0x00);
1039	pci_config_writel(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_LIMIT_UPPER32, 0x00);
1040	break;
1041	}
1042	default:
1043	default_map:
1044	{
1045	/* default memory mappings */
1046	/*
1047	* PCI_NUM_REGIONS is 7 because of the rom region but there are only 6 base address register defined by the PCI spec.
1048	* Leaving only PCI_NUM_REGIONS would cause reading another and enabling a memory region which does not exist.
1049	*/
1050	for(i = 0; i < (PCI_NUM_REGIONS-1); i++)
1051	{
1052	uint32_t u32Size;
1053	uint8_t u8RessourceType;
1054	uint32_t u32Address = 0x10 + i * 4;
1055
1056	/* Calculate size. */
1057	u8RessourceType = pci_config_readb(pGlobals, uBus, uDevFn, u32Address);
1058	pci_config_writel(pGlobals, uBus, uDevFn, u32Address, UINT32_C(0xffffffff));
1059	u32Size = pci_config_readl(pGlobals, uBus, uDevFn, u32Address);
1060	/* Clear ressource information depending on ressource type. */
1061	if ((u8RessourceType & 0x01) == 1) /* I/O */
1062	u32Size &= ~(0x01);
1063	else /* MMIO */
1064	u32Size &= ~(0x0f);
1065
1066	/*
1067	* Invert all bits and add 1 to get size of the region.
1068	* (From PCI implementation note)
1069	*/
1070	if (((u8RessourceType & 0x01) == 1) && (u32Size & UINT32_C(0xffff0000)) == 0)
1071	u32Size = (~(u32Size \| UINT32_C(0xffff0000))) + 1;
1072	else
1073	u32Size = (~u32Size) + 1;
1074
1075	Log(("%s: Size of region %u for device %d on bus %d is %u\n", __FUNCTION__, i, uDevFn, uBus, u32Size));
1076
1077	if (u32Size)
1078	{
1079	if ((u8RessourceType & 0x01) == 1)
1080	paddr = &pGlobals->pci_bios_io_addr;
1081	else
1082	paddr = &pGlobals->pci_bios_mem_addr;
1083	paddr = (paddr + u32Size - 1) & ~(u32Size - 1);
1084	Log(("%s: Start address of %s region %u is %#x\n", __FUNCTION__, ((u8RessourceType & 0x01) == 1 ? "I/O" : "MMIO"), i, *paddr));
1085	pci_set_io_region_addr(pGlobals, uBus, uDevFn, i, *paddr);
1086	*paddr += u32Size;
1087	Log(("%s: New address is %#x\n", __FUNCTION__, *paddr));
1088	}
1089	}
1090	break;
1091	}
1092	}
1093
1094	/* map the interrupt */
1095	pin = pci_config_readb(pGlobals, uBus, uDevFn, PCI_INTERRUPT_PIN);
1096	if (pin != 0)
1097	{
1098	uint8_t uBridgeDevFn = uDevFn;
1099	pin--;
1100
1101	/* We need to go up to the host bus to see which irq this device will assert there. */
1102	while (cBridgeDepth != 0)
1103	{
1104	/* Get the pin the device would assert on the bridge. */
1105	pin = ((uBridgeDevFn >> 3) + pin) & 3;
1106	uBridgeDevFn = paBridgePositions[cBridgeDepth];
1107	cBridgeDepth--;
1108	}
1109
1110	pin = pci_slot_get_pirq(uDevFn, pin);
1111	pic_irq = pci_irqs[pin];
1112	pci_config_writeb(pGlobals, uBus, uDevFn, PCI_INTERRUPT_LINE, pic_irq);
1113	}
1114	}
1115	}
1116
1117	#endif /* IN_RING3 */
1118
1119	/* -=-=-=-=-=- wrappers -=-=-=-=-=- */
1120
1121	/**
1122	* Port I/O Handler for PCI address OUT operations.
1123	*
1124	* @returns VBox status code.
1125	*
1126	* @param pDevIns The device instance.
1127	* @param pvUser User argument - ignored.
1128	* @param uPort Port number used for the IN operation.
1129	* @param u32 The value to output.
1130	* @param cb The value size in bytes.
1131	*/
1132	PDMBOTHCBDECL(int) pciIOPortAddressWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1133	{
1134	Log(("pciIOPortAddressWrite: Port=%#x u32=%#x cb=%d\n", Port, u32, cb));
1135	NOREF(pvUser);
1136	if (cb == 4)
1137	{
1138	PPCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
1139	PCI_LOCK(pDevIns, VINF_IOM_HC_IOPORT_WRITE);
1140	pThis->uConfigReg = u32 & ~3; /* Bits 0-1 are reserved and we silently clear them */
1141	PCI_UNLOCK(pDevIns);
1142	}
1143	/* else: 440FX does "pass through to the bus" for other writes, what ever that means.
1144	* Linux probes for cmd640 using byte writes/reads during ide init. We'll just ignore it. */
1145	return VINF_SUCCESS;
1146	}
1147
1148
1149	/**
1150	* Port I/O Handler for PCI address IN operations.
1151	*
1152	* @returns VBox status code.
1153	*
1154	* @param pDevIns The device instance.
1155	* @param pvUser User argument - ignored.
1156	* @param uPort Port number used for the IN operation.
1157	* @param pu32 Where to store the result.
1158	* @param cb Number of bytes read.
1159	*/
1160	PDMBOTHCBDECL(int) pciIOPortAddressRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
1161	{
1162	NOREF(pvUser);
1163	if (cb == 4)
1164	{
1165	PPCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
1166	PCI_LOCK(pDevIns, VINF_IOM_HC_IOPORT_READ);
1167	*pu32 = pThis->uConfigReg;
1168	PCI_UNLOCK(pDevIns);
1169	Log(("pciIOPortAddressRead: Port=%#x cb=%d -> %#x\n", Port, cb, *pu32));
1170	return VINF_SUCCESS;
1171	}
1172	/* else: 440FX does "pass through to the bus" for other writes, what ever that means.
1173	* Linux probes for cmd640 using byte writes/reads during ide init. We'll just ignore it. */
1174	Log(("pciIOPortAddressRead: Port=%#x cb=%d VERR_IOM_IOPORT_UNUSED\n", Port, cb));
1175	return VERR_IOM_IOPORT_UNUSED;
1176	}
1177
1178
1179	/**
1180	* Port I/O Handler for PCI data OUT operations.
1181	*
1182	* @returns VBox status code.
1183	*
1184	* @param pDevIns The device instance.
1185	* @param pvUser User argument - ignored.
1186	* @param uPort Port number used for the IN operation.
1187	* @param u32 The value to output.
1188	* @param cb The value size in bytes.
1189	*/
1190	PDMBOTHCBDECL(int) pciIOPortDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1191	{
1192	Log(("pciIOPortDataWrite: Port=%#x u32=%#x cb=%d\n", Port, u32, cb));
1193	NOREF(pvUser);
1194	int rc = VINF_SUCCESS;
1195	if (!(Port % cb))
1196	{
1197	PCI_LOCK(pDevIns, VINF_IOM_HC_IOPORT_WRITE);
1198	rc = pci_data_write(PDMINS_2_DATA(pDevIns, PPCIGLOBALS), Port, u32, cb);
1199	PCI_UNLOCK(pDevIns);
1200	}
1201	else
1202	AssertMsgFailed(("Write to port %#x u32=%#x cb=%d\n", Port, u32, cb));
1203	return rc;
1204	}
1205
1206
1207	/**
1208	* Port I/O Handler for PCI data IN operations.
1209	*
1210	* @returns VBox status code.
1211	*
1212	* @param pDevIns The device instance.
1213	* @param pvUser User argument - ignored.
1214	* @param uPort Port number used for the IN operation.
1215	* @param pu32 Where to store the result.
1216	* @param cb Number of bytes read.
1217	*/
1218	PDMBOTHCBDECL(int) pciIOPortDataRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
1219	{
1220	NOREF(pvUser);
1221	if (!(Port % cb))
1222	{
1223	PCI_LOCK(pDevIns, VINF_IOM_HC_IOPORT_READ);
1224	int rc = pci_data_read(PDMINS_2_DATA(pDevIns, PPCIGLOBALS), Port, cb, pu32);
1225	PCI_UNLOCK(pDevIns);
1226	Log(("pciIOPortDataRead: Port=%#x cb=%#x -> %#x (%Rrc)\n", Port, cb, *pu32, rc));
1227	return rc;
1228	}
1229	AssertMsgFailed(("Read from port %#x cb=%d\n", Port, cb));
1230	return VERR_IOM_IOPORT_UNUSED;
1231	}
1232
1233	#ifdef IN_RING3
1234
1235	/**
1236	* Saves a state of the PCI device.
1237	*
1238	* @returns VBox status code.
1239	* @param pDevIns Device instance of the PCI Bus.
1240	* @param pPciDev Pointer to PCI device.
1241	* @param pSSM The handle to save the state to.
1242	*/
1243	static DECLCALLBACK(int) pciGenericSaveExec(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PSSMHANDLE pSSM)
1244	{
1245	return SSMR3PutMem(pSSM, &pPciDev->config[0], sizeof(pPciDev->config));
1246	}
1247
1248
1249	/**
1250	* Loads a saved PCI device state.
1251	*
1252	* @returns VBox status code.
1253	* @param pDevIns Device instance of the PCI Bus.
1254	* @param pPciDev Pointer to PCI device.
1255	* @param pSSM The handle to the saved state.
1256	*/
1257	static DECLCALLBACK(int) pciGenericLoadExec(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PSSMHANDLE pSSM)
1258	{
1259	return SSMR3GetMem(pSSM, &pPciDev->config[0], sizeof(pPciDev->config));
1260	}
1261
1262
1263	/**
1264	* Common worker for pciR3SaveExec and pcibridgeR3SaveExec.
1265	*
1266	* @returns VBox status code.
1267	* @param pBus The bus to save.
1268	* @param pSSM The saved state handle.
1269	*/
1270	static int pciR3CommonSaveExec(PPCIBUS pBus, PSSMHANDLE pSSM)
1271	{
1272	/*
1273	* Iterate thru all the devices.
1274	*/
1275	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->devices); i++)
1276	{
1277	PPCIDEVICE pDev = pBus->devices[i];
1278	if (pDev)
1279	{
1280	SSMR3PutU32(pSSM, i);
1281	SSMR3PutMem(pSSM, pDev->config, sizeof(pDev->config));
1282
1283	int rc = SSMR3PutS32(pSSM, pDev->Int.s.uIrqPinState);
1284	if (RT_FAILURE(rc))
1285	return rc;
1286	}
1287	}
1288	return SSMR3PutU32(pSSM, UINT32_MAX); /* terminator */
1289	}
1290
1291
1292	/**
1293	* Saves a state of the PCI device.
1294	*
1295	* @returns VBox status code.
1296	* @param pDevIns The device instance.
1297	* @param pPciDev Pointer to PCI device.
1298	* @param pSSM The handle to save the state to.
1299	*/
1300	static DECLCALLBACK(int) pciR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
1301	{
1302	uint32_t i;
1303	PPCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
1304
1305	/*
1306	* Bus state data.
1307	*/
1308	SSMR3PutU32(pSSM, pThis->uConfigReg);
1309	SSMR3PutBool(pSSM, pThis->fUseIoApic);
1310
1311	/*
1312	* Save IRQ states.
1313	*/
1314	for (i = 0; i < PCI_IRQ_PINS; i++)
1315	SSMR3PutU32(pSSM, pThis->pci_irq_levels[i]);
1316	for (i = 0; i < PCI_APIC_IRQ_PINS; i++)
1317	SSMR3PutU32(pSSM, pThis->pci_apic_irq_levels[i]);
1318
1319	SSMR3PutU32(pSSM, pThis->acpi_irq_level);
1320	SSMR3PutS32(pSSM, pThis->acpi_irq);
1321
1322	SSMR3PutU32(pSSM, ~0); /* separator */
1323
1324	/*
1325	* Join paths with pcibridgeR3SaveExec.
1326	*/
1327	return pciR3CommonSaveExec(&pThis->PciBus, pSSM);
1328	}
1329
1330
1331	/**
1332	* Common routine for restoring the config registers of a PCI device.
1333	*
1334	* @param pDev The PCI device.
1335	* @param pbSrcConfig The configuration register values to be loaded.
1336	* @param fIsBridge Whether this is a bridge device or not.
1337	*/
1338	static void pciR3CommonRestoreConfig(PPCIDEVICE pDev, uint8_t const *pbSrcConfig, bool fIsBridge)
1339	{
1340	/*
1341	* This table defines the fields for normal devices and bridge devices, and
1342	* the order in which they need to be restored.
1343	*/
1344	static const struct PciField
1345	{
1346	uint8_t off;
1347	uint8_t cb;
1348	uint8_t fWritable;
1349	uint8_t fBridge;
1350	const char *pszName;
1351	} s_aFields[] =
1352	{
1353	/* off,cb,fW,fB, pszName */
1354	{ 0x00, 2, 0, 3, "VENDOR_ID" },
1355	{ 0x02, 2, 0, 3, "DEVICE_ID" },
1356	{ 0x06, 2, 1, 3, "STATUS" },
1357	{ 0x08, 1, 0, 3, "REVISION_ID" },
1358	{ 0x09, 1, 0, 3, "CLASS_PROG" },
1359	{ 0x0a, 1, 0, 3, "CLASS_SUB" },
1360	{ 0x0b, 1, 0, 3, "CLASS_BASE" },
1361	{ 0x0c, 1, 0, 3, "CACHE_LINE_SIZE" }, // fWritable = ??
1362	{ 0x0d, 1, 0, 3, "LATENCY_TIMER" }, // fWritable = ??
1363	{ 0x0e, 1, 0, 3, "HEADER_TYPE" }, // fWritable = ??
1364	{ 0x0f, 1, 0, 3, "BIST" }, // fWritable = ??
1365	{ 0x10, 4, 1, 3, "BASE_ADDRESS_0" },
1366	{ 0x14, 4, 1, 3, "BASE_ADDRESS_1" },
1367	{ 0x18, 4, 1, 1, "BASE_ADDRESS_2" },
1368	{ 0x18, 1, 1, 2, "PRIMARY_BUS" }, // fWritable = ??
1369	{ 0x19, 1, 1, 2, "SECONDARY_BUS" }, // fWritable = ??
1370	{ 0x1a, 1, 1, 2, "SUBORDINATE_BUS" }, // fWritable = ??
1371	{ 0x1b, 1, 1, 2, "SEC_LATENCY_TIMER" }, // fWritable = ??
1372	{ 0x1c, 4, 1, 1, "BASE_ADDRESS_3" },
1373	{ 0x1c, 1, 1, 2, "IO_BASE" }, // fWritable = ??
1374	{ 0x1d, 1, 1, 2, "IO_LIMIT" }, // fWritable = ??
1375	{ 0x1e, 2, 1, 2, "SEC_STATUS" }, // fWritable = ??
1376	{ 0x20, 4, 1, 1, "BASE_ADDRESS_4" },
1377	{ 0x20, 2, 1, 2, "MEMORY_BASE" }, // fWritable = ??
1378	{ 0x22, 2, 1, 2, "MEMORY_LIMIT" }, // fWritable = ??
1379	{ 0x24, 4, 1, 1, "BASE_ADDRESS_4" },
1380	{ 0x24, 2, 1, 2, "PREF_MEMORY_BASE" }, // fWritable = ??
1381	{ 0x26, 2, 1, 2, "PREF_MEMORY_LIMIT" }, // fWritable = ??
1382	{ 0x28, 4, 1, 1, "CARDBUS_CIS" }, // fWritable = ??
1383	{ 0x28, 4, 1, 2, "PREF_BASE_UPPER32" }, // fWritable = ??
1384	{ 0x2c, 2, 0, 1, "SUBSYSTEM_VENDOR_ID" },// fWritable = !?
1385	{ 0x2c, 4, 1, 2, "PREF_LIMIT_UPPER32" },// fWritable = ??
1386	{ 0x2e, 2, 0, 1, "SUBSYSTEM_ID" }, // fWritable = !?
1387	{ 0x30, 4, 1, 1, "ROM_ADDRESS" }, // fWritable = ?!
1388	{ 0x30, 2, 1, 2, "IO_BASE_UPPER16" }, // fWritable = ?!
1389	{ 0x32, 2, 1, 2, "IO_LIMIT_UPPER16" }, // fWritable = ?!
1390	{ 0x34, 4, 0, 3, "CAPABILITY_LIST" }, // fWritable = !? cb=!?
1391	{ 0x38, 4, 1, 1, "???" }, // ???
1392	{ 0x38, 4, 1, 2, "ROM_ADDRESS_BR" }, // fWritable = !? cb=!? fBridge=!?
1393	{ 0x3c, 1, 1, 3, "INTERRUPT_LINE" }, // fBridge=??
1394	{ 0x3d, 1, 0, 3, "INTERRUPT_PIN" }, // fBridge=??
1395	{ 0x3e, 1, 0, 1, "MIN_GNT" }, // fWritable = !?
1396	{ 0x3e, 1, 1, 2, "BRIDGE_CONTROL" }, // fWritable = !? cb=!?
1397	{ 0x3f, 1, 1, 3, "MAX_LAT" }, // fWritable = !? fBridge=!?
1398	/* The COMMAND register must come last as it requires the ADDRESS
1399	registers to be restored before we pretent to change it from 0 to
1400	whatever value the guest assigned it. */
1401	{ 0x04, 2, 1, 3, "COMMAND" },
1402	};
1403
1404	#ifdef RT_STRICT
1405	/* Check that we've got full register coverage. */
1406	uint32_t bmDevice[0x40 / 32];
1407	uint32_t bmBridge[0x40 / 32];
1408	RT_ZERO(bmDevice);
1409	RT_ZERO(bmBridge);
1410	for (uint32_t i = 0; i < RT_ELEMENTS(s_aFields); i++)
1411	{
1412	uint8_t off = s_aFields[i].off;
1413	uint8_t cb = s_aFields[i].cb;
1414	uint8_t f = s_aFields[i].fBridge;
1415	while (cb-- > 0)
1416	{
1417	if (f & 1) AssertMsg(!ASMBitTest(bmDevice, off), ("%#x\n", off));
1418	if (f & 2) AssertMsg(!ASMBitTest(bmBridge, off), ("%#x\n", off));
1419	if (f & 1) ASMBitSet(bmDevice, off);
1420	if (f & 2) ASMBitSet(bmBridge, off);
1421	off++;
1422	}
1423	}
1424	for (uint32_t off = 0; off < 0x40; off++)
1425	{
1426	AssertMsg(ASMBitTest(bmDevice, off), ("%#x\n", off));
1427	AssertMsg(ASMBitTest(bmBridge, off), ("%#x\n", off));
1428	}
1429	#endif
1430
1431	/*
1432	* Loop thru the fields covering the 64 bytes of standard registers.
1433	*/
1434	uint8_t const fBridge = fIsBridge ? 2 : 1;
1435	uint8_t *pbDstConfig = &pDev->config[0];
1436	for (uint32_t i = 0; i < RT_ELEMENTS(s_aFields); i++)
1437	if (s_aFields[i].fBridge & fBridge)
1438	{
1439	uint8_t const off = s_aFields[i].off;
1440	uint8_t const cb = s_aFields[i].cb;
1441	uint32_t u32Src;
1442	uint32_t u32Dst;
1443	switch (cb)
1444	{
1445	case 1:
1446	u32Src = pbSrcConfig[off];
1447	u32Dst = pbDstConfig[off];
1448	break;
1449	case 2:
1450	u32Src = (uint16_t const )&pbSrcConfig[off];
1451	u32Dst = (uint16_t const )&pbDstConfig[off];
1452	break;
1453	case 4:
1454	u32Src = (uint32_t const )&pbSrcConfig[off];
1455	u32Dst = (uint32_t const )&pbDstConfig[off];
1456	break;
1457	default:
1458	AssertFailed();
1459	continue;
1460	}
1461
1462	if ( u32Src != u32Dst
1463	\|\| off == VBOX_PCI_COMMAND)
1464	{
1465	if (u32Src != u32Dst)
1466	{
1467	if (!s_aFields[i].fWritable)
1468	LogRel(("PCI: %8s/%u: %2u-bit field %s: %x -> %x - !READ ONLY!\n",
1469	pDev->name, pDev->pDevIns->iInstance, cb*8, s_aFields[i].pszName, u32Dst, u32Src));
1470	else
1471	LogRel(("PCI: %8s/%u: %2u-bit field %s: %x -> %x\n",
1472	pDev->name, pDev->pDevIns->iInstance, cb*8, s_aFields[i].pszName, u32Dst, u32Src));
1473	}
1474	if (off == VBOX_PCI_COMMAND)
1475	PCIDevSetCommand(pDev, 0); /* For remapping, see pciR3CommonLoadExec. */
1476	pDev->Int.s.pfnConfigWrite(pDev, off, u32Src, cb);
1477	}
1478	}
1479
1480	/*
1481	* The device dependent registers.
1482	*
1483	* We will not use ConfigWrite here as we have no clue about the size
1484	* of the registers, so the device is responsible for correctly
1485	* restoring functionality governed by these registers.
1486	*/
1487	for (uint32_t off = 0x40; off < sizeof(pDev->config); off++)
1488	if (pbDstConfig[off] != pbSrcConfig[off])
1489	{
1490	LogRel(("PCI: %8s/%u: register %02x: %02x -> %02x\n",
1491	pDev->name, pDev->pDevIns->iInstance, off, pbDstConfig[off], pbSrcConfig[off])); /** @todo make this Log() later. */
1492	pbDstConfig[off] = pbSrcConfig[off];
1493	}
1494	}
1495
1496
1497	/**
1498	* Common worker for pciR3LoadExec and pcibridgeR3LoadExec.
1499	*
1500	* @returns VBox status code.
1501	* @param pBus The bus which data is being loaded.
1502	* @param pSSM The saved state handle.
1503	* @param uVersion The data version.
1504	* @param uPass The pass.
1505	*/
1506	static DECLCALLBACK(int) pciR3CommonLoadExec(PPCIBUS pBus, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1507	{
1508	uint32_t u32;
1509	uint32_t i;
1510	int rc;
1511
1512	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
1513
1514	/*
1515	* Iterate thru all the devices and write 0 to the COMMAND register so
1516	* that all the memory is unmapped before we start restoring the saved
1517	* mapping locations.
1518	*
1519	* The register value is restored afterwards so we can do proper
1520	* LogRels in pciR3CommonRestoreConfig.
1521	*/
1522	for (i = 0; i < RT_ELEMENTS(pBus->devices); i++)
1523	{
1524	PPCIDEVICE pDev = pBus->devices[i];
1525	if (pDev)
1526	{
1527	uint16_t u16 = PCIDevGetCommand(pDev);
1528	pDev->Int.s.pfnConfigWrite(pDev, VBOX_PCI_COMMAND, 0, 2);
1529	PCIDevSetCommand(pDev, u16);
1530	Assert(PCIDevGetCommand(pDev) == u16);
1531	}
1532	}
1533
1534	/*
1535	* Iterate all the devices.
1536	*/
1537	for (i = 0;; i++)
1538	{
1539	PCIDEVICE DevTmp;
1540	PPCIDEVICE pDev;
1541
1542	/* index / terminator */
1543	rc = SSMR3GetU32(pSSM, &u32);
1544	if (RT_FAILURE(rc))
1545	return rc;
1546	if (u32 == (uint32_t)~0)
1547	break;
1548	if ( u32 >= RT_ELEMENTS(pBus->devices)
1549	\|\| u32 < i)
1550	{
1551	AssertMsgFailed(("u32=%#x i=%#x\n", u32, i));
1552	return rc;
1553	}
1554
1555	/* skip forward to the device checking that no new devices are present. */
1556	for (; i < u32; i++)
1557	{
1558	if (pBus->devices[i])
1559	{
1560	LogRel(("New device in slot %#x, %s (vendor=%#06x device=%#06x)\n", i, pBus->devices[i]->name,
1561	PCIDevGetVendorId(pBus->devices[i]), PCIDevGetDeviceId(pBus->devices[i])));
1562	if (SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT)
1563	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("New device in slot %#x, %s (vendor=%#06x device=%#06x)"),
1564	i, pBus->devices[i]->name, PCIDevGetVendorId(pBus->devices[i]), PCIDevGetDeviceId(pBus->devices[i]));
1565	}
1566	}
1567
1568	/* get the data */
1569	DevTmp.Int.s.uIrqPinState = ~0; /* Invalid value in case we have an older saved state to force a state change in pciSetIrq. */
1570	SSMR3GetMem(pSSM, DevTmp.config, sizeof(DevTmp.config));
1571	if (uVersion < 3)
1572	{
1573	int32_t i32Temp;
1574	/* Irq value not needed anymore. */
1575	rc = SSMR3GetS32(pSSM, &i32Temp);
1576	if (RT_FAILURE(rc))
1577	return rc;
1578	}
1579	else
1580	{
1581	rc = SSMR3GetS32(pSSM, &DevTmp.Int.s.uIrqPinState);
1582	if (RT_FAILURE(rc))
1583	return rc;
1584	}
1585
1586	/* check that it's still around. */
1587	pDev = pBus->devices[i];
1588	if (!pDev)
1589	{
1590	LogRel(("Device in slot %#x has been removed! vendor=%#06x device=%#06x\n", i,
1591	PCIDevGetVendorId(&DevTmp), PCIDevGetDeviceId(&DevTmp)));
1592	if (SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT)
1593	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Device in slot %#x has been removed! vendor=%#06x device=%#06x"),
1594	i, PCIDevGetVendorId(&DevTmp), PCIDevGetDeviceId(&DevTmp));
1595	continue;
1596	}
1597
1598	/* match the vendor id assuming that this will never be changed. */
1599	if ( DevTmp.config[0] != pDev->config[0]
1600	\|\| DevTmp.config[1] != pDev->config[1])
1601	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Device in slot %#x (%s) vendor id mismatch! saved=%.4Rhxs current=%.4Rhxs"),
1602	i, pDev->name, DevTmp.config, pDev->config);
1603
1604	/* commit the loaded device config. */
1605	pciR3CommonRestoreConfig(pDev, &DevTmp.config[0], false ); /** @todo fix bridge fun! */
1606
1607	pDev->Int.s.uIrqPinState = DevTmp.Int.s.uIrqPinState;
1608	}
1609
1610	return VINF_SUCCESS;
1611	}
1612
1613
1614	/**
1615	* Loads a saved PCI device state.
1616	*
1617	* @returns VBox status code.
1618	* @param pDevIns The device instance.
1619	* @param pSSM The handle to the saved state.
1620	* @param uVersion The data unit version number.
1621	* @param uPass The data pass.
1622	*/
1623	static DECLCALLBACK(int) pciR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1624	{
1625	PPCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
1626	PPCIBUS pBus = &pThis->PciBus;
1627	uint32_t u32;
1628	int rc;
1629
1630	/*
1631	* Check the version.
1632	*/
1633	if (uVersion > VBOX_PCI_SAVED_STATE_VERSION)
1634	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1635	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
1636
1637	/*
1638	* Bus state data.
1639	*/
1640	SSMR3GetU32(pSSM, &pThis->uConfigReg);
1641	if (uVersion > 1)
1642	SSMR3GetBool(pSSM, &pThis->fUseIoApic);
1643
1644	/* Load IRQ states. */
1645	if (uVersion > 2)
1646	{
1647	for (uint8_t i = 0; i < PCI_IRQ_PINS; i++)
1648	SSMR3GetU32(pSSM, (uint32_t *)&pThis->pci_irq_levels[i]);
1649	for (uint8_t i = 0; i < PCI_APIC_IRQ_PINS; i++)
1650	SSMR3GetU32(pSSM, (uint32_t *)&pThis->pci_apic_irq_levels[i]);
1651
1652	SSMR3GetU32(pSSM, &pThis->acpi_irq_level);
1653	SSMR3GetS32(pSSM, &pThis->acpi_irq);
1654	}
1655
1656	/* separator */
1657	rc = SSMR3GetU32(pSSM, &u32);
1658	if (RT_FAILURE(rc))
1659	return rc;
1660	if (u32 != (uint32_t)~0)
1661	AssertMsgFailedReturn(("u32=%#x\n", u32), rc);
1662
1663	/*
1664	* The devices.
1665	*/
1666	return pciR3CommonLoadExec(pBus, pSSM, uVersion, uPass);
1667	}
1668
1669
1670	/* -=-=-=-=-=- real code -=-=-=-=-=- */
1671
1672	/**
1673	* Registers the device with the specified PCI bus.
1674	*
1675	* @returns VBox status code.
1676	* @param pBus The bus to register with.
1677	* @param iDev The PCI device ordinal.
1678	* @param pPciDev The PCI device structure.
1679	* @param pszName Pointer to device name (permanent, readonly). For debugging, not unique.
1680	*/
1681	static int pciRegisterInternal(PPCIBUS pBus, int iDev, PPCIDEVICE pPciDev, const char *pszName)
1682	{
1683	/*
1684	* Find device slot.
1685	*/
1686	if (iDev < 0)
1687	{
1688	/*
1689	* Special check for the IDE controller which is our function 1 device
1690	* before searching.
1691	*/
1692	if ( !strcmp(pszName, "piix3ide")
1693	&& !pBus->devices[9])
1694	iDev = 9;
1695	#ifdef VBOX_WITH_LPC
1696	/* LPC bus expected to be there by some guests, better make an additional argument to PDM
1697	device helpers, but requires significant rewrite */
1698	else if (!strcmp(pszName, "lpc")
1699	&& !pBus->devices[0xf8])
1700	iDev = 0xf8;
1701	#endif
1702	else
1703	{
1704	Assert(!(pBus->iDevSearch % 8));
1705	for (iDev = pBus->iDevSearch; iDev < (int)RT_ELEMENTS(pBus->devices); iDev += 8)
1706	if ( !pBus->devices[iDev]
1707	&& !pBus->devices[iDev + 1]
1708	&& !pBus->devices[iDev + 2]
1709	&& !pBus->devices[iDev + 3]
1710	&& !pBus->devices[iDev + 4]
1711	&& !pBus->devices[iDev + 5]
1712	&& !pBus->devices[iDev + 6]
1713	&& !pBus->devices[iDev + 7])
1714	break;
1715	if (iDev >= (int)RT_ELEMENTS(pBus->devices))
1716	{
1717	AssertMsgFailed(("Couldn't find free spot!\n"));
1718	return VERR_PDM_TOO_PCI_MANY_DEVICES;
1719	}
1720	}
1721	pPciDev->Int.s.fRequestedDevFn = false;
1722	}
1723	else
1724	{
1725	/*
1726	* An explicit request.
1727	*
1728	* If the slot is occupied we'll have to relocate the device
1729	* currently occupying it first. This can only be done if the
1730	* existing device wasn't explicitly assigned. Also we limit
1731	* ourselves to function 0 devices.
1732	*
1733	* If you start setting devices + function in the
1734	* config, do it for all pci devices!
1735	*/
1736	//AssertReleaseMsg(iDev > 8 \|\| pBus->iBus != 0, ("iDev=%d pszName=%s\n", iDev, pszName));
1737	if (pBus->devices[iDev])
1738	{
1739	int iDevRel;
1740	AssertReleaseMsg(!(iDev % 8), ("PCI Configuration Conflict! iDev=%d pszName=%s clashes with %s\n",
1741	iDev, pszName, pBus->devices[iDev]->name));
1742	if ( pBus->devices[iDev]->Int.s.fRequestedDevFn
1743	\|\| (pBus->devices[iDev + 1] && pBus->devices[iDev + 1]->Int.s.fRequestedDevFn)
1744	\|\| (pBus->devices[iDev + 2] && pBus->devices[iDev + 2]->Int.s.fRequestedDevFn)
1745	\|\| (pBus->devices[iDev + 3] && pBus->devices[iDev + 3]->Int.s.fRequestedDevFn)
1746	\|\| (pBus->devices[iDev + 4] && pBus->devices[iDev + 4]->Int.s.fRequestedDevFn)
1747	\|\| (pBus->devices[iDev + 5] && pBus->devices[iDev + 5]->Int.s.fRequestedDevFn)
1748	\|\| (pBus->devices[iDev + 6] && pBus->devices[iDev + 6]->Int.s.fRequestedDevFn)
1749	\|\| (pBus->devices[iDev + 7] && pBus->devices[iDev + 7]->Int.s.fRequestedDevFn))
1750	{
1751	AssertReleaseMsgFailed(("Configuration error:'%s' and '%s' are both configured as device %d\n",
1752	pszName, pBus->devices[iDev]->name, iDev));
1753	return VERR_INTERNAL_ERROR;
1754	}
1755
1756	/* Find free slot for the device(s) we're moving and move them. */
1757	for (iDevRel = pBus->iDevSearch; iDevRel < (int)RT_ELEMENTS(pBus->devices); iDevRel += 8)
1758	{
1759	if ( !pBus->devices[iDevRel]
1760	&& !pBus->devices[iDevRel + 1]
1761	&& !pBus->devices[iDevRel + 2]
1762	&& !pBus->devices[iDevRel + 3]
1763	&& !pBus->devices[iDevRel + 4]
1764	&& !pBus->devices[iDevRel + 5]
1765	&& !pBus->devices[iDevRel + 6]
1766	&& !pBus->devices[iDevRel + 7])
1767	{
1768	int i = 0;
1769	for (i = 0; i < 8; i++)
1770	{
1771	if (!pBus->devices[iDev + i])
1772	continue;
1773	Log(("PCI: relocating '%s' from slot %#x to %#x\n", pBus->devices[iDev + i]->name, iDev + i, iDevRel + i));
1774	pBus->devices[iDevRel + i] = pBus->devices[iDev + i];
1775	pBus->devices[iDevRel + i]->devfn = i;
1776	pBus->devices[iDev + i] = NULL;
1777	}
1778	}
1779	}
1780	if (pBus->devices[iDev])
1781	{
1782	AssertMsgFailed(("Couldn't find free spot!\n"));
1783	return VERR_PDM_TOO_PCI_MANY_DEVICES;
1784	}
1785	} /* if conflict */
1786	pPciDev->Int.s.fRequestedDevFn = true;
1787	}
1788
1789	Assert(!pBus->devices[iDev]);
1790	pPciDev->devfn = iDev;
1791	pPciDev->name = pszName;
1792	pPciDev->Int.s.pBusR3 = pBus;
1793	pPciDev->Int.s.pBusR0 = MMHyperR3ToR0(PDMDevHlpGetVM(pBus->CTX_SUFF(pDevIns)), pBus);
1794	pPciDev->Int.s.pBusRC = MMHyperR3ToRC(PDMDevHlpGetVM(pBus->CTX_SUFF(pDevIns)), pBus);
1795	pPciDev->Int.s.pfnConfigRead = pci_default_read_config;
1796	pPciDev->Int.s.pfnConfigWrite = pci_default_write_config;
1797	pBus->devices[iDev] = pPciDev;
1798	if (pPciDev->Int.s.fPciToPciBridge)
1799	{
1800	AssertMsg(pBus->cBridges < RT_ELEMENTS(pBus->devices), ("Number of bridges exceeds the number of possible devices on the bus\n"));
1801	AssertMsg(pPciDev->Int.s.pfnBridgeConfigRead && pPciDev->Int.s.pfnBridgeConfigWrite,
1802	("device is a bridge but does not implement read/write functions\n"));
1803	pBus->papBridgesR3[pBus->cBridges] = pPciDev;
1804	pBus->cBridges++;
1805	}
1806
1807	Log(("PCI: Registered device %d function %d (%#x) '%s'.\n",
1808	iDev >> 3, iDev & 7, 0x80000000 \| (iDev << 8), pszName));
1809
1810	return VINF_SUCCESS;
1811	}
1812
1813
1814	/**
1815	* Registers the device with the default PCI bus.
1816	*
1817	* @returns VBox status code.
1818	* @param pDevIns Device instance of the PCI Bus.
1819	* @param pPciDev The PCI device structure.
1820	* Any PCI enabled device must keep this in it's instance data!
1821	* Fill in the PCI data config before registration, please.
1822	* @param pszName Pointer to device name (permanent, readonly). For debugging, not unique.
1823	* @param iDev The PCI device number. Use a negative value for auto assigning one.
1824	*/
1825	static DECLCALLBACK(int) pciRegister(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, const char *pszName, int iDev)
1826	{
1827	PPCIBUS pBus = DEVINS_2_PCIBUS(pDevIns);
1828
1829	/*
1830	* Check input.
1831	*/
1832	if ( !pszName
1833	\|\| !pPciDev
1834	\|\| iDev >= (int)RT_ELEMENTS(pBus->devices)
1835	\|\| (iDev >= 0 && iDev <= 8))
1836	{
1837	AssertMsgFailed(("Invalid argument! pszName=%s pPciDev=%p iDev=%d\n", pszName, pPciDev, iDev));
1838	return VERR_INVALID_PARAMETER;
1839	}
1840
1841	/*
1842	* Register the device.
1843	*/
1844	return pciRegisterInternal(pBus, iDev, pPciDev, pszName);
1845	}
1846
1847
1848	static DECLCALLBACK(int) pciIORegionRegister(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iRegion, uint32_t cbRegion, PCIADDRESSSPACE enmType, PFNPCIIOREGIONMAP pfnCallback)
1849	{
1850	/*
1851	* Validate.
1852	*/
1853	AssertMsgReturn( enmType == PCI_ADDRESS_SPACE_MEM
1854	\|\| enmType == PCI_ADDRESS_SPACE_IO
1855	\|\| enmType == PCI_ADDRESS_SPACE_MEM_PREFETCH,
1856	("Invalid enmType=%#x? Or was this a bitmask after all...\n", enmType),
1857	VERR_INVALID_PARAMETER);
1858	AssertMsgReturn((unsigned)iRegion < PCI_NUM_REGIONS,
1859	("Invalid iRegion=%d PCI_NUM_REGIONS=%d\n", iRegion, PCI_NUM_REGIONS),
1860	VERR_INVALID_PARAMETER);
1861	int iLastSet = ASMBitLastSetU32(cbRegion);
1862	AssertMsgReturn( iLastSet != 0
1863	&& RT_BIT_32(iLastSet - 1) == cbRegion,
1864	("Invalid cbRegion=%#x iLastSet=%#x (not a power of 2 or 0)\n", cbRegion, iLastSet),
1865	VERR_INVALID_PARAMETER);
1866
1867	/*
1868	* Register the I/O region.
1869	*/
1870	PPCIIOREGION pRegion = &pPciDev->Int.s.aIORegions[iRegion];
1871	pRegion->addr = ~0U;
1872	pRegion->size = cbRegion;
1873	pRegion->type = enmType;
1874	pRegion->map_func = pfnCallback;
1875
1876	/* Set type in the config space. */
1877	uint32_t u32Address = 0x10 + iRegion * 4;
1878	uint32_t u32Value = (enmType == PCI_ADDRESS_SPACE_MEM_PREFETCH ? (1 << 3) : 0)
1879	\| (enmType == PCI_ADDRESS_SPACE_IO ? 1 : 0);
1880	(uint32_t )(pPciDev->config + u32Address) = RT_H2LE_U32(u32Value);
1881
1882	return VINF_SUCCESS;
1883	}
1884
1885
1886	/**
1887	* @copydoc PDMPCIBUSREG::pfnSetConfigCallbacksR3
1888	*/
1889	static DECLCALLBACK(void) pciSetConfigCallbacks(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PFNPCICONFIGREAD pfnRead, PPFNPCICONFIGREAD ppfnReadOld,
1890	PFNPCICONFIGWRITE pfnWrite, PPFNPCICONFIGWRITE ppfnWriteOld)
1891	{
1892	if (ppfnReadOld)
1893	*ppfnReadOld = pPciDev->Int.s.pfnConfigRead;
1894	pPciDev->Int.s.pfnConfigRead = pfnRead;
1895
1896	if (ppfnWriteOld)
1897	*ppfnWriteOld = pPciDev->Int.s.pfnConfigWrite;
1898	pPciDev->Int.s.pfnConfigWrite = pfnWrite;
1899	}
1900
1901
1902	/**
1903	* Called to perform the job of the bios.
1904	*
1905	* @returns VBox status.
1906	* @param pDevIns Device instance of the first bus.
1907	*/
1908	static DECLCALLBACK(int) pciFakePCIBIOS(PPDMDEVINS pDevIns)
1909	{
1910	unsigned i;
1911	uint8_t elcr[2] = {0, 0};
1912	PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
1913	PVM pVM = PDMDevHlpGetVM(pDevIns);
1914	Assert(pVM);
1915
1916	/*
1917	* Set the start addresses.
1918	*/
1919	pGlobals->pci_bios_io_addr = 0xd000;
1920	pGlobals->pci_bios_mem_addr = UINT32_C(0xf0000000);
1921	pGlobals->uBus = 0;
1922
1923	/*
1924	* Activate IRQ mappings.
1925	*/
1926	for (i = 0; i < 4; i++)
1927	{
1928	uint8_t irq = pci_irqs[i];
1929	/* Set to trigger level. */
1930	elcr[irq >> 3] \|= (1 << (irq & 7));
1931	/* Activate irq remapping in PIIX3. */
1932	pci_config_writeb(pGlobals, 0, pGlobals->PIIX3State.dev.devfn, 0x60 + i, irq);
1933	}
1934
1935	/* Tell to the PIC. */
1936	VBOXSTRICTRC rcStrict = IOMIOPortWrite(pVM, 0x4d0, elcr[0], sizeof(uint8_t));
1937	if (rcStrict == VINF_SUCCESS)
1938	rcStrict = IOMIOPortWrite(pVM, 0x4d1, elcr[1], sizeof(uint8_t));
1939	if (rcStrict != VINF_SUCCESS)
1940	{
1941	AssertMsgFailed(("Writing to PIC failed! rcStrict=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
1942	return RT_SUCCESS(rcStrict) ? VERR_INTERNAL_ERROR : VBOXSTRICTRC_VAL(rcStrict);
1943	}
1944
1945	/*
1946	* Init the devices.
1947	*/
1948	for (i = 0; i < 256; i++)
1949	{
1950	uint8_t aBridgePositions[256];
1951
1952	memset(aBridgePositions, 0, sizeof(aBridgePositions));
1953	Log2(("PCI: Initializing device %d (%#x)\n",
1954	i, 0x80000000 \| (i << 8)));
1955	pci_bios_init_device(pGlobals, 0, i, 0, aBridgePositions);
1956	}
1957
1958	return VINF_SUCCESS;
1959	}
1960
1961	/**
1962	* @copydoc FNPDMDEVRELOCATE
1963	*/
1964	static DECLCALLBACK(void) pciRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
1965	{
1966	PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
1967	PPCIBUS pBus = &pGlobals->PciBus;
1968	pGlobals->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
1969
1970	pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
1971	pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
1972
1973	/* Relocate RC pointers for the attached pci devices. */
1974	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->devices); i++)
1975	{
1976	if (pBus->devices[i])
1977	pBus->devices[i]->Int.s.pBusRC += offDelta;
1978	}
1979	}
1980
1981
1982	/**
1983	* @interface_method_impl{PDMDEVREG,pfnConstruct}
1984	*/
1985	static DECLCALLBACK(int) pciConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
1986	{
1987	int rc;
1988	Assert(iInstance == 0);
1989
1990	/*
1991	* Validate and read configuration.
1992	*/
1993	if (!CFGMR3AreValuesValid(pCfg, "IOAPIC\0" "GCEnabled\0" "R0Enabled\0"))
1994	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
1995
1996	/* query whether we got an IOAPIC */
1997	bool fUseIoApic;
1998	rc = CFGMR3QueryBoolDef(pCfg, "IOAPIC", &fUseIoApic, false);
1999	if (RT_FAILURE(rc))
2000	return PDMDEV_SET_ERROR(pDevIns, rc,
2001	N_("Configuration error: Failed to query boolean value \"IOAPIC\""));
2002
2003	/* check if RC code is enabled. */
2004	bool fGCEnabled;
2005	rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
2006	if (RT_FAILURE(rc))
2007	return PDMDEV_SET_ERROR(pDevIns, rc,
2008	N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
2009
2010	/* check if R0 code is enabled. */
2011	bool fR0Enabled;
2012	rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
2013	if (RT_FAILURE(rc))
2014	return PDMDEV_SET_ERROR(pDevIns, rc,
2015	N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
2016	Log(("PCI: fUseIoApic=%RTbool fGCEnabled=%RTbool fR0Enabled=%RTbool\n", fUseIoApic, fGCEnabled, fR0Enabled));
2017
2018	/*
2019	* Init data and register the PCI bus.
2020	*/
2021	PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
2022	pGlobals->pci_bios_io_addr = 0xc000;
2023	pGlobals->pci_bios_mem_addr = 0xf0000000;
2024	memset((void *)&pGlobals->pci_irq_levels, 0, sizeof(pGlobals->pci_irq_levels));
2025	pGlobals->fUseIoApic = fUseIoApic;
2026	memset((void *)&pGlobals->pci_apic_irq_levels, 0, sizeof(pGlobals->pci_apic_irq_levels));
2027
2028	pGlobals->pDevInsR3 = pDevIns;
2029	pGlobals->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2030	pGlobals->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2031
2032	pGlobals->PciBus.pDevInsR3 = pDevIns;
2033	pGlobals->PciBus.pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2034	pGlobals->PciBus.pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2035	pGlobals->PciBus.papBridgesR3 = (PPCIDEVICE )PDMDevHlpMMHeapAllocZ(pDevIns, sizeof(PPCIDEVICE) RT_ELEMENTS(pGlobals->PciBus.devices));
2036
2037	PDMPCIBUSREG PciBusReg;
2038	PPCIBUS pBus = &pGlobals->PciBus;
2039	PciBusReg.u32Version = PDM_PCIBUSREG_VERSION;
2040	PciBusReg.pfnRegisterR3 = pciRegister;
2041	PciBusReg.pfnIORegionRegisterR3 = pciIORegionRegister;
2042	PciBusReg.pfnSetConfigCallbacksR3 = pciSetConfigCallbacks;
2043	PciBusReg.pfnSetIrqR3 = pciSetIrq;
2044	PciBusReg.pfnSaveExecR3 = pciGenericSaveExec;
2045	PciBusReg.pfnLoadExecR3 = pciGenericLoadExec;
2046	PciBusReg.pfnFakePCIBIOSR3 = pciFakePCIBIOS;
2047	PciBusReg.pszSetIrqRC = fGCEnabled ? "pciSetIrq" : NULL;
2048	PciBusReg.pszSetIrqR0 = fR0Enabled ? "pciSetIrq" : NULL;
2049	rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBus->pPciHlpR3);
2050	if (RT_FAILURE(rc))
2051	return PDMDEV_SET_ERROR(pDevIns, rc,
2052	N_("Failed to register ourselves as a PCI Bus"));
2053	if (pBus->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
2054	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
2055	N_("PCI helper version mismatch; got %#x expected %#x"),
2056	pBus->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION);
2057
2058	pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
2059	pBus->pPciHlpR0 = pBus->pPciHlpR3->pfnGetR0Helpers(pDevIns);
2060
2061	/*
2062	* Fill in PCI configs and add them to the bus.
2063	*/
2064	/* i440FX */
2065	PCIDevSetVendorId( &pBus->PciDev, 0x8086); /* Intel */
2066	PCIDevSetDeviceId( &pBus->PciDev, 0x1237);
2067	PCIDevSetRevisionId(&pBus->PciDev, 0x02);
2068	PCIDevSetClassSub( &pBus->PciDev, 0x00); /* host2pci */
2069	PCIDevSetClassBase( &pBus->PciDev, 0x06); /* PCI_bridge */
2070	PCIDevSetHeaderType(&pBus->PciDev, 0x00);
2071
2072	pBus->PciDev.pDevIns = pDevIns;
2073	pBus->PciDev.Int.s.fRequestedDevFn= true;
2074	pciRegisterInternal(pBus, 0, &pBus->PciDev, "i440FX");
2075
2076	/* PIIX3 */
2077	PCIDevSetVendorId( &pGlobals->PIIX3State.dev, 0x8086); /* Intel */
2078	PCIDevSetDeviceId( &pGlobals->PIIX3State.dev, 0x7000); /* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */
2079	PCIDevSetClassSub( &pGlobals->PIIX3State.dev, 0x01); /* PCI_ISA */
2080	PCIDevSetClassBase( &pGlobals->PIIX3State.dev, 0x06); /* PCI_bridge */
2081	PCIDevSetHeaderType(&pGlobals->PIIX3State.dev, 0x80); /* PCI_multifunction, generic */
2082
2083	pGlobals->PIIX3State.dev.pDevIns = pDevIns;
2084	pGlobals->PIIX3State.dev.Int.s.fRequestedDevFn= true;
2085	pciRegisterInternal(pBus, 8, &pGlobals->PIIX3State.dev, "PIIX3");
2086	piix3_reset(&pGlobals->PIIX3State);
2087
2088	pBus->iDevSearch = 16;
2089
2090	/*
2091	* Register I/O ports and save state.
2092	*/
2093	rc = PDMDevHlpIOPortRegister(pDevIns, 0x0cf8, 1, NULL, pciIOPortAddressWrite, pciIOPortAddressRead, NULL, NULL, "i440FX (PCI)");
2094	if (RT_FAILURE(rc))
2095	return rc;
2096	rc = PDMDevHlpIOPortRegister(pDevIns, 0x0cfc, 4, NULL, pciIOPortDataWrite, pciIOPortDataRead, NULL, NULL, "i440FX (PCI)");
2097	if (RT_FAILURE(rc))
2098	return rc;
2099	if (fGCEnabled)
2100	{
2101	rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x0cf8, 1, NIL_RTGCPTR, "pciIOPortAddressWrite", "pciIOPortAddressRead", NULL, NULL, "i440FX (PCI)");
2102	if (RT_FAILURE(rc))
2103	return rc;
2104	rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x0cfc, 4, NIL_RTGCPTR, "pciIOPortDataWrite", "pciIOPortDataRead", NULL, NULL, "i440FX (PCI)");
2105	if (RT_FAILURE(rc))
2106	return rc;
2107	}
2108	if (fR0Enabled)
2109	{
2110	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x0cf8, 1, NIL_RTR0PTR, "pciIOPortAddressWrite", "pciIOPortAddressRead", NULL, NULL, "i440FX (PCI)");
2111	if (RT_FAILURE(rc))
2112	return rc;
2113	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x0cfc, 4, NIL_RTR0PTR, "pciIOPortDataWrite", "pciIOPortDataRead", NULL, NULL, "i440FX (PCI)");
2114	if (RT_FAILURE(rc))
2115	return rc;
2116	}
2117
2118	rc = PDMDevHlpSSMRegisterEx(pDevIns, VBOX_PCI_SAVED_STATE_VERSION, sizeof(pBus) + 16128, "pgm",
2119	NULL, NULL, NULL,
2120	NULL, pciR3SaveExec, NULL,
2121	NULL, pciR3LoadExec, NULL);
2122	if (RT_FAILURE(rc))
2123	return rc;
2124
2125	return VINF_SUCCESS;
2126	}
2127
2128
2129	/**
2130	* The device registration structure.
2131	*/
2132	const PDMDEVREG g_DevicePCI =
2133	{
2134	/* u32Version */
2135	PDM_DEVREG_VERSION,
2136	/* szName */
2137	"pci",
2138	/* szRCMod */
2139	"VBoxDDGC.gc",
2140	/* szR0Mod */
2141	"VBoxDDR0.r0",
2142	/* pszDescription */
2143	"i440FX PCI bridge and PIIX3 ISA bridge.",
2144	/* fFlags */
2145	PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
2146	/* fClass */
2147	PDM_DEVREG_CLASS_BUS_PCI \| PDM_DEVREG_CLASS_BUS_ISA,
2148	/* cMaxInstances */
2149	1,
2150	/* cbInstance */
2151	sizeof(PCIGLOBALS),
2152	/* pfnConstruct */
2153	pciConstruct,
2154	/* pfnDestruct */
2155	NULL,
2156	/* pfnRelocate */
2157	pciRelocate,
2158	/* pfnIOCtl */
2159	NULL,
2160	/* pfnPowerOn */
2161	NULL,
2162	/* pfnReset */
2163	NULL,
2164	/* pfnSuspend */
2165	NULL,
2166	/* pfnResume */
2167	NULL,
2168	/* pfnAttach */
2169	NULL,
2170	/* pfnDetach */
2171	NULL,
2172	/* pfnQueryInterface */
2173	NULL,
2174	/* pfnInitComplete */
2175	NULL,
2176	/* pfnPowerOff */
2177	NULL,
2178	/* pfnSoftReset */
2179	NULL,
2180	/* u32VersionEnd */
2181	PDM_DEVREG_VERSION
2182
2183	};
2184	#endif /* IN_RING3 */
2185
2186
2187	/**
2188	* Set the IRQ for a PCI device on a secondary bus.
2189	*
2190	* @param pDevIns Device instance of the PCI Bus.
2191	* @param pPciDev The PCI device structure.
2192	* @param iIrq IRQ number to set.
2193	* @param iLevel IRQ level.
2194	*/
2195	PDMBOTHCBDECL(void) pcibridgeSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel)
2196	{
2197	/*
2198	* The PCI-to-PCI bridge specification defines how the interrupt pins
2199	* are routed from the secondary to the primary bus (see chapter 9).
2200	* iIrq gives the interrupt pin the pci device asserted.
2201	* We change iIrq here according to the spec and call the SetIrq function
2202	* of our parent passing the device which asserted the interrupt instead of the device of the bridge.
2203	*/
2204	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
2205	PPCIDEVICE pPciDevBus = pPciDev;
2206	int iIrqPinBridge = iIrq;
2207	uint8_t uDevFnBridge = 0;
2208
2209	/* Walk the chain until we reach the host bus. */
2210	do
2211	{
2212	uDevFnBridge = pBus->PciDev.devfn;
2213	iIrqPinBridge = ((pPciDevBus->devfn >> 3) + iIrqPinBridge) & 3;
2214
2215	/* Get the parent. */
2216	pBus = pBus->PciDev.Int.s.CTX_SUFF(pBus);
2217	pPciDevBus = &pBus->PciDev;
2218	} while (pBus->iBus != 0);
2219
2220	AssertMsg(pBus->iBus == 0, ("This is not the host pci bus iBus=%d\n", pBus->iBus));
2221	pciSetIrqInternal(PCIBUS_2_PCIGLOBALS(pBus), uDevFnBridge, pPciDev, iIrqPinBridge, iLevel);
2222	}
2223
2224	#ifdef IN_RING3
2225
2226	static void pcibridgeConfigWrite(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice, uint32_t u32Address, uint32_t u32Value, unsigned cb)
2227	{
2228	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
2229
2230	LogFlowFunc((": pDevIns=%p iBus=%d iDevice=%d u32Address=%u u32Value=%u cb=%d\n", pDevIns, iBus, iDevice, u32Address, u32Value, cb));
2231
2232	/* If the current bus is not the target bus search for the bus which contains the device. */
2233	if (iBus != pBus->PciDev.config[VBOX_PCI_SECONDARY_BUS])
2234	{
2235	PPCIDEVICE pBridgeDevice = pciFindBridge(pBus, iBus);
2236	if (pBridgeDevice)
2237	{
2238	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigWrite);
2239	pBridgeDevice->Int.s.pfnBridgeConfigWrite(pBridgeDevice->pDevIns, iBus, iDevice, u32Address, u32Value, cb);
2240	}
2241	}
2242	else
2243	{
2244	/* This is the target bus, pass the write to the device. */
2245	PPCIDEVICE pPciDev = pBus->devices[iDevice];
2246	if (pPciDev)
2247	{
2248	Log(("%s: %s: addr=%02x val=%08x len=%d\n", __FUNCTION__, pPciDev->name, u32Address, u32Value, cb));
2249	pPciDev->Int.s.pfnConfigWrite(pPciDev, u32Address, u32Value, cb);
2250	}
2251	}
2252	}
2253
2254	static uint32_t pcibridgeConfigRead(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice, uint32_t u32Address, unsigned cb)
2255	{
2256	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
2257	uint32_t u32Value = 0xffffffff; /* Return value in case there is no device. */
2258
2259	LogFlowFunc((": pDevIns=%p iBus=%d iDevice=%d u32Address=%u cb=%d\n", pDevIns, iBus, iDevice, u32Address, cb));
2260
2261	/* If the current bus is not the target bus search for the bus which contains the device. */
2262	if (iBus != pBus->PciDev.config[VBOX_PCI_SECONDARY_BUS])
2263	{
2264	PPCIDEVICE pBridgeDevice = pciFindBridge(pBus, iBus);
2265	if (pBridgeDevice)
2266	{
2267	AssertPtr( pBridgeDevice->Int.s.pfnBridgeConfigRead);
2268	u32Value = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->pDevIns, iBus, iDevice, u32Address, cb);
2269	}
2270	}
2271	else
2272	{
2273	/* This is the target bus, pass the read to the device. */
2274	PPCIDEVICE pPciDev = pBus->devices[iDevice];
2275	if (pPciDev)
2276	{
2277	u32Value = pPciDev->Int.s.pfnConfigRead(pPciDev, u32Address, cb);
2278	Log(("%s: %s: u32Address=%02x u32Value=%08x cb=%d\n", __FUNCTION__, pPciDev->name, u32Address, u32Value, cb));
2279	}
2280	}
2281
2282	return u32Value;
2283	}
2284
2285
2286	/**
2287	* @copydoc FNSSMDEVSAVEEXEC
2288	*/
2289	static DECLCALLBACK(int) pcibridgeR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
2290	{
2291	PPCIBUS pThis = PDMINS_2_DATA(pDevIns, PPCIBUS);
2292	return pciR3CommonSaveExec(pThis, pSSM);
2293	}
2294
2295
2296	/**
2297	* @copydoc FNSSMDEVLOADEXEC
2298	*/
2299	static DECLCALLBACK(int) pcibridgeR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2300	{
2301	PPCIBUS pThis = PDMINS_2_DATA(pDevIns, PPCIBUS);
2302	if (uVersion > VBOX_PCI_SAVED_STATE_VERSION)
2303	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2304	return pciR3CommonLoadExec(pThis, pSSM, uVersion, uPass);
2305	}
2306
2307
2308	/**
2309	* Registers the device with the default PCI bus.
2310	*
2311	* @returns VBox status code.
2312	* @param pDevIns Device instance of the PCI Bus.
2313	* @param pPciDev The PCI device structure.
2314	* Any PCI enabled device must keep this in it's instance data!
2315	* Fill in the PCI data config before registration, please.
2316	* @param pszName Pointer to device name (permanent, readonly). For debugging, not unique.
2317	* @param iDev The PCI device number. Use a negative value for auto assigning one.
2318	*/
2319	static DECLCALLBACK(int) pcibridgeRegister(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, const char *pszName, int iDev)
2320	{
2321	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
2322
2323	/*
2324	* Check input.
2325	*/
2326	if ( !pszName
2327	\|\| !pPciDev
2328	\|\| iDev >= (int)RT_ELEMENTS(pBus->devices))
2329	{
2330	AssertMsgFailed(("Invalid argument! pszName=%s pPciDev=%p iDev=%d\n", pszName, pPciDev, iDev));
2331	return VERR_INVALID_PARAMETER;
2332	}
2333
2334	/*
2335	* Register the device.
2336	*/
2337	return pciRegisterInternal(pBus, iDev, pPciDev, pszName);
2338	}
2339
2340
2341	/**
2342	* @copydoc FNPDMDEVRESET
2343	*/
2344	static DECLCALLBACK(void) pcibridgeReset(PPDMDEVINS pDevIns)
2345	{
2346	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
2347
2348	/* Reset config space to default values. */
2349	pBus->PciDev.config[VBOX_PCI_PRIMARY_BUS] = 0;
2350	pBus->PciDev.config[VBOX_PCI_SECONDARY_BUS] = 0;
2351	pBus->PciDev.config[VBOX_PCI_SUBORDINATE_BUS] = 0;
2352	}
2353
2354
2355	/**
2356	* @copydoc FNPDMDEVRELOCATE
2357	*/
2358	static DECLCALLBACK(void) pcibridgeRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
2359	{
2360	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
2361	pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2362
2363	/* Relocate RC pointers for the attached pci devices. */
2364	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->devices); i++)
2365	{
2366	if (pBus->devices[i])
2367	pBus->devices[i]->Int.s.pBusRC += offDelta;
2368	}
2369	}
2370
2371
2372	/**
2373	* @interface_method_impl{PDMDEVREG,pfnConstruct}
2374	*/
2375	static DECLCALLBACK(int) pcibridgeConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
2376	{
2377	int rc;
2378
2379	/*
2380	* Validate and read configuration.
2381	*/
2382	if (!CFGMR3AreValuesValid(pCfg, "GCEnabled\0" "R0Enabled\0"))
2383	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
2384
2385	/* check if RC code is enabled. */
2386	bool fGCEnabled;
2387	rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
2388	if (RT_FAILURE(rc))
2389	return PDMDEV_SET_ERROR(pDevIns, rc,
2390	N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
2391
2392	/* check if R0 code is enabled. */
2393	bool fR0Enabled;
2394	rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
2395	if (RT_FAILURE(rc))
2396	return PDMDEV_SET_ERROR(pDevIns, rc,
2397	N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
2398	Log(("PCI: fGCEnabled=%RTbool fR0Enabled=%RTbool\n", fGCEnabled, fR0Enabled));
2399
2400	/*
2401	* Init data and register the PCI bus.
2402	*/
2403	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
2404	pBus->pDevInsR3 = pDevIns;
2405	pBus->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2406	pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2407	pBus->papBridgesR3 = (PPCIDEVICE )PDMDevHlpMMHeapAllocZ(pDevIns, sizeof(PPCIDEVICE) RT_ELEMENTS(pBus->devices));
2408
2409	PDMPCIBUSREG PciBusReg;
2410	PciBusReg.u32Version = PDM_PCIBUSREG_VERSION;
2411	PciBusReg.pfnRegisterR3 = pcibridgeRegister;
2412	PciBusReg.pfnIORegionRegisterR3 = pciIORegionRegister;
2413	PciBusReg.pfnSetConfigCallbacksR3 = pciSetConfigCallbacks;
2414	PciBusReg.pfnSetIrqR3 = pcibridgeSetIrq;
2415	PciBusReg.pfnSaveExecR3 = pciGenericSaveExec;
2416	PciBusReg.pfnLoadExecR3 = pciGenericLoadExec;
2417	PciBusReg.pfnFakePCIBIOSR3 = NULL; /* Only needed for the first bus. */
2418	PciBusReg.pszSetIrqRC = fGCEnabled ? "pcibridgeSetIrq" : NULL;
2419	PciBusReg.pszSetIrqR0 = fR0Enabled ? "pcibridgeSetIrq" : NULL;
2420	rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBus->pPciHlpR3);
2421	if (RT_FAILURE(rc))
2422	return PDMDEV_SET_ERROR(pDevIns, rc,
2423	N_("Failed to register ourselves as a PCI Bus"));
2424	if (pBus->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
2425	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
2426	N_("PCI helper version mismatch; got %#x expected %#x"),
2427	pBus->pPciHlpR3->u32Version, PDM_PCIHLPR3_VERSION);
2428
2429	pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
2430	pBus->pPciHlpR0 = pBus->pPciHlpR3->pfnGetR0Helpers(pDevIns);
2431
2432	/*
2433	* Fill in PCI configs and add them to the bus.
2434	*/
2435	PCIDevSetVendorId( &pBus->PciDev, 0x8086); /* Intel */
2436	PCIDevSetDeviceId( &pBus->PciDev, 0x2448); /* 82801 Mobile PCI bridge. */
2437	PCIDevSetRevisionId(&pBus->PciDev, 0xf2);
2438	PCIDevSetClassSub( &pBus->PciDev, 0x04); /* pci2pci */
2439	PCIDevSetClassBase( &pBus->PciDev, 0x06); /* PCI_bridge */
2440	PCIDevSetClassProg( &pBus->PciDev, 0x01); /* Supports subtractive decoding. */
2441	PCIDevSetHeaderType(&pBus->PciDev, 0x01); /* Single function device which adheres to the PCI-to-PCI bridge spec. */
2442	PCIDevSetCommand( &pBus->PciDev, 0x00);
2443	PCIDevSetStatus( &pBus->PciDev, 0x20); /* 66MHz Capable. */
2444	PCIDevSetInterruptLine(&pBus->PciDev, 0x00); /* This device does not assert interrupts. */
2445
2446	/*
2447	* This device does not generate interrupts. Interrupt delivery from
2448	* devices attached to the bus is unaffected.
2449	*/
2450	PCIDevSetInterruptPin (&pBus->PciDev, 0x00);
2451
2452	pBus->PciDev.pDevIns = pDevIns;
2453	pBus->PciDev.Int.s.fPciToPciBridge = true;
2454	pBus->PciDev.Int.s.pfnBridgeConfigRead = pcibridgeConfigRead;
2455	pBus->PciDev.Int.s.pfnBridgeConfigWrite = pcibridgeConfigWrite;
2456
2457	/*
2458	* Register this PCI bridge. The called function will take care on which bus we will get registered.
2459	*/
2460	rc = PDMDevHlpPCIRegister (pDevIns, &pBus->PciDev);
2461	if (RT_FAILURE(rc))
2462	return rc;
2463
2464	pBus->iDevSearch = 0;
2465	/*
2466	* The iBus property doesn't really represent the bus number
2467	* because the guest and the BIOS can choose different bus numbers
2468	* for them.
2469	* The bus number is mainly for the setIrq function to indicate
2470	* when the host bus is reached which will have iBus = 0.
2471	* Thathswhy the + 1.
2472	*/
2473	pBus->iBus = iInstance + 1;
2474
2475	/*
2476	* Register SSM handlers. We use the same saved state version as for the host bridge
2477	* to make changes easier.
2478	*/
2479	rc = PDMDevHlpSSMRegisterEx(pDevIns, VBOX_PCI_SAVED_STATE_VERSION, sizeof(pBus) + 16128, "pgm",
2480	NULL, NULL, NULL,
2481	NULL, pcibridgeR3SaveExec, NULL,
2482	NULL, pcibridgeR3LoadExec, NULL);
2483	if (RT_FAILURE(rc))
2484	return rc;
2485
2486	return VINF_SUCCESS;
2487	}
2488
2489
2490	/**
2491	* The device registration structure
2492	* for the PCI-to-PCI bridge.
2493	*/
2494	const PDMDEVREG g_DevicePCIBridge =
2495	{
2496	/* u32Version */
2497	PDM_DEVREG_VERSION,
2498	/* szName */
2499	"pcibridge",
2500	/* szRCMod */
2501	"VBoxDDGC.gc",
2502	/* szR0Mod */
2503	"VBoxDDR0.r0",
2504	/* pszDescription */
2505	"82801 Mobile PCI to PCI bridge",
2506	/* fFlags */
2507	PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
2508	/* fClass */
2509	PDM_DEVREG_CLASS_BUS_PCI,
2510	/* cMaxInstances */
2511	~0,
2512	/* cbInstance */
2513	sizeof(PCIBUS),
2514	/* pfnConstruct */
2515	pcibridgeConstruct,
2516	/* pfnDestruct */
2517	NULL,
2518	/* pfnRelocate */
2519	pcibridgeRelocate,
2520	/* pfnIOCtl */
2521	NULL,
2522	/* pfnPowerOn */
2523	NULL,
2524	/* pfnReset */
2525	pcibridgeReset,
2526	/* pfnSuspend */
2527	NULL,
2528	/* pfnResume */
2529	NULL,
2530	/* pfnAttach */
2531	NULL,
2532	/* pfnDetach */
2533	NULL,
2534	/* pfnQueryInterface */
2535	NULL,
2536	/* pfnInitComplete */
2537	NULL,
2538	/* pfnPowerOff */
2539	NULL,
2540	/* pfnSoftReset */
2541	NULL,
2542	/* u32VersionEnd */
2543	PDM_DEVREG_VERSION
2544	};
2545
2546	#endif /* IN_RING3 */
2547	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */

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source: vbox/trunk/src/VBox/Devices/Bus/DevPCI.cpp@ 28185

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