DevPCI.cpp@ 38852

Last change on this file since 38852 was 38852, checked in by vboxsync, 13 years ago
DevPCI.cpp: PDM provides locking via the helper interface, make the device critical section a NOP.
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1	/* $Id: DevPCI.cpp 38852 2011-09-23 14:02:30Z vboxsync $ */
2	/** @file
3	* DevPCI - PCI BUS Device.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	* --------------------------------------------------------------------
17	*
18	* This code is based on:
19	*
20	* QEMU PCI bus manager
21	*
22	* Copyright (c) 2004 Fabrice Bellard
23	*
24	* Permission is hereby granted, free of charge, to any person obtaining a copy
25	* of this software and associated documentation files (the "Software"), to deal
26	* in the Software without restriction, including without limitation the rights
27	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
28	* copies of the Software, and to permit persons to whom the Software is
29	* furnished to do so, subject to the following conditions:
30	*
31	* The above copyright notice and this permission notice shall be included in
32	* all copies or substantial portions of the Software.
33	*
34	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
35	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
36	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
37	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
38	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
39	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
40	* THE SOFTWARE.
41	*/
42
43	/*******************************************************************************
44	* Header Files *
45	*******************************************************************************/
46	#define LOG_GROUP LOG_GROUP_DEV_PCI
47	/* Hack to get PCIDEVICEINT declare at the right point - include "PCIInternal.h". */
48	#define PCI_INCLUDE_PRIVATE
49	#include <VBox/pci.h>
50	#include <VBox/vmm/pdmdev.h>
51	#include <iprt/asm.h>
52	#include <iprt/assert.h>
53	#include <iprt/string.h>
54
55	#include "VBoxDD.h"
56
57
58	/*******************************************************************************
59	* Structures and Typedefs *
60	*******************************************************************************/
61	/**
62	* PIIX3 ISA Bridge state.
63	*/
64	typedef struct PIIX3State
65	{
66	/** The PCI device of the bridge. */
67	PCIDEVICE dev;
68	} PIIX3State, PIIX3, *PPIIX3;
69
70	/**
71	* PCI Bus instance.
72	*/
73	typedef struct PCIBus
74	{
75	/** Bus number. */
76	int32_t iBus;
77	/** Start device number. */
78	int32_t iDevSearch;
79	/** Number of bridges attached to the bus. */
80	uint32_t cBridges;
81
82	uint32_t Alignment0;
83
84	/** Array of PCI devices. */
85	R3PTRTYPE(PPCIDEVICE) devices[256];
86	/** Array of bridges attached to the bus. */
87	R3PTRTYPE(PPCIDEVICE *) papBridgesR3;
88
89	/** R3 pointer to the device instance. */
90	PPDMDEVINSR3 pDevInsR3;
91	/** Pointer to the PCI R3 helpers. */
92	PCPDMPCIHLPR3 pPciHlpR3;
93
94	/** R0 pointer to the device instance. */
95	PPDMDEVINSR0 pDevInsR0;
96	/** Pointer to the PCI R0 helpers. */
97	PCPDMPCIHLPR0 pPciHlpR0;
98
99	/** RC pointer to the device instance. */
100	PPDMDEVINSRC pDevInsRC;
101	/** Pointer to the PCI RC helpers. */
102	PCPDMPCIHLPRC pPciHlpRC;
103
104	/** The PCI device for the PCI bridge. */
105	PCIDEVICE PciDev;
106
107	} PCIBUS;
108	/** Pointer to a PCIBUS instance. */
109	typedef PCIBUS *PPCIBUS;
110	typedef PCIBUS PCIBus;
111
112	/** @def PCI_IRQ_PINS
113	* Number of pins for interrupts (PIRQ#0...PIRQ#3)
114	*/
115	#define PCI_IRQ_PINS 4
116
117	/** @def PCI_APIC_IRQ_PINS
118	* Number of pins for interrupts if the APIC is used.
119	*/
120	#define PCI_APIC_IRQ_PINS 8
121
122	/**
123	* PCI Globals - This is the host-to-pci bridge and the root bus.
124	*/
125	typedef struct PCIGLOBALS
126	{
127	/** Irq levels for the four PCI Irqs.
128	* These count how many devices asserted
129	* the IRQ line. If greater 0 an IRQ is sent to the guest.
130	* If it drops to 0 the IRQ is deasserted.
131	*/
132	volatile uint32_t pci_irq_levels[PCI_IRQ_PINS];
133
134	#if 1 /* Will be moved into the BIOS soon. */
135	/** The next I/O port address which the PCI BIOS will use. */
136	uint32_t pci_bios_io_addr;
137	/** The next MMIO address which the PCI BIOS will use. */
138	uint32_t pci_bios_mem_addr;
139	/** Actual bus number. */
140	uint8_t uBus;
141	#endif
142
143	/** I/O APIC usage flag */
144	bool fUseIoApic;
145	/** I/O APIC irq levels */
146	volatile uint32_t pci_apic_irq_levels[PCI_APIC_IRQ_PINS];
147	/** ACPI IRQ level */
148	uint32_t acpi_irq_level;
149	/** ACPI PIC IRQ */
150	int acpi_irq;
151	/** Config register. */
152	uint32_t uConfigReg;
153
154	/** R3 pointer to the device instance. */
155	PPDMDEVINSR3 pDevInsR3;
156	/** R0 pointer to the device instance. */
157	PPDMDEVINSR0 pDevInsR0;
158	/** RC pointer to the device instance. */
159	PPDMDEVINSRC pDevInsRC;
160
161	#if HC_ARCH_BITS == 64
162	uint32_t Alignment0;
163	#endif
164
165	/** ISA bridge state. */
166	PIIX3 PIIX3State;
167	/** PCI bus which is attached to the host-to-PCI bridge. */
168	PCIBUS PciBus;
169
170	} PCIGLOBALS;
171	/** Pointer to per VM data. */
172	typedef PCIGLOBALS *PPCIGLOBALS;
173
174
175	/*******************************************************************************
176	* Defined Constants And Macros *
177	*******************************************************************************/
178
179	/** Converts a bus instance pointer to a device instance pointer. */
180	#define PCIBUS_2_DEVINS(pPciBus) ((pPciBus)->CTX_SUFF(pDevIns))
181	/** Converts a device instance pointer to a PCIGLOBALS pointer. */
182	#define DEVINS_2_PCIGLOBALS(pDevIns) ((PPCIGLOBALS)(PDMINS_2_DATA(pDevIns, PPCIGLOBALS)))
183	/** Converts a device instance pointer to a PCIBUS pointer. */
184	#define DEVINS_2_PCIBUS(pDevIns) ((PPCIBUS)(&PDMINS_2_DATA(pDevIns, PPCIGLOBALS)->PciBus))
185
186	/** Converts a pointer to a PCI bus instance to a PCIGLOBALS pointer.
187	* @note This works only if the bus number is 0!!!
188	*/
189	#define PCIBUS_2_PCIGLOBALS(pPciBus) ( (PPCIGLOBALS)((uintptr_t)(pPciBus) - RT_OFFSETOF(PCIGLOBALS, PciBus)) )
190
191	/** @def PCI_LOCK
192	* Acquires the PDM lock. This is a NOP if locking is disabled. */
193	/** @def PCI_UNLOCK
194	* Releases the PDM lock. This is a NOP if locking is disabled. */
195	#define PCI_LOCK(pDevIns, rc) \
196	do { \
197	int rc2 = DEVINS_2_PCIBUS(pDevIns)->CTX_SUFF(pPciHlp)->pfnLock((pDevIns), rc); \
198	if (rc2 != VINF_SUCCESS) \
199	return rc2; \
200	} while (0)
201	#define PCI_UNLOCK(pDevIns) \
202	DEVINS_2_PCIBUS(pDevIns)->CTX_SUFF(pPciHlp)->pfnUnlock(pDevIns)
203
204	/** @def VBOX_PCI_SAVED_STATE_VERSION
205	* Saved state version of the PCI bus device.
206	*/
207	#define VBOX_PCI_SAVED_STATE_VERSION 3
208
209
210	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
211	/*******************************************************************************
212	* Internal Functions *
213	*******************************************************************************/
214	RT_C_DECLS_BEGIN
215
216	PDMBOTHCBDECL(void) pciSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel);
217	PDMBOTHCBDECL(void) pcibridgeSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel);
218	PDMBOTHCBDECL(int) pciIOPortAddressWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
219	PDMBOTHCBDECL(int) pciIOPortAddressRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb);
220	PDMBOTHCBDECL(int) pciIOPortDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
221	PDMBOTHCBDECL(int) pciIOPortDataRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb);
222
223	#ifdef IN_RING3
224	DECLINLINE(PPCIDEVICE) pciFindBridge(PPCIBUS pBus, uint8_t iBus);
225	#endif
226
227	RT_C_DECLS_END
228
229	#define DEBUG_PCI
230
231	#define PCI_VENDOR_ID 0x00 /* 16 bits */
232	#define PCI_DEVICE_ID 0x02 /* 16 bits */
233	#define PCI_COMMAND 0x04 /* 16 bits */
234	#define PCI_COMMAND_IO 0x01 /* Enable response in I/O space */
235	#define PCI_COMMAND_MEMORY 0x02 /* Enable response in Memory space */
236	#define PCI_CLASS_DEVICE 0x0a /* Device class */
237	#define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
238	#define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
239	#define PCI_MIN_GNT 0x3e /* 8 bits */
240	#define PCI_MAX_LAT 0x3f /* 8 bits */
241
242
243	#ifdef IN_RING3
244
245	static void pci_update_mappings(PCIDevice *d)
246	{
247	PPCIBUS pBus = d->Int.s.CTX_SUFF(pBus);
248	PCIIORegion *r;
249	int cmd, i;
250	uint32_t last_addr, new_addr, config_ofs;
251
252	cmd = RT_LE2H_U16((uint16_t )(d->config + PCI_COMMAND));
253	for(i = 0; i < PCI_NUM_REGIONS; i++) {
254	r = &d->Int.s.aIORegions[i];
255	if (i == PCI_ROM_SLOT) {
256	config_ofs = 0x30;
257	} else {
258	config_ofs = 0x10 + i * 4;
259	}
260	if (r->size != 0) {
261	if (r->type & PCI_ADDRESS_SPACE_IO) {
262	if (cmd & PCI_COMMAND_IO) {
263	new_addr = RT_LE2H_U32((uint32_t )(d->config +
264	config_ofs));
265	new_addr = new_addr & ~(r->size - 1);
266	last_addr = new_addr + r->size - 1;
267	/* NOTE: we have only 64K ioports on PC */
268	if (last_addr <= new_addr \|\| new_addr == 0 \|\|
269	last_addr >= 0x10000) {
270	new_addr = ~0U;
271	}
272	} else {
273	new_addr = ~0U;
274	}
275	} else {
276	if (cmd & PCI_COMMAND_MEMORY) {
277	new_addr = RT_LE2H_U32((uint32_t )(d->config +
278	config_ofs));
279	/* the ROM slot has a specific enable bit */
280	if (i == PCI_ROM_SLOT && !(new_addr & 1))
281	goto no_mem_map;
282	new_addr = new_addr & ~(r->size - 1);
283	last_addr = new_addr + r->size - 1;
284	/* NOTE: we do not support wrapping */
285	/* XXX: as we cannot support really dynamic
286	mappings, we handle specific values as invalid
287	mappings. */
288	if (last_addr <= new_addr \|\| new_addr == 0 \|\|
289	last_addr == ~0U) {
290	new_addr = ~0U;
291	}
292	} else {
293	no_mem_map:
294	new_addr = ~0U;
295	}
296	}
297	/* now do the real mapping */
298	if (new_addr != r->addr) {
299	if (r->addr != ~0U) {
300	if (r->type & PCI_ADDRESS_SPACE_IO) {
301	int devclass;
302	/* NOTE: specific hack for IDE in PC case:
303	only one byte must be mapped. */
304	devclass = d->config[0x0a] \| (d->config[0x0b] << 8);
305	if (devclass == 0x0101 && r->size == 4) {
306	int rc = PDMDevHlpIOPortDeregister(d->pDevIns, r->addr + 2, 1);
307	AssertRC(rc);
308	} else {
309	int rc = PDMDevHlpIOPortDeregister(d->pDevIns, r->addr, r->size);
310	AssertRC(rc);
311	}
312	} else {
313	RTGCPHYS GCPhysBase = r->addr;
314	int rc;
315	if (pBus->pPciHlpR3->pfnIsMMIO2Base(pBus->pDevInsR3, d->pDevIns, GCPhysBase))
316	{
317	/* unmap it. */
318	rc = r->map_func(d, i, NIL_RTGCPHYS, r->size, (PCIADDRESSSPACE)(r->type));
319	AssertRC(rc);
320	rc = PDMDevHlpMMIO2Unmap(d->pDevIns, i, GCPhysBase);
321	}
322	else
323	rc = PDMDevHlpMMIODeregister(d->pDevIns, GCPhysBase, r->size);
324	AssertMsgRC(rc, ("rc=%Rrc d=%s i=%d GCPhysBase=%RGp size=%#x\n", rc, d->name, i, GCPhysBase, r->size));
325	}
326	}
327	r->addr = new_addr;
328	if (r->addr != ~0U) {
329	int rc = r->map_func(d, i,
330	r->addr + (r->type & PCI_ADDRESS_SPACE_IO ? 0 : 0),
331	r->size, (PCIADDRESSSPACE)(r->type));
332	AssertRC(rc);
333	}
334	}
335	}
336	}
337	}
338
339
340	static DECLCALLBACK(uint32_t) pci_default_read_config(PCIDevice *d, uint32_t address, unsigned len)
341	{
342	uint32_t val;
343	switch(len) {
344	case 1:
345	val = d->config[address];
346	break;
347	case 2:
348	val = RT_LE2H_U16((uint16_t )(d->config + address));
349	break;
350	default:
351	case 4:
352	val = RT_LE2H_U32((uint32_t )(d->config + address));
353	break;
354	}
355	return val;
356	}
357
358	static DECLCALLBACK(void) pci_default_write_config(PCIDevice *d, uint32_t address, uint32_t val, unsigned len)
359	{
360	int can_write;
361	unsigned i;
362	uint32_t end, addr;
363
364	if (len == 4 && ((address >= 0x10 && address < 0x10 + 4 * 6) \|\|
365	(address >= 0x30 && address < 0x34))) {
366	PCIIORegion *r;
367	int reg;
368
369	if ( address >= 0x30 ) {
370	reg = PCI_ROM_SLOT;
371	}else{
372	reg = (address - 0x10) >> 2;
373	}
374	r = &d->Int.s.aIORegions[reg];
375	if (r->size == 0)
376	goto default_config;
377	/* compute the stored value */
378	if (reg == PCI_ROM_SLOT) {
379	/* keep ROM enable bit */
380	val &= (~(r->size - 1)) \| 1;
381	} else {
382	val &= ~(r->size - 1);
383	val \|= r->type;
384	}
385	(uint32_t )(d->config + address) = RT_H2LE_U32(val);
386	pci_update_mappings(d);
387	return;
388	}
389	default_config:
390	/* not efficient, but simple */
391	addr = address;
392	for(i = 0; i < len; i++) {
393	/* default read/write accesses */
394	switch(d->config[0x0e]) {
395	case 0x00: /* normal device */
396	case 0x80: /* multi-function device */
397	switch(addr) {
398	case 0x00:
399	case 0x01:
400	case 0x02:
401	case 0x03:
402	case 0x08:
403	case 0x09:
404	case 0x0a:
405	case 0x0b:
406	case 0x0e:
407	case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17: /* base */
408	case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f:
409	case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27:
410	case 0x2c: case 0x2d: /* subsystem ID */
411	case 0x2e: case 0x2f: /* vendor ID */
412	case 0x30: case 0x31: case 0x32: case 0x33: /* rom */
413	case 0x34: /* Capabilities pointer. */
414	case 0x3d: /* Interrupt pin. */
415	can_write = 0;
416	break;
417	default:
418	can_write = 1;
419	break;
420	}
421	break;
422	default:
423	case 0x01: /* bridge */
424	switch(addr) {
425	case 0x00:
426	case 0x01:
427	case 0x02:
428	case 0x03:
429	case 0x08:
430	case 0x09:
431	case 0x0a:
432	case 0x0b:
433	case 0x0e:
434	case 0x38: case 0x39: case 0x3a: case 0x3b: /* rom */
435	case 0x3d:
436	can_write = 0;
437	break;
438	default:
439	can_write = 1;
440	break;
441	}
442	break;
443	}
444	#ifdef VBOX
445	if (addr == 0x05) /* Command register, bits 8-15. */
446	{
447	/* don't change reserved bits (11-15) */
448	val &= UINT32_C(~0xf8);
449	d->config[addr] = val;
450	}
451	else if (addr == 0x06) /* Status register, bits 0-7. */
452	{
453	/* don't change read-only bits => actually all lower bits are read-only */
454	val &= UINT32_C(~0xff);
455	/* status register, low part: clear bits by writing a '1' to the corresponding bit */
456	d->config[addr] &= ~val;
457	}
458	else if (addr == 0x07) /* Status register, bits 8-15. */
459	{
460	/* don't change read-only bits */
461	val &= UINT32_C(~0x06);
462	/* status register, high part: clear bits by writing a '1' to the corresponding bit */
463	d->config[addr] &= ~val;
464	}
465	else
466	#endif
467	if (can_write) {
468	d->config[addr] = val;
469	}
470	addr++;
471	val >>= 8;
472	}
473
474	end = address + len;
475	if (end > PCI_COMMAND && address < (PCI_COMMAND + 2)) {
476	/* if the command register is modified, we must modify the mappings */
477	pci_update_mappings(d);
478	}
479	}
480
481	#endif /* IN_RING3 */
482
483	static int pci_data_write(PPCIGLOBALS pGlobals, uint32_t addr, uint32_t val, int len)
484	{
485	uint8_t iBus, iDevice;
486	uint32_t config_addr;
487
488	Log(("pci_data_write: addr=%08x val=%08x len=%d\n", pGlobals->uConfigReg, val, len));
489
490	if (!(pGlobals->uConfigReg & (1 << 31))) {
491	return VINF_SUCCESS;
492	}
493	if ((pGlobals->uConfigReg & 0x3) != 0) {
494	return VINF_SUCCESS;
495	}
496	iBus = (pGlobals->uConfigReg >> 16) & 0xff;
497	iDevice = (pGlobals->uConfigReg >> 8) & 0xff;
498	config_addr = (pGlobals->uConfigReg & 0xfc) \| (addr & 3);
499	if (iBus != 0)
500	{
501	if (pGlobals->PciBus.cBridges)
502	{
503	#ifdef IN_RING3 /** @todo do lookup in R0/RC too! */
504	PPCIDEVICE pBridgeDevice = pciFindBridge(&pGlobals->PciBus, iBus);
505	if (pBridgeDevice)
506	{
507	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigWrite);
508	pBridgeDevice->Int.s.pfnBridgeConfigWrite(pBridgeDevice->pDevIns, iBus, iDevice, config_addr, val, len);
509	}
510	#else
511	return VINF_IOM_HC_IOPORT_WRITE;
512	#endif
513	}
514	}
515	else
516	{
517	R3PTRTYPE(PCIDevice *) pci_dev = pGlobals->PciBus.devices[iDevice];
518	if (pci_dev)
519	{
520	#ifdef IN_RING3
521	Log(("pci_config_write: %s: addr=%02x val=%08x len=%d\n", pci_dev->name, config_addr, val, len));
522	pci_dev->Int.s.pfnConfigWrite(pci_dev, config_addr, val, len);
523	#else
524	return VINF_IOM_HC_IOPORT_WRITE;
525	#endif
526	}
527	}
528	return VINF_SUCCESS;
529	}
530
531	static int pci_data_read(PPCIGLOBALS pGlobals, uint32_t addr, int len, uint32_t *pu32)
532	{
533	uint8_t iBus, iDevice;
534	uint32_t config_addr;
535
536	*pu32 = 0xffffffff;
537
538	if (!(pGlobals->uConfigReg & (1 << 31)))
539	return VINF_SUCCESS;
540	if ((pGlobals->uConfigReg & 0x3) != 0)
541	return VINF_SUCCESS;
542	iBus = (pGlobals->uConfigReg >> 16) & 0xff;
543	iDevice = (pGlobals->uConfigReg >> 8) & 0xff;
544	config_addr = (pGlobals->uConfigReg & 0xfc) \| (addr & 3);
545	if (iBus != 0)
546	{
547	if (pGlobals->PciBus.cBridges)
548	{
549	#ifdef IN_RING3 /** @todo do lookup in R0/RC too! */
550	PPCIDEVICE pBridgeDevice = pciFindBridge(&pGlobals->PciBus, iBus);
551	if (pBridgeDevice)
552	{
553	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigRead);
554	*pu32 = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->pDevIns, iBus, iDevice, config_addr, len);
555	}
556	#else
557	return VINF_IOM_HC_IOPORT_READ;
558	#endif
559	}
560	}
561	else
562	{
563	R3PTRTYPE(PCIDevice *) pci_dev = pGlobals->PciBus.devices[iDevice];
564	if (pci_dev)
565	{
566	#ifdef IN_RING3
567	*pu32 = pci_dev->Int.s.pfnConfigRead(pci_dev, config_addr, len);
568	Log(("pci_config_read: %s: addr=%02x val=%08x len=%d\n", pci_dev->name, config_addr, *pu32, len));
569	#else
570	return VINF_IOM_HC_IOPORT_READ;
571	#endif
572	}
573	}
574
575	return VINF_SUCCESS;
576	}
577
578
579
580	/* return the global irq number corresponding to a given device irq
581	pin. We could also use the bus number to have a more precise
582	mapping.
583	This is the implementation note described in the PCI spec chapter 2.2.6 */
584	static inline int pci_slot_get_pirq(uint8_t uDevFn, int irq_num)
585	{
586	int slot_addend;
587	slot_addend = (uDevFn >> 3) - 1;
588	return (irq_num + slot_addend) & 3;
589	}
590
591	static inline int pci_slot_get_apic_pirq(uint8_t uDevFn, int irq_num)
592	{
593	return (irq_num + (uDevFn >> 3)) & 7;
594	}
595
596	static inline int get_pci_irq_apic_level(PPCIGLOBALS pGlobals, int irq_num)
597	{
598	return (pGlobals->pci_apic_irq_levels[irq_num] != 0);
599	}
600
601	static void apic_set_irq(PPCIBUS pBus, uint8_t uDevFn, PCIDevice *pPciDev, int irq_num1, int iLevel, int acpi_irq)
602	{
603	/* This is only allowed to be called with a pointer to the host bus. */
604	AssertMsg(pBus->iBus == 0, ("iBus=%u\n", pBus->iBus));
605
606	if (acpi_irq == -1) {
607	int apic_irq, apic_level;
608	PPCIGLOBALS pGlobals = PCIBUS_2_PCIGLOBALS(pBus);
609	int irq_num = pci_slot_get_apic_pirq(uDevFn, irq_num1);
610
611	if ((iLevel & PDM_IRQ_LEVEL_HIGH) == PDM_IRQ_LEVEL_HIGH)
612	ASMAtomicIncU32(&pGlobals->pci_apic_irq_levels[irq_num]);
613	else if ((iLevel & PDM_IRQ_LEVEL_HIGH) == PDM_IRQ_LEVEL_LOW)
614	ASMAtomicDecU32(&pGlobals->pci_apic_irq_levels[irq_num]);
615
616	apic_irq = irq_num + 0x10;
617	apic_level = get_pci_irq_apic_level(pGlobals, irq_num);
618	Log3(("apic_set_irq: %s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d\n",
619	R3STRING(pPciDev->name), irq_num1, iLevel, apic_irq, apic_level, irq_num));
620	pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), apic_irq, apic_level);
621
622	if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP) {
623	ASMAtomicDecU32(&pGlobals->pci_apic_irq_levels[irq_num]);
624	pPciDev->Int.s.uIrqPinState = PDM_IRQ_LEVEL_LOW;
625	apic_level = get_pci_irq_apic_level(pGlobals, irq_num);
626	Log3(("apic_set_irq: %s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d (flop)\n",
627	R3STRING(pPciDev->name), irq_num1, iLevel, apic_irq, apic_level, irq_num));
628	pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), apic_irq, apic_level);
629	}
630	} else {
631	Log3(("apic_set_irq: %s: irq_num1=%d level=%d acpi_irq=%d\n",
632	R3STRING(pPciDev->name), irq_num1, iLevel, acpi_irq));
633	pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), acpi_irq, iLevel);
634	}
635	}
636
637	DECLINLINE(int) get_pci_irq_level(PPCIGLOBALS pGlobals, int irq_num)
638	{
639	return (pGlobals->pci_irq_levels[irq_num] != 0);
640	}
641
642	/**
643	* Set the IRQ for a PCI device on the host bus - shared by host bus and bridge.
644	*
645	* @param pDevIns Device instance of the host PCI Bus.
646	* @param uDevFn The device number on the host bus which will raise the IRQ
647	* @param pPciDev The PCI device structure which raised the interrupt.
648	* @param iIrq IRQ number to set.
649	* @param iLevel IRQ level.
650	* @remark uDevFn and pPciDev->devfn are not the same if the device is behind a bridge.
651	* In that case uDevFn will be the slot of the bridge which is needed to calculate the
652	* PIRQ value.
653	*/
654	static void pciSetIrqInternal(PPCIGLOBALS pGlobals, uint8_t uDevFn, PPCIDEVICE pPciDev, int iIrq, int iLevel)
655	{
656	PPCIBUS pBus = &pGlobals->PciBus;
657	uint8_t *pbCfg = pGlobals->PIIX3State.dev.config;
658	const bool fIsAcpiDevice = pPciDev->config[2] == 0x13 && pPciDev->config[3] == 0x71;
659	/* If the two configuration space bytes at 0xde, 0xad are set to 0xbe, 0xef, a back door
660	* is opened to route PCI interrupts directly to the I/O APIC and bypass the PIC.
661	* See the \_SB_.PCI0._PRT method in vbox.dsl.
662	*/
663	const bool fIsApicEnabled = pGlobals->fUseIoApic && pbCfg[0xde] == 0xbe && pbCfg[0xad] == 0xef;
664	int pic_irq, pic_level;
665
666	/* Check if the state changed. */
667	if (pPciDev->Int.s.uIrqPinState != iLevel)
668	{
669	pPciDev->Int.s.uIrqPinState = (iLevel & PDM_IRQ_LEVEL_HIGH);
670
671	/* Send interrupt to I/O APIC only. */
672	if (fIsApicEnabled)
673	{
674	if (fIsAcpiDevice)
675	/*
676	* ACPI needs special treatment since SCI is hardwired and
677	* should not be affected by PCI IRQ routing tables at the
678	* same time SCI IRQ is shared in PCI sense hence this
679	* kludge (i.e. we fetch the hardwired value from ACPIs
680	* PCI device configuration space).
681	*/
682	apic_set_irq(pBus, uDevFn, pPciDev, -1, iLevel, pPciDev->config[PCI_INTERRUPT_LINE]);
683	else
684	apic_set_irq(pBus, uDevFn, pPciDev, iIrq, iLevel, -1);
685	return;
686	}
687
688	if (fIsAcpiDevice)
689	{
690	/* As per above treat ACPI in a special way */
691	pic_irq = pPciDev->config[PCI_INTERRUPT_LINE];
692	pGlobals->acpi_irq = pic_irq;
693	pGlobals->acpi_irq_level = iLevel & PDM_IRQ_LEVEL_HIGH;
694	}
695	else
696	{
697	int irq_num;
698	irq_num = pci_slot_get_pirq(uDevFn, iIrq);
699
700	if (pPciDev->Int.s.uIrqPinState == PDM_IRQ_LEVEL_HIGH)
701	ASMAtomicIncU32(&pGlobals->pci_irq_levels[irq_num]);
702	else if (pPciDev->Int.s.uIrqPinState == PDM_IRQ_LEVEL_LOW)
703	ASMAtomicDecU32(&pGlobals->pci_irq_levels[irq_num]);
704
705	/* now we change the pic irq level according to the piix irq mappings */
706	pic_irq = pbCfg[0x60 + irq_num];
707	if (pic_irq >= 16)
708	{
709	if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP)
710	{
711	ASMAtomicDecU32(&pGlobals->pci_irq_levels[irq_num]);
712	pPciDev->Int.s.uIrqPinState = PDM_IRQ_LEVEL_LOW;
713	}
714
715	return;
716	}
717	}
718
719	/* the pic level is the logical OR of all the PCI irqs mapped to it */
720	pic_level = 0;
721	if (pic_irq == pbCfg[0x60])
722	pic_level \|= get_pci_irq_level(pGlobals, 0);
723	if (pic_irq == pbCfg[0x61])
724	pic_level \|= get_pci_irq_level(pGlobals, 1);
725	if (pic_irq == pbCfg[0x62])
726	pic_level \|= get_pci_irq_level(pGlobals, 2);
727	if (pic_irq == pbCfg[0x63])
728	pic_level \|= get_pci_irq_level(pGlobals, 3);
729	if (pic_irq == pGlobals->acpi_irq)
730	pic_level \|= pGlobals->acpi_irq_level;
731
732	Log3(("pciSetIrq: %s: iLevel=%d iIrq=%d pic_irq=%d pic_level=%d\n",
733	R3STRING(pPciDev->name), iLevel, iIrq, pic_irq, pic_level));
734	pBus->CTX_SUFF(pPciHlp)->pfnIsaSetIrq(pBus->CTX_SUFF(pDevIns), pic_irq, pic_level);
735
736	/** @todo optimize pci irq flip-flop some rainy day. */
737	if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP)
738	pciSetIrqInternal(pGlobals, uDevFn, pPciDev, iIrq, PDM_IRQ_LEVEL_LOW);
739	}
740	}
741
742	/**
743	* Set the IRQ for a PCI device on the host bus.
744	*
745	* @param pDevIns Device instance of the PCI Bus.
746	* @param pPciDev The PCI device structure.
747	* @param iIrq IRQ number to set.
748	* @param iLevel IRQ level.
749	*/
750	PDMBOTHCBDECL(void) pciSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel)
751	{
752	pciSetIrqInternal(PDMINS_2_DATA(pDevIns, PPCIGLOBALS), pPciDev->devfn, pPciDev, iIrq, iLevel);
753	}
754
755	#ifdef IN_RING3
756
757	/**
758	* Finds a bridge on the bus which contains the destination bus.
759	*
760	* @return Pointer to the device instance data of the bus or
761	* NULL if no bridge was found.
762	* @param pBus Pointer to the bus to search on.
763	* @param iBus Destination bus number.
764	*/
765	DECLINLINE(PPCIDEVICE) pciFindBridge(PPCIBUS pBus, uint8_t iBus)
766	{
767	/* Search for a fitting bridge. */
768	for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
769	{
770	/*
771	* Examine secondary and subordinate bus number.
772	* If the target bus is in the range we pass the request on to the bridge.
773	*/
774	PPCIDEVICE pBridgeTemp = pBus->papBridgesR3[iBridge];
775	AssertMsg(pBridgeTemp && pciDevIsPci2PciBridge(pBridgeTemp),
776	("Device is not a PCI bridge but on the list of PCI bridges\n"));
777
778	if ( iBus >= pBridgeTemp->config[VBOX_PCI_SECONDARY_BUS]
779	&& iBus <= pBridgeTemp->config[VBOX_PCI_SUBORDINATE_BUS])
780	return pBridgeTemp;
781	}
782
783	/* Nothing found. */
784	return NULL;
785	}
786
787	static void piix3_reset(PIIX3State *d)
788	{
789	uint8_t *pci_conf = d->dev.config;
790
791	pci_conf[0x04] = 0x07; /* master, memory and I/O */
792	pci_conf[0x05] = 0x00;
793	pci_conf[0x06] = 0x00;
794	pci_conf[0x07] = 0x02; /* PCI_status_devsel_medium */
795	pci_conf[0x4c] = 0x4d;
796	pci_conf[0x4e] = 0x03;
797	pci_conf[0x4f] = 0x00;
798	pci_conf[0x60] = 0x80;
799	pci_conf[0x69] = 0x02;
800	pci_conf[0x70] = 0x80;
801	pci_conf[0x76] = 0x0c;
802	pci_conf[0x77] = 0x0c;
803	pci_conf[0x78] = 0x02;
804	pci_conf[0x79] = 0x00;
805	pci_conf[0x80] = 0x00;
806	pci_conf[0x82] = 0x02; /* Get rid of the Linux guest "Enabling Passive Release" PCI quirk warning. */
807	pci_conf[0xa0] = 0x08;
808	pci_conf[0xa0] = 0x08;
809	pci_conf[0xa2] = 0x00;
810	pci_conf[0xa3] = 0x00;
811	pci_conf[0xa4] = 0x00;
812	pci_conf[0xa5] = 0x00;
813	pci_conf[0xa6] = 0x00;
814	pci_conf[0xa7] = 0x00;
815	pci_conf[0xa8] = 0x0f;
816	pci_conf[0xaa] = 0x00;
817	pci_conf[0xab] = 0x00;
818	pci_conf[0xac] = 0x00;
819	pci_conf[0xae] = 0x00;
820	}
821
822	static void pci_config_writel(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t val)
823	{
824	pGlobals->uConfigReg = 0x80000000 \| (uBus << 16) \|
825	(uDevFn << 8) \| addr;
826	pci_data_write(pGlobals, 0, val, 4);
827	}
828
829	static void pci_config_writew(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t val)
830	{
831	pGlobals->uConfigReg = 0x80000000 \| (uBus << 16) \|
832	(uDevFn << 8) \| (addr & ~3);
833	pci_data_write(pGlobals, addr & 3, val, 2);
834	}
835
836	static void pci_config_writeb(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t val)
837	{
838	pGlobals->uConfigReg = 0x80000000 \| (uBus << 16) \|
839	(uDevFn << 8) \| (addr & ~3);
840	pci_data_write(pGlobals, addr & 3, val, 1);
841	}
842
843	static uint32_t pci_config_readl(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr)
844	{
845	pGlobals->uConfigReg = 0x80000000 \| (uBus << 16) \|
846	(uDevFn << 8) \| addr;
847	uint32_t u32Val;
848	int rc = pci_data_read(pGlobals, 0, 4, &u32Val);
849	AssertRC(rc);
850	return u32Val;
851	}
852
853	static uint32_t pci_config_readw(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr)
854	{
855	pGlobals->uConfigReg = 0x80000000 \| (uBus << 16) \|
856	(uDevFn << 8) \| (addr & ~3);
857	uint32_t u32Val;
858	int rc = pci_data_read(pGlobals, addr & 3, 2, &u32Val);
859	AssertRC(rc);
860	return u32Val;
861	}
862
863	static uint32_t pci_config_readb(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr)
864	{
865	pGlobals->uConfigReg = 0x80000000 \| (uBus << 16) \|
866	(uDevFn << 8) \| (addr & ~3);
867	uint32_t u32Val;
868	int rc = pci_data_read(pGlobals, addr & 3, 1, &u32Val);
869	AssertRC(rc);
870	return u32Val;
871	}
872
873	/* host irqs corresponding to PCI irqs A-D */
874	static const uint8_t pci_irqs[4] = { 11, 9, 11, 9 }; /* bird: added const */
875
876	static void pci_set_io_region_addr(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, int region_num, uint32_t addr)
877	{
878	uint16_t cmd;
879	uint32_t ofs;
880
881	if ( region_num == PCI_ROM_SLOT )
882	ofs = 0x30;
883	else
884	ofs = 0x10 + region_num * 4;
885
886	/* Read memory type first. */
887	uint8_t uRessourceType = pci_config_readb(pGlobals, uBus, uDevFn, ofs);
888
889	/* Read command register. */
890	cmd = pci_config_readw(pGlobals, uBus, uDevFn, PCI_COMMAND);
891	if ( region_num == PCI_ROM_SLOT )
892	cmd \|= 2;
893	else if ((uRessourceType & 0x01) == 1) /* Test if region is I/O space. */
894	cmd \|= 1; /* Enable I/O space access. */
895	else /* The region is MMIO. */
896	cmd \|= 2; /* Enable MMIO access. */
897
898	/* Write address of the device. */
899	pci_config_writel(pGlobals, uBus, uDevFn, ofs, addr);
900
901	/* enable memory mappings */
902	pci_config_writew(pGlobals, uBus, uDevFn, PCI_COMMAND, cmd);
903	}
904
905	static void pci_bios_init_device(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint8_t cBridgeDepth, uint8_t *paBridgePositions)
906	{
907	uint32_t *paddr;
908	int i, pin, pic_irq;
909	uint16_t devclass, vendor_id, device_id;
910
911	devclass = pci_config_readw(pGlobals, uBus, uDevFn, PCI_CLASS_DEVICE);
912	vendor_id = pci_config_readw(pGlobals, uBus, uDevFn, PCI_VENDOR_ID);
913	device_id = pci_config_readw(pGlobals, uBus, uDevFn, PCI_DEVICE_ID);
914
915	/* Check if device is present. */
916	if (vendor_id != 0xffff)
917	{
918	switch(devclass)
919	{
920	case 0x0101:
921	if ( (vendor_id == 0x8086)
922	&& (device_id == 0x7010 \|\| device_id == 0x7111 \|\| device_id == 0x269e))
923	{
924	/* PIIX3, PIIX4 or ICH6 IDE */
925	pci_config_writew(pGlobals, uBus, uDevFn, 0x40, 0x8000); /* enable IDE0 */
926	pci_config_writew(pGlobals, uBus, uDevFn, 0x42, 0x8000); /* enable IDE1 */
927	goto default_map;
928	}
929	else
930	{
931	/* IDE: we map it as in ISA mode */
932	pci_set_io_region_addr(pGlobals, uBus, uDevFn, 0, 0x1f0);
933	pci_set_io_region_addr(pGlobals, uBus, uDevFn, 1, 0x3f4);
934	pci_set_io_region_addr(pGlobals, uBus, uDevFn, 2, 0x170);
935	pci_set_io_region_addr(pGlobals, uBus, uDevFn, 3, 0x374);
936	}
937	break;
938	case 0x0300:
939	if (vendor_id != 0x80ee)
940	goto default_map;
941	/* VGA: map frame buffer to default Bochs VBE address */
942	pci_set_io_region_addr(pGlobals, uBus, uDevFn, 0, 0xE0000000);
943	/*
944	* Legacy VGA I/O ports are implicitly decoded by a VGA class device. But
945	* only the framebuffer (i.e., a memory region) is explicitly registered via
946	* pci_set_io_region_addr, so I/O decoding must be enabled manually.
947	*/
948	pci_config_writeb(pGlobals, uBus, uDevFn, PCI_COMMAND,
949	pci_config_readb(pGlobals, uBus, uDevFn, PCI_COMMAND)
950	\| 1 /* Enable I/O space access. */);
951	break;
952	case 0x0800:
953	/* PIC */
954	vendor_id = pci_config_readw(pGlobals, uBus, uDevFn, PCI_VENDOR_ID);
955	device_id = pci_config_readw(pGlobals, uBus, uDevFn, PCI_DEVICE_ID);
956	if (vendor_id == 0x1014)
957	{
958	/* IBM */
959	if (device_id == 0x0046 \|\| device_id == 0xFFFF)
960	{
961	/* MPIC & MPIC2 */
962	pci_set_io_region_addr(pGlobals, uBus, uDevFn, 0, 0x80800000 + 0x00040000);
963	}
964	}
965	break;
966	case 0xff00:
967	if ( (vendor_id == 0x0106b)
968	&& (device_id == 0x0017 \|\| device_id == 0x0022))
969	{
970	/* macio bridge */
971	pci_set_io_region_addr(pGlobals, uBus, uDevFn, 0, 0x80800000);
972	}
973	break;
974	case 0x0604:
975	{
976	/* Init PCI-to-PCI bridge. */
977	pci_config_writeb(pGlobals, uBus, uDevFn, VBOX_PCI_PRIMARY_BUS, uBus);
978
979	AssertMsg(pGlobals->uBus < 255, ("Too many bridges on the bus\n"));
980	pGlobals->uBus++;
981	pci_config_writeb(pGlobals, uBus, uDevFn, VBOX_PCI_SECONDARY_BUS, pGlobals->uBus);
982	pci_config_writeb(pGlobals, uBus, uDevFn, VBOX_PCI_SUBORDINATE_BUS, 0xff); /* Temporary until we know how many other bridges are behind this one. */
983
984	/* Add position of this bridge into the array. */
985	paBridgePositions[cBridgeDepth+1] = (uDevFn >> 3);
986
987	/*
988	* The I/O range for the bridge must be aligned to a 4KB boundary.
989	* This does not change anything really as the access to the device is not going
990	* through the bridge but we want to be compliant to the spec.
991	*/
992	if ((pGlobals->pci_bios_io_addr % 4096) != 0)
993	pGlobals->pci_bios_io_addr = RT_ALIGN_32(pGlobals->pci_bios_io_addr, 4*1024);
994	Log(("%s: Aligned I/O start address. New address %#x\n", __FUNCTION__, pGlobals->pci_bios_io_addr));
995	pci_config_writeb(pGlobals, uBus, uDevFn, VBOX_PCI_IO_BASE, (pGlobals->pci_bios_io_addr >> 8) & 0xf0);
996
997	/* The MMIO range for the bridge must be aligned to a 1MB boundary. */
998	if ((pGlobals->pci_bios_mem_addr % (1024 * 1024)) != 0)
999	pGlobals->pci_bios_mem_addr = RT_ALIGN_32(pGlobals->pci_bios_mem_addr, 1024*1024);
1000	Log(("%s: Aligned MMIO start address. New address %#x\n", __FUNCTION__, pGlobals->pci_bios_mem_addr));
1001	pci_config_writew(pGlobals, uBus, uDevFn, VBOX_PCI_MEMORY_BASE, (pGlobals->pci_bios_mem_addr >> 16) & UINT32_C(0xffff0));
1002
1003	/* Save values to compare later to. */
1004	uint32_t u32IoAddressBase = pGlobals->pci_bios_io_addr;
1005	uint32_t u32MMIOAddressBase = pGlobals->pci_bios_mem_addr;
1006
1007	/* Init devices behind the bridge and possibly other bridges as well. */
1008	for (int iDev = 0; iDev <= 255; iDev++)
1009	pci_bios_init_device(pGlobals, uBus + 1, iDev, cBridgeDepth + 1, paBridgePositions);
1010
1011	/* The number of bridges behind the this one is now available. */
1012	pci_config_writeb(pGlobals, uBus, uDevFn, VBOX_PCI_SUBORDINATE_BUS, pGlobals->uBus);
1013
1014	/*
1015	* Set I/O limit register. If there is no device with I/O space behind the bridge
1016	* we set a lower value than in the base register.
1017	* The result with a real bridge is that no I/O transactions are passed to the secondary
1018	* interface. Again this doesn't really matter here but we want to be compliant to the spec.
1019	*/
1020	if ((u32IoAddressBase != pGlobals->pci_bios_io_addr) && ((pGlobals->pci_bios_io_addr % 4096) != 0))
1021	{
1022	/* The upper boundary must be one byte less than a 4KB boundary. */
1023	pGlobals->pci_bios_io_addr = RT_ALIGN_32(pGlobals->pci_bios_io_addr, 4*1024);
1024	}
1025	pci_config_writeb(pGlobals, uBus, uDevFn, VBOX_PCI_IO_LIMIT, ((pGlobals->pci_bios_io_addr >> 8) & 0xf0) - 1);
1026
1027	/* Same with the MMIO limit register but with 1MB boundary here. */
1028	if ((u32MMIOAddressBase != pGlobals->pci_bios_mem_addr) && ((pGlobals->pci_bios_mem_addr % (1024 * 1024)) != 0))
1029	{
1030	/* The upper boundary must be one byte less than a 1MB boundary. */
1031	pGlobals->pci_bios_mem_addr = RT_ALIGN_32(pGlobals->pci_bios_mem_addr, 1024*1024);
1032	}
1033	pci_config_writew(pGlobals, uBus, uDevFn, VBOX_PCI_MEMORY_LIMIT, ((pGlobals->pci_bios_mem_addr >> 16) & UINT32_C(0xfff0)) - 1);
1034
1035	/*
1036	* Set the prefetch base and limit registers. We currently have no device with a prefetchable region
1037	* which may be behind a bridge. That's why it is unconditionally disabled here atm by writing a higher value into
1038	* the base register than in the limit register.
1039	*/
1040	pci_config_writew(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_MEMORY_BASE, 0xfff0);
1041	pci_config_writew(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_MEMORY_LIMIT, 0x0);
1042	pci_config_writel(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_BASE_UPPER32, 0x00);
1043	pci_config_writel(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_LIMIT_UPPER32, 0x00);
1044	break;
1045	}
1046	default:
1047	default_map:
1048	{
1049	/* default memory mappings */
1050	/*
1051	* PCI_NUM_REGIONS is 7 because of the rom region but there are only 6 base address register defined by the PCI spec.
1052	* Leaving only PCI_NUM_REGIONS would cause reading another and enabling a memory region which does not exist.
1053	*/
1054	for(i = 0; i < (PCI_NUM_REGIONS-1); i++)
1055	{
1056	uint32_t u32Size;
1057	uint8_t u8RessourceType;
1058	uint32_t u32Address = 0x10 + i * 4;
1059
1060	/* Calculate size. */
1061	u8RessourceType = pci_config_readb(pGlobals, uBus, uDevFn, u32Address);
1062	pci_config_writel(pGlobals, uBus, uDevFn, u32Address, UINT32_C(0xffffffff));
1063	u32Size = pci_config_readl(pGlobals, uBus, uDevFn, u32Address);
1064	/* Clear resource information depending on resource type. */
1065	if ((u8RessourceType & 0x01) == 1) /* I/O */
1066	u32Size &= ~(0x01);
1067	else /* MMIO */
1068	u32Size &= ~(0x0f);
1069
1070	/*
1071	* Invert all bits and add 1 to get size of the region.
1072	* (From PCI implementation note)
1073	*/
1074	if (((u8RessourceType & 0x01) == 1) && (u32Size & UINT32_C(0xffff0000)) == 0)
1075	u32Size = (~(u32Size \| UINT32_C(0xffff0000))) + 1;
1076	else
1077	u32Size = (~u32Size) + 1;
1078
1079	Log(("%s: Size of region %u for device %d on bus %d is %u\n", __FUNCTION__, i, uDevFn, uBus, u32Size));
1080
1081	if (u32Size)
1082	{
1083	if ((u8RessourceType & 0x01) == 1)
1084	paddr = &pGlobals->pci_bios_io_addr;
1085	else
1086	paddr = &pGlobals->pci_bios_mem_addr;
1087	paddr = (paddr + u32Size - 1) & ~(u32Size - 1);
1088	Log(("%s: Start address of %s region %u is %#x\n", __FUNCTION__, ((u8RessourceType & 0x01) == 1 ? "I/O" : "MMIO"), i, *paddr));
1089	pci_set_io_region_addr(pGlobals, uBus, uDevFn, i, *paddr);
1090	*paddr += u32Size;
1091	Log(("%s: New address is %#x\n", __FUNCTION__, *paddr));
1092	}
1093	}
1094	break;
1095	}
1096	}
1097
1098	/* map the interrupt */
1099	pin = pci_config_readb(pGlobals, uBus, uDevFn, PCI_INTERRUPT_PIN);
1100	if (pin != 0)
1101	{
1102	uint8_t uBridgeDevFn = uDevFn;
1103	pin--;
1104
1105	/* We need to go up to the host bus to see which irq this device will assert there. */
1106	while (cBridgeDepth != 0)
1107	{
1108	/* Get the pin the device would assert on the bridge. */
1109	pin = ((uBridgeDevFn >> 3) + pin) & 3;
1110	uBridgeDevFn = paBridgePositions[cBridgeDepth];
1111	cBridgeDepth--;
1112	}
1113
1114	pin = pci_slot_get_pirq(uDevFn, pin);
1115	pic_irq = pci_irqs[pin];
1116	pci_config_writeb(pGlobals, uBus, uDevFn, PCI_INTERRUPT_LINE, pic_irq);
1117	}
1118	}
1119	}
1120
1121	#endif /* IN_RING3 */
1122
1123	/* -=-=-=-=-=- wrappers -=-=-=-=-=- */
1124
1125	/**
1126	* Port I/O Handler for PCI address OUT operations.
1127	*
1128	* @returns VBox status code.
1129	*
1130	* @param pDevIns The device instance.
1131	* @param pvUser User argument - ignored.
1132	* @param uPort Port number used for the IN operation.
1133	* @param u32 The value to output.
1134	* @param cb The value size in bytes.
1135	*/
1136	PDMBOTHCBDECL(int) pciIOPortAddressWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1137	{
1138	Log(("pciIOPortAddressWrite: Port=%#x u32=%#x cb=%d\n", Port, u32, cb));
1139	NOREF(pvUser);
1140	if (cb == 4)
1141	{
1142	PPCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
1143	PCI_LOCK(pDevIns, VINF_IOM_HC_IOPORT_WRITE);
1144	pThis->uConfigReg = u32 & ~3; /* Bits 0-1 are reserved and we silently clear them */
1145	PCI_UNLOCK(pDevIns);
1146	}
1147	/* else: 440FX does "pass through to the bus" for other writes, what ever that means.
1148	* Linux probes for cmd640 using byte writes/reads during ide init. We'll just ignore it. */
1149	return VINF_SUCCESS;
1150	}
1151
1152
1153	/**
1154	* Port I/O Handler for PCI address IN operations.
1155	*
1156	* @returns VBox status code.
1157	*
1158	* @param pDevIns The device instance.
1159	* @param pvUser User argument - ignored.
1160	* @param uPort Port number used for the IN operation.
1161	* @param pu32 Where to store the result.
1162	* @param cb Number of bytes read.
1163	*/
1164	PDMBOTHCBDECL(int) pciIOPortAddressRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
1165	{
1166	NOREF(pvUser);
1167	if (cb == 4)
1168	{
1169	PPCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
1170	PCI_LOCK(pDevIns, VINF_IOM_HC_IOPORT_READ);
1171	*pu32 = pThis->uConfigReg;
1172	PCI_UNLOCK(pDevIns);
1173	Log(("pciIOPortAddressRead: Port=%#x cb=%d -> %#x\n", Port, cb, *pu32));
1174	return VINF_SUCCESS;
1175	}
1176	/* else: 440FX does "pass through to the bus" for other writes, what ever that means.
1177	* Linux probes for cmd640 using byte writes/reads during ide init. We'll just ignore it. */
1178	Log(("pciIOPortAddressRead: Port=%#x cb=%d VERR_IOM_IOPORT_UNUSED\n", Port, cb));
1179	return VERR_IOM_IOPORT_UNUSED;
1180	}
1181
1182
1183	/**
1184	* Port I/O Handler for PCI data OUT operations.
1185	*
1186	* @returns VBox status code.
1187	*
1188	* @param pDevIns The device instance.
1189	* @param pvUser User argument - ignored.
1190	* @param uPort Port number used for the IN operation.
1191	* @param u32 The value to output.
1192	* @param cb The value size in bytes.
1193	*/
1194	PDMBOTHCBDECL(int) pciIOPortDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1195	{
1196	Log(("pciIOPortDataWrite: Port=%#x u32=%#x cb=%d\n", Port, u32, cb));
1197	NOREF(pvUser);
1198	int rc = VINF_SUCCESS;
1199	if (!(Port % cb))
1200	{
1201	PCI_LOCK(pDevIns, VINF_IOM_HC_IOPORT_WRITE);
1202	rc = pci_data_write(PDMINS_2_DATA(pDevIns, PPCIGLOBALS), Port, u32, cb);
1203	PCI_UNLOCK(pDevIns);
1204	}
1205	else
1206	AssertMsgFailed(("Write to port %#x u32=%#x cb=%d\n", Port, u32, cb));
1207	return rc;
1208	}
1209
1210
1211	/**
1212	* Port I/O Handler for PCI data IN operations.
1213	*
1214	* @returns VBox status code.
1215	*
1216	* @param pDevIns The device instance.
1217	* @param pvUser User argument - ignored.
1218	* @param uPort Port number used for the IN operation.
1219	* @param pu32 Where to store the result.
1220	* @param cb Number of bytes read.
1221	*/
1222	PDMBOTHCBDECL(int) pciIOPortDataRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
1223	{
1224	NOREF(pvUser);
1225	if (!(Port % cb))
1226	{
1227	PCI_LOCK(pDevIns, VINF_IOM_HC_IOPORT_READ);
1228	int rc = pci_data_read(PDMINS_2_DATA(pDevIns, PPCIGLOBALS), Port, cb, pu32);
1229	PCI_UNLOCK(pDevIns);
1230	Log(("pciIOPortDataRead: Port=%#x cb=%#x -> %#x (%Rrc)\n", Port, cb, *pu32, rc));
1231	return rc;
1232	}
1233	AssertMsgFailed(("Read from port %#x cb=%d\n", Port, cb));
1234	return VERR_IOM_IOPORT_UNUSED;
1235	}
1236
1237	#ifdef IN_RING3
1238
1239	/**
1240	* Saves a state of the PCI device.
1241	*
1242	* @returns VBox status code.
1243	* @param pDevIns Device instance of the PCI Bus.
1244	* @param pPciDev Pointer to PCI device.
1245	* @param pSSM The handle to save the state to.
1246	*/
1247	static DECLCALLBACK(int) pciGenericSaveExec(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PSSMHANDLE pSSM)
1248	{
1249	return SSMR3PutMem(pSSM, &pPciDev->config[0], sizeof(pPciDev->config));
1250	}
1251
1252
1253	/**
1254	* Loads a saved PCI device state.
1255	*
1256	* @returns VBox status code.
1257	* @param pDevIns Device instance of the PCI Bus.
1258	* @param pPciDev Pointer to PCI device.
1259	* @param pSSM The handle to the saved state.
1260	*/
1261	static DECLCALLBACK(int) pciGenericLoadExec(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PSSMHANDLE pSSM)
1262	{
1263	return SSMR3GetMem(pSSM, &pPciDev->config[0], sizeof(pPciDev->config));
1264	}
1265
1266
1267	/**
1268	* Common worker for pciR3SaveExec and pcibridgeR3SaveExec.
1269	*
1270	* @returns VBox status code.
1271	* @param pBus The bus to save.
1272	* @param pSSM The saved state handle.
1273	*/
1274	static int pciR3CommonSaveExec(PPCIBUS pBus, PSSMHANDLE pSSM)
1275	{
1276	/*
1277	* Iterate thru all the devices.
1278	*/
1279	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->devices); i++)
1280	{
1281	PPCIDEVICE pDev = pBus->devices[i];
1282	if (pDev)
1283	{
1284	SSMR3PutU32(pSSM, i);
1285	SSMR3PutMem(pSSM, pDev->config, sizeof(pDev->config));
1286
1287	int rc = SSMR3PutS32(pSSM, pDev->Int.s.uIrqPinState);
1288	if (RT_FAILURE(rc))
1289	return rc;
1290	}
1291	}
1292	return SSMR3PutU32(pSSM, UINT32_MAX); /* terminator */
1293	}
1294
1295
1296	/**
1297	* Saves a state of the PCI device.
1298	*
1299	* @returns VBox status code.
1300	* @param pDevIns The device instance.
1301	* @param pPciDev Pointer to PCI device.
1302	* @param pSSM The handle to save the state to.
1303	*/
1304	static DECLCALLBACK(int) pciR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
1305	{
1306	uint32_t i;
1307	PPCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
1308
1309	/*
1310	* Bus state data.
1311	*/
1312	SSMR3PutU32(pSSM, pThis->uConfigReg);
1313	SSMR3PutBool(pSSM, pThis->fUseIoApic);
1314
1315	/*
1316	* Save IRQ states.
1317	*/
1318	for (i = 0; i < PCI_IRQ_PINS; i++)
1319	SSMR3PutU32(pSSM, pThis->pci_irq_levels[i]);
1320	for (i = 0; i < PCI_APIC_IRQ_PINS; i++)
1321	SSMR3PutU32(pSSM, pThis->pci_apic_irq_levels[i]);
1322
1323	SSMR3PutU32(pSSM, pThis->acpi_irq_level);
1324	SSMR3PutS32(pSSM, pThis->acpi_irq);
1325
1326	SSMR3PutU32(pSSM, ~0); /* separator */
1327
1328	/*
1329	* Join paths with pcibridgeR3SaveExec.
1330	*/
1331	return pciR3CommonSaveExec(&pThis->PciBus, pSSM);
1332	}
1333
1334
1335	/**
1336	* Common routine for restoring the config registers of a PCI device.
1337	*
1338	* @param pDev The PCI device.
1339	* @param pbSrcConfig The configuration register values to be loaded.
1340	* @param fIsBridge Whether this is a bridge device or not.
1341	*/
1342	static void pciR3CommonRestoreConfig(PPCIDEVICE pDev, uint8_t const *pbSrcConfig, bool fIsBridge)
1343	{
1344	/*
1345	* This table defines the fields for normal devices and bridge devices, and
1346	* the order in which they need to be restored.
1347	*/
1348	static const struct PciField
1349	{
1350	uint8_t off;
1351	uint8_t cb;
1352	uint8_t fWritable;
1353	uint8_t fBridge;
1354	const char *pszName;
1355	} s_aFields[] =
1356	{
1357	/* off,cb,fW,fB, pszName */
1358	{ 0x00, 2, 0, 3, "VENDOR_ID" },
1359	{ 0x02, 2, 0, 3, "DEVICE_ID" },
1360	{ 0x06, 2, 1, 3, "STATUS" },
1361	{ 0x08, 1, 0, 3, "REVISION_ID" },
1362	{ 0x09, 1, 0, 3, "CLASS_PROG" },
1363	{ 0x0a, 1, 0, 3, "CLASS_SUB" },
1364	{ 0x0b, 1, 0, 3, "CLASS_BASE" },
1365	{ 0x0c, 1, 0, 3, "CACHE_LINE_SIZE" }, // fWritable = ??
1366	{ 0x0d, 1, 0, 3, "LATENCY_TIMER" }, // fWritable = ??
1367	{ 0x0e, 1, 0, 3, "HEADER_TYPE" }, // fWritable = ??
1368	{ 0x0f, 1, 0, 3, "BIST" }, // fWritable = ??
1369	{ 0x10, 4, 1, 3, "BASE_ADDRESS_0" },
1370	{ 0x14, 4, 1, 3, "BASE_ADDRESS_1" },
1371	{ 0x18, 4, 1, 1, "BASE_ADDRESS_2" },
1372	{ 0x18, 1, 1, 2, "PRIMARY_BUS" }, // fWritable = ??
1373	{ 0x19, 1, 1, 2, "SECONDARY_BUS" }, // fWritable = ??
1374	{ 0x1a, 1, 1, 2, "SUBORDINATE_BUS" }, // fWritable = ??
1375	{ 0x1b, 1, 1, 2, "SEC_LATENCY_TIMER" }, // fWritable = ??
1376	{ 0x1c, 4, 1, 1, "BASE_ADDRESS_3" },
1377	{ 0x1c, 1, 1, 2, "IO_BASE" }, // fWritable = ??
1378	{ 0x1d, 1, 1, 2, "IO_LIMIT" }, // fWritable = ??
1379	{ 0x1e, 2, 1, 2, "SEC_STATUS" }, // fWritable = ??
1380	{ 0x20, 4, 1, 1, "BASE_ADDRESS_4" },
1381	{ 0x20, 2, 1, 2, "MEMORY_BASE" }, // fWritable = ??
1382	{ 0x22, 2, 1, 2, "MEMORY_LIMIT" }, // fWritable = ??
1383	{ 0x24, 4, 1, 1, "BASE_ADDRESS_5" },
1384	{ 0x24, 2, 1, 2, "PREF_MEMORY_BASE" }, // fWritable = ??
1385	{ 0x26, 2, 1, 2, "PREF_MEMORY_LIMIT" }, // fWritable = ??
1386	{ 0x28, 4, 1, 1, "CARDBUS_CIS" }, // fWritable = ??
1387	{ 0x28, 4, 1, 2, "PREF_BASE_UPPER32" }, // fWritable = ??
1388	{ 0x2c, 2, 0, 1, "SUBSYSTEM_VENDOR_ID" },// fWritable = !?
1389	{ 0x2c, 4, 1, 2, "PREF_LIMIT_UPPER32" },// fWritable = ??
1390	{ 0x2e, 2, 0, 1, "SUBSYSTEM_ID" }, // fWritable = !?
1391	{ 0x30, 4, 1, 1, "ROM_ADDRESS" }, // fWritable = ?!
1392	{ 0x30, 2, 1, 2, "IO_BASE_UPPER16" }, // fWritable = ?!
1393	{ 0x32, 2, 1, 2, "IO_LIMIT_UPPER16" }, // fWritable = ?!
1394	{ 0x34, 4, 0, 3, "CAPABILITY_LIST" }, // fWritable = !? cb=!?
1395	{ 0x38, 4, 1, 1, "???" }, // ???
1396	{ 0x38, 4, 1, 2, "ROM_ADDRESS_BR" }, // fWritable = !? cb=!? fBridge=!?
1397	{ 0x3c, 1, 1, 3, "INTERRUPT_LINE" }, // fBridge=??
1398	{ 0x3d, 1, 0, 3, "INTERRUPT_PIN" }, // fBridge=??
1399	{ 0x3e, 1, 0, 1, "MIN_GNT" }, // fWritable = !?
1400	{ 0x3e, 1, 1, 2, "BRIDGE_CONTROL" }, // fWritable = !? cb=!?
1401	{ 0x3f, 1, 1, 3, "MAX_LAT" }, // fWritable = !? fBridge=!?
1402	/* The COMMAND register must come last as it requires the ADDRESS
1403	registers to be restored before we pretent to change it from 0 to
1404	whatever value the guest assigned it. */
1405	{ 0x04, 2, 1, 3, "COMMAND" },
1406	};
1407
1408	#ifdef RT_STRICT
1409	/* Check that we've got full register coverage. */
1410	uint32_t bmDevice[0x40 / 32];
1411	uint32_t bmBridge[0x40 / 32];
1412	RT_ZERO(bmDevice);
1413	RT_ZERO(bmBridge);
1414	for (uint32_t i = 0; i < RT_ELEMENTS(s_aFields); i++)
1415	{
1416	uint8_t off = s_aFields[i].off;
1417	uint8_t cb = s_aFields[i].cb;
1418	uint8_t f = s_aFields[i].fBridge;
1419	while (cb-- > 0)
1420	{
1421	if (f & 1) AssertMsg(!ASMBitTest(bmDevice, off), ("%#x\n", off));
1422	if (f & 2) AssertMsg(!ASMBitTest(bmBridge, off), ("%#x\n", off));
1423	if (f & 1) ASMBitSet(bmDevice, off);
1424	if (f & 2) ASMBitSet(bmBridge, off);
1425	off++;
1426	}
1427	}
1428	for (uint32_t off = 0; off < 0x40; off++)
1429	{
1430	AssertMsg(ASMBitTest(bmDevice, off), ("%#x\n", off));
1431	AssertMsg(ASMBitTest(bmBridge, off), ("%#x\n", off));
1432	}
1433	#endif
1434
1435	/*
1436	* Loop thru the fields covering the 64 bytes of standard registers.
1437	*/
1438	uint8_t const fBridge = fIsBridge ? 2 : 1;
1439	uint8_t *pbDstConfig = &pDev->config[0];
1440	for (uint32_t i = 0; i < RT_ELEMENTS(s_aFields); i++)
1441	if (s_aFields[i].fBridge & fBridge)
1442	{
1443	uint8_t const off = s_aFields[i].off;
1444	uint8_t const cb = s_aFields[i].cb;
1445	uint32_t u32Src;
1446	uint32_t u32Dst;
1447	switch (cb)
1448	{
1449	case 1:
1450	u32Src = pbSrcConfig[off];
1451	u32Dst = pbDstConfig[off];
1452	break;
1453	case 2:
1454	u32Src = (uint16_t const )&pbSrcConfig[off];
1455	u32Dst = (uint16_t const )&pbDstConfig[off];
1456	break;
1457	case 4:
1458	u32Src = (uint32_t const )&pbSrcConfig[off];
1459	u32Dst = (uint32_t const )&pbDstConfig[off];
1460	break;
1461	default:
1462	AssertFailed();
1463	continue;
1464	}
1465
1466	if ( u32Src != u32Dst
1467	\|\| off == VBOX_PCI_COMMAND)
1468	{
1469	if (u32Src != u32Dst)
1470	{
1471	if (!s_aFields[i].fWritable)
1472	LogRel(("PCI: %8s/%u: %2u-bit field %s: %x -> %x - !READ ONLY!\n",
1473	pDev->name, pDev->pDevIns->iInstance, cb*8, s_aFields[i].pszName, u32Dst, u32Src));
1474	else
1475	LogRel(("PCI: %8s/%u: %2u-bit field %s: %x -> %x\n",
1476	pDev->name, pDev->pDevIns->iInstance, cb*8, s_aFields[i].pszName, u32Dst, u32Src));
1477	}
1478	if (off == VBOX_PCI_COMMAND)
1479	PCIDevSetCommand(pDev, 0); /* For remapping, see pciR3CommonLoadExec. */
1480	pDev->Int.s.pfnConfigWrite(pDev, off, u32Src, cb);
1481	}
1482	}
1483
1484	/*
1485	* The device dependent registers.
1486	*
1487	* We will not use ConfigWrite here as we have no clue about the size
1488	* of the registers, so the device is responsible for correctly
1489	* restoring functionality governed by these registers.
1490	*/
1491	for (uint32_t off = 0x40; off < sizeof(pDev->config); off++)
1492	if (pbDstConfig[off] != pbSrcConfig[off])
1493	{
1494	LogRel(("PCI: %8s/%u: register %02x: %02x -> %02x\n",
1495	pDev->name, pDev->pDevIns->iInstance, off, pbDstConfig[off], pbSrcConfig[off])); /** @todo make this Log() later. */
1496	pbDstConfig[off] = pbSrcConfig[off];
1497	}
1498	}
1499
1500
1501	/**
1502	* Common worker for pciR3LoadExec and pcibridgeR3LoadExec.
1503	*
1504	* @returns VBox status code.
1505	* @param pBus The bus which data is being loaded.
1506	* @param pSSM The saved state handle.
1507	* @param uVersion The data version.
1508	* @param uPass The pass.
1509	*/
1510	static DECLCALLBACK(int) pciR3CommonLoadExec(PPCIBUS pBus, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1511	{
1512	uint32_t u32;
1513	uint32_t i;
1514	int rc;
1515
1516	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
1517
1518	/*
1519	* Iterate thru all the devices and write 0 to the COMMAND register so
1520	* that all the memory is unmapped before we start restoring the saved
1521	* mapping locations.
1522	*
1523	* The register value is restored afterwards so we can do proper
1524	* LogRels in pciR3CommonRestoreConfig.
1525	*/
1526	for (i = 0; i < RT_ELEMENTS(pBus->devices); i++)
1527	{
1528	PPCIDEVICE pDev = pBus->devices[i];
1529	if (pDev)
1530	{
1531	uint16_t u16 = PCIDevGetCommand(pDev);
1532	pDev->Int.s.pfnConfigWrite(pDev, VBOX_PCI_COMMAND, 0, 2);
1533	PCIDevSetCommand(pDev, u16);
1534	Assert(PCIDevGetCommand(pDev) == u16);
1535	}
1536	}
1537
1538	/*
1539	* Iterate all the devices.
1540	*/
1541	for (i = 0;; i++)
1542	{
1543	PCIDEVICE DevTmp;
1544	PPCIDEVICE pDev;
1545
1546	/* index / terminator */
1547	rc = SSMR3GetU32(pSSM, &u32);
1548	if (RT_FAILURE(rc))
1549	return rc;
1550	if (u32 == (uint32_t)~0)
1551	break;
1552	if ( u32 >= RT_ELEMENTS(pBus->devices)
1553	\|\| u32 < i)
1554	{
1555	AssertMsgFailed(("u32=%#x i=%#x\n", u32, i));
1556	return rc;
1557	}
1558
1559	/* skip forward to the device checking that no new devices are present. */
1560	for (; i < u32; i++)
1561	{
1562	if (pBus->devices[i])
1563	{
1564	LogRel(("New device in slot %#x, %s (vendor=%#06x device=%#06x)\n", i, pBus->devices[i]->name,
1565	PCIDevGetVendorId(pBus->devices[i]), PCIDevGetDeviceId(pBus->devices[i])));
1566	if (SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT)
1567	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("New device in slot %#x, %s (vendor=%#06x device=%#06x)"),
1568	i, pBus->devices[i]->name, PCIDevGetVendorId(pBus->devices[i]), PCIDevGetDeviceId(pBus->devices[i]));
1569	}
1570	}
1571
1572	/* get the data */
1573	DevTmp.Int.s.uIrqPinState = ~0; /* Invalid value in case we have an older saved state to force a state change in pciSetIrq. */
1574	SSMR3GetMem(pSSM, DevTmp.config, sizeof(DevTmp.config));
1575	if (uVersion < 3)
1576	{
1577	int32_t i32Temp;
1578	/* Irq value not needed anymore. */
1579	rc = SSMR3GetS32(pSSM, &i32Temp);
1580	if (RT_FAILURE(rc))
1581	return rc;
1582	}
1583	else
1584	{
1585	rc = SSMR3GetS32(pSSM, &DevTmp.Int.s.uIrqPinState);
1586	if (RT_FAILURE(rc))
1587	return rc;
1588	}
1589
1590	/* check that it's still around. */
1591	pDev = pBus->devices[i];
1592	if (!pDev)
1593	{
1594	LogRel(("Device in slot %#x has been removed! vendor=%#06x device=%#06x\n", i,
1595	PCIDevGetVendorId(&DevTmp), PCIDevGetDeviceId(&DevTmp)));
1596	if (SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT)
1597	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Device in slot %#x has been removed! vendor=%#06x device=%#06x"),
1598	i, PCIDevGetVendorId(&DevTmp), PCIDevGetDeviceId(&DevTmp));
1599	continue;
1600	}
1601
1602	/* match the vendor id assuming that this will never be changed. */
1603	if ( DevTmp.config[0] != pDev->config[0]
1604	\|\| DevTmp.config[1] != pDev->config[1])
1605	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Device in slot %#x (%s) vendor id mismatch! saved=%.4Rhxs current=%.4Rhxs"),
1606	i, pDev->name, DevTmp.config, pDev->config);
1607
1608	/* commit the loaded device config. */
1609	pciR3CommonRestoreConfig(pDev, &DevTmp.config[0], false ); /** @todo fix bridge fun! */
1610
1611	pDev->Int.s.uIrqPinState = DevTmp.Int.s.uIrqPinState;
1612	}
1613
1614	return VINF_SUCCESS;
1615	}
1616
1617
1618	/**
1619	* Loads a saved PCI device state.
1620	*
1621	* @returns VBox status code.
1622	* @param pDevIns The device instance.
1623	* @param pSSM The handle to the saved state.
1624	* @param uVersion The data unit version number.
1625	* @param uPass The data pass.
1626	*/
1627	static DECLCALLBACK(int) pciR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1628	{
1629	PPCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
1630	PPCIBUS pBus = &pThis->PciBus;
1631	uint32_t u32;
1632	int rc;
1633
1634	/*
1635	* Check the version.
1636	*/
1637	if (uVersion > VBOX_PCI_SAVED_STATE_VERSION)
1638	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1639	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
1640
1641	/*
1642	* Bus state data.
1643	*/
1644	SSMR3GetU32(pSSM, &pThis->uConfigReg);
1645	if (uVersion > 1)
1646	SSMR3GetBool(pSSM, &pThis->fUseIoApic);
1647
1648	/* Load IRQ states. */
1649	if (uVersion > 2)
1650	{
1651	for (uint8_t i = 0; i < PCI_IRQ_PINS; i++)
1652	SSMR3GetU32(pSSM, (uint32_t *)&pThis->pci_irq_levels[i]);
1653	for (uint8_t i = 0; i < PCI_APIC_IRQ_PINS; i++)
1654	SSMR3GetU32(pSSM, (uint32_t *)&pThis->pci_apic_irq_levels[i]);
1655
1656	SSMR3GetU32(pSSM, &pThis->acpi_irq_level);
1657	SSMR3GetS32(pSSM, &pThis->acpi_irq);
1658	}
1659
1660	/* separator */
1661	rc = SSMR3GetU32(pSSM, &u32);
1662	if (RT_FAILURE(rc))
1663	return rc;
1664	if (u32 != (uint32_t)~0)
1665	AssertMsgFailedReturn(("u32=%#x\n", u32), rc);
1666
1667	/*
1668	* The devices.
1669	*/
1670	return pciR3CommonLoadExec(pBus, pSSM, uVersion, uPass);
1671	}
1672
1673
1674	/* -=-=-=-=-=- real code -=-=-=-=-=- */
1675
1676	/**
1677	* Registers the device with the specified PCI bus.
1678	*
1679	* @returns VBox status code.
1680	* @param pBus The bus to register with.
1681	* @param iDev The PCI device ordinal.
1682	* @param pPciDev The PCI device structure.
1683	* @param pszName Pointer to device name (permanent, readonly). For debugging, not unique.
1684	*/
1685	static int pciRegisterInternal(PPCIBUS pBus, int iDev, PPCIDEVICE pPciDev, const char *pszName)
1686	{
1687	/*
1688	* Find device slot.
1689	*/
1690	if (iDev < 0)
1691	{
1692	/*
1693	* Special check for the IDE controller which is our function 1 device
1694	* before searching.
1695	*/
1696	if ( !strcmp(pszName, "piix3ide")
1697	&& !pBus->devices[9])
1698	iDev = 9;
1699	/* LPC bus expected to be there by some guests, better make an additional argument to PDM
1700	device helpers, but requires significant rewrite */
1701	else if (!strcmp(pszName, "lpc")
1702	&& !pBus->devices[0xf8])
1703	iDev = 0xf8;
1704	else
1705	{
1706	Assert(!(pBus->iDevSearch % 8));
1707	for (iDev = pBus->iDevSearch; iDev < (int)RT_ELEMENTS(pBus->devices); iDev += 8)
1708	if ( !pBus->devices[iDev]
1709	&& !pBus->devices[iDev + 1]
1710	&& !pBus->devices[iDev + 2]
1711	&& !pBus->devices[iDev + 3]
1712	&& !pBus->devices[iDev + 4]
1713	&& !pBus->devices[iDev + 5]
1714	&& !pBus->devices[iDev + 6]
1715	&& !pBus->devices[iDev + 7])
1716	break;
1717	if (iDev >= (int)RT_ELEMENTS(pBus->devices))
1718	{
1719	AssertMsgFailed(("Couldn't find free spot!\n"));
1720	return VERR_PDM_TOO_PCI_MANY_DEVICES;
1721	}
1722	}
1723	pciDevClearRequestedDevfunc(pPciDev);
1724	}
1725	else
1726	{
1727	/*
1728	* An explicit request.
1729	*
1730	* If the slot is occupied we'll have to relocate the device
1731	* currently occupying it first. This can only be done if the
1732	* existing device wasn't explicitly assigned. Also we limit
1733	* ourselves to function 0 devices.
1734	*
1735	* If you start setting devices + function in the
1736	* config, do it for all pci devices!
1737	*/
1738	//AssertReleaseMsg(iDev > 8 \|\| pBus->iBus != 0, ("iDev=%d pszName=%s\n", iDev, pszName));
1739	if (pBus->devices[iDev])
1740	{
1741	int iDevRel;
1742	AssertReleaseMsg(!(iDev % 8), ("PCI Configuration Conflict! iDev=%d pszName=%s clashes with %s\n",
1743	iDev, pszName, pBus->devices[iDev]->name));
1744	if ( pciDevIsRequestedDevfunc(pBus->devices[iDev])
1745	\|\| (pBus->devices[iDev + 1] && pciDevIsRequestedDevfunc(pBus->devices[iDev + 1]))
1746	\|\| (pBus->devices[iDev + 2] && pciDevIsRequestedDevfunc(pBus->devices[iDev + 2]))
1747	\|\| (pBus->devices[iDev + 3] && pciDevIsRequestedDevfunc(pBus->devices[iDev + 3]))
1748	\|\| (pBus->devices[iDev + 4] && pciDevIsRequestedDevfunc(pBus->devices[iDev + 4]))
1749	\|\| (pBus->devices[iDev + 5] && pciDevIsRequestedDevfunc(pBus->devices[iDev + 5]))
1750	\|\| (pBus->devices[iDev + 6] && pciDevIsRequestedDevfunc(pBus->devices[iDev + 6]))
1751	\|\| (pBus->devices[iDev + 7] && pciDevIsRequestedDevfunc(pBus->devices[iDev + 7])))
1752	{
1753	AssertReleaseMsgFailed(("Configuration error:'%s' and '%s' are both configured as device %d\n",
1754	pszName, pBus->devices[iDev]->name, iDev));
1755	return VERR_INTERNAL_ERROR;
1756	}
1757
1758	/* Find free slot for the device(s) we're moving and move them. */
1759	for (iDevRel = pBus->iDevSearch; iDevRel < (int)RT_ELEMENTS(pBus->devices); iDevRel += 8)
1760	{
1761	if ( !pBus->devices[iDevRel]
1762	&& !pBus->devices[iDevRel + 1]
1763	&& !pBus->devices[iDevRel + 2]
1764	&& !pBus->devices[iDevRel + 3]
1765	&& !pBus->devices[iDevRel + 4]
1766	&& !pBus->devices[iDevRel + 5]
1767	&& !pBus->devices[iDevRel + 6]
1768	&& !pBus->devices[iDevRel + 7])
1769	{
1770	int i = 0;
1771	for (i = 0; i < 8; i++)
1772	{
1773	if (!pBus->devices[iDev + i])
1774	continue;
1775	Log(("PCI: relocating '%s' from slot %#x to %#x\n", pBus->devices[iDev + i]->name, iDev + i, iDevRel + i));
1776	pBus->devices[iDevRel + i] = pBus->devices[iDev + i];
1777	pBus->devices[iDevRel + i]->devfn = iDevRel + i;
1778	pBus->devices[iDev + i] = NULL;
1779	}
1780	}
1781	}
1782	if (pBus->devices[iDev])
1783	{
1784	AssertMsgFailed(("Couldn't find free spot!\n"));
1785	return VERR_PDM_TOO_PCI_MANY_DEVICES;
1786	}
1787	} /* if conflict */
1788	pciDevSetRequestedDevfunc(pPciDev);
1789	}
1790
1791	Assert(!pBus->devices[iDev]);
1792	pPciDev->devfn = iDev;
1793	pPciDev->name = pszName;
1794	pPciDev->Int.s.pBusR3 = pBus;
1795	pPciDev->Int.s.pBusR0 = MMHyperR3ToR0(PDMDevHlpGetVM(pBus->CTX_SUFF(pDevIns)), pBus);
1796	pPciDev->Int.s.pBusRC = MMHyperR3ToRC(PDMDevHlpGetVM(pBus->CTX_SUFF(pDevIns)), pBus);
1797	pPciDev->Int.s.pfnConfigRead = pci_default_read_config;
1798	pPciDev->Int.s.pfnConfigWrite = pci_default_write_config;
1799	pBus->devices[iDev] = pPciDev;
1800	if (pciDevIsPci2PciBridge(pPciDev))
1801	{
1802	AssertMsg(pBus->cBridges < RT_ELEMENTS(pBus->devices), ("Number of bridges exceeds the number of possible devices on the bus\n"));
1803	AssertMsg(pPciDev->Int.s.pfnBridgeConfigRead && pPciDev->Int.s.pfnBridgeConfigWrite,
1804	("device is a bridge but does not implement read/write functions\n"));
1805	pBus->papBridgesR3[pBus->cBridges] = pPciDev;
1806	pBus->cBridges++;
1807	}
1808
1809	Log(("PCI: Registered device %d function %d (%#x) '%s'.\n",
1810	iDev >> 3, iDev & 7, 0x80000000 \| (iDev << 8), pszName));
1811
1812	return VINF_SUCCESS;
1813	}
1814
1815
1816	/**
1817	* Registers the device with the default PCI bus.
1818	*
1819	* @returns VBox status code.
1820	* @param pDevIns Device instance of the PCI Bus.
1821	* @param pPciDev The PCI device structure.
1822	* Any PCI enabled device must keep this in it's instance data!
1823	* Fill in the PCI data config before registration, please.
1824	* @param pszName Pointer to device name (permanent, readonly). For debugging, not unique.
1825	* @param iDev The PCI device number. Use a negative value for auto assigning one.
1826	*/
1827	static DECLCALLBACK(int) pciRegister(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, const char *pszName, int iDev)
1828	{
1829	PPCIBUS pBus = DEVINS_2_PCIBUS(pDevIns);
1830
1831	/*
1832	* Check input.
1833	*/
1834	if ( !pszName
1835	\|\| !pPciDev
1836	\|\| iDev >= (int)RT_ELEMENTS(pBus->devices)
1837	\|\| (iDev >= 0 && iDev <= 8))
1838	{
1839	AssertMsgFailed(("Invalid argument! pszName=%s pPciDev=%p iDev=%d\n", pszName, pPciDev, iDev));
1840	return VERR_INVALID_PARAMETER;
1841	}
1842
1843	/*
1844	* Register the device.
1845	*/
1846	return pciRegisterInternal(pBus, iDev, pPciDev, pszName);
1847	}
1848
1849
1850	static DECLCALLBACK(int) pciIORegionRegister(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iRegion, uint32_t cbRegion, PCIADDRESSSPACE enmType, PFNPCIIOREGIONMAP pfnCallback)
1851	{
1852	/*
1853	* Validate.
1854	*/
1855	AssertMsgReturn( enmType == PCI_ADDRESS_SPACE_MEM
1856	\|\| enmType == PCI_ADDRESS_SPACE_IO
1857	\|\| enmType == PCI_ADDRESS_SPACE_MEM_PREFETCH,
1858	("Invalid enmType=%#x? Or was this a bitmask after all...\n", enmType),
1859	VERR_INVALID_PARAMETER);
1860	AssertMsgReturn((unsigned)iRegion < PCI_NUM_REGIONS,
1861	("Invalid iRegion=%d PCI_NUM_REGIONS=%d\n", iRegion, PCI_NUM_REGIONS),
1862	VERR_INVALID_PARAMETER);
1863	int iLastSet = ASMBitLastSetU32(cbRegion);
1864	AssertMsgReturn( iLastSet != 0
1865	&& RT_BIT_32(iLastSet - 1) == cbRegion,
1866	("Invalid cbRegion=%#x iLastSet=%#x (not a power of 2 or 0)\n", cbRegion, iLastSet),
1867	VERR_INVALID_PARAMETER);
1868
1869	/*
1870	* Register the I/O region.
1871	*/
1872	PPCIIOREGION pRegion = &pPciDev->Int.s.aIORegions[iRegion];
1873	pRegion->addr = ~0U;
1874	pRegion->size = cbRegion;
1875	pRegion->type = enmType;
1876	pRegion->map_func = pfnCallback;
1877
1878	/* Set type in the config space. */
1879	uint32_t u32Address = 0x10 + iRegion * 4;
1880	uint32_t u32Value = (enmType == PCI_ADDRESS_SPACE_MEM_PREFETCH ? (1 << 3) : 0)
1881	\| (enmType == PCI_ADDRESS_SPACE_IO ? 1 : 0);
1882	(uint32_t )(pPciDev->config + u32Address) = RT_H2LE_U32(u32Value);
1883
1884	return VINF_SUCCESS;
1885	}
1886
1887
1888	/**
1889	* @copydoc PDMPCIBUSREG::pfnSetConfigCallbacksR3
1890	*/
1891	static DECLCALLBACK(void) pciSetConfigCallbacks(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PFNPCICONFIGREAD pfnRead, PPFNPCICONFIGREAD ppfnReadOld,
1892	PFNPCICONFIGWRITE pfnWrite, PPFNPCICONFIGWRITE ppfnWriteOld)
1893	{
1894	if (ppfnReadOld)
1895	*ppfnReadOld = pPciDev->Int.s.pfnConfigRead;
1896	pPciDev->Int.s.pfnConfigRead = pfnRead;
1897
1898	if (ppfnWriteOld)
1899	*ppfnWriteOld = pPciDev->Int.s.pfnConfigWrite;
1900	pPciDev->Int.s.pfnConfigWrite = pfnWrite;
1901	}
1902
1903
1904	/**
1905	* Called to perform the job of the bios.
1906	*
1907	* @returns VBox status.
1908	* @param pDevIns Device instance of the first bus.
1909	*/
1910	static DECLCALLBACK(int) pciFakePCIBIOS(PPDMDEVINS pDevIns)
1911	{
1912	unsigned i;
1913	uint8_t elcr[2] = {0, 0};
1914	PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
1915	PVM pVM = PDMDevHlpGetVM(pDevIns);
1916	Assert(pVM);
1917
1918	/*
1919	* Set the start addresses.
1920	*/
1921	pGlobals->pci_bios_io_addr = 0xd000;
1922	pGlobals->pci_bios_mem_addr = UINT32_C(0xf0000000);
1923	pGlobals->uBus = 0;
1924
1925	/*
1926	* Activate IRQ mappings.
1927	*/
1928	for (i = 0; i < 4; i++)
1929	{
1930	uint8_t irq = pci_irqs[i];
1931	/* Set to trigger level. */
1932	elcr[irq >> 3] \|= (1 << (irq & 7));
1933	/* Activate irq remapping in PIIX3. */
1934	pci_config_writeb(pGlobals, 0, pGlobals->PIIX3State.dev.devfn, 0x60 + i, irq);
1935	}
1936
1937	/* Tell to the PIC. */
1938	VBOXSTRICTRC rcStrict = IOMIOPortWrite(pVM, 0x4d0, elcr[0], sizeof(uint8_t));
1939	if (rcStrict == VINF_SUCCESS)
1940	rcStrict = IOMIOPortWrite(pVM, 0x4d1, elcr[1], sizeof(uint8_t));
1941	if (rcStrict != VINF_SUCCESS)
1942	{
1943	AssertMsgFailed(("Writing to PIC failed! rcStrict=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
1944	return RT_SUCCESS(rcStrict) ? VERR_INTERNAL_ERROR : VBOXSTRICTRC_VAL(rcStrict);
1945	}
1946
1947	/*
1948	* Init the devices.
1949	*/
1950	for (i = 0; i < 256; i++)
1951	{
1952	uint8_t aBridgePositions[256];
1953
1954	memset(aBridgePositions, 0, sizeof(aBridgePositions));
1955	Log2(("PCI: Initializing device %d (%#x)\n",
1956	i, 0x80000000 \| (i << 8)));
1957	pci_bios_init_device(pGlobals, 0, i, 0, aBridgePositions);
1958	}
1959
1960	return VINF_SUCCESS;
1961	}
1962
1963	/**
1964	* Info handler, device version.
1965	*
1966	* @param pDevIns Device instance which registered the info.
1967	* @param pHlp Callback functions for doing output.
1968	* @param pszArgs Argument string. Optional and specific to the handler.
1969	*/
1970	static DECLCALLBACK(void) pciIrqInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
1971	{
1972	PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
1973	PPCIBUS pBus = DEVINS_2_PCIBUS(pDevIns);
1974	uint16_t router;
1975	uint8_t irq_map;
1976	int i;
1977
1978	router = pGlobals->PIIX3State.dev.devfn;
1979	pHlp->pfnPrintf(pHlp, "PCI interrupt router at: %02X:%02X:%X\n",
1980	router >> 8, (router >> 3) & 0x1f, router & 0x7);
1981
1982	for (i = 0; i < 4; ++i)
1983	{
1984	irq_map = pci_config_readb(pGlobals, 0, router, 0x60 + i);
1985	if (irq_map & 0x80)
1986	pHlp->pfnPrintf(pHlp, "PIRQ%c disabled\n", 'A' + i);
1987	else
1988	pHlp->pfnPrintf(pHlp, "PIRQ%c -> IRQ%d\n", 'A' + i, irq_map & 0xf);
1989	}
1990	}
1991
1992	/**
1993	* @copydoc FNPDMDEVRELOCATE
1994	*/
1995	static DECLCALLBACK(void) pciRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
1996	{
1997	PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
1998	PPCIBUS pBus = &pGlobals->PciBus;
1999	pGlobals->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2000
2001	pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
2002	pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2003
2004	/* Relocate RC pointers for the attached pci devices. */
2005	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->devices); i++)
2006	{
2007	if (pBus->devices[i])
2008	pBus->devices[i]->Int.s.pBusRC += offDelta;
2009	}
2010	}
2011
2012
2013	/**
2014	* @copydoc FNPDMDEVRESET
2015	*/
2016	static DECLCALLBACK(void) pciReset(PPDMDEVINS pDevIns)
2017	{
2018	pciFakePCIBIOS(pDevIns);
2019	}
2020
2021	/**
2022	* @interface_method_impl{PDMDEVREG,pfnConstruct}
2023	*/
2024	static DECLCALLBACK(int) pciConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
2025	{
2026	Assert(iInstance == 0);
2027	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
2028
2029	/*
2030	* Validate and read configuration.
2031	*/
2032	if (!CFGMR3AreValuesValid(pCfg, "IOAPIC\0" "GCEnabled\0" "R0Enabled\0"))
2033	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
2034
2035	/* query whether we got an IOAPIC */
2036	bool fUseIoApic;
2037	int rc = CFGMR3QueryBoolDef(pCfg, "IOAPIC", &fUseIoApic, false);
2038	if (RT_FAILURE(rc))
2039	return PDMDEV_SET_ERROR(pDevIns, rc,
2040	N_("Configuration error: Failed to query boolean value \"IOAPIC\""));
2041
2042	/* check if RC code is enabled. */
2043	bool fGCEnabled;
2044	rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
2045	if (RT_FAILURE(rc))
2046	return PDMDEV_SET_ERROR(pDevIns, rc,
2047	N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
2048
2049	/* check if R0 code is enabled. */
2050	bool fR0Enabled;
2051	rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
2052	if (RT_FAILURE(rc))
2053	return PDMDEV_SET_ERROR(pDevIns, rc,
2054	N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
2055	Log(("PCI: fUseIoApic=%RTbool fGCEnabled=%RTbool fR0Enabled=%RTbool\n", fUseIoApic, fGCEnabled, fR0Enabled));
2056
2057	/*
2058	* Init data and register the PCI bus.
2059	*/
2060	PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
2061	pGlobals->pci_bios_io_addr = 0xc000;
2062	pGlobals->pci_bios_mem_addr = 0xf0000000;
2063	memset((void *)&pGlobals->pci_irq_levels, 0, sizeof(pGlobals->pci_irq_levels));
2064	pGlobals->fUseIoApic = fUseIoApic;
2065	memset((void *)&pGlobals->pci_apic_irq_levels, 0, sizeof(pGlobals->pci_apic_irq_levels));
2066
2067	pGlobals->pDevInsR3 = pDevIns;
2068	pGlobals->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2069	pGlobals->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2070
2071	pGlobals->PciBus.pDevInsR3 = pDevIns;
2072	pGlobals->PciBus.pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2073	pGlobals->PciBus.pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2074	pGlobals->PciBus.papBridgesR3 = (PPCIDEVICE )PDMDevHlpMMHeapAllocZ(pDevIns, sizeof(PPCIDEVICE) RT_ELEMENTS(pGlobals->PciBus.devices));
2075
2076	PDMPCIBUSREG PciBusReg;
2077	PPCIBUS pBus = &pGlobals->PciBus;
2078	PciBusReg.u32Version = PDM_PCIBUSREG_VERSION;
2079	PciBusReg.pfnRegisterR3 = pciRegister;
2080	PciBusReg.pfnRegisterMsiR3 = NULL;
2081	PciBusReg.pfnIORegionRegisterR3 = pciIORegionRegister;
2082	PciBusReg.pfnSetConfigCallbacksR3 = pciSetConfigCallbacks;
2083	PciBusReg.pfnSetIrqR3 = pciSetIrq;
2084	PciBusReg.pfnSaveExecR3 = pciGenericSaveExec;
2085	PciBusReg.pfnLoadExecR3 = pciGenericLoadExec;
2086	PciBusReg.pfnFakePCIBIOSR3 = pciFakePCIBIOS;
2087	PciBusReg.pszSetIrqRC = fGCEnabled ? "pciSetIrq" : NULL;
2088	PciBusReg.pszSetIrqR0 = fR0Enabled ? "pciSetIrq" : NULL;
2089	rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBus->pPciHlpR3);
2090	if (RT_FAILURE(rc))
2091	return PDMDEV_SET_ERROR(pDevIns, rc,
2092	N_("Failed to register ourselves as a PCI Bus"));
2093	if (pBus->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
2094	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
2095	N_("PCI helper version mismatch; got %#x expected %#x"),
2096	pBus->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION);
2097
2098	pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
2099	pBus->pPciHlpR0 = pBus->pPciHlpR3->pfnGetR0Helpers(pDevIns);
2100
2101	/* Disable default device locking. */
2102	rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
2103	AssertRCReturn(rc, rc);
2104
2105	/*
2106	* Fill in PCI configs and add them to the bus.
2107	*/
2108	/* i440FX */
2109	PCIDevSetVendorId( &pBus->PciDev, 0x8086); /* Intel */
2110	PCIDevSetDeviceId( &pBus->PciDev, 0x1237);
2111	PCIDevSetRevisionId(&pBus->PciDev, 0x02);
2112	PCIDevSetClassSub( &pBus->PciDev, 0x00); /* host2pci */
2113	PCIDevSetClassBase( &pBus->PciDev, 0x06); /* PCI_bridge */
2114	PCIDevSetHeaderType(&pBus->PciDev, 0x00);
2115
2116	pBus->PciDev.pDevIns = pDevIns;
2117	pciDevSetRequestedDevfunc(&pBus->PciDev);
2118	pciRegisterInternal(pBus, 0, &pBus->PciDev, "i440FX");
2119
2120	/* PIIX3 */
2121	PCIDevSetVendorId( &pGlobals->PIIX3State.dev, 0x8086); /* Intel */
2122	PCIDevSetDeviceId( &pGlobals->PIIX3State.dev, 0x7000); /* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */
2123	PCIDevSetClassSub( &pGlobals->PIIX3State.dev, 0x01); /* PCI_ISA */
2124	PCIDevSetClassBase( &pGlobals->PIIX3State.dev, 0x06); /* PCI_bridge */
2125	PCIDevSetHeaderType(&pGlobals->PIIX3State.dev, 0x80); /* PCI_multifunction, generic */
2126
2127	pGlobals->PIIX3State.dev.pDevIns = pDevIns;
2128	pciDevSetRequestedDevfunc(&pGlobals->PIIX3State.dev);
2129	pciRegisterInternal(pBus, 8, &pGlobals->PIIX3State.dev, "PIIX3");
2130	piix3_reset(&pGlobals->PIIX3State);
2131
2132	pBus->iDevSearch = 16;
2133
2134	/*
2135	* Register I/O ports and save state.
2136	*/
2137	rc = PDMDevHlpIOPortRegister(pDevIns, 0x0cf8, 1, NULL, pciIOPortAddressWrite, pciIOPortAddressRead, NULL, NULL, "i440FX (PCI)");
2138	if (RT_FAILURE(rc))
2139	return rc;
2140	rc = PDMDevHlpIOPortRegister(pDevIns, 0x0cfc, 4, NULL, pciIOPortDataWrite, pciIOPortDataRead, NULL, NULL, "i440FX (PCI)");
2141	if (RT_FAILURE(rc))
2142	return rc;
2143	if (fGCEnabled)
2144	{
2145	rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x0cf8, 1, NIL_RTGCPTR, "pciIOPortAddressWrite", "pciIOPortAddressRead", NULL, NULL, "i440FX (PCI)");
2146	if (RT_FAILURE(rc))
2147	return rc;
2148	rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x0cfc, 4, NIL_RTGCPTR, "pciIOPortDataWrite", "pciIOPortDataRead", NULL, NULL, "i440FX (PCI)");
2149	if (RT_FAILURE(rc))
2150	return rc;
2151	}
2152	if (fR0Enabled)
2153	{
2154	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x0cf8, 1, NIL_RTR0PTR, "pciIOPortAddressWrite", "pciIOPortAddressRead", NULL, NULL, "i440FX (PCI)");
2155	if (RT_FAILURE(rc))
2156	return rc;
2157	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x0cfc, 4, NIL_RTR0PTR, "pciIOPortDataWrite", "pciIOPortDataRead", NULL, NULL, "i440FX (PCI)");
2158	if (RT_FAILURE(rc))
2159	return rc;
2160	}
2161
2162	rc = PDMDevHlpSSMRegisterEx(pDevIns, VBOX_PCI_SAVED_STATE_VERSION, sizeof(pBus) + 16128, "pgm",
2163	NULL, NULL, NULL,
2164	NULL, pciR3SaveExec, NULL,
2165	NULL, pciR3LoadExec, NULL);
2166	if (RT_FAILURE(rc))
2167	return rc;
2168
2169	PDMDevHlpDBGFInfoRegister(pDevIns, "pciirq", "Display PCI IRQ routing state. (no arguments)", pciIrqInfo);
2170
2171	return VINF_SUCCESS;
2172	}
2173
2174
2175	/**
2176	* The device registration structure.
2177	*/
2178	const PDMDEVREG g_DevicePCI =
2179	{
2180	/* u32Version */
2181	PDM_DEVREG_VERSION,
2182	/* szName */
2183	"pci",
2184	/* szRCMod */
2185	"VBoxDDGC.gc",
2186	/* szR0Mod */
2187	"VBoxDDR0.r0",
2188	/* pszDescription */
2189	"i440FX PCI bridge and PIIX3 ISA bridge.",
2190	/* fFlags */
2191	PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
2192	/* fClass */
2193	PDM_DEVREG_CLASS_BUS_PCI \| PDM_DEVREG_CLASS_BUS_ISA,
2194	/* cMaxInstances */
2195	1,
2196	/* cbInstance */
2197	sizeof(PCIGLOBALS),
2198	/* pfnConstruct */
2199	pciConstruct,
2200	/* pfnDestruct */
2201	NULL,
2202	/* pfnRelocate */
2203	pciRelocate,
2204	/* pfnIOCtl */
2205	NULL,
2206	/* pfnPowerOn */
2207	NULL,
2208	/* pfnReset */
2209	pciReset,
2210	/* pfnSuspend */
2211	NULL,
2212	/* pfnResume */
2213	NULL,
2214	/* pfnAttach */
2215	NULL,
2216	/* pfnDetach */
2217	NULL,
2218	/* pfnQueryInterface */
2219	NULL,
2220	/* pfnInitComplete */
2221	NULL,
2222	/* pfnPowerOff */
2223	NULL,
2224	/* pfnSoftReset */
2225	NULL,
2226	/* u32VersionEnd */
2227	PDM_DEVREG_VERSION
2228
2229	};
2230	#endif /* IN_RING3 */
2231
2232
2233	/**
2234	* Set the IRQ for a PCI device on a secondary bus.
2235	*
2236	* @param pDevIns Device instance of the PCI Bus.
2237	* @param pPciDev The PCI device structure.
2238	* @param iIrq IRQ number to set.
2239	* @param iLevel IRQ level.
2240	*/
2241	PDMBOTHCBDECL(void) pcibridgeSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel)
2242	{
2243	/*
2244	* The PCI-to-PCI bridge specification defines how the interrupt pins
2245	* are routed from the secondary to the primary bus (see chapter 9).
2246	* iIrq gives the interrupt pin the pci device asserted.
2247	* We change iIrq here according to the spec and call the SetIrq function
2248	* of our parent passing the device which asserted the interrupt instead of the device of the bridge.
2249	*/
2250	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
2251	PPCIDEVICE pPciDevBus = pPciDev;
2252	int iIrqPinBridge = iIrq;
2253	uint8_t uDevFnBridge = 0;
2254
2255	/* Walk the chain until we reach the host bus. */
2256	do
2257	{
2258	uDevFnBridge = pBus->PciDev.devfn;
2259	iIrqPinBridge = ((pPciDevBus->devfn >> 3) + iIrqPinBridge) & 3;
2260
2261	/* Get the parent. */
2262	pBus = pBus->PciDev.Int.s.CTX_SUFF(pBus);
2263	pPciDevBus = &pBus->PciDev;
2264	} while (pBus->iBus != 0);
2265
2266	AssertMsg(pBus->iBus == 0, ("This is not the host pci bus iBus=%d\n", pBus->iBus));
2267	pciSetIrqInternal(PCIBUS_2_PCIGLOBALS(pBus), uDevFnBridge, pPciDev, iIrqPinBridge, iLevel);
2268	}
2269
2270	#ifdef IN_RING3
2271
2272	static void pcibridgeConfigWrite(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice, uint32_t u32Address, uint32_t u32Value, unsigned cb)
2273	{
2274	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
2275
2276	LogFlowFunc((": pDevIns=%p iBus=%d iDevice=%d u32Address=%u u32Value=%u cb=%d\n", pDevIns, iBus, iDevice, u32Address, u32Value, cb));
2277
2278	/* If the current bus is not the target bus search for the bus which contains the device. */
2279	if (iBus != pBus->PciDev.config[VBOX_PCI_SECONDARY_BUS])
2280	{
2281	PPCIDEVICE pBridgeDevice = pciFindBridge(pBus, iBus);
2282	if (pBridgeDevice)
2283	{
2284	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigWrite);
2285	pBridgeDevice->Int.s.pfnBridgeConfigWrite(pBridgeDevice->pDevIns, iBus, iDevice, u32Address, u32Value, cb);
2286	}
2287	}
2288	else
2289	{
2290	/* This is the target bus, pass the write to the device. */
2291	PPCIDEVICE pPciDev = pBus->devices[iDevice];
2292	if (pPciDev)
2293	{
2294	Log(("%s: %s: addr=%02x val=%08x len=%d\n", __FUNCTION__, pPciDev->name, u32Address, u32Value, cb));
2295	pPciDev->Int.s.pfnConfigWrite(pPciDev, u32Address, u32Value, cb);
2296	}
2297	}
2298	}
2299
2300	static uint32_t pcibridgeConfigRead(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice, uint32_t u32Address, unsigned cb)
2301	{
2302	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
2303	uint32_t u32Value = 0xffffffff; /* Return value in case there is no device. */
2304
2305	LogFlowFunc((": pDevIns=%p iBus=%d iDevice=%d u32Address=%u cb=%d\n", pDevIns, iBus, iDevice, u32Address, cb));
2306
2307	/* If the current bus is not the target bus search for the bus which contains the device. */
2308	if (iBus != pBus->PciDev.config[VBOX_PCI_SECONDARY_BUS])
2309	{
2310	PPCIDEVICE pBridgeDevice = pciFindBridge(pBus, iBus);
2311	if (pBridgeDevice)
2312	{
2313	AssertPtr( pBridgeDevice->Int.s.pfnBridgeConfigRead);
2314	u32Value = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->pDevIns, iBus, iDevice, u32Address, cb);
2315	}
2316	}
2317	else
2318	{
2319	/* This is the target bus, pass the read to the device. */
2320	PPCIDEVICE pPciDev = pBus->devices[iDevice];
2321	if (pPciDev)
2322	{
2323	u32Value = pPciDev->Int.s.pfnConfigRead(pPciDev, u32Address, cb);
2324	Log(("%s: %s: u32Address=%02x u32Value=%08x cb=%d\n", __FUNCTION__, pPciDev->name, u32Address, u32Value, cb));
2325	}
2326	}
2327
2328	return u32Value;
2329	}
2330
2331
2332	/**
2333	* @copydoc FNSSMDEVSAVEEXEC
2334	*/
2335	static DECLCALLBACK(int) pcibridgeR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
2336	{
2337	PPCIBUS pThis = PDMINS_2_DATA(pDevIns, PPCIBUS);
2338	return pciR3CommonSaveExec(pThis, pSSM);
2339	}
2340
2341
2342	/**
2343	* @copydoc FNSSMDEVLOADEXEC
2344	*/
2345	static DECLCALLBACK(int) pcibridgeR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2346	{
2347	PPCIBUS pThis = PDMINS_2_DATA(pDevIns, PPCIBUS);
2348	if (uVersion > VBOX_PCI_SAVED_STATE_VERSION)
2349	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2350	return pciR3CommonLoadExec(pThis, pSSM, uVersion, uPass);
2351	}
2352
2353
2354	/**
2355	* Registers the device with the default PCI bus.
2356	*
2357	* @returns VBox status code.
2358	* @param pDevIns Device instance of the PCI Bus.
2359	* @param pPciDev The PCI device structure.
2360	* Any PCI enabled device must keep this in it's instance data!
2361	* Fill in the PCI data config before registration, please.
2362	* @param pszName Pointer to device name (permanent, readonly). For debugging, not unique.
2363	* @param iDev The PCI device number. Use a negative value for auto assigning one.
2364	*/
2365	static DECLCALLBACK(int) pcibridgeRegister(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, const char *pszName, int iDev)
2366	{
2367	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
2368
2369	/*
2370	* Check input.
2371	*/
2372	if ( !pszName
2373	\|\| !pPciDev
2374	\|\| iDev >= (int)RT_ELEMENTS(pBus->devices))
2375	{
2376	AssertMsgFailed(("Invalid argument! pszName=%s pPciDev=%p iDev=%d\n", pszName, pPciDev, iDev));
2377	return VERR_INVALID_PARAMETER;
2378	}
2379
2380	/*
2381	* Register the device.
2382	*/
2383	return pciRegisterInternal(pBus, iDev, pPciDev, pszName);
2384	}
2385
2386
2387	/**
2388	* @copydoc FNPDMDEVRESET
2389	*/
2390	static DECLCALLBACK(void) pcibridgeReset(PPDMDEVINS pDevIns)
2391	{
2392	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
2393
2394	/* Reset config space to default values. */
2395	pBus->PciDev.config[VBOX_PCI_PRIMARY_BUS] = 0;
2396	pBus->PciDev.config[VBOX_PCI_SECONDARY_BUS] = 0;
2397	pBus->PciDev.config[VBOX_PCI_SUBORDINATE_BUS] = 0;
2398	}
2399
2400
2401	/**
2402	* @copydoc FNPDMDEVRELOCATE
2403	*/
2404	static DECLCALLBACK(void) pcibridgeRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
2405	{
2406	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
2407	pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2408
2409	/* Relocate RC pointers for the attached pci devices. */
2410	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->devices); i++)
2411	{
2412	if (pBus->devices[i])
2413	pBus->devices[i]->Int.s.pBusRC += offDelta;
2414	}
2415	}
2416
2417
2418	/**
2419	* @interface_method_impl{PDMDEVREG,pfnConstruct}
2420	*/
2421	static DECLCALLBACK(int) pcibridgeConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
2422	{
2423	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
2424
2425	/*
2426	* Validate and read configuration.
2427	*/
2428	if (!CFGMR3AreValuesValid(pCfg, "GCEnabled\0" "R0Enabled\0"))
2429	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
2430
2431	/* check if RC code is enabled. */
2432	bool fGCEnabled;
2433	int rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
2434	if (RT_FAILURE(rc))
2435	return PDMDEV_SET_ERROR(pDevIns, rc,
2436	N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
2437
2438	/* check if R0 code is enabled. */
2439	bool fR0Enabled;
2440	rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
2441	if (RT_FAILURE(rc))
2442	return PDMDEV_SET_ERROR(pDevIns, rc,
2443	N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
2444	Log(("PCI: fGCEnabled=%RTbool fR0Enabled=%RTbool\n", fGCEnabled, fR0Enabled));
2445
2446	/*
2447	* Init data and register the PCI bus.
2448	*/
2449	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
2450	pBus->pDevInsR3 = pDevIns;
2451	pBus->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2452	pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2453	pBus->papBridgesR3 = (PPCIDEVICE )PDMDevHlpMMHeapAllocZ(pDevIns, sizeof(PPCIDEVICE) RT_ELEMENTS(pBus->devices));
2454
2455	PDMPCIBUSREG PciBusReg;
2456	PciBusReg.u32Version = PDM_PCIBUSREG_VERSION;
2457	PciBusReg.pfnRegisterR3 = pcibridgeRegister;
2458	PciBusReg.pfnRegisterMsiR3 = NULL;
2459	PciBusReg.pfnIORegionRegisterR3 = pciIORegionRegister;
2460	PciBusReg.pfnSetConfigCallbacksR3 = pciSetConfigCallbacks;
2461	PciBusReg.pfnSetIrqR3 = pcibridgeSetIrq;
2462	PciBusReg.pfnSaveExecR3 = pciGenericSaveExec;
2463	PciBusReg.pfnLoadExecR3 = pciGenericLoadExec;
2464	PciBusReg.pfnFakePCIBIOSR3 = NULL; /* Only needed for the first bus. */
2465	PciBusReg.pszSetIrqRC = fGCEnabled ? "pcibridgeSetIrq" : NULL;
2466	PciBusReg.pszSetIrqR0 = fR0Enabled ? "pcibridgeSetIrq" : NULL;
2467	rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBus->pPciHlpR3);
2468	if (RT_FAILURE(rc))
2469	return PDMDEV_SET_ERROR(pDevIns, rc,
2470	N_("Failed to register ourselves as a PCI Bus"));
2471	if (pBus->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
2472	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
2473	N_("PCI helper version mismatch; got %#x expected %#x"),
2474	pBus->pPciHlpR3->u32Version, PDM_PCIHLPR3_VERSION);
2475
2476	pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
2477	pBus->pPciHlpR0 = pBus->pPciHlpR3->pfnGetR0Helpers(pDevIns);
2478
2479	/*
2480	* Fill in PCI configs and add them to the bus.
2481	*/
2482	PCIDevSetVendorId( &pBus->PciDev, 0x8086); /* Intel */
2483	PCIDevSetDeviceId( &pBus->PciDev, 0x2448); /* 82801 Mobile PCI bridge. */
2484	PCIDevSetRevisionId(&pBus->PciDev, 0xf2);
2485	PCIDevSetClassSub( &pBus->PciDev, 0x04); /* pci2pci */
2486	PCIDevSetClassBase( &pBus->PciDev, 0x06); /* PCI_bridge */
2487	PCIDevSetClassProg( &pBus->PciDev, 0x01); /* Supports subtractive decoding. */
2488	PCIDevSetHeaderType(&pBus->PciDev, 0x01); /* Single function device which adheres to the PCI-to-PCI bridge spec. */
2489	PCIDevSetCommand( &pBus->PciDev, 0x00);
2490	PCIDevSetStatus( &pBus->PciDev, 0x20); /* 66MHz Capable. */
2491	PCIDevSetInterruptLine(&pBus->PciDev, 0x00); /* This device does not assert interrupts. */
2492
2493	/*
2494	* This device does not generate interrupts. Interrupt delivery from
2495	* devices attached to the bus is unaffected.
2496	*/
2497	PCIDevSetInterruptPin (&pBus->PciDev, 0x00);
2498
2499	pBus->PciDev.pDevIns = pDevIns;
2500
2501	/* Bridge-specific data */
2502	pciDevSetPci2PciBridge(&pBus->PciDev);
2503	pBus->PciDev.Int.s.pfnBridgeConfigRead = pcibridgeConfigRead;
2504	pBus->PciDev.Int.s.pfnBridgeConfigWrite = pcibridgeConfigWrite;
2505
2506	/*
2507	* Register this PCI bridge. The called function will take care on which bus we will get registered.
2508	*/
2509	rc = PDMDevHlpPCIRegister (pDevIns, &pBus->PciDev);
2510	if (RT_FAILURE(rc))
2511	return rc;
2512
2513	pBus->iDevSearch = 0;
2514	/*
2515	* The iBus property doesn't really represent the bus number
2516	* because the guest and the BIOS can choose different bus numbers
2517	* for them.
2518	* The bus number is mainly for the setIrq function to indicate
2519	* when the host bus is reached which will have iBus = 0.
2520	* That's why the + 1.
2521	*/
2522	pBus->iBus = iInstance + 1;
2523
2524	/*
2525	* Register SSM handlers. We use the same saved state version as for the host bridge
2526	* to make changes easier.
2527	*/
2528	rc = PDMDevHlpSSMRegisterEx(pDevIns, VBOX_PCI_SAVED_STATE_VERSION, sizeof(pBus) + 16128, "pgm",
2529	NULL, NULL, NULL,
2530	NULL, pcibridgeR3SaveExec, NULL,
2531	NULL, pcibridgeR3LoadExec, NULL);
2532	if (RT_FAILURE(rc))
2533	return rc;
2534
2535	return VINF_SUCCESS;
2536	}
2537
2538
2539	/**
2540	* The device registration structure
2541	* for the PCI-to-PCI bridge.
2542	*/
2543	const PDMDEVREG g_DevicePCIBridge =
2544	{
2545	/* u32Version */
2546	PDM_DEVREG_VERSION,
2547	/* szName */
2548	"pcibridge",
2549	/* szRCMod */
2550	"VBoxDDGC.gc",
2551	/* szR0Mod */
2552	"VBoxDDR0.r0",
2553	/* pszDescription */
2554	"82801 Mobile PCI to PCI bridge",
2555	/* fFlags */
2556	PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
2557	/* fClass */
2558	PDM_DEVREG_CLASS_BUS_PCI,
2559	/* cMaxInstances */
2560	~0,
2561	/* cbInstance */
2562	sizeof(PCIBUS),
2563	/* pfnConstruct */
2564	pcibridgeConstruct,
2565	/* pfnDestruct */
2566	NULL,
2567	/* pfnRelocate */
2568	pcibridgeRelocate,
2569	/* pfnIOCtl */
2570	NULL,
2571	/* pfnPowerOn */
2572	NULL,
2573	/* pfnReset */
2574	pcibridgeReset,
2575	/* pfnSuspend */
2576	NULL,
2577	/* pfnResume */
2578	NULL,
2579	/* pfnAttach */
2580	NULL,
2581	/* pfnDetach */
2582	NULL,
2583	/* pfnQueryInterface */
2584	NULL,
2585	/* pfnInitComplete */
2586	NULL,
2587	/* pfnPowerOff */
2588	NULL,
2589	/* pfnSoftReset */
2590	NULL,
2591	/* u32VersionEnd */
2592	PDM_DEVREG_VERSION
2593	};
2594
2595	#endif /* IN_RING3 */
2596	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */

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source: vbox/trunk/src/VBox/Devices/Bus/DevPCI.cpp@ 38852

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