DevPCI.cpp@ 63845

Last change on this file since 63845 was 63685, checked in by vboxsync, 8 years ago
PDM,DevPci*: Allow larger PCI region sizes.
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1	/* $Id: DevPCI.cpp 63685 2016-09-02 10:28:52Z vboxsync $ */
2	/** @file
3	* DevPCI - PCI BUS Device.
4	*/
5
6	/*
7	* Copyright (C) 2006-2016 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	* --------------------------------------------------------------------
17	*
18	* This code is based on:
19	*
20	* QEMU PCI bus manager
21	*
22	* Copyright (c) 2004 Fabrice Bellard
23	*
24	* Permission is hereby granted, free of charge, to any person obtaining a copy
25	* of this software and associated documentation files (the "Software"), to deal
26	* in the Software without restriction, including without limitation the rights
27	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
28	* copies of the Software, and to permit persons to whom the Software is
29	* furnished to do so, subject to the following conditions:
30	*
31	* The above copyright notice and this permission notice shall be included in
32	* all copies or substantial portions of the Software.
33	*
34	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
35	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
36	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
37	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
38	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
39	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
40	* THE SOFTWARE.
41	*/
42
43
44	/*********************************************************************************************************************************
45	* Header Files *
46	*********************************************************************************************************************************/
47	#define LOG_GROUP LOG_GROUP_DEV_PCI
48	/* Hack to get PCIDEVICEINT declared at the right point - include "PCIInternal.h". */
49	#define PCI_INCLUDE_PRIVATE
50	#include <VBox/pci.h>
51	#include <VBox/vmm/pdmdev.h>
52	#include <VBox/vmm/mm.h>
53	#include <iprt/asm.h>
54	#include <iprt/assert.h>
55	#include <iprt/string.h>
56
57	#include "VBoxDD.h"
58
59
60	/*********************************************************************************************************************************
61	* Structures and Typedefs *
62	*********************************************************************************************************************************/
63	/**
64	* PIIX3 ISA Bridge state.
65	*/
66	typedef struct PIIX3State
67	{
68	/** The PCI device of the bridge. */
69	PCIDEVICE dev;
70	} PIIX3State, PIIX3, *PPIIX3;
71
72	/**
73	* PCI Bus instance.
74	*/
75	typedef struct PCIBus
76	{
77	/** Bus number. */
78	int32_t iBus;
79	/** Start device number. */
80	int32_t iDevSearch;
81	/** Number of bridges attached to the bus. */
82	uint32_t cBridges;
83
84	uint32_t Alignment0;
85
86	/** Array of PCI devices. */
87	R3PTRTYPE(PPCIDEVICE) devices[256];
88	/** Array of bridges attached to the bus. */
89	R3PTRTYPE(PPCIDEVICE *) papBridgesR3;
90
91	/** R3 pointer to the device instance. */
92	PPDMDEVINSR3 pDevInsR3;
93	/** Pointer to the PCI R3 helpers. */
94	PCPDMPCIHLPR3 pPciHlpR3;
95
96	/** R0 pointer to the device instance. */
97	PPDMDEVINSR0 pDevInsR0;
98	/** Pointer to the PCI R0 helpers. */
99	PCPDMPCIHLPR0 pPciHlpR0;
100
101	/** RC pointer to the device instance. */
102	PPDMDEVINSRC pDevInsRC;
103	/** Pointer to the PCI RC helpers. */
104	PCPDMPCIHLPRC pPciHlpRC;
105
106	/** The PCI device for the PCI bridge. */
107	PCIDEVICE PciDev;
108
109	} PCIBUS;
110	/** Pointer to a PCIBUS instance. */
111	typedef PCIBUS *PPCIBUS;
112	typedef PCIBUS PCIBus;
113
114	/** @def PCI_IRQ_PINS
115	* Number of pins for interrupts (PIRQ#0...PIRQ#3)
116	*/
117	#define PCI_IRQ_PINS 4
118
119	/** @def PCI_APIC_IRQ_PINS
120	* Number of pins for interrupts if the APIC is used.
121	*/
122	#define PCI_APIC_IRQ_PINS 8
123
124	/**
125	* PCI Globals - This is the host-to-pci bridge and the root bus.
126	*/
127	typedef struct PCIGLOBALS
128	{
129	/** Irq levels for the four PCI Irqs.
130	* These count how many devices asserted
131	* the IRQ line. If greater 0 an IRQ is sent to the guest.
132	* If it drops to 0 the IRQ is deasserted.
133	*/
134	volatile uint32_t pci_irq_levels[PCI_IRQ_PINS];
135
136	#if 1 /* Will be moved into the BIOS soon. */
137	/** The next I/O port address which the PCI BIOS will use. */
138	uint32_t pci_bios_io_addr;
139	/** The next MMIO address which the PCI BIOS will use. */
140	uint32_t pci_bios_mem_addr;
141	/** Actual bus number. */
142	uint8_t uBus;
143	#endif
144
145	/** I/O APIC usage flag */
146	bool fUseIoApic;
147	/** I/O APIC irq levels */
148	volatile uint32_t pci_apic_irq_levels[PCI_APIC_IRQ_PINS];
149	/** ACPI IRQ level */
150	uint32_t acpi_irq_level;
151	/** ACPI PIC IRQ */
152	int acpi_irq;
153	/** Config register. */
154	uint32_t uConfigReg;
155
156	/** R3 pointer to the device instance. */
157	PPDMDEVINSR3 pDevInsR3;
158	/** R0 pointer to the device instance. */
159	PPDMDEVINSR0 pDevInsR0;
160	/** RC pointer to the device instance. */
161	PPDMDEVINSRC pDevInsRC;
162
163	#if HC_ARCH_BITS == 64
164	uint32_t Alignment0;
165	#endif
166
167	/** ISA bridge state. */
168	PIIX3 PIIX3State;
169	/** PCI bus which is attached to the host-to-PCI bridge. */
170	PCIBUS PciBus;
171
172	} PCIGLOBALS;
173	/** Pointer to per VM data. */
174	typedef PCIGLOBALS *PPCIGLOBALS;
175
176
177	/*********************************************************************************************************************************
178	* Defined Constants And Macros *
179	*********************************************************************************************************************************/
180
181	/** Converts a bus instance pointer to a device instance pointer. */
182	#define PCIBUS_2_DEVINS(pPciBus) ((pPciBus)->CTX_SUFF(pDevIns))
183	/** Converts a PCI bus device instance pointer to a PCIGLOBALS pointer. */
184	#define DEVINS_2_PCIGLOBALS(pDevIns) ((PPCIGLOBALS)(PDMINS_2_DATA(pDevIns, PPCIGLOBALS)))
185	/** Converts a PCI bus device instance pointer to a PCIBUS pointer. */
186	#define DEVINS_2_PCIBUS(pDevIns) ((PPCIBUS)(&PDMINS_2_DATA(pDevIns, PPCIGLOBALS)->PciBus))
187
188	/** Converts a pointer to a PCI bus instance to a PCIGLOBALS pointer.
189	* @note This works only if the bus number is 0!!!
190	*/
191	#define PCIBUS_2_PCIGLOBALS(pPciBus) RT_FROM_MEMBER(pPciBus, PCIGLOBALS, PciBus)
192
193	/** @def PCI_LOCK
194	* Acquires the PDM lock. This is a NOP if locking is disabled. */
195	/** @def PCI_UNLOCK
196	* Releases the PDM lock. This is a NOP if locking is disabled. */
197	#define PCI_LOCK(pDevIns, rc) \
198	do { \
199	int rc2 = DEVINS_2_PCIBUS(pDevIns)->CTX_SUFF(pPciHlp)->pfnLock((pDevIns), rc); \
200	if (rc2 != VINF_SUCCESS) \
201	return rc2; \
202	} while (0)
203	#define PCI_UNLOCK(pDevIns) \
204	DEVINS_2_PCIBUS(pDevIns)->CTX_SUFF(pPciHlp)->pfnUnlock(pDevIns)
205
206	/** @def VBOX_PCI_SAVED_STATE_VERSION
207	* Saved state version of the PCI bus device.
208	*/
209	#define VBOX_PCI_SAVED_STATE_VERSION 3
210
211
212	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
213
214
215	/*********************************************************************************************************************************
216	* Internal Functions *
217	*********************************************************************************************************************************/
218	RT_C_DECLS_BEGIN
219
220	PDMBOTHCBDECL(void) pciSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel, uint32_t uTag);
221	PDMBOTHCBDECL(void) pcibridgeSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel, uint32_t uTag);
222	PDMBOTHCBDECL(int) pciIOPortAddressWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
223	PDMBOTHCBDECL(int) pciIOPortAddressRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb);
224	PDMBOTHCBDECL(int) pciIOPortDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
225	PDMBOTHCBDECL(int) pciIOPortDataRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb);
226
227	#ifdef IN_RING3
228	DECLINLINE(PPCIDEVICE) pciR3FindBridge(PPCIBUS pBus, uint8_t iBus);
229	#endif
230
231	RT_C_DECLS_END
232
233	#define DEBUG_PCI
234
235	#define PCI_VENDOR_ID 0x00 /* 16 bits */
236	#define PCI_DEVICE_ID 0x02 /* 16 bits */
237	#define PCI_COMMAND 0x04 /* 16 bits */
238	#define PCI_COMMAND_IO 0x01 /* Enable response in I/O space */
239	#define PCI_COMMAND_MEMORY 0x02 /* Enable response in Memory space */
240	#define PCI_CLASS_DEVICE 0x0a /* Device class */
241	#define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
242	#define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
243	#define PCI_MIN_GNT 0x3e /* 8 bits */
244	#define PCI_MAX_LAT 0x3f /* 8 bits */
245
246
247	#ifdef IN_RING3
248
249	static void pci_update_mappings(PCIDevice *d)
250	{
251	PPCIBUS pBus = d->Int.s.CTX_SUFF(pBus);
252	PCIIORegion *r;
253	int cmd, i;
254	uint32_t last_addr, new_addr, config_ofs;
255
256	cmd = RT_LE2H_U16((uint16_t )(d->config + PCI_COMMAND));
257	for(i = 0; i < PCI_NUM_REGIONS; i++) {
258	r = &d->Int.s.aIORegions[i];
259	if (i == PCI_ROM_SLOT) {
260	config_ofs = 0x30;
261	} else {
262	config_ofs = 0x10 + i * 4;
263	}
264	if (r->size != 0) {
265	if (r->type & PCI_ADDRESS_SPACE_IO) {
266	if (cmd & PCI_COMMAND_IO) {
267	new_addr = RT_LE2H_U32((uint32_t )(d->config +
268	config_ofs));
269	new_addr = new_addr & ~(r->size - 1);
270	last_addr = new_addr + r->size - 1;
271	/* NOTE: we have only 64K ioports on PC */
272	if (last_addr <= new_addr \|\| new_addr == 0 \|\|
273	last_addr >= 0x10000) {
274	new_addr = ~0U;
275	}
276	} else {
277	new_addr = ~0U;
278	}
279	} else {
280	if (cmd & PCI_COMMAND_MEMORY) {
281	new_addr = RT_LE2H_U32((uint32_t )(d->config +
282	config_ofs));
283	/* the ROM slot has a specific enable bit */
284	if (i == PCI_ROM_SLOT && !(new_addr & 1))
285	goto no_mem_map;
286	new_addr = new_addr & ~(r->size - 1);
287	last_addr = new_addr + r->size - 1;
288	/* NOTE: we do not support wrapping */
289	/* XXX: as we cannot support really dynamic
290	mappings, we handle specific values as invalid
291	mappings. */
292	/* Unconditionally exclude I/O-APIC/HPET/ROM. Pessimistic, but better than causing a mess. */
293	if (last_addr <= new_addr \|\| new_addr == 0 \|\|
294	(new_addr <= ~0U && last_addr >= 0xfec00000U)) {
295	new_addr = ~0U;
296	}
297	} else {
298	no_mem_map:
299	new_addr = ~0U;
300	}
301	}
302	//LogRel(("PCI: config dev %u/%u BAR%i uOld=%#018llx uNew=%#018llx size=%llu\n", d->devfn >> 3, d->devfn & 7, i, r->addr, new_addr, r->size));
303	/* now do the real mapping */
304	if (new_addr != r->addr) {
305	if (r->addr != ~0U) {
306	if (r->type & PCI_ADDRESS_SPACE_IO) {
307	int devclass;
308	/* NOTE: specific hack for IDE in PC case:
309	only one byte must be mapped. */
310	devclass = d->config[0x0a] \| (d->config[0x0b] << 8);
311	if (devclass == 0x0101 && r->size == 4) {
312	int rc = PDMDevHlpIOPortDeregister(d->pDevIns, r->addr + 2, 1);
313	AssertRC(rc);
314	} else {
315	int rc = PDMDevHlpIOPortDeregister(d->pDevIns, r->addr, r->size);
316	AssertRC(rc);
317	}
318	} else {
319	RTGCPHYS GCPhysBase = r->addr;
320	int rc;
321	if (pBus->pPciHlpR3->pfnIsMMIO2Base(pBus->pDevInsR3, d->pDevIns, GCPhysBase))
322	{
323	/* unmap it. */
324	rc = r->map_func(d, i, NIL_RTGCPHYS, r->size, (PCIADDRESSSPACE)(r->type));
325	AssertRC(rc);
326	rc = PDMDevHlpMMIO2Unmap(d->pDevIns, i, GCPhysBase);
327	}
328	else
329	rc = PDMDevHlpMMIODeregister(d->pDevIns, GCPhysBase, r->size);
330	AssertMsgRC(rc, ("rc=%Rrc d=%s i=%d GCPhysBase=%RGp size=%#x\n", rc, d->name, i, GCPhysBase, r->size));
331	}
332	}
333	r->addr = new_addr;
334	if (r->addr != ~0U) {
335	int rc = r->map_func(d, i,
336	r->addr + (r->type & PCI_ADDRESS_SPACE_IO ? 0 : 0),
337	r->size, (PCIADDRESSSPACE)(r->type));
338	AssertRC(rc);
339	}
340	}
341	}
342	}
343	}
344
345
346	static DECLCALLBACK(uint32_t) pci_default_read_config(PCIDevice *d, uint32_t address, unsigned len)
347	{
348	uint32_t val;
349	switch(len) {
350	case 1:
351	val = d->config[address];
352	break;
353	case 2:
354	val = RT_LE2H_U16((uint16_t )(d->config + address));
355	break;
356	default:
357	case 4:
358	val = RT_LE2H_U32((uint32_t )(d->config + address));
359	break;
360	}
361	return val;
362	}
363
364	static DECLCALLBACK(void) pci_default_write_config(PCIDevice *d, uint32_t address, uint32_t val, unsigned len)
365	{
366	int can_write;
367	unsigned i;
368	uint32_t end, addr;
369
370	if (len == 4 && ((address >= 0x10 && address < 0x10 + 4 * 6) \|\|
371	(address >= 0x30 && address < 0x34))) {
372	PCIIORegion *r;
373	int reg;
374
375	if ( address >= 0x30 ) {
376	reg = PCI_ROM_SLOT;
377	}else{
378	reg = (address - 0x10) >> 2;
379	}
380	r = &d->Int.s.aIORegions[reg];
381	if (r->size == 0)
382	goto default_config;
383	/* compute the stored value */
384	if (reg == PCI_ROM_SLOT) {
385	/* keep ROM enable bit */
386	val &= (~(r->size - 1)) \| 1;
387	} else {
388	val &= ~(r->size - 1);
389	val \|= r->type;
390	}
391	(uint32_t )(d->config + address) = RT_H2LE_U32(val);
392	pci_update_mappings(d);
393	return;
394	}
395	default_config:
396	/* not efficient, but simple */
397	addr = address;
398	for(i = 0; i < len; i++) {
399	/* default read/write accesses */
400	switch(d->config[0x0e]) {
401	case 0x00: /* normal device */
402	case 0x80: /* multi-function device */
403	switch(addr) {
404	case 0x00:
405	case 0x01:
406	case 0x02:
407	case 0x03:
408	case 0x08:
409	case 0x09:
410	case 0x0a:
411	case 0x0b:
412	case 0x0e:
413	case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17: /* base */
414	case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f:
415	case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27:
416	case 0x2c: case 0x2d: /* subsystem ID */
417	case 0x2e: case 0x2f: /* vendor ID */
418	case 0x30: case 0x31: case 0x32: case 0x33: /* rom */
419	case 0x34: /* Capabilities pointer. */
420	case 0x3d: /* Interrupt pin. */
421	can_write = 0;
422	break;
423	default:
424	can_write = 1;
425	break;
426	}
427	break;
428	default:
429	case 0x01: /* bridge */
430	switch(addr) {
431	case 0x00:
432	case 0x01:
433	case 0x02:
434	case 0x03:
435	case 0x08:
436	case 0x09:
437	case 0x0a:
438	case 0x0b:
439	case 0x0e:
440	case 0x38: case 0x39: case 0x3a: case 0x3b: /* rom */
441	case 0x3d:
442	can_write = 0;
443	break;
444	default:
445	can_write = 1;
446	break;
447	}
448	break;
449	}
450	#ifdef VBOX
451	if (addr == 0x05) /* Command register, bits 8-15. */
452	{
453	/* don't change reserved bits (11-15) */
454	val &= ~UINT32_C(0xf8);
455	d->config[addr] = val;
456	}
457	else if (addr == 0x06) /* Status register, bits 0-7. */
458	{
459	/* don't change read-only bits => actually all lower bits are read-only */
460	val &= ~UINT32_C(0xff);
461	/* status register, low part: clear bits by writing a '1' to the corresponding bit */
462	d->config[addr] &= ~val;
463	}
464	else if (addr == 0x07) /* Status register, bits 8-15. */
465	{
466	/* don't change read-only bits */
467	val &= ~UINT32_C(0x06);
468	/* status register, high part: clear bits by writing a '1' to the corresponding bit */
469	d->config[addr] &= ~val;
470	}
471	else
472	#endif
473	if (can_write) {
474	d->config[addr] = val;
475	}
476	addr++;
477	val >>= 8;
478	}
479
480	end = address + len;
481	if (end > PCI_COMMAND && address < (PCI_COMMAND + 2)) {
482	/* if the command register is modified, we must modify the mappings */
483	pci_update_mappings(d);
484	}
485	}
486
487	#endif /* IN_RING3 */
488
489	static int pci_data_write(PPCIGLOBALS pGlobals, uint32_t addr, uint32_t val, int len)
490	{
491	uint8_t iBus, iDevice;
492	uint32_t config_addr;
493
494	Log(("pci_data_write: addr=%08x val=%08x len=%d\n", pGlobals->uConfigReg, val, len));
495
496	if (!(pGlobals->uConfigReg & (1 << 31))) {
497	return VINF_SUCCESS;
498	}
499	if ((pGlobals->uConfigReg & 0x3) != 0) {
500	return VINF_SUCCESS;
501	}
502	iBus = (pGlobals->uConfigReg >> 16) & 0xff;
503	iDevice = (pGlobals->uConfigReg >> 8) & 0xff;
504	config_addr = (pGlobals->uConfigReg & 0xfc) \| (addr & 3);
505	if (iBus != 0)
506	{
507	if (pGlobals->PciBus.cBridges)
508	{
509	#ifdef IN_RING3 /** @todo do lookup in R0/RC too! */
510	PPCIDEVICE pBridgeDevice = pciR3FindBridge(&pGlobals->PciBus, iBus);
511	if (pBridgeDevice)
512	{
513	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigWrite);
514	pBridgeDevice->Int.s.pfnBridgeConfigWrite(pBridgeDevice->pDevIns, iBus, iDevice, config_addr, val, len);
515	}
516	#else
517	RT_NOREF2(val, len);
518	return VINF_IOM_R3_IOPORT_WRITE;
519	#endif
520	}
521	}
522	else
523	{
524	R3PTRTYPE(PCIDevice *) pci_dev = pGlobals->PciBus.devices[iDevice];
525	if (pci_dev)
526	{
527	#ifdef IN_RING3
528	Log(("pci_config_write: %s: addr=%02x val=%08x len=%d\n", pci_dev->name, config_addr, val, len));
529	pci_dev->Int.s.pfnConfigWrite(pci_dev, config_addr, val, len);
530	#else
531	return VINF_IOM_R3_IOPORT_WRITE;
532	#endif
533	}
534	}
535	return VINF_SUCCESS;
536	}
537
538	static int pci_data_read(PPCIGLOBALS pGlobals, uint32_t addr, int len, uint32_t *pu32)
539	{
540	uint8_t iBus, iDevice;
541	uint32_t config_addr;
542
543	*pu32 = 0xffffffff;
544
545	if (!(pGlobals->uConfigReg & (1 << 31)))
546	return VINF_SUCCESS;
547	if ((pGlobals->uConfigReg & 0x3) != 0)
548	return VINF_SUCCESS;
549	iBus = (pGlobals->uConfigReg >> 16) & 0xff;
550	iDevice = (pGlobals->uConfigReg >> 8) & 0xff;
551	config_addr = (pGlobals->uConfigReg & 0xfc) \| (addr & 3);
552	if (iBus != 0)
553	{
554	if (pGlobals->PciBus.cBridges)
555	{
556	#ifdef IN_RING3 /** @todo do lookup in R0/RC too! */
557	PPCIDEVICE pBridgeDevice = pciR3FindBridge(&pGlobals->PciBus, iBus);
558	if (pBridgeDevice)
559	{
560	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigRead);
561	*pu32 = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->pDevIns, iBus, iDevice, config_addr, len);
562	}
563	#else
564	NOREF(len);
565	return VINF_IOM_R3_IOPORT_READ;
566	#endif
567	}
568	}
569	else
570	{
571	R3PTRTYPE(PCIDevice *) pci_dev = pGlobals->PciBus.devices[iDevice];
572	if (pci_dev)
573	{
574	#ifdef IN_RING3
575	*pu32 = pci_dev->Int.s.pfnConfigRead(pci_dev, config_addr, len);
576	Log(("pci_config_read: %s: addr=%02x val=%08x len=%d\n", pci_dev->name, config_addr, *pu32, len));
577	#else
578	NOREF(len);
579	return VINF_IOM_R3_IOPORT_READ;
580	#endif
581	}
582	}
583
584	return VINF_SUCCESS;
585	}
586
587
588
589	/* return the global irq number corresponding to a given device irq
590	pin. We could also use the bus number to have a more precise
591	mapping.
592	This is the implementation note described in the PCI spec chapter 2.2.6 */
593	static inline int pci_slot_get_pirq(uint8_t uDevFn, int irq_num)
594	{
595	int slot_addend;
596	slot_addend = (uDevFn >> 3) - 1;
597	return (irq_num + slot_addend) & 3;
598	}
599
600	static inline int pci_slot_get_apic_pirq(uint8_t uDevFn, int irq_num)
601	{
602	return (irq_num + (uDevFn >> 3)) & 7;
603	}
604
605	static inline int get_pci_irq_apic_level(PPCIGLOBALS pGlobals, int irq_num)
606	{
607	return (pGlobals->pci_apic_irq_levels[irq_num] != 0);
608	}
609
610	static void apic_set_irq(PPCIBUS pBus, uint8_t uDevFn, PCIDevice *pPciDev, int irq_num1, int iLevel, int acpi_irq, uint32_t uTagSrc)
611	{
612	/* This is only allowed to be called with a pointer to the host bus. */
613	AssertMsg(pBus->iBus == 0, ("iBus=%u\n", pBus->iBus));
614
615	if (acpi_irq == -1) {
616	int apic_irq, apic_level;
617	PPCIGLOBALS pGlobals = PCIBUS_2_PCIGLOBALS(pBus);
618	int irq_num = pci_slot_get_apic_pirq(uDevFn, irq_num1);
619
620	if ((iLevel & PDM_IRQ_LEVEL_HIGH) == PDM_IRQ_LEVEL_HIGH)
621	ASMAtomicIncU32(&pGlobals->pci_apic_irq_levels[irq_num]);
622	else if ((iLevel & PDM_IRQ_LEVEL_HIGH) == PDM_IRQ_LEVEL_LOW)
623	ASMAtomicDecU32(&pGlobals->pci_apic_irq_levels[irq_num]);
624
625	apic_irq = irq_num + 0x10;
626	apic_level = get_pci_irq_apic_level(pGlobals, irq_num);
627	Log3(("apic_set_irq: %s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d\n",
628	R3STRING(pPciDev->name), irq_num1, iLevel, apic_irq, apic_level, irq_num));
629	pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), apic_irq, apic_level, uTagSrc);
630
631	if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP) {
632	ASMAtomicDecU32(&pGlobals->pci_apic_irq_levels[irq_num]);
633	pPciDev->Int.s.uIrqPinState = PDM_IRQ_LEVEL_LOW;
634	apic_level = get_pci_irq_apic_level(pGlobals, irq_num);
635	Log3(("apic_set_irq: %s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d (flop)\n",
636	R3STRING(pPciDev->name), irq_num1, iLevel, apic_irq, apic_level, irq_num));
637	pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), apic_irq, apic_level, uTagSrc);
638	}
639	} else {
640	Log3(("apic_set_irq: %s: irq_num1=%d level=%d acpi_irq=%d\n",
641	R3STRING(pPciDev->name), irq_num1, iLevel, acpi_irq));
642	pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), acpi_irq, iLevel, uTagSrc);
643	}
644	}
645
646	DECLINLINE(int) get_pci_irq_level(PPCIGLOBALS pGlobals, int irq_num)
647	{
648	return (pGlobals->pci_irq_levels[irq_num] != 0);
649	}
650
651	/**
652	* Set the IRQ for a PCI device on the host bus - shared by host bus and bridge.
653	*
654	* @param pDevIns Device instance of the host PCI Bus.
655	* @param uDevFn The device number on the host bus which will raise the IRQ
656	* @param pPciDev The PCI device structure which raised the interrupt.
657	* @param iIrq IRQ number to set.
658	* @param iLevel IRQ level.
659	* @param uTagSrc The IRQ tag and source ID (for tracing).
660	* @remark uDevFn and pPciDev->devfn are not the same if the device is behind a bridge.
661	* In that case uDevFn will be the slot of the bridge which is needed to calculate the
662	* PIRQ value.
663	*/
664	static void pciSetIrqInternal(PPCIGLOBALS pGlobals, uint8_t uDevFn, PPCIDEVICE pPciDev, int iIrq, int iLevel, uint32_t uTagSrc)
665	{
666	PPCIBUS pBus = &pGlobals->PciBus;
667	uint8_t *pbCfg = pGlobals->PIIX3State.dev.config;
668	const bool fIsAcpiDevice = pPciDev->config[2] == 0x13 && pPciDev->config[3] == 0x71;
669	/* If the two configuration space bytes at 0xde, 0xad are set to 0xbe, 0xef, a back door
670	* is opened to route PCI interrupts directly to the I/O APIC and bypass the PIC.
671	* See the \_SB_.PCI0._PRT method in vbox.dsl.
672	*/
673	const bool fIsApicEnabled = pGlobals->fUseIoApic && pbCfg[0xde] == 0xbe && pbCfg[0xad] == 0xef;
674	int pic_irq, pic_level;
675
676	/* Check if the state changed. */
677	if (pPciDev->Int.s.uIrqPinState != iLevel)
678	{
679	pPciDev->Int.s.uIrqPinState = (iLevel & PDM_IRQ_LEVEL_HIGH);
680
681	/* Send interrupt to I/O APIC only. */
682	if (fIsApicEnabled)
683	{
684	if (fIsAcpiDevice)
685	/*
686	* ACPI needs special treatment since SCI is hardwired and
687	* should not be affected by PCI IRQ routing tables at the
688	* same time SCI IRQ is shared in PCI sense hence this
689	* kludge (i.e. we fetch the hardwired value from ACPIs
690	* PCI device configuration space).
691	*/
692	apic_set_irq(pBus, uDevFn, pPciDev, -1, iLevel, pPciDev->config[PCI_INTERRUPT_LINE], uTagSrc);
693	else
694	apic_set_irq(pBus, uDevFn, pPciDev, iIrq, iLevel, -1, uTagSrc);
695	return;
696	}
697
698	if (fIsAcpiDevice)
699	{
700	/* As per above treat ACPI in a special way */
701	pic_irq = pPciDev->config[PCI_INTERRUPT_LINE];
702	pGlobals->acpi_irq = pic_irq;
703	pGlobals->acpi_irq_level = iLevel & PDM_IRQ_LEVEL_HIGH;
704	}
705	else
706	{
707	int irq_num;
708	irq_num = pci_slot_get_pirq(uDevFn, iIrq);
709
710	if (pPciDev->Int.s.uIrqPinState == PDM_IRQ_LEVEL_HIGH)
711	ASMAtomicIncU32(&pGlobals->pci_irq_levels[irq_num]);
712	else if (pPciDev->Int.s.uIrqPinState == PDM_IRQ_LEVEL_LOW)
713	ASMAtomicDecU32(&pGlobals->pci_irq_levels[irq_num]);
714
715	/* now we change the pic irq level according to the piix irq mappings */
716	pic_irq = pbCfg[0x60 + irq_num];
717	if (pic_irq >= 16)
718	{
719	if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP)
720	{
721	ASMAtomicDecU32(&pGlobals->pci_irq_levels[irq_num]);
722	pPciDev->Int.s.uIrqPinState = PDM_IRQ_LEVEL_LOW;
723	}
724
725	return;
726	}
727	}
728
729	/* the pic level is the logical OR of all the PCI irqs mapped to it */
730	pic_level = 0;
731	if (pic_irq == pbCfg[0x60])
732	pic_level \|= get_pci_irq_level(pGlobals, 0);
733	if (pic_irq == pbCfg[0x61])
734	pic_level \|= get_pci_irq_level(pGlobals, 1);
735	if (pic_irq == pbCfg[0x62])
736	pic_level \|= get_pci_irq_level(pGlobals, 2);
737	if (pic_irq == pbCfg[0x63])
738	pic_level \|= get_pci_irq_level(pGlobals, 3);
739	if (pic_irq == pGlobals->acpi_irq)
740	pic_level \|= pGlobals->acpi_irq_level;
741
742	Log3(("pciSetIrq: %s: iLevel=%d iIrq=%d pic_irq=%d pic_level=%d uTagSrc=%#x\n",
743	R3STRING(pPciDev->name), iLevel, iIrq, pic_irq, pic_level, uTagSrc));
744	pBus->CTX_SUFF(pPciHlp)->pfnIsaSetIrq(pBus->CTX_SUFF(pDevIns), pic_irq, pic_level, uTagSrc);
745
746	/** @todo optimize pci irq flip-flop some rainy day. */
747	if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP)
748	pciSetIrqInternal(pGlobals, uDevFn, pPciDev, iIrq, PDM_IRQ_LEVEL_LOW, uTagSrc);
749	}
750	}
751
752
753	/**
754	* @interface_method_impl{PDMPCIBUSREG,pfnSetIrqR3}
755	*/
756	PDMBOTHCBDECL(void) pciSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel, uint32_t uTagSrc)
757	{
758	pciSetIrqInternal(PDMINS_2_DATA(pDevIns, PPCIGLOBALS), pPciDev->devfn, pPciDev, iIrq, iLevel, uTagSrc);
759	}
760
761	#ifdef IN_RING3
762
763	/**
764	* Finds a bridge on the bus which contains the destination bus.
765	*
766	* @return Pointer to the device instance data of the bus or
767	* NULL if no bridge was found.
768	* @param pBus Pointer to the bus to search on.
769	* @param iBus Destination bus number.
770	*/
771	DECLINLINE(PPCIDEVICE) pciR3FindBridge(PPCIBUS pBus, uint8_t iBus)
772	{
773	/* Search for a fitting bridge. */
774	for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
775	{
776	/*
777	* Examine secondary and subordinate bus number.
778	* If the target bus is in the range we pass the request on to the bridge.
779	*/
780	PPCIDEVICE pBridgeTemp = pBus->papBridgesR3[iBridge];
781	AssertMsg(pBridgeTemp && pciDevIsPci2PciBridge(pBridgeTemp),
782	("Device is not a PCI bridge but on the list of PCI bridges\n"));
783
784	if ( iBus >= pBridgeTemp->config[VBOX_PCI_SECONDARY_BUS]
785	&& iBus <= pBridgeTemp->config[VBOX_PCI_SUBORDINATE_BUS])
786	return pBridgeTemp;
787	}
788
789	/* Nothing found. */
790	return NULL;
791	}
792
793	static void pciR3Piix3Reset(PIIX3State *d)
794	{
795	uint8_t *pci_conf = d->dev.config;
796
797	pci_conf[0x04] = 0x07; /* master, memory and I/O */
798	pci_conf[0x05] = 0x00;
799	pci_conf[0x06] = 0x00;
800	pci_conf[0x07] = 0x02; /* PCI_status_devsel_medium */
801	pci_conf[0x4c] = 0x4d;
802	pci_conf[0x4e] = 0x03;
803	pci_conf[0x4f] = 0x00;
804	pci_conf[0x60] = 0x80;
805	pci_conf[0x69] = 0x02;
806	pci_conf[0x70] = 0x80;
807	pci_conf[0x76] = 0x0c;
808	pci_conf[0x77] = 0x0c;
809	pci_conf[0x78] = 0x02;
810	pci_conf[0x79] = 0x00;
811	pci_conf[0x80] = 0x00;
812	pci_conf[0x82] = 0x02; /* Get rid of the Linux guest "Enabling Passive Release" PCI quirk warning. */
813	pci_conf[0xa0] = 0x08;
814	pci_conf[0xa2] = 0x00;
815	pci_conf[0xa3] = 0x00;
816	pci_conf[0xa4] = 0x00;
817	pci_conf[0xa5] = 0x00;
818	pci_conf[0xa6] = 0x00;
819	pci_conf[0xa7] = 0x00;
820	pci_conf[0xa8] = 0x0f;
821	pci_conf[0xaa] = 0x00;
822	pci_conf[0xab] = 0x00;
823	pci_conf[0xac] = 0x00;
824	pci_conf[0xae] = 0x00;
825	}
826
827	static void pci_config_writel(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t val)
828	{
829	pGlobals->uConfigReg = 0x80000000 \| (uBus << 16) \|
830	(uDevFn << 8) \| addr;
831	pci_data_write(pGlobals, 0, val, 4);
832	}
833
834	static void pci_config_writew(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t val)
835	{
836	pGlobals->uConfigReg = 0x80000000 \| (uBus << 16) \|
837	(uDevFn << 8) \| (addr & ~3);
838	pci_data_write(pGlobals, addr & 3, val, 2);
839	}
840
841	static void pci_config_writeb(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t val)
842	{
843	pGlobals->uConfigReg = 0x80000000 \| (uBus << 16) \|
844	(uDevFn << 8) \| (addr & ~3);
845	pci_data_write(pGlobals, addr & 3, val, 1);
846	}
847
848	static uint32_t pci_config_readl(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr)
849	{
850	pGlobals->uConfigReg = 0x80000000 \| (uBus << 16) \|
851	(uDevFn << 8) \| addr;
852	uint32_t u32Val;
853	int rc = pci_data_read(pGlobals, 0, 4, &u32Val);
854	AssertRC(rc);
855	return u32Val;
856	}
857
858	static uint32_t pci_config_readw(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr)
859	{
860	pGlobals->uConfigReg = 0x80000000 \| (uBus << 16) \|
861	(uDevFn << 8) \| (addr & ~3);
862	uint32_t u32Val;
863	int rc = pci_data_read(pGlobals, addr & 3, 2, &u32Val);
864	AssertRC(rc);
865	return u32Val;
866	}
867
868	static uint32_t pci_config_readb(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr)
869	{
870	pGlobals->uConfigReg = 0x80000000 \| (uBus << 16) \|
871	(uDevFn << 8) \| (addr & ~3);
872	uint32_t u32Val;
873	int rc = pci_data_read(pGlobals, addr & 3, 1, &u32Val);
874	AssertRC(rc);
875	return u32Val;
876	}
877
878	/* host irqs corresponding to PCI irqs A-D */
879	static const uint8_t pci_irqs[4] = { 11, 9, 11, 9 }; /* bird: added const */
880
881	static void pci_set_io_region_addr(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, int region_num, uint32_t addr)
882	{
883	uint32_t ofs;
884
885	if ( region_num == PCI_ROM_SLOT )
886	ofs = 0x30;
887	else
888	ofs = 0x10 + region_num * 4;
889
890	Log(("Set region address: %02x:%02x.%d region %d address=%lld\n",
891	uBus, uDevFn >> 3, uDevFn & 7, region_num, addr));
892
893	/* Write address of the device. */
894	pci_config_writel(pGlobals, uBus, uDevFn, ofs, addr);
895	}
896
897	static void pci_bios_init_device(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint8_t cBridgeDepth, uint8_t *paBridgePositions)
898	{
899	uint32_t *paddr;
900	int i, pin, pic_irq;
901	uint16_t devclass, vendor_id, device_id;
902
903	devclass = pci_config_readw(pGlobals, uBus, uDevFn, PCI_CLASS_DEVICE);
904	vendor_id = pci_config_readw(pGlobals, uBus, uDevFn, PCI_VENDOR_ID);
905	device_id = pci_config_readw(pGlobals, uBus, uDevFn, PCI_DEVICE_ID);
906
907	/* Check if device is present. */
908	if (vendor_id != 0xffff)
909	{
910	switch(devclass)
911	{
912	case 0x0101:
913	if ( (vendor_id == 0x8086)
914	&& (device_id == 0x7010 \|\| device_id == 0x7111 \|\| device_id == 0x269e))
915	{
916	/* PIIX3, PIIX4 or ICH6 IDE */
917	pci_config_writew(pGlobals, uBus, uDevFn, 0x40, 0x8000); /* enable IDE0 */
918	pci_config_writew(pGlobals, uBus, uDevFn, 0x42, 0x8000); /* enable IDE1 */
919	goto default_map;
920	}
921	else
922	{
923	/* IDE: we map it as in ISA mode */
924	pci_set_io_region_addr(pGlobals, uBus, uDevFn, 0, 0x1f0);
925	pci_set_io_region_addr(pGlobals, uBus, uDevFn, 1, 0x3f4);
926	pci_set_io_region_addr(pGlobals, uBus, uDevFn, 2, 0x170);
927	pci_set_io_region_addr(pGlobals, uBus, uDevFn, 3, 0x374);
928	pci_config_writeb(pGlobals, uBus, uDevFn, PCI_COMMAND,
929	pci_config_readb(pGlobals, uBus, uDevFn, PCI_COMMAND)
930	\| PCI_COMMAND_IOACCESS);
931	}
932	break;
933	case 0x0300:
934	if (vendor_id != 0x80ee)
935	goto default_map;
936	/* VGA: map frame buffer to default Bochs VBE address */
937	pci_set_io_region_addr(pGlobals, uBus, uDevFn, 0, 0xE0000000);
938	/*
939	* Legacy VGA I/O ports are implicitly decoded by a VGA class device. But
940	* only the framebuffer (i.e., a memory region) is explicitly registered via
941	* pci_set_io_region_addr, so don't forget to enable I/O decoding.
942	*/
943	pci_config_writeb(pGlobals, uBus, uDevFn, PCI_COMMAND,
944	pci_config_readb(pGlobals, uBus, uDevFn, PCI_COMMAND)
945	\| PCI_COMMAND_IOACCESS \| PCI_COMMAND_MEMACCESS);
946	break;
947	case 0x0800:
948	/* PIC */
949	vendor_id = pci_config_readw(pGlobals, uBus, uDevFn, PCI_VENDOR_ID);
950	device_id = pci_config_readw(pGlobals, uBus, uDevFn, PCI_DEVICE_ID);
951	if (vendor_id == 0x1014)
952	{
953	/* IBM */
954	if (device_id == 0x0046 \|\| device_id == 0xFFFF)
955	{
956	/* MPIC & MPIC2 */
957	pci_set_io_region_addr(pGlobals, uBus, uDevFn, 0, 0x80800000 + 0x00040000);
958	pci_config_writeb(pGlobals, uBus, uDevFn, PCI_COMMAND,
959	pci_config_readb(pGlobals, uBus, uDevFn, PCI_COMMAND)
960	\| PCI_COMMAND_MEMACCESS);
961	}
962	}
963	break;
964	case 0xff00:
965	if ( (vendor_id == 0x0106b)
966	&& (device_id == 0x0017 \|\| device_id == 0x0022))
967	{
968	/* macio bridge */
969	pci_set_io_region_addr(pGlobals, uBus, uDevFn, 0, 0x80800000);
970	pci_config_writeb(pGlobals, uBus, uDevFn, PCI_COMMAND,
971	pci_config_readb(pGlobals, uBus, uDevFn, PCI_COMMAND)
972	\| PCI_COMMAND_MEMACCESS);
973	}
974	break;
975	case 0x0604:
976	{
977	/* Init PCI-to-PCI bridge. */
978	pci_config_writeb(pGlobals, uBus, uDevFn, VBOX_PCI_PRIMARY_BUS, uBus);
979
980	AssertMsg(pGlobals->uBus < 255, ("Too many bridges on the bus\n"));
981	pGlobals->uBus++;
982	pci_config_writeb(pGlobals, uBus, uDevFn, VBOX_PCI_SECONDARY_BUS, pGlobals->uBus);
983	pci_config_writeb(pGlobals, uBus, uDevFn, VBOX_PCI_SUBORDINATE_BUS, 0xff); /* Temporary until we know how many other bridges are behind this one. */
984
985	/* Add position of this bridge into the array. */
986	paBridgePositions[cBridgeDepth+1] = (uDevFn >> 3);
987
988	/*
989	* The I/O range for the bridge must be aligned to a 4KB boundary.
990	* This does not change anything really as the access to the device is not going
991	* through the bridge but we want to be compliant to the spec.
992	*/
993	if ((pGlobals->pci_bios_io_addr % 4096) != 0)
994	pGlobals->pci_bios_io_addr = RT_ALIGN_32(pGlobals->pci_bios_io_addr, 4*1024);
995	Log(("%s: Aligned I/O start address. New address %#x\n", __FUNCTION__, pGlobals->pci_bios_io_addr));
996	pci_config_writeb(pGlobals, uBus, uDevFn, VBOX_PCI_IO_BASE, (pGlobals->pci_bios_io_addr >> 8) & 0xf0);
997
998	/* The MMIO range for the bridge must be aligned to a 1MB boundary. */
999	if ((pGlobals->pci_bios_mem_addr % (1024 * 1024)) != 0)
1000	pGlobals->pci_bios_mem_addr = RT_ALIGN_32(pGlobals->pci_bios_mem_addr, 1024*1024);
1001	Log(("%s: Aligned MMIO start address. New address %#x\n", __FUNCTION__, pGlobals->pci_bios_mem_addr));
1002	pci_config_writew(pGlobals, uBus, uDevFn, VBOX_PCI_MEMORY_BASE, (pGlobals->pci_bios_mem_addr >> 16) & UINT32_C(0xffff0));
1003
1004	/* Save values to compare later to. */
1005	uint32_t u32IoAddressBase = pGlobals->pci_bios_io_addr;
1006	uint32_t u32MMIOAddressBase = pGlobals->pci_bios_mem_addr;
1007
1008	/* Init devices behind the bridge and possibly other bridges as well. */
1009	for (int iDev = 0; iDev <= 255; iDev++)
1010	pci_bios_init_device(pGlobals, uBus + 1, iDev, cBridgeDepth + 1, paBridgePositions);
1011
1012	/* The number of bridges behind the this one is now available. */
1013	pci_config_writeb(pGlobals, uBus, uDevFn, VBOX_PCI_SUBORDINATE_BUS, pGlobals->uBus);
1014
1015	/*
1016	* Set I/O limit register. If there is no device with I/O space behind the bridge
1017	* we set a lower value than in the base register.
1018	* The result with a real bridge is that no I/O transactions are passed to the secondary
1019	* interface. Again this doesn't really matter here but we want to be compliant to the spec.
1020	*/
1021	if ((u32IoAddressBase != pGlobals->pci_bios_io_addr) && ((pGlobals->pci_bios_io_addr % 4096) != 0))
1022	{
1023	/* The upper boundary must be one byte less than a 4KB boundary. */
1024	pGlobals->pci_bios_io_addr = RT_ALIGN_32(pGlobals->pci_bios_io_addr, 4*1024);
1025	}
1026	pci_config_writeb(pGlobals, uBus, uDevFn, VBOX_PCI_IO_LIMIT, ((pGlobals->pci_bios_io_addr >> 8) & 0xf0) - 1);
1027
1028	/* Same with the MMIO limit register but with 1MB boundary here. */
1029	if ((u32MMIOAddressBase != pGlobals->pci_bios_mem_addr) && ((pGlobals->pci_bios_mem_addr % (1024 * 1024)) != 0))
1030	{
1031	/* The upper boundary must be one byte less than a 1MB boundary. */
1032	pGlobals->pci_bios_mem_addr = RT_ALIGN_32(pGlobals->pci_bios_mem_addr, 1024*1024);
1033	}
1034	pci_config_writew(pGlobals, uBus, uDevFn, VBOX_PCI_MEMORY_LIMIT, ((pGlobals->pci_bios_mem_addr >> 16) & UINT32_C(0xfff0)) - 1);
1035
1036	/*
1037	* Set the prefetch base and limit registers. We currently have no device with a prefetchable region
1038	* which may be behind a bridge. That's why it is unconditionally disabled here atm by writing a higher value into
1039	* the base register than in the limit register.
1040	*/
1041	pci_config_writew(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_MEMORY_BASE, 0xfff0);
1042	pci_config_writew(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_MEMORY_LIMIT, 0x0);
1043	pci_config_writel(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_BASE_UPPER32, 0x00);
1044	pci_config_writel(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_LIMIT_UPPER32, 0x00);
1045	break;
1046	}
1047	default:
1048	default_map:
1049	{
1050	/* default memory mappings */
1051	bool fActiveMemRegion = false;
1052	bool fActiveIORegion = false;
1053	/*
1054	* PCI_NUM_REGIONS is 7 because of the rom region but there are only 6 base address register defined by the PCI spec.
1055	* Leaving only PCI_NUM_REGIONS would cause reading another and enabling a memory region which does not exist.
1056	*/
1057	for(i = 0; i < (PCI_NUM_REGIONS-1); i++)
1058	{
1059	uint32_t u32Size;
1060	uint8_t u8RessourceType;
1061	uint32_t u32Address = 0x10 + i * 4;
1062
1063	/* Calculate size. */
1064	u8RessourceType = pci_config_readb(pGlobals, uBus, uDevFn, u32Address);
1065	pci_config_writel(pGlobals, uBus, uDevFn, u32Address, UINT32_C(0xffffffff));
1066	u32Size = pci_config_readl(pGlobals, uBus, uDevFn, u32Address);
1067	bool fIsPio = ((u8RessourceType & PCI_COMMAND_IOACCESS) == PCI_COMMAND_IOACCESS);
1068	/* Clear resource information depending on resource type. */
1069	if (fIsPio) /* I/O */
1070	u32Size &= ~(0x01);
1071	else /* MMIO */
1072	u32Size &= ~(0x0f);
1073
1074	/*
1075	* Invert all bits and add 1 to get size of the region.
1076	* (From PCI implementation note)
1077	*/
1078	if (fIsPio && (u32Size & UINT32_C(0xffff0000)) == 0)
1079	u32Size = (~(u32Size \| UINT32_C(0xffff0000))) + 1;
1080	else
1081	u32Size = (~u32Size) + 1;
1082
1083	Log2(("%s: Size of region %u for device %d on bus %d is %u\n", __FUNCTION__, i, uDevFn, uBus, u32Size));
1084
1085	if (u32Size)
1086	{
1087	if (fIsPio)
1088	paddr = &pGlobals->pci_bios_io_addr;
1089	else
1090	paddr = &pGlobals->pci_bios_mem_addr;
1091	uint32_t uNew = *paddr;
1092	uNew = (uNew + u32Size - 1) & ~(u32Size - 1);
1093	if (fIsPio)
1094	uNew &= UINT32_C(0xffff);
1095	/* Unconditionally exclude I/O-APIC/HPET/ROM. Pessimistic, but better than causing a mess. */
1096	if (!uNew \|\| (uNew <= UINT32_C(0xffffffff) && uNew + u32Size - 1 >= UINT32_C(0xfec00000)))
1097	{
1098	LogRel(("PCI: no space left for BAR%u of device %u/%u/%u (vendor=%#06x device=%#06x)\n",
1099	i, uBus, uDevFn >> 3, uDevFn & 7, vendor_id, device_id)); /** @todo make this a VM start failure later. */
1100	/* Undo the mapping mess caused by the size probing. */
1101	pci_config_writel(pGlobals, uBus, uDevFn, u32Address, UINT32_C(0));
1102	}
1103	else
1104	{
1105	Log(("%s: Start address of %s region %u is %#x\n", __FUNCTION__, (fIsPio ? "I/O" : "MMIO"), i, uNew));
1106	pci_set_io_region_addr(pGlobals, uBus, uDevFn, i, uNew);
1107	if (fIsPio)
1108	fActiveIORegion = true;
1109	else
1110	fActiveMemRegion = true;
1111	*paddr = uNew + u32Size;
1112	Log2(("%s: New address is %#x\n", __FUNCTION__, *paddr));
1113	}
1114	}
1115	}
1116
1117	/* Update the command word appropriately. */
1118	pci_config_writeb(pGlobals, uBus, uDevFn, PCI_COMMAND,
1119	pci_config_readb(pGlobals, uBus, uDevFn, PCI_COMMAND)
1120	\| (fActiveMemRegion ? PCI_COMMAND_MEMACCESS : 0)
1121	\| (fActiveIORegion ? PCI_COMMAND_IOACCESS : 0));
1122
1123	break;
1124	}
1125	}
1126
1127	/* map the interrupt */
1128	pin = pci_config_readb(pGlobals, uBus, uDevFn, PCI_INTERRUPT_PIN);
1129	if (pin != 0)
1130	{
1131	uint8_t uBridgeDevFn = uDevFn;
1132	pin--;
1133
1134	/* We need to go up to the host bus to see which irq this device will assert there. */
1135	while (cBridgeDepth != 0)
1136	{
1137	/* Get the pin the device would assert on the bridge. */
1138	pin = ((uBridgeDevFn >> 3) + pin) & 3;
1139	uBridgeDevFn = paBridgePositions[cBridgeDepth];
1140	cBridgeDepth--;
1141	}
1142
1143	pin = pci_slot_get_pirq(uDevFn, pin);
1144	pic_irq = pci_irqs[pin];
1145	pci_config_writeb(pGlobals, uBus, uDevFn, PCI_INTERRUPT_LINE, pic_irq);
1146	}
1147	}
1148	}
1149
1150	#endif /* IN_RING3 */
1151
1152
1153	/* -=-=-=-=-=- I/O ports -=-=-=-=-=- */
1154
1155	/**
1156	* @callback_method_impl{FNIOMIOPORTOUT, PCI address}
1157	*/
1158	PDMBOTHCBDECL(int) pciIOPortAddressWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1159	{
1160	Log(("pciIOPortAddressWrite: Port=%#x u32=%#x cb=%d\n", Port, u32, cb));
1161	RT_NOREF2(Port, pvUser);
1162	if (cb == 4)
1163	{
1164	PPCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
1165	PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_WRITE);
1166	pThis->uConfigReg = u32 & ~3; /* Bits 0-1 are reserved and we silently clear them */
1167	PCI_UNLOCK(pDevIns);
1168	}
1169	/* else: 440FX does "pass through to the bus" for other writes, what ever that means.
1170	* Linux probes for cmd640 using byte writes/reads during ide init. We'll just ignore it. */
1171	return VINF_SUCCESS;
1172	}
1173
1174
1175	/**
1176	* @callback_method_impl{FNIOMIOPORTIN, PCI address}
1177	*/
1178	PDMBOTHCBDECL(int) pciIOPortAddressRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
1179	{
1180	RT_NOREF2(Port, pvUser);
1181	if (cb == 4)
1182	{
1183	PPCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
1184	PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_READ);
1185	*pu32 = pThis->uConfigReg;
1186	PCI_UNLOCK(pDevIns);
1187	Log(("pciIOPortAddressRead: Port=%#x cb=%d -> %#x\n", Port, cb, *pu32));
1188	return VINF_SUCCESS;
1189	}
1190	/* else: 440FX does "pass through to the bus" for other writes, what ever that means.
1191	* Linux probes for cmd640 using byte writes/reads during ide init. We'll just ignore it. */
1192	Log(("pciIOPortAddressRead: Port=%#x cb=%d VERR_IOM_IOPORT_UNUSED\n", Port, cb));
1193	return VERR_IOM_IOPORT_UNUSED;
1194	}
1195
1196
1197	/**
1198	* @callback_method_impl{FNIOMIOPORTOUT, PCI data}
1199	*/
1200	PDMBOTHCBDECL(int) pciIOPortDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1201	{
1202	Log(("pciIOPortDataWrite: Port=%#x u32=%#x cb=%d\n", Port, u32, cb));
1203	NOREF(pvUser);
1204	int rc = VINF_SUCCESS;
1205	if (!(Port % cb))
1206	{
1207	PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_WRITE);
1208	rc = pci_data_write(PDMINS_2_DATA(pDevIns, PPCIGLOBALS), Port, u32, cb);
1209	PCI_UNLOCK(pDevIns);
1210	}
1211	else
1212	AssertMsgFailed(("Write to port %#x u32=%#x cb=%d\n", Port, u32, cb));
1213	return rc;
1214	}
1215
1216
1217	/**
1218	* @callback_method_impl{FNIOMIOPORTIN, PCI data}
1219	*/
1220	PDMBOTHCBDECL(int) pciIOPortDataRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
1221	{
1222	NOREF(pvUser);
1223	if (!(Port % cb))
1224	{
1225	PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_READ);
1226	int rc = pci_data_read(PDMINS_2_DATA(pDevIns, PPCIGLOBALS), Port, cb, pu32);
1227	PCI_UNLOCK(pDevIns);
1228	Log(("pciIOPortDataRead: Port=%#x cb=%#x -> %#x (%Rrc)\n", Port, cb, *pu32, rc));
1229	return rc;
1230	}
1231	AssertMsgFailed(("Read from port %#x cb=%d\n", Port, cb));
1232	return VERR_IOM_IOPORT_UNUSED;
1233	}
1234
1235	#ifdef IN_RING3
1236
1237	/* -=-=-=-=-=- Saved state -=-=-=-=-=- */
1238
1239	/**
1240	* Common worker for pciR3SaveExec and pcibridgeR3SaveExec.
1241	*
1242	* @returns VBox status code.
1243	* @param pBus The bus to save.
1244	* @param pSSM The saved state handle.
1245	*/
1246	static int pciR3CommonSaveExec(PPCIBUS pBus, PSSMHANDLE pSSM)
1247	{
1248	/*
1249	* Iterate thru all the devices.
1250	*/
1251	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->devices); i++)
1252	{
1253	PPCIDEVICE pDev = pBus->devices[i];
1254	if (pDev)
1255	{
1256	SSMR3PutU32(pSSM, i);
1257	SSMR3PutMem(pSSM, pDev->config, sizeof(pDev->config));
1258
1259	int rc = SSMR3PutS32(pSSM, pDev->Int.s.uIrqPinState);
1260	if (RT_FAILURE(rc))
1261	return rc;
1262	}
1263	}
1264	return SSMR3PutU32(pSSM, UINT32_MAX); /* terminator */
1265	}
1266
1267
1268	/**
1269	* @callback_method_impl{FNSSMDEVSAVEEXEC}
1270	*/
1271	static DECLCALLBACK(int) pciR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
1272	{
1273	uint32_t i;
1274	PPCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
1275
1276	/*
1277	* Bus state data.
1278	*/
1279	SSMR3PutU32(pSSM, pThis->uConfigReg);
1280	SSMR3PutBool(pSSM, pThis->fUseIoApic);
1281
1282	/*
1283	* Save IRQ states.
1284	*/
1285	for (i = 0; i < PCI_IRQ_PINS; i++)
1286	SSMR3PutU32(pSSM, pThis->pci_irq_levels[i]);
1287	for (i = 0; i < PCI_APIC_IRQ_PINS; i++)
1288	SSMR3PutU32(pSSM, pThis->pci_apic_irq_levels[i]);
1289
1290	SSMR3PutU32(pSSM, pThis->acpi_irq_level);
1291	SSMR3PutS32(pSSM, pThis->acpi_irq);
1292
1293	SSMR3PutU32(pSSM, UINT32_MAX); /* separator */
1294
1295	/*
1296	* Join paths with pcibridgeR3SaveExec.
1297	*/
1298	return pciR3CommonSaveExec(&pThis->PciBus, pSSM);
1299	}
1300
1301
1302	/**
1303	* Common routine for restoring the config registers of a PCI device.
1304	*
1305	* @param pDev The PCI device.
1306	* @param pbSrcConfig The configuration register values to be loaded.
1307	* @param fIsBridge Whether this is a bridge device or not.
1308	*/
1309	static void pciR3CommonRestoreConfig(PPCIDEVICE pDev, uint8_t const *pbSrcConfig, bool fIsBridge)
1310	{
1311	/*
1312	* This table defines the fields for normal devices and bridge devices, and
1313	* the order in which they need to be restored.
1314	*/
1315	static const struct PciField
1316	{
1317	uint8_t off;
1318	uint8_t cb;
1319	uint8_t fWritable;
1320	uint8_t fBridge;
1321	const char *pszName;
1322	} s_aFields[] =
1323	{
1324	/* off,cb,fW,fB, pszName */
1325	{ 0x00, 2, 0, 3, "VENDOR_ID" },
1326	{ 0x02, 2, 0, 3, "DEVICE_ID" },
1327	{ 0x06, 2, 1, 3, "STATUS" },
1328	{ 0x08, 1, 0, 3, "REVISION_ID" },
1329	{ 0x09, 1, 0, 3, "CLASS_PROG" },
1330	{ 0x0a, 1, 0, 3, "CLASS_SUB" },
1331	{ 0x0b, 1, 0, 3, "CLASS_BASE" },
1332	{ 0x0c, 1, 1, 3, "CACHE_LINE_SIZE" },
1333	{ 0x0d, 1, 1, 3, "LATENCY_TIMER" },
1334	{ 0x0e, 1, 0, 3, "HEADER_TYPE" },
1335	{ 0x0f, 1, 1, 3, "BIST" },
1336	{ 0x10, 4, 1, 3, "BASE_ADDRESS_0" },
1337	{ 0x14, 4, 1, 3, "BASE_ADDRESS_1" },
1338	{ 0x18, 4, 1, 1, "BASE_ADDRESS_2" },
1339	{ 0x18, 1, 1, 2, "PRIMARY_BUS" }, // fWritable = ??
1340	{ 0x19, 1, 1, 2, "SECONDARY_BUS" }, // fWritable = ??
1341	{ 0x1a, 1, 1, 2, "SUBORDINATE_BUS" }, // fWritable = ??
1342	{ 0x1b, 1, 1, 2, "SEC_LATENCY_TIMER" }, // fWritable = ??
1343	{ 0x1c, 4, 1, 1, "BASE_ADDRESS_3" },
1344	{ 0x1c, 1, 1, 2, "IO_BASE" }, // fWritable = ??
1345	{ 0x1d, 1, 1, 2, "IO_LIMIT" }, // fWritable = ??
1346	{ 0x1e, 2, 1, 2, "SEC_STATUS" }, // fWritable = ??
1347	{ 0x20, 4, 1, 1, "BASE_ADDRESS_4" },
1348	{ 0x20, 2, 1, 2, "MEMORY_BASE" }, // fWritable = ??
1349	{ 0x22, 2, 1, 2, "MEMORY_LIMIT" }, // fWritable = ??
1350	{ 0x24, 4, 1, 1, "BASE_ADDRESS_5" },
1351	{ 0x24, 2, 1, 2, "PREF_MEMORY_BASE" }, // fWritable = ??
1352	{ 0x26, 2, 1, 2, "PREF_MEMORY_LIMIT" }, // fWritable = ??
1353	{ 0x28, 4, 1, 1, "CARDBUS_CIS" }, // fWritable = ??
1354	{ 0x28, 4, 1, 2, "PREF_BASE_UPPER32" }, // fWritable = ??
1355	{ 0x2c, 2, 0, 1, "SUBSYSTEM_VENDOR_ID" },// fWritable = !?
1356	{ 0x2c, 4, 1, 2, "PREF_LIMIT_UPPER32" },// fWritable = ??
1357	{ 0x2e, 2, 0, 1, "SUBSYSTEM_ID" }, // fWritable = !?
1358	{ 0x30, 4, 1, 1, "ROM_ADDRESS" }, // fWritable = ?!
1359	{ 0x30, 2, 1, 2, "IO_BASE_UPPER16" }, // fWritable = ?!
1360	{ 0x32, 2, 1, 2, "IO_LIMIT_UPPER16" }, // fWritable = ?!
1361	{ 0x34, 4, 0, 3, "CAPABILITY_LIST" }, // fWritable = !? cb=!?
1362	{ 0x38, 4, 1, 1, "RESERVED_38" }, // ???
1363	{ 0x38, 4, 1, 2, "ROM_ADDRESS_BR" }, // fWritable = !? cb=!? fBridge=!?
1364	{ 0x3c, 1, 1, 3, "INTERRUPT_LINE" }, // fBridge=??
1365	{ 0x3d, 1, 0, 3, "INTERRUPT_PIN" }, // fBridge=??
1366	{ 0x3e, 1, 0, 1, "MIN_GNT" },
1367	{ 0x3e, 2, 1, 2, "BRIDGE_CONTROL" }, // fWritable = !?
1368	{ 0x3f, 1, 0, 1, "MAX_LAT" },
1369	/* The COMMAND register must come last as it requires the ADDRESS
1370	registers to be restored before we pretent to change it from 0 to
1371	whatever value the guest assigned it. */
1372	{ 0x04, 2, 1, 3, "COMMAND" },
1373	};
1374
1375	#ifdef RT_STRICT
1376	/* Check that we've got full register coverage. */
1377	uint32_t bmDevice[0x40 / 32];
1378	uint32_t bmBridge[0x40 / 32];
1379	RT_ZERO(bmDevice);
1380	RT_ZERO(bmBridge);
1381	for (uint32_t i = 0; i < RT_ELEMENTS(s_aFields); i++)
1382	{
1383	uint8_t off = s_aFields[i].off;
1384	uint8_t cb = s_aFields[i].cb;
1385	uint8_t f = s_aFields[i].fBridge;
1386	while (cb-- > 0)
1387	{
1388	if (f & 1) AssertMsg(!ASMBitTest(bmDevice, off), ("%#x\n", off));
1389	if (f & 2) AssertMsg(!ASMBitTest(bmBridge, off), ("%#x\n", off));
1390	if (f & 1) ASMBitSet(bmDevice, off);
1391	if (f & 2) ASMBitSet(bmBridge, off);
1392	off++;
1393	}
1394	}
1395	for (uint32_t off = 0; off < 0x40; off++)
1396	{
1397	AssertMsg(ASMBitTest(bmDevice, off), ("%#x\n", off));
1398	AssertMsg(ASMBitTest(bmBridge, off), ("%#x\n", off));
1399	}
1400	#endif
1401
1402	/*
1403	* Loop thru the fields covering the 64 bytes of standard registers.
1404	*/
1405	uint8_t const fBridge = fIsBridge ? 2 : 1;
1406	uint8_t *pbDstConfig = &pDev->config[0];
1407	for (uint32_t i = 0; i < RT_ELEMENTS(s_aFields); i++)
1408	if (s_aFields[i].fBridge & fBridge)
1409	{
1410	uint8_t const off = s_aFields[i].off;
1411	uint8_t const cb = s_aFields[i].cb;
1412	uint32_t u32Src;
1413	uint32_t u32Dst;
1414	switch (cb)
1415	{
1416	case 1:
1417	u32Src = pbSrcConfig[off];
1418	u32Dst = pbDstConfig[off];
1419	break;
1420	case 2:
1421	u32Src = (uint16_t const )&pbSrcConfig[off];
1422	u32Dst = (uint16_t const )&pbDstConfig[off];
1423	break;
1424	case 4:
1425	u32Src = (uint32_t const )&pbSrcConfig[off];
1426	u32Dst = (uint32_t const )&pbDstConfig[off];
1427	break;
1428	default:
1429	AssertFailed();
1430	continue;
1431	}
1432
1433	if ( u32Src != u32Dst
1434	\|\| off == VBOX_PCI_COMMAND)
1435	{
1436	if (u32Src != u32Dst)
1437	{
1438	if (!s_aFields[i].fWritable)
1439	LogRel(("PCI: %8s/%u: %2u-bit field %s: %x -> %x - !READ ONLY!\n",
1440	pDev->name, pDev->pDevIns->iInstance, cb*8, s_aFields[i].pszName, u32Dst, u32Src));
1441	else
1442	LogRel(("PCI: %8s/%u: %2u-bit field %s: %x -> %x\n",
1443	pDev->name, pDev->pDevIns->iInstance, cb*8, s_aFields[i].pszName, u32Dst, u32Src));
1444	}
1445	if (off == VBOX_PCI_COMMAND)
1446	PCIDevSetCommand(pDev, 0); /* For remapping, see pciR3CommonLoadExec. */
1447	pDev->Int.s.pfnConfigWrite(pDev, off, u32Src, cb);
1448	}
1449	}
1450
1451	/*
1452	* The device dependent registers.
1453	*
1454	* We will not use ConfigWrite here as we have no clue about the size
1455	* of the registers, so the device is responsible for correctly
1456	* restoring functionality governed by these registers.
1457	*/
1458	for (uint32_t off = 0x40; off < sizeof(pDev->config); off++)
1459	if (pbDstConfig[off] != pbSrcConfig[off])
1460	{
1461	LogRel(("PCI: %8s/%u: register %02x: %02x -> %02x\n",
1462	pDev->name, pDev->pDevIns->iInstance, off, pbDstConfig[off], pbSrcConfig[off])); /** @todo make this Log() later. */
1463	pbDstConfig[off] = pbSrcConfig[off];
1464	}
1465	}
1466
1467
1468	/**
1469	* Common worker for pciR3LoadExec and pcibridgeR3LoadExec.
1470	*
1471	* @returns VBox status code.
1472	* @param pBus The bus which data is being loaded.
1473	* @param pSSM The saved state handle.
1474	* @param uVersion The data version.
1475	* @param uPass The pass.
1476	*/
1477	static DECLCALLBACK(int) pciR3CommonLoadExec(PPCIBUS pBus, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1478	{
1479	uint32_t u32;
1480	uint32_t i;
1481	int rc;
1482
1483	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
1484
1485	/*
1486	* Iterate thru all the devices and write 0 to the COMMAND register so
1487	* that all the memory is unmapped before we start restoring the saved
1488	* mapping locations.
1489	*
1490	* The register value is restored afterwards so we can do proper
1491	* LogRels in pciR3CommonRestoreConfig.
1492	*/
1493	for (i = 0; i < RT_ELEMENTS(pBus->devices); i++)
1494	{
1495	PPCIDEVICE pDev = pBus->devices[i];
1496	if (pDev)
1497	{
1498	uint16_t u16 = PCIDevGetCommand(pDev);
1499	pDev->Int.s.pfnConfigWrite(pDev, VBOX_PCI_COMMAND, 0, 2);
1500	PCIDevSetCommand(pDev, u16);
1501	Assert(PCIDevGetCommand(pDev) == u16);
1502	}
1503	}
1504
1505	/*
1506	* Iterate all the devices.
1507	*/
1508	for (i = 0;; i++)
1509	{
1510	PCIDEVICE DevTmp;
1511	PPCIDEVICE pDev;
1512
1513	/* index / terminator */
1514	rc = SSMR3GetU32(pSSM, &u32);
1515	if (RT_FAILURE(rc))
1516	return rc;
1517	if (u32 == (uint32_t)~0)
1518	break;
1519	if ( u32 >= RT_ELEMENTS(pBus->devices)
1520	\|\| u32 < i)
1521	{
1522	AssertMsgFailed(("u32=%#x i=%#x\n", u32, i));
1523	return rc;
1524	}
1525
1526	/* skip forward to the device checking that no new devices are present. */
1527	for (; i < u32; i++)
1528	{
1529	if (pBus->devices[i])
1530	{
1531	LogRel(("PCI: New device in slot %#x, %s (vendor=%#06x device=%#06x)\n", i, pBus->devices[i]->name,
1532	PCIDevGetVendorId(pBus->devices[i]), PCIDevGetDeviceId(pBus->devices[i])));
1533	if (SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT)
1534	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("New device in slot %#x, %s (vendor=%#06x device=%#06x)"),
1535	i, pBus->devices[i]->name, PCIDevGetVendorId(pBus->devices[i]), PCIDevGetDeviceId(pBus->devices[i]));
1536	}
1537	}
1538
1539	/* get the data */
1540	DevTmp.Int.s.uIrqPinState = ~0; /* Invalid value in case we have an older saved state to force a state change in pciSetIrq. */
1541	SSMR3GetMem(pSSM, DevTmp.config, sizeof(DevTmp.config));
1542	if (uVersion < 3)
1543	{
1544	int32_t i32Temp;
1545	/* Irq value not needed anymore. */
1546	rc = SSMR3GetS32(pSSM, &i32Temp);
1547	if (RT_FAILURE(rc))
1548	return rc;
1549	}
1550	else
1551	{
1552	rc = SSMR3GetS32(pSSM, &DevTmp.Int.s.uIrqPinState);
1553	if (RT_FAILURE(rc))
1554	return rc;
1555	}
1556
1557	/* check that it's still around. */
1558	pDev = pBus->devices[i];
1559	if (!pDev)
1560	{
1561	LogRel(("PCI: Device in slot %#x has been removed! vendor=%#06x device=%#06x\n", i,
1562	PCIDevGetVendorId(&DevTmp), PCIDevGetDeviceId(&DevTmp)));
1563	if (SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT)
1564	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Device in slot %#x has been removed! vendor=%#06x device=%#06x"),
1565	i, PCIDevGetVendorId(&DevTmp), PCIDevGetDeviceId(&DevTmp));
1566	continue;
1567	}
1568
1569	/* match the vendor id assuming that this will never be changed. */
1570	if ( DevTmp.config[0] != pDev->config[0]
1571	\|\| DevTmp.config[1] != pDev->config[1])
1572	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Device in slot %#x (%s) vendor id mismatch! saved=%.4Rhxs current=%.4Rhxs"),
1573	i, pDev->name, DevTmp.config, pDev->config);
1574
1575	/* commit the loaded device config. */
1576	pciR3CommonRestoreConfig(pDev, &DevTmp.config[0], false ); /** @todo fix bridge fun! */
1577
1578	pDev->Int.s.uIrqPinState = DevTmp.Int.s.uIrqPinState;
1579	}
1580
1581	return VINF_SUCCESS;
1582	}
1583
1584
1585	/**
1586	* @callback_method_impl{FNSSMDEVLOADEXEC}
1587	*/
1588	static DECLCALLBACK(int) pciR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1589	{
1590	PPCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
1591	PPCIBUS pBus = &pThis->PciBus;
1592	uint32_t u32;
1593	int rc;
1594
1595	/*
1596	* Check the version.
1597	*/
1598	if (uVersion > VBOX_PCI_SAVED_STATE_VERSION)
1599	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1600	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
1601
1602	/*
1603	* Bus state data.
1604	*/
1605	SSMR3GetU32(pSSM, &pThis->uConfigReg);
1606	if (uVersion > 1)
1607	SSMR3GetBool(pSSM, &pThis->fUseIoApic);
1608
1609	/* Load IRQ states. */
1610	if (uVersion > 2)
1611	{
1612	for (uint8_t i = 0; i < PCI_IRQ_PINS; i++)
1613	SSMR3GetU32(pSSM, (uint32_t *)&pThis->pci_irq_levels[i]);
1614	for (uint8_t i = 0; i < PCI_APIC_IRQ_PINS; i++)
1615	SSMR3GetU32(pSSM, (uint32_t *)&pThis->pci_apic_irq_levels[i]);
1616
1617	SSMR3GetU32(pSSM, &pThis->acpi_irq_level);
1618	SSMR3GetS32(pSSM, &pThis->acpi_irq);
1619	}
1620
1621	/* separator */
1622	rc = SSMR3GetU32(pSSM, &u32);
1623	if (RT_FAILURE(rc))
1624	return rc;
1625	if (u32 != (uint32_t)~0)
1626	AssertMsgFailedReturn(("u32=%#x\n", u32), rc);
1627
1628	/*
1629	* The devices.
1630	*/
1631	return pciR3CommonLoadExec(pBus, pSSM, uVersion, uPass);
1632	}
1633
1634
1635	/* -=-=-=-=-=- PCI Bus Interface Methods (PDMPCIBUSREG) -=-=-=-=-=- */
1636
1637	/**
1638	* Registers the device with the specified PCI bus.
1639	*
1640	* @returns VBox status code.
1641	* @param pBus The bus to register with.
1642	* @param iDev The PCI device ordinal.
1643	* @param pPciDev The PCI device structure.
1644	* @param pszName Pointer to device name (permanent, readonly). For debugging, not unique.
1645	*/
1646	static int pciR3RegisterDeviceInternal(PPCIBUS pBus, int iDev, PPCIDEVICE pPciDev, const char *pszName)
1647	{
1648	/*
1649	* Find device slot.
1650	*/
1651	if (iDev < 0)
1652	{
1653	/*
1654	* Special check for the IDE controller which is our function 1 device
1655	* before searching.
1656	*/
1657	if ( !strcmp(pszName, "piix3ide")
1658	&& !pBus->devices[9])
1659	iDev = 9;
1660	/* LPC bus expected to be there by some guests, better make an additional argument to PDM
1661	device helpers, but requires significant rewrite */
1662	else if (!strcmp(pszName, "lpc")
1663	&& !pBus->devices[0xf8])
1664	iDev = 0xf8;
1665	else
1666	{
1667	Assert(!(pBus->iDevSearch % 8));
1668	for (iDev = pBus->iDevSearch; iDev < (int)RT_ELEMENTS(pBus->devices)-7; iDev += 8)
1669	if ( !pBus->devices[iDev]
1670	&& !pBus->devices[iDev + 1]
1671	&& !pBus->devices[iDev + 2]
1672	&& !pBus->devices[iDev + 3]
1673	&& !pBus->devices[iDev + 4]
1674	&& !pBus->devices[iDev + 5]
1675	&& !pBus->devices[iDev + 6]
1676	&& !pBus->devices[iDev + 7])
1677	break;
1678	if (iDev >= (int)RT_ELEMENTS(pBus->devices))
1679	{
1680	AssertMsgFailed(("Couldn't find free spot!\n"));
1681	return VERR_PDM_TOO_PCI_MANY_DEVICES;
1682	}
1683	}
1684	pciDevClearRequestedDevfunc(pPciDev);
1685	}
1686	else
1687	{
1688	/*
1689	* An explicit request.
1690	*
1691	* If the slot is occupied we'll have to relocate the device
1692	* currently occupying it first. This can only be done if the
1693	* existing device wasn't explicitly assigned. Also we limit
1694	* ourselves to function 0 devices.
1695	*
1696	* If you start setting devices + function in the
1697	* config, do it for all pci devices!
1698	*/
1699	//AssertReleaseMsg(iDev > 8 \|\| pBus->iBus != 0, ("iDev=%d pszName=%s\n", iDev, pszName));
1700	if (pBus->devices[iDev])
1701	{
1702	int iDevRel;
1703	AssertReleaseMsg(!(iDev % 8), ("PCI Configuration Conflict! iDev=%d pszName=%s clashes with %s\n",
1704	iDev, pszName, pBus->devices[iDev]->name));
1705	if ( pciDevIsRequestedDevfunc(pBus->devices[iDev])
1706	\|\| (pBus->devices[iDev + 1] && pciDevIsRequestedDevfunc(pBus->devices[iDev + 1]))
1707	\|\| (pBus->devices[iDev + 2] && pciDevIsRequestedDevfunc(pBus->devices[iDev + 2]))
1708	\|\| (pBus->devices[iDev + 3] && pciDevIsRequestedDevfunc(pBus->devices[iDev + 3]))
1709	\|\| (pBus->devices[iDev + 4] && pciDevIsRequestedDevfunc(pBus->devices[iDev + 4]))
1710	\|\| (pBus->devices[iDev + 5] && pciDevIsRequestedDevfunc(pBus->devices[iDev + 5]))
1711	\|\| (pBus->devices[iDev + 6] && pciDevIsRequestedDevfunc(pBus->devices[iDev + 6]))
1712	\|\| (pBus->devices[iDev + 7] && pciDevIsRequestedDevfunc(pBus->devices[iDev + 7])))
1713	{
1714	AssertReleaseMsgFailed(("Configuration error:'%s' and '%s' are both configured as device %d\n",
1715	pszName, pBus->devices[iDev]->name, iDev));
1716	return VERR_INTERNAL_ERROR;
1717	}
1718
1719	/* Find free slot for the device(s) we're moving and move them. */
1720	for (iDevRel = pBus->iDevSearch; iDevRel < (int)RT_ELEMENTS(pBus->devices)-7; iDevRel += 8)
1721	{
1722	if ( !pBus->devices[iDevRel]
1723	&& !pBus->devices[iDevRel + 1]
1724	&& !pBus->devices[iDevRel + 2]
1725	&& !pBus->devices[iDevRel + 3]
1726	&& !pBus->devices[iDevRel + 4]
1727	&& !pBus->devices[iDevRel + 5]
1728	&& !pBus->devices[iDevRel + 6]
1729	&& !pBus->devices[iDevRel + 7])
1730	{
1731	int i = 0;
1732	for (i = 0; i < 8; i++)
1733	{
1734	if (!pBus->devices[iDev + i])
1735	continue;
1736	Log(("PCI: relocating '%s' from slot %#x to %#x\n", pBus->devices[iDev + i]->name, iDev + i, iDevRel + i));
1737	pBus->devices[iDevRel + i] = pBus->devices[iDev + i];
1738	pBus->devices[iDevRel + i]->devfn = iDevRel + i;
1739	pBus->devices[iDev + i] = NULL;
1740	}
1741	}
1742	}
1743	if (pBus->devices[iDev])
1744	{
1745	AssertMsgFailed(("Couldn't find free spot!\n"));
1746	return VERR_PDM_TOO_PCI_MANY_DEVICES;
1747	}
1748	} /* if conflict */
1749	pciDevSetRequestedDevfunc(pPciDev);
1750	}
1751
1752	Assert(!pBus->devices[iDev]);
1753	pPciDev->devfn = iDev;
1754	pPciDev->name = pszName;
1755	pPciDev->Int.s.pBusR3 = pBus;
1756	pPciDev->Int.s.pBusR0 = MMHyperR3ToR0(PDMDevHlpGetVM(pBus->CTX_SUFF(pDevIns)), pBus);
1757	pPciDev->Int.s.pBusRC = MMHyperR3ToRC(PDMDevHlpGetVM(pBus->CTX_SUFF(pDevIns)), pBus);
1758	pPciDev->Int.s.pfnConfigRead = pci_default_read_config;
1759	pPciDev->Int.s.pfnConfigWrite = pci_default_write_config;
1760	pBus->devices[iDev] = pPciDev;
1761	if (pciDevIsPci2PciBridge(pPciDev))
1762	{
1763	AssertMsg(pBus->cBridges < RT_ELEMENTS(pBus->devices), ("Number of bridges exceeds the number of possible devices on the bus\n"));
1764	AssertMsg(pPciDev->Int.s.pfnBridgeConfigRead && pPciDev->Int.s.pfnBridgeConfigWrite,
1765	("device is a bridge but does not implement read/write functions\n"));
1766	pBus->papBridgesR3[pBus->cBridges] = pPciDev;
1767	pBus->cBridges++;
1768	}
1769
1770	Log(("PCI: Registered device %d function %d (%#x) '%s'.\n",
1771	iDev >> 3, iDev & 7, 0x80000000 \| (iDev << 8), pszName));
1772
1773	return VINF_SUCCESS;
1774	}
1775
1776
1777	/**
1778	* @interface_method_impl{PDMPCIBUSREG,pfnRegisterR3}
1779	*/
1780	static DECLCALLBACK(int) pciR3Register(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, const char *pszName, int iDev)
1781	{
1782	PPCIBUS pBus = DEVINS_2_PCIBUS(pDevIns);
1783
1784	/*
1785	* Check input.
1786	*/
1787	if ( !pszName
1788	\|\| !pPciDev
1789	\|\| iDev >= (int)RT_ELEMENTS(pBus->devices)
1790	\|\| (iDev >= 0 && iDev <= 8))
1791	{
1792	AssertMsgFailed(("Invalid argument! pszName=%s pPciDev=%p iDev=%d\n", pszName, pPciDev, iDev));
1793	return VERR_INVALID_PARAMETER;
1794	}
1795
1796	/*
1797	* Register the device.
1798	*/
1799	return pciR3RegisterDeviceInternal(pBus, iDev, pPciDev, pszName);
1800	}
1801
1802
1803	/**
1804	* @interface_method_impl{PDMPCIBUSREG,pfnIORegionRegisterR3}
1805	*/
1806	static DECLCALLBACK(int) pciR3CommonIORegionRegister(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iRegion, RTGCPHYS cbRegion,
1807	PCIADDRESSSPACE enmType, PFNPCIIOREGIONMAP pfnCallback)
1808	{
1809	NOREF(pDevIns);
1810
1811	/*
1812	* Validate.
1813	*/
1814	AssertMsgReturn( enmType == PCI_ADDRESS_SPACE_MEM
1815	\|\| enmType == PCI_ADDRESS_SPACE_IO
1816	\|\| enmType == PCI_ADDRESS_SPACE_MEM_PREFETCH,
1817	("Invalid enmType=%#x? Or was this a bitmask after all...\n", enmType),
1818	VERR_INVALID_PARAMETER);
1819	AssertMsgReturn((unsigned)iRegion < PCI_NUM_REGIONS,
1820	("Invalid iRegion=%d PCI_NUM_REGIONS=%d\n", iRegion, PCI_NUM_REGIONS),
1821	VERR_INVALID_PARAMETER);
1822	int iLastSet = ASMBitLastSetU64(cbRegion);
1823	AssertMsgReturn( iLastSet != 0
1824	&& RT_BIT_64(iLastSet - 1) == cbRegion,
1825	("Invalid cbRegion=%RGp iLastSet=%#x (not a power of 2 or 0)\n", cbRegion, iLastSet),
1826	VERR_INVALID_PARAMETER);
1827
1828	/*
1829	* Register the I/O region.
1830	*/
1831	PPCIIOREGION pRegion = &pPciDev->Int.s.aIORegions[iRegion];
1832	pRegion->addr = ~0U;
1833	pRegion->size = cbRegion;
1834	pRegion->type = enmType;
1835	pRegion->map_func = pfnCallback;
1836
1837	/* Set type in the config space. */
1838	AssertCompile(PCI_ADDRESS_SPACE_MEM == 0);
1839	AssertCompile(PCI_ADDRESS_SPACE_IO == 1);
1840	AssertCompile(PCI_ADDRESS_SPACE_MEM_PREFETCH == RT_BIT_32(3));
1841	PCIDevSetDWord(pPciDev, 0x10 + iRegion * 4, enmType);
1842
1843	return VINF_SUCCESS;
1844	}
1845
1846
1847	/**
1848	* @interface_method_impl{PDMPCIBUSREG,pfnSetConfigCallbacksR3}
1849	*/
1850	static DECLCALLBACK(void)
1851	pciR3CommonSetConfigCallbacks(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PFNPCICONFIGREAD pfnRead, PPFNPCICONFIGREAD ppfnReadOld,
1852	PFNPCICONFIGWRITE pfnWrite, PPFNPCICONFIGWRITE ppfnWriteOld)
1853	{
1854	NOREF(pDevIns);
1855
1856	if (ppfnReadOld)
1857	*ppfnReadOld = pPciDev->Int.s.pfnConfigRead;
1858	pPciDev->Int.s.pfnConfigRead = pfnRead;
1859
1860	if (ppfnWriteOld)
1861	*ppfnWriteOld = pPciDev->Int.s.pfnConfigWrite;
1862	pPciDev->Int.s.pfnConfigWrite = pfnWrite;
1863	}
1864
1865
1866	/**
1867	* @interface_method_impl{PDMPCIBUSREG,pfnFakePCIBIOSR3}
1868	*/
1869	static DECLCALLBACK(int) pciR3FakePCIBIOS(PPDMDEVINS pDevIns)
1870	{
1871	unsigned i;
1872	uint8_t elcr[2] = {0, 0};
1873	PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
1874	PVM pVM = PDMDevHlpGetVM(pDevIns); Assert(pVM);
1875	PVMCPU pVCpu = PDMDevHlpGetVMCPU(pDevIns); Assert(pVM);
1876	uint32_t const cbBelow4GB = MMR3PhysGetRamSizeBelow4GB(pVM);
1877	uint64_t const cbAbove4GB = MMR3PhysGetRamSizeAbove4GB(pVM);
1878	RT_NOREF(cbBelow4GB, cbAbove4GB);
1879
1880	/*
1881	* Set the start addresses.
1882	*/
1883	pGlobals->pci_bios_io_addr = 0xd000;
1884	pGlobals->pci_bios_mem_addr = UINT32_C(0xf0000000);
1885	pGlobals->uBus = 0;
1886
1887	/*
1888	* Activate IRQ mappings.
1889	*/
1890	for (i = 0; i < 4; i++)
1891	{
1892	uint8_t irq = pci_irqs[i];
1893	/* Set to trigger level. */
1894	elcr[irq >> 3] \|= (1 << (irq & 7));
1895	/* Activate irq remapping in PIIX3. */
1896	pci_config_writeb(pGlobals, 0, pGlobals->PIIX3State.dev.devfn, 0x60 + i, irq);
1897	}
1898
1899	/* Tell to the PIC. */
1900	VBOXSTRICTRC rcStrict = IOMIOPortWrite(pVM, pVCpu, 0x4d0, elcr[0], sizeof(uint8_t));
1901	if (rcStrict == VINF_SUCCESS)
1902	rcStrict = IOMIOPortWrite(pVM, pVCpu, 0x4d1, elcr[1], sizeof(uint8_t));
1903	if (rcStrict != VINF_SUCCESS)
1904	{
1905	AssertMsgFailed(("Writing to PIC failed! rcStrict=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
1906	return RT_SUCCESS(rcStrict) ? VERR_INTERNAL_ERROR : VBOXSTRICTRC_VAL(rcStrict);
1907	}
1908
1909	/*
1910	* Init the devices.
1911	*/
1912	for (i = 0; i < 256; i++)
1913	{
1914	uint8_t aBridgePositions[256];
1915
1916	memset(aBridgePositions, 0, sizeof(aBridgePositions));
1917	Log2(("PCI: Initializing device %d (%#x)\n",
1918	i, 0x80000000 \| (i << 8)));
1919	pci_bios_init_device(pGlobals, 0, i, 0, aBridgePositions);
1920	}
1921
1922	return VINF_SUCCESS;
1923	}
1924
1925
1926	/* -=-=-=-=-=- Debug Info Handlers -=-=-=-=-=- */
1927
1928	/**
1929	* @callback_method_impl{FNDBGFHANDLERDEV}
1930	*/
1931	static DECLCALLBACK(void) pciR3IrqRouteInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
1932	{
1933	PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
1934	NOREF(pszArgs);
1935
1936	uint16_t router = pGlobals->PIIX3State.dev.devfn;
1937	pHlp->pfnPrintf(pHlp, "PCI interrupt router at: %02X:%02X:%X\n",
1938	router >> 8, (router >> 3) & 0x1f, router & 0x7);
1939
1940	for (int i = 0; i < 4; ++i)
1941	{
1942	uint8_t irq_map = pci_config_readb(pGlobals, 0, router, 0x60 + i);
1943	if (irq_map & 0x80)
1944	pHlp->pfnPrintf(pHlp, "PIRQ%c disabled\n", 'A' + i);
1945	else
1946	pHlp->pfnPrintf(pHlp, "PIRQ%c -> IRQ%d\n", 'A' + i, irq_map & 0xf);
1947	}
1948	}
1949
1950	/**
1951	* @callback_method_impl{FNDBGFHANDLERDEV}
1952	*/
1953	static DECLCALLBACK(void) pciR3IrqInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
1954	{
1955	PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
1956	NOREF(pszArgs);
1957
1958	pHlp->pfnPrintf(pHlp, "PCI I/O APIC IRQ levels:\n");
1959	for (int i = 0; i < PCI_APIC_IRQ_PINS; ++i)
1960	{
1961	pHlp->pfnPrintf(pHlp, " IRQ%02d: %u\n", 0x10 + i, pGlobals->pci_apic_irq_levels[i]);
1962	}
1963	}
1964
1965	/**
1966	* Outputs indent.
1967	*
1968	* @param pHlp Output helpers.
1969	* @param iIndent Indentation level.
1970	*/
1971	static void pciR3PrintIndent(PCDBGFINFOHLP pHlp, int iIndent)
1972	{
1973	while (iIndent-- > 0)
1974	pHlp->pfnPrintf(pHlp, " ");
1975	}
1976
1977	/**
1978	* Recursive worker for pciR3Info.
1979	*
1980	* @param pBus The bus to display.
1981	* @param pHlp Output helpers.
1982	* @param iIndent Indentation level.
1983	* @param fRegisters Whether to also display the PCI configuration registers
1984	* of each device on the bus.
1985	*/
1986	static void pciR3BusInfo(PPCIBUS pBus, PCDBGFINFOHLP pHlp, int iIndent, bool fRegisters)
1987	{
1988	for (uint32_t iDev = 0; iDev < RT_ELEMENTS(pBus->devices); iDev++)
1989	{
1990	PPCIDEVICE pPciDev = pBus->devices[iDev];
1991	if (pPciDev != NULL)
1992	{
1993	pciR3PrintIndent(pHlp, iIndent);
1994
1995	/*
1996	* For passthrough devices MSI/MSI-X mostly reflects the way interrupts delivered to the guest,
1997	* as host driver handles real devices interrupts.
1998	*/
1999	pHlp->pfnPrintf(pHlp, "%02x:%02x:%02x %s%s: %04x-%04x%s%s",
2000	pBus->iBus, (iDev >> 3) & 0xff, iDev & 0x7,
2001	pPciDev->name,
2002	pciDevIsPassthrough(pPciDev) ? " (PASSTHROUGH)" : "",
2003	PCIDevGetWord(pPciDev, VBOX_PCI_VENDOR_ID), PCIDevGetWord(pPciDev, VBOX_PCI_DEVICE_ID),
2004	pciDevIsMsiCapable(pPciDev) ? " MSI" : "",
2005	pciDevIsMsixCapable(pPciDev) ? " MSI-X" : ""
2006	);
2007	if (PCIDevGetByte(pPciDev, VBOX_PCI_INTERRUPT_PIN) != 0)
2008	{
2009	pHlp->pfnPrintf(pHlp, " IRQ%d", PCIDevGetByte(pPciDev, VBOX_PCI_INTERRUPT_LINE));
2010	pHlp->pfnPrintf(pHlp, " (INTA#->IRQ%d)", 0x10 + pci_slot_get_apic_pirq(iDev, 0));
2011	}
2012
2013	pHlp->pfnPrintf(pHlp, "\n");
2014
2015	uint16_t iCmd = PCIDevGetWord(pPciDev, VBOX_PCI_COMMAND);
2016	if ((iCmd & (VBOX_PCI_COMMAND_IO \| VBOX_PCI_COMMAND_MEMORY)) != 0)
2017	{
2018	for (int iRegion = 0; iRegion < PCI_NUM_REGIONS; iRegion++)
2019	{
2020	PCIIORegion* pRegion = &pPciDev->Int.s.aIORegions[iRegion];
2021	uint64_t iRegionSize = pRegion->size;
2022
2023	if (iRegionSize == 0)
2024	continue;
2025
2026	uint32_t u32Addr = PCIDevGetDWord(pPciDev, PCIDevGetRegionReg(iRegion));
2027	const char * pszDesc;
2028	char szDescBuf[128];
2029
2030	bool f64Bit = !!(pRegion->type & PCI_ADDRESS_SPACE_BAR64);
2031	if (pRegion->type & PCI_ADDRESS_SPACE_IO)
2032	{
2033	pszDesc = "IO";
2034	u32Addr &= ~0x3;
2035	}
2036	else
2037	{
2038	RTStrPrintf(szDescBuf, sizeof(szDescBuf), "MMIO%s%s",
2039	f64Bit ? "64" : "32",
2040	(pRegion->type & PCI_ADDRESS_SPACE_MEM_PREFETCH) ? " PREFETCH" : "");
2041	pszDesc = szDescBuf;
2042	u32Addr &= ~0xf;
2043	}
2044
2045	pciR3PrintIndent(pHlp, iIndent + 2);
2046	pHlp->pfnPrintf(pHlp, "%s region #%d: %x..%x\n",
2047	pszDesc, iRegion, u32Addr, u32Addr+iRegionSize);
2048	if (f64Bit)
2049	iRegion++;
2050	}
2051	}
2052
2053	pciR3PrintIndent(pHlp, iIndent + 2);
2054	uint16_t iStatus = PCIDevGetWord(pPciDev, VBOX_PCI_STATUS);
2055	pHlp->pfnPrintf(pHlp, "Command: %.Rhxs, Status: %.Rhxs\n",
2056	sizeof(uint16_t), &iCmd, sizeof(uint16_t), &iStatus);
2057	pciR3PrintIndent(pHlp, iIndent + 2);
2058	pHlp->pfnPrintf(pHlp, "Bus master: %s\n",
2059	iCmd & VBOX_PCI_COMMAND_MASTER ? "Yes" : "No");
2060
2061	if (fRegisters)
2062	{
2063	pciR3PrintIndent(pHlp, iIndent + 2);
2064	pHlp->pfnPrintf(pHlp, "PCI registers:\n");
2065	for (int iReg = 0; iReg < 0x100; )
2066	{
2067	int iPerLine = 0x10;
2068	Assert (0x100 % iPerLine == 0);
2069	pciR3PrintIndent(pHlp, iIndent + 3);
2070
2071	while (iPerLine-- > 0)
2072	{
2073	pHlp->pfnPrintf(pHlp, "%02x ", PCIDevGetByte(pPciDev, iReg++));
2074	}
2075	pHlp->pfnPrintf(pHlp, "\n");
2076	}
2077	}
2078	}
2079	}
2080
2081	if (pBus->cBridges > 0)
2082	{
2083	pciR3PrintIndent(pHlp, iIndent);
2084	pHlp->pfnPrintf(pHlp, "Registered %d bridges, subordinate buses info follows\n", pBus->cBridges);
2085	for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
2086	{
2087	PPCIBUS pBusSub = PDMINS_2_DATA(pBus->papBridgesR3[iBridge]->pDevIns, PPCIBUS);
2088	pciR3BusInfo(pBusSub, pHlp, iIndent + 1, fRegisters);
2089	}
2090	}
2091	}
2092
2093
2094	/**
2095	* @callback_method_impl{FNDBGFHANDLERDEV}
2096	*/
2097	static DECLCALLBACK(void) pciR3Info(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
2098	{
2099	PPCIBUS pBus = DEVINS_2_PCIBUS(pDevIns);
2100
2101	if (pszArgs == NULL \|\| !*pszArgs \|\| !strcmp(pszArgs, "basic"))
2102	pciR3BusInfo(pBus, pHlp, 0, false);
2103	else if (!strcmp(pszArgs, "verbose"))
2104	pciR3BusInfo(pBus, pHlp, 0, true);
2105	else
2106	pHlp->pfnPrintf(pHlp, "Invalid argument. Recognized arguments are 'basic', 'verbose'.\n");
2107	}
2108
2109
2110	/* -=-=-=-=-=- PDMDEVREG -=-=-=-=-=- */
2111
2112	/**
2113	* @interface_method_impl{PDMDEVREG,pfnRelocate}
2114	*/
2115	static DECLCALLBACK(void) pciR3Relocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
2116	{
2117	PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
2118	PPCIBUS pBus = &pGlobals->PciBus;
2119	pGlobals->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2120
2121	pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
2122	pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2123
2124	/* Relocate RC pointers for the attached pci devices. */
2125	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->devices); i++)
2126	{
2127	if (pBus->devices[i])
2128	pBus->devices[i]->Int.s.pBusRC += offDelta;
2129	}
2130	}
2131
2132
2133	/**
2134	* @interface_method_impl{PDMDEVREG,pfnReset}
2135	*/
2136	static DECLCALLBACK(void) pciR3Reset(PPDMDEVINS pDevIns)
2137	{
2138	pciR3FakePCIBIOS(pDevIns);
2139	}
2140
2141
2142	/**
2143	* @interface_method_impl{PDMDEVREG,pfnConstruct}
2144	*/
2145	static DECLCALLBACK(int) pciR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
2146	{
2147	RT_NOREF1(iInstance);
2148	Assert(iInstance == 0);
2149	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
2150
2151	/*
2152	* Validate and read configuration.
2153	*/
2154	if (!CFGMR3AreValuesValid(pCfg, "IOAPIC\0" "GCEnabled\0" "R0Enabled\0"))
2155	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
2156
2157	/* query whether we got an IOAPIC */
2158	bool fUseIoApic;
2159	int rc = CFGMR3QueryBoolDef(pCfg, "IOAPIC", &fUseIoApic, false);
2160	if (RT_FAILURE(rc))
2161	return PDMDEV_SET_ERROR(pDevIns, rc,
2162	N_("Configuration error: Failed to query boolean value \"IOAPIC\""));
2163
2164	/* check if RC code is enabled. */
2165	bool fGCEnabled;
2166	rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
2167	if (RT_FAILURE(rc))
2168	return PDMDEV_SET_ERROR(pDevIns, rc,
2169	N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
2170
2171	/* check if R0 code is enabled. */
2172	bool fR0Enabled;
2173	rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
2174	if (RT_FAILURE(rc))
2175	return PDMDEV_SET_ERROR(pDevIns, rc,
2176	N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
2177	Log(("PCI: fUseIoApic=%RTbool fGCEnabled=%RTbool fR0Enabled=%RTbool\n", fUseIoApic, fGCEnabled, fR0Enabled));
2178
2179	/*
2180	* Init data and register the PCI bus.
2181	*/
2182	PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
2183	pGlobals->pci_bios_io_addr = 0xc000;
2184	pGlobals->pci_bios_mem_addr = 0xf0000000;
2185	memset((void *)&pGlobals->pci_irq_levels, 0, sizeof(pGlobals->pci_irq_levels));
2186	pGlobals->fUseIoApic = fUseIoApic;
2187	memset((void *)&pGlobals->pci_apic_irq_levels, 0, sizeof(pGlobals->pci_apic_irq_levels));
2188
2189	pGlobals->pDevInsR3 = pDevIns;
2190	pGlobals->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2191	pGlobals->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2192
2193	pGlobals->PciBus.pDevInsR3 = pDevIns;
2194	pGlobals->PciBus.pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2195	pGlobals->PciBus.pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2196	pGlobals->PciBus.papBridgesR3 = (PPCIDEVICE *)PDMDevHlpMMHeapAllocZ(pDevIns, sizeof(PPCIDEVICE)
2197	* RT_ELEMENTS(pGlobals->PciBus.devices));
2198
2199	PDMPCIBUSREG PciBusReg;
2200	PPCIBUS pBus = &pGlobals->PciBus;
2201	PciBusReg.u32Version = PDM_PCIBUSREG_VERSION;
2202	PciBusReg.pfnRegisterR3 = pciR3Register;
2203	PciBusReg.pfnRegisterMsiR3 = NULL;
2204	PciBusReg.pfnIORegionRegisterR3 = pciR3CommonIORegionRegister;
2205	PciBusReg.pfnSetConfigCallbacksR3 = pciR3CommonSetConfigCallbacks;
2206	PciBusReg.pfnSetIrqR3 = pciSetIrq;
2207	PciBusReg.pfnFakePCIBIOSR3 = pciR3FakePCIBIOS;
2208	PciBusReg.pszSetIrqRC = fGCEnabled ? "pciSetIrq" : NULL;
2209	PciBusReg.pszSetIrqR0 = fR0Enabled ? "pciSetIrq" : NULL;
2210	rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBus->pPciHlpR3);
2211	if (RT_FAILURE(rc))
2212	return PDMDEV_SET_ERROR(pDevIns, rc,
2213	N_("Failed to register ourselves as a PCI Bus"));
2214	if (pBus->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
2215	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
2216	N_("PCI helper version mismatch; got %#x expected %#x"),
2217	pBus->pPciHlpR3->u32Version, PDM_PCIHLPR3_VERSION);
2218
2219	pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
2220	pBus->pPciHlpR0 = pBus->pPciHlpR3->pfnGetR0Helpers(pDevIns);
2221
2222	/* Disable default device locking. */
2223	rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
2224	AssertRCReturn(rc, rc);
2225
2226	/*
2227	* Fill in PCI configs and add them to the bus.
2228	*/
2229	/* i440FX */
2230	PCIDevSetVendorId( &pBus->PciDev, 0x8086); /* Intel */
2231	PCIDevSetDeviceId( &pBus->PciDev, 0x1237);
2232	PCIDevSetRevisionId(&pBus->PciDev, 0x02);
2233	PCIDevSetClassSub( &pBus->PciDev, 0x00); /* host2pci */
2234	PCIDevSetClassBase( &pBus->PciDev, 0x06); /* PCI_bridge */
2235	PCIDevSetHeaderType(&pBus->PciDev, 0x00);
2236
2237	pBus->PciDev.pDevIns = pDevIns;
2238	pciDevSetRequestedDevfunc(&pBus->PciDev);
2239	pciR3RegisterDeviceInternal(pBus, 0, &pBus->PciDev, "i440FX");
2240
2241	/* PIIX3 */
2242	PCIDevSetVendorId( &pGlobals->PIIX3State.dev, 0x8086); /* Intel */
2243	PCIDevSetDeviceId( &pGlobals->PIIX3State.dev, 0x7000); /* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */
2244	PCIDevSetClassSub( &pGlobals->PIIX3State.dev, 0x01); /* PCI_ISA */
2245	PCIDevSetClassBase( &pGlobals->PIIX3State.dev, 0x06); /* PCI_bridge */
2246	PCIDevSetHeaderType(&pGlobals->PIIX3State.dev, 0x80); /* PCI_multifunction, generic */
2247
2248	pGlobals->PIIX3State.dev.pDevIns = pDevIns;
2249	pciDevSetRequestedDevfunc(&pGlobals->PIIX3State.dev);
2250	pciR3RegisterDeviceInternal(pBus, 8, &pGlobals->PIIX3State.dev, "PIIX3");
2251	pciR3Piix3Reset(&pGlobals->PIIX3State);
2252
2253	pBus->iDevSearch = 16;
2254
2255	/*
2256	* Register I/O ports and save state.
2257	*/
2258	rc = PDMDevHlpIOPortRegister(pDevIns, 0x0cf8, 1, NULL, pciIOPortAddressWrite, pciIOPortAddressRead, NULL, NULL, "i440FX (PCI)");
2259	if (RT_FAILURE(rc))
2260	return rc;
2261	rc = PDMDevHlpIOPortRegister(pDevIns, 0x0cfc, 4, NULL, pciIOPortDataWrite, pciIOPortDataRead, NULL, NULL, "i440FX (PCI)");
2262	if (RT_FAILURE(rc))
2263	return rc;
2264	if (fGCEnabled)
2265	{
2266	rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x0cf8, 1, NIL_RTGCPTR, "pciIOPortAddressWrite", "pciIOPortAddressRead", NULL, NULL, "i440FX (PCI)");
2267	if (RT_FAILURE(rc))
2268	return rc;
2269	rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x0cfc, 4, NIL_RTGCPTR, "pciIOPortDataWrite", "pciIOPortDataRead", NULL, NULL, "i440FX (PCI)");
2270	if (RT_FAILURE(rc))
2271	return rc;
2272	}
2273	if (fR0Enabled)
2274	{
2275	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x0cf8, 1, NIL_RTR0PTR, "pciIOPortAddressWrite", "pciIOPortAddressRead", NULL, NULL, "i440FX (PCI)");
2276	if (RT_FAILURE(rc))
2277	return rc;
2278	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x0cfc, 4, NIL_RTR0PTR, "pciIOPortDataWrite", "pciIOPortDataRead", NULL, NULL, "i440FX (PCI)");
2279	if (RT_FAILURE(rc))
2280	return rc;
2281	}
2282
2283	rc = PDMDevHlpSSMRegisterEx(pDevIns, VBOX_PCI_SAVED_STATE_VERSION, sizeof(pBus) + 16128, "pgm",
2284	NULL, NULL, NULL,
2285	NULL, pciR3SaveExec, NULL,
2286	NULL, pciR3LoadExec, NULL);
2287	if (RT_FAILURE(rc))
2288	return rc;
2289
2290	PDMDevHlpDBGFInfoRegister(pDevIns, "pci",
2291	"Display PCI bus status. Recognizes 'basic' or 'verbose' as arguments, defaults to 'basic'.",
2292	pciR3Info);
2293	PDMDevHlpDBGFInfoRegister(pDevIns, "pciirq", "Display PCI IRQ state. (no arguments)", pciR3IrqInfo);
2294	PDMDevHlpDBGFInfoRegister(pDevIns, "irqroute", "Display PCI IRQ routing. (no arguments)", pciR3IrqRouteInfo);
2295
2296	return VINF_SUCCESS;
2297	}
2298
2299
2300	/**
2301	* The device registration structure.
2302	*/
2303	const PDMDEVREG g_DevicePCI =
2304	{
2305	/* u32Version */
2306	PDM_DEVREG_VERSION,
2307	/* szName */
2308	"pci",
2309	/* szRCMod */
2310	"VBoxDDRC.rc",
2311	/* szR0Mod */
2312	"VBoxDDR0.r0",
2313	/* pszDescription */
2314	"i440FX PCI bridge and PIIX3 ISA bridge.",
2315	/* fFlags */
2316	PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
2317	/* fClass */
2318	PDM_DEVREG_CLASS_BUS_PCI \| PDM_DEVREG_CLASS_BUS_ISA,
2319	/* cMaxInstances */
2320	1,
2321	/* cbInstance */
2322	sizeof(PCIGLOBALS),
2323	/* pfnConstruct */
2324	pciR3Construct,
2325	/* pfnDestruct */
2326	NULL,
2327	/* pfnRelocate */
2328	pciR3Relocate,
2329	/* pfnMemSetup */
2330	NULL,
2331	/* pfnPowerOn */
2332	NULL,
2333	/* pfnReset */
2334	pciR3Reset,
2335	/* pfnSuspend */
2336	NULL,
2337	/* pfnResume */
2338	NULL,
2339	/* pfnAttach */
2340	NULL,
2341	/* pfnDetach */
2342	NULL,
2343	/* pfnQueryInterface */
2344	NULL,
2345	/* pfnInitComplete */
2346	NULL,
2347	/* pfnPowerOff */
2348	NULL,
2349	/* pfnSoftReset */
2350	NULL,
2351	/* u32VersionEnd */
2352	PDM_DEVREG_VERSION
2353
2354	};
2355	#endif /* IN_RING3 */
2356
2357
2358
2359	/* -=-=-=-=-=- The PCI bridge specific bits -=-=-=-=-=- */
2360
2361	/**
2362	* @interface_method_impl{PDMPCIBUSREG,pfnSetIrqR3}
2363	*/
2364	PDMBOTHCBDECL(void) pcibridgeSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel, uint32_t uTagSrc)
2365	{
2366	/*
2367	* The PCI-to-PCI bridge specification defines how the interrupt pins
2368	* are routed from the secondary to the primary bus (see chapter 9).
2369	* iIrq gives the interrupt pin the pci device asserted.
2370	* We change iIrq here according to the spec and call the SetIrq function
2371	* of our parent passing the device which asserted the interrupt instead of the device of the bridge.
2372	*/
2373	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
2374	PPCIDEVICE pPciDevBus = pPciDev;
2375	int iIrqPinBridge = iIrq;
2376	uint8_t uDevFnBridge = 0;
2377
2378	/* Walk the chain until we reach the host bus. */
2379	do
2380	{
2381	uDevFnBridge = pBus->PciDev.devfn;
2382	iIrqPinBridge = ((pPciDevBus->devfn >> 3) + iIrqPinBridge) & 3;
2383
2384	/* Get the parent. */
2385	pBus = pBus->PciDev.Int.s.CTX_SUFF(pBus);
2386	pPciDevBus = &pBus->PciDev;
2387	} while (pBus->iBus != 0);
2388
2389	AssertMsg(pBus->iBus == 0, ("This is not the host pci bus iBus=%d\n", pBus->iBus));
2390	pciSetIrqInternal(PCIBUS_2_PCIGLOBALS(pBus), uDevFnBridge, pPciDev, iIrqPinBridge, iLevel, uTagSrc);
2391	}
2392
2393	#ifdef IN_RING3
2394
2395	/**
2396	* @callback_method_impl{FNPCIBRIDGECONFIGWRITE}
2397	*/
2398	static DECLCALLBACK(void) pcibridgeR3ConfigWrite(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice, uint32_t u32Address, uint32_t u32Value, unsigned cb)
2399	{
2400	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
2401
2402	LogFlowFunc(("pDevIns=%p iBus=%d iDevice=%d u32Address=%u u32Value=%u cb=%d\n", pDevIns, iBus, iDevice, u32Address, u32Value, cb));
2403
2404	/* If the current bus is not the target bus search for the bus which contains the device. */
2405	if (iBus != pBus->PciDev.config[VBOX_PCI_SECONDARY_BUS])
2406	{
2407	PPCIDEVICE pBridgeDevice = pciR3FindBridge(pBus, iBus);
2408	if (pBridgeDevice)
2409	{
2410	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigWrite);
2411	pBridgeDevice->Int.s.pfnBridgeConfigWrite(pBridgeDevice->pDevIns, iBus, iDevice, u32Address, u32Value, cb);
2412	}
2413	}
2414	else
2415	{
2416	/* This is the target bus, pass the write to the device. */
2417	PPCIDEVICE pPciDev = pBus->devices[iDevice];
2418	if (pPciDev)
2419	{
2420	Log(("%s: %s: addr=%02x val=%08x len=%d\n", __FUNCTION__, pPciDev->name, u32Address, u32Value, cb));
2421	pPciDev->Int.s.pfnConfigWrite(pPciDev, u32Address, u32Value, cb);
2422	}
2423	}
2424	}
2425
2426
2427	/**
2428	* @callback_method_impl{FNPCIBRIDGECONFIGREAD}
2429	*/
2430	static DECLCALLBACK(uint32_t) pcibridgeR3ConfigRead(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice, uint32_t u32Address, unsigned cb)
2431	{
2432	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
2433	uint32_t u32Value = 0xffffffff; /* Return value in case there is no device. */
2434
2435	LogFlowFunc(("pDevIns=%p iBus=%d iDevice=%d u32Address=%u cb=%d\n", pDevIns, iBus, iDevice, u32Address, cb));
2436
2437	/* If the current bus is not the target bus search for the bus which contains the device. */
2438	if (iBus != pBus->PciDev.config[VBOX_PCI_SECONDARY_BUS])
2439	{
2440	PPCIDEVICE pBridgeDevice = pciR3FindBridge(pBus, iBus);
2441	if (pBridgeDevice)
2442	{
2443	AssertPtr( pBridgeDevice->Int.s.pfnBridgeConfigRead);
2444	u32Value = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->pDevIns, iBus, iDevice, u32Address, cb);
2445	}
2446	}
2447	else
2448	{
2449	/* This is the target bus, pass the read to the device. */
2450	PPCIDEVICE pPciDev = pBus->devices[iDevice];
2451	if (pPciDev)
2452	{
2453	u32Value = pPciDev->Int.s.pfnConfigRead(pPciDev, u32Address, cb);
2454	Log(("%s: %s: u32Address=%02x u32Value=%08x cb=%d\n", __FUNCTION__, pPciDev->name, u32Address, u32Value, cb));
2455	}
2456	}
2457
2458	return u32Value;
2459	}
2460
2461
2462	/**
2463	* @callback_method_impl{FNSSMDEVSAVEEXEC}
2464	*/
2465	static DECLCALLBACK(int) pcibridgeR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
2466	{
2467	PPCIBUS pThis = PDMINS_2_DATA(pDevIns, PPCIBUS);
2468	return pciR3CommonSaveExec(pThis, pSSM);
2469	}
2470
2471
2472	/**
2473	* @callback_method_impl{FNSSMDEVLOADEXEC}
2474	*/
2475	static DECLCALLBACK(int) pcibridgeR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2476	{
2477	PPCIBUS pThis = PDMINS_2_DATA(pDevIns, PPCIBUS);
2478	if (uVersion > VBOX_PCI_SAVED_STATE_VERSION)
2479	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2480	return pciR3CommonLoadExec(pThis, pSSM, uVersion, uPass);
2481	}
2482
2483
2484	/**
2485	* @interface_method_impl{PDMPCIBUSREG,pfnRegisterR3}
2486	*/
2487	static DECLCALLBACK(int) pcibridgeR3RegisterDevice(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, const char *pszName, int iDev)
2488	{
2489	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
2490
2491	/*
2492	* Check input.
2493	*/
2494	if ( !pszName
2495	\|\| !pPciDev
2496	\|\| iDev >= (int)RT_ELEMENTS(pBus->devices))
2497	{
2498	AssertMsgFailed(("Invalid argument! pszName=%s pPciDev=%p iDev=%d\n", pszName, pPciDev, iDev));
2499	return VERR_INVALID_PARAMETER;
2500	}
2501
2502	/*
2503	* Register the device.
2504	*/
2505	return pciR3RegisterDeviceInternal(pBus, iDev, pPciDev, pszName);
2506	}
2507
2508
2509	/**
2510	* @interface_method_impl{PDMDEVREG,pfnReset}
2511	*/
2512	static DECLCALLBACK(void) pcibridgeR3Reset(PPDMDEVINS pDevIns)
2513	{
2514	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
2515
2516	/* Reset config space to default values. */
2517	pBus->PciDev.config[VBOX_PCI_PRIMARY_BUS] = 0;
2518	pBus->PciDev.config[VBOX_PCI_SECONDARY_BUS] = 0;
2519	pBus->PciDev.config[VBOX_PCI_SUBORDINATE_BUS] = 0;
2520	}
2521
2522
2523	/**
2524	* @interface_method_impl{PDMDEVREG,pfnRelocate}
2525	*/
2526	static DECLCALLBACK(void) pcibridgeR3Relocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
2527	{
2528	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
2529	pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2530
2531	/* Relocate RC pointers for the attached pci devices. */
2532	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->devices); i++)
2533	{
2534	if (pBus->devices[i])
2535	pBus->devices[i]->Int.s.pBusRC += offDelta;
2536	}
2537	}
2538
2539
2540	/**
2541	* @interface_method_impl{PDMDEVREG,pfnConstruct}
2542	*/
2543	static DECLCALLBACK(int) pcibridgeR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
2544	{
2545	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
2546
2547	/*
2548	* Validate and read configuration.
2549	*/
2550	if (!CFGMR3AreValuesValid(pCfg, "GCEnabled\0" "R0Enabled\0"))
2551	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
2552
2553	/* check if RC code is enabled. */
2554	bool fGCEnabled;
2555	int rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
2556	if (RT_FAILURE(rc))
2557	return PDMDEV_SET_ERROR(pDevIns, rc,
2558	N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
2559
2560	/* check if R0 code is enabled. */
2561	bool fR0Enabled;
2562	rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
2563	if (RT_FAILURE(rc))
2564	return PDMDEV_SET_ERROR(pDevIns, rc,
2565	N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
2566	Log(("PCI: fGCEnabled=%RTbool fR0Enabled=%RTbool\n", fGCEnabled, fR0Enabled));
2567
2568	/*
2569	* Init data and register the PCI bus.
2570	*/
2571	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
2572	pBus->pDevInsR3 = pDevIns;
2573	pBus->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2574	pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2575	pBus->papBridgesR3 = (PPCIDEVICE )PDMDevHlpMMHeapAllocZ(pDevIns, sizeof(PPCIDEVICE) RT_ELEMENTS(pBus->devices));
2576
2577	PDMPCIBUSREG PciBusReg;
2578	PciBusReg.u32Version = PDM_PCIBUSREG_VERSION;
2579	PciBusReg.pfnRegisterR3 = pcibridgeR3RegisterDevice;
2580	PciBusReg.pfnRegisterMsiR3 = NULL;
2581	PciBusReg.pfnIORegionRegisterR3 = pciR3CommonIORegionRegister;
2582	PciBusReg.pfnSetConfigCallbacksR3 = pciR3CommonSetConfigCallbacks;
2583	PciBusReg.pfnSetIrqR3 = pcibridgeSetIrq;
2584	PciBusReg.pfnFakePCIBIOSR3 = NULL; /* Only needed for the first bus. */
2585	PciBusReg.pszSetIrqRC = fGCEnabled ? "pcibridgeSetIrq" : NULL;
2586	PciBusReg.pszSetIrqR0 = fR0Enabled ? "pcibridgeSetIrq" : NULL;
2587	rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBus->pPciHlpR3);
2588	if (RT_FAILURE(rc))
2589	return PDMDEV_SET_ERROR(pDevIns, rc,
2590	N_("Failed to register ourselves as a PCI Bus"));
2591	if (pBus->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
2592	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
2593	N_("PCI helper version mismatch; got %#x expected %#x"),
2594	pBus->pPciHlpR3->u32Version, PDM_PCIHLPR3_VERSION);
2595
2596	pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
2597	pBus->pPciHlpR0 = pBus->pPciHlpR3->pfnGetR0Helpers(pDevIns);
2598
2599	/*
2600	* Fill in PCI configs and add them to the bus.
2601	*/
2602	PCIDevSetVendorId( &pBus->PciDev, 0x8086); /* Intel */
2603	PCIDevSetDeviceId( &pBus->PciDev, 0x2448); /* 82801 Mobile PCI bridge. */
2604	PCIDevSetRevisionId(&pBus->PciDev, 0xf2);
2605	PCIDevSetClassSub( &pBus->PciDev, 0x04); /* pci2pci */
2606	PCIDevSetClassBase( &pBus->PciDev, 0x06); /* PCI_bridge */
2607	PCIDevSetClassProg( &pBus->PciDev, 0x01); /* Supports subtractive decoding. */
2608	PCIDevSetHeaderType(&pBus->PciDev, 0x01); /* Single function device which adheres to the PCI-to-PCI bridge spec. */
2609	PCIDevSetCommand( &pBus->PciDev, 0x00);
2610	PCIDevSetStatus( &pBus->PciDev, 0x20); /* 66MHz Capable. */
2611	PCIDevSetInterruptLine(&pBus->PciDev, 0x00); /* This device does not assert interrupts. */
2612
2613	/*
2614	* This device does not generate interrupts. Interrupt delivery from
2615	* devices attached to the bus is unaffected.
2616	*/
2617	PCIDevSetInterruptPin(&pBus->PciDev, 0x00);
2618
2619	pBus->PciDev.pDevIns = pDevIns;
2620
2621	/* Bridge-specific data */
2622	pciDevSetPci2PciBridge(&pBus->PciDev);
2623	pBus->PciDev.Int.s.pfnBridgeConfigRead = pcibridgeR3ConfigRead;
2624	pBus->PciDev.Int.s.pfnBridgeConfigWrite = pcibridgeR3ConfigWrite;
2625
2626	/*
2627	* Register this PCI bridge. The called function will take care on which bus we will get registered.
2628	*/
2629	rc = PDMDevHlpPCIRegister(pDevIns, &pBus->PciDev);
2630	if (RT_FAILURE(rc))
2631	return rc;
2632
2633	pBus->iDevSearch = 0;
2634	/*
2635	* The iBus property doesn't really represent the bus number
2636	* because the guest and the BIOS can choose different bus numbers
2637	* for them.
2638	* The bus number is mainly for the setIrq function to indicate
2639	* when the host bus is reached which will have iBus = 0.
2640	* That's why the + 1.
2641	*/
2642	pBus->iBus = iInstance + 1;
2643
2644	/*
2645	* Register SSM handlers. We use the same saved state version as for the host bridge
2646	* to make changes easier.
2647	*/
2648	rc = PDMDevHlpSSMRegisterEx(pDevIns, VBOX_PCI_SAVED_STATE_VERSION, sizeof(pBus) + 16128, "pgm",
2649	NULL, NULL, NULL,
2650	NULL, pcibridgeR3SaveExec, NULL,
2651	NULL, pcibridgeR3LoadExec, NULL);
2652	if (RT_FAILURE(rc))
2653	return rc;
2654
2655	return VINF_SUCCESS;
2656	}
2657
2658
2659	/**
2660	* The device registration structure
2661	* for the PCI-to-PCI bridge.
2662	*/
2663	const PDMDEVREG g_DevicePCIBridge =
2664	{
2665	/* u32Version */
2666	PDM_DEVREG_VERSION,
2667	/* szName */
2668	"pcibridge",
2669	/* szRCMod */
2670	"VBoxDDRC.rc",
2671	/* szR0Mod */
2672	"VBoxDDR0.r0",
2673	/* pszDescription */
2674	"82801 Mobile PCI to PCI bridge",
2675	/* fFlags */
2676	PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
2677	/* fClass */
2678	PDM_DEVREG_CLASS_BUS_PCI,
2679	/* cMaxInstances */
2680	~0U,
2681	/* cbInstance */
2682	sizeof(PCIBUS),
2683	/* pfnConstruct */
2684	pcibridgeR3Construct,
2685	/* pfnDestruct */
2686	NULL,
2687	/* pfnRelocate */
2688	pcibridgeR3Relocate,
2689	/* pfnMemSetup */
2690	NULL,
2691	/* pfnPowerOn */
2692	NULL,
2693	/* pfnReset */
2694	pcibridgeR3Reset,
2695	/* pfnSuspend */
2696	NULL,
2697	/* pfnResume */
2698	NULL,
2699	/* pfnAttach */
2700	NULL,
2701	/* pfnDetach */
2702	NULL,
2703	/* pfnQueryInterface */
2704	NULL,
2705	/* pfnInitComplete */
2706	NULL,
2707	/* pfnPowerOff */
2708	NULL,
2709	/* pfnSoftReset */
2710	NULL,
2711	/* u32VersionEnd */
2712	PDM_DEVREG_VERSION
2713	};
2714
2715	#endif /* IN_RING3 */
2716	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */

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source: vbox/trunk/src/VBox/Devices/Bus/DevPCI.cpp@ 63845

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