DevPCI.cpp@ 64375

Last change on this file since 64375 was 64373, checked in by vboxsync, 8 years ago
PDM,Devices: Support for multiple PCI devices/function in a single PDM device.
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1	/* $Id: DevPCI.cpp 64373 2016-10-23 19:03:39Z vboxsync $ */
2	/** @file
3	* DevPCI - PCI BUS Device.
4	*/
5
6	/*
7	* Copyright (C) 2006-2016 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	* --------------------------------------------------------------------
17	*
18	* This code is based on:
19	*
20	* QEMU PCI bus manager
21	*
22	* Copyright (c) 2004 Fabrice Bellard
23	*
24	* Permission is hereby granted, free of charge, to any person obtaining a copy
25	* of this software and associated documentation files (the "Software"), to deal
26	* in the Software without restriction, including without limitation the rights
27	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
28	* copies of the Software, and to permit persons to whom the Software is
29	* furnished to do so, subject to the following conditions:
30	*
31	* The above copyright notice and this permission notice shall be included in
32	* all copies or substantial portions of the Software.
33	*
34	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
35	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
36	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
37	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
38	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
39	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
40	* THE SOFTWARE.
41	*/
42
43
44	/*********************************************************************************************************************************
45	* Header Files *
46	*********************************************************************************************************************************/
47	#define LOG_GROUP LOG_GROUP_DEV_PCI
48	#define PDMPCIDEV_INCLUDE_PRIVATE /* Hack to get pdmpcidevint.h included at the right point. */
49	#include <VBox/vmm/pdmpcidev.h>
50	#include <VBox/vmm/pdmdev.h>
51	#include <VBox/vmm/mm.h>
52	#include <iprt/asm.h>
53	#include <iprt/assert.h>
54	#include <iprt/string.h>
55
56	#include "PciInline.h"
57	#include "VBoxDD.h"
58
59
60	/*********************************************************************************************************************************
61	* Structures and Typedefs *
62	*********************************************************************************************************************************/
63	/**
64	* PIIX3 ISA Bridge state.
65	*/
66	typedef struct PIIX3State
67	{
68	/** The PCI device of the bridge. */
69	PCIDEVICE dev;
70	} PIIX3State, PIIX3, *PPIIX3;
71
72	/**
73	* PCI Bus instance.
74	*/
75	typedef struct PCIBus
76	{
77	/** Bus number. */
78	int32_t iBus;
79	/** Start device number. */
80	uint32_t iDevSearch;
81	/** Number of bridges attached to the bus. */
82	uint32_t cBridges;
83
84	uint32_t Alignment0;
85
86	union
87	{
88	/** Array of PCI devices. */
89	R3PTRTYPE(PPCIDEVICE) apDevices[256];
90	/** @deprecated */
91	R3PTRTYPE(PPCIDEVICE) devices[256];
92	};
93	/** Array of bridges attached to the bus. */
94	R3PTRTYPE(PPCIDEVICE *) papBridgesR3;
95
96	/** R3 pointer to the device instance. */
97	PPDMDEVINSR3 pDevInsR3;
98	/** Pointer to the PCI R3 helpers. */
99	PCPDMPCIHLPR3 pPciHlpR3;
100
101	/** R0 pointer to the device instance. */
102	PPDMDEVINSR0 pDevInsR0;
103	/** Pointer to the PCI R0 helpers. */
104	PCPDMPCIHLPR0 pPciHlpR0;
105
106	/** RC pointer to the device instance. */
107	PPDMDEVINSRC pDevInsRC;
108	/** Pointer to the PCI RC helpers. */
109	PCPDMPCIHLPRC pPciHlpRC;
110
111	/** The PCI device for the PCI bridge. */
112	PCIDEVICE PciDev;
113
114	} PCIBUS;
115	/** Pointer to a PCIBUS instance. */
116	typedef PCIBUS *PPCIBUS;
117	typedef PCIBUS PCIBus;
118
119	/** @def PCI_IRQ_PINS
120	* Number of pins for interrupts (PIRQ#0...PIRQ#3)
121	*/
122	#define PCI_IRQ_PINS 4
123
124	/** @def PCI_APIC_IRQ_PINS
125	* Number of pins for interrupts if the APIC is used.
126	*/
127	#define PCI_APIC_IRQ_PINS 8
128
129	/**
130	* PCI Globals - This is the host-to-pci bridge and the root bus.
131	*/
132	typedef struct PCIGLOBALS
133	{
134	/** Irq levels for the four PCI Irqs.
135	* These count how many devices asserted
136	* the IRQ line. If greater 0 an IRQ is sent to the guest.
137	* If it drops to 0 the IRQ is deasserted.
138	*/
139	volatile uint32_t pci_irq_levels[PCI_IRQ_PINS];
140
141	#if 1 /* Will be moved into the BIOS soon. */
142	/** The next I/O port address which the PCI BIOS will use. */
143	uint32_t pci_bios_io_addr;
144	/** The next MMIO address which the PCI BIOS will use. */
145	uint32_t pci_bios_mem_addr;
146	/** Actual bus number. */
147	uint8_t uBus;
148	#endif
149
150	/** I/O APIC usage flag */
151	bool fUseIoApic;
152	/** I/O APIC irq levels */
153	volatile uint32_t pci_apic_irq_levels[PCI_APIC_IRQ_PINS];
154	/** ACPI IRQ level */
155	uint32_t acpi_irq_level;
156	/** ACPI PIC IRQ */
157	int acpi_irq;
158	/** Config register. */
159	uint32_t uConfigReg;
160
161	/** R3 pointer to the device instance. */
162	PPDMDEVINSR3 pDevInsR3;
163	/** R0 pointer to the device instance. */
164	PPDMDEVINSR0 pDevInsR0;
165	/** RC pointer to the device instance. */
166	PPDMDEVINSRC pDevInsRC;
167
168	#if HC_ARCH_BITS == 64
169	uint32_t Alignment0;
170	#endif
171
172	/** ISA bridge state. */
173	PIIX3 PIIX3State;
174	/** PCI bus which is attached to the host-to-PCI bridge. */
175	PCIBUS PciBus;
176
177	} PCIGLOBALS;
178	/** Pointer to per VM data. */
179	typedef PCIGLOBALS *PPCIGLOBALS;
180
181
182	/*********************************************************************************************************************************
183	* Defined Constants And Macros *
184	*********************************************************************************************************************************/
185
186	/** Converts a bus instance pointer to a device instance pointer. */
187	#define PCIBUS_2_DEVINS(pPciBus) ((pPciBus)->CTX_SUFF(pDevIns))
188	/** Converts a PCI bus device instance pointer to a PCIGLOBALS pointer. */
189	#define DEVINS_2_PCIGLOBALS(pDevIns) ((PPCIGLOBALS)(PDMINS_2_DATA(pDevIns, PPCIGLOBALS)))
190	/** Converts a PCI bus device instance pointer to a PCIBUS pointer. */
191	#define DEVINS_2_PCIBUS(pDevIns) ((PPCIBUS)(&PDMINS_2_DATA(pDevIns, PPCIGLOBALS)->PciBus))
192
193	/** Converts a pointer to a PCI bus instance to a PCIGLOBALS pointer.
194	* @note This works only if the bus number is 0!!!
195	*/
196	#define PCIBUS_2_PCIGLOBALS(pPciBus) RT_FROM_MEMBER(pPciBus, PCIGLOBALS, PciBus)
197
198	/** @def PCI_LOCK
199	* Acquires the PDM lock. This is a NOP if locking is disabled. */
200	/** @def PCI_UNLOCK
201	* Releases the PDM lock. This is a NOP if locking is disabled. */
202	#define PCI_LOCK(pDevIns, rc) \
203	do { \
204	int rc2 = DEVINS_2_PCIBUS(pDevIns)->CTX_SUFF(pPciHlp)->pfnLock((pDevIns), rc); \
205	if (rc2 != VINF_SUCCESS) \
206	return rc2; \
207	} while (0)
208	#define PCI_UNLOCK(pDevIns) \
209	DEVINS_2_PCIBUS(pDevIns)->CTX_SUFF(pPciHlp)->pfnUnlock(pDevIns)
210
211	/** @def VBOX_PCI_SAVED_STATE_VERSION
212	* Saved state version of the PCI bus device.
213	*/
214	#define VBOX_PCI_SAVED_STATE_VERSION 3
215
216
217	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
218
219
220	/*********************************************************************************************************************************
221	* Internal Functions *
222	*********************************************************************************************************************************/
223	RT_C_DECLS_BEGIN
224
225	PDMBOTHCBDECL(void) pciSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel, uint32_t uTag);
226	PDMBOTHCBDECL(void) pcibridgeSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel, uint32_t uTag);
227	PDMBOTHCBDECL(int) pciIOPortAddressWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
228	PDMBOTHCBDECL(int) pciIOPortAddressRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb);
229	PDMBOTHCBDECL(int) pciIOPortDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
230	PDMBOTHCBDECL(int) pciIOPortDataRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb);
231
232	#ifdef IN_RING3
233	DECLINLINE(PPCIDEVICE) pciR3FindBridge(PPCIBUS pBus, uint8_t iBus);
234	#endif
235
236	RT_C_DECLS_END
237
238	#define DEBUG_PCI
239
240	#define PCI_VENDOR_ID 0x00 /* 16 bits */
241	#define PCI_DEVICE_ID 0x02 /* 16 bits */
242	#define PCI_COMMAND 0x04 /* 16 bits */
243	#define PCI_COMMAND_IO 0x01 /* Enable response in I/O space */
244	#define PCI_COMMAND_MEMORY 0x02 /* Enable response in Memory space */
245	#define PCI_CLASS_DEVICE 0x0a /* Device class */
246	#define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
247	#define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
248	#define PCI_MIN_GNT 0x3e /* 8 bits */
249	#define PCI_MAX_LAT 0x3f /* 8 bits */
250
251
252	#ifdef IN_RING3
253
254	static void pci_update_mappings(PCIDevice *d)
255	{
256	PPCIBUS pBus = d->Int.s.CTX_SUFF(pBus);
257	PCIIORegion *r;
258	int cmd, i;
259	uint32_t last_addr, new_addr, config_ofs;
260
261	cmd = RT_LE2H_U16((uint16_t )(d->config + PCI_COMMAND));
262	for(i = 0; i < PCI_NUM_REGIONS; i++) {
263	r = &d->Int.s.aIORegions[i];
264	if (i == PCI_ROM_SLOT) {
265	config_ofs = 0x30;
266	} else {
267	config_ofs = 0x10 + i * 4;
268	}
269	if (r->size != 0) {
270	if (r->type & PCI_ADDRESS_SPACE_IO) {
271	if (cmd & PCI_COMMAND_IO) {
272	new_addr = RT_LE2H_U32((uint32_t )(d->config +
273	config_ofs));
274	new_addr = new_addr & ~(r->size - 1);
275	last_addr = new_addr + r->size - 1;
276	/* NOTE: we have only 64K ioports on PC */
277	if (last_addr <= new_addr \|\| new_addr == 0 \|\|
278	last_addr >= 0x10000) {
279	new_addr = ~0U;
280	}
281	} else {
282	new_addr = ~0U;
283	}
284	} else {
285	if (cmd & PCI_COMMAND_MEMORY) {
286	new_addr = RT_LE2H_U32((uint32_t )(d->config +
287	config_ofs));
288	/* the ROM slot has a specific enable bit */
289	if (i == PCI_ROM_SLOT && !(new_addr & 1))
290	goto no_mem_map;
291	new_addr = new_addr & ~(r->size - 1);
292	last_addr = new_addr + r->size - 1;
293	/* NOTE: we do not support wrapping */
294	/* XXX: as we cannot support really dynamic
295	mappings, we handle specific values as invalid
296	mappings. */
297	/* Unconditionally exclude I/O-APIC/HPET/ROM. Pessimistic, but better than causing a mess. */
298	if (last_addr <= new_addr \|\| new_addr == 0 \|\|
299	(new_addr <= ~0U && last_addr >= 0xfec00000U)) {
300	new_addr = ~0U;
301	}
302	} else {
303	no_mem_map:
304	new_addr = ~0U;
305	}
306	}
307	//LogRel(("PCI: config dev %u/%u BAR%i uOld=%#018llx uNew=%#018llx size=%llu\n", d->devfn >> 3, d->devfn & 7, i, r->addr, new_addr, r->size));
308	/* now do the real mapping */
309	if (new_addr != r->addr) {
310	if (r->addr != ~0U) {
311	if (r->type & PCI_ADDRESS_SPACE_IO) {
312	int devclass;
313	/* NOTE: specific hack for IDE in PC case:
314	only one byte must be mapped. */
315	devclass = d->config[0x0a] \| (d->config[0x0b] << 8);
316	if (devclass == 0x0101 && r->size == 4) {
317	int rc = PDMDevHlpIOPortDeregister(d->pDevIns, r->addr + 2, 1);
318	AssertRC(rc);
319	} else {
320	int rc = PDMDevHlpIOPortDeregister(d->pDevIns, r->addr, r->size);
321	AssertRC(rc);
322	}
323	} else {
324	RTGCPHYS GCPhysBase = r->addr;
325	int rc;
326	if (pBus->pPciHlpR3->pfnIsMMIOExBase(pBus->pDevInsR3, d->pDevIns, GCPhysBase))
327	{
328	/* unmap it. */
329	rc = r->map_func(d->Int.s.pDevInsR3, d, i, NIL_RTGCPHYS, r->size, (PCIADDRESSSPACE)(r->type));
330	AssertRC(rc);
331	rc = PDMDevHlpMMIOExUnmap(d->pDevIns, d, i, GCPhysBase);
332	}
333	else
334	rc = PDMDevHlpMMIODeregister(d->pDevIns, GCPhysBase, r->size);
335	AssertMsgRC(rc, ("rc=%Rrc d=%s i=%d GCPhysBase=%RGp size=%#x\n", rc, d->name, i, GCPhysBase, r->size));
336	}
337	}
338	r->addr = new_addr;
339	if (r->addr != ~0U) {
340	int rc = r->map_func(d->Int.s.pDevInsR3, d, i,
341	r->addr + (r->type & PCI_ADDRESS_SPACE_IO ? 0 : 0),
342	r->size, (PCIADDRESSSPACE)(r->type));
343	AssertRC(rc);
344	}
345	}
346	}
347	}
348	}
349
350
351	static DECLCALLBACK(uint32_t) pci_default_read_config(PPDMDEVINS pDevIns, PCIDevice *d, uint32_t address, unsigned len)
352	{
353	NOREF(pDevIns);
354	uint32_t val;
355	switch(len) {
356	case 1:
357	val = d->config[address];
358	break;
359	case 2:
360	val = RT_LE2H_U16((uint16_t )(d->config + address));
361	break;
362	default:
363	case 4:
364	val = RT_LE2H_U32((uint32_t )(d->config + address));
365	break;
366	}
367	return val;
368	}
369
370	static DECLCALLBACK(void) pci_default_write_config(PPDMDEVINS pDevIns, PCIDevice *d, uint32_t address, uint32_t val, unsigned len)
371	{
372	NOREF(pDevIns);
373	int can_write;
374	unsigned i;
375	uint32_t end, addr;
376
377	if (len == 4 && ((address >= 0x10 && address < 0x10 + 4 * 6) \|\|
378	(address >= 0x30 && address < 0x34))) {
379	PCIIORegion *r;
380	int reg;
381
382	if ( address >= 0x30 ) {
383	reg = PCI_ROM_SLOT;
384	}else{
385	reg = (address - 0x10) >> 2;
386	}
387	r = &d->Int.s.aIORegions[reg];
388	if (r->size == 0)
389	goto default_config;
390	/* compute the stored value */
391	if (reg == PCI_ROM_SLOT) {
392	/* keep ROM enable bit */
393	val &= (~(r->size - 1)) \| 1;
394	} else {
395	val &= ~(r->size - 1);
396	val \|= r->type;
397	}
398	(uint32_t )(d->config + address) = RT_H2LE_U32(val);
399	pci_update_mappings(d);
400	return;
401	}
402	default_config:
403	/* not efficient, but simple */
404	addr = address;
405	for(i = 0; i < len; i++) {
406	/* default read/write accesses */
407	switch(d->config[0x0e]) {
408	case 0x00: /* normal device */
409	case 0x80: /* multi-function device */
410	switch(addr) {
411	case 0x00:
412	case 0x01:
413	case 0x02:
414	case 0x03:
415	case 0x08:
416	case 0x09:
417	case 0x0a:
418	case 0x0b:
419	case 0x0e:
420	case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17: /* base */
421	case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f:
422	case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27:
423	case 0x2c: case 0x2d: /* subsystem ID */
424	case 0x2e: case 0x2f: /* vendor ID */
425	case 0x30: case 0x31: case 0x32: case 0x33: /* rom */
426	case 0x34: /* Capabilities pointer. */
427	case 0x3d: /* Interrupt pin. */
428	can_write = 0;
429	break;
430	default:
431	can_write = 1;
432	break;
433	}
434	break;
435	default:
436	case 0x01: /* bridge */
437	switch(addr) {
438	case 0x00:
439	case 0x01:
440	case 0x02:
441	case 0x03:
442	case 0x08:
443	case 0x09:
444	case 0x0a:
445	case 0x0b:
446	case 0x0e:
447	case 0x38: case 0x39: case 0x3a: case 0x3b: /* rom */
448	case 0x3d:
449	can_write = 0;
450	break;
451	default:
452	can_write = 1;
453	break;
454	}
455	break;
456	}
457	#ifdef VBOX
458	if (addr == 0x05) /* Command register, bits 8-15. */
459	{
460	/* don't change reserved bits (11-15) */
461	val &= ~UINT32_C(0xf8);
462	d->config[addr] = val;
463	}
464	else if (addr == 0x06) /* Status register, bits 0-7. */
465	{
466	/* don't change read-only bits => actually all lower bits are read-only */
467	val &= ~UINT32_C(0xff);
468	/* status register, low part: clear bits by writing a '1' to the corresponding bit */
469	d->config[addr] &= ~val;
470	}
471	else if (addr == 0x07) /* Status register, bits 8-15. */
472	{
473	/* don't change read-only bits */
474	val &= ~UINT32_C(0x06);
475	/* status register, high part: clear bits by writing a '1' to the corresponding bit */
476	d->config[addr] &= ~val;
477	}
478	else
479	#endif
480	if (can_write) {
481	d->config[addr] = val;
482	}
483	addr++;
484	val >>= 8;
485	}
486
487	end = address + len;
488	if (end > PCI_COMMAND && address < (PCI_COMMAND + 2)) {
489	/* if the command register is modified, we must modify the mappings */
490	pci_update_mappings(d);
491	}
492	}
493
494	#endif /* IN_RING3 */
495
496	static int pci_data_write(PPCIGLOBALS pGlobals, uint32_t addr, uint32_t val, int len)
497	{
498	uint8_t iBus, iDevice;
499	uint32_t config_addr;
500
501	Log(("pci_data_write: addr=%08x val=%08x len=%d\n", pGlobals->uConfigReg, val, len));
502
503	if (!(pGlobals->uConfigReg & (1 << 31))) {
504	return VINF_SUCCESS;
505	}
506	if ((pGlobals->uConfigReg & 0x3) != 0) {
507	return VINF_SUCCESS;
508	}
509	iBus = (pGlobals->uConfigReg >> 16) & 0xff;
510	iDevice = (pGlobals->uConfigReg >> 8) & 0xff;
511	config_addr = (pGlobals->uConfigReg & 0xfc) \| (addr & 3);
512	if (iBus != 0)
513	{
514	if (pGlobals->PciBus.cBridges)
515	{
516	#ifdef IN_RING3 /** @todo do lookup in R0/RC too! */
517	PPCIDEVICE pBridgeDevice = pciR3FindBridge(&pGlobals->PciBus, iBus);
518	if (pBridgeDevice)
519	{
520	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigWrite);
521	pBridgeDevice->Int.s.pfnBridgeConfigWrite(pBridgeDevice->pDevIns, iBus, iDevice, config_addr, val, len);
522	}
523	#else
524	RT_NOREF2(val, len);
525	return VINF_IOM_R3_IOPORT_WRITE;
526	#endif
527	}
528	}
529	else
530	{
531	R3PTRTYPE(PCIDevice *) pci_dev = pGlobals->PciBus.devices[iDevice];
532	if (pci_dev)
533	{
534	#ifdef IN_RING3
535	Log(("pci_config_write: %s: addr=%02x val=%08x len=%d\n", pci_dev->name, config_addr, val, len));
536	pci_dev->Int.s.pfnConfigWrite(pci_dev->Int.s.CTX_SUFF(pDevIns), pci_dev, config_addr, val, len);
537	#else
538	return VINF_IOM_R3_IOPORT_WRITE;
539	#endif
540	}
541	}
542	return VINF_SUCCESS;
543	}
544
545	static int pci_data_read(PPCIGLOBALS pGlobals, uint32_t addr, int len, uint32_t *pu32)
546	{
547	uint8_t iBus, iDevice;
548	uint32_t config_addr;
549
550	*pu32 = 0xffffffff;
551
552	if (!(pGlobals->uConfigReg & (1 << 31)))
553	return VINF_SUCCESS;
554	if ((pGlobals->uConfigReg & 0x3) != 0)
555	return VINF_SUCCESS;
556	iBus = (pGlobals->uConfigReg >> 16) & 0xff;
557	iDevice = (pGlobals->uConfigReg >> 8) & 0xff;
558	config_addr = (pGlobals->uConfigReg & 0xfc) \| (addr & 3);
559	if (iBus != 0)
560	{
561	if (pGlobals->PciBus.cBridges)
562	{
563	#ifdef IN_RING3 /** @todo do lookup in R0/RC too! */
564	PPCIDEVICE pBridgeDevice = pciR3FindBridge(&pGlobals->PciBus, iBus);
565	if (pBridgeDevice)
566	{
567	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigRead);
568	*pu32 = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->pDevIns, iBus, iDevice, config_addr, len);
569	}
570	#else
571	NOREF(len);
572	return VINF_IOM_R3_IOPORT_READ;
573	#endif
574	}
575	}
576	else
577	{
578	R3PTRTYPE(PCIDevice *) pci_dev = pGlobals->PciBus.devices[iDevice];
579	if (pci_dev)
580	{
581	#ifdef IN_RING3
582	*pu32 = pci_dev->Int.s.pfnConfigRead(pci_dev->Int.s.CTX_SUFF(pDevIns), pci_dev, config_addr, len);
583	Log(("pci_config_read: %s: addr=%02x val=%08x len=%d\n", pci_dev->name, config_addr, *pu32, len));
584	#else
585	NOREF(len);
586	return VINF_IOM_R3_IOPORT_READ;
587	#endif
588	}
589	}
590
591	return VINF_SUCCESS;
592	}
593
594
595
596	/* return the global irq number corresponding to a given device irq
597	pin. We could also use the bus number to have a more precise
598	mapping.
599	This is the implementation note described in the PCI spec chapter 2.2.6 */
600	static inline int pci_slot_get_pirq(uint8_t uDevFn, int irq_num)
601	{
602	int slot_addend;
603	slot_addend = (uDevFn >> 3) - 1;
604	return (irq_num + slot_addend) & 3;
605	}
606
607	static inline int pci_slot_get_apic_pirq(uint8_t uDevFn, int irq_num)
608	{
609	return (irq_num + (uDevFn >> 3)) & 7;
610	}
611
612	static inline int get_pci_irq_apic_level(PPCIGLOBALS pGlobals, int irq_num)
613	{
614	return (pGlobals->pci_apic_irq_levels[irq_num] != 0);
615	}
616
617	static void apic_set_irq(PPCIBUS pBus, uint8_t uDevFn, PCIDevice *pPciDev, int irq_num1, int iLevel, int acpi_irq, uint32_t uTagSrc)
618	{
619	/* This is only allowed to be called with a pointer to the host bus. */
620	AssertMsg(pBus->iBus == 0, ("iBus=%u\n", pBus->iBus));
621
622	if (acpi_irq == -1) {
623	int apic_irq, apic_level;
624	PPCIGLOBALS pGlobals = PCIBUS_2_PCIGLOBALS(pBus);
625	int irq_num = pci_slot_get_apic_pirq(uDevFn, irq_num1);
626
627	if ((iLevel & PDM_IRQ_LEVEL_HIGH) == PDM_IRQ_LEVEL_HIGH)
628	ASMAtomicIncU32(&pGlobals->pci_apic_irq_levels[irq_num]);
629	else if ((iLevel & PDM_IRQ_LEVEL_HIGH) == PDM_IRQ_LEVEL_LOW)
630	ASMAtomicDecU32(&pGlobals->pci_apic_irq_levels[irq_num]);
631
632	apic_irq = irq_num + 0x10;
633	apic_level = get_pci_irq_apic_level(pGlobals, irq_num);
634	Log3(("apic_set_irq: %s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d\n",
635	R3STRING(pPciDev->name), irq_num1, iLevel, apic_irq, apic_level, irq_num));
636	pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), apic_irq, apic_level, uTagSrc);
637
638	if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP) {
639	ASMAtomicDecU32(&pGlobals->pci_apic_irq_levels[irq_num]);
640	pPciDev->Int.s.uIrqPinState = PDM_IRQ_LEVEL_LOW;
641	apic_level = get_pci_irq_apic_level(pGlobals, irq_num);
642	Log3(("apic_set_irq: %s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d (flop)\n",
643	R3STRING(pPciDev->name), irq_num1, iLevel, apic_irq, apic_level, irq_num));
644	pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), apic_irq, apic_level, uTagSrc);
645	}
646	} else {
647	Log3(("apic_set_irq: %s: irq_num1=%d level=%d acpi_irq=%d\n",
648	R3STRING(pPciDev->name), irq_num1, iLevel, acpi_irq));
649	pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), acpi_irq, iLevel, uTagSrc);
650	}
651	}
652
653	DECLINLINE(int) get_pci_irq_level(PPCIGLOBALS pGlobals, int irq_num)
654	{
655	return (pGlobals->pci_irq_levels[irq_num] != 0);
656	}
657
658	/**
659	* Set the IRQ for a PCI device on the host bus - shared by host bus and bridge.
660	*
661	* @param pDevIns Device instance of the host PCI Bus.
662	* @param uDevFn The device number on the host bus which will raise the IRQ
663	* @param pPciDev The PCI device structure which raised the interrupt.
664	* @param iIrq IRQ number to set.
665	* @param iLevel IRQ level.
666	* @param uTagSrc The IRQ tag and source ID (for tracing).
667	* @remark uDevFn and pPciDev->devfn are not the same if the device is behind a bridge.
668	* In that case uDevFn will be the slot of the bridge which is needed to calculate the
669	* PIRQ value.
670	*/
671	static void pciSetIrqInternal(PPCIGLOBALS pGlobals, uint8_t uDevFn, PPCIDEVICE pPciDev, int iIrq, int iLevel, uint32_t uTagSrc)
672	{
673	PPCIBUS pBus = &pGlobals->PciBus;
674	uint8_t *pbCfg = pGlobals->PIIX3State.dev.config;
675	const bool fIsAcpiDevice = pPciDev->config[2] == 0x13 && pPciDev->config[3] == 0x71;
676	/* If the two configuration space bytes at 0xde, 0xad are set to 0xbe, 0xef, a back door
677	* is opened to route PCI interrupts directly to the I/O APIC and bypass the PIC.
678	* See the \_SB_.PCI0._PRT method in vbox.dsl.
679	*/
680	const bool fIsApicEnabled = pGlobals->fUseIoApic && pbCfg[0xde] == 0xbe && pbCfg[0xad] == 0xef;
681	int pic_irq, pic_level;
682
683	/* Check if the state changed. */
684	if (pPciDev->Int.s.uIrqPinState != iLevel)
685	{
686	pPciDev->Int.s.uIrqPinState = (iLevel & PDM_IRQ_LEVEL_HIGH);
687
688	/* Send interrupt to I/O APIC only. */
689	if (fIsApicEnabled)
690	{
691	if (fIsAcpiDevice)
692	/*
693	* ACPI needs special treatment since SCI is hardwired and
694	* should not be affected by PCI IRQ routing tables at the
695	* same time SCI IRQ is shared in PCI sense hence this
696	* kludge (i.e. we fetch the hardwired value from ACPIs
697	* PCI device configuration space).
698	*/
699	apic_set_irq(pBus, uDevFn, pPciDev, -1, iLevel, pPciDev->config[PCI_INTERRUPT_LINE], uTagSrc);
700	else
701	apic_set_irq(pBus, uDevFn, pPciDev, iIrq, iLevel, -1, uTagSrc);
702	return;
703	}
704
705	if (fIsAcpiDevice)
706	{
707	/* As per above treat ACPI in a special way */
708	pic_irq = pPciDev->config[PCI_INTERRUPT_LINE];
709	pGlobals->acpi_irq = pic_irq;
710	pGlobals->acpi_irq_level = iLevel & PDM_IRQ_LEVEL_HIGH;
711	}
712	else
713	{
714	int irq_num;
715	irq_num = pci_slot_get_pirq(uDevFn, iIrq);
716
717	if (pPciDev->Int.s.uIrqPinState == PDM_IRQ_LEVEL_HIGH)
718	ASMAtomicIncU32(&pGlobals->pci_irq_levels[irq_num]);
719	else if (pPciDev->Int.s.uIrqPinState == PDM_IRQ_LEVEL_LOW)
720	ASMAtomicDecU32(&pGlobals->pci_irq_levels[irq_num]);
721
722	/* now we change the pic irq level according to the piix irq mappings */
723	pic_irq = pbCfg[0x60 + irq_num];
724	if (pic_irq >= 16)
725	{
726	if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP)
727	{
728	ASMAtomicDecU32(&pGlobals->pci_irq_levels[irq_num]);
729	pPciDev->Int.s.uIrqPinState = PDM_IRQ_LEVEL_LOW;
730	}
731
732	return;
733	}
734	}
735
736	/* the pic level is the logical OR of all the PCI irqs mapped to it */
737	pic_level = 0;
738	if (pic_irq == pbCfg[0x60])
739	pic_level \|= get_pci_irq_level(pGlobals, 0);
740	if (pic_irq == pbCfg[0x61])
741	pic_level \|= get_pci_irq_level(pGlobals, 1);
742	if (pic_irq == pbCfg[0x62])
743	pic_level \|= get_pci_irq_level(pGlobals, 2);
744	if (pic_irq == pbCfg[0x63])
745	pic_level \|= get_pci_irq_level(pGlobals, 3);
746	if (pic_irq == pGlobals->acpi_irq)
747	pic_level \|= pGlobals->acpi_irq_level;
748
749	Log3(("pciSetIrq: %s: iLevel=%d iIrq=%d pic_irq=%d pic_level=%d uTagSrc=%#x\n",
750	R3STRING(pPciDev->name), iLevel, iIrq, pic_irq, pic_level, uTagSrc));
751	pBus->CTX_SUFF(pPciHlp)->pfnIsaSetIrq(pBus->CTX_SUFF(pDevIns), pic_irq, pic_level, uTagSrc);
752
753	/** @todo optimize pci irq flip-flop some rainy day. */
754	if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP)
755	pciSetIrqInternal(pGlobals, uDevFn, pPciDev, iIrq, PDM_IRQ_LEVEL_LOW, uTagSrc);
756	}
757	}
758
759
760	/**
761	* @interface_method_impl{PDMPCIBUSREG,pfnSetIrqR3}
762	*/
763	PDMBOTHCBDECL(void) pciSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel, uint32_t uTagSrc)
764	{
765	pciSetIrqInternal(PDMINS_2_DATA(pDevIns, PPCIGLOBALS), pPciDev->devfn, pPciDev, iIrq, iLevel, uTagSrc);
766	}
767
768	#ifdef IN_RING3
769
770	/**
771	* Finds a bridge on the bus which contains the destination bus.
772	*
773	* @return Pointer to the device instance data of the bus or
774	* NULL if no bridge was found.
775	* @param pBus Pointer to the bus to search on.
776	* @param iBus Destination bus number.
777	*/
778	DECLINLINE(PPCIDEVICE) pciR3FindBridge(PPCIBUS pBus, uint8_t iBus)
779	{
780	/* Search for a fitting bridge. */
781	for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
782	{
783	/*
784	* Examine secondary and subordinate bus number.
785	* If the target bus is in the range we pass the request on to the bridge.
786	*/
787	PPCIDEVICE pBridgeTemp = pBus->papBridgesR3[iBridge];
788	AssertMsg(pBridgeTemp && pciDevIsPci2PciBridge(pBridgeTemp),
789	("Device is not a PCI bridge but on the list of PCI bridges\n"));
790
791	if ( iBus >= pBridgeTemp->config[VBOX_PCI_SECONDARY_BUS]
792	&& iBus <= pBridgeTemp->config[VBOX_PCI_SUBORDINATE_BUS])
793	return pBridgeTemp;
794	}
795
796	/* Nothing found. */
797	return NULL;
798	}
799
800	static void pciR3Piix3Reset(PIIX3State *d)
801	{
802	uint8_t *pci_conf = d->dev.config;
803
804	pci_conf[0x04] = 0x07; /* master, memory and I/O */
805	pci_conf[0x05] = 0x00;
806	pci_conf[0x06] = 0x00;
807	pci_conf[0x07] = 0x02; /* PCI_status_devsel_medium */
808	pci_conf[0x4c] = 0x4d;
809	pci_conf[0x4e] = 0x03;
810	pci_conf[0x4f] = 0x00;
811	pci_conf[0x60] = 0x80;
812	pci_conf[0x69] = 0x02;
813	pci_conf[0x70] = 0x80;
814	pci_conf[0x76] = 0x0c;
815	pci_conf[0x77] = 0x0c;
816	pci_conf[0x78] = 0x02;
817	pci_conf[0x79] = 0x00;
818	pci_conf[0x80] = 0x00;
819	pci_conf[0x82] = 0x02; /* Get rid of the Linux guest "Enabling Passive Release" PCI quirk warning. */
820	pci_conf[0xa0] = 0x08;
821	pci_conf[0xa2] = 0x00;
822	pci_conf[0xa3] = 0x00;
823	pci_conf[0xa4] = 0x00;
824	pci_conf[0xa5] = 0x00;
825	pci_conf[0xa6] = 0x00;
826	pci_conf[0xa7] = 0x00;
827	pci_conf[0xa8] = 0x0f;
828	pci_conf[0xaa] = 0x00;
829	pci_conf[0xab] = 0x00;
830	pci_conf[0xac] = 0x00;
831	pci_conf[0xae] = 0x00;
832	}
833
834	static void pci_config_writel(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t val)
835	{
836	pGlobals->uConfigReg = 0x80000000 \| (uBus << 16) \|
837	(uDevFn << 8) \| addr;
838	pci_data_write(pGlobals, 0, val, 4);
839	}
840
841	static void pci_config_writew(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t val)
842	{
843	pGlobals->uConfigReg = 0x80000000 \| (uBus << 16) \|
844	(uDevFn << 8) \| (addr & ~3);
845	pci_data_write(pGlobals, addr & 3, val, 2);
846	}
847
848	static void pci_config_writeb(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t val)
849	{
850	pGlobals->uConfigReg = 0x80000000 \| (uBus << 16) \|
851	(uDevFn << 8) \| (addr & ~3);
852	pci_data_write(pGlobals, addr & 3, val, 1);
853	}
854
855	static uint32_t pci_config_readl(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr)
856	{
857	pGlobals->uConfigReg = 0x80000000 \| (uBus << 16) \|
858	(uDevFn << 8) \| addr;
859	uint32_t u32Val;
860	int rc = pci_data_read(pGlobals, 0, 4, &u32Val);
861	AssertRC(rc);
862	return u32Val;
863	}
864
865	static uint32_t pci_config_readw(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr)
866	{
867	pGlobals->uConfigReg = 0x80000000 \| (uBus << 16) \|
868	(uDevFn << 8) \| (addr & ~3);
869	uint32_t u32Val;
870	int rc = pci_data_read(pGlobals, addr & 3, 2, &u32Val);
871	AssertRC(rc);
872	return u32Val;
873	}
874
875	static uint32_t pci_config_readb(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr)
876	{
877	pGlobals->uConfigReg = 0x80000000 \| (uBus << 16) \|
878	(uDevFn << 8) \| (addr & ~3);
879	uint32_t u32Val;
880	int rc = pci_data_read(pGlobals, addr & 3, 1, &u32Val);
881	AssertRC(rc);
882	return u32Val;
883	}
884
885	/* host irqs corresponding to PCI irqs A-D */
886	static const uint8_t pci_irqs[4] = { 11, 9, 11, 9 }; /* bird: added const */
887
888	static void pci_set_io_region_addr(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, int region_num, uint32_t addr)
889	{
890	uint32_t ofs;
891
892	if ( region_num == PCI_ROM_SLOT )
893	ofs = 0x30;
894	else
895	ofs = 0x10 + region_num * 4;
896
897	Log(("Set region address: %02x:%02x.%d region %d address=%lld\n",
898	uBus, uDevFn >> 3, uDevFn & 7, region_num, addr));
899
900	/* Write address of the device. */
901	pci_config_writel(pGlobals, uBus, uDevFn, ofs, addr);
902	}
903
904	static void pci_bios_init_device(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint8_t cBridgeDepth, uint8_t *paBridgePositions)
905	{
906	uint32_t *paddr;
907	int i, pin, pic_irq;
908	uint16_t devclass, vendor_id, device_id;
909
910	devclass = pci_config_readw(pGlobals, uBus, uDevFn, PCI_CLASS_DEVICE);
911	vendor_id = pci_config_readw(pGlobals, uBus, uDevFn, PCI_VENDOR_ID);
912	device_id = pci_config_readw(pGlobals, uBus, uDevFn, PCI_DEVICE_ID);
913
914	/* Check if device is present. */
915	if (vendor_id != 0xffff)
916	{
917	switch(devclass)
918	{
919	case 0x0101:
920	if ( (vendor_id == 0x8086)
921	&& (device_id == 0x7010 \|\| device_id == 0x7111 \|\| device_id == 0x269e))
922	{
923	/* PIIX3, PIIX4 or ICH6 IDE */
924	pci_config_writew(pGlobals, uBus, uDevFn, 0x40, 0x8000); /* enable IDE0 */
925	pci_config_writew(pGlobals, uBus, uDevFn, 0x42, 0x8000); /* enable IDE1 */
926	goto default_map;
927	}
928	else
929	{
930	/* IDE: we map it as in ISA mode */
931	pci_set_io_region_addr(pGlobals, uBus, uDevFn, 0, 0x1f0);
932	pci_set_io_region_addr(pGlobals, uBus, uDevFn, 1, 0x3f4);
933	pci_set_io_region_addr(pGlobals, uBus, uDevFn, 2, 0x170);
934	pci_set_io_region_addr(pGlobals, uBus, uDevFn, 3, 0x374);
935	pci_config_writeb(pGlobals, uBus, uDevFn, PCI_COMMAND,
936	pci_config_readb(pGlobals, uBus, uDevFn, PCI_COMMAND)
937	\| PCI_COMMAND_IOACCESS);
938	}
939	break;
940	case 0x0300:
941	if (vendor_id != 0x80ee)
942	goto default_map;
943	/* VGA: map frame buffer to default Bochs VBE address */
944	pci_set_io_region_addr(pGlobals, uBus, uDevFn, 0, 0xE0000000);
945	/*
946	* Legacy VGA I/O ports are implicitly decoded by a VGA class device. But
947	* only the framebuffer (i.e., a memory region) is explicitly registered via
948	* pci_set_io_region_addr, so don't forget to enable I/O decoding.
949	*/
950	pci_config_writeb(pGlobals, uBus, uDevFn, PCI_COMMAND,
951	pci_config_readb(pGlobals, uBus, uDevFn, PCI_COMMAND)
952	\| PCI_COMMAND_IOACCESS \| PCI_COMMAND_MEMACCESS);
953	break;
954	case 0x0800:
955	/* PIC */
956	vendor_id = pci_config_readw(pGlobals, uBus, uDevFn, PCI_VENDOR_ID);
957	device_id = pci_config_readw(pGlobals, uBus, uDevFn, PCI_DEVICE_ID);
958	if (vendor_id == 0x1014)
959	{
960	/* IBM */
961	if (device_id == 0x0046 \|\| device_id == 0xFFFF)
962	{
963	/* MPIC & MPIC2 */
964	pci_set_io_region_addr(pGlobals, uBus, uDevFn, 0, 0x80800000 + 0x00040000);
965	pci_config_writeb(pGlobals, uBus, uDevFn, PCI_COMMAND,
966	pci_config_readb(pGlobals, uBus, uDevFn, PCI_COMMAND)
967	\| PCI_COMMAND_MEMACCESS);
968	}
969	}
970	break;
971	case 0xff00:
972	if ( (vendor_id == 0x0106b)
973	&& (device_id == 0x0017 \|\| device_id == 0x0022))
974	{
975	/* macio bridge */
976	pci_set_io_region_addr(pGlobals, uBus, uDevFn, 0, 0x80800000);
977	pci_config_writeb(pGlobals, uBus, uDevFn, PCI_COMMAND,
978	pci_config_readb(pGlobals, uBus, uDevFn, PCI_COMMAND)
979	\| PCI_COMMAND_MEMACCESS);
980	}
981	break;
982	case 0x0604:
983	{
984	/* Init PCI-to-PCI bridge. */
985	pci_config_writeb(pGlobals, uBus, uDevFn, VBOX_PCI_PRIMARY_BUS, uBus);
986
987	AssertMsg(pGlobals->uBus < 255, ("Too many bridges on the bus\n"));
988	pGlobals->uBus++;
989	pci_config_writeb(pGlobals, uBus, uDevFn, VBOX_PCI_SECONDARY_BUS, pGlobals->uBus);
990	pci_config_writeb(pGlobals, uBus, uDevFn, VBOX_PCI_SUBORDINATE_BUS, 0xff); /* Temporary until we know how many other bridges are behind this one. */
991
992	/* Add position of this bridge into the array. */
993	paBridgePositions[cBridgeDepth+1] = (uDevFn >> 3);
994
995	/*
996	* The I/O range for the bridge must be aligned to a 4KB boundary.
997	* This does not change anything really as the access to the device is not going
998	* through the bridge but we want to be compliant to the spec.
999	*/
1000	if ((pGlobals->pci_bios_io_addr % 4096) != 0)
1001	pGlobals->pci_bios_io_addr = RT_ALIGN_32(pGlobals->pci_bios_io_addr, 4*1024);
1002	Log(("%s: Aligned I/O start address. New address %#x\n", __FUNCTION__, pGlobals->pci_bios_io_addr));
1003	pci_config_writeb(pGlobals, uBus, uDevFn, VBOX_PCI_IO_BASE, (pGlobals->pci_bios_io_addr >> 8) & 0xf0);
1004
1005	/* The MMIO range for the bridge must be aligned to a 1MB boundary. */
1006	if ((pGlobals->pci_bios_mem_addr % (1024 * 1024)) != 0)
1007	pGlobals->pci_bios_mem_addr = RT_ALIGN_32(pGlobals->pci_bios_mem_addr, 1024*1024);
1008	Log(("%s: Aligned MMIO start address. New address %#x\n", __FUNCTION__, pGlobals->pci_bios_mem_addr));
1009	pci_config_writew(pGlobals, uBus, uDevFn, VBOX_PCI_MEMORY_BASE, (pGlobals->pci_bios_mem_addr >> 16) & UINT32_C(0xffff0));
1010
1011	/* Save values to compare later to. */
1012	uint32_t u32IoAddressBase = pGlobals->pci_bios_io_addr;
1013	uint32_t u32MMIOAddressBase = pGlobals->pci_bios_mem_addr;
1014
1015	/* Init devices behind the bridge and possibly other bridges as well. */
1016	for (int iDev = 0; iDev <= 255; iDev++)
1017	pci_bios_init_device(pGlobals, uBus + 1, iDev, cBridgeDepth + 1, paBridgePositions);
1018
1019	/* The number of bridges behind the this one is now available. */
1020	pci_config_writeb(pGlobals, uBus, uDevFn, VBOX_PCI_SUBORDINATE_BUS, pGlobals->uBus);
1021
1022	/*
1023	* Set I/O limit register. If there is no device with I/O space behind the bridge
1024	* we set a lower value than in the base register.
1025	* The result with a real bridge is that no I/O transactions are passed to the secondary
1026	* interface. Again this doesn't really matter here but we want to be compliant to the spec.
1027	*/
1028	if ((u32IoAddressBase != pGlobals->pci_bios_io_addr) && ((pGlobals->pci_bios_io_addr % 4096) != 0))
1029	{
1030	/* The upper boundary must be one byte less than a 4KB boundary. */
1031	pGlobals->pci_bios_io_addr = RT_ALIGN_32(pGlobals->pci_bios_io_addr, 4*1024);
1032	}
1033	pci_config_writeb(pGlobals, uBus, uDevFn, VBOX_PCI_IO_LIMIT, ((pGlobals->pci_bios_io_addr >> 8) & 0xf0) - 1);
1034
1035	/* Same with the MMIO limit register but with 1MB boundary here. */
1036	if ((u32MMIOAddressBase != pGlobals->pci_bios_mem_addr) && ((pGlobals->pci_bios_mem_addr % (1024 * 1024)) != 0))
1037	{
1038	/* The upper boundary must be one byte less than a 1MB boundary. */
1039	pGlobals->pci_bios_mem_addr = RT_ALIGN_32(pGlobals->pci_bios_mem_addr, 1024*1024);
1040	}
1041	pci_config_writew(pGlobals, uBus, uDevFn, VBOX_PCI_MEMORY_LIMIT, ((pGlobals->pci_bios_mem_addr >> 16) & UINT32_C(0xfff0)) - 1);
1042
1043	/*
1044	* Set the prefetch base and limit registers. We currently have no device with a prefetchable region
1045	* which may be behind a bridge. That's why it is unconditionally disabled here atm by writing a higher value into
1046	* the base register than in the limit register.
1047	*/
1048	pci_config_writew(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_MEMORY_BASE, 0xfff0);
1049	pci_config_writew(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_MEMORY_LIMIT, 0x0);
1050	pci_config_writel(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_BASE_UPPER32, 0x00);
1051	pci_config_writel(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_LIMIT_UPPER32, 0x00);
1052	break;
1053	}
1054	default:
1055	default_map:
1056	{
1057	/* default memory mappings */
1058	bool fActiveMemRegion = false;
1059	bool fActiveIORegion = false;
1060	/*
1061	* PCI_NUM_REGIONS is 7 because of the rom region but there are only 6 base address register defined by the PCI spec.
1062	* Leaving only PCI_NUM_REGIONS would cause reading another and enabling a memory region which does not exist.
1063	*/
1064	for(i = 0; i < (PCI_NUM_REGIONS-1); i++)
1065	{
1066	uint32_t u32Size;
1067	uint8_t u8RessourceType;
1068	uint32_t u32Address = 0x10 + i * 4;
1069
1070	/* Calculate size. */
1071	u8RessourceType = pci_config_readb(pGlobals, uBus, uDevFn, u32Address);
1072	pci_config_writel(pGlobals, uBus, uDevFn, u32Address, UINT32_C(0xffffffff));
1073	u32Size = pci_config_readl(pGlobals, uBus, uDevFn, u32Address);
1074	bool fIsPio = ((u8RessourceType & PCI_COMMAND_IOACCESS) == PCI_COMMAND_IOACCESS);
1075	/* Clear resource information depending on resource type. */
1076	if (fIsPio) /* I/O */
1077	u32Size &= ~(0x01);
1078	else /* MMIO */
1079	u32Size &= ~(0x0f);
1080
1081	/*
1082	* Invert all bits and add 1 to get size of the region.
1083	* (From PCI implementation note)
1084	*/
1085	if (fIsPio && (u32Size & UINT32_C(0xffff0000)) == 0)
1086	u32Size = (~(u32Size \| UINT32_C(0xffff0000))) + 1;
1087	else
1088	u32Size = (~u32Size) + 1;
1089
1090	Log2(("%s: Size of region %u for device %d on bus %d is %u\n", __FUNCTION__, i, uDevFn, uBus, u32Size));
1091
1092	if (u32Size)
1093	{
1094	if (fIsPio)
1095	paddr = &pGlobals->pci_bios_io_addr;
1096	else
1097	paddr = &pGlobals->pci_bios_mem_addr;
1098	uint32_t uNew = *paddr;
1099	uNew = (uNew + u32Size - 1) & ~(u32Size - 1);
1100	if (fIsPio)
1101	uNew &= UINT32_C(0xffff);
1102	/* Unconditionally exclude I/O-APIC/HPET/ROM. Pessimistic, but better than causing a mess. */
1103	if (!uNew \|\| (uNew <= UINT32_C(0xffffffff) && uNew + u32Size - 1 >= UINT32_C(0xfec00000)))
1104	{
1105	LogRel(("PCI: no space left for BAR%u of device %u/%u/%u (vendor=%#06x device=%#06x)\n",
1106	i, uBus, uDevFn >> 3, uDevFn & 7, vendor_id, device_id)); /** @todo make this a VM start failure later. */
1107	/* Undo the mapping mess caused by the size probing. */
1108	pci_config_writel(pGlobals, uBus, uDevFn, u32Address, UINT32_C(0));
1109	}
1110	else
1111	{
1112	Log(("%s: Start address of %s region %u is %#x\n", __FUNCTION__, (fIsPio ? "I/O" : "MMIO"), i, uNew));
1113	pci_set_io_region_addr(pGlobals, uBus, uDevFn, i, uNew);
1114	if (fIsPio)
1115	fActiveIORegion = true;
1116	else
1117	fActiveMemRegion = true;
1118	*paddr = uNew + u32Size;
1119	Log2(("%s: New address is %#x\n", __FUNCTION__, *paddr));
1120	}
1121	}
1122	}
1123
1124	/* Update the command word appropriately. */
1125	pci_config_writeb(pGlobals, uBus, uDevFn, PCI_COMMAND,
1126	pci_config_readb(pGlobals, uBus, uDevFn, PCI_COMMAND)
1127	\| (fActiveMemRegion ? PCI_COMMAND_MEMACCESS : 0)
1128	\| (fActiveIORegion ? PCI_COMMAND_IOACCESS : 0));
1129
1130	break;
1131	}
1132	}
1133
1134	/* map the interrupt */
1135	pin = pci_config_readb(pGlobals, uBus, uDevFn, PCI_INTERRUPT_PIN);
1136	if (pin != 0)
1137	{
1138	uint8_t uBridgeDevFn = uDevFn;
1139	pin--;
1140
1141	/* We need to go up to the host bus to see which irq this device will assert there. */
1142	while (cBridgeDepth != 0)
1143	{
1144	/* Get the pin the device would assert on the bridge. */
1145	pin = ((uBridgeDevFn >> 3) + pin) & 3;
1146	uBridgeDevFn = paBridgePositions[cBridgeDepth];
1147	cBridgeDepth--;
1148	}
1149
1150	pin = pci_slot_get_pirq(uDevFn, pin);
1151	pic_irq = pci_irqs[pin];
1152	pci_config_writeb(pGlobals, uBus, uDevFn, PCI_INTERRUPT_LINE, pic_irq);
1153	}
1154	}
1155	}
1156
1157	#endif /* IN_RING3 */
1158
1159
1160	/* -=-=-=-=-=- I/O ports -=-=-=-=-=- */
1161
1162	/**
1163	* @callback_method_impl{FNIOMIOPORTOUT, PCI address}
1164	*/
1165	PDMBOTHCBDECL(int) pciIOPortAddressWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1166	{
1167	Log(("pciIOPortAddressWrite: Port=%#x u32=%#x cb=%d\n", Port, u32, cb));
1168	RT_NOREF2(Port, pvUser);
1169	if (cb == 4)
1170	{
1171	PPCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
1172	PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_WRITE);
1173	pThis->uConfigReg = u32 & ~3; /* Bits 0-1 are reserved and we silently clear them */
1174	PCI_UNLOCK(pDevIns);
1175	}
1176	/* else: 440FX does "pass through to the bus" for other writes, what ever that means.
1177	* Linux probes for cmd640 using byte writes/reads during ide init. We'll just ignore it. */
1178	return VINF_SUCCESS;
1179	}
1180
1181
1182	/**
1183	* @callback_method_impl{FNIOMIOPORTIN, PCI address}
1184	*/
1185	PDMBOTHCBDECL(int) pciIOPortAddressRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
1186	{
1187	RT_NOREF2(Port, pvUser);
1188	if (cb == 4)
1189	{
1190	PPCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
1191	PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_READ);
1192	*pu32 = pThis->uConfigReg;
1193	PCI_UNLOCK(pDevIns);
1194	Log(("pciIOPortAddressRead: Port=%#x cb=%d -> %#x\n", Port, cb, *pu32));
1195	return VINF_SUCCESS;
1196	}
1197	/* else: 440FX does "pass through to the bus" for other writes, what ever that means.
1198	* Linux probes for cmd640 using byte writes/reads during ide init. We'll just ignore it. */
1199	Log(("pciIOPortAddressRead: Port=%#x cb=%d VERR_IOM_IOPORT_UNUSED\n", Port, cb));
1200	return VERR_IOM_IOPORT_UNUSED;
1201	}
1202
1203
1204	/**
1205	* @callback_method_impl{FNIOMIOPORTOUT, PCI data}
1206	*/
1207	PDMBOTHCBDECL(int) pciIOPortDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1208	{
1209	Log(("pciIOPortDataWrite: Port=%#x u32=%#x cb=%d\n", Port, u32, cb));
1210	NOREF(pvUser);
1211	int rc = VINF_SUCCESS;
1212	if (!(Port % cb))
1213	{
1214	PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_WRITE);
1215	rc = pci_data_write(PDMINS_2_DATA(pDevIns, PPCIGLOBALS), Port, u32, cb);
1216	PCI_UNLOCK(pDevIns);
1217	}
1218	else
1219	AssertMsgFailed(("Write to port %#x u32=%#x cb=%d\n", Port, u32, cb));
1220	return rc;
1221	}
1222
1223
1224	/**
1225	* @callback_method_impl{FNIOMIOPORTIN, PCI data}
1226	*/
1227	PDMBOTHCBDECL(int) pciIOPortDataRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
1228	{
1229	NOREF(pvUser);
1230	if (!(Port % cb))
1231	{
1232	PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_READ);
1233	int rc = pci_data_read(PDMINS_2_DATA(pDevIns, PPCIGLOBALS), Port, cb, pu32);
1234	PCI_UNLOCK(pDevIns);
1235	Log(("pciIOPortDataRead: Port=%#x cb=%#x -> %#x (%Rrc)\n", Port, cb, *pu32, rc));
1236	return rc;
1237	}
1238	AssertMsgFailed(("Read from port %#x cb=%d\n", Port, cb));
1239	return VERR_IOM_IOPORT_UNUSED;
1240	}
1241
1242	#ifdef IN_RING3
1243
1244	/*
1245	* Include code we share with the other PCI bus implementation.
1246	*
1247	* Note! No #ifdefs, use instant data booleans/flags/whatever. Goal is to
1248	* completely merge these files! File #1 contains code we write, where
1249	* as a possible file #2 contains external code if there's any left.
1250	*/
1251	typedef PPCIBUS PPCIMERGEDBUS;
1252	# define pciR3UnmergedConfigReadDev pci_default_read_config
1253	# define pciR3UnmergedConfigWriteDev pci_default_write_config
1254	# include "DevPciMerge1.cpp.h"
1255
1256
1257	/* -=-=-=-=-=- Saved state -=-=-=-=-=- */
1258
1259	/**
1260	* Common worker for pciR3SaveExec and pcibridgeR3SaveExec.
1261	*
1262	* @returns VBox status code.
1263	* @param pBus The bus to save.
1264	* @param pSSM The saved state handle.
1265	*/
1266	static int pciR3CommonSaveExec(PPCIBUS pBus, PSSMHANDLE pSSM)
1267	{
1268	/*
1269	* Iterate thru all the devices.
1270	*/
1271	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->devices); i++)
1272	{
1273	PPCIDEVICE pDev = pBus->devices[i];
1274	if (pDev)
1275	{
1276	SSMR3PutU32(pSSM, i);
1277	SSMR3PutMem(pSSM, pDev->config, sizeof(pDev->config));
1278
1279	int rc = SSMR3PutS32(pSSM, pDev->Int.s.uIrqPinState);
1280	if (RT_FAILURE(rc))
1281	return rc;
1282	}
1283	}
1284	return SSMR3PutU32(pSSM, UINT32_MAX); /* terminator */
1285	}
1286
1287
1288	/**
1289	* @callback_method_impl{FNSSMDEVSAVEEXEC}
1290	*/
1291	static DECLCALLBACK(int) pciR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
1292	{
1293	uint32_t i;
1294	PPCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
1295
1296	/*
1297	* Bus state data.
1298	*/
1299	SSMR3PutU32(pSSM, pThis->uConfigReg);
1300	SSMR3PutBool(pSSM, pThis->fUseIoApic);
1301
1302	/*
1303	* Save IRQ states.
1304	*/
1305	for (i = 0; i < PCI_IRQ_PINS; i++)
1306	SSMR3PutU32(pSSM, pThis->pci_irq_levels[i]);
1307	for (i = 0; i < PCI_APIC_IRQ_PINS; i++)
1308	SSMR3PutU32(pSSM, pThis->pci_apic_irq_levels[i]);
1309
1310	SSMR3PutU32(pSSM, pThis->acpi_irq_level);
1311	SSMR3PutS32(pSSM, pThis->acpi_irq);
1312
1313	SSMR3PutU32(pSSM, UINT32_MAX); /* separator */
1314
1315	/*
1316	* Join paths with pcibridgeR3SaveExec.
1317	*/
1318	return pciR3CommonSaveExec(&pThis->PciBus, pSSM);
1319	}
1320
1321
1322	/**
1323	* Common routine for restoring the config registers of a PCI device.
1324	*
1325	* @param pDev The PCI device.
1326	* @param pbSrcConfig The configuration register values to be loaded.
1327	* @param fIsBridge Whether this is a bridge device or not.
1328	*/
1329	static void pciR3CommonRestoreConfig(PPCIDEVICE pDev, uint8_t const *pbSrcConfig, bool fIsBridge)
1330	{
1331	/*
1332	* This table defines the fields for normal devices and bridge devices, and
1333	* the order in which they need to be restored.
1334	*/
1335	static const struct PciField
1336	{
1337	uint8_t off;
1338	uint8_t cb;
1339	uint8_t fWritable;
1340	uint8_t fBridge;
1341	const char *pszName;
1342	} s_aFields[] =
1343	{
1344	/* off,cb,fW,fB, pszName */
1345	{ 0x00, 2, 0, 3, "VENDOR_ID" },
1346	{ 0x02, 2, 0, 3, "DEVICE_ID" },
1347	{ 0x06, 2, 1, 3, "STATUS" },
1348	{ 0x08, 1, 0, 3, "REVISION_ID" },
1349	{ 0x09, 1, 0, 3, "CLASS_PROG" },
1350	{ 0x0a, 1, 0, 3, "CLASS_SUB" },
1351	{ 0x0b, 1, 0, 3, "CLASS_BASE" },
1352	{ 0x0c, 1, 1, 3, "CACHE_LINE_SIZE" },
1353	{ 0x0d, 1, 1, 3, "LATENCY_TIMER" },
1354	{ 0x0e, 1, 0, 3, "HEADER_TYPE" },
1355	{ 0x0f, 1, 1, 3, "BIST" },
1356	{ 0x10, 4, 1, 3, "BASE_ADDRESS_0" },
1357	{ 0x14, 4, 1, 3, "BASE_ADDRESS_1" },
1358	{ 0x18, 4, 1, 1, "BASE_ADDRESS_2" },
1359	{ 0x18, 1, 1, 2, "PRIMARY_BUS" }, // fWritable = ??
1360	{ 0x19, 1, 1, 2, "SECONDARY_BUS" }, // fWritable = ??
1361	{ 0x1a, 1, 1, 2, "SUBORDINATE_BUS" }, // fWritable = ??
1362	{ 0x1b, 1, 1, 2, "SEC_LATENCY_TIMER" }, // fWritable = ??
1363	{ 0x1c, 4, 1, 1, "BASE_ADDRESS_3" },
1364	{ 0x1c, 1, 1, 2, "IO_BASE" }, // fWritable = ??
1365	{ 0x1d, 1, 1, 2, "IO_LIMIT" }, // fWritable = ??
1366	{ 0x1e, 2, 1, 2, "SEC_STATUS" }, // fWritable = ??
1367	{ 0x20, 4, 1, 1, "BASE_ADDRESS_4" },
1368	{ 0x20, 2, 1, 2, "MEMORY_BASE" }, // fWritable = ??
1369	{ 0x22, 2, 1, 2, "MEMORY_LIMIT" }, // fWritable = ??
1370	{ 0x24, 4, 1, 1, "BASE_ADDRESS_5" },
1371	{ 0x24, 2, 1, 2, "PREF_MEMORY_BASE" }, // fWritable = ??
1372	{ 0x26, 2, 1, 2, "PREF_MEMORY_LIMIT" }, // fWritable = ??
1373	{ 0x28, 4, 1, 1, "CARDBUS_CIS" }, // fWritable = ??
1374	{ 0x28, 4, 1, 2, "PREF_BASE_UPPER32" }, // fWritable = ??
1375	{ 0x2c, 2, 0, 1, "SUBSYSTEM_VENDOR_ID" },// fWritable = !?
1376	{ 0x2c, 4, 1, 2, "PREF_LIMIT_UPPER32" },// fWritable = ??
1377	{ 0x2e, 2, 0, 1, "SUBSYSTEM_ID" }, // fWritable = !?
1378	{ 0x30, 4, 1, 1, "ROM_ADDRESS" }, // fWritable = ?!
1379	{ 0x30, 2, 1, 2, "IO_BASE_UPPER16" }, // fWritable = ?!
1380	{ 0x32, 2, 1, 2, "IO_LIMIT_UPPER16" }, // fWritable = ?!
1381	{ 0x34, 4, 0, 3, "CAPABILITY_LIST" }, // fWritable = !? cb=!?
1382	{ 0x38, 4, 1, 1, "RESERVED_38" }, // ???
1383	{ 0x38, 4, 1, 2, "ROM_ADDRESS_BR" }, // fWritable = !? cb=!? fBridge=!?
1384	{ 0x3c, 1, 1, 3, "INTERRUPT_LINE" }, // fBridge=??
1385	{ 0x3d, 1, 0, 3, "INTERRUPT_PIN" }, // fBridge=??
1386	{ 0x3e, 1, 0, 1, "MIN_GNT" },
1387	{ 0x3e, 2, 1, 2, "BRIDGE_CONTROL" }, // fWritable = !?
1388	{ 0x3f, 1, 0, 1, "MAX_LAT" },
1389	/* The COMMAND register must come last as it requires the ADDRESS
1390	registers to be restored before we pretent to change it from 0 to
1391	whatever value the guest assigned it. */
1392	{ 0x04, 2, 1, 3, "COMMAND" },
1393	};
1394
1395	#ifdef RT_STRICT
1396	/* Check that we've got full register coverage. */
1397	uint32_t bmDevice[0x40 / 32];
1398	uint32_t bmBridge[0x40 / 32];
1399	RT_ZERO(bmDevice);
1400	RT_ZERO(bmBridge);
1401	for (uint32_t i = 0; i < RT_ELEMENTS(s_aFields); i++)
1402	{
1403	uint8_t off = s_aFields[i].off;
1404	uint8_t cb = s_aFields[i].cb;
1405	uint8_t f = s_aFields[i].fBridge;
1406	while (cb-- > 0)
1407	{
1408	if (f & 1) AssertMsg(!ASMBitTest(bmDevice, off), ("%#x\n", off));
1409	if (f & 2) AssertMsg(!ASMBitTest(bmBridge, off), ("%#x\n", off));
1410	if (f & 1) ASMBitSet(bmDevice, off);
1411	if (f & 2) ASMBitSet(bmBridge, off);
1412	off++;
1413	}
1414	}
1415	for (uint32_t off = 0; off < 0x40; off++)
1416	{
1417	AssertMsg(ASMBitTest(bmDevice, off), ("%#x\n", off));
1418	AssertMsg(ASMBitTest(bmBridge, off), ("%#x\n", off));
1419	}
1420	#endif
1421
1422	/*
1423	* Loop thru the fields covering the 64 bytes of standard registers.
1424	*/
1425	uint8_t const fBridge = fIsBridge ? 2 : 1;
1426	uint8_t *pbDstConfig = &pDev->config[0];
1427	for (uint32_t i = 0; i < RT_ELEMENTS(s_aFields); i++)
1428	if (s_aFields[i].fBridge & fBridge)
1429	{
1430	uint8_t const off = s_aFields[i].off;
1431	uint8_t const cb = s_aFields[i].cb;
1432	uint32_t u32Src;
1433	uint32_t u32Dst;
1434	switch (cb)
1435	{
1436	case 1:
1437	u32Src = pbSrcConfig[off];
1438	u32Dst = pbDstConfig[off];
1439	break;
1440	case 2:
1441	u32Src = (uint16_t const )&pbSrcConfig[off];
1442	u32Dst = (uint16_t const )&pbDstConfig[off];
1443	break;
1444	case 4:
1445	u32Src = (uint32_t const )&pbSrcConfig[off];
1446	u32Dst = (uint32_t const )&pbDstConfig[off];
1447	break;
1448	default:
1449	AssertFailed();
1450	continue;
1451	}
1452
1453	if ( u32Src != u32Dst
1454	\|\| off == VBOX_PCI_COMMAND)
1455	{
1456	if (u32Src != u32Dst)
1457	{
1458	if (!s_aFields[i].fWritable)
1459	LogRel(("PCI: %8s/%u: %2u-bit field %s: %x -> %x - !READ ONLY!\n",
1460	pDev->name, pDev->pDevIns->iInstance, cb*8, s_aFields[i].pszName, u32Dst, u32Src));
1461	else
1462	LogRel(("PCI: %8s/%u: %2u-bit field %s: %x -> %x\n",
1463	pDev->name, pDev->pDevIns->iInstance, cb*8, s_aFields[i].pszName, u32Dst, u32Src));
1464	}
1465	if (off == VBOX_PCI_COMMAND)
1466	PCIDevSetCommand(pDev, 0); /* For remapping, see pciR3CommonLoadExec. */
1467	pDev->Int.s.pfnConfigWrite(pDev->Int.s.CTX_SUFF(pDevIns), pDev, off, u32Src, cb);
1468	}
1469	}
1470
1471	/*
1472	* The device dependent registers.
1473	*
1474	* We will not use ConfigWrite here as we have no clue about the size
1475	* of the registers, so the device is responsible for correctly
1476	* restoring functionality governed by these registers.
1477	*/
1478	for (uint32_t off = 0x40; off < sizeof(pDev->config); off++)
1479	if (pbDstConfig[off] != pbSrcConfig[off])
1480	{
1481	LogRel(("PCI: %8s/%u: register %02x: %02x -> %02x\n",
1482	pDev->name, pDev->pDevIns->iInstance, off, pbDstConfig[off], pbSrcConfig[off])); /** @todo make this Log() later. */
1483	pbDstConfig[off] = pbSrcConfig[off];
1484	}
1485	}
1486
1487
1488	/**
1489	* Common worker for pciR3LoadExec and pcibridgeR3LoadExec.
1490	*
1491	* @returns VBox status code.
1492	* @param pBus The bus which data is being loaded.
1493	* @param pSSM The saved state handle.
1494	* @param uVersion The data version.
1495	* @param uPass The pass.
1496	*/
1497	static DECLCALLBACK(int) pciR3CommonLoadExec(PPCIBUS pBus, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1498	{
1499	uint32_t u32;
1500	uint32_t i;
1501	int rc;
1502
1503	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
1504
1505	/*
1506	* Iterate thru all the devices and write 0 to the COMMAND register so
1507	* that all the memory is unmapped before we start restoring the saved
1508	* mapping locations.
1509	*
1510	* The register value is restored afterwards so we can do proper
1511	* LogRels in pciR3CommonRestoreConfig.
1512	*/
1513	for (i = 0; i < RT_ELEMENTS(pBus->devices); i++)
1514	{
1515	PPCIDEVICE pDev = pBus->devices[i];
1516	if (pDev)
1517	{
1518	uint16_t u16 = PCIDevGetCommand(pDev);
1519	pDev->Int.s.pfnConfigWrite(pDev->Int.s.CTX_SUFF(pDevIns), pDev, VBOX_PCI_COMMAND, 0, 2);
1520	PCIDevSetCommand(pDev, u16);
1521	Assert(PCIDevGetCommand(pDev) == u16);
1522	}
1523	}
1524
1525	/*
1526	* Iterate all the devices.
1527	*/
1528	for (i = 0;; i++)
1529	{
1530	PCIDEVICE DevTmp;
1531	PPCIDEVICE pDev;
1532
1533	/* index / terminator */
1534	rc = SSMR3GetU32(pSSM, &u32);
1535	if (RT_FAILURE(rc))
1536	return rc;
1537	if (u32 == (uint32_t)~0)
1538	break;
1539	if ( u32 >= RT_ELEMENTS(pBus->devices)
1540	\|\| u32 < i)
1541	{
1542	AssertMsgFailed(("u32=%#x i=%#x\n", u32, i));
1543	return rc;
1544	}
1545
1546	/* skip forward to the device checking that no new devices are present. */
1547	for (; i < u32; i++)
1548	{
1549	if (pBus->devices[i])
1550	{
1551	LogRel(("PCI: New device in slot %#x, %s (vendor=%#06x device=%#06x)\n", i, pBus->devices[i]->name,
1552	PCIDevGetVendorId(pBus->devices[i]), PCIDevGetDeviceId(pBus->devices[i])));
1553	if (SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT)
1554	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("New device in slot %#x, %s (vendor=%#06x device=%#06x)"),
1555	i, pBus->devices[i]->name, PCIDevGetVendorId(pBus->devices[i]), PCIDevGetDeviceId(pBus->devices[i]));
1556	}
1557	}
1558
1559	/* get the data */
1560	DevTmp.Int.s.uIrqPinState = ~0; /* Invalid value in case we have an older saved state to force a state change in pciSetIrq. */
1561	SSMR3GetMem(pSSM, DevTmp.config, sizeof(DevTmp.config));
1562	if (uVersion < 3)
1563	{
1564	int32_t i32Temp;
1565	/* Irq value not needed anymore. */
1566	rc = SSMR3GetS32(pSSM, &i32Temp);
1567	if (RT_FAILURE(rc))
1568	return rc;
1569	}
1570	else
1571	{
1572	rc = SSMR3GetS32(pSSM, &DevTmp.Int.s.uIrqPinState);
1573	if (RT_FAILURE(rc))
1574	return rc;
1575	}
1576
1577	/* check that it's still around. */
1578	pDev = pBus->devices[i];
1579	if (!pDev)
1580	{
1581	LogRel(("PCI: Device in slot %#x has been removed! vendor=%#06x device=%#06x\n", i,
1582	PCIDevGetVendorId(&DevTmp), PCIDevGetDeviceId(&DevTmp)));
1583	if (SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT)
1584	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Device in slot %#x has been removed! vendor=%#06x device=%#06x"),
1585	i, PCIDevGetVendorId(&DevTmp), PCIDevGetDeviceId(&DevTmp));
1586	continue;
1587	}
1588
1589	/* match the vendor id assuming that this will never be changed. */
1590	if ( DevTmp.config[0] != pDev->config[0]
1591	\|\| DevTmp.config[1] != pDev->config[1])
1592	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Device in slot %#x (%s) vendor id mismatch! saved=%.4Rhxs current=%.4Rhxs"),
1593	i, pDev->name, DevTmp.config, pDev->config);
1594
1595	/* commit the loaded device config. */
1596	pciR3CommonRestoreConfig(pDev, &DevTmp.config[0], false ); /** @todo fix bridge fun! */
1597
1598	pDev->Int.s.uIrqPinState = DevTmp.Int.s.uIrqPinState;
1599	}
1600
1601	return VINF_SUCCESS;
1602	}
1603
1604
1605	/**
1606	* @callback_method_impl{FNSSMDEVLOADEXEC}
1607	*/
1608	static DECLCALLBACK(int) pciR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1609	{
1610	PPCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
1611	PPCIBUS pBus = &pThis->PciBus;
1612	uint32_t u32;
1613	int rc;
1614
1615	/*
1616	* Check the version.
1617	*/
1618	if (uVersion > VBOX_PCI_SAVED_STATE_VERSION)
1619	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1620	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
1621
1622	/*
1623	* Bus state data.
1624	*/
1625	SSMR3GetU32(pSSM, &pThis->uConfigReg);
1626	if (uVersion > 1)
1627	SSMR3GetBool(pSSM, &pThis->fUseIoApic);
1628
1629	/* Load IRQ states. */
1630	if (uVersion > 2)
1631	{
1632	for (uint8_t i = 0; i < PCI_IRQ_PINS; i++)
1633	SSMR3GetU32(pSSM, (uint32_t *)&pThis->pci_irq_levels[i]);
1634	for (uint8_t i = 0; i < PCI_APIC_IRQ_PINS; i++)
1635	SSMR3GetU32(pSSM, (uint32_t *)&pThis->pci_apic_irq_levels[i]);
1636
1637	SSMR3GetU32(pSSM, &pThis->acpi_irq_level);
1638	SSMR3GetS32(pSSM, &pThis->acpi_irq);
1639	}
1640
1641	/* separator */
1642	rc = SSMR3GetU32(pSSM, &u32);
1643	if (RT_FAILURE(rc))
1644	return rc;
1645	if (u32 != (uint32_t)~0)
1646	AssertMsgFailedReturn(("u32=%#x\n", u32), rc);
1647
1648	/*
1649	* The devices.
1650	*/
1651	return pciR3CommonLoadExec(pBus, pSSM, uVersion, uPass);
1652	}
1653
1654
1655	/* -=-=-=-=-=- PCI Bus Interface Methods (PDMPCIBUSREG) -=-=-=-=-=- */
1656
1657
1658	/**
1659	* @interface_method_impl{PDMPCIBUSREG,pfnIORegionRegisterR3}
1660	*/
1661	static DECLCALLBACK(int) pciR3CommonIORegionRegister(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iRegion, RTGCPHYS cbRegion,
1662	PCIADDRESSSPACE enmType, PFNPCIIOREGIONMAP pfnCallback)
1663	{
1664	NOREF(pDevIns);
1665
1666	/*
1667	* Validate.
1668	*/
1669	AssertMsgReturn( enmType == PCI_ADDRESS_SPACE_MEM
1670	\|\| enmType == PCI_ADDRESS_SPACE_IO
1671	\|\| enmType == PCI_ADDRESS_SPACE_MEM_PREFETCH,
1672	("Invalid enmType=%#x? Or was this a bitmask after all...\n", enmType),
1673	VERR_INVALID_PARAMETER);
1674	AssertMsgReturn((unsigned)iRegion < PCI_NUM_REGIONS,
1675	("Invalid iRegion=%d PCI_NUM_REGIONS=%d\n", iRegion, PCI_NUM_REGIONS),
1676	VERR_INVALID_PARAMETER);
1677	int iLastSet = ASMBitLastSetU64(cbRegion);
1678	AssertMsgReturn( iLastSet != 0
1679	&& RT_BIT_64(iLastSet - 1) == cbRegion,
1680	("Invalid cbRegion=%RGp iLastSet=%#x (not a power of 2 or 0)\n", cbRegion, iLastSet),
1681	VERR_INVALID_PARAMETER);
1682
1683	/*
1684	* Register the I/O region.
1685	*/
1686	PPCIIOREGION pRegion = &pPciDev->Int.s.aIORegions[iRegion];
1687	pRegion->addr = ~0U;
1688	pRegion->size = cbRegion;
1689	pRegion->type = enmType;
1690	pRegion->map_func = pfnCallback;
1691
1692	/* Set type in the config space. */
1693	AssertCompile(PCI_ADDRESS_SPACE_MEM == 0);
1694	AssertCompile(PCI_ADDRESS_SPACE_IO == 1);
1695	AssertCompile(PCI_ADDRESS_SPACE_MEM_PREFETCH == RT_BIT_32(3));
1696	PCIDevSetDWord(pPciDev, 0x10 + iRegion * 4, enmType);
1697
1698	return VINF_SUCCESS;
1699	}
1700
1701
1702	/**
1703	* @interface_method_impl{PDMPCIBUSREG,pfnSetConfigCallbacksR3}
1704	*/
1705	static DECLCALLBACK(void)
1706	pciR3CommonSetConfigCallbacks(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PFNPCICONFIGREAD pfnRead, PPFNPCICONFIGREAD ppfnReadOld,
1707	PFNPCICONFIGWRITE pfnWrite, PPFNPCICONFIGWRITE ppfnWriteOld)
1708	{
1709	NOREF(pDevIns);
1710
1711	if (ppfnReadOld)
1712	*ppfnReadOld = pPciDev->Int.s.pfnConfigRead;
1713	pPciDev->Int.s.pfnConfigRead = pfnRead;
1714
1715	if (ppfnWriteOld)
1716	*ppfnWriteOld = pPciDev->Int.s.pfnConfigWrite;
1717	pPciDev->Int.s.pfnConfigWrite = pfnWrite;
1718	}
1719
1720
1721	/**
1722	* @interface_method_impl{PDMPCIBUSREG,pfnFakePCIBIOSR3}
1723	*/
1724	static DECLCALLBACK(int) pciR3FakePCIBIOS(PPDMDEVINS pDevIns)
1725	{
1726	unsigned i;
1727	uint8_t elcr[2] = {0, 0};
1728	PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
1729	PVM pVM = PDMDevHlpGetVM(pDevIns); Assert(pVM);
1730	PVMCPU pVCpu = PDMDevHlpGetVMCPU(pDevIns); Assert(pVM);
1731	uint32_t const cbBelow4GB = MMR3PhysGetRamSizeBelow4GB(pVM);
1732	uint64_t const cbAbove4GB = MMR3PhysGetRamSizeAbove4GB(pVM);
1733	RT_NOREF(cbBelow4GB, cbAbove4GB);
1734
1735	/*
1736	* Set the start addresses.
1737	*/
1738	pGlobals->pci_bios_io_addr = 0xd000;
1739	pGlobals->pci_bios_mem_addr = UINT32_C(0xf0000000);
1740	pGlobals->uBus = 0;
1741
1742	/*
1743	* Activate IRQ mappings.
1744	*/
1745	for (i = 0; i < 4; i++)
1746	{
1747	uint8_t irq = pci_irqs[i];
1748	/* Set to trigger level. */
1749	elcr[irq >> 3] \|= (1 << (irq & 7));
1750	/* Activate irq remapping in PIIX3. */
1751	pci_config_writeb(pGlobals, 0, pGlobals->PIIX3State.dev.devfn, 0x60 + i, irq);
1752	}
1753
1754	/* Tell to the PIC. */
1755	VBOXSTRICTRC rcStrict = IOMIOPortWrite(pVM, pVCpu, 0x4d0, elcr[0], sizeof(uint8_t));
1756	if (rcStrict == VINF_SUCCESS)
1757	rcStrict = IOMIOPortWrite(pVM, pVCpu, 0x4d1, elcr[1], sizeof(uint8_t));
1758	if (rcStrict != VINF_SUCCESS)
1759	{
1760	AssertMsgFailed(("Writing to PIC failed! rcStrict=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
1761	return RT_SUCCESS(rcStrict) ? VERR_INTERNAL_ERROR : VBOXSTRICTRC_VAL(rcStrict);
1762	}
1763
1764	/*
1765	* Init the devices.
1766	*/
1767	for (i = 0; i < 256; i++)
1768	{
1769	uint8_t aBridgePositions[256];
1770
1771	memset(aBridgePositions, 0, sizeof(aBridgePositions));
1772	Log2(("PCI: Initializing device %d (%#x)\n",
1773	i, 0x80000000 \| (i << 8)));
1774	pci_bios_init_device(pGlobals, 0, i, 0, aBridgePositions);
1775	}
1776
1777	return VINF_SUCCESS;
1778	}
1779
1780
1781	/* -=-=-=-=-=- Debug Info Handlers -=-=-=-=-=- */
1782
1783	/**
1784	* @callback_method_impl{FNDBGFHANDLERDEV}
1785	*/
1786	static DECLCALLBACK(void) pciR3IrqRouteInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
1787	{
1788	PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
1789	NOREF(pszArgs);
1790
1791	uint16_t router = pGlobals->PIIX3State.dev.devfn;
1792	pHlp->pfnPrintf(pHlp, "PCI interrupt router at: %02X:%02X:%X\n",
1793	router >> 8, (router >> 3) & 0x1f, router & 0x7);
1794
1795	for (int i = 0; i < 4; ++i)
1796	{
1797	uint8_t irq_map = pci_config_readb(pGlobals, 0, router, 0x60 + i);
1798	if (irq_map & 0x80)
1799	pHlp->pfnPrintf(pHlp, "PIRQ%c disabled\n", 'A' + i);
1800	else
1801	pHlp->pfnPrintf(pHlp, "PIRQ%c -> IRQ%d\n", 'A' + i, irq_map & 0xf);
1802	}
1803	}
1804
1805	/**
1806	* @callback_method_impl{FNDBGFHANDLERDEV}
1807	*/
1808	static DECLCALLBACK(void) pciR3IrqInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
1809	{
1810	PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
1811	NOREF(pszArgs);
1812
1813	pHlp->pfnPrintf(pHlp, "PCI I/O APIC IRQ levels:\n");
1814	for (int i = 0; i < PCI_APIC_IRQ_PINS; ++i)
1815	{
1816	pHlp->pfnPrintf(pHlp, " IRQ%02d: %u\n", 0x10 + i, pGlobals->pci_apic_irq_levels[i]);
1817	}
1818	}
1819
1820	/**
1821	* Outputs indent.
1822	*
1823	* @param pHlp Output helpers.
1824	* @param iIndent Indentation level.
1825	*/
1826	static void pciR3PrintIndent(PCDBGFINFOHLP pHlp, int iIndent)
1827	{
1828	while (iIndent-- > 0)
1829	pHlp->pfnPrintf(pHlp, " ");
1830	}
1831
1832	/**
1833	* Recursive worker for pciR3Info.
1834	*
1835	* @param pBus The bus to display.
1836	* @param pHlp Output helpers.
1837	* @param iIndent Indentation level.
1838	* @param fRegisters Whether to also display the PCI configuration registers
1839	* of each device on the bus.
1840	*/
1841	static void pciR3BusInfo(PPCIBUS pBus, PCDBGFINFOHLP pHlp, int iIndent, bool fRegisters)
1842	{
1843	for (uint32_t iDev = 0; iDev < RT_ELEMENTS(pBus->devices); iDev++)
1844	{
1845	PPCIDEVICE pPciDev = pBus->devices[iDev];
1846	if (pPciDev != NULL)
1847	{
1848	pciR3PrintIndent(pHlp, iIndent);
1849
1850	/*
1851	* For passthrough devices MSI/MSI-X mostly reflects the way interrupts delivered to the guest,
1852	* as host driver handles real devices interrupts.
1853	*/
1854	pHlp->pfnPrintf(pHlp, "%02x:%02x:%02x %s%s: %04x-%04x%s%s",
1855	pBus->iBus, (iDev >> 3) & 0xff, iDev & 0x7,
1856	pPciDev->name,
1857	pciDevIsPassthrough(pPciDev) ? " (PASSTHROUGH)" : "",
1858	PCIDevGetWord(pPciDev, VBOX_PCI_VENDOR_ID), PCIDevGetWord(pPciDev, VBOX_PCI_DEVICE_ID),
1859	pciDevIsMsiCapable(pPciDev) ? " MSI" : "",
1860	pciDevIsMsixCapable(pPciDev) ? " MSI-X" : ""
1861	);
1862	if (PCIDevGetByte(pPciDev, VBOX_PCI_INTERRUPT_PIN) != 0)
1863	{
1864	pHlp->pfnPrintf(pHlp, " IRQ%d", PCIDevGetByte(pPciDev, VBOX_PCI_INTERRUPT_LINE));
1865	pHlp->pfnPrintf(pHlp, " (INTA#->IRQ%d)", 0x10 + pci_slot_get_apic_pirq(iDev, 0));
1866	}
1867
1868	pHlp->pfnPrintf(pHlp, "\n");
1869
1870	uint16_t iCmd = PCIDevGetWord(pPciDev, VBOX_PCI_COMMAND);
1871	if ((iCmd & (VBOX_PCI_COMMAND_IO \| VBOX_PCI_COMMAND_MEMORY)) != 0)
1872	{
1873	for (int iRegion = 0; iRegion < PCI_NUM_REGIONS; iRegion++)
1874	{
1875	PCIIORegion* pRegion = &pPciDev->Int.s.aIORegions[iRegion];
1876	uint64_t iRegionSize = pRegion->size;
1877
1878	if (iRegionSize == 0)
1879	continue;
1880
1881	uint32_t u32Addr = PCIDevGetDWord(pPciDev, PCIDevGetRegionReg(iRegion));
1882	const char * pszDesc;
1883	char szDescBuf[128];
1884
1885	bool f64Bit = !!(pRegion->type & PCI_ADDRESS_SPACE_BAR64);
1886	if (pRegion->type & PCI_ADDRESS_SPACE_IO)
1887	{
1888	pszDesc = "IO";
1889	u32Addr &= ~0x3;
1890	}
1891	else
1892	{
1893	RTStrPrintf(szDescBuf, sizeof(szDescBuf), "MMIO%s%s",
1894	f64Bit ? "64" : "32",
1895	(pRegion->type & PCI_ADDRESS_SPACE_MEM_PREFETCH) ? " PREFETCH" : "");
1896	pszDesc = szDescBuf;
1897	u32Addr &= ~0xf;
1898	}
1899
1900	pciR3PrintIndent(pHlp, iIndent + 2);
1901	pHlp->pfnPrintf(pHlp, "%s region #%d: %x..%x\n",
1902	pszDesc, iRegion, u32Addr, u32Addr+iRegionSize);
1903	if (f64Bit)
1904	iRegion++;
1905	}
1906	}
1907
1908	pciR3PrintIndent(pHlp, iIndent + 2);
1909	uint16_t iStatus = PCIDevGetWord(pPciDev, VBOX_PCI_STATUS);
1910	pHlp->pfnPrintf(pHlp, "Command: %.Rhxs, Status: %.Rhxs\n",
1911	sizeof(uint16_t), &iCmd, sizeof(uint16_t), &iStatus);
1912	pciR3PrintIndent(pHlp, iIndent + 2);
1913	pHlp->pfnPrintf(pHlp, "Bus master: %s\n",
1914	iCmd & VBOX_PCI_COMMAND_MASTER ? "Yes" : "No");
1915
1916	if (fRegisters)
1917	{
1918	pciR3PrintIndent(pHlp, iIndent + 2);
1919	pHlp->pfnPrintf(pHlp, "PCI registers:\n");
1920	for (int iReg = 0; iReg < 0x100; )
1921	{
1922	int iPerLine = 0x10;
1923	Assert (0x100 % iPerLine == 0);
1924	pciR3PrintIndent(pHlp, iIndent + 3);
1925
1926	while (iPerLine-- > 0)
1927	{
1928	pHlp->pfnPrintf(pHlp, "%02x ", PCIDevGetByte(pPciDev, iReg++));
1929	}
1930	pHlp->pfnPrintf(pHlp, "\n");
1931	}
1932	}
1933	}
1934	}
1935
1936	if (pBus->cBridges > 0)
1937	{
1938	pciR3PrintIndent(pHlp, iIndent);
1939	pHlp->pfnPrintf(pHlp, "Registered %d bridges, subordinate buses info follows\n", pBus->cBridges);
1940	for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
1941	{
1942	PPCIBUS pBusSub = PDMINS_2_DATA(pBus->papBridgesR3[iBridge]->pDevIns, PPCIBUS);
1943	pciR3BusInfo(pBusSub, pHlp, iIndent + 1, fRegisters);
1944	}
1945	}
1946	}
1947
1948
1949	/**
1950	* @callback_method_impl{FNDBGFHANDLERDEV}
1951	*/
1952	static DECLCALLBACK(void) pciR3Info(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
1953	{
1954	PPCIBUS pBus = DEVINS_2_PCIBUS(pDevIns);
1955
1956	if (pszArgs == NULL \|\| !*pszArgs \|\| !strcmp(pszArgs, "basic"))
1957	pciR3BusInfo(pBus, pHlp, 0, false);
1958	else if (!strcmp(pszArgs, "verbose"))
1959	pciR3BusInfo(pBus, pHlp, 0, true);
1960	else
1961	pHlp->pfnPrintf(pHlp, "Invalid argument. Recognized arguments are 'basic', 'verbose'.\n");
1962	}
1963
1964
1965	/* -=-=-=-=-=- PDMDEVREG -=-=-=-=-=- */
1966
1967	/**
1968	* @interface_method_impl{PDMDEVREG,pfnRelocate}
1969	*/
1970	static DECLCALLBACK(void) pciR3Relocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
1971	{
1972	PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
1973	PPCIBUS pBus = &pGlobals->PciBus;
1974	pGlobals->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
1975
1976	pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
1977	pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
1978
1979	/* Relocate RC pointers for the attached pci devices. */
1980	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->devices); i++)
1981	{
1982	if (pBus->devices[i])
1983	pBus->devices[i]->Int.s.pBusRC += offDelta;
1984	}
1985	}
1986
1987
1988	/**
1989	* @interface_method_impl{PDMDEVREG,pfnReset}
1990	*/
1991	static DECLCALLBACK(void) pciR3Reset(PPDMDEVINS pDevIns)
1992	{
1993	pciR3FakePCIBIOS(pDevIns);
1994	}
1995
1996
1997	/**
1998	* @interface_method_impl{PDMDEVREG,pfnConstruct}
1999	*/
2000	static DECLCALLBACK(int) pciR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
2001	{
2002	RT_NOREF1(iInstance);
2003	Assert(iInstance == 0);
2004	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
2005
2006	/*
2007	* Validate and read configuration.
2008	*/
2009	if (!CFGMR3AreValuesValid(pCfg, "IOAPIC\0" "GCEnabled\0" "R0Enabled\0"))
2010	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
2011
2012	/* query whether we got an IOAPIC */
2013	bool fUseIoApic;
2014	int rc = CFGMR3QueryBoolDef(pCfg, "IOAPIC", &fUseIoApic, false);
2015	if (RT_FAILURE(rc))
2016	return PDMDEV_SET_ERROR(pDevIns, rc,
2017	N_("Configuration error: Failed to query boolean value \"IOAPIC\""));
2018
2019	/* check if RC code is enabled. */
2020	bool fGCEnabled;
2021	rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
2022	if (RT_FAILURE(rc))
2023	return PDMDEV_SET_ERROR(pDevIns, rc,
2024	N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
2025
2026	/* check if R0 code is enabled. */
2027	bool fR0Enabled;
2028	rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
2029	if (RT_FAILURE(rc))
2030	return PDMDEV_SET_ERROR(pDevIns, rc,
2031	N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
2032	Log(("PCI: fUseIoApic=%RTbool fGCEnabled=%RTbool fR0Enabled=%RTbool\n", fUseIoApic, fGCEnabled, fR0Enabled));
2033
2034	/*
2035	* Init data and register the PCI bus.
2036	*/
2037	PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
2038	pGlobals->pci_bios_io_addr = 0xc000;
2039	pGlobals->pci_bios_mem_addr = 0xf0000000;
2040	memset((void *)&pGlobals->pci_irq_levels, 0, sizeof(pGlobals->pci_irq_levels));
2041	pGlobals->fUseIoApic = fUseIoApic;
2042	memset((void *)&pGlobals->pci_apic_irq_levels, 0, sizeof(pGlobals->pci_apic_irq_levels));
2043
2044	pGlobals->pDevInsR3 = pDevIns;
2045	pGlobals->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2046	pGlobals->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2047
2048	pGlobals->PciBus.pDevInsR3 = pDevIns;
2049	pGlobals->PciBus.pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2050	pGlobals->PciBus.pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2051	pGlobals->PciBus.papBridgesR3 = (PPCIDEVICE *)PDMDevHlpMMHeapAllocZ(pDevIns, sizeof(PPCIDEVICE)
2052	* RT_ELEMENTS(pGlobals->PciBus.devices));
2053
2054	PDMPCIBUSREG PciBusReg;
2055	PPCIBUS pBus = &pGlobals->PciBus;
2056	PciBusReg.u32Version = PDM_PCIBUSREG_VERSION;
2057	PciBusReg.pfnRegisterR3 = pciR3MergedRegister;
2058	PciBusReg.pfnRegisterMsiR3 = NULL;
2059	PciBusReg.pfnIORegionRegisterR3 = pciR3CommonIORegionRegister;
2060	PciBusReg.pfnSetConfigCallbacksR3 = pciR3CommonSetConfigCallbacks;
2061	PciBusReg.pfnSetIrqR3 = pciSetIrq;
2062	PciBusReg.pfnFakePCIBIOSR3 = pciR3FakePCIBIOS;
2063	PciBusReg.pszSetIrqRC = fGCEnabled ? "pciSetIrq" : NULL;
2064	PciBusReg.pszSetIrqR0 = fR0Enabled ? "pciSetIrq" : NULL;
2065	rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBus->pPciHlpR3);
2066	if (RT_FAILURE(rc))
2067	return PDMDEV_SET_ERROR(pDevIns, rc,
2068	N_("Failed to register ourselves as a PCI Bus"));
2069	if (pBus->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
2070	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
2071	N_("PCI helper version mismatch; got %#x expected %#x"),
2072	pBus->pPciHlpR3->u32Version, PDM_PCIHLPR3_VERSION);
2073
2074	pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
2075	pBus->pPciHlpR0 = pBus->pPciHlpR3->pfnGetR0Helpers(pDevIns);
2076
2077	/* Disable default device locking. */
2078	rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
2079	AssertRCReturn(rc, rc);
2080
2081	/*
2082	* Fill in PCI configs and add them to the bus.
2083	*/
2084	/* i440FX */
2085	PCIDevSetVendorId( &pBus->PciDev, 0x8086); /* Intel */
2086	PCIDevSetDeviceId( &pBus->PciDev, 0x1237);
2087	PCIDevSetRevisionId(&pBus->PciDev, 0x02);
2088	PCIDevSetClassSub( &pBus->PciDev, 0x00); /* host2pci */
2089	PCIDevSetClassBase( &pBus->PciDev, 0x06); /* PCI_bridge */
2090	PCIDevSetHeaderType(&pBus->PciDev, 0x00);
2091	rc = PDMDevHlpPCIRegisterEx(pDevIns, &pBus->PciDev, PDMPCIDEVREG_CFG_PRIMARY, 0 /fFlags/,
2092	0 /uPciDevNo/, 0 /uPciFunNo/, "i440FX");
2093	AssertLogRelRCReturn(rc, rc);
2094
2095	/* PIIX3 */
2096	PCIDevSetVendorId( &pGlobals->PIIX3State.dev, 0x8086); /* Intel */
2097	PCIDevSetDeviceId( &pGlobals->PIIX3State.dev, 0x7000); /* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */
2098	PCIDevSetClassSub( &pGlobals->PIIX3State.dev, 0x01); /* PCI_ISA */
2099	PCIDevSetClassBase( &pGlobals->PIIX3State.dev, 0x06); /* PCI_bridge */
2100	PCIDevSetHeaderType(&pGlobals->PIIX3State.dev, 0x80); /* PCI_multifunction, generic */
2101	rc = PDMDevHlpPCIRegisterEx(pDevIns, &pGlobals->PIIX3State.dev, PDMPCIDEVREG_CFG_NEXT, 0 /fFlags/,
2102	1 /uPciDevNo/, 0 /uPciFunNo/, "PIIX3");
2103	AssertLogRelRCReturn(rc, rc);
2104	pciR3Piix3Reset(&pGlobals->PIIX3State);
2105
2106	pBus->iDevSearch = 16;
2107
2108	/*
2109	* Register I/O ports and save state.
2110	*/
2111	rc = PDMDevHlpIOPortRegister(pDevIns, 0x0cf8, 1, NULL, pciIOPortAddressWrite, pciIOPortAddressRead, NULL, NULL, "i440FX (PCI)");
2112	if (RT_FAILURE(rc))
2113	return rc;
2114	rc = PDMDevHlpIOPortRegister(pDevIns, 0x0cfc, 4, NULL, pciIOPortDataWrite, pciIOPortDataRead, NULL, NULL, "i440FX (PCI)");
2115	if (RT_FAILURE(rc))
2116	return rc;
2117	if (fGCEnabled)
2118	{
2119	rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x0cf8, 1, NIL_RTGCPTR, "pciIOPortAddressWrite", "pciIOPortAddressRead", NULL, NULL, "i440FX (PCI)");
2120	if (RT_FAILURE(rc))
2121	return rc;
2122	rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x0cfc, 4, NIL_RTGCPTR, "pciIOPortDataWrite", "pciIOPortDataRead", NULL, NULL, "i440FX (PCI)");
2123	if (RT_FAILURE(rc))
2124	return rc;
2125	}
2126	if (fR0Enabled)
2127	{
2128	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x0cf8, 1, NIL_RTR0PTR, "pciIOPortAddressWrite", "pciIOPortAddressRead", NULL, NULL, "i440FX (PCI)");
2129	if (RT_FAILURE(rc))
2130	return rc;
2131	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x0cfc, 4, NIL_RTR0PTR, "pciIOPortDataWrite", "pciIOPortDataRead", NULL, NULL, "i440FX (PCI)");
2132	if (RT_FAILURE(rc))
2133	return rc;
2134	}
2135
2136	rc = PDMDevHlpSSMRegisterEx(pDevIns, VBOX_PCI_SAVED_STATE_VERSION, sizeof(pBus) + 16128, "pgm",
2137	NULL, NULL, NULL,
2138	NULL, pciR3SaveExec, NULL,
2139	NULL, pciR3LoadExec, NULL);
2140	if (RT_FAILURE(rc))
2141	return rc;
2142
2143	PDMDevHlpDBGFInfoRegister(pDevIns, "pci",
2144	"Display PCI bus status. Recognizes 'basic' or 'verbose' as arguments, defaults to 'basic'.",
2145	pciR3Info);
2146	PDMDevHlpDBGFInfoRegister(pDevIns, "pciirq", "Display PCI IRQ state. (no arguments)", pciR3IrqInfo);
2147	PDMDevHlpDBGFInfoRegister(pDevIns, "irqroute", "Display PCI IRQ routing. (no arguments)", pciR3IrqRouteInfo);
2148
2149	return VINF_SUCCESS;
2150	}
2151
2152
2153	/**
2154	* The device registration structure.
2155	*/
2156	const PDMDEVREG g_DevicePCI =
2157	{
2158	/* u32Version */
2159	PDM_DEVREG_VERSION,
2160	/* szName */
2161	"pci",
2162	/* szRCMod */
2163	"VBoxDDRC.rc",
2164	/* szR0Mod */
2165	"VBoxDDR0.r0",
2166	/* pszDescription */
2167	"i440FX PCI bridge and PIIX3 ISA bridge.",
2168	/* fFlags */
2169	PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
2170	/* fClass */
2171	PDM_DEVREG_CLASS_BUS_PCI \| PDM_DEVREG_CLASS_BUS_ISA,
2172	/* cMaxInstances */
2173	1,
2174	/* cbInstance */
2175	sizeof(PCIGLOBALS),
2176	/* pfnConstruct */
2177	pciR3Construct,
2178	/* pfnDestruct */
2179	NULL,
2180	/* pfnRelocate */
2181	pciR3Relocate,
2182	/* pfnMemSetup */
2183	NULL,
2184	/* pfnPowerOn */
2185	NULL,
2186	/* pfnReset */
2187	pciR3Reset,
2188	/* pfnSuspend */
2189	NULL,
2190	/* pfnResume */
2191	NULL,
2192	/* pfnAttach */
2193	NULL,
2194	/* pfnDetach */
2195	NULL,
2196	/* pfnQueryInterface */
2197	NULL,
2198	/* pfnInitComplete */
2199	NULL,
2200	/* pfnPowerOff */
2201	NULL,
2202	/* pfnSoftReset */
2203	NULL,
2204	/* u32VersionEnd */
2205	PDM_DEVREG_VERSION
2206
2207	};
2208	#endif /* IN_RING3 */
2209
2210
2211
2212	/* -=-=-=-=-=- The PCI bridge specific bits -=-=-=-=-=- */
2213
2214	/**
2215	* @interface_method_impl{PDMPCIBUSREG,pfnSetIrqR3}
2216	*/
2217	PDMBOTHCBDECL(void) pcibridgeSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel, uint32_t uTagSrc)
2218	{
2219	/*
2220	* The PCI-to-PCI bridge specification defines how the interrupt pins
2221	* are routed from the secondary to the primary bus (see chapter 9).
2222	* iIrq gives the interrupt pin the pci device asserted.
2223	* We change iIrq here according to the spec and call the SetIrq function
2224	* of our parent passing the device which asserted the interrupt instead of the device of the bridge.
2225	*/
2226	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
2227	PPCIDEVICE pPciDevBus = pPciDev;
2228	int iIrqPinBridge = iIrq;
2229	uint8_t uDevFnBridge = 0;
2230
2231	/* Walk the chain until we reach the host bus. */
2232	do
2233	{
2234	uDevFnBridge = pBus->PciDev.devfn;
2235	iIrqPinBridge = ((pPciDevBus->devfn >> 3) + iIrqPinBridge) & 3;
2236
2237	/* Get the parent. */
2238	pBus = pBus->PciDev.Int.s.CTX_SUFF(pBus);
2239	pPciDevBus = &pBus->PciDev;
2240	} while (pBus->iBus != 0);
2241
2242	AssertMsg(pBus->iBus == 0, ("This is not the host pci bus iBus=%d\n", pBus->iBus));
2243	pciSetIrqInternal(PCIBUS_2_PCIGLOBALS(pBus), uDevFnBridge, pPciDev, iIrqPinBridge, iLevel, uTagSrc);
2244	}
2245
2246	#ifdef IN_RING3
2247
2248	/**
2249	* @callback_method_impl{FNPCIBRIDGECONFIGWRITE}
2250	*/
2251	static DECLCALLBACK(void) pcibridgeR3ConfigWrite(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice, uint32_t u32Address, uint32_t u32Value, unsigned cb)
2252	{
2253	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
2254
2255	LogFlowFunc(("pDevIns=%p iBus=%d iDevice=%d u32Address=%u u32Value=%u cb=%d\n", pDevIns, iBus, iDevice, u32Address, u32Value, cb));
2256
2257	/* If the current bus is not the target bus search for the bus which contains the device. */
2258	if (iBus != pBus->PciDev.config[VBOX_PCI_SECONDARY_BUS])
2259	{
2260	PPCIDEVICE pBridgeDevice = pciR3FindBridge(pBus, iBus);
2261	if (pBridgeDevice)
2262	{
2263	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigWrite);
2264	pBridgeDevice->Int.s.pfnBridgeConfigWrite(pBridgeDevice->pDevIns, iBus, iDevice, u32Address, u32Value, cb);
2265	}
2266	}
2267	else
2268	{
2269	/* This is the target bus, pass the write to the device. */
2270	PPCIDEVICE pPciDev = pBus->devices[iDevice];
2271	if (pPciDev)
2272	{
2273	Log(("%s: %s: addr=%02x val=%08x len=%d\n", __FUNCTION__, pPciDev->name, u32Address, u32Value, cb));
2274	pPciDev->Int.s.pfnConfigWrite(pPciDev->Int.s.CTX_SUFF(pDevIns), pPciDev, u32Address, u32Value, cb);
2275	}
2276	}
2277	}
2278
2279
2280	/**
2281	* @callback_method_impl{FNPCIBRIDGECONFIGREAD}
2282	*/
2283	static DECLCALLBACK(uint32_t) pcibridgeR3ConfigRead(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice, uint32_t u32Address, unsigned cb)
2284	{
2285	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
2286	uint32_t u32Value = 0xffffffff; /* Return value in case there is no device. */
2287
2288	LogFlowFunc(("pDevIns=%p iBus=%d iDevice=%d u32Address=%u cb=%d\n", pDevIns, iBus, iDevice, u32Address, cb));
2289
2290	/* If the current bus is not the target bus search for the bus which contains the device. */
2291	if (iBus != pBus->PciDev.config[VBOX_PCI_SECONDARY_BUS])
2292	{
2293	PPCIDEVICE pBridgeDevice = pciR3FindBridge(pBus, iBus);
2294	if (pBridgeDevice)
2295	{
2296	AssertPtr( pBridgeDevice->Int.s.pfnBridgeConfigRead);
2297	u32Value = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->pDevIns, iBus, iDevice, u32Address, cb);
2298	}
2299	}
2300	else
2301	{
2302	/* This is the target bus, pass the read to the device. */
2303	PPCIDEVICE pPciDev = pBus->devices[iDevice];
2304	if (pPciDev)
2305	{
2306	u32Value = pPciDev->Int.s.pfnConfigRead(pPciDev->Int.s.CTX_SUFF(pDevIns), pPciDev, u32Address, cb);
2307	Log(("%s: %s: u32Address=%02x u32Value=%08x cb=%d\n", __FUNCTION__, pPciDev->name, u32Address, u32Value, cb));
2308	}
2309	}
2310
2311	return u32Value;
2312	}
2313
2314
2315	/**
2316	* @callback_method_impl{FNSSMDEVSAVEEXEC}
2317	*/
2318	static DECLCALLBACK(int) pcibridgeR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
2319	{
2320	PPCIBUS pThis = PDMINS_2_DATA(pDevIns, PPCIBUS);
2321	return pciR3CommonSaveExec(pThis, pSSM);
2322	}
2323
2324
2325	/**
2326	* @callback_method_impl{FNSSMDEVLOADEXEC}
2327	*/
2328	static DECLCALLBACK(int) pcibridgeR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2329	{
2330	PPCIBUS pThis = PDMINS_2_DATA(pDevIns, PPCIBUS);
2331	if (uVersion > VBOX_PCI_SAVED_STATE_VERSION)
2332	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2333	return pciR3CommonLoadExec(pThis, pSSM, uVersion, uPass);
2334	}
2335
2336
2337	/**
2338	* @interface_method_impl{PDMDEVREG,pfnReset}
2339	*/
2340	static DECLCALLBACK(void) pcibridgeR3Reset(PPDMDEVINS pDevIns)
2341	{
2342	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
2343
2344	/* Reset config space to default values. */
2345	pBus->PciDev.config[VBOX_PCI_PRIMARY_BUS] = 0;
2346	pBus->PciDev.config[VBOX_PCI_SECONDARY_BUS] = 0;
2347	pBus->PciDev.config[VBOX_PCI_SUBORDINATE_BUS] = 0;
2348	}
2349
2350
2351	/**
2352	* @interface_method_impl{PDMDEVREG,pfnRelocate}
2353	*/
2354	static DECLCALLBACK(void) pcibridgeR3Relocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
2355	{
2356	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
2357	pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2358
2359	/* Relocate RC pointers for the attached pci devices. */
2360	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->devices); i++)
2361	{
2362	if (pBus->devices[i])
2363	pBus->devices[i]->Int.s.pBusRC += offDelta;
2364	}
2365	}
2366
2367
2368	/**
2369	* @interface_method_impl{PDMDEVREG,pfnConstruct}
2370	*/
2371	static DECLCALLBACK(int) pcibridgeR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
2372	{
2373	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
2374
2375	/*
2376	* Validate and read configuration.
2377	*/
2378	if (!CFGMR3AreValuesValid(pCfg, "GCEnabled\0" "R0Enabled\0"))
2379	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
2380
2381	/* check if RC code is enabled. */
2382	bool fGCEnabled;
2383	int rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
2384	if (RT_FAILURE(rc))
2385	return PDMDEV_SET_ERROR(pDevIns, rc,
2386	N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
2387
2388	/* check if R0 code is enabled. */
2389	bool fR0Enabled;
2390	rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
2391	if (RT_FAILURE(rc))
2392	return PDMDEV_SET_ERROR(pDevIns, rc,
2393	N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
2394	Log(("PCI: fGCEnabled=%RTbool fR0Enabled=%RTbool\n", fGCEnabled, fR0Enabled));
2395
2396	/*
2397	* Init data and register the PCI bus.
2398	*/
2399	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
2400	pBus->pDevInsR3 = pDevIns;
2401	pBus->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2402	pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2403	pBus->papBridgesR3 = (PPCIDEVICE )PDMDevHlpMMHeapAllocZ(pDevIns, sizeof(PPCIDEVICE) RT_ELEMENTS(pBus->devices));
2404
2405	PDMPCIBUSREG PciBusReg;
2406	PciBusReg.u32Version = PDM_PCIBUSREG_VERSION;
2407	PciBusReg.pfnRegisterR3 = pcibridgeR3MergedRegisterDevice;
2408	PciBusReg.pfnRegisterMsiR3 = NULL;
2409	PciBusReg.pfnIORegionRegisterR3 = pciR3CommonIORegionRegister;
2410	PciBusReg.pfnSetConfigCallbacksR3 = pciR3CommonSetConfigCallbacks;
2411	PciBusReg.pfnSetIrqR3 = pcibridgeSetIrq;
2412	PciBusReg.pfnFakePCIBIOSR3 = NULL; /* Only needed for the first bus. */
2413	PciBusReg.pszSetIrqRC = fGCEnabled ? "pcibridgeSetIrq" : NULL;
2414	PciBusReg.pszSetIrqR0 = fR0Enabled ? "pcibridgeSetIrq" : NULL;
2415	rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBus->pPciHlpR3);
2416	if (RT_FAILURE(rc))
2417	return PDMDEV_SET_ERROR(pDevIns, rc,
2418	N_("Failed to register ourselves as a PCI Bus"));
2419	if (pBus->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
2420	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
2421	N_("PCI helper version mismatch; got %#x expected %#x"),
2422	pBus->pPciHlpR3->u32Version, PDM_PCIHLPR3_VERSION);
2423
2424	pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
2425	pBus->pPciHlpR0 = pBus->pPciHlpR3->pfnGetR0Helpers(pDevIns);
2426
2427	/*
2428	* Fill in PCI configs and add them to the bus.
2429	*/
2430	PCIDevSetVendorId( &pBus->PciDev, 0x8086); /* Intel */
2431	PCIDevSetDeviceId( &pBus->PciDev, 0x2448); /* 82801 Mobile PCI bridge. */
2432	PCIDevSetRevisionId(&pBus->PciDev, 0xf2);
2433	PCIDevSetClassSub( &pBus->PciDev, 0x04); /* pci2pci */
2434	PCIDevSetClassBase( &pBus->PciDev, 0x06); /* PCI_bridge */
2435	PCIDevSetClassProg( &pBus->PciDev, 0x01); /* Supports subtractive decoding. */
2436	PCIDevSetHeaderType(&pBus->PciDev, 0x01); /* Single function device which adheres to the PCI-to-PCI bridge spec. */
2437	PCIDevSetCommand( &pBus->PciDev, 0x00);
2438	PCIDevSetStatus( &pBus->PciDev, 0x20); /* 66MHz Capable. */
2439	PCIDevSetInterruptLine(&pBus->PciDev, 0x00); /* This device does not assert interrupts. */
2440
2441	/*
2442	* This device does not generate interrupts. Interrupt delivery from
2443	* devices attached to the bus is unaffected.
2444	*/
2445	PCIDevSetInterruptPin(&pBus->PciDev, 0x00);
2446
2447	/*
2448	* Register this PCI bridge. The called function will take care on which bus we will get registered.
2449	*/
2450	rc = PDMDevHlpPCIRegisterEx(pDevIns, &pBus->PciDev, PDMPCIDEVREG_CFG_PRIMARY, PDMPCIDEVREG_F_PCI_BRIDGE,
2451	PDMPCIDEVREG_DEV_NO_FIRST_UNUSED, PDMPCIDEVREG_FUN_NO_FIRST_UNUSED, "pcibridge");
2452	if (RT_FAILURE(rc))
2453	return rc;
2454	pBus->PciDev.Int.s.pfnBridgeConfigRead = pcibridgeR3ConfigRead;
2455	pBus->PciDev.Int.s.pfnBridgeConfigWrite = pcibridgeR3ConfigWrite;
2456
2457	pBus->iDevSearch = 0;
2458	/*
2459	* The iBus property doesn't really represent the bus number
2460	* because the guest and the BIOS can choose different bus numbers
2461	* for them.
2462	* The bus number is mainly for the setIrq function to indicate
2463	* when the host bus is reached which will have iBus = 0.
2464	* That's why the + 1.
2465	*/
2466	pBus->iBus = iInstance + 1;
2467
2468	/*
2469	* Register SSM handlers. We use the same saved state version as for the host bridge
2470	* to make changes easier.
2471	*/
2472	rc = PDMDevHlpSSMRegisterEx(pDevIns, VBOX_PCI_SAVED_STATE_VERSION, sizeof(pBus) + 16128, "pgm",
2473	NULL, NULL, NULL,
2474	NULL, pcibridgeR3SaveExec, NULL,
2475	NULL, pcibridgeR3LoadExec, NULL);
2476	if (RT_FAILURE(rc))
2477	return rc;
2478
2479	return VINF_SUCCESS;
2480	}
2481
2482
2483	/**
2484	* The device registration structure
2485	* for the PCI-to-PCI bridge.
2486	*/
2487	const PDMDEVREG g_DevicePCIBridge =
2488	{
2489	/* u32Version */
2490	PDM_DEVREG_VERSION,
2491	/* szName */
2492	"pcibridge",
2493	/* szRCMod */
2494	"VBoxDDRC.rc",
2495	/* szR0Mod */
2496	"VBoxDDR0.r0",
2497	/* pszDescription */
2498	"82801 Mobile PCI to PCI bridge",
2499	/* fFlags */
2500	PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
2501	/* fClass */
2502	PDM_DEVREG_CLASS_BUS_PCI,
2503	/* cMaxInstances */
2504	~0U,
2505	/* cbInstance */
2506	sizeof(PCIBUS),
2507	/* pfnConstruct */
2508	pcibridgeR3Construct,
2509	/* pfnDestruct */
2510	NULL,
2511	/* pfnRelocate */
2512	pcibridgeR3Relocate,
2513	/* pfnMemSetup */
2514	NULL,
2515	/* pfnPowerOn */
2516	NULL,
2517	/* pfnReset */
2518	pcibridgeR3Reset,
2519	/* pfnSuspend */
2520	NULL,
2521	/* pfnResume */
2522	NULL,
2523	/* pfnAttach */
2524	NULL,
2525	/* pfnDetach */
2526	NULL,
2527	/* pfnQueryInterface */
2528	NULL,
2529	/* pfnInitComplete */
2530	NULL,
2531	/* pfnPowerOff */
2532	NULL,
2533	/* pfnSoftReset */
2534	NULL,
2535	/* u32VersionEnd */
2536	PDM_DEVREG_VERSION
2537	};
2538
2539	#endif /* IN_RING3 */
2540	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */

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source: vbox/trunk/src/VBox/Devices/Bus/DevPCI.cpp@ 64375

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