VirtualBox

source: vbox/trunk/src/VBox/Devices/Bus/DevPCI.cpp@ 67672

Last change on this file since 67672 was 67672, checked in by vboxsync, 7 years ago

Devices/Bus: fix logging errors which crept into the big cleanup
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1/* $Id: DevPCI.cpp 67672 2017-06-28 17:59:39Z vboxsync $ */
2/** @file
3 * DevPCI - PCI BUS Device.
4 *
5 * @remarks New code shall be added to DevPciIch9.cpp as that will become
6 * the common PCI bus code soon. Don't fix code in both DevPCI.cpp
7 * and DevPciIch9.cpp when it's possible to just make the latter
8 * version common. Common code uses the 'devpci' prefix, is
9 * prototyped in DevPciInternal.h, and is defined in DevPciIch9.cpp.
10 */
11
12/*
13 * Copyright (C) 2006-2016 Oracle Corporation
14 *
15 * This file is part of VirtualBox Open Source Edition (OSE), as
16 * available from http://www.virtualbox.org. This file is free software;
17 * you can redistribute it and/or modify it under the terms of the GNU
18 * General Public License (GPL) as published by the Free Software
19 * Foundation, in version 2 as it comes in the "COPYING" file of the
20 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
21 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
22 * --------------------------------------------------------------------
23 *
24 * This code is based on:
25 *
26 * QEMU PCI bus manager
27 *
28 * Copyright (c) 2004 Fabrice Bellard
29 *
30 * Permission is hereby granted, free of charge, to any person obtaining a copy
31 * of this software and associated documentation files (the "Software"), to deal
32 * in the Software without restriction, including without limitation the rights
33 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
34 * copies of the Software, and to permit persons to whom the Software is
35 * furnished to do so, subject to the following conditions:
36 *
37 * The above copyright notice and this permission notice shall be included in
38 * all copies or substantial portions of the Software.
39 *
40 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
41 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
42 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
43 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
44 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
45 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
46 * THE SOFTWARE.
47 */
48
49
50/*********************************************************************************************************************************
51* Header Files *
52*********************************************************************************************************************************/
53#define LOG_GROUP LOG_GROUP_DEV_PCI
54#define PDMPCIDEV_INCLUDE_PRIVATE /* Hack to get pdmpcidevint.h included at the right point. */
55#include <VBox/vmm/pdmpcidev.h>
56#include <VBox/vmm/pdmdev.h>
57#include <VBox/vmm/mm.h>
58#include <iprt/asm.h>
59#include <iprt/assert.h>
60#include <iprt/string.h>
61
62#include "PciInline.h"
63#include "VBoxDD.h"
64#include "DevPciInternal.h"
65
66
67/*********************************************************************************************************************************
68* Defined Constants And Macros *
69*********************************************************************************************************************************/
70/** Saved state version of the PCI bus device. */
71#define VBOX_PCI_SAVED_STATE_VERSION VBOX_PCI_SAVED_STATE_VERSION_REGION_SIZES
72/** Adds I/O region types and sizes for dealing changes in resource regions. */
73#define VBOX_PCI_SAVED_STATE_VERSION_REGION_SIZES 4
74/** Before region sizes, the first named one.
75 * Looking at the code though, we support even older version. */
76#define VBOX_PCI_SAVED_STATE_VERSION_IRQ_STATES 3
77/** Notes whether we use the I/O APIC. */
78#define VBOX_PCI_SAVED_STATE_VERSION_USE_IO_APIC 2
79
80
81/*********************************************************************************************************************************
82* Internal Functions *
83*********************************************************************************************************************************/
84RT_C_DECLS_BEGIN
85
86PDMBOTHCBDECL(void) pciSetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTag);
87PDMBOTHCBDECL(void) pcibridgeSetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTag);
88PDMBOTHCBDECL(int) pciIOPortAddressWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
89PDMBOTHCBDECL(int) pciIOPortAddressRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb);
90PDMBOTHCBDECL(int) pciIOPortDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
91PDMBOTHCBDECL(int) pciIOPortDataRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb);
92
93#ifdef IN_RING3
94DECLINLINE(PPDMPCIDEV) pciR3FindBridge(PDEVPCIBUS pBus, uint8_t iBus);
95#endif
96
97RT_C_DECLS_END
98
99#define DEBUG_PCI
100
101#define PCI_VENDOR_ID 0x00 /* 16 bits */
102#define PCI_DEVICE_ID 0x02 /* 16 bits */
103#define PCI_COMMAND 0x04 /* 16 bits */
104#define PCI_COMMAND_IO 0x01 /* Enable response in I/O space */
105#define PCI_COMMAND_MEMORY 0x02 /* Enable response in Memory space */
106#define PCI_CLASS_DEVICE 0x0a /* Device class */
107#define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
108#define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
109#define PCI_MIN_GNT 0x3e /* 8 bits */
110#define PCI_MAX_LAT 0x3f /* 8 bits */
111
112
113static int pci_data_write(PDEVPCIROOT pGlobals, uint32_t addr, uint32_t val, int len)
114{
115 uint8_t iBus, iDevice;
116 uint32_t config_addr;
117
118 LogFunc(("addr=%08x val=%08x len=%d\n", pGlobals->uConfigReg, val, len));
119
120 if (!(pGlobals->uConfigReg & (1 << 31))) {
121 return VINF_SUCCESS;
122 }
123 if ((pGlobals->uConfigReg & 0x3) != 0) {
124 return VINF_SUCCESS;
125 }
126 iBus = (pGlobals->uConfigReg >> 16) & 0xff;
127 iDevice = (pGlobals->uConfigReg >> 8) & 0xff;
128 config_addr = (pGlobals->uConfigReg & 0xfc) | (addr & 3);
129 if (iBus != 0)
130 {
131 if (pGlobals->PciBus.cBridges)
132 {
133#ifdef IN_RING3 /** @todo do lookup in R0/RC too! */
134 PPDMPCIDEV pBridgeDevice = pciR3FindBridge(&pGlobals->PciBus, iBus);
135 if (pBridgeDevice)
136 {
137 AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigWrite);
138 pBridgeDevice->Int.s.pfnBridgeConfigWrite(pBridgeDevice->Int.s.CTX_SUFF(pDevIns), iBus, iDevice, config_addr, val, len);
139 }
140#else
141 RT_NOREF2(val, len);
142 return VINF_IOM_R3_IOPORT_WRITE;
143#endif
144 }
145 }
146 else
147 {
148 R3PTRTYPE(PDMPCIDEV *) pci_dev = pGlobals->PciBus.apDevices[iDevice];
149 if (pci_dev)
150 {
151#ifdef IN_RING3
152 LogFunc(("%s: addr=%02x val=%08x len=%d\n", pci_dev->pszNameR3, config_addr, val, len));
153 pci_dev->Int.s.pfnConfigWrite(pci_dev->Int.s.CTX_SUFF(pDevIns), pci_dev, config_addr, val, len);
154#else
155 return VINF_IOM_R3_IOPORT_WRITE;
156#endif
157 }
158 }
159 return VINF_SUCCESS;
160}
161
162static int pci_data_read(PDEVPCIROOT pGlobals, uint32_t addr, int len, uint32_t *pu32)
163{
164 uint8_t iBus, iDevice;
165 uint32_t config_addr;
166
167 *pu32 = 0xffffffff;
168
169 if (!(pGlobals->uConfigReg & (1 << 31)))
170 return VINF_SUCCESS;
171 if ((pGlobals->uConfigReg & 0x3) != 0)
172 return VINF_SUCCESS;
173 iBus = (pGlobals->uConfigReg >> 16) & 0xff;
174 iDevice = (pGlobals->uConfigReg >> 8) & 0xff;
175 config_addr = (pGlobals->uConfigReg & 0xfc) | (addr & 3);
176 if (iBus != 0)
177 {
178 if (pGlobals->PciBus.cBridges)
179 {
180#ifdef IN_RING3 /** @todo do lookup in R0/RC too! */
181 PPDMPCIDEV pBridgeDevice = pciR3FindBridge(&pGlobals->PciBus, iBus);
182 if (pBridgeDevice)
183 {
184 AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigRead);
185 *pu32 = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->Int.s.CTX_SUFF(pDevIns), iBus, iDevice, config_addr, len);
186 }
187#else
188 NOREF(len);
189 return VINF_IOM_R3_IOPORT_READ;
190#endif
191 }
192 }
193 else
194 {
195 R3PTRTYPE(PDMPCIDEV *) pci_dev = pGlobals->PciBus.apDevices[iDevice];
196 if (pci_dev)
197 {
198#ifdef IN_RING3
199 *pu32 = pci_dev->Int.s.pfnConfigRead(pci_dev->Int.s.CTX_SUFF(pDevIns), pci_dev, config_addr, len);
200 LogFunc(("%s: addr=%02x val=%08x len=%d\n", pci_dev->pszNameR3, config_addr, *pu32, len));
201#else
202 NOREF(len);
203 return VINF_IOM_R3_IOPORT_READ;
204#endif
205 }
206 }
207
208 return VINF_SUCCESS;
209}
210
211
212
213/* return the global irq number corresponding to a given device irq
214 pin. We could also use the bus number to have a more precise
215 mapping.
216 This is the implementation note described in the PCI spec chapter 2.2.6 */
217static inline int pci_slot_get_pirq(uint8_t uDevFn, int irq_num)
218{
219 int slot_addend;
220 slot_addend = (uDevFn >> 3) - 1;
221 return (irq_num + slot_addend) & 3;
222}
223
224static inline int pci_slot_get_apic_pirq(uint8_t uDevFn, int irq_num)
225{
226 return (irq_num + (uDevFn >> 3)) & 7;
227}
228
229static inline int get_pci_irq_apic_level(PDEVPCIROOT pGlobals, int irq_num)
230{
231 return (pGlobals->auPciApicIrqLevels[irq_num] != 0);
232}
233
234static void apic_set_irq(PDEVPCIBUS pBus, uint8_t uDevFn, PDMPCIDEV *pPciDev, int irq_num1, int iLevel, int iAcpiIrq, uint32_t uTagSrc)
235{
236 /* This is only allowed to be called with a pointer to the host bus. */
237 AssertMsg(pBus->iBus == 0, ("iBus=%u\n", pBus->iBus));
238
239 if (iAcpiIrq == -1) {
240 int apic_irq, apic_level;
241 PDEVPCIROOT pGlobals = DEVPCIBUS_2_DEVPCIROOT(pBus);
242 int irq_num = pci_slot_get_apic_pirq(uDevFn, irq_num1);
243
244 if ((iLevel & PDM_IRQ_LEVEL_HIGH) == PDM_IRQ_LEVEL_HIGH)
245 ASMAtomicIncU32(&pGlobals->auPciApicIrqLevels[irq_num]);
246 else if ((iLevel & PDM_IRQ_LEVEL_HIGH) == PDM_IRQ_LEVEL_LOW)
247 ASMAtomicDecU32(&pGlobals->auPciApicIrqLevels[irq_num]);
248
249 apic_irq = irq_num + 0x10;
250 apic_level = get_pci_irq_apic_level(pGlobals, irq_num);
251 Log3Func(("%s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d\n",
252 R3STRING(pPciDev->pszNameR3), irq_num1, iLevel, apic_irq, apic_level, irq_num));
253 pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), apic_irq, apic_level, uTagSrc);
254
255 if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP) {
256 ASMAtomicDecU32(&pGlobals->auPciApicIrqLevels[irq_num]);
257 pPciDev->Int.s.uIrqPinState = PDM_IRQ_LEVEL_LOW;
258 apic_level = get_pci_irq_apic_level(pGlobals, irq_num);
259 Log3Func(("%s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d (flop)\n",
260 R3STRING(pPciDev->pszNameR3), irq_num1, iLevel, apic_irq, apic_level, irq_num));
261 pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), apic_irq, apic_level, uTagSrc);
262 }
263 } else {
264 Log3Func(("%s: irq_num1=%d level=%d iAcpiIrq=%d\n",
265 R3STRING(pPciDev->pszNameR3), irq_num1, iLevel, iAcpiIrq));
266 pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), iAcpiIrq, iLevel, uTagSrc);
267 }
268}
269
270DECLINLINE(int) get_pci_irq_level(PDEVPCIROOT pGlobals, int irq_num)
271{
272 return (pGlobals->Piix3.auPciLegacyIrqLevels[irq_num] != 0);
273}
274
275/**
276 * Set the IRQ for a PCI device on the host bus - shared by host bus and bridge.
277 *
278 * @param pGlobals Device instance of the host PCI Bus.
279 * @param uDevFn The device number on the host bus which will raise the IRQ
280 * @param pPciDev The PCI device structure which raised the interrupt.
281 * @param iIrq IRQ number to set.
282 * @param iLevel IRQ level.
283 * @param uTagSrc The IRQ tag and source ID (for tracing).
284 * @remark uDevFn and pPciDev->uDevFn are not the same if the device is behind
285 * a bridge. In that case uDevFn will be the slot of the bridge which
286 * is needed to calculate the PIRQ value.
287 */
288static void pciSetIrqInternal(PDEVPCIROOT pGlobals, uint8_t uDevFn, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc)
289{
290 PDEVPCIBUS pBus = &pGlobals->PciBus;
291 uint8_t *pbCfg = pGlobals->Piix3.PIIX3State.dev.abConfig;
292 const bool fIsAcpiDevice = pPciDev->abConfig[2] == 0x13 && pPciDev->abConfig[3] == 0x71;
293 /* If the two configuration space bytes at 0xde, 0xad are set to 0xbe, 0xef, a back door
294 * is opened to route PCI interrupts directly to the I/O APIC and bypass the PIC.
295 * See the \_SB_.PCI0._PRT method in vbox.dsl.
296 */
297 const bool fIsApicEnabled = pGlobals->fUseIoApic && pbCfg[0xde] == 0xbe && pbCfg[0xad] == 0xef;
298 int pic_irq, pic_level;
299
300 /* Check if the state changed. */
301 if (pPciDev->Int.s.uIrqPinState != iLevel)
302 {
303 pPciDev->Int.s.uIrqPinState = (iLevel & PDM_IRQ_LEVEL_HIGH);
304
305 /* Send interrupt to I/O APIC only. */
306 if (fIsApicEnabled)
307 {
308 if (fIsAcpiDevice)
309 /*
310 * ACPI needs special treatment since SCI is hardwired and
311 * should not be affected by PCI IRQ routing tables at the
312 * same time SCI IRQ is shared in PCI sense hence this
313 * kludge (i.e. we fetch the hardwired value from ACPIs
314 * PCI device configuration space).
315 */
316 apic_set_irq(pBus, uDevFn, pPciDev, -1, iLevel, pPciDev->abConfig[PCI_INTERRUPT_LINE], uTagSrc);
317 else
318 apic_set_irq(pBus, uDevFn, pPciDev, iIrq, iLevel, -1, uTagSrc);
319 return;
320 }
321
322 if (fIsAcpiDevice)
323 {
324 /* As per above treat ACPI in a special way */
325 pic_irq = pPciDev->abConfig[PCI_INTERRUPT_LINE];
326 pGlobals->Piix3.iAcpiIrq = pic_irq;
327 pGlobals->Piix3.iAcpiIrqLevel = iLevel & PDM_IRQ_LEVEL_HIGH;
328 }
329 else
330 {
331 int irq_num;
332 irq_num = pci_slot_get_pirq(uDevFn, iIrq);
333
334 if (pPciDev->Int.s.uIrqPinState == PDM_IRQ_LEVEL_HIGH)
335 ASMAtomicIncU32(&pGlobals->Piix3.auPciLegacyIrqLevels[irq_num]);
336 else if (pPciDev->Int.s.uIrqPinState == PDM_IRQ_LEVEL_LOW)
337 ASMAtomicDecU32(&pGlobals->Piix3.auPciLegacyIrqLevels[irq_num]);
338
339 /* now we change the pic irq level according to the piix irq mappings */
340 pic_irq = pbCfg[0x60 + irq_num];
341 if (pic_irq >= 16)
342 {
343 if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP)
344 {
345 ASMAtomicDecU32(&pGlobals->Piix3.auPciLegacyIrqLevels[irq_num]);
346 pPciDev->Int.s.uIrqPinState = PDM_IRQ_LEVEL_LOW;
347 }
348
349 return;
350 }
351 }
352
353 /* the pic level is the logical OR of all the PCI irqs mapped to it */
354 pic_level = 0;
355 if (pic_irq == pbCfg[0x60])
356 pic_level |= get_pci_irq_level(pGlobals, 0);
357 if (pic_irq == pbCfg[0x61])
358 pic_level |= get_pci_irq_level(pGlobals, 1);
359 if (pic_irq == pbCfg[0x62])
360 pic_level |= get_pci_irq_level(pGlobals, 2);
361 if (pic_irq == pbCfg[0x63])
362 pic_level |= get_pci_irq_level(pGlobals, 3);
363 if (pic_irq == pGlobals->Piix3.iAcpiIrq)
364 pic_level |= pGlobals->Piix3.iAcpiIrqLevel;
365
366 Log3Func(("%s: iLevel=%d iIrq=%d pic_irq=%d pic_level=%d uTagSrc=%#x\n",
367 R3STRING(pPciDev->pszNameR3), iLevel, iIrq, pic_irq, pic_level, uTagSrc));
368 pBus->CTX_SUFF(pPciHlp)->pfnIsaSetIrq(pBus->CTX_SUFF(pDevIns), pic_irq, pic_level, uTagSrc);
369
370 /** @todo optimize pci irq flip-flop some rainy day. */
371 if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP)
372 pciSetIrqInternal(pGlobals, uDevFn, pPciDev, iIrq, PDM_IRQ_LEVEL_LOW, uTagSrc);
373 }
374}
375
376
377/**
378 * @interface_method_impl{PDMPCIBUSREG,pfnSetIrqR3}
379 */
380PDMBOTHCBDECL(void) pciSetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc)
381{
382 pciSetIrqInternal(PDMINS_2_DATA(pDevIns, PDEVPCIROOT), pPciDev->uDevFn, pPciDev, iIrq, iLevel, uTagSrc);
383}
384
385#ifdef IN_RING3
386
387/**
388 * Finds a bridge on the bus which contains the destination bus.
389 *
390 * @return Pointer to the device instance data of the bus or
391 * NULL if no bridge was found.
392 * @param pBus Pointer to the bus to search on.
393 * @param iBus Destination bus number.
394 */
395DECLINLINE(PPDMPCIDEV) pciR3FindBridge(PDEVPCIBUS pBus, uint8_t iBus)
396{
397 /* Search for a fitting bridge. */
398 for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
399 {
400 /*
401 * Examine secondary and subordinate bus number.
402 * If the target bus is in the range we pass the request on to the bridge.
403 */
404 PPDMPCIDEV pBridgeTemp = pBus->papBridgesR3[iBridge];
405 AssertMsg(pBridgeTemp && pciDevIsPci2PciBridge(pBridgeTemp),
406 ("Device is not a PCI bridge but on the list of PCI bridges\n"));
407
408 if ( iBus >= pBridgeTemp->abConfig[VBOX_PCI_SECONDARY_BUS]
409 && iBus <= pBridgeTemp->abConfig[VBOX_PCI_SUBORDINATE_BUS])
410 return pBridgeTemp;
411 }
412
413 /* Nothing found. */
414 return NULL;
415}
416
417static void pciR3Piix3Reset(PIIX3ISABRIDGE *d)
418{
419 uint8_t *pci_conf = d->dev.abConfig;
420
421 pci_conf[0x04] = 0x07; /* master, memory and I/O */
422 pci_conf[0x05] = 0x00;
423 pci_conf[0x06] = 0x00;
424 pci_conf[0x07] = 0x02; /* PCI_status_devsel_medium */
425 pci_conf[0x4c] = 0x4d;
426 pci_conf[0x4e] = 0x03;
427 pci_conf[0x4f] = 0x00;
428 pci_conf[0x60] = 0x80;
429 pci_conf[0x69] = 0x02;
430 pci_conf[0x70] = 0x80;
431 pci_conf[0x76] = 0x0c;
432 pci_conf[0x77] = 0x0c;
433 pci_conf[0x78] = 0x02;
434 pci_conf[0x79] = 0x00;
435 pci_conf[0x80] = 0x00;
436 pci_conf[0x82] = 0x02; /* Get rid of the Linux guest "Enabling Passive Release" PCI quirk warning. */
437 pci_conf[0xa0] = 0x08;
438 pci_conf[0xa2] = 0x00;
439 pci_conf[0xa3] = 0x00;
440 pci_conf[0xa4] = 0x00;
441 pci_conf[0xa5] = 0x00;
442 pci_conf[0xa6] = 0x00;
443 pci_conf[0xa7] = 0x00;
444 pci_conf[0xa8] = 0x0f;
445 pci_conf[0xaa] = 0x00;
446 pci_conf[0xab] = 0x00;
447 pci_conf[0xac] = 0x00;
448 pci_conf[0xae] = 0x00;
449}
450
451static void pci_config_writel(PDEVPCIROOT pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t val)
452{
453 pGlobals->uConfigReg = 0x80000000 | (uBus << 16) |
454 (uDevFn << 8) | addr;
455 pci_data_write(pGlobals, 0, val, 4);
456}
457
458static void pci_config_writew(PDEVPCIROOT pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t val)
459{
460 pGlobals->uConfigReg = 0x80000000 | (uBus << 16) |
461 (uDevFn << 8) | (addr & ~3);
462 pci_data_write(pGlobals, addr & 3, val, 2);
463}
464
465static void pci_config_writeb(PDEVPCIROOT pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t val)
466{
467 pGlobals->uConfigReg = 0x80000000 | (uBus << 16) |
468 (uDevFn << 8) | (addr & ~3);
469 pci_data_write(pGlobals, addr & 3, val, 1);
470}
471
472static uint32_t pci_config_readl(PDEVPCIROOT pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr)
473{
474 pGlobals->uConfigReg = 0x80000000 | (uBus << 16) |
475 (uDevFn << 8) | addr;
476 uint32_t u32Val;
477 int rc = pci_data_read(pGlobals, 0, 4, &u32Val);
478 AssertRC(rc);
479 return u32Val;
480}
481
482static uint32_t pci_config_readw(PDEVPCIROOT pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr)
483{
484 pGlobals->uConfigReg = 0x80000000 | (uBus << 16) |
485 (uDevFn << 8) | (addr & ~3);
486 uint32_t u32Val;
487 int rc = pci_data_read(pGlobals, addr & 3, 2, &u32Val);
488 AssertRC(rc);
489 return u32Val;
490}
491
492static uint32_t pci_config_readb(PDEVPCIROOT pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr)
493{
494 pGlobals->uConfigReg = 0x80000000 | (uBus << 16) |
495 (uDevFn << 8) | (addr & ~3);
496 uint32_t u32Val;
497 int rc = pci_data_read(pGlobals, addr & 3, 1, &u32Val);
498 AssertRC(rc);
499 return u32Val;
500}
501
502/* host irqs corresponding to PCI irqs A-D */
503static const uint8_t pci_irqs[4] = { 11, 9, 11, 9 }; /* bird: added const */
504
505static void pci_set_io_region_addr(PDEVPCIROOT pGlobals, uint8_t uBus, uint8_t uDevFn, int region_num, uint32_t addr)
506{
507 uint32_t ofs;
508
509 if ( region_num == PCI_ROM_SLOT )
510 ofs = 0x30;
511 else
512 ofs = 0x10 + region_num * 4;
513
514 Log(("Set region address: %02x:%02x.%d region %d address=%lld\n",
515 uBus, uDevFn >> 3, uDevFn & 7, region_num, addr));
516
517 /* Write address of the device. */
518 pci_config_writel(pGlobals, uBus, uDevFn, ofs, addr);
519}
520
521static void pci_bios_init_device(PDEVPCIROOT pGlobals, uint8_t uBus, uint8_t uDevFn, uint8_t cBridgeDepth, uint8_t *paBridgePositions)
522{
523 uint32_t *paddr;
524 int i, pin, pic_irq;
525 uint16_t devclass, vendor_id, device_id;
526
527 devclass = pci_config_readw(pGlobals, uBus, uDevFn, PCI_CLASS_DEVICE);
528 vendor_id = pci_config_readw(pGlobals, uBus, uDevFn, PCI_VENDOR_ID);
529 device_id = pci_config_readw(pGlobals, uBus, uDevFn, PCI_DEVICE_ID);
530
531 /* Check if device is present. */
532 if (vendor_id != 0xffff)
533 {
534 switch(devclass)
535 {
536 case 0x0101:
537 if ( (vendor_id == 0x8086)
538 && (device_id == 0x7010 || device_id == 0x7111 || device_id == 0x269e))
539 {
540 /* PIIX3, PIIX4 or ICH6 IDE */
541 pci_config_writew(pGlobals, uBus, uDevFn, 0x40, 0x8000); /* enable IDE0 */
542 pci_config_writew(pGlobals, uBus, uDevFn, 0x42, 0x8000); /* enable IDE1 */
543 goto default_map;
544 }
545 else
546 {
547 /* IDE: we map it as in ISA mode */
548 pci_set_io_region_addr(pGlobals, uBus, uDevFn, 0, 0x1f0);
549 pci_set_io_region_addr(pGlobals, uBus, uDevFn, 1, 0x3f4);
550 pci_set_io_region_addr(pGlobals, uBus, uDevFn, 2, 0x170);
551 pci_set_io_region_addr(pGlobals, uBus, uDevFn, 3, 0x374);
552 pci_config_writeb(pGlobals, uBus, uDevFn, PCI_COMMAND,
553 pci_config_readb(pGlobals, uBus, uDevFn, PCI_COMMAND)
554 | PCI_COMMAND_IOACCESS);
555 }
556 break;
557 case 0x0300:
558 if (vendor_id != 0x80ee)
559 goto default_map;
560 /* VGA: map frame buffer to default Bochs VBE address */
561 pci_set_io_region_addr(pGlobals, uBus, uDevFn, 0, 0xE0000000);
562 /*
563 * Legacy VGA I/O ports are implicitly decoded by a VGA class device. But
564 * only the framebuffer (i.e., a memory region) is explicitly registered via
565 * pci_set_io_region_addr, so don't forget to enable I/O decoding.
566 */
567 pci_config_writeb(pGlobals, uBus, uDevFn, PCI_COMMAND,
568 pci_config_readb(pGlobals, uBus, uDevFn, PCI_COMMAND)
569 | PCI_COMMAND_IOACCESS | PCI_COMMAND_MEMACCESS);
570 break;
571 case 0x0800:
572 /* PIC */
573 vendor_id = pci_config_readw(pGlobals, uBus, uDevFn, PCI_VENDOR_ID);
574 device_id = pci_config_readw(pGlobals, uBus, uDevFn, PCI_DEVICE_ID);
575 if (vendor_id == 0x1014)
576 {
577 /* IBM */
578 if (device_id == 0x0046 || device_id == 0xFFFF)
579 {
580 /* MPIC & MPIC2 */
581 pci_set_io_region_addr(pGlobals, uBus, uDevFn, 0, 0x80800000 + 0x00040000);
582 pci_config_writeb(pGlobals, uBus, uDevFn, PCI_COMMAND,
583 pci_config_readb(pGlobals, uBus, uDevFn, PCI_COMMAND)
584 | PCI_COMMAND_MEMACCESS);
585 }
586 }
587 break;
588 case 0xff00:
589 if ( (vendor_id == 0x0106b)
590 && (device_id == 0x0017 || device_id == 0x0022))
591 {
592 /* macio bridge */
593 pci_set_io_region_addr(pGlobals, uBus, uDevFn, 0, 0x80800000);
594 pci_config_writeb(pGlobals, uBus, uDevFn, PCI_COMMAND,
595 pci_config_readb(pGlobals, uBus, uDevFn, PCI_COMMAND)
596 | PCI_COMMAND_MEMACCESS);
597 }
598 break;
599 case 0x0604:
600 {
601 /* Init PCI-to-PCI bridge. */
602 pci_config_writeb(pGlobals, uBus, uDevFn, VBOX_PCI_PRIMARY_BUS, uBus);
603
604 AssertMsg(pGlobals->uPciBiosBus < 255, ("Too many bridges on the bus\n"));
605 pGlobals->uPciBiosBus++;
606 pci_config_writeb(pGlobals, uBus, uDevFn, VBOX_PCI_SECONDARY_BUS, pGlobals->uPciBiosBus);
607 pci_config_writeb(pGlobals, uBus, uDevFn, VBOX_PCI_SUBORDINATE_BUS, 0xff); /* Temporary until we know how many other bridges are behind this one. */
608
609 /* Add position of this bridge into the array. */
610 paBridgePositions[cBridgeDepth+1] = (uDevFn >> 3);
611
612 /*
613 * The I/O range for the bridge must be aligned to a 4KB boundary.
614 * This does not change anything really as the access to the device is not going
615 * through the bridge but we want to be compliant to the spec.
616 */
617 if ((pGlobals->uPciBiosIo % _4K) != 0)
618 pGlobals->uPciBiosIo = RT_ALIGN_32(pGlobals->uPciBiosIo, _4K);
619 LogFunc(("Aligned I/O start address. New address %#x\n", pGlobals->uPciBiosIo));
620 pci_config_writeb(pGlobals, uBus, uDevFn, VBOX_PCI_IO_BASE, (pGlobals->uPciBiosIo >> 8) & 0xf0);
621
622 /* The MMIO range for the bridge must be aligned to a 1MB boundary. */
623 if ((pGlobals->uPciBiosMmio % _1M) != 0)
624 pGlobals->uPciBiosMmio = RT_ALIGN_32(pGlobals->uPciBiosMmio, _1M);
625 LogFunc(("Aligned MMIO start address. New address %#x\n", pGlobals->uPciBiosMmio));
626 pci_config_writew(pGlobals, uBus, uDevFn, VBOX_PCI_MEMORY_BASE, (pGlobals->uPciBiosMmio >> 16) & UINT32_C(0xffff0));
627
628 /* Save values to compare later to. */
629 uint32_t u32IoAddressBase = pGlobals->uPciBiosIo;
630 uint32_t u32MMIOAddressBase = pGlobals->uPciBiosMmio;
631
632 /* Init devices behind the bridge and possibly other bridges as well. */
633 for (int iDev = 0; iDev <= 255; iDev++)
634 pci_bios_init_device(pGlobals, uBus + 1, iDev, cBridgeDepth + 1, paBridgePositions);
635
636 /* The number of bridges behind the this one is now available. */
637 pci_config_writeb(pGlobals, uBus, uDevFn, VBOX_PCI_SUBORDINATE_BUS, pGlobals->uPciBiosBus);
638
639 /*
640 * Set I/O limit register. If there is no device with I/O space behind the bridge
641 * we set a lower value than in the base register.
642 * The result with a real bridge is that no I/O transactions are passed to the secondary
643 * interface. Again this doesn't really matter here but we want to be compliant to the spec.
644 */
645 if ((u32IoAddressBase != pGlobals->uPciBiosIo) && ((pGlobals->uPciBiosIo % _4K) != 0))
646 {
647 /* The upper boundary must be one byte less than a 4KB boundary. */
648 pGlobals->uPciBiosIo = RT_ALIGN_32(pGlobals->uPciBiosIo, _4K);
649 }
650 pci_config_writeb(pGlobals, uBus, uDevFn, VBOX_PCI_IO_LIMIT, ((pGlobals->uPciBiosIo >> 8) & 0xf0) - 1);
651
652 /* Same with the MMIO limit register but with 1MB boundary here. */
653 if ((u32MMIOAddressBase != pGlobals->uPciBiosMmio) && ((pGlobals->uPciBiosMmio % _1M) != 0))
654 {
655 /* The upper boundary must be one byte less than a 1MB boundary. */
656 pGlobals->uPciBiosMmio = RT_ALIGN_32(pGlobals->uPciBiosMmio, _1M);
657 }
658 pci_config_writew(pGlobals, uBus, uDevFn, VBOX_PCI_MEMORY_LIMIT, ((pGlobals->uPciBiosMmio >> 16) & UINT32_C(0xfff0)) - 1);
659
660 /*
661 * Set the prefetch base and limit registers. We currently have no device with a prefetchable region
662 * which may be behind a bridge. That's why it is unconditionally disabled here atm by writing a higher value into
663 * the base register than in the limit register.
664 */
665 pci_config_writew(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_MEMORY_BASE, 0xfff0);
666 pci_config_writew(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_MEMORY_LIMIT, 0x0);
667 pci_config_writel(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_BASE_UPPER32, 0x00);
668 pci_config_writel(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_LIMIT_UPPER32, 0x00);
669 break;
670 }
671 default:
672 default_map:
673 {
674 /* default memory mappings */
675 bool fActiveMemRegion = false;
676 bool fActiveIORegion = false;
677 /*
678 * PCI_NUM_REGIONS is 7 because of the rom region but there are only 6 base address register defined by the PCI spec.
679 * Leaving only PCI_NUM_REGIONS would cause reading another and enabling a memory region which does not exist.
680 */
681 for(i = 0; i < (PCI_NUM_REGIONS-1); i++)
682 {
683 uint32_t u32Size;
684 uint8_t u8RessourceType;
685 uint32_t u32Address = 0x10 + i * 4;
686
687 /* Calculate size. */
688 u8RessourceType = pci_config_readb(pGlobals, uBus, uDevFn, u32Address);
689 pci_config_writel(pGlobals, uBus, uDevFn, u32Address, UINT32_C(0xffffffff));
690 u32Size = pci_config_readl(pGlobals, uBus, uDevFn, u32Address);
691 bool fIsPio = ((u8RessourceType & PCI_COMMAND_IOACCESS) == PCI_COMMAND_IOACCESS);
692 /* Clear resource information depending on resource type. */
693 if (fIsPio) /* I/O */
694 u32Size &= ~(0x01);
695 else /* MMIO */
696 u32Size &= ~(0x0f);
697
698 /*
699 * Invert all bits and add 1 to get size of the region.
700 * (From PCI implementation note)
701 */
702 if (fIsPio && (u32Size & UINT32_C(0xffff0000)) == 0)
703 u32Size = (~(u32Size | UINT32_C(0xffff0000))) + 1;
704 else
705 u32Size = (~u32Size) + 1;
706
707 Log2Func(("Size of region %u for device %d on bus %d is %u\n", i, uDevFn, uBus, u32Size));
708
709 if (u32Size)
710 {
711 if (fIsPio)
712 paddr = &pGlobals->uPciBiosIo;
713 else
714 paddr = &pGlobals->uPciBiosMmio;
715 uint32_t uNew = *paddr;
716 uNew = (uNew + u32Size - 1) & ~(u32Size - 1);
717 if (fIsPio)
718 uNew &= UINT32_C(0xffff);
719 /* Unconditionally exclude I/O-APIC/HPET/ROM. Pessimistic, but better than causing a mess. */
720 if (!uNew || (uNew <= UINT32_C(0xffffffff) && uNew + u32Size - 1 >= UINT32_C(0xfec00000)))
721 {
722 LogRel(("PCI: no space left for BAR%u of device %u/%u/%u (vendor=%#06x device=%#06x)\n",
723 i, uBus, uDevFn >> 3, uDevFn & 7, vendor_id, device_id)); /** @todo make this a VM start failure later. */
724 /* Undo the mapping mess caused by the size probing. */
725 pci_config_writel(pGlobals, uBus, uDevFn, u32Address, UINT32_C(0));
726 }
727 else
728 {
729 LogFunc(("Start address of %s region %u is %#x\n", (fIsPio ? "I/O" : "MMIO"), i, uNew));
730 pci_set_io_region_addr(pGlobals, uBus, uDevFn, i, uNew);
731 if (fIsPio)
732 fActiveIORegion = true;
733 else
734 fActiveMemRegion = true;
735 *paddr = uNew + u32Size;
736 Log2Func(("New address is %#x\n", *paddr));
737 }
738 }
739 }
740
741 /* Update the command word appropriately. */
742 pci_config_writeb(pGlobals, uBus, uDevFn, PCI_COMMAND,
743 pci_config_readb(pGlobals, uBus, uDevFn, PCI_COMMAND)
744 | (fActiveMemRegion ? PCI_COMMAND_MEMACCESS : 0)
745 | (fActiveIORegion ? PCI_COMMAND_IOACCESS : 0));
746
747 break;
748 }
749 }
750
751 /* map the interrupt */
752 pin = pci_config_readb(pGlobals, uBus, uDevFn, PCI_INTERRUPT_PIN);
753 if (pin != 0)
754 {
755 uint8_t uBridgeDevFn = uDevFn;
756 pin--;
757
758 /* We need to go up to the host bus to see which irq this device will assert there. */
759 while (cBridgeDepth != 0)
760 {
761 /* Get the pin the device would assert on the bridge. */
762 pin = ((uBridgeDevFn >> 3) + pin) & 3;
763 uBridgeDevFn = paBridgePositions[cBridgeDepth];
764 cBridgeDepth--;
765 }
766
767 pin = pci_slot_get_pirq(uDevFn, pin);
768 pic_irq = pci_irqs[pin];
769 pci_config_writeb(pGlobals, uBus, uDevFn, PCI_INTERRUPT_LINE, pic_irq);
770 }
771 }
772}
773
774/**
775 * Worker for Fake PCI BIOS config, triggered by magic port access by BIOS.
776 *
777 * @returns VBox status code.
778 *
779 * @param pDevIns i440FX device instance.
780 */
781static int pciR3FakePCIBIOS(PPDMDEVINS pDevIns)
782{
783 unsigned i;
784 uint8_t elcr[2] = {0, 0};
785 PDEVPCIROOT pGlobals = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
786 PVM pVM = PDMDevHlpGetVM(pDevIns); Assert(pVM);
787 PVMCPU pVCpu = PDMDevHlpGetVMCPU(pDevIns); Assert(pVM);
788 uint32_t const cbBelow4GB = MMR3PhysGetRamSizeBelow4GB(pVM);
789 uint64_t const cbAbove4GB = MMR3PhysGetRamSizeAbove4GB(pVM);
790 RT_NOREF(cbBelow4GB, cbAbove4GB);
791
792 LogRel(("PCI: setting up resources and interrupts\n"));
793
794 /*
795 * Set the start addresses.
796 */
797 pGlobals->uPciBiosBus = 0;
798 pGlobals->uPciBiosIo = 0xd000;
799 pGlobals->uPciBiosMmio = UINT32_C(0xf0000000);
800
801 /*
802 * Activate IRQ mappings.
803 */
804 for (i = 0; i < 4; i++)
805 {
806 uint8_t irq = pci_irqs[i];
807 /* Set to trigger level. */
808 elcr[irq >> 3] |= (1 << (irq & 7));
809 /* Activate irq remapping in PIIX3. */
810 pci_config_writeb(pGlobals, 0, pGlobals->Piix3.PIIX3State.dev.uDevFn, 0x60 + i, irq);
811 }
812
813 /* Tell to the PIC. */
814 VBOXSTRICTRC rcStrict = IOMIOPortWrite(pVM, pVCpu, 0x4d0, elcr[0], sizeof(uint8_t));
815 if (rcStrict == VINF_SUCCESS)
816 rcStrict = IOMIOPortWrite(pVM, pVCpu, 0x4d1, elcr[1], sizeof(uint8_t));
817 if (rcStrict != VINF_SUCCESS)
818 {
819 AssertMsgFailed(("Writing to PIC failed! rcStrict=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
820 return RT_SUCCESS(rcStrict) ? VERR_INTERNAL_ERROR : VBOXSTRICTRC_VAL(rcStrict);
821 }
822
823 /*
824 * Init the devices.
825 */
826 for (i = 0; i < 256; i++)
827 {
828 uint8_t aBridgePositions[256];
829
830 memset(aBridgePositions, 0, sizeof(aBridgePositions));
831 Log2(("PCI: Initializing device %d (%#x)\n",
832 i, 0x80000000 | (i << 8)));
833 pci_bios_init_device(pGlobals, 0, i, 0, aBridgePositions);
834 }
835
836 return VINF_SUCCESS;
837}
838
839#endif /* IN_RING3 */
840
841
842/* -=-=-=-=-=- I/O ports -=-=-=-=-=- */
843
844/**
845 * @callback_method_impl{FNIOMIOPORTOUT, PCI address}
846 */
847PDMBOTHCBDECL(int) pciIOPortAddressWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
848{
849 LogFunc(("Port=%#x u32=%#x cb=%d\n", Port, u32, cb));
850 RT_NOREF2(Port, pvUser);
851 if (cb == 4)
852 {
853 PDEVPCIROOT pThis = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
854 PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_WRITE);
855 pThis->uConfigReg = u32 & ~3; /* Bits 0-1 are reserved and we silently clear them */
856 PCI_UNLOCK(pDevIns);
857 }
858 /* else: 440FX does "pass through to the bus" for other writes, what ever that means.
859 * Linux probes for cmd640 using byte writes/reads during ide init. We'll just ignore it. */
860 return VINF_SUCCESS;
861}
862
863
864/**
865 * @callback_method_impl{FNIOMIOPORTIN, PCI address}
866 */
867PDMBOTHCBDECL(int) pciIOPortAddressRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
868{
869 RT_NOREF2(Port, pvUser);
870 if (cb == 4)
871 {
872 PDEVPCIROOT pThis = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
873 PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_READ);
874 *pu32 = pThis->uConfigReg;
875 PCI_UNLOCK(pDevIns);
876 LogFunc(("Port=%#x cb=%d -> %#x\n", Port, cb, *pu32));
877 return VINF_SUCCESS;
878 }
879 /* else: 440FX does "pass through to the bus" for other writes, what ever that means.
880 * Linux probes for cmd640 using byte writes/reads during ide init. We'll just ignore it. */
881 LogFunc(("Port=%#x cb=%d VERR_IOM_IOPORT_UNUSED\n", Port, cb));
882 return VERR_IOM_IOPORT_UNUSED;
883}
884
885
886/**
887 * @callback_method_impl{FNIOMIOPORTOUT, PCI data}
888 */
889PDMBOTHCBDECL(int) pciIOPortDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
890{
891 LogFunc(("Port=%#x u32=%#x cb=%d\n", Port, u32, cb));
892 NOREF(pvUser);
893 int rc = VINF_SUCCESS;
894 if (!(Port % cb))
895 {
896 PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_WRITE);
897 rc = pci_data_write(PDMINS_2_DATA(pDevIns, PDEVPCIROOT), Port, u32, cb);
898 PCI_UNLOCK(pDevIns);
899 }
900 else
901 AssertMsgFailed(("Write to port %#x u32=%#x cb=%d\n", Port, u32, cb));
902 return rc;
903}
904
905
906/**
907 * @callback_method_impl{FNIOMIOPORTIN, PCI data}
908 */
909PDMBOTHCBDECL(int) pciIOPortDataRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
910{
911 NOREF(pvUser);
912 if (!(Port % cb))
913 {
914 PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_READ);
915 int rc = pci_data_read(PDMINS_2_DATA(pDevIns, PDEVPCIROOT), Port, cb, pu32);
916 PCI_UNLOCK(pDevIns);
917 LogFunc(("Port=%#x cb=%#x -> %#x (%Rrc)\n", Port, cb, *pu32, rc));
918 return rc;
919 }
920 AssertMsgFailed(("Read from port %#x cb=%d\n", Port, cb));
921 return VERR_IOM_IOPORT_UNUSED;
922}
923
924#ifdef IN_RING3
925
926/**
927 * @callback_method_impl{FNIOMIOPORTOUT, PCI data}
928 */
929DECLCALLBACK(int) pciR3IOPortMagicPCIWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
930{
931 RT_NOREF2(pvUser, Port);
932 LogFunc(("Port=%#x u32=%#x cb=%d\n", Port, u32, cb));
933 if (cb == 4)
934 {
935 if (u32 == UINT32_C(19200509)) // Richard Adams
936 {
937 int rc = pciR3FakePCIBIOS(pDevIns);
938 AssertRC(rc);
939 }
940 }
941
942 return VINF_SUCCESS;
943}
944
945/**
946 * @callback_method_impl{FNIOMIOPORTIN, PCI data}
947 */
948DECLCALLBACK(int) pciR3IOPortMagicPCIRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
949{
950 RT_NOREF5(pDevIns, pvUser, Port, pu32, cb);
951 LogFunc(("Port=%#x cb=%d VERR_IOM_IOPORT_UNUSED\n", Port, cb));
952 return VERR_IOM_IOPORT_UNUSED;
953}
954
955
956/*
957 * Include code we share with the other PCI bus implementation.
958 *
959 * Note! No #ifdefs, use instant data booleans/flags/whatever. Goal is to
960 * completely merge these files! File #1 contains code we write, where
961 * as a possible file #2 contains external code if there's any left.
962 */
963# include "DevPciMerge1.cpp.h"
964
965
966/* -=-=-=-=-=- Saved state -=-=-=-=-=- */
967
968/**
969 * Common worker for pciR3SaveExec and pcibridgeR3SaveExec.
970 *
971 * @returns VBox status code.
972 * @param pBus The bus to save.
973 * @param pSSM The saved state handle.
974 */
975static int pciR3CommonSaveExec(PDEVPCIBUS pBus, PSSMHANDLE pSSM)
976{
977 /*
978 * Iterate thru all the devices.
979 */
980 for (uint32_t i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
981 {
982 PPDMPCIDEV pDev = pBus->apDevices[i];
983 if (pDev)
984 {
985 SSMR3PutU32(pSSM, i);
986 SSMR3PutMem(pSSM, pDev->abConfig, sizeof(pDev->abConfig));
987
988 SSMR3PutS32(pSSM, pDev->Int.s.uIrqPinState);
989
990 /* Save the type an size of all the regions. */
991 for (uint32_t iRegion = 0; iRegion < VBOX_PCI_NUM_REGIONS; iRegion++)
992 {
993 SSMR3PutU8(pSSM, pDev->Int.s.aIORegions[iRegion].type);
994 SSMR3PutU64(pSSM, pDev->Int.s.aIORegions[iRegion].size);
995 }
996 }
997 }
998 return SSMR3PutU32(pSSM, UINT32_MAX); /* terminator */
999}
1000
1001
1002/**
1003 * @callback_method_impl{FNSSMDEVSAVEEXEC}
1004 */
1005static DECLCALLBACK(int) pciR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
1006{
1007 uint32_t i;
1008 PDEVPCIROOT pThis = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
1009
1010 /*
1011 * Bus state data.
1012 */
1013 SSMR3PutU32(pSSM, pThis->uConfigReg);
1014 SSMR3PutBool(pSSM, pThis->fUseIoApic);
1015
1016 /*
1017 * Save IRQ states.
1018 */
1019 for (i = 0; i < RT_ELEMENTS(pThis->Piix3.auPciLegacyIrqLevels); i++)
1020 SSMR3PutU32(pSSM, pThis->Piix3.auPciLegacyIrqLevels[i]);
1021 for (i = 0; i < RT_ELEMENTS(pThis->auPciApicIrqLevels); i++)
1022 SSMR3PutU32(pSSM, pThis->auPciApicIrqLevels[i]);
1023
1024 SSMR3PutU32(pSSM, pThis->Piix3.iAcpiIrqLevel);
1025 SSMR3PutS32(pSSM, pThis->Piix3.iAcpiIrq);
1026
1027 SSMR3PutU32(pSSM, UINT32_MAX); /* separator */
1028
1029 /*
1030 * Join paths with pcibridgeR3SaveExec.
1031 */
1032 return pciR3CommonSaveExec(&pThis->PciBus, pSSM);
1033}
1034
1035
1036/**
1037 * Common worker for pciR3LoadExec and pcibridgeR3LoadExec.
1038 *
1039 * @returns VBox status code.
1040 * @param pBus The bus which data is being loaded.
1041 * @param pSSM The saved state handle.
1042 * @param uVersion The data version.
1043 * @param uPass The pass.
1044 */
1045static DECLCALLBACK(int) pciR3CommonLoadExec(PDEVPCIBUS pBus, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1046{
1047 uint32_t u32;
1048 uint32_t i;
1049 int rc;
1050
1051 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
1052
1053 /*
1054 * Iterate thru all the devices and write 0 to the COMMAND register so
1055 * that all the memory is unmapped before we start restoring the saved
1056 * mapping locations.
1057 *
1058 * The register value is restored afterwards so we can do proper
1059 * LogRels in devpciR3CommonRestoreConfig.
1060 */
1061 for (i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
1062 {
1063 PPDMPCIDEV pDev = pBus->apDevices[i];
1064 if (pDev)
1065 {
1066 uint16_t u16 = PCIDevGetCommand(pDev);
1067 pDev->Int.s.pfnConfigWrite(pDev->Int.s.CTX_SUFF(pDevIns), pDev, VBOX_PCI_COMMAND, 0, 2);
1068 PCIDevSetCommand(pDev, u16);
1069 Assert(PCIDevGetCommand(pDev) == u16);
1070 }
1071 }
1072
1073 /*
1074 * Iterate all the devices.
1075 */
1076 for (i = 0;; i++)
1077 {
1078 /* index / terminator */
1079 rc = SSMR3GetU32(pSSM, &u32);
1080 if (RT_FAILURE(rc))
1081 return rc;
1082 if (u32 == UINT32_MAX)
1083 break;
1084 if ( u32 >= RT_ELEMENTS(pBus->apDevices)
1085 || u32 < i)
1086 {
1087 AssertMsgFailed(("u32=%#x i=%#x\n", u32, i));
1088 return rc;
1089 }
1090
1091 /* skip forward to the device checking that no new devices are present. */
1092 for (; i < u32; i++)
1093 {
1094 if (pBus->apDevices[i])
1095 {
1096 LogRel(("PCI: New device in slot %#x, %s (vendor=%#06x device=%#06x)\n", i, pBus->apDevices[i]->pszNameR3,
1097 PCIDevGetVendorId(pBus->apDevices[i]), PCIDevGetDeviceId(pBus->apDevices[i])));
1098 if (SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT)
1099 return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("New device in slot %#x, %s (vendor=%#06x device=%#06x)"),
1100 i, pBus->apDevices[i]->pszNameR3, PCIDevGetVendorId(pBus->apDevices[i]), PCIDevGetDeviceId(pBus->apDevices[i]));
1101 }
1102 }
1103
1104 /* get the data */
1105 PDMPCIDEV DevTmp;
1106 RT_ZERO(DevTmp);
1107 DevTmp.Int.s.uIrqPinState = ~0; /* Invalid value in case we have an older saved state to force a state change in pciSetIrq. */
1108 SSMR3GetMem(pSSM, DevTmp.abConfig, sizeof(DevTmp.abConfig));
1109 if (uVersion < VBOX_PCI_SAVED_STATE_VERSION_IRQ_STATES)
1110 {
1111 int32_t i32Temp;
1112 /* Irq value not needed anymore. */
1113 rc = SSMR3GetS32(pSSM, &i32Temp);
1114 if (RT_FAILURE(rc))
1115 return rc;
1116 }
1117 else
1118 {
1119 rc = SSMR3GetS32(pSSM, &DevTmp.Int.s.uIrqPinState);
1120 if (RT_FAILURE(rc))
1121 return rc;
1122 }
1123
1124 /* Load the region types and sizes. */
1125 if (uVersion >= VBOX_PCI_SAVED_STATE_VERSION_REGION_SIZES)
1126 {
1127 for (uint32_t iRegion = 0; iRegion < VBOX_PCI_NUM_REGIONS; iRegion++)
1128 {
1129 SSMR3GetU8(pSSM, &DevTmp.Int.s.aIORegions[iRegion].type);
1130 rc = SSMR3GetU64(pSSM, &DevTmp.Int.s.aIORegions[iRegion].size);
1131 AssertLogRelRCReturn(rc, rc);
1132 }
1133 }
1134
1135 /* check that it's still around. */
1136 PPDMPCIDEV pDev = pBus->apDevices[i];
1137 if (!pDev)
1138 {
1139 LogRel(("PCI: Device in slot %#x has been removed! vendor=%#06x device=%#06x\n", i,
1140 PCIDevGetVendorId(&DevTmp), PCIDevGetDeviceId(&DevTmp)));
1141 if (SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT)
1142 return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Device in slot %#x has been removed! vendor=%#06x device=%#06x"),
1143 i, PCIDevGetVendorId(&DevTmp), PCIDevGetDeviceId(&DevTmp));
1144 continue;
1145 }
1146
1147 /* match the vendor id assuming that this will never be changed. */
1148 if ( DevTmp.abConfig[0] != pDev->abConfig[0]
1149 || DevTmp.abConfig[1] != pDev->abConfig[1])
1150 return SSMR3SetCfgError(pSSM, RT_SRC_POS,
1151 N_("Device in slot %#x (%s) vendor id mismatch! saved=%.4Rhxs current=%.4Rhxs"),
1152 i, pDev->pszNameR3, DevTmp.abConfig, pDev->abConfig);
1153
1154 /* commit the loaded device config. */
1155 rc = devpciR3CommonRestoreRegions(pSSM, pDev, DevTmp.Int.s.aIORegions,
1156 uVersion >= VBOX_PCI_SAVED_STATE_VERSION_REGION_SIZES);
1157 if (RT_FAILURE(rc))
1158 break;
1159 devpciR3CommonRestoreConfig(pDev, &DevTmp.abConfig[0]);
1160
1161 pDev->Int.s.uIrqPinState = DevTmp.Int.s.uIrqPinState;
1162 }
1163
1164 return VINF_SUCCESS;
1165}
1166
1167
1168/**
1169 * @callback_method_impl{FNSSMDEVLOADEXEC}
1170 */
1171static DECLCALLBACK(int) pciR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1172{
1173 PDEVPCIROOT pThis = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
1174 PDEVPCIBUS pBus = &pThis->PciBus;
1175 uint32_t u32;
1176 int rc;
1177
1178 /*
1179 * Check the version.
1180 */
1181 if (uVersion > VBOX_PCI_SAVED_STATE_VERSION)
1182 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1183 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
1184
1185 /*
1186 * Bus state data.
1187 */
1188 SSMR3GetU32(pSSM, &pThis->uConfigReg);
1189 if (uVersion >= VBOX_PCI_SAVED_STATE_VERSION_USE_IO_APIC)
1190 SSMR3GetBool(pSSM, &pThis->fUseIoApic);
1191
1192 /* Load IRQ states. */
1193 if (uVersion >= VBOX_PCI_SAVED_STATE_VERSION_IRQ_STATES)
1194 {
1195 for (uint8_t i = 0; i < RT_ELEMENTS(pThis->Piix3.auPciLegacyIrqLevels); i++)
1196 SSMR3GetU32(pSSM, (uint32_t *)&pThis->Piix3.auPciLegacyIrqLevels[i]);
1197 for (uint8_t i = 0; i < RT_ELEMENTS(pThis->auPciApicIrqLevels); i++)
1198 SSMR3GetU32(pSSM, (uint32_t *)&pThis->auPciApicIrqLevels[i]);
1199
1200 SSMR3GetU32(pSSM, &pThis->Piix3.iAcpiIrqLevel);
1201 SSMR3GetS32(pSSM, &pThis->Piix3.iAcpiIrq);
1202 }
1203
1204 /* separator */
1205 rc = SSMR3GetU32(pSSM, &u32);
1206 if (RT_FAILURE(rc))
1207 return rc;
1208 if (u32 != UINT32_MAX)
1209 AssertMsgFailedReturn(("u32=%#x\n", u32), rc);
1210
1211 /*
1212 * The devices.
1213 */
1214 return pciR3CommonLoadExec(pBus, pSSM, uVersion, uPass);
1215}
1216
1217
1218/* -=-=-=-=-=- PCI Bus Interface Methods (PDMPCIBUSREG) -=-=-=-=-=- */
1219
1220
1221/* -=-=-=-=-=- Debug Info Handlers -=-=-=-=-=- */
1222
1223/**
1224 * @callback_method_impl{FNDBGFHANDLERDEV}
1225 */
1226static DECLCALLBACK(void) pciR3IrqRouteInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
1227{
1228 PDEVPCIROOT pGlobals = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
1229 NOREF(pszArgs);
1230
1231 uint16_t router = pGlobals->Piix3.PIIX3State.dev.uDevFn;
1232 pHlp->pfnPrintf(pHlp, "PCI interrupt router at: %02X:%02X:%X\n",
1233 router >> 8, (router >> 3) & 0x1f, router & 0x7);
1234
1235 for (int i = 0; i < 4; ++i)
1236 {
1237 uint8_t irq_map = pci_config_readb(pGlobals, 0, router, 0x60 + i);
1238 if (irq_map & 0x80)
1239 pHlp->pfnPrintf(pHlp, "PIRQ%c disabled\n", 'A' + i);
1240 else
1241 pHlp->pfnPrintf(pHlp, "PIRQ%c -> IRQ%d\n", 'A' + i, irq_map & 0xf);
1242 }
1243}
1244
1245
1246/* -=-=-=-=-=- PDMDEVREG -=-=-=-=-=- */
1247
1248
1249/**
1250 * @interface_method_impl{PDMDEVREG,pfnConstruct}
1251 */
1252static DECLCALLBACK(int) pciR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
1253{
1254 RT_NOREF1(iInstance);
1255 Assert(iInstance == 0);
1256 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
1257
1258 /*
1259 * Validate and read configuration.
1260 */
1261 if (!CFGMR3AreValuesValid(pCfg, "IOAPIC\0" "GCEnabled\0" "R0Enabled\0"))
1262 return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
1263
1264 /* query whether we got an IOAPIC */
1265 bool fUseIoApic;
1266 int rc = CFGMR3QueryBoolDef(pCfg, "IOAPIC", &fUseIoApic, false);
1267 if (RT_FAILURE(rc))
1268 return PDMDEV_SET_ERROR(pDevIns, rc,
1269 N_("Configuration error: Failed to query boolean value \"IOAPIC\""));
1270
1271 /* check if RC code is enabled. */
1272 bool fGCEnabled;
1273 rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
1274 if (RT_FAILURE(rc))
1275 return PDMDEV_SET_ERROR(pDevIns, rc,
1276 N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
1277
1278 /* check if R0 code is enabled. */
1279 bool fR0Enabled;
1280 rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
1281 if (RT_FAILURE(rc))
1282 return PDMDEV_SET_ERROR(pDevIns, rc,
1283 N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
1284 Log(("PCI: fUseIoApic=%RTbool fGCEnabled=%RTbool fR0Enabled=%RTbool\n", fUseIoApic, fGCEnabled, fR0Enabled));
1285
1286 /*
1287 * Init data and register the PCI bus.
1288 */
1289 PDEVPCIROOT pGlobals = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
1290 pGlobals->uPciBiosIo = 0xc000;
1291 pGlobals->uPciBiosMmio = 0xf0000000;
1292 memset((void *)&pGlobals->Piix3.auPciLegacyIrqLevels, 0, sizeof(pGlobals->Piix3.auPciLegacyIrqLevels));
1293 pGlobals->fUseIoApic = fUseIoApic;
1294 memset((void *)&pGlobals->auPciApicIrqLevels, 0, sizeof(pGlobals->auPciApicIrqLevels));
1295
1296 pGlobals->pDevInsR3 = pDevIns;
1297 pGlobals->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
1298 pGlobals->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
1299
1300 pGlobals->PciBus.fTypePiix3 = true;
1301 pGlobals->PciBus.fTypeIch9 = false;
1302 pGlobals->PciBus.fPureBridge = false;
1303 pGlobals->PciBus.pDevInsR3 = pDevIns;
1304 pGlobals->PciBus.pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
1305 pGlobals->PciBus.pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
1306 pGlobals->PciBus.papBridgesR3 = (PPDMPCIDEV *)PDMDevHlpMMHeapAllocZ(pDevIns,
1307 sizeof(PPDMPCIDEV)
1308 * RT_ELEMENTS(pGlobals->PciBus.apDevices));
1309 AssertLogRelReturn(pGlobals->PciBus.papBridgesR3, VERR_NO_MEMORY);
1310
1311
1312 PDMPCIBUSREG PciBusReg;
1313 PDEVPCIBUS pBus = &pGlobals->PciBus;
1314 PciBusReg.u32Version = PDM_PCIBUSREG_VERSION;
1315 PciBusReg.pfnRegisterR3 = pciR3MergedRegister;
1316 PciBusReg.pfnRegisterMsiR3 = NULL;
1317 PciBusReg.pfnIORegionRegisterR3 = devpciR3CommonIORegionRegister;
1318 PciBusReg.pfnSetConfigCallbacksR3 = devpciR3CommonSetConfigCallbacks;
1319 PciBusReg.pfnSetIrqR3 = pciSetIrq;
1320 PciBusReg.pszSetIrqRC = fGCEnabled ? "pciSetIrq" : NULL;
1321 PciBusReg.pszSetIrqR0 = fR0Enabled ? "pciSetIrq" : NULL;
1322#if PDM_DEVHLPR3_VERSION >= PDM_VERSION_MAKE_PP(0xffe7, 20, 0)
1323 rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBus->pPciHlpR3, &pBus->iBus);
1324#else
1325 rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBus->pPciHlpR3);
1326 pBus->iBus = rc;
1327#endif
1328 if (RT_FAILURE(rc))
1329 return PDMDEV_SET_ERROR(pDevIns, rc,
1330 N_("Failed to register ourselves as a PCI Bus"));
1331 Assert(pBus->iBus == 0);
1332 if (pBus->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
1333 return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
1334 N_("PCI helper version mismatch; got %#x expected %#x"),
1335 pBus->pPciHlpR3->u32Version, PDM_PCIHLPR3_VERSION);
1336
1337 pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
1338 pBus->pPciHlpR0 = pBus->pPciHlpR3->pfnGetR0Helpers(pDevIns);
1339
1340 /* Disable default device locking. */
1341 rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
1342 AssertRCReturn(rc, rc);
1343
1344 /*
1345 * Fill in PCI configs and add them to the bus.
1346 */
1347 /* i440FX */
1348 PCIDevSetVendorId( &pBus->PciDev, 0x8086); /* Intel */
1349 PCIDevSetDeviceId( &pBus->PciDev, 0x1237);
1350 PCIDevSetRevisionId(&pBus->PciDev, 0x02);
1351 PCIDevSetClassSub( &pBus->PciDev, 0x00); /* host2pci */
1352 PCIDevSetClassBase( &pBus->PciDev, 0x06); /* PCI_bridge */
1353 PCIDevSetHeaderType(&pBus->PciDev, 0x00);
1354 rc = PDMDevHlpPCIRegisterEx(pDevIns, &pBus->PciDev, PDMPCIDEVREG_CFG_PRIMARY, 0 /*fFlags*/,
1355 0 /*uPciDevNo*/, 0 /*uPciFunNo*/, "i440FX");
1356 AssertLogRelRCReturn(rc, rc);
1357
1358 /* PIIX3 */
1359 PCIDevSetVendorId( &pGlobals->Piix3.PIIX3State.dev, 0x8086); /* Intel */
1360 PCIDevSetDeviceId( &pGlobals->Piix3.PIIX3State.dev, 0x7000); /* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */
1361 PCIDevSetClassSub( &pGlobals->Piix3.PIIX3State.dev, 0x01); /* PCI_ISA */
1362 PCIDevSetClassBase( &pGlobals->Piix3.PIIX3State.dev, 0x06); /* PCI_bridge */
1363 PCIDevSetHeaderType(&pGlobals->Piix3.PIIX3State.dev, 0x80); /* PCI_multifunction, generic */
1364 rc = PDMDevHlpPCIRegisterEx(pDevIns, &pGlobals->Piix3.PIIX3State.dev, PDMPCIDEVREG_CFG_NEXT, 0 /*fFlags*/,
1365 1 /*uPciDevNo*/, 0 /*uPciFunNo*/, "PIIX3");
1366 AssertLogRelRCReturn(rc, rc);
1367 pciR3Piix3Reset(&pGlobals->Piix3.PIIX3State);
1368
1369 pBus->iDevSearch = 16;
1370
1371 /*
1372 * Register I/O ports and save state.
1373 */
1374 rc = PDMDevHlpIOPortRegister(pDevIns, 0x0cf8, 1, NULL, pciIOPortAddressWrite, pciIOPortAddressRead, NULL, NULL, "i440FX (PCI)");
1375 if (RT_FAILURE(rc))
1376 return rc;
1377 rc = PDMDevHlpIOPortRegister(pDevIns, 0x0cfc, 4, NULL, pciIOPortDataWrite, pciIOPortDataRead, NULL, NULL, "i440FX (PCI)");
1378 if (RT_FAILURE(rc))
1379 return rc;
1380 if (fGCEnabled)
1381 {
1382 rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x0cf8, 1, NIL_RTGCPTR, "pciIOPortAddressWrite", "pciIOPortAddressRead", NULL, NULL, "i440FX (PCI)");
1383 if (RT_FAILURE(rc))
1384 return rc;
1385 rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x0cfc, 4, NIL_RTGCPTR, "pciIOPortDataWrite", "pciIOPortDataRead", NULL, NULL, "i440FX (PCI)");
1386 if (RT_FAILURE(rc))
1387 return rc;
1388 }
1389 if (fR0Enabled)
1390 {
1391 rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x0cf8, 1, NIL_RTR0PTR, "pciIOPortAddressWrite", "pciIOPortAddressRead", NULL, NULL, "i440FX (PCI)");
1392 if (RT_FAILURE(rc))
1393 return rc;
1394 rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x0cfc, 4, NIL_RTR0PTR, "pciIOPortDataWrite", "pciIOPortDataRead", NULL, NULL, "i440FX (PCI)");
1395 if (RT_FAILURE(rc))
1396 return rc;
1397 }
1398
1399 rc = PDMDevHlpIOPortRegister(pDevIns, 0x0410, 1, NULL, pciR3IOPortMagicPCIWrite, pciR3IOPortMagicPCIRead, NULL, NULL, "i440FX (Fake PCI BIOS trigger)")
1400;
1401 if (RT_FAILURE(rc))
1402 return rc;
1403
1404
1405 rc = PDMDevHlpSSMRegisterEx(pDevIns, VBOX_PCI_SAVED_STATE_VERSION, sizeof(*pBus) + 16*128, "pgm",
1406 NULL, NULL, NULL,
1407 NULL, pciR3SaveExec, NULL,
1408 NULL, pciR3LoadExec, NULL);
1409 if (RT_FAILURE(rc))
1410 return rc;
1411
1412 PDMDevHlpDBGFInfoRegister(pDevIns, "pci",
1413 "Display PCI bus status. Recognizes 'basic' or 'verbose' as arguments, defaults to 'basic'.",
1414 devpciR3InfoPci);
1415 PDMDevHlpDBGFInfoRegister(pDevIns, "pciirq", "Display PCI IRQ state. (no arguments)", devpciR3InfoPciIrq);
1416 PDMDevHlpDBGFInfoRegister(pDevIns, "irqroute", "Display PCI IRQ routing. (no arguments)", pciR3IrqRouteInfo);
1417
1418 return VINF_SUCCESS;
1419}
1420
1421
1422/**
1423 * @interface_method_impl{PDMDEVREG,pfnDestruct}
1424 */
1425static DECLCALLBACK(int) pciR3Destruct(PPDMDEVINS pDevIns)
1426{
1427 PDEVPCIROOT pGlobals = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
1428 if (pGlobals->PciBus.papBridgesR3)
1429 {
1430 PDMDevHlpMMHeapFree(pDevIns, pGlobals->PciBus.papBridgesR3);
1431 pGlobals->PciBus.papBridgesR3 = NULL;
1432 }
1433 return VINF_SUCCESS;
1434}
1435
1436
1437/**
1438 * The device registration structure.
1439 */
1440const PDMDEVREG g_DevicePCI =
1441{
1442 /* u32Version */
1443 PDM_DEVREG_VERSION,
1444 /* szName */
1445 "pci",
1446 /* szRCMod */
1447 "VBoxDDRC.rc",
1448 /* szR0Mod */
1449 "VBoxDDR0.r0",
1450 /* pszDescription */
1451 "i440FX PCI bridge and PIIX3 ISA bridge.",
1452 /* fFlags */
1453 PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0,
1454 /* fClass */
1455 PDM_DEVREG_CLASS_BUS_PCI | PDM_DEVREG_CLASS_BUS_ISA,
1456 /* cMaxInstances */
1457 1,
1458 /* cbInstance */
1459 sizeof(DEVPCIROOT),
1460 /* pfnConstruct */
1461 pciR3Construct,
1462 /* pfnDestruct */
1463 pciR3Destruct,
1464 /* pfnRelocate */
1465 devpciR3RootRelocate,
1466 /* pfnMemSetup */
1467 NULL,
1468 /* pfnPowerOn */
1469 NULL,
1470 /* pfnReset */
1471 NULL,
1472 /* pfnSuspend */
1473 NULL,
1474 /* pfnResume */
1475 NULL,
1476 /* pfnAttach */
1477 NULL,
1478 /* pfnDetach */
1479 NULL,
1480 /* pfnQueryInterface */
1481 NULL,
1482 /* pfnInitComplete */
1483 NULL,
1484 /* pfnPowerOff */
1485 NULL,
1486 /* pfnSoftReset */
1487 NULL,
1488 /* u32VersionEnd */
1489 PDM_DEVREG_VERSION
1490
1491};
1492#endif /* IN_RING3 */
1493
1494
1495
1496/* -=-=-=-=-=- The PCI bridge specific bits -=-=-=-=-=- */
1497
1498/**
1499 * @interface_method_impl{PDMPCIBUSREG,pfnSetIrqR3}
1500 */
1501PDMBOTHCBDECL(void) pcibridgeSetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc)
1502{
1503 /*
1504 * The PCI-to-PCI bridge specification defines how the interrupt pins
1505 * are routed from the secondary to the primary bus (see chapter 9).
1506 * iIrq gives the interrupt pin the pci device asserted.
1507 * We change iIrq here according to the spec and call the SetIrq function
1508 * of our parent passing the device which asserted the interrupt instead of the device of the bridge.
1509 */
1510 PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
1511 PPDMPCIDEV pPciDevBus = pPciDev;
1512 int iIrqPinBridge = iIrq;
1513 uint8_t uDevFnBridge = 0;
1514
1515 /* Walk the chain until we reach the host bus. */
1516 do
1517 {
1518 uDevFnBridge = pBus->PciDev.uDevFn;
1519 iIrqPinBridge = ((pPciDevBus->uDevFn >> 3) + iIrqPinBridge) & 3;
1520
1521 /* Get the parent. */
1522 pBus = pBus->PciDev.Int.s.CTX_SUFF(pBus);
1523 pPciDevBus = &pBus->PciDev;
1524 } while (pBus->iBus != 0);
1525
1526 AssertMsg(pBus->iBus == 0, ("This is not the host pci bus iBus=%d\n", pBus->iBus));
1527 pciSetIrqInternal(DEVPCIBUS_2_DEVPCIROOT(pBus), uDevFnBridge, pPciDev, iIrqPinBridge, iLevel, uTagSrc);
1528}
1529
1530#ifdef IN_RING3
1531
1532/**
1533 * @callback_method_impl{FNPCIBRIDGECONFIGWRITE}
1534 */
1535static DECLCALLBACK(void) pcibridgeR3ConfigWrite(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice, uint32_t u32Address, uint32_t u32Value, unsigned cb)
1536{
1537 PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
1538
1539 LogFlowFunc(("pDevIns=%p iBus=%d iDevice=%d u32Address=%u u32Value=%u cb=%d\n", pDevIns, iBus, iDevice, u32Address, u32Value, cb));
1540
1541 /* If the current bus is not the target bus search for the bus which contains the device. */
1542 if (iBus != pBus->PciDev.abConfig[VBOX_PCI_SECONDARY_BUS])
1543 {
1544 PPDMPCIDEV pBridgeDevice = pciR3FindBridge(pBus, iBus);
1545 if (pBridgeDevice)
1546 {
1547 AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigWrite);
1548 pBridgeDevice->Int.s.pfnBridgeConfigWrite(pBridgeDevice->Int.s.CTX_SUFF(pDevIns), iBus, iDevice, u32Address, u32Value, cb);
1549 }
1550 }
1551 else
1552 {
1553 /* This is the target bus, pass the write to the device. */
1554 PPDMPCIDEV pPciDev = pBus->apDevices[iDevice];
1555 if (pPciDev)
1556 {
1557 LogFunc(("%s: addr=%02x val=%08x len=%d\n", pPciDev->pszNameR3, u32Address, u32Value, cb));
1558 pPciDev->Int.s.pfnConfigWrite(pPciDev->Int.s.CTX_SUFF(pDevIns), pPciDev, u32Address, u32Value, cb);
1559 }
1560 }
1561}
1562
1563
1564/**
1565 * @callback_method_impl{FNPCIBRIDGECONFIGREAD}
1566 */
1567static DECLCALLBACK(uint32_t) pcibridgeR3ConfigRead(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice, uint32_t u32Address, unsigned cb)
1568{
1569 PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
1570 uint32_t u32Value = 0xffffffff; /* Return value in case there is no device. */
1571
1572 LogFlowFunc(("pDevIns=%p iBus=%d iDevice=%d u32Address=%u cb=%d\n", pDevIns, iBus, iDevice, u32Address, cb));
1573
1574 /* If the current bus is not the target bus search for the bus which contains the device. */
1575 if (iBus != pBus->PciDev.abConfig[VBOX_PCI_SECONDARY_BUS])
1576 {
1577 PPDMPCIDEV pBridgeDevice = pciR3FindBridge(pBus, iBus);
1578 if (pBridgeDevice)
1579 {
1580 AssertPtr( pBridgeDevice->Int.s.pfnBridgeConfigRead);
1581 u32Value = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->Int.s.CTX_SUFF(pDevIns), iBus, iDevice, u32Address, cb);
1582 }
1583 }
1584 else
1585 {
1586 /* This is the target bus, pass the read to the device. */
1587 PPDMPCIDEV pPciDev = pBus->apDevices[iDevice];
1588 if (pPciDev)
1589 {
1590 u32Value = pPciDev->Int.s.pfnConfigRead(pPciDev->Int.s.CTX_SUFF(pDevIns), pPciDev, u32Address, cb);
1591 LogFunc(("%s: u32Address=%02x u32Value=%08x cb=%d\n", pPciDev->pszNameR3, u32Address, u32Value, cb));
1592 }
1593 }
1594
1595 return u32Value;
1596}
1597
1598
1599/**
1600 * @callback_method_impl{FNSSMDEVSAVEEXEC}
1601 */
1602static DECLCALLBACK(int) pcibridgeR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
1603{
1604 PDEVPCIBUS pThis = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
1605 return pciR3CommonSaveExec(pThis, pSSM);
1606}
1607
1608
1609/**
1610 * @callback_method_impl{FNSSMDEVLOADEXEC}
1611 */
1612static DECLCALLBACK(int) pcibridgeR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1613{
1614 PDEVPCIBUS pThis = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
1615 if (uVersion > VBOX_PCI_SAVED_STATE_VERSION)
1616 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1617 return pciR3CommonLoadExec(pThis, pSSM, uVersion, uPass);
1618}
1619
1620
1621/**
1622 * @interface_method_impl{PDMDEVREG,pfnReset}
1623 */
1624static DECLCALLBACK(void) pcibridgeR3Reset(PPDMDEVINS pDevIns)
1625{
1626 PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
1627
1628 /* Reset config space to default values. */
1629 pBus->PciDev.abConfig[VBOX_PCI_PRIMARY_BUS] = 0;
1630 pBus->PciDev.abConfig[VBOX_PCI_SECONDARY_BUS] = 0;
1631 pBus->PciDev.abConfig[VBOX_PCI_SUBORDINATE_BUS] = 0;
1632}
1633
1634
1635/**
1636 * @interface_method_impl{PDMDEVREG,pfnConstruct}
1637 */
1638static DECLCALLBACK(int) pcibridgeR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
1639{
1640 RT_NOREF(iInstance);
1641 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
1642
1643 /*
1644 * Validate and read configuration.
1645 */
1646 if (!CFGMR3AreValuesValid(pCfg, "GCEnabled\0" "R0Enabled\0"))
1647 return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
1648
1649 /* check if RC code is enabled. */
1650 bool fGCEnabled;
1651 int rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
1652 if (RT_FAILURE(rc))
1653 return PDMDEV_SET_ERROR(pDevIns, rc,
1654 N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
1655
1656 /* check if R0 code is enabled. */
1657 bool fR0Enabled;
1658 rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
1659 if (RT_FAILURE(rc))
1660 return PDMDEV_SET_ERROR(pDevIns, rc,
1661 N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
1662 Log(("PCI: fGCEnabled=%RTbool fR0Enabled=%RTbool\n", fGCEnabled, fR0Enabled));
1663
1664 /*
1665 * Init data and register the PCI bus.
1666 */
1667 PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
1668 pBus->fTypePiix3 = true;
1669 pBus->fTypeIch9 = false;
1670 pBus->fPureBridge = true;
1671 pBus->pDevInsR3 = pDevIns;
1672 pBus->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
1673 pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
1674 pBus->papBridgesR3 = (PPDMPCIDEV *)PDMDevHlpMMHeapAllocZ(pDevIns, sizeof(PPDMPCIDEV) * RT_ELEMENTS(pBus->apDevices));
1675 AssertLogRelReturn(pBus->papBridgesR3, VERR_NO_MEMORY);
1676
1677 PDMPCIBUSREG PciBusReg;
1678 PciBusReg.u32Version = PDM_PCIBUSREG_VERSION;
1679 PciBusReg.pfnRegisterR3 = pcibridgeR3MergedRegisterDevice;
1680 PciBusReg.pfnRegisterMsiR3 = NULL;
1681 PciBusReg.pfnIORegionRegisterR3 = devpciR3CommonIORegionRegister;
1682 PciBusReg.pfnSetConfigCallbacksR3 = devpciR3CommonSetConfigCallbacks;
1683 PciBusReg.pfnSetIrqR3 = pcibridgeSetIrq;
1684 PciBusReg.pszSetIrqRC = fGCEnabled ? "pcibridgeSetIrq" : NULL;
1685 PciBusReg.pszSetIrqR0 = fR0Enabled ? "pcibridgeSetIrq" : NULL;
1686#if PDM_DEVHLPR3_VERSION >= PDM_VERSION_MAKE_PP(0xffe7, 20, 0)
1687 rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBus->pPciHlpR3, &pBus->iBus);
1688#else
1689 rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBus->pPciHlpR3);
1690 pBus->iBus = rc;
1691#endif
1692 if (RT_FAILURE(rc))
1693 return PDMDEV_SET_ERROR(pDevIns, rc,
1694 N_("Failed to register ourselves as a PCI Bus"));
1695 Assert(pBus->iBus == (uint32_t)iInstance + 1); /* Can be removed when adding support for multiple bridge implementations. */
1696 if (pBus->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
1697 return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
1698 N_("PCI helper version mismatch; got %#x expected %#x"),
1699 pBus->pPciHlpR3->u32Version, PDM_PCIHLPR3_VERSION);
1700
1701 pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
1702 pBus->pPciHlpR0 = pBus->pPciHlpR3->pfnGetR0Helpers(pDevIns);
1703
1704 /*
1705 * Fill in PCI configs and add them to the bus.
1706 */
1707 PCIDevSetVendorId( &pBus->PciDev, 0x8086); /* Intel */
1708 PCIDevSetDeviceId( &pBus->PciDev, 0x2448); /* 82801 Mobile PCI bridge. */
1709 PCIDevSetRevisionId(&pBus->PciDev, 0xf2);
1710 PCIDevSetClassSub( &pBus->PciDev, 0x04); /* pci2pci */
1711 PCIDevSetClassBase( &pBus->PciDev, 0x06); /* PCI_bridge */
1712 PCIDevSetClassProg( &pBus->PciDev, 0x01); /* Supports subtractive decoding. */
1713 PCIDevSetHeaderType(&pBus->PciDev, 0x01); /* Single function device which adheres to the PCI-to-PCI bridge spec. */
1714 PCIDevSetCommand( &pBus->PciDev, 0x00);
1715 PCIDevSetStatus( &pBus->PciDev, 0x20); /* 66MHz Capable. */
1716 PCIDevSetInterruptLine(&pBus->PciDev, 0x00); /* This device does not assert interrupts. */
1717
1718 /*
1719 * This device does not generate interrupts. Interrupt delivery from
1720 * devices attached to the bus is unaffected.
1721 */
1722 PCIDevSetInterruptPin(&pBus->PciDev, 0x00);
1723
1724 /*
1725 * Register this PCI bridge. The called function will take care on which bus we will get registered.
1726 */
1727 rc = PDMDevHlpPCIRegisterEx(pDevIns, &pBus->PciDev, PDMPCIDEVREG_CFG_PRIMARY, PDMPCIDEVREG_F_PCI_BRIDGE,
1728 PDMPCIDEVREG_DEV_NO_FIRST_UNUSED, PDMPCIDEVREG_FUN_NO_FIRST_UNUSED, "pcibridge");
1729 if (RT_FAILURE(rc))
1730 return rc;
1731 pBus->PciDev.Int.s.pfnBridgeConfigRead = pcibridgeR3ConfigRead;
1732 pBus->PciDev.Int.s.pfnBridgeConfigWrite = pcibridgeR3ConfigWrite;
1733
1734 pBus->iDevSearch = 0;
1735
1736 /*
1737 * Register SSM handlers. We use the same saved state version as for the host bridge
1738 * to make changes easier.
1739 */
1740 rc = PDMDevHlpSSMRegisterEx(pDevIns, VBOX_PCI_SAVED_STATE_VERSION, sizeof(*pBus) + 16*128, "pgm",
1741 NULL, NULL, NULL,
1742 NULL, pcibridgeR3SaveExec, NULL,
1743 NULL, pcibridgeR3LoadExec, NULL);
1744 if (RT_FAILURE(rc))
1745 return rc;
1746
1747 return VINF_SUCCESS;
1748}
1749
1750
1751/**
1752 * @interface_method_impl{PDMDEVREG,pfnDestruct}
1753 */
1754static DECLCALLBACK(int) pcibridgeR3Destruct(PPDMDEVINS pDevIns)
1755{
1756 PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
1757 if (pBus->papBridgesR3)
1758 {
1759 PDMDevHlpMMHeapFree(pDevIns, pBus->papBridgesR3);
1760 pBus->papBridgesR3 = NULL;
1761 }
1762 return VINF_SUCCESS;
1763}
1764
1765
1766/**
1767 * The device registration structure
1768 * for the PCI-to-PCI bridge.
1769 */
1770const PDMDEVREG g_DevicePCIBridge =
1771{
1772 /* u32Version */
1773 PDM_DEVREG_VERSION,
1774 /* szName */
1775 "pcibridge",
1776 /* szRCMod */
1777 "VBoxDDRC.rc",
1778 /* szR0Mod */
1779 "VBoxDDR0.r0",
1780 /* pszDescription */
1781 "82801 Mobile PCI to PCI bridge",
1782 /* fFlags */
1783 PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0,
1784 /* fClass */
1785 PDM_DEVREG_CLASS_BUS_PCI,
1786 /* cMaxInstances */
1787 ~0U,
1788 /* cbInstance */
1789 sizeof(DEVPCIBUS),
1790 /* pfnConstruct */
1791 pcibridgeR3Construct,
1792 /* pfnDestruct */
1793 pcibridgeR3Destruct,
1794 /* pfnRelocate */
1795 devpciR3BusRelocate,
1796 /* pfnMemSetup */
1797 NULL,
1798 /* pfnPowerOn */
1799 NULL,
1800 /* pfnReset */
1801 pcibridgeR3Reset,
1802 /* pfnSuspend */
1803 NULL,
1804 /* pfnResume */
1805 NULL,
1806 /* pfnAttach */
1807 NULL,
1808 /* pfnDetach */
1809 NULL,
1810 /* pfnQueryInterface */
1811 NULL,
1812 /* pfnInitComplete */
1813 NULL,
1814 /* pfnPowerOff */
1815 NULL,
1816 /* pfnSoftReset */
1817 NULL,
1818 /* u32VersionEnd */
1819 PDM_DEVREG_VERSION
1820};
1821
1822#endif /* IN_RING3 */
1823
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