DevPCI.cpp@ 75142

Last change on this file since 75142 was 74474, checked in by vboxsync, 6 years ago
Main,Devices: Graphics controller updates. bugref:8893
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1	/* $Id: DevPCI.cpp 74474 2018-09-26 11:55:47Z vboxsync $ */
2	/** @file
3	* DevPCI - PCI BUS Device.
4	*
5	* @remarks New code shall be added to DevPciIch9.cpp as that will become
6	* the common PCI bus code soon. Don't fix code in both DevPCI.cpp
7	* and DevPciIch9.cpp when it's possible to just make the latter
8	* version common. Common code uses the 'devpci' prefix, is
9	* prototyped in DevPciInternal.h, and is defined in DevPciIch9.cpp.
10	*/
11
12	/*
13	* Copyright (C) 2006-2017 Oracle Corporation
14	*
15	* This file is part of VirtualBox Open Source Edition (OSE), as
16	* available from http://www.virtualbox.org. This file is free software;
17	* you can redistribute it and/or modify it under the terms of the GNU
18	* General Public License (GPL) as published by the Free Software
19	* Foundation, in version 2 as it comes in the "COPYING" file of the
20	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
21	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
22	* --------------------------------------------------------------------
23	*
24	* This code is based on:
25	*
26	* QEMU PCI bus manager
27	*
28	* Copyright (c) 2004 Fabrice Bellard
29	*
30	* Permission is hereby granted, free of charge, to any person obtaining a copy
31	* of this software and associated documentation files (the "Software"), to deal
32	* in the Software without restriction, including without limitation the rights
33	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
34	* copies of the Software, and to permit persons to whom the Software is
35	* furnished to do so, subject to the following conditions:
36	*
37	* The above copyright notice and this permission notice shall be included in
38	* all copies or substantial portions of the Software.
39	*
40	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
41	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
42	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
43	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
44	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
45	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
46	* THE SOFTWARE.
47	*/
48
49
50	/*********************************************************************************************************************************
51	* Header Files *
52	*********************************************************************************************************************************/
53	#define LOG_GROUP LOG_GROUP_DEV_PCI
54	#define PDMPCIDEV_INCLUDE_PRIVATE /* Hack to get pdmpcidevint.h included at the right point. */
55	#include <VBox/vmm/pdmpcidev.h>
56	#include <VBox/vmm/pdmdev.h>
57	#include <VBox/vmm/mm.h>
58	#include <iprt/asm.h>
59	#include <iprt/assert.h>
60	#include <iprt/string.h>
61
62	#include "PciInline.h"
63	#include "VBoxDD.h"
64	#include "DevPciInternal.h"
65
66
67	/*********************************************************************************************************************************
68	* Defined Constants And Macros *
69	*********************************************************************************************************************************/
70	/** Saved state version of the PCI bus device. */
71	#define VBOX_PCI_SAVED_STATE_VERSION VBOX_PCI_SAVED_STATE_VERSION_REGION_SIZES
72	/** Adds I/O region types and sizes for dealing changes in resource regions. */
73	#define VBOX_PCI_SAVED_STATE_VERSION_REGION_SIZES 4
74	/** Before region sizes, the first named one.
75	* Looking at the code though, we support even older version. */
76	#define VBOX_PCI_SAVED_STATE_VERSION_IRQ_STATES 3
77	/** Notes whether we use the I/O APIC. */
78	#define VBOX_PCI_SAVED_STATE_VERSION_USE_IO_APIC 2
79
80
81	/*********************************************************************************************************************************
82	* Internal Functions *
83	*********************************************************************************************************************************/
84	RT_C_DECLS_BEGIN
85
86	PDMBOTHCBDECL(void) pciSetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTag);
87	PDMBOTHCBDECL(void) pcibridgeSetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTag);
88	PDMBOTHCBDECL(int) pciIOPortAddressWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
89	PDMBOTHCBDECL(int) pciIOPortAddressRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb);
90	PDMBOTHCBDECL(int) pciIOPortDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
91	PDMBOTHCBDECL(int) pciIOPortDataRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb);
92
93	#ifdef IN_RING3
94	DECLINLINE(PPDMPCIDEV) pciR3FindBridge(PDEVPCIBUS pBus, uint8_t iBus);
95	#endif
96
97	RT_C_DECLS_END
98
99	#define DEBUG_PCI
100
101	#define PCI_VENDOR_ID 0x00 /* 16 bits */
102	#define PCI_DEVICE_ID 0x02 /* 16 bits */
103	#define PCI_COMMAND 0x04 /* 16 bits */
104	#define PCI_COMMAND_IO 0x01 /* Enable response in I/O space */
105	#define PCI_COMMAND_MEMORY 0x02 /* Enable response in Memory space */
106	#define PCI_CLASS_DEVICE 0x0a /* Device class */
107	#define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
108	#define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
109	#define PCI_MIN_GNT 0x3e /* 8 bits */
110	#define PCI_MAX_LAT 0x3f /* 8 bits */
111
112
113	static int pci_data_write(PDEVPCIROOT pGlobals, uint32_t addr, uint32_t val, int len)
114	{
115	uint8_t iBus, iDevice;
116	uint32_t config_addr;
117
118	LogFunc(("addr=%08x val=%08x len=%d\n", pGlobals->uConfigReg, val, len));
119
120	if (!(pGlobals->uConfigReg & (1 << 31))) {
121	return VINF_SUCCESS;
122	}
123	if ((pGlobals->uConfigReg & 0x3) != 0) {
124	return VINF_SUCCESS;
125	}
126	iBus = (pGlobals->uConfigReg >> 16) & 0xff;
127	iDevice = (pGlobals->uConfigReg >> 8) & 0xff;
128	config_addr = (pGlobals->uConfigReg & 0xfc) \| (addr & 3);
129	RT_UNTRUSTED_VALIDATED_FENCE(); /* paranoia */
130	if (iBus != 0)
131	{
132	if (pGlobals->PciBus.cBridges)
133	{
134	#ifdef IN_RING3 /** @todo do lookup in R0/RC too! */
135	PPDMPCIDEV pBridgeDevice = pciR3FindBridge(&pGlobals->PciBus, iBus);
136	if (pBridgeDevice)
137	{
138	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigWrite);
139	pBridgeDevice->Int.s.pfnBridgeConfigWrite(pBridgeDevice->Int.s.CTX_SUFF(pDevIns), iBus, iDevice, config_addr, val, len);
140	}
141	#else
142	RT_NOREF2(val, len);
143	return VINF_IOM_R3_IOPORT_WRITE;
144	#endif
145	}
146	}
147	else
148	{
149	R3PTRTYPE(PDMPCIDEV *) pci_dev = pGlobals->PciBus.apDevices[iDevice];
150	if (pci_dev)
151	{
152	#ifdef IN_RING3
153	LogFunc(("%s: addr=%02x val=%08x len=%d\n", pci_dev->pszNameR3, config_addr, val, len));
154	return VBOXSTRICTRC_TODO(pci_dev->Int.s.pfnConfigWrite(pci_dev->Int.s.CTX_SUFF(pDevIns), pci_dev, config_addr, val, len));
155	#else
156	return VINF_IOM_R3_IOPORT_WRITE;
157	#endif
158	}
159	}
160	return VINF_SUCCESS;
161	}
162
163	static int pci_data_read(PDEVPCIROOT pGlobals, uint32_t addr, int len, uint32_t *pu32)
164	{
165	uint8_t iBus, iDevice;
166	uint32_t config_addr;
167
168	*pu32 = 0xffffffff;
169
170	if (!(pGlobals->uConfigReg & (1 << 31)))
171	return VINF_SUCCESS;
172	if ((pGlobals->uConfigReg & 0x3) != 0)
173	return VINF_SUCCESS;
174	iBus = (pGlobals->uConfigReg >> 16) & 0xff;
175	iDevice = (pGlobals->uConfigReg >> 8) & 0xff;
176	config_addr = (pGlobals->uConfigReg & 0xfc) \| (addr & 3);
177	RT_UNTRUSTED_VALIDATED_FENCE();
178	if (iBus != 0)
179	{
180	if (pGlobals->PciBus.cBridges)
181	{
182	#ifdef IN_RING3 /** @todo do lookup in R0/RC too! */
183	PPDMPCIDEV pBridgeDevice = pciR3FindBridge(&pGlobals->PciBus, iBus);
184	if (pBridgeDevice)
185	{
186	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigRead);
187	*pu32 = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->Int.s.CTX_SUFF(pDevIns), iBus, iDevice, config_addr, len);
188	}
189	#else
190	NOREF(len);
191	return VINF_IOM_R3_IOPORT_READ;
192	#endif
193	}
194	}
195	else
196	{
197	R3PTRTYPE(PDMPCIDEV *) pci_dev = pGlobals->PciBus.apDevices[iDevice];
198	if (pci_dev)
199	{
200	#ifdef IN_RING3
201	*pu32 = pci_dev->Int.s.pfnConfigRead(pci_dev->Int.s.CTX_SUFF(pDevIns), pci_dev, config_addr, len);
202	LogFunc(("%s: addr=%02x val=%08x len=%d\n", pci_dev->pszNameR3, config_addr, *pu32, len));
203	#else
204	NOREF(len);
205	return VINF_IOM_R3_IOPORT_READ;
206	#endif
207	}
208	}
209
210	return VINF_SUCCESS;
211	}
212
213
214
215	/* return the global irq number corresponding to a given device irq
216	pin. We could also use the bus number to have a more precise
217	mapping.
218	This is the implementation note described in the PCI spec chapter 2.2.6 */
219	static inline int pci_slot_get_pirq(uint8_t uDevFn, int irq_num)
220	{
221	int slot_addend;
222	slot_addend = (uDevFn >> 3) - 1;
223	return (irq_num + slot_addend) & 3;
224	}
225
226	static inline int pci_slot_get_apic_pirq(uint8_t uDevFn, int irq_num)
227	{
228	return (irq_num + (uDevFn >> 3)) & 7;
229	}
230
231	static inline int get_pci_irq_apic_level(PDEVPCIROOT pGlobals, int irq_num)
232	{
233	return (pGlobals->auPciApicIrqLevels[irq_num] != 0);
234	}
235
236	static void apic_set_irq(PDEVPCIBUS pBus, uint8_t uDevFn, PDMPCIDEV *pPciDev, int irq_num1, int iLevel, int iAcpiIrq, uint32_t uTagSrc)
237	{
238	/* This is only allowed to be called with a pointer to the host bus. */
239	AssertMsg(pBus->iBus == 0, ("iBus=%u\n", pBus->iBus));
240
241	if (iAcpiIrq == -1) {
242	int apic_irq, apic_level;
243	PDEVPCIROOT pGlobals = DEVPCIBUS_2_DEVPCIROOT(pBus);
244	int irq_num = pci_slot_get_apic_pirq(uDevFn, irq_num1);
245
246	if ((iLevel & PDM_IRQ_LEVEL_HIGH) == PDM_IRQ_LEVEL_HIGH)
247	ASMAtomicIncU32(&pGlobals->auPciApicIrqLevels[irq_num]);
248	else if ((iLevel & PDM_IRQ_LEVEL_HIGH) == PDM_IRQ_LEVEL_LOW)
249	ASMAtomicDecU32(&pGlobals->auPciApicIrqLevels[irq_num]);
250
251	apic_irq = irq_num + 0x10;
252	apic_level = get_pci_irq_apic_level(pGlobals, irq_num);
253	Log3Func(("%s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d\n",
254	R3STRING(pPciDev->pszNameR3), irq_num1, iLevel, apic_irq, apic_level, irq_num));
255	pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), apic_irq, apic_level, uTagSrc);
256
257	if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP) {
258	ASMAtomicDecU32(&pGlobals->auPciApicIrqLevels[irq_num]);
259	pPciDev->Int.s.uIrqPinState = PDM_IRQ_LEVEL_LOW;
260	apic_level = get_pci_irq_apic_level(pGlobals, irq_num);
261	Log3Func(("%s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d (flop)\n",
262	R3STRING(pPciDev->pszNameR3), irq_num1, iLevel, apic_irq, apic_level, irq_num));
263	pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), apic_irq, apic_level, uTagSrc);
264	}
265	} else {
266	Log3Func(("%s: irq_num1=%d level=%d iAcpiIrq=%d\n",
267	R3STRING(pPciDev->pszNameR3), irq_num1, iLevel, iAcpiIrq));
268	pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), iAcpiIrq, iLevel, uTagSrc);
269	}
270	}
271
272	DECLINLINE(int) get_pci_irq_level(PDEVPCIROOT pGlobals, int irq_num)
273	{
274	return (pGlobals->Piix3.auPciLegacyIrqLevels[irq_num] != 0);
275	}
276
277	/**
278	* Set the IRQ for a PCI device on the host bus - shared by host bus and bridge.
279	*
280	* @param pGlobals Device instance of the host PCI Bus.
281	* @param uDevFn The device number on the host bus which will raise the IRQ
282	* @param pPciDev The PCI device structure which raised the interrupt.
283	* @param iIrq IRQ number to set.
284	* @param iLevel IRQ level.
285	* @param uTagSrc The IRQ tag and source ID (for tracing).
286	* @remark uDevFn and pPciDev->uDevFn are not the same if the device is behind
287	* a bridge. In that case uDevFn will be the slot of the bridge which
288	* is needed to calculate the PIRQ value.
289	*/
290	static void pciSetIrqInternal(PDEVPCIROOT pGlobals, uint8_t uDevFn, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc)
291	{
292	PDEVPCIBUS pBus = &pGlobals->PciBus;
293	uint8_t *pbCfg = pGlobals->Piix3.PIIX3State.dev.abConfig;
294	const bool fIsAcpiDevice = pPciDev->abConfig[2] == 0x13 && pPciDev->abConfig[3] == 0x71;
295	/* If the two configuration space bytes at 0xde, 0xad are set to 0xbe, 0xef, a back door
296	* is opened to route PCI interrupts directly to the I/O APIC and bypass the PIC.
297	* See the \_SB_.PCI0._PRT method in vbox.dsl.
298	*/
299	const bool fIsApicEnabled = pGlobals->fUseIoApic && pbCfg[0xde] == 0xbe && pbCfg[0xad] == 0xef;
300	int pic_irq, pic_level;
301
302	/* Check if the state changed. */
303	if (pPciDev->Int.s.uIrqPinState != iLevel)
304	{
305	pPciDev->Int.s.uIrqPinState = (iLevel & PDM_IRQ_LEVEL_HIGH);
306
307	/* Send interrupt to I/O APIC only. */
308	if (fIsApicEnabled)
309	{
310	if (fIsAcpiDevice)
311	/*
312	* ACPI needs special treatment since SCI is hardwired and
313	* should not be affected by PCI IRQ routing tables at the
314	* same time SCI IRQ is shared in PCI sense hence this
315	* kludge (i.e. we fetch the hardwired value from ACPIs
316	* PCI device configuration space).
317	*/
318	apic_set_irq(pBus, uDevFn, pPciDev, -1, iLevel, pPciDev->abConfig[PCI_INTERRUPT_LINE], uTagSrc);
319	else
320	apic_set_irq(pBus, uDevFn, pPciDev, iIrq, iLevel, -1, uTagSrc);
321	return;
322	}
323
324	if (fIsAcpiDevice)
325	{
326	/* As per above treat ACPI in a special way */
327	pic_irq = pPciDev->abConfig[PCI_INTERRUPT_LINE];
328	pGlobals->Piix3.iAcpiIrq = pic_irq;
329	pGlobals->Piix3.iAcpiIrqLevel = iLevel & PDM_IRQ_LEVEL_HIGH;
330	}
331	else
332	{
333	int irq_num;
334	irq_num = pci_slot_get_pirq(uDevFn, iIrq);
335
336	if (pPciDev->Int.s.uIrqPinState == PDM_IRQ_LEVEL_HIGH)
337	ASMAtomicIncU32(&pGlobals->Piix3.auPciLegacyIrqLevels[irq_num]);
338	else if (pPciDev->Int.s.uIrqPinState == PDM_IRQ_LEVEL_LOW)
339	ASMAtomicDecU32(&pGlobals->Piix3.auPciLegacyIrqLevels[irq_num]);
340
341	/* now we change the pic irq level according to the piix irq mappings */
342	pic_irq = pbCfg[0x60 + irq_num];
343	if (pic_irq >= 16)
344	{
345	if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP)
346	{
347	ASMAtomicDecU32(&pGlobals->Piix3.auPciLegacyIrqLevels[irq_num]);
348	pPciDev->Int.s.uIrqPinState = PDM_IRQ_LEVEL_LOW;
349	}
350
351	return;
352	}
353	}
354
355	/* the pic level is the logical OR of all the PCI irqs mapped to it */
356	pic_level = 0;
357	if (pic_irq == pbCfg[0x60])
358	pic_level \|= get_pci_irq_level(pGlobals, 0);
359	if (pic_irq == pbCfg[0x61])
360	pic_level \|= get_pci_irq_level(pGlobals, 1);
361	if (pic_irq == pbCfg[0x62])
362	pic_level \|= get_pci_irq_level(pGlobals, 2);
363	if (pic_irq == pbCfg[0x63])
364	pic_level \|= get_pci_irq_level(pGlobals, 3);
365	if (pic_irq == pGlobals->Piix3.iAcpiIrq)
366	pic_level \|= pGlobals->Piix3.iAcpiIrqLevel;
367
368	Log3Func(("%s: iLevel=%d iIrq=%d pic_irq=%d pic_level=%d uTagSrc=%#x\n",
369	R3STRING(pPciDev->pszNameR3), iLevel, iIrq, pic_irq, pic_level, uTagSrc));
370	pBus->CTX_SUFF(pPciHlp)->pfnIsaSetIrq(pBus->CTX_SUFF(pDevIns), pic_irq, pic_level, uTagSrc);
371
372	/** @todo optimize pci irq flip-flop some rainy day. */
373	if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP)
374	pciSetIrqInternal(pGlobals, uDevFn, pPciDev, iIrq, PDM_IRQ_LEVEL_LOW, uTagSrc);
375	}
376	}
377
378
379	/**
380	* @interface_method_impl{PDMPCIBUSREG,pfnSetIrqR3}
381	*/
382	PDMBOTHCBDECL(void) pciSetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc)
383	{
384	pciSetIrqInternal(PDMINS_2_DATA(pDevIns, PDEVPCIROOT), pPciDev->uDevFn, pPciDev, iIrq, iLevel, uTagSrc);
385	}
386
387	#ifdef IN_RING3
388
389	/**
390	* Finds a bridge on the bus which contains the destination bus.
391	*
392	* @return Pointer to the device instance data of the bus or
393	* NULL if no bridge was found.
394	* @param pBus Pointer to the bus to search on.
395	* @param iBus Destination bus number.
396	*/
397	DECLINLINE(PPDMPCIDEV) pciR3FindBridge(PDEVPCIBUS pBus, uint8_t iBus)
398	{
399	/* Search for a fitting bridge. */
400	for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
401	{
402	/*
403	* Examine secondary and subordinate bus number.
404	* If the target bus is in the range we pass the request on to the bridge.
405	*/
406	PPDMPCIDEV pBridgeTemp = pBus->papBridgesR3[iBridge];
407	AssertMsg(pBridgeTemp && pciDevIsPci2PciBridge(pBridgeTemp),
408	("Device is not a PCI bridge but on the list of PCI bridges\n"));
409
410	if ( iBus >= pBridgeTemp->abConfig[VBOX_PCI_SECONDARY_BUS]
411	&& iBus <= pBridgeTemp->abConfig[VBOX_PCI_SUBORDINATE_BUS])
412	return pBridgeTemp;
413	}
414
415	/* Nothing found. */
416	return NULL;
417	}
418
419	static void pciR3Piix3Reset(PIIX3ISABRIDGE *d)
420	{
421	uint8_t *pci_conf = d->dev.abConfig;
422
423	pci_conf[0x04] = 0x07; /* master, memory and I/O */
424	pci_conf[0x05] = 0x00;
425	pci_conf[0x06] = 0x00;
426	pci_conf[0x07] = 0x02; /* PCI_status_devsel_medium */
427	pci_conf[0x4c] = 0x4d;
428	pci_conf[0x4e] = 0x03;
429	pci_conf[0x4f] = 0x00;
430	pci_conf[0x60] = 0x80;
431	pci_conf[0x69] = 0x02;
432	pci_conf[0x70] = 0x80;
433	pci_conf[0x76] = 0x0c;
434	pci_conf[0x77] = 0x0c;
435	pci_conf[0x78] = 0x02;
436	pci_conf[0x79] = 0x00;
437	pci_conf[0x80] = 0x00;
438	pci_conf[0x82] = 0x02; /* Get rid of the Linux guest "Enabling Passive Release" PCI quirk warning. */
439	pci_conf[0xa0] = 0x08;
440	pci_conf[0xa2] = 0x00;
441	pci_conf[0xa3] = 0x00;
442	pci_conf[0xa4] = 0x00;
443	pci_conf[0xa5] = 0x00;
444	pci_conf[0xa6] = 0x00;
445	pci_conf[0xa7] = 0x00;
446	pci_conf[0xa8] = 0x0f;
447	pci_conf[0xaa] = 0x00;
448	pci_conf[0xab] = 0x00;
449	pci_conf[0xac] = 0x00;
450	pci_conf[0xae] = 0x00;
451	}
452
453	/* host irqs corresponding to PCI irqs A-D */
454	static const uint8_t pci_irqs[4] = { 11, 10, 9, 11 }; /* bird: added const */
455
456	static void pci_bios_init_device(PDEVPCIROOT pGlobals, PDEVPCIBUS pBus, PPDMPCIDEV pPciDev, uint8_t cBridgeDepth, uint8_t *paBridgePositions)
457	{
458	uint32_t *paddr;
459	int pin, pic_irq;
460	uint16_t devclass, vendor_id, device_id;
461
462	devclass = devpciR3GetWord(pPciDev, PCI_CLASS_DEVICE);
463	vendor_id = devpciR3GetWord(pPciDev, PCI_VENDOR_ID);
464	device_id = devpciR3GetWord(pPciDev, PCI_DEVICE_ID);
465
466	/* Check if device is present. */
467	if (vendor_id != 0xffff)
468	{
469	switch(devclass)
470	{
471	case 0x0101:
472	if ( (vendor_id == 0x8086)
473	&& (device_id == 0x7010 \|\| device_id == 0x7111 \|\| device_id == 0x269e))
474	{
475	/* PIIX3, PIIX4 or ICH6 IDE */
476	devpciR3SetWord(pPciDev, 0x40, 0x8000); /* enable IDE0 */
477	devpciR3SetWord(pPciDev, 0x42, 0x8000); /* enable IDE1 */
478	goto default_map;
479	}
480	else
481	{
482	/* IDE: we map it as in ISA mode */
483	devpciR3BiosInitSetRegionAddress(pBus, pPciDev, 0, 0x1f0);
484	devpciR3BiosInitSetRegionAddress(pBus, pPciDev, 1, 0x3f4);
485	devpciR3BiosInitSetRegionAddress(pBus, pPciDev, 2, 0x170);
486	devpciR3BiosInitSetRegionAddress(pBus, pPciDev, 3, 0x374);
487	devpciR3SetWord(pPciDev, PCI_COMMAND,
488	devpciR3GetWord(pPciDev, PCI_COMMAND)
489	\| PCI_COMMAND_IOACCESS);
490	}
491	break;
492	case 0x0300:
493	{
494	if (vendor_id != 0x80ee)
495	goto default_map;
496	/* VGA: map frame buffer to default Bochs VBE address */
497	int iRegion = devpciR3GetWord(pPciDev, VBOX_PCI_SUBSYSTEM_VENDOR_ID) == 0x15ad ? 1 : 0;
498	devpciR3BiosInitSetRegionAddress(pBus, pPciDev, iRegion, 0xe0000000);
499	/*
500	* Legacy VGA I/O ports are implicitly decoded by a VGA class device. But
501	* only the framebuffer (i.e., a memory region) is explicitly registered via
502	* devpciR3BiosInitSetRegionAddress, so don't forget to enable I/O decoding.
503	*/
504	devpciR3SetWord(pPciDev, PCI_COMMAND,
505	devpciR3GetWord(pPciDev, PCI_COMMAND)
506	\| PCI_COMMAND_IOACCESS \| PCI_COMMAND_MEMACCESS);
507	break;
508	}
509	case 0x0800:
510	/* PIC */
511	vendor_id = devpciR3GetWord(pPciDev, PCI_VENDOR_ID);
512	device_id = devpciR3GetWord(pPciDev, PCI_DEVICE_ID);
513	if (vendor_id == 0x1014)
514	{
515	/* IBM */
516	if (device_id == 0x0046 \|\| device_id == 0xFFFF)
517	{
518	/* MPIC & MPIC2 */
519	devpciR3BiosInitSetRegionAddress(pBus, pPciDev, 0, 0x80800000 + 0x00040000);
520	devpciR3SetWord(pPciDev, PCI_COMMAND,
521	devpciR3GetWord(pPciDev, PCI_COMMAND)
522	\| PCI_COMMAND_MEMACCESS);
523	}
524	}
525	break;
526	case 0xff00:
527	if ( (vendor_id == 0x0106b)
528	&& (device_id == 0x0017 \|\| device_id == 0x0022))
529	{
530	/* macio bridge */
531	devpciR3BiosInitSetRegionAddress(pBus, pPciDev, 0, 0x80800000);
532	devpciR3SetWord(pPciDev, PCI_COMMAND,
533	devpciR3GetWord(pPciDev, PCI_COMMAND)
534	\| PCI_COMMAND_MEMACCESS);
535	}
536	break;
537	case 0x0604:
538	{
539	/* Init PCI-to-PCI bridge. */
540	devpciR3SetByte(pPciDev, VBOX_PCI_PRIMARY_BUS, pBus->iBus);
541
542	AssertMsg(pGlobals->uPciBiosBus < 255, ("Too many bridges on the bus\n"));
543	pGlobals->uPciBiosBus++;
544	devpciR3SetByte(pPciDev, VBOX_PCI_SECONDARY_BUS, pGlobals->uPciBiosBus);
545	devpciR3SetByte(pPciDev, VBOX_PCI_SUBORDINATE_BUS, 0xff); /* Temporary until we know how many other bridges are behind this one. */
546
547	/* Add position of this bridge into the array. */
548	paBridgePositions[cBridgeDepth+1] = (pPciDev->uDevFn >> 3);
549
550	/*
551	* The I/O range for the bridge must be aligned to a 4KB boundary.
552	* This does not change anything really as the access to the device is not going
553	* through the bridge but we want to be compliant to the spec.
554	*/
555	if ((pGlobals->uPciBiosIo % _4K) != 0)
556	pGlobals->uPciBiosIo = RT_ALIGN_32(pGlobals->uPciBiosIo, _4K);
557	LogFunc(("Aligned I/O start address. New address %#x\n", pGlobals->uPciBiosIo));
558	devpciR3SetByte(pPciDev, VBOX_PCI_IO_BASE, (pGlobals->uPciBiosIo >> 8) & 0xf0);
559
560	/* The MMIO range for the bridge must be aligned to a 1MB boundary. */
561	if ((pGlobals->uPciBiosMmio % _1M) != 0)
562	pGlobals->uPciBiosMmio = RT_ALIGN_32(pGlobals->uPciBiosMmio, _1M);
563	LogFunc(("Aligned MMIO start address. New address %#x\n", pGlobals->uPciBiosMmio));
564	devpciR3SetWord(pPciDev, VBOX_PCI_MEMORY_BASE, (pGlobals->uPciBiosMmio >> 16) & UINT32_C(0xffff0));
565
566	/* Save values to compare later to. */
567	uint32_t u32IoAddressBase = pGlobals->uPciBiosIo;
568	uint32_t u32MMIOAddressBase = pGlobals->uPciBiosMmio;
569
570	/* Init devices behind the bridge and possibly other bridges as well. */
571	PDEVPCIBUS pChildBus = PDMINS_2_DATA(pPciDev->Int.s.CTX_SUFF(pDevIns), PDEVPCIBUS);
572	for (uint32_t uDevFn = 0; uDevFn < RT_ELEMENTS(pChildBus->apDevices); uDevFn++)
573	{
574	PPDMPCIDEV pChildPciDev = pChildBus->apDevices[uDevFn];
575	if (pChildPciDev)
576	pci_bios_init_device(pGlobals, pChildBus, pChildPciDev, cBridgeDepth + 1, paBridgePositions);
577	}
578
579	/* The number of bridges behind the this one is now available. */
580	devpciR3SetByte(pPciDev, VBOX_PCI_SUBORDINATE_BUS, pGlobals->uPciBiosBus);
581
582	/*
583	* Set I/O limit register. If there is no device with I/O space behind the bridge
584	* we set a lower value than in the base register.
585	* The result with a real bridge is that no I/O transactions are passed to the secondary
586	* interface. Again this doesn't really matter here but we want to be compliant to the spec.
587	*/
588	if ((u32IoAddressBase != pGlobals->uPciBiosIo) && ((pGlobals->uPciBiosIo % _4K) != 0))
589	{
590	/* The upper boundary must be one byte less than a 4KB boundary. */
591	pGlobals->uPciBiosIo = RT_ALIGN_32(pGlobals->uPciBiosIo, _4K);
592	}
593	devpciR3SetByte(pPciDev, VBOX_PCI_IO_LIMIT, ((pGlobals->uPciBiosIo >> 8) & 0xf0) - 1);
594
595	/* Same with the MMIO limit register but with 1MB boundary here. */
596	if ((u32MMIOAddressBase != pGlobals->uPciBiosMmio) && ((pGlobals->uPciBiosMmio % _1M) != 0))
597	{
598	/* The upper boundary must be one byte less than a 1MB boundary. */
599	pGlobals->uPciBiosMmio = RT_ALIGN_32(pGlobals->uPciBiosMmio, _1M);
600	}
601	devpciR3SetWord(pPciDev, VBOX_PCI_MEMORY_LIMIT, ((pGlobals->uPciBiosMmio >> 16) & UINT32_C(0xfff0)) - 1);
602
603	/*
604	* Set the prefetch base and limit registers. We currently have no device with a prefetchable region
605	* which may be behind a bridge. That's why it is unconditionally disabled here atm by writing a higher value into
606	* the base register than in the limit register.
607	*/
608	devpciR3SetWord(pPciDev, VBOX_PCI_PREF_MEMORY_BASE, 0xfff0);
609	devpciR3SetWord(pPciDev, VBOX_PCI_PREF_MEMORY_LIMIT, 0x0);
610	devpciR3SetDWord(pPciDev, VBOX_PCI_PREF_BASE_UPPER32, 0x00);
611	devpciR3SetDWord(pPciDev, VBOX_PCI_PREF_LIMIT_UPPER32, 0x00);
612	break;
613	}
614	default:
615	default_map:
616	{
617	/* default memory mappings */
618	bool fActiveMemRegion = false;
619	bool fActiveIORegion = false;
620	/*
621	* PCI_NUM_REGIONS is 7 because of the rom region but there are only 6 base address register defined by the PCI spec.
622	* Leaving only PCI_NUM_REGIONS would cause reading another and enabling a memory region which does not exist.
623	*/
624	for (unsigned i = 0; i < (PCI_NUM_REGIONS-1); i++)
625	{
626	uint32_t u32Size;
627	uint8_t u8RessourceType;
628	uint32_t u32Address = 0x10 + i * 4;
629
630	/* Calculate size. */
631	u8RessourceType = devpciR3GetByte(pPciDev, u32Address);
632	devpciR3SetDWord(pPciDev, u32Address, UINT32_C(0xffffffff));
633	u32Size = devpciR3GetDWord(pPciDev, u32Address);
634	bool fIsPio = ((u8RessourceType & PCI_COMMAND_IOACCESS) == PCI_COMMAND_IOACCESS);
635	/* Clear resource information depending on resource type. */
636	if (fIsPio) /* I/O */
637	u32Size &= ~(0x01);
638	else /* MMIO */
639	u32Size &= ~(0x0f);
640
641	/*
642	* Invert all bits and add 1 to get size of the region.
643	* (From PCI implementation note)
644	*/
645	if (fIsPio && (u32Size & UINT32_C(0xffff0000)) == 0)
646	u32Size = (~(u32Size \| UINT32_C(0xffff0000))) + 1;
647	else
648	u32Size = (~u32Size) + 1;
649
650	Log2Func(("Size of region %u for device %d on bus %d is %u\n", i, pPciDev->uDevFn, pBus->iBus, u32Size));
651
652	if (u32Size)
653	{
654	if (fIsPio)
655	paddr = &pGlobals->uPciBiosIo;
656	else
657	paddr = &pGlobals->uPciBiosMmio;
658	uint32_t uNew = *paddr;
659	uNew = (uNew + u32Size - 1) & ~(u32Size - 1);
660	if (fIsPio)
661	uNew &= UINT32_C(0xffff);
662	/* Unconditionally exclude I/O-APIC/HPET/ROM. Pessimistic, but better than causing a mess. */
663	if (!uNew \|\| (uNew <= UINT32_C(0xffffffff) && uNew + u32Size - 1 >= UINT32_C(0xfec00000)))
664	{
665	LogRel(("PCI: no space left for BAR%u of device %u/%u/%u (vendor=%#06x device=%#06x)\n",
666	i, pBus->iBus, pPciDev->uDevFn >> 3, pPciDev->uDevFn & 7, vendor_id, device_id)); /** @todo make this a VM start failure later. */
667	/* Undo the mapping mess caused by the size probing. */
668	devpciR3SetDWord(pPciDev, u32Address, UINT32_C(0));
669	}
670	else
671	{
672	LogFunc(("Start address of %s region %u is %#x\n", (fIsPio ? "I/O" : "MMIO"), i, uNew));
673	devpciR3BiosInitSetRegionAddress(pBus, pPciDev, i, uNew);
674	if (fIsPio)
675	fActiveIORegion = true;
676	else
677	fActiveMemRegion = true;
678	*paddr = uNew + u32Size;
679	Log2Func(("New address is %#x\n", *paddr));
680	}
681	}
682	}
683
684	/* Update the command word appropriately. */
685	devpciR3SetWord(pPciDev, PCI_COMMAND,
686	devpciR3GetWord(pPciDev, PCI_COMMAND)
687	\| (fActiveMemRegion ? PCI_COMMAND_MEMACCESS : 0)
688	\| (fActiveIORegion ? PCI_COMMAND_IOACCESS : 0));
689
690	break;
691	}
692	}
693
694	/* map the interrupt */
695	pin = devpciR3GetByte(pPciDev, PCI_INTERRUPT_PIN);
696	if (pin != 0)
697	{
698	uint8_t uBridgeDevFn = pPciDev->uDevFn;
699	pin--;
700
701	/* We need to go up to the host bus to see which irq this device will assert there. */
702	while (cBridgeDepth != 0)
703	{
704	/* Get the pin the device would assert on the bridge. */
705	pin = ((uBridgeDevFn >> 3) + pin) & 3;
706	uBridgeDevFn = paBridgePositions[cBridgeDepth];
707	cBridgeDepth--;
708	}
709
710	pin = pci_slot_get_pirq(pPciDev->uDevFn, pin);
711	pic_irq = pci_irqs[pin];
712	devpciR3SetByte(pPciDev, PCI_INTERRUPT_LINE, pic_irq);
713	}
714	}
715	}
716
717	/**
718	* Worker for Fake PCI BIOS config, triggered by magic port access by BIOS.
719	*
720	* @returns VBox status code.
721	*
722	* @param pDevIns i440FX device instance.
723	*/
724	static int pciR3FakePCIBIOS(PPDMDEVINS pDevIns)
725	{
726	uint8_t elcr[2] = {0, 0};
727	PDEVPCIROOT pGlobals = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
728	PVM pVM = PDMDevHlpGetVM(pDevIns); Assert(pVM);
729	PVMCPU pVCpu = PDMDevHlpGetVMCPU(pDevIns); Assert(pVM);
730	uint32_t const cbBelow4GB = MMR3PhysGetRamSizeBelow4GB(pVM);
731	uint64_t const cbAbove4GB = MMR3PhysGetRamSizeAbove4GB(pVM);
732	RT_NOREF(cbBelow4GB, cbAbove4GB);
733
734	LogRel(("PCI: Setting up resources and interrupts\n"));
735
736	/*
737	* Set the start addresses.
738	*/
739	pGlobals->uPciBiosBus = 0;
740	pGlobals->uPciBiosIo = 0xd000;
741	pGlobals->uPciBiosMmio = UINT32_C(0xf0000000);
742
743	/*
744	* Activate IRQ mappings.
745	*/
746	PPDMPCIDEV pPIIX3 = &pGlobals->Piix3.PIIX3State.dev;
747	for (unsigned i = 0; i < 4; i++)
748	{
749	uint8_t irq = pci_irqs[i];
750	/* Set to trigger level. */
751	elcr[irq >> 3] \|= (1 << (irq & 7));
752	/* Activate irq remapping in PIIX3. */
753	devpciR3SetByte(pPIIX3, 0x60 + i, irq);
754	}
755
756	/* Tell to the PIC. */
757	VBOXSTRICTRC rcStrict = IOMIOPortWrite(pVM, pVCpu, 0x4d0, elcr[0], sizeof(uint8_t));
758	if (rcStrict == VINF_SUCCESS)
759	rcStrict = IOMIOPortWrite(pVM, pVCpu, 0x4d1, elcr[1], sizeof(uint8_t));
760	if (rcStrict != VINF_SUCCESS)
761	{
762	AssertMsgFailed(("Writing to PIC failed! rcStrict=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
763	return RT_SUCCESS(rcStrict) ? VERR_INTERNAL_ERROR : VBOXSTRICTRC_VAL(rcStrict);
764	}
765
766	/*
767	* Init the devices.
768	*/
769	PDEVPCIBUS pBus = &pGlobals->PciBus;
770	for (uint32_t uDevFn = 0; uDevFn < RT_ELEMENTS(pBus->apDevices); uDevFn++)
771	{
772	PPDMPCIDEV pPciDev = pBus->apDevices[uDevFn];
773	uint8_t aBridgePositions[256];
774
775	if (pPciDev)
776	{
777	memset(aBridgePositions, 0, sizeof(aBridgePositions));
778	Log2(("PCI: Initializing device %d (%#x)\n",
779	uDevFn, 0x80000000 \| (uDevFn << 8)));
780	pci_bios_init_device(pGlobals, pBus, pPciDev, 0, aBridgePositions);
781	}
782	}
783
784	return VINF_SUCCESS;
785	}
786
787	#endif /* IN_RING3 */
788
789
790	/* -=-=-=-=-=- I/O ports -=-=-=-=-=- */
791
792	/**
793	* @callback_method_impl{FNIOMIOPORTOUT, PCI address}
794	*/
795	PDMBOTHCBDECL(int) pciIOPortAddressWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
796	{
797	LogFunc(("Port=%#x u32=%#x cb=%d\n", Port, u32, cb));
798	RT_NOREF2(Port, pvUser);
799	if (cb == 4)
800	{
801	PDEVPCIROOT pThis = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
802	PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_WRITE);
803	pThis->uConfigReg = u32 & ~3; /* Bits 0-1 are reserved and we silently clear them */
804	PCI_UNLOCK(pDevIns);
805	}
806	/* else: 440FX does "pass through to the bus" for other writes, what ever that means.
807	* Linux probes for cmd640 using byte writes/reads during ide init. We'll just ignore it. */
808	return VINF_SUCCESS;
809	}
810
811
812	/**
813	* @callback_method_impl{FNIOMIOPORTIN, PCI address}
814	*/
815	PDMBOTHCBDECL(int) pciIOPortAddressRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
816	{
817	RT_NOREF2(Port, pvUser);
818	if (cb == 4)
819	{
820	PDEVPCIROOT pThis = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
821	PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_READ);
822	*pu32 = pThis->uConfigReg;
823	PCI_UNLOCK(pDevIns);
824	LogFunc(("Port=%#x cb=%d -> %#x\n", Port, cb, *pu32));
825	return VINF_SUCCESS;
826	}
827	/* else: 440FX does "pass through to the bus" for other writes, what ever that means.
828	* Linux probes for cmd640 using byte writes/reads during ide init. We'll just ignore it. */
829	LogFunc(("Port=%#x cb=%d VERR_IOM_IOPORT_UNUSED\n", Port, cb));
830	return VERR_IOM_IOPORT_UNUSED;
831	}
832
833
834	/**
835	* @callback_method_impl{FNIOMIOPORTOUT, PCI data}
836	*/
837	PDMBOTHCBDECL(int) pciIOPortDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
838	{
839	LogFunc(("Port=%#x u32=%#x cb=%d\n", Port, u32, cb));
840	NOREF(pvUser);
841	int rc = VINF_SUCCESS;
842	if (!(Port % cb))
843	{
844	PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_WRITE);
845	rc = pci_data_write(PDMINS_2_DATA(pDevIns, PDEVPCIROOT), Port, u32, cb);
846	PCI_UNLOCK(pDevIns);
847	}
848	else
849	AssertMsgFailed(("Write to port %#x u32=%#x cb=%d\n", Port, u32, cb));
850	return rc;
851	}
852
853
854	/**
855	* @callback_method_impl{FNIOMIOPORTIN, PCI data}
856	*/
857	PDMBOTHCBDECL(int) pciIOPortDataRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
858	{
859	NOREF(pvUser);
860	if (!(Port % cb))
861	{
862	PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_READ);
863	int rc = pci_data_read(PDMINS_2_DATA(pDevIns, PDEVPCIROOT), Port, cb, pu32);
864	PCI_UNLOCK(pDevIns);
865	LogFunc(("Port=%#x cb=%#x -> %#x (%Rrc)\n", Port, cb, *pu32, rc));
866	return rc;
867	}
868	AssertMsgFailed(("Read from port %#x cb=%d\n", Port, cb));
869	return VERR_IOM_IOPORT_UNUSED;
870	}
871
872	#ifdef IN_RING3
873
874	/**
875	* @callback_method_impl{FNIOMIOPORTOUT, PCI data}
876	*/
877	DECLCALLBACK(int) pciR3IOPortMagicPCIWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
878	{
879	RT_NOREF2(pvUser, Port);
880	LogFunc(("Port=%#x u32=%#x cb=%d\n", Port, u32, cb));
881	if (cb == 4)
882	{
883	if (u32 == UINT32_C(19200509)) // Richard Adams
884	{
885	int rc = pciR3FakePCIBIOS(pDevIns);
886	AssertRC(rc);
887	}
888	}
889
890	return VINF_SUCCESS;
891	}
892
893	/**
894	* @callback_method_impl{FNIOMIOPORTIN, PCI data}
895	*/
896	DECLCALLBACK(int) pciR3IOPortMagicPCIRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
897	{
898	RT_NOREF5(pDevIns, pvUser, Port, pu32, cb);
899	LogFunc(("Port=%#x cb=%d VERR_IOM_IOPORT_UNUSED\n", Port, cb));
900	return VERR_IOM_IOPORT_UNUSED;
901	}
902
903
904	/*
905	* Include code we share with the other PCI bus implementation.
906	*
907	* Note! No #ifdefs, use instant data booleans/flags/whatever. Goal is to
908	* completely merge these files! File #1 contains code we write, where
909	* as a possible file #2 contains external code if there's any left.
910	*/
911	# include "DevPciMerge1.cpp.h"
912
913
914	/* -=-=-=-=-=- Saved state -=-=-=-=-=- */
915
916	/**
917	* Common worker for pciR3SaveExec and pcibridgeR3SaveExec.
918	*
919	* @returns VBox status code.
920	* @param pBus The bus to save.
921	* @param pSSM The saved state handle.
922	*/
923	static int pciR3CommonSaveExec(PDEVPCIBUS pBus, PSSMHANDLE pSSM)
924	{
925	/*
926	* Iterate thru all the devices.
927	*/
928	for (uint32_t uDevFn = 0; uDevFn < RT_ELEMENTS(pBus->apDevices); uDevFn++)
929	{
930	PPDMPCIDEV pDev = pBus->apDevices[uDevFn];
931	if (pDev)
932	{
933	SSMR3PutU32(pSSM, uDevFn);
934	SSMR3PutMem(pSSM, pDev->abConfig, sizeof(pDev->abConfig));
935
936	SSMR3PutS32(pSSM, pDev->Int.s.uIrqPinState);
937
938	/* Save the type an size of all the regions. */
939	for (uint32_t iRegion = 0; iRegion < VBOX_PCI_NUM_REGIONS; iRegion++)
940	{
941	SSMR3PutU8(pSSM, pDev->Int.s.aIORegions[iRegion].type);
942	SSMR3PutU64(pSSM, pDev->Int.s.aIORegions[iRegion].size);
943	}
944	}
945	}
946	return SSMR3PutU32(pSSM, UINT32_MAX); /* terminator */
947	}
948
949
950	/**
951	* @callback_method_impl{FNSSMDEVSAVEEXEC}
952	*/
953	static DECLCALLBACK(int) pciR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
954	{
955	PDEVPCIROOT pThis = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
956
957	/*
958	* Bus state data.
959	*/
960	SSMR3PutU32(pSSM, pThis->uConfigReg);
961	SSMR3PutBool(pSSM, pThis->fUseIoApic);
962
963	/*
964	* Save IRQ states.
965	*/
966	for (unsigned i = 0; i < RT_ELEMENTS(pThis->Piix3.auPciLegacyIrqLevels); i++)
967	SSMR3PutU32(pSSM, pThis->Piix3.auPciLegacyIrqLevels[i]);
968	for (unsigned i = 0; i < RT_ELEMENTS(pThis->auPciApicIrqLevels); i++)
969	SSMR3PutU32(pSSM, pThis->auPciApicIrqLevels[i]);
970
971	SSMR3PutU32(pSSM, pThis->Piix3.iAcpiIrqLevel);
972	SSMR3PutS32(pSSM, pThis->Piix3.iAcpiIrq);
973
974	SSMR3PutU32(pSSM, UINT32_MAX); /* separator */
975
976	/*
977	* Join paths with pcibridgeR3SaveExec.
978	*/
979	return pciR3CommonSaveExec(&pThis->PciBus, pSSM);
980	}
981
982
983	/**
984	* Common worker for pciR3LoadExec and pcibridgeR3LoadExec.
985	*
986	* @returns VBox status code.
987	* @param pBus The bus which data is being loaded.
988	* @param pSSM The saved state handle.
989	* @param uVersion The data version.
990	* @param uPass The pass.
991	*/
992	static DECLCALLBACK(int) pciR3CommonLoadExec(PDEVPCIBUS pBus, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
993	{
994	uint32_t u32;
995	int rc;
996
997	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
998
999	/*
1000	* Iterate thru all the devices and write 0 to the COMMAND register so
1001	* that all the memory is unmapped before we start restoring the saved
1002	* mapping locations.
1003	*
1004	* The register value is restored afterwards so we can do proper
1005	* LogRels in devpciR3CommonRestoreConfig.
1006	*/
1007	for (uint32_t uDevFn = 0; uDevFn < RT_ELEMENTS(pBus->apDevices); uDevFn++)
1008	{
1009	PPDMPCIDEV pDev = pBus->apDevices[uDevFn];
1010	if (pDev)
1011	{
1012	uint16_t u16 = PCIDevGetCommand(pDev);
1013	pDev->Int.s.pfnConfigWrite(pDev->Int.s.CTX_SUFF(pDevIns), pDev, VBOX_PCI_COMMAND, 0, 2);
1014	PCIDevSetCommand(pDev, u16);
1015	Assert(PCIDevGetCommand(pDev) == u16);
1016	}
1017	}
1018
1019	/*
1020	* Iterate all the devices.
1021	*/
1022	for (uint32_t uDevFn = 0;; uDevFn++)
1023	{
1024	/* index / terminator */
1025	rc = SSMR3GetU32(pSSM, &u32);
1026	if (RT_FAILURE(rc))
1027	return rc;
1028	if (u32 == UINT32_MAX)
1029	break;
1030	if ( u32 >= RT_ELEMENTS(pBus->apDevices)
1031	\|\| u32 < uDevFn)
1032	{
1033	AssertMsgFailed(("u32=%#x uDevFn=%#x\n", u32, uDevFn));
1034	return rc;
1035	}
1036
1037	/* skip forward to the device checking that no new devices are present. */
1038	for (; uDevFn < u32; uDevFn++)
1039	{
1040	if (pBus->apDevices[uDevFn])
1041	{
1042	LogRel(("PCI: New device in slot %#x, %s (vendor=%#06x device=%#06x)\n", uDevFn, pBus->apDevices[uDevFn]->pszNameR3,
1043	PCIDevGetVendorId(pBus->apDevices[uDevFn]), PCIDevGetDeviceId(pBus->apDevices[uDevFn])));
1044	if (SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT)
1045	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("New device in slot %#x, %s (vendor=%#06x device=%#06x)"),
1046	uDevFn, pBus->apDevices[uDevFn]->pszNameR3, PCIDevGetVendorId(pBus->apDevices[uDevFn]), PCIDevGetDeviceId(pBus->apDevices[uDevFn]));
1047	}
1048	}
1049
1050	/* get the data */
1051	PDMPCIDEV DevTmp;
1052	RT_ZERO(DevTmp);
1053	DevTmp.Int.s.uIrqPinState = ~0; /* Invalid value in case we have an older saved state to force a state change in pciSetIrq. */
1054	SSMR3GetMem(pSSM, DevTmp.abConfig, sizeof(DevTmp.abConfig));
1055	if (uVersion < VBOX_PCI_SAVED_STATE_VERSION_IRQ_STATES)
1056	{
1057	int32_t i32Temp;
1058	/* Irq value not needed anymore. */
1059	rc = SSMR3GetS32(pSSM, &i32Temp);
1060	if (RT_FAILURE(rc))
1061	return rc;
1062	}
1063	else
1064	{
1065	rc = SSMR3GetS32(pSSM, &DevTmp.Int.s.uIrqPinState);
1066	if (RT_FAILURE(rc))
1067	return rc;
1068	}
1069
1070	/* Load the region types and sizes. */
1071	if (uVersion >= VBOX_PCI_SAVED_STATE_VERSION_REGION_SIZES)
1072	{
1073	for (uint32_t iRegion = 0; iRegion < VBOX_PCI_NUM_REGIONS; iRegion++)
1074	{
1075	SSMR3GetU8(pSSM, &DevTmp.Int.s.aIORegions[iRegion].type);
1076	rc = SSMR3GetU64(pSSM, &DevTmp.Int.s.aIORegions[iRegion].size);
1077	AssertLogRelRCReturn(rc, rc);
1078	}
1079	}
1080
1081	/* check that it's still around. */
1082	PPDMPCIDEV pDev = pBus->apDevices[uDevFn];
1083	if (!pDev)
1084	{
1085	LogRel(("PCI: Device in slot %#x has been removed! vendor=%#06x device=%#06x\n", uDevFn,
1086	PCIDevGetVendorId(&DevTmp), PCIDevGetDeviceId(&DevTmp)));
1087	if (SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT)
1088	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Device in slot %#x has been removed! vendor=%#06x device=%#06x"),
1089	uDevFn, PCIDevGetVendorId(&DevTmp), PCIDevGetDeviceId(&DevTmp));
1090	continue;
1091	}
1092
1093	/* match the vendor id assuming that this will never be changed. */
1094	if ( DevTmp.abConfig[0] != pDev->abConfig[0]
1095	\|\| DevTmp.abConfig[1] != pDev->abConfig[1])
1096	return SSMR3SetCfgError(pSSM, RT_SRC_POS,
1097	N_("Device in slot %#x (%s) vendor id mismatch! saved=%.4Rhxs current=%.4Rhxs"),
1098	uDevFn, pDev->pszNameR3, DevTmp.abConfig, pDev->abConfig);
1099
1100	/* commit the loaded device config. */
1101	rc = devpciR3CommonRestoreRegions(pSSM, pDev, DevTmp.Int.s.aIORegions,
1102	uVersion >= VBOX_PCI_SAVED_STATE_VERSION_REGION_SIZES);
1103	if (RT_FAILURE(rc))
1104	break;
1105	devpciR3CommonRestoreConfig(pDev, &DevTmp.abConfig[0]);
1106
1107	pDev->Int.s.uIrqPinState = DevTmp.Int.s.uIrqPinState;
1108	}
1109
1110	return VINF_SUCCESS;
1111	}
1112
1113
1114	/**
1115	* @callback_method_impl{FNSSMDEVLOADEXEC}
1116	*/
1117	static DECLCALLBACK(int) pciR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1118	{
1119	PDEVPCIROOT pThis = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
1120	PDEVPCIBUS pBus = &pThis->PciBus;
1121	uint32_t u32;
1122	int rc;
1123
1124	/*
1125	* Check the version.
1126	*/
1127	if (uVersion > VBOX_PCI_SAVED_STATE_VERSION)
1128	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1129	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
1130
1131	/*
1132	* Bus state data.
1133	*/
1134	SSMR3GetU32(pSSM, &pThis->uConfigReg);
1135	if (uVersion >= VBOX_PCI_SAVED_STATE_VERSION_USE_IO_APIC)
1136	SSMR3GetBool(pSSM, &pThis->fUseIoApic);
1137
1138	/* Load IRQ states. */
1139	if (uVersion >= VBOX_PCI_SAVED_STATE_VERSION_IRQ_STATES)
1140	{
1141	for (uint8_t i = 0; i < RT_ELEMENTS(pThis->Piix3.auPciLegacyIrqLevels); i++)
1142	SSMR3GetU32(pSSM, (uint32_t *)&pThis->Piix3.auPciLegacyIrqLevels[i]);
1143	for (uint8_t i = 0; i < RT_ELEMENTS(pThis->auPciApicIrqLevels); i++)
1144	SSMR3GetU32(pSSM, (uint32_t *)&pThis->auPciApicIrqLevels[i]);
1145
1146	SSMR3GetU32(pSSM, &pThis->Piix3.iAcpiIrqLevel);
1147	SSMR3GetS32(pSSM, &pThis->Piix3.iAcpiIrq);
1148	}
1149
1150	/* separator */
1151	rc = SSMR3GetU32(pSSM, &u32);
1152	if (RT_FAILURE(rc))
1153	return rc;
1154	if (u32 != UINT32_MAX)
1155	AssertMsgFailedReturn(("u32=%#x\n", u32), rc);
1156
1157	/*
1158	* The devices.
1159	*/
1160	return pciR3CommonLoadExec(pBus, pSSM, uVersion, uPass);
1161	}
1162
1163
1164	/* -=-=-=-=-=- PCI Bus Interface Methods (PDMPCIBUSREG) -=-=-=-=-=- */
1165
1166
1167	/* -=-=-=-=-=- Debug Info Handlers -=-=-=-=-=- */
1168
1169	/**
1170	* @callback_method_impl{FNDBGFHANDLERDEV}
1171	*/
1172	static DECLCALLBACK(void) pciR3IrqRouteInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
1173	{
1174	PDEVPCIROOT pGlobals = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
1175	PPDMPCIDEV pPIIX3 = &pGlobals->Piix3.PIIX3State.dev;
1176	NOREF(pszArgs);
1177
1178	uint16_t router = pPIIX3->uDevFn;
1179	pHlp->pfnPrintf(pHlp, "PCI interrupt router at: %02X:%02X:%X\n",
1180	router >> 8, (router >> 3) & 0x1f, router & 0x7);
1181
1182	for (int i = 0; i < 4; ++i)
1183	{
1184	uint8_t irq_map = devpciR3GetByte(pPIIX3, 0x60 + i);
1185	if (irq_map & 0x80)
1186	pHlp->pfnPrintf(pHlp, "PIRQ%c disabled\n", 'A' + i);
1187	else
1188	pHlp->pfnPrintf(pHlp, "PIRQ%c -> IRQ%d\n", 'A' + i, irq_map & 0xf);
1189	}
1190	}
1191
1192
1193	/* -=-=-=-=-=- PDMDEVREG -=-=-=-=-=- */
1194
1195
1196	/**
1197	* @interface_method_impl{PDMDEVREG,pfnConstruct}
1198	*/
1199	static DECLCALLBACK(int) pciR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
1200	{
1201	RT_NOREF1(iInstance);
1202	Assert(iInstance == 0);
1203	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
1204
1205	/*
1206	* Validate and read configuration.
1207	*/
1208	if (!CFGMR3AreValuesValid(pCfg, "IOAPIC\0" "GCEnabled\0" "R0Enabled\0"))
1209	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
1210
1211	/* query whether we got an IOAPIC */
1212	bool fUseIoApic;
1213	int rc = CFGMR3QueryBoolDef(pCfg, "IOAPIC", &fUseIoApic, false);
1214	if (RT_FAILURE(rc))
1215	return PDMDEV_SET_ERROR(pDevIns, rc,
1216	N_("Configuration error: Failed to query boolean value \"IOAPIC\""));
1217
1218	/* check if RC code is enabled. */
1219	bool fGCEnabled;
1220	rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
1221	if (RT_FAILURE(rc))
1222	return PDMDEV_SET_ERROR(pDevIns, rc,
1223	N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
1224
1225	/* check if R0 code is enabled. */
1226	bool fR0Enabled;
1227	rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
1228	if (RT_FAILURE(rc))
1229	return PDMDEV_SET_ERROR(pDevIns, rc,
1230	N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
1231	Log(("PCI: fUseIoApic=%RTbool fGCEnabled=%RTbool fR0Enabled=%RTbool\n", fUseIoApic, fGCEnabled, fR0Enabled));
1232
1233	/*
1234	* Init data and register the PCI bus.
1235	*/
1236	PDEVPCIROOT pGlobals = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
1237	pGlobals->uPciBiosIo = 0xc000;
1238	pGlobals->uPciBiosMmio = 0xf0000000;
1239	memset((void *)&pGlobals->Piix3.auPciLegacyIrqLevels, 0, sizeof(pGlobals->Piix3.auPciLegacyIrqLevels));
1240	pGlobals->fUseIoApic = fUseIoApic;
1241	memset((void *)&pGlobals->auPciApicIrqLevels, 0, sizeof(pGlobals->auPciApicIrqLevels));
1242
1243	pGlobals->pDevInsR3 = pDevIns;
1244	pGlobals->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
1245	pGlobals->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
1246
1247	pGlobals->PciBus.fTypePiix3 = true;
1248	pGlobals->PciBus.fTypeIch9 = false;
1249	pGlobals->PciBus.fPureBridge = false;
1250	pGlobals->PciBus.pDevInsR3 = pDevIns;
1251	pGlobals->PciBus.pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
1252	pGlobals->PciBus.pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
1253	pGlobals->PciBus.papBridgesR3 = (PPDMPCIDEV *)PDMDevHlpMMHeapAllocZ(pDevIns,
1254	sizeof(PPDMPCIDEV)
1255	* RT_ELEMENTS(pGlobals->PciBus.apDevices));
1256	AssertLogRelReturn(pGlobals->PciBus.papBridgesR3, VERR_NO_MEMORY);
1257
1258
1259	PDMPCIBUSREG PciBusReg;
1260	PDEVPCIBUS pBus = &pGlobals->PciBus;
1261	PciBusReg.u32Version = PDM_PCIBUSREG_VERSION;
1262	PciBusReg.pfnRegisterR3 = pciR3MergedRegister;
1263	PciBusReg.pfnRegisterMsiR3 = NULL;
1264	PciBusReg.pfnIORegionRegisterR3 = devpciR3CommonIORegionRegister;
1265	PciBusReg.pfnSetConfigCallbacksR3 = devpciR3CommonSetConfigCallbacks;
1266	PciBusReg.pfnSetIrqR3 = pciSetIrq;
1267	PciBusReg.pszSetIrqRC = fGCEnabled ? "pciSetIrq" : NULL;
1268	PciBusReg.pszSetIrqR0 = fR0Enabled ? "pciSetIrq" : NULL;
1269	rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBus->pPciHlpR3, &pBus->iBus);
1270	if (RT_FAILURE(rc))
1271	return PDMDEV_SET_ERROR(pDevIns, rc,
1272	N_("Failed to register ourselves as a PCI Bus"));
1273	Assert(pBus->iBus == 0);
1274	if (pBus->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
1275	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
1276	N_("PCI helper version mismatch; got %#x expected %#x"),
1277	pBus->pPciHlpR3->u32Version, PDM_PCIHLPR3_VERSION);
1278
1279	pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
1280	pBus->pPciHlpR0 = pBus->pPciHlpR3->pfnGetR0Helpers(pDevIns);
1281
1282	/* Disable default device locking. */
1283	rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
1284	AssertRCReturn(rc, rc);
1285
1286	/*
1287	* Fill in PCI configs and add them to the bus.
1288	*/
1289	/* i440FX */
1290	PCIDevSetVendorId( &pBus->PciDev, 0x8086); /* Intel */
1291	PCIDevSetDeviceId( &pBus->PciDev, 0x1237);
1292	PCIDevSetRevisionId(&pBus->PciDev, 0x02);
1293	PCIDevSetClassSub( &pBus->PciDev, 0x00); /* host2pci */
1294	PCIDevSetClassBase( &pBus->PciDev, 0x06); /* PCI_bridge */
1295	PCIDevSetHeaderType(&pBus->PciDev, 0x00);
1296	rc = PDMDevHlpPCIRegisterEx(pDevIns, &pBus->PciDev, PDMPCIDEVREG_CFG_PRIMARY, 0 /fFlags/,
1297	0 /uPciDevNo/, 0 /uPciFunNo/, "i440FX");
1298	AssertLogRelRCReturn(rc, rc);
1299
1300	/* PIIX3 */
1301	PCIDevSetVendorId( &pGlobals->Piix3.PIIX3State.dev, 0x8086); /* Intel */
1302	PCIDevSetDeviceId( &pGlobals->Piix3.PIIX3State.dev, 0x7000); /* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */
1303	PCIDevSetClassSub( &pGlobals->Piix3.PIIX3State.dev, 0x01); /* PCI_ISA */
1304	PCIDevSetClassBase( &pGlobals->Piix3.PIIX3State.dev, 0x06); /* PCI_bridge */
1305	PCIDevSetHeaderType(&pGlobals->Piix3.PIIX3State.dev, 0x80); /* PCI_multifunction, generic */
1306	rc = PDMDevHlpPCIRegisterEx(pDevIns, &pGlobals->Piix3.PIIX3State.dev, PDMPCIDEVREG_CFG_NEXT, 0 /fFlags/,
1307	1 /uPciDevNo/, 0 /uPciFunNo/, "PIIX3");
1308	AssertLogRelRCReturn(rc, rc);
1309	pciR3Piix3Reset(&pGlobals->Piix3.PIIX3State);
1310
1311	pBus->iDevSearch = 16;
1312
1313	/*
1314	* Register I/O ports and save state.
1315	*/
1316	rc = PDMDevHlpIOPortRegister(pDevIns, 0x0cf8, 1, NULL, pciIOPortAddressWrite, pciIOPortAddressRead, NULL, NULL, "i440FX (PCI)");
1317	if (RT_FAILURE(rc))
1318	return rc;
1319	rc = PDMDevHlpIOPortRegister(pDevIns, 0x0cfc, 4, NULL, pciIOPortDataWrite, pciIOPortDataRead, NULL, NULL, "i440FX (PCI)");
1320	if (RT_FAILURE(rc))
1321	return rc;
1322	if (fGCEnabled)
1323	{
1324	rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x0cf8, 1, NIL_RTGCPTR, "pciIOPortAddressWrite", "pciIOPortAddressRead", NULL, NULL, "i440FX (PCI)");
1325	if (RT_FAILURE(rc))
1326	return rc;
1327	rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x0cfc, 4, NIL_RTGCPTR, "pciIOPortDataWrite", "pciIOPortDataRead", NULL, NULL, "i440FX (PCI)");
1328	if (RT_FAILURE(rc))
1329	return rc;
1330	}
1331	if (fR0Enabled)
1332	{
1333	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x0cf8, 1, NIL_RTR0PTR, "pciIOPortAddressWrite", "pciIOPortAddressRead", NULL, NULL, "i440FX (PCI)");
1334	if (RT_FAILURE(rc))
1335	return rc;
1336	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x0cfc, 4, NIL_RTR0PTR, "pciIOPortDataWrite", "pciIOPortDataRead", NULL, NULL, "i440FX (PCI)");
1337	if (RT_FAILURE(rc))
1338	return rc;
1339	}
1340
1341	rc = PDMDevHlpIOPortRegister(pDevIns, 0x0410, 1, NULL, pciR3IOPortMagicPCIWrite, pciR3IOPortMagicPCIRead, NULL, NULL, "i440FX (Fake PCI BIOS trigger)")
1342	;
1343	if (RT_FAILURE(rc))
1344	return rc;
1345
1346
1347	rc = PDMDevHlpSSMRegisterEx(pDevIns, VBOX_PCI_SAVED_STATE_VERSION, sizeof(pBus) + 16128, "pgm",
1348	NULL, NULL, NULL,
1349	NULL, pciR3SaveExec, NULL,
1350	NULL, pciR3LoadExec, NULL);
1351	if (RT_FAILURE(rc))
1352	return rc;
1353
1354	PDMDevHlpDBGFInfoRegister(pDevIns, "pci",
1355	"Display PCI bus status. Recognizes 'basic' or 'verbose' as arguments, defaults to 'basic'.",
1356	devpciR3InfoPci);
1357	PDMDevHlpDBGFInfoRegister(pDevIns, "pciirq", "Display PCI IRQ state. (no arguments)", devpciR3InfoPciIrq);
1358	PDMDevHlpDBGFInfoRegister(pDevIns, "irqroute", "Display PCI IRQ routing. (no arguments)", pciR3IrqRouteInfo);
1359
1360	return VINF_SUCCESS;
1361	}
1362
1363
1364	/**
1365	* @interface_method_impl{PDMDEVREG,pfnDestruct}
1366	*/
1367	static DECLCALLBACK(int) pciR3Destruct(PPDMDEVINS pDevIns)
1368	{
1369	PDEVPCIROOT pGlobals = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
1370	if (pGlobals->PciBus.papBridgesR3)
1371	{
1372	PDMDevHlpMMHeapFree(pDevIns, pGlobals->PciBus.papBridgesR3);
1373	pGlobals->PciBus.papBridgesR3 = NULL;
1374	}
1375	return VINF_SUCCESS;
1376	}
1377
1378
1379	/**
1380	* @interface_method_impl{PDMDEVREG,pfnReset}
1381	*/
1382	static DECLCALLBACK(void) pciR3Reset(PPDMDEVINS pDevIns)
1383	{
1384	PDEVPCIROOT pGlobals = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
1385	PDEVPCIBUS pBus = &pGlobals->PciBus;
1386
1387	/* PCI-specific reset for each device. */
1388	for (uint32_t uDevFn = 0; uDevFn < RT_ELEMENTS(pBus->apDevices); uDevFn++)
1389	{
1390	if (pBus->apDevices[uDevFn])
1391	devpciR3ResetDevice(pBus->apDevices[uDevFn]);
1392	}
1393
1394	pciR3Piix3Reset(&pGlobals->Piix3.PIIX3State);
1395	}
1396
1397
1398	/**
1399	* The device registration structure.
1400	*/
1401	const PDMDEVREG g_DevicePCI =
1402	{
1403	/* u32Version */
1404	PDM_DEVREG_VERSION,
1405	/* szName */
1406	"pci",
1407	/* szRCMod */
1408	"VBoxDDRC.rc",
1409	/* szR0Mod */
1410	"VBoxDDR0.r0",
1411	/* pszDescription */
1412	"i440FX PCI bridge and PIIX3 ISA bridge.",
1413	/* fFlags */
1414	PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
1415	/* fClass */
1416	PDM_DEVREG_CLASS_BUS_PCI \| PDM_DEVREG_CLASS_BUS_ISA,
1417	/* cMaxInstances */
1418	1,
1419	/* cbInstance */
1420	sizeof(DEVPCIROOT),
1421	/* pfnConstruct */
1422	pciR3Construct,
1423	/* pfnDestruct */
1424	pciR3Destruct,
1425	/* pfnRelocate */
1426	devpciR3RootRelocate,
1427	/* pfnMemSetup */
1428	NULL,
1429	/* pfnPowerOn */
1430	NULL,
1431	/* pfnReset */
1432	pciR3Reset,
1433	/* pfnSuspend */
1434	NULL,
1435	/* pfnResume */
1436	NULL,
1437	/* pfnAttach */
1438	NULL,
1439	/* pfnDetach */
1440	NULL,
1441	/* pfnQueryInterface */
1442	NULL,
1443	/* pfnInitComplete */
1444	NULL,
1445	/* pfnPowerOff */
1446	NULL,
1447	/* pfnSoftReset */
1448	NULL,
1449	/* u32VersionEnd */
1450	PDM_DEVREG_VERSION
1451
1452	};
1453	#endif /* IN_RING3 */
1454
1455
1456
1457	/* -=-=-=-=-=- The PCI bridge specific bits -=-=-=-=-=- */
1458
1459	/**
1460	* @interface_method_impl{PDMPCIBUSREG,pfnSetIrqR3}
1461	*/
1462	PDMBOTHCBDECL(void) pcibridgeSetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc)
1463	{
1464	/*
1465	* The PCI-to-PCI bridge specification defines how the interrupt pins
1466	* are routed from the secondary to the primary bus (see chapter 9).
1467	* iIrq gives the interrupt pin the pci device asserted.
1468	* We change iIrq here according to the spec and call the SetIrq function
1469	* of our parent passing the device which asserted the interrupt instead of the device of the bridge.
1470	*/
1471	PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
1472	PPDMPCIDEV pPciDevBus = pPciDev;
1473	int iIrqPinBridge = iIrq;
1474	uint8_t uDevFnBridge = 0;
1475
1476	/* Walk the chain until we reach the host bus. */
1477	do
1478	{
1479	uDevFnBridge = pBus->PciDev.uDevFn;
1480	iIrqPinBridge = ((pPciDevBus->uDevFn >> 3) + iIrqPinBridge) & 3;
1481
1482	/* Get the parent. */
1483	pBus = pBus->PciDev.Int.s.CTX_SUFF(pBus);
1484	pPciDevBus = &pBus->PciDev;
1485	} while (pBus->iBus != 0);
1486
1487	AssertMsg(pBus->iBus == 0, ("This is not the host pci bus iBus=%d\n", pBus->iBus));
1488	pciSetIrqInternal(DEVPCIBUS_2_DEVPCIROOT(pBus), uDevFnBridge, pPciDev, iIrqPinBridge, iLevel, uTagSrc);
1489	}
1490
1491	#ifdef IN_RING3
1492
1493	/**
1494	* @callback_method_impl{FNPCIBRIDGECONFIGWRITE}
1495	*/
1496	static DECLCALLBACK(void) pcibridgeR3ConfigWrite(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice, uint32_t u32Address, uint32_t u32Value, unsigned cb)
1497	{
1498	PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
1499
1500	LogFlowFunc(("pDevIns=%p iBus=%d iDevice=%d u32Address=%u u32Value=%u cb=%d\n", pDevIns, iBus, iDevice, u32Address, u32Value, cb));
1501
1502	/* If the current bus is not the target bus search for the bus which contains the device. */
1503	if (iBus != pBus->PciDev.abConfig[VBOX_PCI_SECONDARY_BUS])
1504	{
1505	PPDMPCIDEV pBridgeDevice = pciR3FindBridge(pBus, iBus);
1506	if (pBridgeDevice)
1507	{
1508	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigWrite);
1509	pBridgeDevice->Int.s.pfnBridgeConfigWrite(pBridgeDevice->Int.s.CTX_SUFF(pDevIns), iBus, iDevice, u32Address, u32Value, cb);
1510	}
1511	}
1512	else
1513	{
1514	/* This is the target bus, pass the write to the device. */
1515	PPDMPCIDEV pPciDev = pBus->apDevices[iDevice];
1516	if (pPciDev)
1517	{
1518	LogFunc(("%s: addr=%02x val=%08x len=%d\n", pPciDev->pszNameR3, u32Address, u32Value, cb));
1519	/** @todo return rc */
1520	pPciDev->Int.s.pfnConfigWrite(pPciDev->Int.s.CTX_SUFF(pDevIns), pPciDev, u32Address, u32Value, cb);
1521	}
1522	}
1523	}
1524
1525
1526	/**
1527	* @callback_method_impl{FNPCIBRIDGECONFIGREAD}
1528	*/
1529	static DECLCALLBACK(uint32_t) pcibridgeR3ConfigRead(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice, uint32_t u32Address, unsigned cb)
1530	{
1531	PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
1532	uint32_t u32Value = 0xffffffff; /* Return value in case there is no device. */
1533
1534	LogFlowFunc(("pDevIns=%p iBus=%d iDevice=%d u32Address=%u cb=%d\n", pDevIns, iBus, iDevice, u32Address, cb));
1535
1536	/* If the current bus is not the target bus search for the bus which contains the device. */
1537	if (iBus != pBus->PciDev.abConfig[VBOX_PCI_SECONDARY_BUS])
1538	{
1539	PPDMPCIDEV pBridgeDevice = pciR3FindBridge(pBus, iBus);
1540	if (pBridgeDevice)
1541	{
1542	AssertPtr( pBridgeDevice->Int.s.pfnBridgeConfigRead);
1543	u32Value = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->Int.s.CTX_SUFF(pDevIns), iBus, iDevice, u32Address, cb);
1544	}
1545	}
1546	else
1547	{
1548	/* This is the target bus, pass the read to the device. */
1549	PPDMPCIDEV pPciDev = pBus->apDevices[iDevice];
1550	if (pPciDev)
1551	{
1552	u32Value = pPciDev->Int.s.pfnConfigRead(pPciDev->Int.s.CTX_SUFF(pDevIns), pPciDev, u32Address, cb);
1553	LogFunc(("%s: u32Address=%02x u32Value=%08x cb=%d\n", pPciDev->pszNameR3, u32Address, u32Value, cb));
1554	}
1555	}
1556
1557	return u32Value;
1558	}
1559
1560
1561	/**
1562	* @callback_method_impl{FNSSMDEVSAVEEXEC}
1563	*/
1564	static DECLCALLBACK(int) pcibridgeR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
1565	{
1566	PDEVPCIBUS pThis = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
1567	return pciR3CommonSaveExec(pThis, pSSM);
1568	}
1569
1570
1571	/**
1572	* @callback_method_impl{FNSSMDEVLOADEXEC}
1573	*/
1574	static DECLCALLBACK(int) pcibridgeR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1575	{
1576	PDEVPCIBUS pThis = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
1577	if (uVersion > VBOX_PCI_SAVED_STATE_VERSION)
1578	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1579	return pciR3CommonLoadExec(pThis, pSSM, uVersion, uPass);
1580	}
1581
1582
1583	/**
1584	* @interface_method_impl{PDMDEVREG,pfnReset}
1585	*/
1586	static DECLCALLBACK(void) pcibridgeR3Reset(PPDMDEVINS pDevIns)
1587	{
1588	PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
1589
1590	/* Reset config space to default values. */
1591	pBus->PciDev.abConfig[VBOX_PCI_PRIMARY_BUS] = 0;
1592	pBus->PciDev.abConfig[VBOX_PCI_SECONDARY_BUS] = 0;
1593	pBus->PciDev.abConfig[VBOX_PCI_SUBORDINATE_BUS] = 0;
1594	}
1595
1596
1597	/**
1598	* @interface_method_impl{PDMDEVREG,pfnConstruct}
1599	*/
1600	static DECLCALLBACK(int) pcibridgeR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
1601	{
1602	RT_NOREF(iInstance);
1603	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
1604
1605	/*
1606	* Validate and read configuration.
1607	*/
1608	if (!CFGMR3AreValuesValid(pCfg, "GCEnabled\0" "R0Enabled\0"))
1609	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
1610
1611	/* check if RC code is enabled. */
1612	bool fGCEnabled;
1613	int rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
1614	if (RT_FAILURE(rc))
1615	return PDMDEV_SET_ERROR(pDevIns, rc,
1616	N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
1617
1618	/* check if R0 code is enabled. */
1619	bool fR0Enabled;
1620	rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
1621	if (RT_FAILURE(rc))
1622	return PDMDEV_SET_ERROR(pDevIns, rc,
1623	N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
1624	Log(("PCI: fGCEnabled=%RTbool fR0Enabled=%RTbool\n", fGCEnabled, fR0Enabled));
1625
1626	/*
1627	* Init data and register the PCI bus.
1628	*/
1629	PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
1630	pBus->fTypePiix3 = true;
1631	pBus->fTypeIch9 = false;
1632	pBus->fPureBridge = true;
1633	pBus->pDevInsR3 = pDevIns;
1634	pBus->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
1635	pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
1636	pBus->papBridgesR3 = (PPDMPCIDEV )PDMDevHlpMMHeapAllocZ(pDevIns, sizeof(PPDMPCIDEV) RT_ELEMENTS(pBus->apDevices));
1637	AssertLogRelReturn(pBus->papBridgesR3, VERR_NO_MEMORY);
1638
1639	PDMPCIBUSREG PciBusReg;
1640	PciBusReg.u32Version = PDM_PCIBUSREG_VERSION;
1641	PciBusReg.pfnRegisterR3 = pcibridgeR3MergedRegisterDevice;
1642	PciBusReg.pfnRegisterMsiR3 = NULL;
1643	PciBusReg.pfnIORegionRegisterR3 = devpciR3CommonIORegionRegister;
1644	PciBusReg.pfnSetConfigCallbacksR3 = devpciR3CommonSetConfigCallbacks;
1645	PciBusReg.pfnSetIrqR3 = pcibridgeSetIrq;
1646	PciBusReg.pszSetIrqRC = fGCEnabled ? "pcibridgeSetIrq" : NULL;
1647	PciBusReg.pszSetIrqR0 = fR0Enabled ? "pcibridgeSetIrq" : NULL;
1648	rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBus->pPciHlpR3, &pBus->iBus);
1649	if (RT_FAILURE(rc))
1650	return PDMDEV_SET_ERROR(pDevIns, rc,
1651	N_("Failed to register ourselves as a PCI Bus"));
1652	Assert(pBus->iBus == (uint32_t)iInstance + 1); /* Can be removed when adding support for multiple bridge implementations. */
1653	if (pBus->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
1654	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
1655	N_("PCI helper version mismatch; got %#x expected %#x"),
1656	pBus->pPciHlpR3->u32Version, PDM_PCIHLPR3_VERSION);
1657
1658	pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
1659	pBus->pPciHlpR0 = pBus->pPciHlpR3->pfnGetR0Helpers(pDevIns);
1660
1661	/*
1662	* Fill in PCI configs and add them to the bus.
1663	*/
1664	PCIDevSetVendorId( &pBus->PciDev, 0x8086); /* Intel */
1665	PCIDevSetDeviceId( &pBus->PciDev, 0x2448); /* 82801 Mobile PCI bridge. */
1666	PCIDevSetRevisionId(&pBus->PciDev, 0xf2);
1667	PCIDevSetClassSub( &pBus->PciDev, 0x04); /* pci2pci */
1668	PCIDevSetClassBase( &pBus->PciDev, 0x06); /* PCI_bridge */
1669	PCIDevSetClassProg( &pBus->PciDev, 0x01); /* Supports subtractive decoding. */
1670	PCIDevSetHeaderType(&pBus->PciDev, 0x01); /* Single function device which adheres to the PCI-to-PCI bridge spec. */
1671	PCIDevSetCommand( &pBus->PciDev, 0x0000);
1672	PCIDevSetStatus( &pBus->PciDev, 0x0020); /* 66MHz Capable. */
1673	PCIDevSetInterruptLine(&pBus->PciDev, 0x00); /* This device does not assert interrupts. */
1674
1675	/*
1676	* This device does not generate interrupts. Interrupt delivery from
1677	* devices attached to the bus is unaffected.
1678	*/
1679	PCIDevSetInterruptPin(&pBus->PciDev, 0x00);
1680
1681	/*
1682	* Register this PCI bridge. The called function will take care on which bus we will get registered.
1683	*/
1684	rc = PDMDevHlpPCIRegisterEx(pDevIns, &pBus->PciDev, PDMPCIDEVREG_CFG_PRIMARY, PDMPCIDEVREG_F_PCI_BRIDGE,
1685	PDMPCIDEVREG_DEV_NO_FIRST_UNUSED, PDMPCIDEVREG_FUN_NO_FIRST_UNUSED, "pcibridge");
1686	if (RT_FAILURE(rc))
1687	return rc;
1688	pBus->PciDev.Int.s.pfnBridgeConfigRead = pcibridgeR3ConfigRead;
1689	pBus->PciDev.Int.s.pfnBridgeConfigWrite = pcibridgeR3ConfigWrite;
1690
1691	pBus->iDevSearch = 0;
1692
1693	/*
1694	* Register SSM handlers. We use the same saved state version as for the host bridge
1695	* to make changes easier.
1696	*/
1697	rc = PDMDevHlpSSMRegisterEx(pDevIns, VBOX_PCI_SAVED_STATE_VERSION, sizeof(pBus) + 16128, "pgm",
1698	NULL, NULL, NULL,
1699	NULL, pcibridgeR3SaveExec, NULL,
1700	NULL, pcibridgeR3LoadExec, NULL);
1701	if (RT_FAILURE(rc))
1702	return rc;
1703
1704	return VINF_SUCCESS;
1705	}
1706
1707
1708	/**
1709	* @interface_method_impl{PDMDEVREG,pfnDestruct}
1710	*/
1711	static DECLCALLBACK(int) pcibridgeR3Destruct(PPDMDEVINS pDevIns)
1712	{
1713	PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
1714	if (pBus->papBridgesR3)
1715	{
1716	PDMDevHlpMMHeapFree(pDevIns, pBus->papBridgesR3);
1717	pBus->papBridgesR3 = NULL;
1718	}
1719	return VINF_SUCCESS;
1720	}
1721
1722
1723	/**
1724	* The device registration structure
1725	* for the PCI-to-PCI bridge.
1726	*/
1727	const PDMDEVREG g_DevicePCIBridge =
1728	{
1729	/* u32Version */
1730	PDM_DEVREG_VERSION,
1731	/* szName */
1732	"pcibridge",
1733	/* szRCMod */
1734	"VBoxDDRC.rc",
1735	/* szR0Mod */
1736	"VBoxDDR0.r0",
1737	/* pszDescription */
1738	"82801 Mobile PCI to PCI bridge",
1739	/* fFlags */
1740	PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
1741	/* fClass */
1742	PDM_DEVREG_CLASS_BUS_PCI,
1743	/* cMaxInstances */
1744	~0U,
1745	/* cbInstance */
1746	sizeof(DEVPCIBUS),
1747	/* pfnConstruct */
1748	pcibridgeR3Construct,
1749	/* pfnDestruct */
1750	pcibridgeR3Destruct,
1751	/* pfnRelocate */
1752	devpciR3BusRelocate,
1753	/* pfnMemSetup */
1754	NULL,
1755	/* pfnPowerOn */
1756	NULL,
1757	/* pfnReset */
1758	pcibridgeR3Reset,
1759	/* pfnSuspend */
1760	NULL,
1761	/* pfnResume */
1762	NULL,
1763	/* pfnAttach */
1764	NULL,
1765	/* pfnDetach */
1766	NULL,
1767	/* pfnQueryInterface */
1768	NULL,
1769	/* pfnInitComplete */
1770	NULL,
1771	/* pfnPowerOff */
1772	NULL,
1773	/* pfnSoftReset */
1774	NULL,
1775	/* u32VersionEnd */
1776	PDM_DEVREG_VERSION
1777	};
1778
1779	#endif /* IN_RING3 */
1780

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source: vbox/trunk/src/VBox/Devices/Bus/DevPCI.cpp@ 75142

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