DevPCI.cpp@ 83575

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1	/* $Id: DevPCI.cpp 82968 2020-02-04 10:35:17Z vboxsync $ */
2	/** @file
3	* DevPCI - PCI BUS Device.
4	*
5	* @remarks New code shall be added to DevPciIch9.cpp as that will become
6	* the common PCI bus code soon. Don't fix code in both DevPCI.cpp
7	* and DevPciIch9.cpp when it's possible to just make the latter
8	* version common. Common code uses the 'devpci' prefix, is
9	* prototyped in DevPciInternal.h, and is defined in DevPciIch9.cpp.
10	*/
11
12	/*
13	* Copyright (C) 2006-2020 Oracle Corporation
14	*
15	* This file is part of VirtualBox Open Source Edition (OSE), as
16	* available from http://www.virtualbox.org. This file is free software;
17	* you can redistribute it and/or modify it under the terms of the GNU
18	* General Public License (GPL) as published by the Free Software
19	* Foundation, in version 2 as it comes in the "COPYING" file of the
20	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
21	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
22	* --------------------------------------------------------------------
23	*
24	* This code is based on:
25	*
26	* QEMU PCI bus manager
27	*
28	* Copyright (c) 2004 Fabrice Bellard
29	*
30	* Permission is hereby granted, free of charge, to any person obtaining a copy
31	* of this software and associated documentation files (the "Software"), to deal
32	* in the Software without restriction, including without limitation the rights
33	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
34	* copies of the Software, and to permit persons to whom the Software is
35	* furnished to do so, subject to the following conditions:
36	*
37	* The above copyright notice and this permission notice shall be included in
38	* all copies or substantial portions of the Software.
39	*
40	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
41	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
42	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
43	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
44	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
45	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
46	* THE SOFTWARE.
47	*/
48
49
50	/*********************************************************************************************************************************
51	* Header Files *
52	*********************************************************************************************************************************/
53	#define LOG_GROUP LOG_GROUP_DEV_PCI
54	#define PDMPCIDEV_INCLUDE_PRIVATE /* Hack to get pdmpcidevint.h included at the right point. */
55	#include <VBox/vmm/pdmpcidev.h>
56	#include <VBox/vmm/pdmdev.h>
57	#include <VBox/vmm/mm.h>
58	#include <iprt/asm.h>
59	#include <iprt/assert.h>
60	#include <iprt/string.h>
61
62	#include "PciInline.h"
63	#include "VBoxDD.h"
64	#include "DevPciInternal.h"
65
66
67	/*********************************************************************************************************************************
68	* Defined Constants And Macros *
69	*********************************************************************************************************************************/
70	/** Saved state version of the PCI bus device. */
71	#define VBOX_PCI_SAVED_STATE_VERSION VBOX_PCI_SAVED_STATE_VERSION_REGION_SIZES
72	/** Adds I/O region types and sizes for dealing changes in resource regions. */
73	#define VBOX_PCI_SAVED_STATE_VERSION_REGION_SIZES 4
74	/** Before region sizes, the first named one.
75	* Looking at the code though, we support even older version. */
76	#define VBOX_PCI_SAVED_STATE_VERSION_IRQ_STATES 3
77	/** Notes whether we use the I/O APIC. */
78	#define VBOX_PCI_SAVED_STATE_VERSION_USE_IO_APIC 2
79
80
81	/*********************************************************************************************************************************
82	* Internal Functions *
83	*********************************************************************************************************************************/
84	RT_C_DECLS_BEGIN
85
86	static DECLCALLBACK(void) pcibridgeSetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTag);
87
88	#ifdef IN_RING3
89	DECLINLINE(PPDMPCIDEV) pciR3FindBridge(PDEVPCIBUS pBus, uint8_t iBus);
90	#endif
91
92	RT_C_DECLS_END
93
94	#define DEBUG_PCI
95
96	#define PCI_VENDOR_ID 0x00 /* 16 bits */
97	#define PCI_DEVICE_ID 0x02 /* 16 bits */
98	#define PCI_COMMAND 0x04 /* 16 bits */
99	#define PCI_COMMAND_IO 0x01 /* Enable response in I/O space */
100	#define PCI_COMMAND_MEMORY 0x02 /* Enable response in Memory space */
101	#define PCI_CLASS_DEVICE 0x0a /* Device class */
102	#define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
103	#define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
104	#define PCI_MIN_GNT 0x3e /* 8 bits */
105	#define PCI_MAX_LAT 0x3f /* 8 bits */
106
107
108	static VBOXSTRICTRC pci_data_write(PPDMDEVINS pDevIns, PDEVPCIROOT pGlobals, uint32_t addr, uint32_t u32Value, int cb)
109	{
110	LogFunc(("addr=%08x u32Value=%08x cb=%d\n", pGlobals->uConfigReg, u32Value, cb));
111
112	if (!(pGlobals->uConfigReg & (1 << 31)))
113	return VINF_SUCCESS;
114	if ((pGlobals->uConfigReg & 0x3) != 0)
115	return VINF_SUCCESS;
116
117	uint8_t const iBus = (pGlobals->uConfigReg >> 16) & 0xff;
118	uint8_t const iDevice = (pGlobals->uConfigReg >> 8) & 0xff;
119	#ifdef IN_RING3
120	uint32_t const config_addr = (pGlobals->uConfigReg & 0xfc) \| (addr & 3);
121	#endif
122	RT_UNTRUSTED_VALIDATED_FENCE(); /* paranoia */
123
124	VBOXSTRICTRC rcStrict = VINF_SUCCESS;
125	if (iBus != 0)
126	{
127	if (pGlobals->PciBus.cBridges)
128	{
129	#ifdef IN_RING3 /** @todo do lookup in R0/RC too! */
130	PPDMPCIDEV pBridgeDevice = pciR3FindBridge(&pGlobals->PciBus, iBus);
131	if (pBridgeDevice)
132	{
133	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigWrite);
134	rcStrict = pBridgeDevice->Int.s.pfnBridgeConfigWrite(pBridgeDevice->Int.s.CTX_SUFF(pDevIns), iBus,
135	iDevice, config_addr, cb, u32Value);
136	}
137	#else
138	RT_NOREF(pDevIns, addr, u32Value, cb);
139	rcStrict = VINF_IOM_R3_IOPORT_WRITE;
140	#endif
141	}
142	}
143	else
144	{
145	R3PTRTYPE(PDMPCIDEV *) pPciDev = pGlobals->PciBus.apDevices[iDevice];
146	if (pPciDev)
147	{
148	#ifdef IN_RING3
149	LogFunc(("%s: addr=%02x u32Value=%08x cb=%d\n", pPciDev->pszNameR3, config_addr, u32Value, cb));
150	rcStrict = VINF_PDM_PCI_DO_DEFAULT;
151	if (pPciDev->Int.s.pfnConfigWrite)
152	rcStrict = pPciDev->Int.s.pfnConfigWrite(pPciDev->Int.s.CTX_SUFF(pDevIns), pPciDev, config_addr, cb, u32Value);
153	if (rcStrict == VINF_PDM_PCI_DO_DEFAULT)
154	rcStrict = devpciR3CommonConfigWriteWorker(pDevIns, PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC),
155	pPciDev, config_addr, cb, u32Value);
156	#else
157	rcStrict = VINF_IOM_R3_IOPORT_WRITE;
158	#endif
159	}
160	}
161	return rcStrict;
162	}
163
164	static VBOXSTRICTRC pci_data_read(PDEVPCIROOT pGlobals, uint32_t addr, int cb, uint32_t *pu32Value)
165	{
166	*pu32Value = UINT32_MAX;
167
168	if (!(pGlobals->uConfigReg & (1 << 31)))
169	return VINF_SUCCESS;
170	if ((pGlobals->uConfigReg & 0x3) != 0)
171	return VINF_SUCCESS;
172	uint8_t const iBus = (pGlobals->uConfigReg >> 16) & 0xff;
173	uint8_t const iDevice = (pGlobals->uConfigReg >> 8) & 0xff;
174	#ifdef IN_RING3
175	uint32_t const config_addr = (pGlobals->uConfigReg & 0xfc) \| (addr & 3);
176	#endif
177	RT_UNTRUSTED_VALIDATED_FENCE();
178
179	VBOXSTRICTRC rcStrict = VINF_SUCCESS;
180	if (iBus != 0)
181	{
182	if (pGlobals->PciBus.cBridges)
183	{
184	#ifdef IN_RING3 /** @todo do lookup in R0/RC too! */
185	PPDMPCIDEV pBridgeDevice = pciR3FindBridge(&pGlobals->PciBus, iBus);
186	if (pBridgeDevice)
187	{
188	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigRead);
189	rcStrict = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->Int.s.CTX_SUFF(pDevIns),
190	iBus, iDevice, config_addr, cb, pu32Value);
191	}
192	#else
193	RT_NOREF(addr, cb);
194	rcStrict = VINF_IOM_R3_IOPORT_READ;
195	#endif
196	}
197	}
198	else
199	{
200	R3PTRTYPE(PDMPCIDEV *) pPciDev = pGlobals->PciBus.apDevices[iDevice];
201	if (pPciDev)
202	{
203	#ifdef IN_RING3
204	rcStrict = VINF_PDM_PCI_DO_DEFAULT;
205	if (pPciDev->Int.s.pfnConfigRead)
206	rcStrict = pPciDev->Int.s.pfnConfigRead(pPciDev->Int.s.CTX_SUFF(pDevIns), pPciDev, config_addr, cb, pu32Value);
207	if (rcStrict == VINF_PDM_PCI_DO_DEFAULT)
208	rcStrict = devpciR3CommonConfigReadWorker(pPciDev, config_addr, cb, pu32Value);
209	LogFunc(("%s: addr=%02x val=%08x cb=%d\n", pPciDev->pszNameR3, config_addr, *pu32Value, cb));
210	#else
211	NOREF(cb);
212	rcStrict = VINF_IOM_R3_IOPORT_READ;
213	#endif
214	}
215	}
216
217	return rcStrict;
218	}
219
220
221
222	/* return the global irq number corresponding to a given device irq
223	pin. We could also use the bus number to have a more precise
224	mapping.
225	This is the implementation note described in the PCI spec chapter 2.2.6 */
226	static inline int pci_slot_get_pirq(uint8_t uDevFn, int irq_num)
227	{
228	int slot_addend;
229	slot_addend = (uDevFn >> 3) - 1;
230	return (irq_num + slot_addend) & 3;
231	}
232
233	static inline int pci_slot_get_apic_pirq(uint8_t uDevFn, int irq_num)
234	{
235	return (irq_num + (uDevFn >> 3)) & 7;
236	}
237
238	static inline int get_pci_irq_apic_level(PDEVPCIROOT pGlobals, int irq_num)
239	{
240	return (pGlobals->auPciApicIrqLevels[irq_num] != 0);
241	}
242
243	static void apic_set_irq(PPDMDEVINS pDevIns, PDEVPCIBUS pBus, PDEVPCIBUSCC pBusCC,
244	uint8_t uDevFn, PDMPCIDEV *pPciDev, int irq_num1, int iLevel, int iAcpiIrq, uint32_t uTagSrc)
245	{
246	/* This is only allowed to be called with a pointer to the host bus. */
247	AssertMsg(pBus->iBus == 0, ("iBus=%u\n", pBus->iBus));
248
249	if (iAcpiIrq == -1) {
250	int apic_irq, apic_level;
251	PDEVPCIROOT pGlobals = DEVPCIBUS_2_DEVPCIROOT(pBus);
252	int irq_num = pci_slot_get_apic_pirq(uDevFn, irq_num1);
253
254	if ((iLevel & PDM_IRQ_LEVEL_HIGH) == PDM_IRQ_LEVEL_HIGH)
255	ASMAtomicIncU32(&pGlobals->auPciApicIrqLevels[irq_num]);
256	else if ((iLevel & PDM_IRQ_LEVEL_HIGH) == PDM_IRQ_LEVEL_LOW)
257	ASMAtomicDecU32(&pGlobals->auPciApicIrqLevels[irq_num]);
258
259	apic_irq = irq_num + 0x10;
260	apic_level = get_pci_irq_apic_level(pGlobals, irq_num);
261	Log3Func(("%s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d\n",
262	R3STRING(pPciDev->pszNameR3), irq_num1, iLevel, apic_irq, apic_level, irq_num));
263	pBusCC->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pDevIns, apic_irq, apic_level, uTagSrc);
264
265	if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP) {
266	ASMAtomicDecU32(&pGlobals->auPciApicIrqLevels[irq_num]);
267	pPciDev->Int.s.uIrqPinState = PDM_IRQ_LEVEL_LOW;
268	apic_level = get_pci_irq_apic_level(pGlobals, irq_num);
269	Log3Func(("%s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d (flop)\n",
270	R3STRING(pPciDev->pszNameR3), irq_num1, iLevel, apic_irq, apic_level, irq_num));
271	pBusCC->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pDevIns, apic_irq, apic_level, uTagSrc);
272	}
273	} else {
274	Log3Func(("%s: irq_num1=%d level=%d iAcpiIrq=%d\n",
275	R3STRING(pPciDev->pszNameR3), irq_num1, iLevel, iAcpiIrq));
276	pBusCC->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pDevIns, iAcpiIrq, iLevel, uTagSrc);
277	}
278	}
279
280	DECLINLINE(int) get_pci_irq_level(PDEVPCIROOT pGlobals, int irq_num)
281	{
282	return (pGlobals->Piix3.auPciLegacyIrqLevels[irq_num] != 0);
283	}
284
285	/**
286	* Set the IRQ for a PCI device on the host bus - shared by host bus and bridge.
287	*
288	* @param pDevIns The PDM device instance for the PCI bus.
289	* @param pGlobals Device instance of the host PCI bus.
290	* @param pBusCC Context specific data for the PCI bus.
291	* @param uDevFn The device number on the host bus which will raise the IRQ
292	* @param pPciDev The PCI device structure which raised the interrupt.
293	* @param iIrq IRQ number to set.
294	* @param iLevel IRQ level.
295	* @param uTagSrc The IRQ tag and source ID (for tracing).
296	* @remark uDevFn and pPciDev->uDevFn are not the same if the device is behind
297	* a bridge. In that case uDevFn will be the slot of the bridge which
298	* is needed to calculate the PIRQ value.
299	*/
300	static void pciSetIrqInternal(PPDMDEVINS pDevIns, PDEVPCIROOT pGlobals, PDEVPCIBUSCC pBusCC,
301	uint8_t uDevFn, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc)
302	{
303	PDEVPCIBUS pBus = &pGlobals->PciBus;
304	uint8_t *pbCfg = pDevIns->apPciDevs[1]->abConfig;
305	const bool fIsAcpiDevice = pPciDev->abConfig[2] == 0x13 && pPciDev->abConfig[3] == 0x71;
306	/* If the two configuration space bytes at 0xde, 0xad are set to 0xbe, 0xef, a back door
307	* is opened to route PCI interrupts directly to the I/O APIC and bypass the PIC.
308	* See the \_SB_.PCI0._PRT method in vbox.dsl.
309	*/
310	const bool fIsApicEnabled = pGlobals->fUseIoApic && pbCfg[0xde] == 0xbe && pbCfg[0xad] == 0xef;
311	int pic_irq, pic_level;
312
313	/* Check if the state changed. */
314	if (pPciDev->Int.s.uIrqPinState != iLevel)
315	{
316	pPciDev->Int.s.uIrqPinState = (iLevel & PDM_IRQ_LEVEL_HIGH);
317
318	/* Send interrupt to I/O APIC only. */
319	if (fIsApicEnabled)
320	{
321	if (fIsAcpiDevice)
322	/*
323	* ACPI needs special treatment since SCI is hardwired and
324	* should not be affected by PCI IRQ routing tables at the
325	* same time SCI IRQ is shared in PCI sense hence this
326	* kludge (i.e. we fetch the hardwired value from ACPIs
327	* PCI device configuration space).
328	*/
329	apic_set_irq(pDevIns, pBus, pBusCC, uDevFn, pPciDev, -1, iLevel, pPciDev->abConfig[PCI_INTERRUPT_LINE], uTagSrc);
330	else
331	apic_set_irq(pDevIns, pBus, pBusCC, uDevFn, pPciDev, iIrq, iLevel, -1, uTagSrc);
332	return;
333	}
334
335	if (fIsAcpiDevice)
336	{
337	/* As per above treat ACPI in a special way */
338	pic_irq = pPciDev->abConfig[PCI_INTERRUPT_LINE];
339	pGlobals->Piix3.iAcpiIrq = pic_irq;
340	pGlobals->Piix3.iAcpiIrqLevel = iLevel & PDM_IRQ_LEVEL_HIGH;
341	}
342	else
343	{
344	int irq_num;
345	irq_num = pci_slot_get_pirq(uDevFn, iIrq);
346
347	if (pPciDev->Int.s.uIrqPinState == PDM_IRQ_LEVEL_HIGH)
348	ASMAtomicIncU32(&pGlobals->Piix3.auPciLegacyIrqLevels[irq_num]);
349	else if (pPciDev->Int.s.uIrqPinState == PDM_IRQ_LEVEL_LOW)
350	ASMAtomicDecU32(&pGlobals->Piix3.auPciLegacyIrqLevels[irq_num]);
351
352	/* now we change the pic irq level according to the piix irq mappings */
353	pic_irq = pbCfg[0x60 + irq_num];
354	if (pic_irq >= 16)
355	{
356	if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP)
357	{
358	ASMAtomicDecU32(&pGlobals->Piix3.auPciLegacyIrqLevels[irq_num]);
359	pPciDev->Int.s.uIrqPinState = PDM_IRQ_LEVEL_LOW;
360	}
361
362	return;
363	}
364	}
365
366	/* the pic level is the logical OR of all the PCI irqs mapped to it */
367	pic_level = 0;
368	if (pic_irq == pbCfg[0x60])
369	pic_level \|= get_pci_irq_level(pGlobals, 0); /* PIRQA */
370	if (pic_irq == pbCfg[0x61])
371	pic_level \|= get_pci_irq_level(pGlobals, 1); /* PIRQB */
372	if (pic_irq == pbCfg[0x62])
373	pic_level \|= get_pci_irq_level(pGlobals, 2); /* PIRQC */
374	if (pic_irq == pbCfg[0x63])
375	pic_level \|= get_pci_irq_level(pGlobals, 3); /* PIRQD */
376	if (pic_irq == pGlobals->Piix3.iAcpiIrq)
377	pic_level \|= pGlobals->Piix3.iAcpiIrqLevel;
378
379	Log3Func(("%s: iLevel=%d iIrq=%d pic_irq=%d pic_level=%d uTagSrc=%#x\n",
380	R3STRING(pPciDev->pszNameR3), iLevel, iIrq, pic_irq, pic_level, uTagSrc));
381	pBusCC->CTX_SUFF(pPciHlp)->pfnIsaSetIrq(pDevIns, pic_irq, pic_level, uTagSrc);
382
383	/** @todo optimize pci irq flip-flop some rainy day. */
384	if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP)
385	pciSetIrqInternal(pDevIns, pGlobals, pBusCC, uDevFn, pPciDev, iIrq, PDM_IRQ_LEVEL_LOW, uTagSrc);
386	}
387	}
388
389
390	/**
391	* @interface_method_impl{PDMPCIBUSREGR3,pfnSetIrqR3}
392	*/
393	static DECLCALLBACK(void) pciSetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc)
394	{
395	PDEVPCIROOT pBus = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
396	PDEVPCIBUSCC pBusCC = PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC);
397	LogFlow(("pciSetIrq: %p %u %u %#x\n", pPciDev, iIrq, iLevel, uTagSrc));
398	pciSetIrqInternal(pDevIns, pBus, pBusCC, pPciDev->uDevFn, pPciDev, iIrq, iLevel, uTagSrc);
399	}
400
401	#ifdef IN_RING3
402
403	/**
404	* Finds a bridge on the bus which contains the destination bus.
405	*
406	* @return Pointer to the device instance data of the bus or
407	* NULL if no bridge was found.
408	* @param pBus Pointer to the bus to search on.
409	* @param iBus Destination bus number.
410	*/
411	DECLINLINE(PPDMPCIDEV) pciR3FindBridge(PDEVPCIBUS pBus, uint8_t iBus)
412	{
413	/* Search for a fitting bridge. */
414	for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
415	{
416	/*
417	* Examine secondary and subordinate bus number.
418	* If the target bus is in the range we pass the request on to the bridge.
419	*/
420	PPDMPCIDEV pBridgeTemp = pBus->papBridgesR3[iBridge];
421	AssertMsg(pBridgeTemp && pciDevIsPci2PciBridge(pBridgeTemp),
422	("Device is not a PCI bridge but on the list of PCI bridges\n"));
423
424	if ( iBus >= pBridgeTemp->abConfig[VBOX_PCI_SECONDARY_BUS]
425	&& iBus <= pBridgeTemp->abConfig[VBOX_PCI_SUBORDINATE_BUS])
426	return pBridgeTemp;
427	}
428
429	/* Nothing found. */
430	return NULL;
431	}
432
433	static void pciR3Piix3Reset(PPDMPCIDEV pPiix3PciDev)
434	{
435	uint8_t *pci_conf = pPiix3PciDev->abConfig;
436
437	pci_conf[0x04] = 0x07; /* master, memory and I/O */
438	pci_conf[0x05] = 0x00;
439	pci_conf[0x06] = 0x00;
440	pci_conf[0x07] = 0x02; /* PCI_status_devsel_medium */
441	pci_conf[0x4c] = 0x4d;
442	pci_conf[0x4e] = 0x03;
443	pci_conf[0x4f] = 0x00;
444	pci_conf[0x60] = 0x80;
445	pci_conf[0x69] = 0x02;
446	pci_conf[0x70] = 0x80;
447	pci_conf[0x76] = 0x0c;
448	pci_conf[0x77] = 0x0c;
449	pci_conf[0x78] = 0x02;
450	pci_conf[0x79] = 0x00;
451	pci_conf[0x80] = 0x00;
452	pci_conf[0x82] = 0x02; /* Get rid of the Linux guest "Enabling Passive Release" PCI quirk warning. */
453	pci_conf[0xa0] = 0x08;
454	pci_conf[0xa2] = 0x00;
455	pci_conf[0xa3] = 0x00;
456	pci_conf[0xa4] = 0x00;
457	pci_conf[0xa5] = 0x00;
458	pci_conf[0xa6] = 0x00;
459	pci_conf[0xa7] = 0x00;
460	pci_conf[0xa8] = 0x0f;
461	pci_conf[0xaa] = 0x00;
462	pci_conf[0xab] = 0x00;
463	pci_conf[0xac] = 0x00;
464	pci_conf[0xae] = 0x00;
465	}
466
467	/* host irqs corresponding to PCI irqs A-D */
468	static const uint8_t pci_irqs[4] = { 11, 10, 9, 11 }; /* bird: added const */
469
470	static void pci_bios_init_device(PPDMDEVINS pDevIns, PDEVPCIROOT pGlobals, PDEVPCIBUS pBus,
471	PPDMPCIDEV pPciDev, uint8_t cBridgeDepth, uint8_t *paBridgePositions)
472	{
473	uint32_t *paddr;
474	int pin, pic_irq;
475	uint16_t devclass, vendor_id, device_id;
476
477	devclass = devpciR3GetWord(pPciDev, PCI_CLASS_DEVICE);
478	vendor_id = devpciR3GetWord(pPciDev, PCI_VENDOR_ID);
479	device_id = devpciR3GetWord(pPciDev, PCI_DEVICE_ID);
480
481	/* Check if device is present. */
482	if (vendor_id != 0xffff)
483	{
484	switch(devclass)
485	{
486	case 0x0101:
487	if ( (vendor_id == 0x8086)
488	&& (device_id == 0x7010 \|\| device_id == 0x7111 \|\| device_id == 0x269e))
489	{
490	/* PIIX3, PIIX4 or ICH6 IDE */
491	devpciR3SetWord(pDevIns, pPciDev, 0x40, 0x8011); /* enable IDE0 + fast timing */
492	devpciR3SetWord(pDevIns, pPciDev, 0x42, 0x8011); /* enable IDE1 + fast timing */
493	goto default_map;
494	}
495	else
496	{
497	/* IDE: we map it as in ISA mode */
498	devpciR3BiosInitSetRegionAddress(pDevIns, pBus, pPciDev, 0, 0x1f0);
499	devpciR3BiosInitSetRegionAddress(pDevIns, pBus, pPciDev, 1, 0x3f4);
500	devpciR3BiosInitSetRegionAddress(pDevIns, pBus, pPciDev, 2, 0x170);
501	devpciR3BiosInitSetRegionAddress(pDevIns, pBus, pPciDev, 3, 0x374);
502	devpciR3SetWord(pDevIns, pPciDev, PCI_COMMAND,
503	devpciR3GetWord(pPciDev, PCI_COMMAND)
504	\| PCI_COMMAND_IOACCESS);
505	}
506	break;
507	case 0x0300:
508	{
509	if (vendor_id != 0x80ee)
510	goto default_map;
511	/* VGA: map frame buffer to default Bochs VBE address */
512	devpciR3BiosInitSetRegionAddress(pDevIns, pBus, pPciDev, 0, 0xe0000000);
513	/*
514	* Legacy VGA I/O ports are implicitly decoded by a VGA class device. But
515	* only the framebuffer (i.e., a memory region) is explicitly registered via
516	* devpciR3BiosInitSetRegionAddress, so don't forget to enable I/O decoding.
517	*/
518	devpciR3SetWord(pDevIns, pPciDev, PCI_COMMAND,
519	devpciR3GetWord(pPciDev, PCI_COMMAND)
520	\| PCI_COMMAND_IOACCESS \| PCI_COMMAND_MEMACCESS);
521	break;
522	}
523	case 0x0800:
524	/* PIC */
525	vendor_id = devpciR3GetWord(pPciDev, PCI_VENDOR_ID);
526	device_id = devpciR3GetWord(pPciDev, PCI_DEVICE_ID);
527	if (vendor_id == 0x1014)
528	{
529	/* IBM */
530	if (device_id == 0x0046 \|\| device_id == 0xFFFF)
531	{
532	/* MPIC & MPIC2 */
533	devpciR3BiosInitSetRegionAddress(pDevIns, pBus, pPciDev, 0, 0x80800000 + 0x00040000);
534	devpciR3SetWord(pDevIns, pPciDev, PCI_COMMAND,
535	devpciR3GetWord(pPciDev, PCI_COMMAND)
536	\| PCI_COMMAND_MEMACCESS);
537	}
538	}
539	break;
540	case 0xff00:
541	if ( (vendor_id == 0x0106b)
542	&& (device_id == 0x0017 \|\| device_id == 0x0022))
543	{
544	/* macio bridge */
545	devpciR3BiosInitSetRegionAddress(pDevIns, pBus, pPciDev, 0, 0x80800000);
546	devpciR3SetWord(pDevIns, pPciDev, PCI_COMMAND,
547	devpciR3GetWord(pPciDev, PCI_COMMAND)
548	\| PCI_COMMAND_MEMACCESS);
549	}
550	break;
551	case 0x0604:
552	{
553	/* Init PCI-to-PCI bridge. */
554	devpciR3SetByte(pDevIns, pPciDev, VBOX_PCI_PRIMARY_BUS, pBus->iBus);
555
556	AssertMsg(pGlobals->uPciBiosBus < 255, ("Too many bridges on the bus\n"));
557	pGlobals->uPciBiosBus++;
558	devpciR3SetByte(pDevIns, pPciDev, VBOX_PCI_SECONDARY_BUS, pGlobals->uPciBiosBus);
559	devpciR3SetByte(pDevIns, pPciDev, VBOX_PCI_SUBORDINATE_BUS, 0xff); /* Temporary until we know how many other bridges are behind this one. */
560
561	/* Add position of this bridge into the array. */
562	paBridgePositions[cBridgeDepth+1] = (pPciDev->uDevFn >> 3);
563
564	/*
565	* The I/O range for the bridge must be aligned to a 4KB boundary.
566	* This does not change anything really as the access to the device is not going
567	* through the bridge but we want to be compliant to the spec.
568	*/
569	if ((pGlobals->uPciBiosIo % _4K) != 0)
570	pGlobals->uPciBiosIo = RT_ALIGN_32(pGlobals->uPciBiosIo, _4K);
571	LogFunc(("Aligned I/O start address. New address %#x\n", pGlobals->uPciBiosIo));
572	devpciR3SetByte(pDevIns, pPciDev, VBOX_PCI_IO_BASE, (pGlobals->uPciBiosIo >> 8) & 0xf0);
573
574	/* The MMIO range for the bridge must be aligned to a 1MB boundary. */
575	if ((pGlobals->uPciBiosMmio % _1M) != 0)
576	pGlobals->uPciBiosMmio = RT_ALIGN_32(pGlobals->uPciBiosMmio, _1M);
577	LogFunc(("Aligned MMIO start address. New address %#x\n", pGlobals->uPciBiosMmio));
578	devpciR3SetWord(pDevIns, pPciDev, VBOX_PCI_MEMORY_BASE, (pGlobals->uPciBiosMmio >> 16) & UINT32_C(0xffff0));
579
580	/* Save values to compare later to. */
581	uint32_t u32IoAddressBase = pGlobals->uPciBiosIo;
582	uint32_t u32MMIOAddressBase = pGlobals->uPciBiosMmio;
583
584	/* Init devices behind the bridge and possibly other bridges as well. */
585	PDEVPCIBUS pChildBus = PDMINS_2_DATA(pPciDev->Int.s.CTX_SUFF(pDevIns), PDEVPCIBUS);
586	for (uint32_t uDevFn = 0; uDevFn < RT_ELEMENTS(pChildBus->apDevices); uDevFn++)
587	{
588	PPDMPCIDEV pChildPciDev = pChildBus->apDevices[uDevFn];
589	if (pChildPciDev)
590	pci_bios_init_device(pDevIns, pGlobals, pChildBus, pChildPciDev, cBridgeDepth + 1, paBridgePositions);
591	}
592
593	/* The number of bridges behind the this one is now available. */
594	devpciR3SetByte(pDevIns, pPciDev, VBOX_PCI_SUBORDINATE_BUS, pGlobals->uPciBiosBus);
595
596	/*
597	* Set I/O limit register. If there is no device with I/O space behind the bridge
598	* we set a lower value than in the base register.
599	* The result with a real bridge is that no I/O transactions are passed to the secondary
600	* interface. Again this doesn't really matter here but we want to be compliant to the spec.
601	*/
602	if ((u32IoAddressBase != pGlobals->uPciBiosIo) && ((pGlobals->uPciBiosIo % _4K) != 0))
603	{
604	/* The upper boundary must be one byte less than a 4KB boundary. */
605	pGlobals->uPciBiosIo = RT_ALIGN_32(pGlobals->uPciBiosIo, _4K);
606	}
607	devpciR3SetByte(pDevIns, pPciDev, VBOX_PCI_IO_LIMIT, ((pGlobals->uPciBiosIo >> 8) & 0xf0) - 1);
608
609	/* Same with the MMIO limit register but with 1MB boundary here. */
610	if ((u32MMIOAddressBase != pGlobals->uPciBiosMmio) && ((pGlobals->uPciBiosMmio % _1M) != 0))
611	{
612	/* The upper boundary must be one byte less than a 1MB boundary. */
613	pGlobals->uPciBiosMmio = RT_ALIGN_32(pGlobals->uPciBiosMmio, _1M);
614	}
615	devpciR3SetWord(pDevIns, pPciDev, VBOX_PCI_MEMORY_LIMIT, ((pGlobals->uPciBiosMmio >> 16) & UINT32_C(0xfff0)) - 1);
616
617	/*
618	* Set the prefetch base and limit registers. We currently have no device with a prefetchable region
619	* which may be behind a bridge. That's why it is unconditionally disabled here atm by writing a higher value into
620	* the base register than in the limit register.
621	*/
622	devpciR3SetWord(pDevIns, pPciDev, VBOX_PCI_PREF_MEMORY_BASE, 0xfff0);
623	devpciR3SetWord(pDevIns, pPciDev, VBOX_PCI_PREF_MEMORY_LIMIT, 0x0);
624	devpciR3SetDWord(pDevIns, pPciDev, VBOX_PCI_PREF_BASE_UPPER32, 0x00);
625	devpciR3SetDWord(pDevIns, pPciDev, VBOX_PCI_PREF_LIMIT_UPPER32, 0x00);
626	break;
627	}
628	default:
629	default_map:
630	{
631	/* default memory mappings */
632	bool fActiveMemRegion = false;
633	bool fActiveIORegion = false;
634	/*
635	* PCI_NUM_REGIONS is 7 because of the rom region but there are only 6 base address register defined by the PCI spec.
636	* Leaving only PCI_NUM_REGIONS would cause reading another and enabling a memory region which does not exist.
637	*/
638	for (unsigned i = 0; i < (PCI_NUM_REGIONS-1); i++)
639	{
640	uint32_t u32Size;
641	uint8_t u8RessourceType;
642	uint32_t u32Address = 0x10 + i * 4;
643
644	/* Calculate size. */
645	u8RessourceType = devpciR3GetByte(pPciDev, u32Address);
646	devpciR3SetDWord(pDevIns, pPciDev, u32Address, UINT32_C(0xffffffff));
647	u32Size = devpciR3GetDWord(pPciDev, u32Address);
648	bool fIsPio = ((u8RessourceType & PCI_COMMAND_IOACCESS) == PCI_COMMAND_IOACCESS);
649	/* Clear resource information depending on resource type. */
650	if (fIsPio) /* I/O */
651	u32Size &= ~(0x01);
652	else /* MMIO */
653	u32Size &= ~(0x0f);
654
655	/*
656	* Invert all bits and add 1 to get size of the region.
657	* (From PCI implementation note)
658	*/
659	if (fIsPio && (u32Size & UINT32_C(0xffff0000)) == 0)
660	u32Size = (~(u32Size \| UINT32_C(0xffff0000))) + 1;
661	else
662	u32Size = (~u32Size) + 1;
663
664	Log2Func(("Size of region %u for device %d on bus %d is %u\n", i, pPciDev->uDevFn, pBus->iBus, u32Size));
665
666	if (u32Size)
667	{
668	if (fIsPio)
669	paddr = &pGlobals->uPciBiosIo;
670	else
671	paddr = &pGlobals->uPciBiosMmio;
672	uint32_t uNew = *paddr;
673	uNew = (uNew + u32Size - 1) & ~(u32Size - 1);
674	if (fIsPio)
675	uNew &= UINT32_C(0xffff);
676	/* Unconditionally exclude I/O-APIC/HPET/ROM. Pessimistic, but better than causing a mess. */
677	if (!uNew \|\| (uNew <= UINT32_C(0xffffffff) && uNew + u32Size - 1 >= UINT32_C(0xfec00000)))
678	{
679	LogRel(("PCI: no space left for BAR%u of device %u/%u/%u (vendor=%#06x device=%#06x)\n",
680	i, pBus->iBus, pPciDev->uDevFn >> 3, pPciDev->uDevFn & 7, vendor_id, device_id)); /** @todo make this a VM start failure later. */
681	/* Undo the mapping mess caused by the size probing. */
682	devpciR3SetDWord(pDevIns, pPciDev, u32Address, UINT32_C(0));
683	}
684	else
685	{
686	LogFunc(("Start address of %s region %u is %#x\n", (fIsPio ? "I/O" : "MMIO"), i, uNew));
687	devpciR3BiosInitSetRegionAddress(pDevIns, pBus, pPciDev, i, uNew);
688	if (fIsPio)
689	fActiveIORegion = true;
690	else
691	fActiveMemRegion = true;
692	*paddr = uNew + u32Size;
693	Log2Func(("New address is %#x\n", *paddr));
694	}
695	}
696	}
697
698	/* Update the command word appropriately. */
699	devpciR3SetWord(pDevIns, pPciDev, PCI_COMMAND,
700	devpciR3GetWord(pPciDev, PCI_COMMAND)
701	\| (fActiveMemRegion ? PCI_COMMAND_MEMACCESS : 0)
702	\| (fActiveIORegion ? PCI_COMMAND_IOACCESS : 0));
703
704	break;
705	}
706	}
707
708	/* map the interrupt */
709	pin = devpciR3GetByte(pPciDev, PCI_INTERRUPT_PIN);
710	if (pin != 0)
711	{
712	uint8_t uBridgeDevFn = pPciDev->uDevFn;
713	pin--;
714
715	/* We need to go up to the host bus to see which irq this device will assert there. */
716	while (cBridgeDepth != 0)
717	{
718	/* Get the pin the device would assert on the bridge. */
719	pin = ((uBridgeDevFn >> 3) + pin) & 3;
720	uBridgeDevFn = paBridgePositions[cBridgeDepth];
721	cBridgeDepth--;
722	}
723
724	pin = pci_slot_get_pirq(pPciDev->uDevFn, pin);
725	pic_irq = pci_irqs[pin];
726	devpciR3SetByte(pDevIns, pPciDev, PCI_INTERRUPT_LINE, pic_irq);
727	}
728	}
729	}
730
731	/**
732	* Worker for Fake PCI BIOS config, triggered by magic port access by BIOS.
733	*
734	* @returns VBox status code.
735	*
736	* @param pDevIns i440FX device instance.
737	*/
738	static int pciR3FakePCIBIOS(PPDMDEVINS pDevIns)
739	{
740	uint8_t elcr[2] = {0, 0};
741	PDEVPCIROOT pGlobals = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
742	PVM pVM = PDMDevHlpGetVM(pDevIns); Assert(pVM);
743	PVMCPU pVCpu = PDMDevHlpGetVMCPU(pDevIns); Assert(pVM);
744	uint32_t const cbBelow4GB = MMR3PhysGetRamSizeBelow4GB(pVM);
745	uint64_t const cbAbove4GB = MMR3PhysGetRamSizeAbove4GB(pVM);
746	RT_NOREF(cbBelow4GB, cbAbove4GB);
747
748	LogRel(("PCI: Setting up resources and interrupts\n"));
749
750	/*
751	* Set the start addresses.
752	*/
753	pGlobals->uPciBiosBus = 0;
754	pGlobals->uPciBiosIo = 0xd000;
755	pGlobals->uPciBiosMmio = UINT32_C(0xf0000000);
756
757	/*
758	* Activate IRQ mappings.
759	*/
760	PPDMPCIDEV pPIIX3 = pDevIns->apPciDevs[1];
761	for (unsigned i = 0; i < 4; i++)
762	{
763	uint8_t irq = pci_irqs[i];
764	/* Set to trigger level. */
765	elcr[irq >> 3] \|= (1 << (irq & 7));
766	/* Activate irq remapping in PIIX3. */
767	devpciR3SetByte(pDevIns, pPIIX3, 0x60 + i, irq);
768	}
769
770	/* Tell to the PIC. */
771	VBOXSTRICTRC rcStrict = IOMIOPortWrite(pVM, pVCpu, 0x4d0, elcr[0], sizeof(uint8_t));
772	if (rcStrict == VINF_SUCCESS)
773	rcStrict = IOMIOPortWrite(pVM, pVCpu, 0x4d1, elcr[1], sizeof(uint8_t));
774	if (rcStrict != VINF_SUCCESS)
775	{
776	AssertMsgFailed(("Writing to PIC failed! rcStrict=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
777	return RT_SUCCESS(rcStrict) ? VERR_INTERNAL_ERROR : VBOXSTRICTRC_VAL(rcStrict);
778	}
779
780	/*
781	* Init the devices.
782	*/
783	PDEVPCIBUS pBus = &pGlobals->PciBus;
784	for (uint32_t uDevFn = 0; uDevFn < RT_ELEMENTS(pBus->apDevices); uDevFn++)
785	{
786	PPDMPCIDEV pPciDev = pBus->apDevices[uDevFn];
787	if (pPciDev)
788	{
789	Log2(("PCI: Initializing device %d (%#x)\n", uDevFn, 0x80000000 \| (uDevFn << 8)));
790	uint8_t aBridgePositions[256];
791	RT_ZERO(aBridgePositions);
792	pci_bios_init_device(pDevIns, pGlobals, pBus, pPciDev, 0, aBridgePositions);
793	}
794	}
795
796	return VINF_SUCCESS;
797	}
798
799	#endif /* IN_RING3 */
800
801
802	/* -=-=-=-=-=- I/O ports -=-=-=-=-=- */
803
804	/**
805	* @callback_method_impl{FNIOMIOPORTNEWOUT, PCI address}
806	*/
807	static DECLCALLBACK(VBOXSTRICTRC)
808	pciIOPortAddressWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
809	{
810	LogFunc(("offPort=%#x u32=%#x cb=%d\n", offPort, u32, cb));
811	Assert(offPort == 0); RT_NOREF2(offPort, pvUser);
812	if (cb == 4)
813	{
814	PDEVPCIROOT pThis = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
815	PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_WRITE);
816	pThis->uConfigReg = u32 & ~3; /* Bits 0-1 are reserved and we silently clear them */
817	PCI_UNLOCK(pDevIns);
818	}
819	/* else: 440FX does "pass through to the bus" for other writes, what ever that means.
820	* Linux probes for cmd640 using byte writes/reads during ide init. We'll just ignore it. */
821	return VINF_SUCCESS;
822	}
823
824
825	/**
826	* @callback_method_impl{FNIOMIOPORTNEWIN, PCI address}
827	*/
828	static DECLCALLBACK(VBOXSTRICTRC)
829	pciIOPortAddressRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT offPort, uint32_t pu32, unsigned cb)
830	{
831	Assert(offPort == 0); RT_NOREF2(offPort, pvUser);
832	if (cb == 4)
833	{
834	PDEVPCIROOT pThis = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
835	PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_READ);
836	*pu32 = pThis->uConfigReg;
837	PCI_UNLOCK(pDevIns);
838	LogFunc(("offPort=%#x cb=%d -> %#x\n", offPort, cb, *pu32));
839	return VINF_SUCCESS;
840	}
841	/* else: 440FX does "pass through to the bus" for other writes, what ever that means.
842	* Linux probes for cmd640 using byte writes/reads during ide init. We'll just ignore it. */
843	LogFunc(("offPort=%#x cb=%d VERR_IOM_IOPORT_UNUSED\n", offPort, cb));
844	return VERR_IOM_IOPORT_UNUSED;
845	}
846
847
848	/**
849	* @callback_method_impl{FNIOMIOPORTNEWOUT, PCI data}
850	*/
851	static DECLCALLBACK(VBOXSTRICTRC)
852	pciIOPortDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
853	{
854	LogFunc(("offPort=%#x u32=%#x cb=%d\n", offPort, u32, cb));
855	Assert(offPort < 4); NOREF(pvUser);
856	VBOXSTRICTRC rcStrict = VINF_SUCCESS;
857	if (!(offPort % cb))
858	{
859	PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_WRITE);
860	rcStrict = pci_data_write(pDevIns, PDMINS_2_DATA(pDevIns, PDEVPCIROOT), offPort, u32, cb);
861	PCI_UNLOCK(pDevIns);
862	}
863	else
864	AssertMsgFailed(("Write to port %#x u32=%#x cb=%d\n", offPort, u32, cb));
865	return rcStrict;
866	}
867
868
869	/**
870	* @callback_method_impl{FNIOMIOPORTNEWIN, PCI data}
871	*/
872	static DECLCALLBACK(VBOXSTRICTRC)
873	pciIOPortDataRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT offPort, uint32_t pu32, unsigned cb)
874	{
875	Assert(offPort < 4); NOREF(pvUser);
876	if (!(offPort % cb))
877	{
878	PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_READ);
879	VBOXSTRICTRC rcStrict = pci_data_read(PDMINS_2_DATA(pDevIns, PDEVPCIROOT), offPort, cb, pu32);
880	PCI_UNLOCK(pDevIns);
881	LogFunc(("offPort=%#x cb=%#x -> %#x (%Rrc)\n", offPort, cb, *pu32, VBOXSTRICTRC_VAL(rcStrict)));
882	return rcStrict;
883	}
884	AssertMsgFailed(("Read from port %#x cb=%d\n", offPort, cb));
885	return VERR_IOM_IOPORT_UNUSED;
886	}
887
888	#ifdef IN_RING3
889
890	/**
891	* @callback_method_impl{FNIOMIOPORTNEWOUT, PCI data}
892	*/
893	static DECLCALLBACK(VBOXSTRICTRC)
894	pciR3IOPortMagicPCIWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
895	{
896	Assert(offPort == 0); RT_NOREF2(pvUser, offPort);
897	LogFunc(("offPort=%#x u32=%#x cb=%d\n", offPort, u32, cb));
898	if (cb == 4)
899	{
900	if (u32 == UINT32_C(19200509)) // Richard Adams - Note! In decimal rather hex.
901	{
902	int rc = pciR3FakePCIBIOS(pDevIns);
903	AssertRC(rc);
904	}
905	}
906
907	return VINF_SUCCESS;
908	}
909
910	/**
911	* @callback_method_impl{FNIOMIOPORTNEWIN, PCI data}
912	*/
913	static DECLCALLBACK(VBOXSTRICTRC)
914	pciR3IOPortMagicPCIRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT offPort, uint32_t pu32, unsigned cb)
915	{
916	Assert(offPort == 0); RT_NOREF5(pDevIns, pvUser, offPort, pu32, cb);
917	LogFunc(("offPort=%#x cb=%d VERR_IOM_IOPORT_UNUSED\n", offPort, cb));
918	return VERR_IOM_IOPORT_UNUSED;
919	}
920
921
922	/* -=-=-=-=-=- Saved state -=-=-=-=-=- */
923
924	/**
925	* Common worker for pciR3SaveExec and pcibridgeR3SaveExec.
926	*
927	* @returns VBox status code.
928	* @param pHlp The device helpers.
929	* @param pBus The bus to save.
930	* @param pSSM The saved state handle.
931	*/
932	static int pciR3CommonSaveExec(PCPDMDEVHLPR3 pHlp, PDEVPCIBUS pBus, PSSMHANDLE pSSM)
933	{
934	/*
935	* Iterate thru all the devices.
936	*/
937	for (uint32_t uDevFn = 0; uDevFn < RT_ELEMENTS(pBus->apDevices); uDevFn++)
938	{
939	PPDMPCIDEV pDev = pBus->apDevices[uDevFn];
940	if (pDev)
941	{
942	pHlp->pfnSSMPutU32(pSSM, uDevFn);
943	pHlp->pfnSSMPutMem(pSSM, pDev->abConfig, 256); /* Only save 256 bytes here! */
944
945	pHlp->pfnSSMPutS32(pSSM, pDev->Int.s.uIrqPinState);
946
947	/* Save the type an size of all the regions. */
948	for (uint32_t iRegion = 0; iRegion < VBOX_PCI_NUM_REGIONS; iRegion++)
949	{
950	pHlp->pfnSSMPutU8(pSSM, pDev->Int.s.aIORegions[iRegion].type);
951	pHlp->pfnSSMPutU64(pSSM, pDev->Int.s.aIORegions[iRegion].size);
952	}
953	}
954	}
955	return pHlp->pfnSSMPutU32(pSSM, UINT32_MAX); /* terminator */
956	}
957
958
959	/**
960	* @callback_method_impl{FNSSMDEVSAVEEXEC}
961	*/
962	static DECLCALLBACK(int) pciR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
963	{
964	PDEVPCIROOT pThis = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
965	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
966
967	/*
968	* Bus state data.
969	*/
970	pHlp->pfnSSMPutU32(pSSM, pThis->uConfigReg);
971	pHlp->pfnSSMPutBool(pSSM, pThis->fUseIoApic);
972
973	/*
974	* Save IRQ states.
975	*/
976	for (unsigned i = 0; i < RT_ELEMENTS(pThis->Piix3.auPciLegacyIrqLevels); i++)
977	pHlp->pfnSSMPutU32(pSSM, pThis->Piix3.auPciLegacyIrqLevels[i]);
978	for (unsigned i = 0; i < RT_ELEMENTS(pThis->auPciApicIrqLevels); i++)
979	pHlp->pfnSSMPutU32(pSSM, pThis->auPciApicIrqLevels[i]);
980
981	pHlp->pfnSSMPutU32(pSSM, pThis->Piix3.iAcpiIrqLevel);
982	pHlp->pfnSSMPutS32(pSSM, pThis->Piix3.iAcpiIrq);
983
984	pHlp->pfnSSMPutU32(pSSM, UINT32_MAX); /* separator */
985
986	/*
987	* Join paths with pcibridgeR3SaveExec.
988	*/
989	return pciR3CommonSaveExec(pHlp, &pThis->PciBus, pSSM);
990	}
991
992
993	/**
994	* Common worker for pciR3LoadExec and pcibridgeR3LoadExec.
995	*
996	* @returns VBox status code.
997	* @param pDevIns The device instance.
998	* @param pBus The bus which data is being loaded.
999	* @param pSSM The saved state handle.
1000	* @param uVersion The data version.
1001	* @param uPass The pass.
1002	*/
1003	static int pciR3CommonLoadExec(PPDMDEVINS pDevIns, PDEVPCIBUS pBus, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1004	{
1005	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
1006	uint32_t u32;
1007	int rc;
1008
1009	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
1010
1011	/*
1012	* Iterate thru all the devices and write 0 to the COMMAND register so
1013	* that all the memory is unmapped before we start restoring the saved
1014	* mapping locations.
1015	*
1016	* The register value is restored afterwards so we can do proper
1017	* LogRels in devpciR3CommonRestoreConfig.
1018	*/
1019	for (uint32_t uDevFn = 0; uDevFn < RT_ELEMENTS(pBus->apDevices); uDevFn++)
1020	{
1021	PPDMPCIDEV pDev = pBus->apDevices[uDevFn];
1022	if (pDev)
1023	{
1024	uint16_t u16 = PCIDevGetCommand(pDev);
1025	devpciR3SetCfg(pDevIns, pDev, VBOX_PCI_COMMAND, 0 /u32Value/, 2 /cb/);
1026	PCIDevSetCommand(pDev, u16);
1027	Assert(PCIDevGetCommand(pDev) == u16);
1028	}
1029	}
1030
1031	/*
1032	* Iterate all the devices.
1033	*/
1034	for (uint32_t uDevFn = 0;; uDevFn++)
1035	{
1036	/* index / terminator */
1037	rc = pHlp->pfnSSMGetU32(pSSM, &u32);
1038	if (RT_FAILURE(rc))
1039	return rc;
1040	if (u32 == UINT32_MAX)
1041	break;
1042	if ( u32 >= RT_ELEMENTS(pBus->apDevices)
1043	\|\| u32 < uDevFn)
1044	{
1045	AssertMsgFailed(("u32=%#x uDevFn=%#x\n", u32, uDevFn));
1046	return rc;
1047	}
1048
1049	/* skip forward to the device checking that no new devices are present. */
1050	for (; uDevFn < u32; uDevFn++)
1051	{
1052	if (pBus->apDevices[uDevFn])
1053	{
1054	LogRel(("PCI: New device in slot %#x, %s (vendor=%#06x device=%#06x)\n", uDevFn, pBus->apDevices[uDevFn]->pszNameR3,
1055	PCIDevGetVendorId(pBus->apDevices[uDevFn]), PCIDevGetDeviceId(pBus->apDevices[uDevFn])));
1056	if (pHlp->pfnSSMHandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT)
1057	return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS, N_("New device in slot %#x, %s (vendor=%#06x device=%#06x)"),
1058	uDevFn, pBus->apDevices[uDevFn]->pszNameR3, PCIDevGetVendorId(pBus->apDevices[uDevFn]), PCIDevGetDeviceId(pBus->apDevices[uDevFn]));
1059	}
1060	}
1061
1062	/* get the data */
1063	union
1064	{
1065	PDMPCIDEV DevTmp;
1066	uint8_t abDevTmpPadding[RT_UOFFSETOF(PDMPCIDEV, abMsixState)];
1067	} u;
1068	RT_ZERO(u.DevTmp);
1069	u.DevTmp.Int.s.uIrqPinState = ~0; /* Invalid value in case we have an older saved state to force a state change in pciSetIrq. */
1070	pHlp->pfnSSMGetMem(pSSM, u.DevTmp.abConfig, 256);
1071	if (uVersion < VBOX_PCI_SAVED_STATE_VERSION_IRQ_STATES)
1072	{
1073	int32_t i32Temp;
1074	/* Irq value not needed anymore. */
1075	rc = pHlp->pfnSSMGetS32(pSSM, &i32Temp);
1076	if (RT_FAILURE(rc))
1077	return rc;
1078	}
1079	else
1080	{
1081	rc = pHlp->pfnSSMGetS32(pSSM, &u.DevTmp.Int.s.uIrqPinState);
1082	if (RT_FAILURE(rc))
1083	return rc;
1084	}
1085
1086	/* Load the region types and sizes. */
1087	if (uVersion >= VBOX_PCI_SAVED_STATE_VERSION_REGION_SIZES)
1088	{
1089	for (uint32_t iRegion = 0; iRegion < VBOX_PCI_NUM_REGIONS; iRegion++)
1090	{
1091	pHlp->pfnSSMGetU8(pSSM, &u.DevTmp.Int.s.aIORegions[iRegion].type);
1092	rc = pHlp->pfnSSMGetU64(pSSM, &u.DevTmp.Int.s.aIORegions[iRegion].size);
1093	AssertLogRelRCReturn(rc, rc);
1094	}
1095	}
1096
1097	/* check that it's still around. */
1098	PPDMPCIDEV pDev = pBus->apDevices[uDevFn];
1099	if (!pDev)
1100	{
1101	LogRel(("PCI: Device in slot %#x has been removed! vendor=%#06x device=%#06x\n", uDevFn,
1102	PCIDevGetVendorId(&u.DevTmp), PCIDevGetDeviceId(&u.DevTmp)));
1103	if (pHlp->pfnSSMHandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT)
1104	return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS, N_("Device in slot %#x has been removed! vendor=%#06x device=%#06x"),
1105	uDevFn, PCIDevGetVendorId(&u.DevTmp), PCIDevGetDeviceId(&u.DevTmp));
1106	continue;
1107	}
1108
1109	/* match the vendor id assuming that this will never be changed. */
1110	if ( u.DevTmp.abConfig[0] != pDev->abConfig[0]
1111	\|\| u.DevTmp.abConfig[1] != pDev->abConfig[1])
1112	return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS,
1113	N_("Device in slot %#x (%s) vendor id mismatch! saved=%.4Rhxs current=%.4Rhxs"),
1114	uDevFn, pDev->pszNameR3, u.DevTmp.abConfig, pDev->abConfig);
1115
1116	/* commit the loaded device config. */
1117	rc = devpciR3CommonRestoreRegions(pSSM, pDev, u.DevTmp.Int.s.aIORegions,
1118	uVersion >= VBOX_PCI_SAVED_STATE_VERSION_REGION_SIZES);
1119	if (RT_FAILURE(rc))
1120	break;
1121	devpciR3CommonRestoreConfig(pDevIns, pDev, &u.DevTmp.abConfig[0]);
1122
1123	pDev->Int.s.uIrqPinState = u.DevTmp.Int.s.uIrqPinState;
1124	}
1125
1126	return VINF_SUCCESS;
1127	}
1128
1129
1130	/**
1131	* @callback_method_impl{FNSSMDEVLOADEXEC}
1132	*/
1133	static DECLCALLBACK(int) pciR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1134	{
1135	PDEVPCIROOT pThis = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
1136	PDEVPCIBUS pBus = &pThis->PciBus;
1137	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
1138	uint32_t u32;
1139	int rc;
1140
1141	/*
1142	* Check the version.
1143	*/
1144	if (uVersion > VBOX_PCI_SAVED_STATE_VERSION)
1145	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1146	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
1147
1148	/*
1149	* Bus state data.
1150	*/
1151	pHlp->pfnSSMGetU32(pSSM, &pThis->uConfigReg);
1152	if (uVersion >= VBOX_PCI_SAVED_STATE_VERSION_USE_IO_APIC)
1153	pHlp->pfnSSMGetBool(pSSM, &pThis->fUseIoApic);
1154
1155	/* Load IRQ states. */
1156	if (uVersion >= VBOX_PCI_SAVED_STATE_VERSION_IRQ_STATES)
1157	{
1158	for (uint8_t i = 0; i < RT_ELEMENTS(pThis->Piix3.auPciLegacyIrqLevels); i++)
1159	pHlp->pfnSSMGetU32V(pSSM, &pThis->Piix3.auPciLegacyIrqLevels[i]);
1160	for (uint8_t i = 0; i < RT_ELEMENTS(pThis->auPciApicIrqLevels); i++)
1161	pHlp->pfnSSMGetU32V(pSSM, &pThis->auPciApicIrqLevels[i]);
1162
1163	pHlp->pfnSSMGetU32(pSSM, &pThis->Piix3.iAcpiIrqLevel);
1164	pHlp->pfnSSMGetS32(pSSM, &pThis->Piix3.iAcpiIrq);
1165	}
1166
1167	/* separator */
1168	rc = pHlp->pfnSSMGetU32(pSSM, &u32);
1169	if (RT_FAILURE(rc))
1170	return rc;
1171	if (u32 != UINT32_MAX)
1172	AssertMsgFailedReturn(("u32=%#x\n", u32), rc);
1173
1174	/*
1175	* The devices.
1176	*/
1177	return pciR3CommonLoadExec(pDevIns, pBus, pSSM, uVersion, uPass);
1178	}
1179
1180
1181	/* -=-=-=-=-=- PCI Bus Interface Methods (PDMPCIBUSREG) -=-=-=-=-=- */
1182
1183
1184	/* -=-=-=-=-=- Debug Info Handlers -=-=-=-=-=- */
1185
1186	/**
1187	* @callback_method_impl{FNDBGFHANDLERDEV}
1188	*/
1189	static DECLCALLBACK(void) pciR3IrqRouteInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
1190	{
1191	PPDMPCIDEV pPIIX3 = pDevIns->apPciDevs[1];
1192	NOREF(pszArgs);
1193
1194	uint16_t router = pPIIX3->uDevFn;
1195	pHlp->pfnPrintf(pHlp, "PCI interrupt router at: %02X:%02X:%X\n",
1196	router >> 8, (router >> 3) & 0x1f, router & 0x7);
1197
1198	for (int i = 0; i < 4; ++i)
1199	{
1200	uint8_t irq_map = devpciR3GetByte(pPIIX3, 0x60 + i);
1201	if (irq_map & 0x80)
1202	pHlp->pfnPrintf(pHlp, "PIRQ%c disabled\n", 'A' + i);
1203	else
1204	pHlp->pfnPrintf(pHlp, "PIRQ%c -> IRQ%d\n", 'A' + i, irq_map & 0xf);
1205	}
1206	}
1207
1208	/**
1209	* @callback_method_impl{FNDBGFHANDLERDEV, 'pirq'}
1210	*/
1211	DECLCALLBACK(void) devpciR3InfoPIRQ(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
1212	{
1213	PDEVPCIROOT pGlobals = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
1214	NOREF(pszArgs);
1215
1216	pHlp->pfnPrintf(pHlp, "PCI IRQ levels:\n");
1217	for (int i = 0; i < DEVPCI_LEGACY_IRQ_PINS; ++i)
1218	pHlp->pfnPrintf(pHlp, " IRQ%c: %u\n", 'A' + i, pGlobals->Piix3.auPciLegacyIrqLevels[i]);
1219	}
1220
1221
1222	/* -=-=-=-=-=- PDMDEVREG -=-=-=-=-=- */
1223
1224	/**
1225	* @interface_method_impl{PDMDEVREG,pfnReset}
1226	*/
1227	static DECLCALLBACK(void) pciR3Reset(PPDMDEVINS pDevIns)
1228	{
1229	PDEVPCIROOT pGlobals = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
1230	PDEVPCIBUS pBus = &pGlobals->PciBus;
1231
1232	/* PCI-specific reset for each device. */
1233	for (uint32_t uDevFn = 0; uDevFn < RT_ELEMENTS(pBus->apDevices); uDevFn++)
1234	{
1235	if (pBus->apDevices[uDevFn])
1236	devpciR3ResetDevice(pDevIns, pBus->apDevices[uDevFn]);
1237	}
1238
1239	pciR3Piix3Reset(pDevIns->apPciDevs[1]);
1240	}
1241
1242
1243	/**
1244	* @interface_method_impl{PDMDEVREG,pfnDestruct}
1245	*/
1246	static DECLCALLBACK(int) pciR3Destruct(PPDMDEVINS pDevIns)
1247	{
1248	PDEVPCIROOT pGlobals = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
1249	if (pGlobals->PciBus.papBridgesR3)
1250	{
1251	PDMDevHlpMMHeapFree(pDevIns, pGlobals->PciBus.papBridgesR3);
1252	pGlobals->PciBus.papBridgesR3 = NULL;
1253	}
1254	return VINF_SUCCESS;
1255	}
1256
1257
1258	/**
1259	* @interface_method_impl{PDMDEVREG,pfnConstruct}
1260	*/
1261	static DECLCALLBACK(int) pciR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
1262	{
1263	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
1264	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
1265	PDEVPCIBUSCC pBusCC = PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC);
1266	PDEVPCIROOT pGlobals = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
1267	RT_NOREF(iInstance);
1268	Assert(iInstance == 0);
1269
1270	/*
1271	* Validate and read configuration.
1272	*/
1273	PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "IOAPIC", "");
1274
1275	/* query whether we got an IOAPIC */
1276	bool fUseIoApic;
1277	int rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "IOAPIC", &fUseIoApic, false);
1278	if (RT_FAILURE(rc))
1279	return PDMDEV_SET_ERROR(pDevIns, rc,
1280	N_("Configuration error: Failed to query boolean value \"IOAPIC\""));
1281
1282	Log(("PCI: fUseIoApic=%RTbool fR0Enabled=%RTbool fRCEnabled=%RTbool\n", fUseIoApic, pDevIns->fR0Enabled, pDevIns->fRCEnabled));
1283
1284	/*
1285	* Init data and register the PCI bus.
1286	*/
1287	pGlobals->uPciBiosIo = 0xc000;
1288	pGlobals->uPciBiosMmio = 0xf0000000;
1289	memset((void *)&pGlobals->Piix3.auPciLegacyIrqLevels, 0, sizeof(pGlobals->Piix3.auPciLegacyIrqLevels));
1290	pGlobals->fUseIoApic = fUseIoApic;
1291	memset((void *)&pGlobals->auPciApicIrqLevels, 0, sizeof(pGlobals->auPciApicIrqLevels));
1292
1293	pGlobals->PciBus.fTypePiix3 = true;
1294	pGlobals->PciBus.fTypeIch9 = false;
1295	pGlobals->PciBus.fPureBridge = false;
1296	pGlobals->PciBus.papBridgesR3 = (PPDMPCIDEV *)PDMDevHlpMMHeapAllocZ(pDevIns,
1297	sizeof(PPDMPCIDEV)
1298	* RT_ELEMENTS(pGlobals->PciBus.apDevices));
1299	AssertLogRelReturn(pGlobals->PciBus.papBridgesR3, VERR_NO_MEMORY);
1300
1301	PDEVPCIBUS pBus = &pGlobals->PciBus;
1302	PDMPCIBUSREGCC PciBusReg;
1303	PciBusReg.u32Version = PDM_PCIBUSREGCC_VERSION;
1304	PciBusReg.pfnRegisterR3 = devpciR3CommonRegisterDevice;
1305	PciBusReg.pfnRegisterMsiR3 = NULL;
1306	PciBusReg.pfnIORegionRegisterR3 = devpciR3CommonIORegionRegister;
1307	PciBusReg.pfnInterceptConfigAccesses = devpciR3CommonInterceptConfigAccesses;
1308	PciBusReg.pfnConfigRead = devpciR3CommonConfigRead;
1309	PciBusReg.pfnConfigWrite = devpciR3CommonConfigWrite;
1310	PciBusReg.pfnSetIrqR3 = pciSetIrq;
1311	PciBusReg.u32EndVersion = PDM_PCIBUSREGCC_VERSION;
1312	rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBusCC->pPciHlpR3, &pBus->iBus);
1313	if (RT_FAILURE(rc))
1314	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to register ourselves as a PCI Bus"));
1315	Assert(pBus->iBus == 0);
1316	if (pBusCC->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
1317	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
1318	N_("PCI helper version mismatch; got %#x expected %#x"),
1319	pBusCC->pPciHlpR3->u32Version, PDM_PCIHLPR3_VERSION);
1320
1321	/* Disable default device locking. */
1322	rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
1323	AssertRCReturn(rc, rc);
1324
1325	/*
1326	* Fill in PCI configs and add them to the bus.
1327	*/
1328	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1329	AssertPtr(pPciDev);
1330
1331	/* i440FX */
1332	PCIDevSetVendorId( pPciDev, 0x8086); /* Intel */
1333	PCIDevSetDeviceId( pPciDev, 0x1237);
1334	PCIDevSetRevisionId(pPciDev, 0x02);
1335	PCIDevSetClassSub( pPciDev, 0x00); /* host2pci */
1336	PCIDevSetClassBase( pPciDev, 0x06); /* PCI_bridge */
1337	PCIDevSetHeaderType(pPciDev, 0x00);
1338	rc = PDMDevHlpPCIRegisterEx(pDevIns, pPciDev, 0 /fFlags/, 0 /uPciDevNo/, 0 /uPciFunNo/, "i440FX");
1339	AssertLogRelRCReturn(rc, rc);
1340
1341	/* PIIX3 */
1342	PPDMPCIDEV pPiix3PciDev = pDevIns->apPciDevs[1];
1343	PCIDevSetVendorId( pPiix3PciDev, 0x8086); /* Intel */
1344	PCIDevSetDeviceId( pPiix3PciDev, 0x7000); /* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */
1345	PCIDevSetClassSub( pPiix3PciDev, 0x01); /* PCI_ISA */
1346	PCIDevSetClassBase( pPiix3PciDev, 0x06); /* PCI_bridge */
1347	PCIDevSetHeaderType(pPiix3PciDev, 0x80); /* PCI_multifunction, generic */
1348	rc = PDMDevHlpPCIRegisterEx(pDevIns, pPiix3PciDev, 0 /fFlags/, 1 /uPciDevNo/, 0 /uPciFunNo/, "PIIX3");
1349	AssertLogRelRCReturn(rc, rc);
1350	pciR3Piix3Reset(pDevIns->apPciDevs[1]);
1351
1352	pBus->iDevSearch = 16;
1353
1354	/*
1355	* Register I/O ports and save state.
1356	*/
1357	static const IOMIOPORTDESC s_aAddrDesc[] = { { "PCI address", "PCI address", NULL, NULL }, { NULL, NULL, NULL, NULL } };
1358	rc = PDMDevHlpIoPortCreateAndMap(pDevIns, 0x0cf8, 1, pciIOPortAddressWrite, pciIOPortAddressRead, "i440FX (PCI)", s_aAddrDesc,
1359	&pGlobals->hIoPortAddress);
1360	AssertLogRelRCReturn(rc, rc);
1361
1362	static const IOMIOPORTDESC s_aDataDesc[] = { { "PCI data", "PCI data", NULL, NULL }, { NULL, NULL, NULL, NULL } };
1363	rc = PDMDevHlpIoPortCreateAndMap(pDevIns, 0x0cfc, 4, pciIOPortDataWrite, pciIOPortDataRead, "i440FX (PCI)", s_aDataDesc,
1364	&pGlobals->hIoPortData);
1365	AssertLogRelRCReturn(rc, rc);
1366
1367	static const IOMIOPORTDESC s_aMagicDesc[] = { { "PCI magic", NULL, NULL, NULL }, { NULL, NULL, NULL, NULL } };
1368	rc = PDMDevHlpIoPortCreateAndMap(pDevIns, 0x0410, 1, pciR3IOPortMagicPCIWrite, pciR3IOPortMagicPCIRead,
1369	"i440FX (Fake PCI BIOS trigger)", s_aMagicDesc, &pGlobals->hIoPortMagic);
1370	AssertLogRelRCReturn(rc, rc);
1371
1372
1373	rc = PDMDevHlpSSMRegisterEx(pDevIns, VBOX_PCI_SAVED_STATE_VERSION, sizeof(pBus) + 16128, "pgm",
1374	NULL, NULL, NULL,
1375	NULL, pciR3SaveExec, NULL,
1376	NULL, pciR3LoadExec, NULL);
1377	AssertLogRelRCReturn(rc, rc);
1378
1379	PDMDevHlpDBGFInfoRegister(pDevIns, "pci",
1380	"Display PCI bus status. Recognizes 'basic' or 'verbose' as arguments, defaults to 'basic'.",
1381	devpciR3InfoPci);
1382	PDMDevHlpDBGFInfoRegister(pDevIns, "pciirq", "Display PCI IRQ state. (no arguments)", devpciR3InfoPciIrq);
1383	PDMDevHlpDBGFInfoRegister(pDevIns, "pirq", "Display PIRQ state. (no arguments)", devpciR3InfoPIRQ);
1384	PDMDevHlpDBGFInfoRegister(pDevIns, "irqroute", "Display PCI IRQ routing. (no arguments)", pciR3IrqRouteInfo);
1385
1386	return VINF_SUCCESS;
1387	}
1388
1389	#else /* !IN_RING3 */
1390
1391	/**
1392	* @interface_method_impl{PDMDEVREGR0,pfnConstruct}
1393	*/
1394	static DECLCALLBACK(int) pciRZRootConstruct(PPDMDEVINS pDevIns)
1395	{
1396	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
1397	PDEVPCIROOT pGlobals = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
1398	PDEVPCIBUSCC pBusCC = PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC);
1399
1400	/* Mirror the ring-3 device lock disabling: */
1401	int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
1402	AssertRCReturn(rc, rc);
1403
1404	/* Set up the RZ PCI bus callbacks: */
1405	PDMPCIBUSREGCC PciBusReg;
1406	PciBusReg.u32Version = PDM_PCIBUSREGCC_VERSION;
1407	PciBusReg.iBus = pGlobals->PciBus.iBus;
1408	PciBusReg.pfnSetIrq = pciSetIrq;
1409	PciBusReg.u32EndVersion = PDM_PCIBUSREGCC_VERSION;
1410	rc = PDMDevHlpPCIBusSetUpContext(pDevIns, &PciBusReg, &pBusCC->CTX_SUFF(pPciHlp));
1411	AssertRCReturn(rc, rc);
1412
1413	/* Set up I/O port callbacks, except for the magic port: */
1414	rc = PDMDevHlpIoPortSetUpContext(pDevIns, pGlobals->hIoPortAddress, pciIOPortAddressWrite, pciIOPortAddressRead, NULL);
1415	AssertLogRelRCReturn(rc, rc);
1416
1417	rc = PDMDevHlpIoPortSetUpContext(pDevIns, pGlobals->hIoPortData, pciIOPortDataWrite, pciIOPortDataRead, NULL);
1418	AssertLogRelRCReturn(rc, rc);
1419
1420	return rc;
1421	}
1422
1423	#endif /* !IN_RING3 */
1424
1425	/**
1426	* The device registration structure.
1427	*/
1428	const PDMDEVREG g_DevicePCI =
1429	{
1430	/* .u32Version = */ PDM_DEVREG_VERSION,
1431	/* .uReserved0 = */ 0,
1432	/* .szName = */ "pci",
1433	/* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RZ \| PDM_DEVREG_FLAGS_NEW_STYLE,
1434	/* .fClass = */ PDM_DEVREG_CLASS_BUS_PCI \| PDM_DEVREG_CLASS_BUS_ISA,
1435	/* .cMaxInstances = */ 1,
1436	/* .uSharedVersion = */ 42,
1437	/* .cbInstanceShared = */ sizeof(DEVPCIROOT),
1438	/* .cbInstanceCC = */ sizeof(CTX_SUFF(DEVPCIBUS)),
1439	/* .cbInstanceRC = */ sizeof(DEVPCIBUSRC),
1440	/* .cMaxPciDevices = */ 2,
1441	/* .cMaxMsixVectors = */ 0,
1442	/* .pszDescription = */ "i440FX PCI bridge and PIIX3 ISA bridge.",
1443	#if defined(IN_RING3)
1444	/* .pszRCMod = */ "VBoxDDRC.rc",
1445	/* .pszR0Mod = */ "VBoxDDR0.r0",
1446	/* .pfnConstruct = */ pciR3Construct,
1447	/* .pfnDestruct = */ pciR3Destruct,
1448	/* .pfnRelocate = */ NULL,
1449	/* .pfnMemSetup = */ NULL,
1450	/* .pfnPowerOn = */ NULL,
1451	/* .pfnReset = */ pciR3Reset,
1452	/* .pfnSuspend = */ NULL,
1453	/* .pfnResume = */ NULL,
1454	/* .pfnAttach = */ NULL,
1455	/* .pfnDetach = */ NULL,
1456	/* .pfnQueryInterface = */ NULL,
1457	/* .pfnInitComplete = */ NULL,
1458	/* .pfnPowerOff = */ NULL,
1459	/* .pfnSoftReset = */ NULL,
1460	/* .pfnReserved0 = */ NULL,
1461	/* .pfnReserved1 = */ NULL,
1462	/* .pfnReserved2 = */ NULL,
1463	/* .pfnReserved3 = */ NULL,
1464	/* .pfnReserved4 = */ NULL,
1465	/* .pfnReserved5 = */ NULL,
1466	/* .pfnReserved6 = */ NULL,
1467	/* .pfnReserved7 = */ NULL,
1468	#elif defined(IN_RING0)
1469	/* .pfnEarlyConstruct = */ NULL,
1470	/* .pfnConstruct = */ pciRZRootConstruct,
1471	/* .pfnDestruct = */ NULL,
1472	/* .pfnFinalDestruct = */ NULL,
1473	/* .pfnRequest = */ NULL,
1474	/* .pfnReserved0 = */ NULL,
1475	/* .pfnReserved1 = */ NULL,
1476	/* .pfnReserved2 = */ NULL,
1477	/* .pfnReserved3 = */ NULL,
1478	/* .pfnReserved4 = */ NULL,
1479	/* .pfnReserved5 = */ NULL,
1480	/* .pfnReserved6 = */ NULL,
1481	/* .pfnReserved7 = */ NULL,
1482	#elif defined(IN_RC)
1483	/* .pfnConstruct = */ pciRZRootConstruct,
1484	/* .pfnReserved0 = */ NULL,
1485	/* .pfnReserved1 = */ NULL,
1486	/* .pfnReserved2 = */ NULL,
1487	/* .pfnReserved3 = */ NULL,
1488	/* .pfnReserved4 = */ NULL,
1489	/* .pfnReserved5 = */ NULL,
1490	/* .pfnReserved6 = */ NULL,
1491	/* .pfnReserved7 = */ NULL,
1492	#else
1493	# error "Not in IN_RING3, IN_RING0 or IN_RC!"
1494	#endif
1495	/* .u32VersionEnd = */ PDM_DEVREG_VERSION
1496
1497	};
1498
1499
1500
1501	/* -=-=-=-=-=- The PCI bridge specific bits -=-=-=-=-=- */
1502
1503	/**
1504	* @interface_method_impl{PDMPCIBUSREGR3,pfnSetIrqR3}
1505	*/
1506	static DECLCALLBACK(void) pcibridgeSetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc)
1507	{
1508	LogFlow(("pcibridgeSetIrq: %p %u %u %#x\n", pPciDev, iIrq, iLevel, uTagSrc));
1509
1510	/*
1511	* The PCI-to-PCI bridge specification defines how the interrupt pins
1512	* are routed from the secondary to the primary bus (see chapter 9).
1513	* iIrq gives the interrupt pin the pci device asserted.
1514	* We change iIrq here according to the spec and call the SetIrq function
1515	* of our parent passing the device which asserted the interrupt instead of the device of the bridge.
1516	*/
1517	PDEVPCIBUS pBus;
1518	uint8_t uDevFnBridge;
1519	int iIrqPinBridge;
1520	PPDMDEVINS pDevInsBus = devpcibridgeCommonSetIrqRootWalk(pDevIns, pPciDev, iIrq, &pBus, &uDevFnBridge, &iIrqPinBridge);
1521	AssertReturnVoid(pDevInsBus);
1522	AssertMsg(pBus->iBus == 0, ("This is not the host pci bus iBus=%d\n", pBus->iBus));
1523	Assert(pDevInsBus->pReg == &g_DevicePCI);
1524
1525	pciSetIrqInternal(pDevInsBus, DEVPCIBUS_2_DEVPCIROOT(pBus), PDMINS_2_DATA_CC(pDevInsBus, PDEVPCIBUSCC),
1526	uDevFnBridge, pPciDev, iIrqPinBridge, iLevel, uTagSrc);
1527	}
1528
1529	#ifdef IN_RING3
1530
1531	/**
1532	* @callback_method_impl{FNPCIBRIDGECONFIGWRITE}
1533	*/
1534	static DECLCALLBACK(VBOXSTRICTRC) pcibridgeR3ConfigWrite(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice,
1535	uint32_t u32Address, unsigned cb, uint32_t u32Value)
1536	{
1537	LogFlowFunc(("pDevIns=%p iBus=%d iDevice=%d u32Address=%u cb=%d u32Value=%u\n", pDevIns, iBus, iDevice, u32Address, cb, u32Value));
1538	PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
1539	VBOXSTRICTRC rcStrict = VINF_SUCCESS;
1540
1541	/* If the current bus is not the target bus search for the bus which contains the device. */
1542	if (iBus != pDevIns->apPciDevs[0]->abConfig[VBOX_PCI_SECONDARY_BUS])
1543	{
1544	PPDMPCIDEV pBridgeDevice = pciR3FindBridge(pBus, iBus);
1545	if (pBridgeDevice)
1546	{
1547	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigWrite);
1548	rcStrict = pBridgeDevice->Int.s.pfnBridgeConfigWrite(pBridgeDevice->Int.s.CTX_SUFF(pDevIns), iBus, iDevice,
1549	u32Address, cb, u32Value);
1550	}
1551	}
1552	else
1553	{
1554	/* This is the target bus, pass the write to the device. */
1555	PPDMPCIDEV pPciDev = pBus->apDevices[iDevice];
1556	if (pPciDev)
1557	{
1558	LogFunc(("%s: addr=%02x val=%08x len=%d\n", pPciDev->pszNameR3, u32Address, u32Value, cb));
1559	rcStrict = VINF_PDM_PCI_DO_DEFAULT;
1560	if (pPciDev->Int.s.pfnConfigWrite)
1561	rcStrict = pPciDev->Int.s.pfnConfigWrite(pPciDev->Int.s.CTX_SUFF(pDevIns), pPciDev, u32Address, cb, u32Value);
1562	if (rcStrict == VINF_PDM_PCI_DO_DEFAULT)
1563	rcStrict = devpciR3CommonConfigWriteWorker(pDevIns, PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC),
1564	pPciDev, u32Address, cb, u32Value);
1565	}
1566	}
1567	return rcStrict;
1568	}
1569
1570
1571	/**
1572	* @callback_method_impl{FNPCIBRIDGECONFIGREAD}
1573	*/
1574	static DECLCALLBACK(VBOXSTRICTRC) pcibridgeR3ConfigRead(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice,
1575	uint32_t u32Address, unsigned cb, uint32_t *pu32Value)
1576	{
1577	LogFlowFunc(("pDevIns=%p iBus=%d iDevice=%d u32Address=%u cb=%d\n", pDevIns, iBus, iDevice, u32Address, cb));
1578	PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
1579	VBOXSTRICTRC rcStrict = VINF_SUCCESS;
1580
1581	/* If the current bus is not the target bus search for the bus which contains the device. */
1582	if (iBus != pDevIns->apPciDevs[0]->abConfig[VBOX_PCI_SECONDARY_BUS])
1583	{
1584	PPDMPCIDEV pBridgeDevice = pciR3FindBridge(pBus, iBus);
1585	if (pBridgeDevice)
1586	{
1587	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigRead);
1588	rcStrict = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->Int.s.CTX_SUFF(pDevIns),
1589	iBus, iDevice, u32Address, cb, pu32Value);
1590	}
1591	else
1592	*pu32Value = UINT32_MAX;
1593	}
1594	else
1595	{
1596	/* This is the target bus, pass the read to the device. */
1597	PPDMPCIDEV pPciDev = pBus->apDevices[iDevice];
1598	if (pPciDev)
1599	{
1600	rcStrict = VINF_PDM_PCI_DO_DEFAULT;
1601	if (pPciDev->Int.s.pfnConfigRead)
1602	rcStrict = pPciDev->Int.s.pfnConfigRead(pPciDev->Int.s.CTX_SUFF(pDevIns), pPciDev, u32Address, cb, pu32Value);
1603	if (rcStrict == VINF_PDM_PCI_DO_DEFAULT)
1604	rcStrict = devpciR3CommonConfigReadWorker(pPciDev, u32Address, cb, pu32Value);
1605
1606	LogFunc(("%s: u32Address=%02x u32Value=%08x cb=%d\n", pPciDev->pszNameR3, u32Address, *pu32Value, cb));
1607	}
1608	else
1609	*pu32Value = UINT32_MAX;
1610	}
1611
1612	return rcStrict;
1613	}
1614
1615
1616	/**
1617	* @callback_method_impl{FNSSMDEVSAVEEXEC}
1618	*/
1619	static DECLCALLBACK(int) pcibridgeR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
1620	{
1621	return pciR3CommonSaveExec(pDevIns->pHlpR3, PDMINS_2_DATA(pDevIns, PDEVPCIBUS), pSSM);
1622	}
1623
1624
1625	/**
1626	* @callback_method_impl{FNSSMDEVLOADEXEC}
1627	*/
1628	static DECLCALLBACK(int) pcibridgeR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1629	{
1630	PDEVPCIBUS pThis = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
1631	if (uVersion > VBOX_PCI_SAVED_STATE_VERSION)
1632	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1633	return pciR3CommonLoadExec(pDevIns, pThis, pSSM, uVersion, uPass);
1634	}
1635
1636
1637	/**
1638	* @interface_method_impl{PDMDEVREG,pfnReset}
1639	*/
1640	static DECLCALLBACK(void) pcibridgeR3Reset(PPDMDEVINS pDevIns)
1641	{
1642	/* Reset config space to default values. */
1643	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1644	pPciDev->abConfig[VBOX_PCI_PRIMARY_BUS] = 0;
1645	pPciDev->abConfig[VBOX_PCI_SECONDARY_BUS] = 0;
1646	pPciDev->abConfig[VBOX_PCI_SUBORDINATE_BUS] = 0;
1647	}
1648
1649
1650	/**
1651	* @interface_method_impl{PDMDEVREG,pfnDestruct}
1652	*/
1653	static DECLCALLBACK(int) pcibridgeR3Destruct(PPDMDEVINS pDevIns)
1654	{
1655	PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
1656	if (pBus->papBridgesR3)
1657	{
1658	PDMDevHlpMMHeapFree(pDevIns, pBus->papBridgesR3);
1659	pBus->papBridgesR3 = NULL;
1660	}
1661	return VINF_SUCCESS;
1662	}
1663
1664
1665	/**
1666	* @interface_method_impl{PDMDEVREG,pfnConstruct}
1667	*/
1668	static DECLCALLBACK(int) pcibridgeR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
1669	{
1670	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
1671	RT_NOREF(iInstance, pCfg);
1672	PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
1673	PDEVPCIBUSCC pBusCC = PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC);
1674
1675	/*
1676	* Validate and read configuration (none left).
1677	*/
1678	PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "", "");
1679	Log(("PCI: fRCEnabled=%RTbool fR0Enabled=%RTbool\n", pDevIns->fRCEnabled, pDevIns->fR0Enabled));
1680
1681	/*
1682	* Init data and register the PCI bus.
1683	*/
1684	pBus->fTypePiix3 = true;
1685	pBus->fTypeIch9 = false;
1686	pBus->fPureBridge = true;
1687	pBus->papBridgesR3 = (PPDMPCIDEV )PDMDevHlpMMHeapAllocZ(pDevIns, sizeof(PPDMPCIDEV) RT_ELEMENTS(pBus->apDevices));
1688	AssertLogRelReturn(pBus->papBridgesR3, VERR_NO_MEMORY);
1689
1690	PDMPCIBUSREGCC PciBusReg;
1691	PciBusReg.u32Version = PDM_PCIBUSREGCC_VERSION;
1692	PciBusReg.pfnRegisterR3 = devpcibridgeR3CommonRegisterDevice;
1693	PciBusReg.pfnRegisterMsiR3 = NULL;
1694	PciBusReg.pfnIORegionRegisterR3 = devpciR3CommonIORegionRegister;
1695	PciBusReg.pfnInterceptConfigAccesses = devpciR3CommonInterceptConfigAccesses;
1696	PciBusReg.pfnConfigWrite = devpciR3CommonConfigWrite;
1697	PciBusReg.pfnConfigRead = devpciR3CommonConfigRead;
1698	PciBusReg.pfnSetIrqR3 = pcibridgeSetIrq;
1699	PciBusReg.u32EndVersion = PDM_PCIBUSREGCC_VERSION;
1700	int rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBusCC->pPciHlpR3, &pBus->iBus);
1701	if (RT_FAILURE(rc))
1702	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to register ourselves as a PCI Bus"));
1703	Assert(pBus->iBus == (uint32_t)iInstance + 1); /* Can be removed when adding support for multiple bridge implementations. */
1704	if (pBusCC->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
1705	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
1706	N_("PCI helper version mismatch; got %#x expected %#x"),
1707	pBusCC->pPciHlpR3->u32Version, PDM_PCIHLPR3_VERSION);
1708
1709	/*
1710	* Fill in PCI configs and add them to the bus.
1711	*/
1712	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1713	PCIDevSetVendorId( pPciDev, 0x8086); /* Intel */
1714	PCIDevSetDeviceId( pPciDev, 0x2448); /* 82801 Mobile PCI bridge. */
1715	PCIDevSetRevisionId(pPciDev, 0xf2);
1716	PCIDevSetClassSub( pPciDev, 0x04); /* pci2pci */
1717	PCIDevSetClassBase( pPciDev, 0x06); /* PCI_bridge */
1718	PCIDevSetClassProg( pPciDev, 0x01); /* Supports subtractive decoding. */
1719	PCIDevSetHeaderType(pPciDev, 0x01); /* Single function device which adheres to the PCI-to-PCI bridge spec. */
1720	PCIDevSetCommand( pPciDev, 0x0000);
1721	PCIDevSetStatus( pPciDev, 0x0020); /* 66MHz Capable. */
1722	PCIDevSetInterruptLine(pPciDev, 0x00); /* This device does not assert interrupts. */
1723
1724	/*
1725	* This device does not generate interrupts. Interrupt delivery from
1726	* devices attached to the bus is unaffected.
1727	*/
1728	PCIDevSetInterruptPin(pPciDev, 0x00);
1729
1730	/*
1731	* Register this PCI bridge. The called function will take care on which bus we will get registered.
1732	*/
1733	rc = PDMDevHlpPCIRegisterEx(pDevIns, pPciDev, PDMPCIDEVREG_F_PCI_BRIDGE, PDMPCIDEVREG_DEV_NO_FIRST_UNUSED,
1734	PDMPCIDEVREG_FUN_NO_FIRST_UNUSED, "pcibridge");
1735	if (RT_FAILURE(rc))
1736	return rc;
1737	pPciDev->Int.s.pfnBridgeConfigRead = pcibridgeR3ConfigRead;
1738	pPciDev->Int.s.pfnBridgeConfigWrite = pcibridgeR3ConfigWrite;
1739
1740	pBus->iDevSearch = 0;
1741
1742	/*
1743	* Register SSM handlers. We use the same saved state version as for the host bridge
1744	* to make changes easier.
1745	*/
1746	rc = PDMDevHlpSSMRegisterEx(pDevIns, VBOX_PCI_SAVED_STATE_VERSION, sizeof(pBus) + 16128, "pgm",
1747	NULL, NULL, NULL,
1748	NULL, pcibridgeR3SaveExec, NULL,
1749	NULL, pcibridgeR3LoadExec, NULL);
1750	if (RT_FAILURE(rc))
1751	return rc;
1752
1753	return VINF_SUCCESS;
1754	}
1755
1756	#else /* !IN_RING3 */
1757
1758	/**
1759	* @interface_method_impl{PDMDEVREGR0,pfnConstruct}
1760	*/
1761	static DECLCALLBACK(int) pcibridgeRZConstruct(PPDMDEVINS pDevIns)
1762	{
1763	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
1764	PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
1765	PDEVPCIBUSCC pBusCC = PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC);
1766
1767	PDMPCIBUSREGCC PciBusReg;
1768	PciBusReg.u32Version = PDM_PCIBUSREGCC_VERSION;
1769	PciBusReg.iBus = pBus->iBus;
1770	PciBusReg.pfnSetIrq = pcibridgeSetIrq;
1771	PciBusReg.u32EndVersion = PDM_PCIBUSREGCC_VERSION;
1772	int rc = PDMDevHlpPCIBusSetUpContext(pDevIns, &PciBusReg, &pBusCC->CTX_SUFF(pPciHlp));
1773	AssertRC(rc);
1774
1775	return rc;
1776	}
1777
1778	#endif /* !IN_RING3 */
1779
1780	/**
1781	* The device registration structure
1782	* for the PCI-to-PCI bridge.
1783	*/
1784	const PDMDEVREG g_DevicePCIBridge =
1785	{
1786	/* .u32Version = */ PDM_DEVREG_VERSION,
1787	/* .uReserved0 = */ 0,
1788	/* .szName = */ "pcibridge",
1789	/* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RZ \| PDM_DEVREG_FLAGS_NEW_STYLE,
1790	/* .fClass = */ PDM_DEVREG_CLASS_BUS_PCI,
1791	/* .cMaxInstances = */ ~0U,
1792	/* .uSharedVersion = */ 42,
1793	/* .cbInstanceShared = */ sizeof(DEVPCIBUS),
1794	/* .cbInstanceCC = */ sizeof(CTX_SUFF(DEVPCIBUS)),
1795	/* .cbInstanceRC = */ 0,
1796	/* .cMaxPciDevices = */ 1,
1797	/* .cMaxMsixVectors = */ 0,
1798	/* .pszDescription = */ "82801 Mobile PCI to PCI bridge",
1799	#if defined(IN_RING3)
1800	/* .pszRCMod = */ "VBoxDDRC.rc",
1801	/* .pszR0Mod = */ "VBoxDDR0.r0",
1802	/* .pfnConstruct = */ pcibridgeR3Construct,
1803	/* .pfnDestruct = */ pcibridgeR3Destruct,
1804	/* .pfnRelocate = */ NULL,
1805	/* .pfnMemSetup = */ NULL,
1806	/* .pfnPowerOn = */ NULL,
1807	/* .pfnReset = */ pcibridgeR3Reset,
1808	/* .pfnSuspend = */ NULL,
1809	/* .pfnResume = */ NULL,
1810	/* .pfnAttach = */ NULL,
1811	/* .pfnDetach = */ NULL,
1812	/* .pfnQueryInterface = */ NULL,
1813	/* .pfnInitComplete = */ NULL,
1814	/* .pfnPowerOff = */ NULL,
1815	/* .pfnSoftReset = */ NULL,
1816	/* .pfnReserved0 = */ NULL,
1817	/* .pfnReserved1 = */ NULL,
1818	/* .pfnReserved2 = */ NULL,
1819	/* .pfnReserved3 = */ NULL,
1820	/* .pfnReserved4 = */ NULL,
1821	/* .pfnReserved5 = */ NULL,
1822	/* .pfnReserved6 = */ NULL,
1823	/* .pfnReserved7 = */ NULL,
1824	#elif defined(IN_RING0)
1825	/* .pfnEarlyConstruct = */ NULL,
1826	/* .pfnConstruct = */ pcibridgeRZConstruct,
1827	/* .pfnDestruct = */ NULL,
1828	/* .pfnFinalDestruct = */ NULL,
1829	/* .pfnRequest = */ NULL,
1830	/* .pfnReserved0 = */ NULL,
1831	/* .pfnReserved1 = */ NULL,
1832	/* .pfnReserved2 = */ NULL,
1833	/* .pfnReserved3 = */ NULL,
1834	/* .pfnReserved4 = */ NULL,
1835	/* .pfnReserved5 = */ NULL,
1836	/* .pfnReserved6 = */ NULL,
1837	/* .pfnReserved7 = */ NULL,
1838	#elif defined(IN_RC)
1839	/* .pfnConstruct = */ pcibridgeRZConstruct,
1840	/* .pfnReserved0 = */ NULL,
1841	/* .pfnReserved1 = */ NULL,
1842	/* .pfnReserved2 = */ NULL,
1843	/* .pfnReserved3 = */ NULL,
1844	/* .pfnReserved4 = */ NULL,
1845	/* .pfnReserved5 = */ NULL,
1846	/* .pfnReserved6 = */ NULL,
1847	/* .pfnReserved7 = */ NULL,
1848	#else
1849	# error "Not in IN_RING3, IN_RING0 or IN_RC!"
1850	#endif
1851	/* .u32VersionEnd = */ PDM_DEVREG_VERSION
1852	};
1853

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source: vbox/trunk/src/VBox/Devices/Bus/DevPCI.cpp@ 83575

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