DevPCI.cpp@ 86728

Last change on this file since 86728 was 85478, checked in by vboxsync, 4 years ago
DevPCI.cpp: Move special VGA case into generic allocation, to make it flexibly handle VBoxVGA, VMSVGA and VBoxSVGA. Important for 256MB VRAM, since it fits only in the special place.
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File size: 75.0 KB

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1	/* $Id: DevPCI.cpp 85478 2020-07-27 18:20:55Z vboxsync $ */
2	/** @file
3	* DevPCI - PCI BUS Device.
4	*
5	* @remarks New code shall be added to DevPciIch9.cpp as that will become
6	* the common PCI bus code soon. Don't fix code in both DevPCI.cpp
7	* and DevPciIch9.cpp when it's possible to just make the latter
8	* version common. Common code uses the 'devpci' prefix, is
9	* prototyped in DevPciInternal.h, and is defined in DevPciIch9.cpp.
10	*/
11
12	/*
13	* Copyright (C) 2006-2020 Oracle Corporation
14	*
15	* This file is part of VirtualBox Open Source Edition (OSE), as
16	* available from http://www.virtualbox.org. This file is free software;
17	* you can redistribute it and/or modify it under the terms of the GNU
18	* General Public License (GPL) as published by the Free Software
19	* Foundation, in version 2 as it comes in the "COPYING" file of the
20	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
21	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
22	* --------------------------------------------------------------------
23	*
24	* This code is based on:
25	*
26	* QEMU PCI bus manager
27	*
28	* Copyright (c) 2004 Fabrice Bellard
29	*
30	* Permission is hereby granted, free of charge, to any person obtaining a copy
31	* of this software and associated documentation files (the "Software"), to deal
32	* in the Software without restriction, including without limitation the rights
33	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
34	* copies of the Software, and to permit persons to whom the Software is
35	* furnished to do so, subject to the following conditions:
36	*
37	* The above copyright notice and this permission notice shall be included in
38	* all copies or substantial portions of the Software.
39	*
40	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
41	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
42	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
43	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
44	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
45	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
46	* THE SOFTWARE.
47	*/
48
49
50	/*********************************************************************************************************************************
51	* Header Files *
52	*********************************************************************************************************************************/
53	#define LOG_GROUP LOG_GROUP_DEV_PCI
54	#define PDMPCIDEV_INCLUDE_PRIVATE /* Hack to get pdmpcidevint.h included at the right point. */
55	#include <VBox/vmm/pdmpcidev.h>
56	#include <VBox/vmm/pdmdev.h>
57	#include <VBox/vmm/mm.h>
58	#include <iprt/asm.h>
59	#include <iprt/assert.h>
60	#include <iprt/string.h>
61
62	#include "PciInline.h"
63	#include "VBoxDD.h"
64	#include "DevPciInternal.h"
65
66
67	/*********************************************************************************************************************************
68	* Defined Constants And Macros *
69	*********************************************************************************************************************************/
70	/** Saved state version of the PCI bus device. */
71	#define VBOX_PCI_SAVED_STATE_VERSION VBOX_PCI_SAVED_STATE_VERSION_REGION_SIZES
72	/** Adds I/O region types and sizes for dealing changes in resource regions. */
73	#define VBOX_PCI_SAVED_STATE_VERSION_REGION_SIZES 4
74	/** Before region sizes, the first named one.
75	* Looking at the code though, we support even older version. */
76	#define VBOX_PCI_SAVED_STATE_VERSION_IRQ_STATES 3
77	/** Notes whether we use the I/O APIC. */
78	#define VBOX_PCI_SAVED_STATE_VERSION_USE_IO_APIC 2
79
80
81	/*********************************************************************************************************************************
82	* Internal Functions *
83	*********************************************************************************************************************************/
84	RT_C_DECLS_BEGIN
85
86	static DECLCALLBACK(void) pcibridgeSetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTag);
87
88	#ifdef IN_RING3
89	DECLINLINE(PPDMPCIDEV) pciR3FindBridge(PDEVPCIBUS pBus, uint8_t iBus);
90	#endif
91
92	RT_C_DECLS_END
93
94	#define DEBUG_PCI
95
96	#define PCI_VENDOR_ID 0x00 /* 16 bits */
97	#define PCI_DEVICE_ID 0x02 /* 16 bits */
98	#define PCI_COMMAND 0x04 /* 16 bits */
99	#define PCI_COMMAND_IO 0x01 /* Enable response in I/O space */
100	#define PCI_COMMAND_MEMORY 0x02 /* Enable response in Memory space */
101	#define PCI_CLASS_DEVICE 0x0a /* Device class */
102	#define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
103	#define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
104	#define PCI_MIN_GNT 0x3e /* 8 bits */
105	#define PCI_MAX_LAT 0x3f /* 8 bits */
106
107
108	static VBOXSTRICTRC pci_data_write(PPDMDEVINS pDevIns, PDEVPCIROOT pGlobals, uint32_t addr, uint32_t u32Value, int cb)
109	{
110	LogFunc(("addr=%08x u32Value=%08x cb=%d\n", pGlobals->uConfigReg, u32Value, cb));
111
112	if (!(pGlobals->uConfigReg & (1 << 31)))
113	return VINF_SUCCESS;
114	if ((pGlobals->uConfigReg & 0x3) != 0)
115	return VINF_SUCCESS;
116
117	uint8_t const iBus = (pGlobals->uConfigReg >> 16) & 0xff;
118	uint8_t const iDevice = (pGlobals->uConfigReg >> 8) & 0xff;
119	#ifdef IN_RING3
120	uint32_t const config_addr = (pGlobals->uConfigReg & 0xfc) \| (addr & 3);
121	#endif
122	RT_UNTRUSTED_VALIDATED_FENCE(); /* paranoia */
123
124	VBOXSTRICTRC rcStrict = VINF_SUCCESS;
125	if (iBus != 0)
126	{
127	if (pGlobals->PciBus.cBridges)
128	{
129	#ifdef IN_RING3 /** @todo do lookup in R0/RC too! */
130	PPDMPCIDEV pBridgeDevice = pciR3FindBridge(&pGlobals->PciBus, iBus);
131	if (pBridgeDevice)
132	{
133	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigWrite);
134	rcStrict = pBridgeDevice->Int.s.pfnBridgeConfigWrite(pBridgeDevice->Int.s.CTX_SUFF(pDevIns), iBus,
135	iDevice, config_addr, cb, u32Value);
136	}
137	#else
138	RT_NOREF(pDevIns, addr, u32Value, cb);
139	rcStrict = VINF_IOM_R3_IOPORT_WRITE;
140	#endif
141	}
142	}
143	else
144	{
145	R3PTRTYPE(PDMPCIDEV *) pPciDev = pGlobals->PciBus.apDevices[iDevice];
146	if (pPciDev)
147	{
148	#ifdef IN_RING3
149	LogFunc(("%s: addr=%02x u32Value=%08x cb=%d\n", pPciDev->pszNameR3, config_addr, u32Value, cb));
150	rcStrict = VINF_PDM_PCI_DO_DEFAULT;
151	if (pPciDev->Int.s.pfnConfigWrite)
152	rcStrict = pPciDev->Int.s.pfnConfigWrite(pPciDev->Int.s.CTX_SUFF(pDevIns), pPciDev, config_addr, cb, u32Value);
153	if (rcStrict == VINF_PDM_PCI_DO_DEFAULT)
154	rcStrict = devpciR3CommonConfigWriteWorker(pDevIns, PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC),
155	pPciDev, config_addr, cb, u32Value);
156	#else
157	rcStrict = VINF_IOM_R3_IOPORT_WRITE;
158	#endif
159	}
160	}
161	return rcStrict;
162	}
163
164	static VBOXSTRICTRC pci_data_read(PDEVPCIROOT pGlobals, uint32_t addr, int cb, uint32_t *pu32Value)
165	{
166	*pu32Value = UINT32_MAX;
167
168	if (!(pGlobals->uConfigReg & (1 << 31)))
169	return VINF_SUCCESS;
170	if ((pGlobals->uConfigReg & 0x3) != 0)
171	return VINF_SUCCESS;
172	uint8_t const iBus = (pGlobals->uConfigReg >> 16) & 0xff;
173	uint8_t const iDevice = (pGlobals->uConfigReg >> 8) & 0xff;
174	#ifdef IN_RING3
175	uint32_t const config_addr = (pGlobals->uConfigReg & 0xfc) \| (addr & 3);
176	#endif
177	RT_UNTRUSTED_VALIDATED_FENCE();
178
179	VBOXSTRICTRC rcStrict = VINF_SUCCESS;
180	if (iBus != 0)
181	{
182	if (pGlobals->PciBus.cBridges)
183	{
184	#ifdef IN_RING3 /** @todo do lookup in R0/RC too! */
185	PPDMPCIDEV pBridgeDevice = pciR3FindBridge(&pGlobals->PciBus, iBus);
186	if (pBridgeDevice)
187	{
188	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigRead);
189	rcStrict = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->Int.s.CTX_SUFF(pDevIns),
190	iBus, iDevice, config_addr, cb, pu32Value);
191	}
192	#else
193	RT_NOREF(addr, cb);
194	rcStrict = VINF_IOM_R3_IOPORT_READ;
195	#endif
196	}
197	}
198	else
199	{
200	R3PTRTYPE(PDMPCIDEV *) pPciDev = pGlobals->PciBus.apDevices[iDevice];
201	if (pPciDev)
202	{
203	#ifdef IN_RING3
204	rcStrict = VINF_PDM_PCI_DO_DEFAULT;
205	if (pPciDev->Int.s.pfnConfigRead)
206	rcStrict = pPciDev->Int.s.pfnConfigRead(pPciDev->Int.s.CTX_SUFF(pDevIns), pPciDev, config_addr, cb, pu32Value);
207	if (rcStrict == VINF_PDM_PCI_DO_DEFAULT)
208	rcStrict = devpciR3CommonConfigReadWorker(pPciDev, config_addr, cb, pu32Value);
209	LogFunc(("%s: addr=%02x val=%08x cb=%d\n", pPciDev->pszNameR3, config_addr, *pu32Value, cb));
210	#else
211	NOREF(cb);
212	rcStrict = VINF_IOM_R3_IOPORT_READ;
213	#endif
214	}
215	}
216
217	return rcStrict;
218	}
219
220
221
222	/* return the global irq number corresponding to a given device irq
223	pin. We could also use the bus number to have a more precise
224	mapping.
225	This is the implementation note described in the PCI spec chapter 2.2.6 */
226	static inline int pci_slot_get_pirq(uint8_t uDevFn, int irq_num)
227	{
228	int slot_addend;
229	slot_addend = (uDevFn >> 3) - 1;
230	return (irq_num + slot_addend) & 3;
231	}
232
233	static inline int pci_slot_get_apic_pirq(uint8_t uDevFn, int irq_num)
234	{
235	return (irq_num + (uDevFn >> 3)) & 7;
236	}
237
238	static inline int get_pci_irq_apic_level(PDEVPCIROOT pGlobals, int irq_num)
239	{
240	return (pGlobals->auPciApicIrqLevels[irq_num] != 0);
241	}
242
243	static void apic_set_irq(PPDMDEVINS pDevIns, PDEVPCIBUS pBus, PDEVPCIBUSCC pBusCC,
244	uint8_t uDevFn, PDMPCIDEV *pPciDev, int irq_num1, int iLevel, int iAcpiIrq, uint32_t uTagSrc)
245	{
246	/* This is only allowed to be called with a pointer to the host bus. */
247	AssertMsg(pBus->iBus == 0, ("iBus=%u\n", pBus->iBus));
248	uint16_t const uBusDevFn = PCIBDF_MAKE(pBus->iBus, uDevFn);
249
250	if (iAcpiIrq == -1) {
251	int apic_irq, apic_level;
252	PDEVPCIROOT pGlobals = DEVPCIBUS_2_DEVPCIROOT(pBus);
253	int irq_num = pci_slot_get_apic_pirq(uDevFn, irq_num1);
254
255	if ((iLevel & PDM_IRQ_LEVEL_HIGH) == PDM_IRQ_LEVEL_HIGH)
256	ASMAtomicIncU32(&pGlobals->auPciApicIrqLevels[irq_num]);
257	else if ((iLevel & PDM_IRQ_LEVEL_HIGH) == PDM_IRQ_LEVEL_LOW)
258	ASMAtomicDecU32(&pGlobals->auPciApicIrqLevels[irq_num]);
259
260	apic_irq = irq_num + 0x10;
261	apic_level = get_pci_irq_apic_level(pGlobals, irq_num);
262	Log3Func(("%s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d\n",
263	R3STRING(pPciDev->pszNameR3), irq_num1, iLevel, apic_irq, apic_level, irq_num));
264	pBusCC->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pDevIns, uBusDevFn, apic_irq, apic_level, uTagSrc);
265
266	if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP) {
267	ASMAtomicDecU32(&pGlobals->auPciApicIrqLevels[irq_num]);
268	pPciDev->Int.s.uIrqPinState = PDM_IRQ_LEVEL_LOW;
269	apic_level = get_pci_irq_apic_level(pGlobals, irq_num);
270	Log3Func(("%s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d (flop)\n",
271	R3STRING(pPciDev->pszNameR3), irq_num1, iLevel, apic_irq, apic_level, irq_num));
272	pBusCC->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pDevIns, uBusDevFn, apic_irq, apic_level, uTagSrc);
273	}
274	} else {
275	Log3Func(("%s: irq_num1=%d level=%d iAcpiIrq=%d\n", R3STRING(pPciDev->pszNameR3), irq_num1, iLevel, iAcpiIrq));
276	pBusCC->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pDevIns, uBusDevFn, iAcpiIrq, iLevel, uTagSrc);
277	}
278	}
279
280	DECLINLINE(int) get_pci_irq_level(PDEVPCIROOT pGlobals, int irq_num)
281	{
282	return (pGlobals->Piix3.auPciLegacyIrqLevels[irq_num] != 0);
283	}
284
285	/**
286	* Set the IRQ for a PCI device on the host bus - shared by host bus and bridge.
287	*
288	* @param pDevIns The PDM device instance for the PCI bus.
289	* @param pGlobals Device instance of the host PCI bus.
290	* @param pBusCC Context specific data for the PCI bus.
291	* @param uDevFn The device number on the host bus which will raise the IRQ
292	* @param pPciDev The PCI device structure which raised the interrupt.
293	* @param iIrq IRQ number to set.
294	* @param iLevel IRQ level.
295	* @param uTagSrc The IRQ tag and source ID (for tracing).
296	* @remark uDevFn and pPciDev->uDevFn are not the same if the device is behind
297	* a bridge. In that case uDevFn will be the slot of the bridge which
298	* is needed to calculate the PIRQ value.
299	*/
300	static void pciSetIrqInternal(PPDMDEVINS pDevIns, PDEVPCIROOT pGlobals, PDEVPCIBUSCC pBusCC,
301	uint8_t uDevFn, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc)
302	{
303	PDEVPCIBUS pBus = &pGlobals->PciBus;
304	uint8_t *pbCfg = pDevIns->apPciDevs[1]->abConfig;
305	const bool fIsAcpiDevice = pPciDev->abConfig[2] == 0x13 && pPciDev->abConfig[3] == 0x71;
306	/* If the two configuration space bytes at 0xde, 0xad are set to 0xbe, 0xef, a back door
307	* is opened to route PCI interrupts directly to the I/O APIC and bypass the PIC.
308	* See the \_SB_.PCI0._PRT method in vbox.dsl.
309	*/
310	const bool fIsApicEnabled = pGlobals->fUseIoApic && pbCfg[0xde] == 0xbe && pbCfg[0xad] == 0xef;
311	int pic_irq, pic_level;
312
313	/* Check if the state changed. */
314	if (pPciDev->Int.s.uIrqPinState != iLevel)
315	{
316	pPciDev->Int.s.uIrqPinState = (iLevel & PDM_IRQ_LEVEL_HIGH);
317
318	/* Send interrupt to I/O APIC only. */
319	if (fIsApicEnabled)
320	{
321	if (fIsAcpiDevice)
322	/*
323	* ACPI needs special treatment since SCI is hardwired and
324	* should not be affected by PCI IRQ routing tables at the
325	* same time SCI IRQ is shared in PCI sense hence this
326	* kludge (i.e. we fetch the hardwired value from ACPIs
327	* PCI device configuration space).
328	*/
329	apic_set_irq(pDevIns, pBus, pBusCC, uDevFn, pPciDev, -1, iLevel, pPciDev->abConfig[PCI_INTERRUPT_LINE], uTagSrc);
330	else
331	apic_set_irq(pDevIns, pBus, pBusCC, uDevFn, pPciDev, iIrq, iLevel, -1, uTagSrc);
332	return;
333	}
334
335	if (fIsAcpiDevice)
336	{
337	/* As per above treat ACPI in a special way */
338	pic_irq = pPciDev->abConfig[PCI_INTERRUPT_LINE];
339	pGlobals->Piix3.iAcpiIrq = pic_irq;
340	pGlobals->Piix3.iAcpiIrqLevel = iLevel & PDM_IRQ_LEVEL_HIGH;
341	}
342	else
343	{
344	int irq_num;
345	irq_num = pci_slot_get_pirq(uDevFn, iIrq);
346
347	if (pPciDev->Int.s.uIrqPinState == PDM_IRQ_LEVEL_HIGH)
348	ASMAtomicIncU32(&pGlobals->Piix3.auPciLegacyIrqLevels[irq_num]);
349	else if (pPciDev->Int.s.uIrqPinState == PDM_IRQ_LEVEL_LOW)
350	ASMAtomicDecU32(&pGlobals->Piix3.auPciLegacyIrqLevels[irq_num]);
351
352	/* now we change the pic irq level according to the piix irq mappings */
353	pic_irq = pbCfg[0x60 + irq_num];
354	if (pic_irq >= 16)
355	{
356	if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP)
357	{
358	ASMAtomicDecU32(&pGlobals->Piix3.auPciLegacyIrqLevels[irq_num]);
359	pPciDev->Int.s.uIrqPinState = PDM_IRQ_LEVEL_LOW;
360	}
361
362	return;
363	}
364	}
365
366	/* the pic level is the logical OR of all the PCI irqs mapped to it */
367	pic_level = 0;
368	if (pic_irq == pbCfg[0x60])
369	pic_level \|= get_pci_irq_level(pGlobals, 0); /* PIRQA */
370	if (pic_irq == pbCfg[0x61])
371	pic_level \|= get_pci_irq_level(pGlobals, 1); /* PIRQB */
372	if (pic_irq == pbCfg[0x62])
373	pic_level \|= get_pci_irq_level(pGlobals, 2); /* PIRQC */
374	if (pic_irq == pbCfg[0x63])
375	pic_level \|= get_pci_irq_level(pGlobals, 3); /* PIRQD */
376	if (pic_irq == pGlobals->Piix3.iAcpiIrq)
377	pic_level \|= pGlobals->Piix3.iAcpiIrqLevel;
378
379	Log3Func(("%s: iLevel=%d iIrq=%d pic_irq=%d pic_level=%d uTagSrc=%#x\n",
380	R3STRING(pPciDev->pszNameR3), iLevel, iIrq, pic_irq, pic_level, uTagSrc));
381	pBusCC->CTX_SUFF(pPciHlp)->pfnIsaSetIrq(pDevIns, pic_irq, pic_level, uTagSrc);
382
383	/** @todo optimize pci irq flip-flop some rainy day. */
384	if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP)
385	pciSetIrqInternal(pDevIns, pGlobals, pBusCC, uDevFn, pPciDev, iIrq, PDM_IRQ_LEVEL_LOW, uTagSrc);
386	}
387	}
388
389
390	/**
391	* @interface_method_impl{PDMPCIBUSREGR3,pfnSetIrqR3}
392	*/
393	static DECLCALLBACK(void) pciSetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc)
394	{
395	PDEVPCIROOT pBus = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
396	PDEVPCIBUSCC pBusCC = PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC);
397	LogFlow(("pciSetIrq: %p %u %u %#x\n", pPciDev, iIrq, iLevel, uTagSrc));
398	pciSetIrqInternal(pDevIns, pBus, pBusCC, pPciDev->uDevFn, pPciDev, iIrq, iLevel, uTagSrc);
399	}
400
401	#ifdef IN_RING3
402
403	/**
404	* Finds a bridge on the bus which contains the destination bus.
405	*
406	* @return Pointer to the device instance data of the bus or
407	* NULL if no bridge was found.
408	* @param pBus Pointer to the bus to search on.
409	* @param iBus Destination bus number.
410	*/
411	DECLINLINE(PPDMPCIDEV) pciR3FindBridge(PDEVPCIBUS pBus, uint8_t iBus)
412	{
413	/* Search for a fitting bridge. */
414	for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
415	{
416	/*
417	* Examine secondary and subordinate bus number.
418	* If the target bus is in the range we pass the request on to the bridge.
419	*/
420	PPDMPCIDEV pBridgeTemp = pBus->papBridgesR3[iBridge];
421	AssertMsg(pBridgeTemp && pciDevIsPci2PciBridge(pBridgeTemp),
422	("Device is not a PCI bridge but on the list of PCI bridges\n"));
423
424	if ( iBus >= pBridgeTemp->abConfig[VBOX_PCI_SECONDARY_BUS]
425	&& iBus <= pBridgeTemp->abConfig[VBOX_PCI_SUBORDINATE_BUS])
426	return pBridgeTemp;
427	}
428
429	/* Nothing found. */
430	return NULL;
431	}
432
433	static void pciR3Piix3Reset(PPDMPCIDEV pPiix3PciDev)
434	{
435	uint8_t *pci_conf = pPiix3PciDev->abConfig;
436
437	pci_conf[0x04] = 0x07; /* master, memory and I/O */
438	pci_conf[0x05] = 0x00;
439	pci_conf[0x06] = 0x00;
440	pci_conf[0x07] = 0x02; /* PCI_status_devsel_medium */
441	pci_conf[0x4c] = 0x4d;
442	pci_conf[0x4e] = 0x03;
443	pci_conf[0x4f] = 0x00;
444	pci_conf[0x60] = 0x80;
445	pci_conf[0x69] = 0x02;
446	pci_conf[0x70] = 0x80;
447	pci_conf[0x76] = 0x0c;
448	pci_conf[0x77] = 0x0c;
449	pci_conf[0x78] = 0x02;
450	pci_conf[0x79] = 0x00;
451	pci_conf[0x80] = 0x00;
452	pci_conf[0x82] = 0x02; /* Get rid of the Linux guest "Enabling Passive Release" PCI quirk warning. */
453	pci_conf[0xa0] = 0x08;
454	pci_conf[0xa2] = 0x00;
455	pci_conf[0xa3] = 0x00;
456	pci_conf[0xa4] = 0x00;
457	pci_conf[0xa5] = 0x00;
458	pci_conf[0xa6] = 0x00;
459	pci_conf[0xa7] = 0x00;
460	pci_conf[0xa8] = 0x0f;
461	pci_conf[0xaa] = 0x00;
462	pci_conf[0xab] = 0x00;
463	pci_conf[0xac] = 0x00;
464	pci_conf[0xae] = 0x00;
465	}
466
467	/* host irqs corresponding to PCI irqs A-D */
468	static const uint8_t pci_irqs[4] = { 11, 10, 9, 11 }; /* bird: added const */
469
470	static void pci_bios_init_device(PPDMDEVINS pDevIns, PDEVPCIROOT pGlobals, PDEVPCIBUS pBus,
471	PPDMPCIDEV pPciDev, uint8_t cBridgeDepth, uint8_t *paBridgePositions)
472	{
473	uint32_t uPciBiosSpecialVRAM = 0xe0000000;
474	uint32_t *paddr;
475	int pin, pic_irq;
476	uint16_t devclass, vendor_id, device_id;
477
478	devclass = devpciR3GetWord(pPciDev, PCI_CLASS_DEVICE);
479	vendor_id = devpciR3GetWord(pPciDev, PCI_VENDOR_ID);
480	device_id = devpciR3GetWord(pPciDev, PCI_DEVICE_ID);
481
482	/* Check if device is present. */
483	if (vendor_id != 0xffff)
484	{
485	switch (devclass)
486	{
487	case 0x0101:
488	if ( (vendor_id == 0x8086)
489	&& (device_id == 0x7010 \|\| device_id == 0x7111 \|\| device_id == 0x269e))
490	{
491	/* PIIX3, PIIX4 or ICH6 IDE */
492	devpciR3SetWord(pDevIns, pPciDev, 0x40, 0x8011); /* enable IDE0 + fast timing */
493	devpciR3SetWord(pDevIns, pPciDev, 0x42, 0x8011); /* enable IDE1 + fast timing */
494	goto default_map;
495	}
496	else
497	{
498	/* IDE: we map it as in ISA mode */
499	devpciR3BiosInitSetRegionAddress(pDevIns, pBus, pPciDev, 0, 0x1f0);
500	devpciR3BiosInitSetRegionAddress(pDevIns, pBus, pPciDev, 1, 0x3f4);
501	devpciR3BiosInitSetRegionAddress(pDevIns, pBus, pPciDev, 2, 0x170);
502	devpciR3BiosInitSetRegionAddress(pDevIns, pBus, pPciDev, 3, 0x374);
503	devpciR3SetWord(pDevIns, pPciDev, PCI_COMMAND,
504	devpciR3GetWord(pPciDev, PCI_COMMAND)
505	\| PCI_COMMAND_IOACCESS);
506	}
507	break;
508	case 0x0800:
509	/* PIC */
510	vendor_id = devpciR3GetWord(pPciDev, PCI_VENDOR_ID);
511	device_id = devpciR3GetWord(pPciDev, PCI_DEVICE_ID);
512	if (vendor_id == 0x1014)
513	{
514	/* IBM */
515	if (device_id == 0x0046 \|\| device_id == 0xFFFF)
516	{
517	/* MPIC & MPIC2 */
518	devpciR3BiosInitSetRegionAddress(pDevIns, pBus, pPciDev, 0, 0x80800000 + 0x00040000);
519	devpciR3SetWord(pDevIns, pPciDev, PCI_COMMAND,
520	devpciR3GetWord(pPciDev, PCI_COMMAND)
521	\| PCI_COMMAND_MEMACCESS);
522	}
523	}
524	break;
525	case 0xff00:
526	if ( (vendor_id == 0x0106b)
527	&& (device_id == 0x0017 \|\| device_id == 0x0022))
528	{
529	/* macio bridge */
530	devpciR3BiosInitSetRegionAddress(pDevIns, pBus, pPciDev, 0, 0x80800000);
531	devpciR3SetWord(pDevIns, pPciDev, PCI_COMMAND,
532	devpciR3GetWord(pPciDev, PCI_COMMAND)
533	\| PCI_COMMAND_MEMACCESS);
534	}
535	break;
536	case 0x0604:
537	{
538	/* Init PCI-to-PCI bridge. */
539	devpciR3SetByte(pDevIns, pPciDev, VBOX_PCI_PRIMARY_BUS, pBus->iBus);
540
541	AssertMsg(pGlobals->uPciBiosBus < 255, ("Too many bridges on the bus\n"));
542	pGlobals->uPciBiosBus++;
543	devpciR3SetByte(pDevIns, pPciDev, VBOX_PCI_SECONDARY_BUS, pGlobals->uPciBiosBus);
544	devpciR3SetByte(pDevIns, pPciDev, VBOX_PCI_SUBORDINATE_BUS, 0xff); /* Temporary until we know how many other bridges are behind this one. */
545
546	/* Add position of this bridge into the array. */
547	paBridgePositions[cBridgeDepth+1] = (pPciDev->uDevFn >> 3);
548
549	/*
550	* The I/O range for the bridge must be aligned to a 4KB boundary.
551	* This does not change anything really as the access to the device is not going
552	* through the bridge but we want to be compliant to the spec.
553	*/
554	if ((pGlobals->uPciBiosIo % _4K) != 0)
555	pGlobals->uPciBiosIo = RT_ALIGN_32(pGlobals->uPciBiosIo, _4K);
556	LogFunc(("Aligned I/O start address. New address %#x\n", pGlobals->uPciBiosIo));
557	devpciR3SetByte(pDevIns, pPciDev, VBOX_PCI_IO_BASE, (pGlobals->uPciBiosIo >> 8) & 0xf0);
558
559	/* The MMIO range for the bridge must be aligned to a 1MB boundary. */
560	if ((pGlobals->uPciBiosMmio % _1M) != 0)
561	pGlobals->uPciBiosMmio = RT_ALIGN_32(pGlobals->uPciBiosMmio, _1M);
562	LogFunc(("Aligned MMIO start address. New address %#x\n", pGlobals->uPciBiosMmio));
563	devpciR3SetWord(pDevIns, pPciDev, VBOX_PCI_MEMORY_BASE, (pGlobals->uPciBiosMmio >> 16) & UINT32_C(0xffff0));
564
565	/* Save values to compare later to. */
566	uint32_t u32IoAddressBase = pGlobals->uPciBiosIo;
567	uint32_t u32MMIOAddressBase = pGlobals->uPciBiosMmio;
568
569	/* Init devices behind the bridge and possibly other bridges as well. */
570	PDEVPCIBUS pChildBus = PDMINS_2_DATA(pPciDev->Int.s.CTX_SUFF(pDevIns), PDEVPCIBUS);
571	for (uint32_t uDevFn = 0; uDevFn < RT_ELEMENTS(pChildBus->apDevices); uDevFn++)
572	{
573	PPDMPCIDEV pChildPciDev = pChildBus->apDevices[uDevFn];
574	if (pChildPciDev)
575	pci_bios_init_device(pDevIns, pGlobals, pChildBus, pChildPciDev, cBridgeDepth + 1, paBridgePositions);
576	}
577
578	/* The number of bridges behind the this one is now available. */
579	devpciR3SetByte(pDevIns, pPciDev, VBOX_PCI_SUBORDINATE_BUS, pGlobals->uPciBiosBus);
580
581	/*
582	* Set I/O limit register. If there is no device with I/O space behind the bridge
583	* we set a lower value than in the base register.
584	* The result with a real bridge is that no I/O transactions are passed to the secondary
585	* interface. Again this doesn't really matter here but we want to be compliant to the spec.
586	*/
587	if ((u32IoAddressBase != pGlobals->uPciBiosIo) && ((pGlobals->uPciBiosIo % _4K) != 0))
588	{
589	/* The upper boundary must be one byte less than a 4KB boundary. */
590	pGlobals->uPciBiosIo = RT_ALIGN_32(pGlobals->uPciBiosIo, _4K);
591	}
592	devpciR3SetByte(pDevIns, pPciDev, VBOX_PCI_IO_LIMIT, ((pGlobals->uPciBiosIo >> 8) & 0xf0) - 1);
593
594	/* Same with the MMIO limit register but with 1MB boundary here. */
595	if ((u32MMIOAddressBase != pGlobals->uPciBiosMmio) && ((pGlobals->uPciBiosMmio % _1M) != 0))
596	{
597	/* The upper boundary must be one byte less than a 1MB boundary. */
598	pGlobals->uPciBiosMmio = RT_ALIGN_32(pGlobals->uPciBiosMmio, _1M);
599	}
600	devpciR3SetWord(pDevIns, pPciDev, VBOX_PCI_MEMORY_LIMIT, ((pGlobals->uPciBiosMmio >> 16) & UINT32_C(0xfff0)) - 1);
601
602	/*
603	* Set the prefetch base and limit registers. We currently have no device with a prefetchable region
604	* which may be behind a bridge. That's why it is unconditionally disabled here atm by writing a higher value into
605	* the base register than in the limit register.
606	*/
607	devpciR3SetWord(pDevIns, pPciDev, VBOX_PCI_PREF_MEMORY_BASE, 0xfff0);
608	devpciR3SetWord(pDevIns, pPciDev, VBOX_PCI_PREF_MEMORY_LIMIT, 0x0);
609	devpciR3SetDWord(pDevIns, pPciDev, VBOX_PCI_PREF_BASE_UPPER32, 0x00);
610	devpciR3SetDWord(pDevIns, pPciDev, VBOX_PCI_PREF_LIMIT_UPPER32, 0x00);
611	break;
612	}
613	default:
614	default_map:
615	{
616	/* default memory mappings */
617	bool fActiveMemRegion = false;
618	bool fActiveIORegion = false;
619	/*
620	* PCI_NUM_REGIONS is 7 because of the rom region but there are only 6 base address register defined by the PCI spec.
621	* Leaving only PCI_NUM_REGIONS would cause reading another and enabling a memory region which does not exist.
622	*/
623	for (unsigned i = 0; i < (PCI_NUM_REGIONS-1); i++)
624	{
625	uint32_t u32Size;
626	uint8_t u8ResourceType;
627	uint32_t u32Address = 0x10 + i * 4;
628
629	/* Calculate size. */
630	u8ResourceType = devpciR3GetByte(pPciDev, u32Address);
631	devpciR3SetDWord(pDevIns, pPciDev, u32Address, UINT32_C(0xffffffff));
632	u32Size = devpciR3GetDWord(pPciDev, u32Address);
633	bool fIsPio = ((u8ResourceType & PCI_COMMAND_IOACCESS) == PCI_COMMAND_IOACCESS);
634	/* Clear resource information depending on resource type. */
635	if (fIsPio) /* I/O */
636	u32Size &= ~(0x01);
637	else /* MMIO */
638	u32Size &= ~(0x0f);
639
640	/*
641	* Invert all bits and add 1 to get size of the region.
642	* (From PCI implementation note)
643	*/
644	if (fIsPio && (u32Size & UINT32_C(0xffff0000)) == 0)
645	u32Size = (~(u32Size \| UINT32_C(0xffff0000))) + 1;
646	else
647	u32Size = (~u32Size) + 1;
648
649	Log2Func(("Size of region %u for device %d on bus %d is %u\n", i, pPciDev->uDevFn, pBus->iBus, u32Size));
650
651	if (u32Size)
652	{
653	if (fIsPio)
654	paddr = &pGlobals->uPciBiosIo;
655	else
656	{
657	paddr = &pGlobals->uPciBiosMmio;
658	bool fPrefetch = (u8ResourceType & ((uint8_t)(PCI_ADDRESS_SPACE_MEM_PREFETCH \| PCI_ADDRESS_SPACE_IO)))
659	== PCI_ADDRESS_SPACE_MEM_PREFETCH;
660
661	if (devclass == 0x0300 && (vendor_id == 0x80ee \|\| vendor_id == 0x15ad) && fPrefetch)
662	{
663	/* VGA: map frame buffer to default Bochs VBE address */
664	paddr = &uPciBiosSpecialVRAM;
665	/*
666	* For VBoxVGA must enable I/O decoding, because legacy
667	* VGA I/O ports are implicitly decoded by a VGA class
668	* device. Not needed for VMSVGA or VBoxSVGA, because
669	* they have an explicit I/O BAR.
670	*/
671	fActiveIORegion = true;
672	}
673	}
674	uint32_t uNew = *paddr;
675	uNew = (uNew + u32Size - 1) & ~(u32Size - 1);
676	if (fIsPio)
677	uNew &= UINT32_C(0xffff);
678	/* Unconditionally exclude I/O-APIC/HPET/ROM. Pessimistic, but better than causing a mess. */
679	if (!uNew \|\| (uNew <= UINT32_C(0xffffffff) && uNew + u32Size - 1 >= UINT32_C(0xfec00000)))
680	{
681	LogRel(("PCI: no space left for BAR%u of device %u/%u/%u (vendor=%#06x device=%#06x)\n",
682	i, pBus->iBus, pPciDev->uDevFn >> 3, pPciDev->uDevFn & 7, vendor_id, device_id)); /** @todo make this a VM start failure later. */
683	/* Undo the mapping mess caused by the size probing. */
684	devpciR3SetDWord(pDevIns, pPciDev, u32Address, UINT32_C(0));
685	}
686	else
687	{
688	LogFunc(("Start address of %s region %u is %#x\n", (fIsPio ? "I/O" : "MMIO"), i, uNew));
689	devpciR3BiosInitSetRegionAddress(pDevIns, pBus, pPciDev, i, uNew);
690	if (fIsPio)
691	fActiveIORegion = true;
692	else
693	fActiveMemRegion = true;
694	*paddr = uNew + u32Size;
695	Log2Func(("New address is %#x\n", *paddr));
696	}
697	}
698	}
699
700	/* Update the command word appropriately. */
701	devpciR3SetWord(pDevIns, pPciDev, PCI_COMMAND,
702	devpciR3GetWord(pPciDev, PCI_COMMAND)
703	\| (fActiveMemRegion ? PCI_COMMAND_MEMACCESS : 0)
704	\| (fActiveIORegion ? PCI_COMMAND_IOACCESS : 0));
705
706	break;
707	}
708	}
709
710	/* map the interrupt */
711	pin = devpciR3GetByte(pPciDev, PCI_INTERRUPT_PIN);
712	if (pin != 0)
713	{
714	uint8_t uBridgeDevFn = pPciDev->uDevFn;
715	pin--;
716
717	/* We need to go up to the host bus to see which irq this device will assert there. */
718	while (cBridgeDepth != 0)
719	{
720	/* Get the pin the device would assert on the bridge. */
721	pin = ((uBridgeDevFn >> 3) + pin) & 3;
722	uBridgeDevFn = paBridgePositions[cBridgeDepth];
723	cBridgeDepth--;
724	}
725
726	pin = pci_slot_get_pirq(pPciDev->uDevFn, pin);
727	pic_irq = pci_irqs[pin];
728	devpciR3SetByte(pDevIns, pPciDev, PCI_INTERRUPT_LINE, pic_irq);
729	}
730	}
731	}
732
733	/**
734	* Worker for Fake PCI BIOS config, triggered by magic port access by BIOS.
735	*
736	* @returns VBox status code.
737	*
738	* @param pDevIns i440FX device instance.
739	*/
740	static int pciR3FakePCIBIOS(PPDMDEVINS pDevIns)
741	{
742	uint8_t elcr[2] = {0, 0};
743	PDEVPCIROOT pGlobals = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
744	PVM pVM = PDMDevHlpGetVM(pDevIns); Assert(pVM);
745	PVMCPU pVCpu = PDMDevHlpGetVMCPU(pDevIns); Assert(pVM);
746	uint32_t const cbBelow4GB = MMR3PhysGetRamSizeBelow4GB(pVM);
747	uint64_t const cbAbove4GB = MMR3PhysGetRamSizeAbove4GB(pVM);
748	RT_NOREF(cbBelow4GB, cbAbove4GB);
749
750	LogRel(("PCI: Setting up resources and interrupts\n"));
751
752	/*
753	* Set the start addresses.
754	*/
755	pGlobals->uPciBiosBus = 0;
756	pGlobals->uPciBiosIo = 0xd000;
757	pGlobals->uPciBiosMmio = UINT32_C(0xf0000000);
758
759	/*
760	* Activate IRQ mappings.
761	*/
762	PPDMPCIDEV pPIIX3 = pDevIns->apPciDevs[1];
763	for (unsigned i = 0; i < 4; i++)
764	{
765	uint8_t irq = pci_irqs[i];
766	/* Set to trigger level. */
767	elcr[irq >> 3] \|= (1 << (irq & 7));
768	/* Activate irq remapping in PIIX3. */
769	devpciR3SetByte(pDevIns, pPIIX3, 0x60 + i, irq);
770	}
771
772	/* Tell to the PIC. */
773	VBOXSTRICTRC rcStrict = IOMIOPortWrite(pVM, pVCpu, 0x4d0, elcr[0], sizeof(uint8_t));
774	if (rcStrict == VINF_SUCCESS)
775	rcStrict = IOMIOPortWrite(pVM, pVCpu, 0x4d1, elcr[1], sizeof(uint8_t));
776	if (rcStrict != VINF_SUCCESS)
777	{
778	AssertMsgFailed(("Writing to PIC failed! rcStrict=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
779	return RT_SUCCESS(rcStrict) ? VERR_INTERNAL_ERROR : VBOXSTRICTRC_VAL(rcStrict);
780	}
781
782	/*
783	* Init the devices.
784	*/
785	PDEVPCIBUS pBus = &pGlobals->PciBus;
786	for (uint32_t uDevFn = 0; uDevFn < RT_ELEMENTS(pBus->apDevices); uDevFn++)
787	{
788	PPDMPCIDEV pPciDev = pBus->apDevices[uDevFn];
789	if (pPciDev)
790	{
791	Log2(("PCI: Initializing device %d (%#x)\n", uDevFn, 0x80000000 \| (uDevFn << 8)));
792	uint8_t aBridgePositions[256];
793	RT_ZERO(aBridgePositions);
794	pci_bios_init_device(pDevIns, pGlobals, pBus, pPciDev, 0, aBridgePositions);
795	}
796	}
797
798	return VINF_SUCCESS;
799	}
800
801	#endif /* IN_RING3 */
802
803
804	/* -=-=-=-=-=- I/O ports -=-=-=-=-=- */
805
806	/**
807	* @callback_method_impl{FNIOMIOPORTNEWOUT, PCI address}
808	*/
809	static DECLCALLBACK(VBOXSTRICTRC)
810	pciIOPortAddressWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
811	{
812	LogFunc(("offPort=%#x u32=%#x cb=%d\n", offPort, u32, cb));
813	Assert(offPort == 0); RT_NOREF2(offPort, pvUser);
814	if (cb == 4)
815	{
816	PDEVPCIROOT pThis = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
817	PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_WRITE);
818	pThis->uConfigReg = u32 & ~3; /* Bits 0-1 are reserved and we silently clear them */
819	PCI_UNLOCK(pDevIns);
820	}
821	/* else: 440FX does "pass through to the bus" for other writes, what ever that means.
822	* Linux probes for cmd640 using byte writes/reads during ide init. We'll just ignore it. */
823	return VINF_SUCCESS;
824	}
825
826
827	/**
828	* @callback_method_impl{FNIOMIOPORTNEWIN, PCI address}
829	*/
830	static DECLCALLBACK(VBOXSTRICTRC)
831	pciIOPortAddressRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT offPort, uint32_t pu32, unsigned cb)
832	{
833	Assert(offPort == 0); RT_NOREF2(offPort, pvUser);
834	if (cb == 4)
835	{
836	PDEVPCIROOT pThis = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
837	PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_READ);
838	*pu32 = pThis->uConfigReg;
839	PCI_UNLOCK(pDevIns);
840	LogFunc(("offPort=%#x cb=%d -> %#x\n", offPort, cb, *pu32));
841	return VINF_SUCCESS;
842	}
843	/* else: 440FX does "pass through to the bus" for other writes, what ever that means.
844	* Linux probes for cmd640 using byte writes/reads during ide init. We'll just ignore it. */
845	LogFunc(("offPort=%#x cb=%d VERR_IOM_IOPORT_UNUSED\n", offPort, cb));
846	return VERR_IOM_IOPORT_UNUSED;
847	}
848
849
850	/**
851	* @callback_method_impl{FNIOMIOPORTNEWOUT, PCI data}
852	*/
853	static DECLCALLBACK(VBOXSTRICTRC)
854	pciIOPortDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
855	{
856	LogFunc(("offPort=%#x u32=%#x cb=%d\n", offPort, u32, cb));
857	Assert(offPort < 4); NOREF(pvUser);
858	VBOXSTRICTRC rcStrict = VINF_SUCCESS;
859	if (!(offPort % cb))
860	{
861	PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_WRITE);
862	rcStrict = pci_data_write(pDevIns, PDMINS_2_DATA(pDevIns, PDEVPCIROOT), offPort, u32, cb);
863	PCI_UNLOCK(pDevIns);
864	}
865	else
866	AssertMsgFailed(("Write to port %#x u32=%#x cb=%d\n", offPort, u32, cb));
867	return rcStrict;
868	}
869
870
871	/**
872	* @callback_method_impl{FNIOMIOPORTNEWIN, PCI data}
873	*/
874	static DECLCALLBACK(VBOXSTRICTRC)
875	pciIOPortDataRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT offPort, uint32_t pu32, unsigned cb)
876	{
877	Assert(offPort < 4); NOREF(pvUser);
878	if (!(offPort % cb))
879	{
880	PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_READ);
881	VBOXSTRICTRC rcStrict = pci_data_read(PDMINS_2_DATA(pDevIns, PDEVPCIROOT), offPort, cb, pu32);
882	PCI_UNLOCK(pDevIns);
883	LogFunc(("offPort=%#x cb=%#x -> %#x (%Rrc)\n", offPort, cb, *pu32, VBOXSTRICTRC_VAL(rcStrict)));
884	return rcStrict;
885	}
886	AssertMsgFailed(("Read from port %#x cb=%d\n", offPort, cb));
887	return VERR_IOM_IOPORT_UNUSED;
888	}
889
890	#ifdef IN_RING3
891
892	/**
893	* @callback_method_impl{FNIOMIOPORTNEWOUT, PCI data}
894	*/
895	static DECLCALLBACK(VBOXSTRICTRC)
896	pciR3IOPortMagicPCIWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
897	{
898	Assert(offPort == 0); RT_NOREF2(pvUser, offPort);
899	LogFunc(("offPort=%#x u32=%#x cb=%d\n", offPort, u32, cb));
900	if (cb == 4)
901	{
902	if (u32 == UINT32_C(19200509)) // Richard Adams - Note! In decimal rather hex.
903	{
904	int rc = pciR3FakePCIBIOS(pDevIns);
905	AssertRC(rc);
906	}
907	}
908
909	return VINF_SUCCESS;
910	}
911
912	/**
913	* @callback_method_impl{FNIOMIOPORTNEWIN, PCI data}
914	*/
915	static DECLCALLBACK(VBOXSTRICTRC)
916	pciR3IOPortMagicPCIRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT offPort, uint32_t pu32, unsigned cb)
917	{
918	Assert(offPort == 0); RT_NOREF5(pDevIns, pvUser, offPort, pu32, cb);
919	LogFunc(("offPort=%#x cb=%d VERR_IOM_IOPORT_UNUSED\n", offPort, cb));
920	return VERR_IOM_IOPORT_UNUSED;
921	}
922
923
924	/* -=-=-=-=-=- Saved state -=-=-=-=-=- */
925
926	/**
927	* Common worker for pciR3SaveExec and pcibridgeR3SaveExec.
928	*
929	* @returns VBox status code.
930	* @param pHlp The device helpers.
931	* @param pBus The bus to save.
932	* @param pSSM The saved state handle.
933	*/
934	static int pciR3CommonSaveExec(PCPDMDEVHLPR3 pHlp, PDEVPCIBUS pBus, PSSMHANDLE pSSM)
935	{
936	/*
937	* Iterate thru all the devices.
938	*/
939	for (uint32_t uDevFn = 0; uDevFn < RT_ELEMENTS(pBus->apDevices); uDevFn++)
940	{
941	PPDMPCIDEV pDev = pBus->apDevices[uDevFn];
942	if (pDev)
943	{
944	pHlp->pfnSSMPutU32(pSSM, uDevFn);
945	pHlp->pfnSSMPutMem(pSSM, pDev->abConfig, 256); /* Only save 256 bytes here! */
946
947	pHlp->pfnSSMPutS32(pSSM, pDev->Int.s.uIrqPinState);
948
949	/* Save the type an size of all the regions. */
950	for (uint32_t iRegion = 0; iRegion < VBOX_PCI_NUM_REGIONS; iRegion++)
951	{
952	pHlp->pfnSSMPutU8(pSSM, pDev->Int.s.aIORegions[iRegion].type);
953	pHlp->pfnSSMPutU64(pSSM, pDev->Int.s.aIORegions[iRegion].size);
954	}
955	}
956	}
957	return pHlp->pfnSSMPutU32(pSSM, UINT32_MAX); /* terminator */
958	}
959
960
961	/**
962	* @callback_method_impl{FNSSMDEVSAVEEXEC}
963	*/
964	static DECLCALLBACK(int) pciR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
965	{
966	PDEVPCIROOT pThis = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
967	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
968
969	/*
970	* Bus state data.
971	*/
972	pHlp->pfnSSMPutU32(pSSM, pThis->uConfigReg);
973	pHlp->pfnSSMPutBool(pSSM, pThis->fUseIoApic);
974
975	/*
976	* Save IRQ states.
977	*/
978	for (unsigned i = 0; i < RT_ELEMENTS(pThis->Piix3.auPciLegacyIrqLevels); i++)
979	pHlp->pfnSSMPutU32(pSSM, pThis->Piix3.auPciLegacyIrqLevels[i]);
980	for (unsigned i = 0; i < RT_ELEMENTS(pThis->auPciApicIrqLevels); i++)
981	pHlp->pfnSSMPutU32(pSSM, pThis->auPciApicIrqLevels[i]);
982
983	pHlp->pfnSSMPutU32(pSSM, pThis->Piix3.iAcpiIrqLevel);
984	pHlp->pfnSSMPutS32(pSSM, pThis->Piix3.iAcpiIrq);
985
986	pHlp->pfnSSMPutU32(pSSM, UINT32_MAX); /* separator */
987
988	/*
989	* Join paths with pcibridgeR3SaveExec.
990	*/
991	return pciR3CommonSaveExec(pHlp, &pThis->PciBus, pSSM);
992	}
993
994
995	/**
996	* Common worker for pciR3LoadExec and pcibridgeR3LoadExec.
997	*
998	* @returns VBox status code.
999	* @param pDevIns The device instance.
1000	* @param pBus The bus which data is being loaded.
1001	* @param pSSM The saved state handle.
1002	* @param uVersion The data version.
1003	* @param uPass The pass.
1004	*/
1005	static int pciR3CommonLoadExec(PPDMDEVINS pDevIns, PDEVPCIBUS pBus, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1006	{
1007	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
1008	uint32_t u32;
1009	int rc;
1010
1011	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
1012
1013	/*
1014	* Iterate thru all the devices and write 0 to the COMMAND register so
1015	* that all the memory is unmapped before we start restoring the saved
1016	* mapping locations.
1017	*
1018	* The register value is restored afterwards so we can do proper
1019	* LogRels in devpciR3CommonRestoreConfig.
1020	*/
1021	for (uint32_t uDevFn = 0; uDevFn < RT_ELEMENTS(pBus->apDevices); uDevFn++)
1022	{
1023	PPDMPCIDEV pDev = pBus->apDevices[uDevFn];
1024	if (pDev)
1025	{
1026	uint16_t u16 = PCIDevGetCommand(pDev);
1027	devpciR3SetCfg(pDevIns, pDev, VBOX_PCI_COMMAND, 0 /u32Value/, 2 /cb/);
1028	PCIDevSetCommand(pDev, u16);
1029	Assert(PCIDevGetCommand(pDev) == u16);
1030	}
1031	}
1032
1033	/*
1034	* Iterate all the devices.
1035	*/
1036	for (uint32_t uDevFn = 0;; uDevFn++)
1037	{
1038	/* index / terminator */
1039	rc = pHlp->pfnSSMGetU32(pSSM, &u32);
1040	if (RT_FAILURE(rc))
1041	return rc;
1042	if (u32 == UINT32_MAX)
1043	break;
1044	if ( u32 >= RT_ELEMENTS(pBus->apDevices)
1045	\|\| u32 < uDevFn)
1046	{
1047	AssertMsgFailed(("u32=%#x uDevFn=%#x\n", u32, uDevFn));
1048	return rc;
1049	}
1050
1051	/* skip forward to the device checking that no new devices are present. */
1052	for (; uDevFn < u32; uDevFn++)
1053	{
1054	if (pBus->apDevices[uDevFn])
1055	{
1056	LogRel(("PCI: New device in slot %#x, %s (vendor=%#06x device=%#06x)\n", uDevFn, pBus->apDevices[uDevFn]->pszNameR3,
1057	PCIDevGetVendorId(pBus->apDevices[uDevFn]), PCIDevGetDeviceId(pBus->apDevices[uDevFn])));
1058	if (pHlp->pfnSSMHandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT)
1059	return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS, N_("New device in slot %#x, %s (vendor=%#06x device=%#06x)"),
1060	uDevFn, pBus->apDevices[uDevFn]->pszNameR3, PCIDevGetVendorId(pBus->apDevices[uDevFn]), PCIDevGetDeviceId(pBus->apDevices[uDevFn]));
1061	}
1062	}
1063
1064	/* get the data */
1065	union
1066	{
1067	PDMPCIDEV DevTmp;
1068	uint8_t abDevTmpPadding[RT_UOFFSETOF(PDMPCIDEV, abMsixState)];
1069	} u;
1070	RT_ZERO(u.DevTmp);
1071	u.DevTmp.Int.s.uIrqPinState = ~0; /* Invalid value in case we have an older saved state to force a state change in pciSetIrq. */
1072	pHlp->pfnSSMGetMem(pSSM, u.DevTmp.abConfig, 256);
1073	if (uVersion < VBOX_PCI_SAVED_STATE_VERSION_IRQ_STATES)
1074	{
1075	int32_t i32Temp;
1076	/* Irq value not needed anymore. */
1077	rc = pHlp->pfnSSMGetS32(pSSM, &i32Temp);
1078	if (RT_FAILURE(rc))
1079	return rc;
1080	}
1081	else
1082	{
1083	rc = pHlp->pfnSSMGetS32(pSSM, &u.DevTmp.Int.s.uIrqPinState);
1084	if (RT_FAILURE(rc))
1085	return rc;
1086	}
1087
1088	/* Load the region types and sizes. */
1089	if (uVersion >= VBOX_PCI_SAVED_STATE_VERSION_REGION_SIZES)
1090	{
1091	for (uint32_t iRegion = 0; iRegion < VBOX_PCI_NUM_REGIONS; iRegion++)
1092	{
1093	pHlp->pfnSSMGetU8(pSSM, &u.DevTmp.Int.s.aIORegions[iRegion].type);
1094	rc = pHlp->pfnSSMGetU64(pSSM, &u.DevTmp.Int.s.aIORegions[iRegion].size);
1095	AssertLogRelRCReturn(rc, rc);
1096	}
1097	}
1098
1099	/* check that it's still around. */
1100	PPDMPCIDEV pDev = pBus->apDevices[uDevFn];
1101	if (!pDev)
1102	{
1103	LogRel(("PCI: Device in slot %#x has been removed! vendor=%#06x device=%#06x\n", uDevFn,
1104	PCIDevGetVendorId(&u.DevTmp), PCIDevGetDeviceId(&u.DevTmp)));
1105	if (pHlp->pfnSSMHandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT)
1106	return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS, N_("Device in slot %#x has been removed! vendor=%#06x device=%#06x"),
1107	uDevFn, PCIDevGetVendorId(&u.DevTmp), PCIDevGetDeviceId(&u.DevTmp));
1108	continue;
1109	}
1110
1111	/* match the vendor id assuming that this will never be changed. */
1112	if ( u.DevTmp.abConfig[0] != pDev->abConfig[0]
1113	\|\| u.DevTmp.abConfig[1] != pDev->abConfig[1])
1114	return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS,
1115	N_("Device in slot %#x (%s) vendor id mismatch! saved=%.4Rhxs current=%.4Rhxs"),
1116	uDevFn, pDev->pszNameR3, u.DevTmp.abConfig, pDev->abConfig);
1117
1118	/* commit the loaded device config. */
1119	rc = devpciR3CommonRestoreRegions(pSSM, pDev, u.DevTmp.Int.s.aIORegions,
1120	uVersion >= VBOX_PCI_SAVED_STATE_VERSION_REGION_SIZES);
1121	if (RT_FAILURE(rc))
1122	break;
1123	devpciR3CommonRestoreConfig(pDevIns, pDev, &u.DevTmp.abConfig[0]);
1124
1125	pDev->Int.s.uIrqPinState = u.DevTmp.Int.s.uIrqPinState;
1126	}
1127
1128	return VINF_SUCCESS;
1129	}
1130
1131
1132	/**
1133	* @callback_method_impl{FNSSMDEVLOADEXEC}
1134	*/
1135	static DECLCALLBACK(int) pciR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1136	{
1137	PDEVPCIROOT pThis = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
1138	PDEVPCIBUS pBus = &pThis->PciBus;
1139	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
1140	uint32_t u32;
1141	int rc;
1142
1143	/*
1144	* Check the version.
1145	*/
1146	if (uVersion > VBOX_PCI_SAVED_STATE_VERSION)
1147	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1148	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
1149
1150	/*
1151	* Bus state data.
1152	*/
1153	pHlp->pfnSSMGetU32(pSSM, &pThis->uConfigReg);
1154	if (uVersion >= VBOX_PCI_SAVED_STATE_VERSION_USE_IO_APIC)
1155	pHlp->pfnSSMGetBool(pSSM, &pThis->fUseIoApic);
1156
1157	/* Load IRQ states. */
1158	if (uVersion >= VBOX_PCI_SAVED_STATE_VERSION_IRQ_STATES)
1159	{
1160	for (uint8_t i = 0; i < RT_ELEMENTS(pThis->Piix3.auPciLegacyIrqLevels); i++)
1161	pHlp->pfnSSMGetU32V(pSSM, &pThis->Piix3.auPciLegacyIrqLevels[i]);
1162	for (uint8_t i = 0; i < RT_ELEMENTS(pThis->auPciApicIrqLevels); i++)
1163	pHlp->pfnSSMGetU32V(pSSM, &pThis->auPciApicIrqLevels[i]);
1164
1165	pHlp->pfnSSMGetU32(pSSM, &pThis->Piix3.iAcpiIrqLevel);
1166	pHlp->pfnSSMGetS32(pSSM, &pThis->Piix3.iAcpiIrq);
1167	}
1168
1169	/* separator */
1170	rc = pHlp->pfnSSMGetU32(pSSM, &u32);
1171	if (RT_FAILURE(rc))
1172	return rc;
1173	if (u32 != UINT32_MAX)
1174	AssertMsgFailedReturn(("u32=%#x\n", u32), rc);
1175
1176	/*
1177	* The devices.
1178	*/
1179	return pciR3CommonLoadExec(pDevIns, pBus, pSSM, uVersion, uPass);
1180	}
1181
1182
1183	/* -=-=-=-=-=- PCI Bus Interface Methods (PDMPCIBUSREG) -=-=-=-=-=- */
1184
1185
1186	/* -=-=-=-=-=- Debug Info Handlers -=-=-=-=-=- */
1187
1188	/**
1189	* @callback_method_impl{FNDBGFHANDLERDEV}
1190	*/
1191	static DECLCALLBACK(void) pciR3IrqRouteInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
1192	{
1193	PPDMPCIDEV pPIIX3 = pDevIns->apPciDevs[1];
1194	NOREF(pszArgs);
1195
1196	uint16_t router = pPIIX3->uDevFn;
1197	pHlp->pfnPrintf(pHlp, "PCI interrupt router at: %02X:%02X:%X\n",
1198	router >> 8, (router >> 3) & 0x1f, router & 0x7);
1199
1200	for (int i = 0; i < 4; ++i)
1201	{
1202	uint8_t irq_map = devpciR3GetByte(pPIIX3, 0x60 + i);
1203	if (irq_map & 0x80)
1204	pHlp->pfnPrintf(pHlp, "PIRQ%c disabled\n", 'A' + i);
1205	else
1206	pHlp->pfnPrintf(pHlp, "PIRQ%c -> IRQ%d\n", 'A' + i, irq_map & 0xf);
1207	}
1208	}
1209
1210	/**
1211	* @callback_method_impl{FNDBGFHANDLERDEV, 'pirq'}
1212	*/
1213	DECLCALLBACK(void) devpciR3InfoPIRQ(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
1214	{
1215	PDEVPCIROOT pGlobals = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
1216	NOREF(pszArgs);
1217
1218	pHlp->pfnPrintf(pHlp, "PCI IRQ levels:\n");
1219	for (int i = 0; i < DEVPCI_LEGACY_IRQ_PINS; ++i)
1220	pHlp->pfnPrintf(pHlp, " IRQ%c: %u\n", 'A' + i, pGlobals->Piix3.auPciLegacyIrqLevels[i]);
1221	}
1222
1223
1224	/* -=-=-=-=-=- PDMDEVREG -=-=-=-=-=- */
1225
1226	/**
1227	* @interface_method_impl{PDMDEVREG,pfnReset}
1228	*/
1229	static DECLCALLBACK(void) pciR3Reset(PPDMDEVINS pDevIns)
1230	{
1231	PDEVPCIROOT pGlobals = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
1232	PDEVPCIBUS pBus = &pGlobals->PciBus;
1233
1234	/* PCI-specific reset for each device. */
1235	for (uint32_t uDevFn = 0; uDevFn < RT_ELEMENTS(pBus->apDevices); uDevFn++)
1236	{
1237	if (pBus->apDevices[uDevFn])
1238	devpciR3ResetDevice(pDevIns, pBus->apDevices[uDevFn]);
1239	}
1240
1241	pciR3Piix3Reset(pDevIns->apPciDevs[1]);
1242	}
1243
1244
1245	/**
1246	* @interface_method_impl{PDMDEVREG,pfnDestruct}
1247	*/
1248	static DECLCALLBACK(int) pciR3Destruct(PPDMDEVINS pDevIns)
1249	{
1250	PDEVPCIROOT pGlobals = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
1251	if (pGlobals->PciBus.papBridgesR3)
1252	{
1253	PDMDevHlpMMHeapFree(pDevIns, pGlobals->PciBus.papBridgesR3);
1254	pGlobals->PciBus.papBridgesR3 = NULL;
1255	}
1256	return VINF_SUCCESS;
1257	}
1258
1259
1260	/**
1261	* @interface_method_impl{PDMDEVREG,pfnConstruct}
1262	*/
1263	static DECLCALLBACK(int) pciR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
1264	{
1265	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
1266	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
1267	PDEVPCIBUSCC pBusCC = PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC);
1268	PDEVPCIROOT pGlobals = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
1269	RT_NOREF(iInstance);
1270	Assert(iInstance == 0);
1271
1272	/*
1273	* Validate and read configuration.
1274	*/
1275	PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "IOAPIC", "");
1276
1277	/* query whether we got an IOAPIC */
1278	bool fUseIoApic;
1279	int rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "IOAPIC", &fUseIoApic, false);
1280	if (RT_FAILURE(rc))
1281	return PDMDEV_SET_ERROR(pDevIns, rc,
1282	N_("Configuration error: Failed to query boolean value \"IOAPIC\""));
1283
1284	Log(("PCI: fUseIoApic=%RTbool fR0Enabled=%RTbool fRCEnabled=%RTbool\n", fUseIoApic, pDevIns->fR0Enabled, pDevIns->fRCEnabled));
1285
1286	/*
1287	* Init data and register the PCI bus.
1288	*/
1289	pGlobals->uPciBiosIo = 0xc000;
1290	pGlobals->uPciBiosMmio = 0xf0000000;
1291	memset((void *)&pGlobals->Piix3.auPciLegacyIrqLevels, 0, sizeof(pGlobals->Piix3.auPciLegacyIrqLevels));
1292	pGlobals->fUseIoApic = fUseIoApic;
1293	memset((void *)&pGlobals->auPciApicIrqLevels, 0, sizeof(pGlobals->auPciApicIrqLevels));
1294
1295	pGlobals->PciBus.fTypePiix3 = true;
1296	pGlobals->PciBus.fTypeIch9 = false;
1297	pGlobals->PciBus.fPureBridge = false;
1298	pGlobals->PciBus.papBridgesR3 = (PPDMPCIDEV *)PDMDevHlpMMHeapAllocZ(pDevIns,
1299	sizeof(PPDMPCIDEV)
1300	* RT_ELEMENTS(pGlobals->PciBus.apDevices));
1301	AssertLogRelReturn(pGlobals->PciBus.papBridgesR3, VERR_NO_MEMORY);
1302
1303	PDEVPCIBUS pBus = &pGlobals->PciBus;
1304	PDMPCIBUSREGCC PciBusReg;
1305	PciBusReg.u32Version = PDM_PCIBUSREGCC_VERSION;
1306	PciBusReg.pfnRegisterR3 = devpciR3CommonRegisterDevice;
1307	PciBusReg.pfnRegisterMsiR3 = NULL;
1308	PciBusReg.pfnIORegionRegisterR3 = devpciR3CommonIORegionRegister;
1309	PciBusReg.pfnInterceptConfigAccesses = devpciR3CommonInterceptConfigAccesses;
1310	PciBusReg.pfnConfigRead = devpciR3CommonConfigRead;
1311	PciBusReg.pfnConfigWrite = devpciR3CommonConfigWrite;
1312	PciBusReg.pfnSetIrqR3 = pciSetIrq;
1313	PciBusReg.u32EndVersion = PDM_PCIBUSREGCC_VERSION;
1314	rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBusCC->pPciHlpR3, &pBus->iBus);
1315	if (RT_FAILURE(rc))
1316	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to register ourselves as a PCI Bus"));
1317	Assert(pBus->iBus == 0);
1318	if (pBusCC->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
1319	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
1320	N_("PCI helper version mismatch; got %#x expected %#x"),
1321	pBusCC->pPciHlpR3->u32Version, PDM_PCIHLPR3_VERSION);
1322
1323	/* Disable default device locking. */
1324	rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
1325	AssertRCReturn(rc, rc);
1326
1327	/*
1328	* Fill in PCI configs and add them to the bus.
1329	*/
1330	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1331	AssertPtr(pPciDev);
1332
1333	/* i440FX */
1334	PCIDevSetVendorId( pPciDev, 0x8086); /* Intel */
1335	PCIDevSetDeviceId( pPciDev, 0x1237);
1336	PCIDevSetRevisionId(pPciDev, 0x02);
1337	PCIDevSetClassSub( pPciDev, 0x00); /* host2pci */
1338	PCIDevSetClassBase( pPciDev, 0x06); /* PCI_bridge */
1339	PCIDevSetHeaderType(pPciDev, 0x00);
1340	rc = PDMDevHlpPCIRegisterEx(pDevIns, pPciDev, 0 /fFlags/, 0 /uPciDevNo/, 0 /uPciFunNo/, "i440FX");
1341	AssertLogRelRCReturn(rc, rc);
1342
1343	/* PIIX3 */
1344	PPDMPCIDEV pPiix3PciDev = pDevIns->apPciDevs[1];
1345	PCIDevSetVendorId( pPiix3PciDev, 0x8086); /* Intel */
1346	PCIDevSetDeviceId( pPiix3PciDev, 0x7000); /* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */
1347	PCIDevSetClassSub( pPiix3PciDev, 0x01); /* PCI_ISA */
1348	PCIDevSetClassBase( pPiix3PciDev, 0x06); /* PCI_bridge */
1349	PCIDevSetHeaderType(pPiix3PciDev, 0x80); /* PCI_multifunction, generic */
1350	rc = PDMDevHlpPCIRegisterEx(pDevIns, pPiix3PciDev, 0 /fFlags/, 1 /uPciDevNo/, 0 /uPciFunNo/, "PIIX3");
1351	AssertLogRelRCReturn(rc, rc);
1352	pciR3Piix3Reset(pDevIns->apPciDevs[1]);
1353
1354	pBus->iDevSearch = 16;
1355
1356	/*
1357	* Register I/O ports and save state.
1358	*/
1359	static const IOMIOPORTDESC s_aAddrDesc[] = { { "PCI address", "PCI address", NULL, NULL }, { NULL, NULL, NULL, NULL } };
1360	rc = PDMDevHlpIoPortCreateAndMap(pDevIns, 0x0cf8, 1, pciIOPortAddressWrite, pciIOPortAddressRead, "i440FX (PCI)", s_aAddrDesc,
1361	&pGlobals->hIoPortAddress);
1362	AssertLogRelRCReturn(rc, rc);
1363
1364	static const IOMIOPORTDESC s_aDataDesc[] = { { "PCI data", "PCI data", NULL, NULL }, { NULL, NULL, NULL, NULL } };
1365	rc = PDMDevHlpIoPortCreateAndMap(pDevIns, 0x0cfc, 4, pciIOPortDataWrite, pciIOPortDataRead, "i440FX (PCI)", s_aDataDesc,
1366	&pGlobals->hIoPortData);
1367	AssertLogRelRCReturn(rc, rc);
1368
1369	static const IOMIOPORTDESC s_aMagicDesc[] = { { "PCI magic", NULL, NULL, NULL }, { NULL, NULL, NULL, NULL } };
1370	rc = PDMDevHlpIoPortCreateAndMap(pDevIns, 0x0410, 1, pciR3IOPortMagicPCIWrite, pciR3IOPortMagicPCIRead,
1371	"i440FX (Fake PCI BIOS trigger)", s_aMagicDesc, &pGlobals->hIoPortMagic);
1372	AssertLogRelRCReturn(rc, rc);
1373
1374
1375	rc = PDMDevHlpSSMRegisterEx(pDevIns, VBOX_PCI_SAVED_STATE_VERSION, sizeof(pBus) + 16128, "pgm",
1376	NULL, NULL, NULL,
1377	NULL, pciR3SaveExec, NULL,
1378	NULL, pciR3LoadExec, NULL);
1379	AssertLogRelRCReturn(rc, rc);
1380
1381	PDMDevHlpDBGFInfoRegister(pDevIns, "pci",
1382	"Display PCI bus status. Recognizes 'basic' or 'verbose' as arguments, defaults to 'basic'.",
1383	devpciR3InfoPci);
1384	PDMDevHlpDBGFInfoRegister(pDevIns, "pciirq", "Display PCI IRQ state. (no arguments)", devpciR3InfoPciIrq);
1385	PDMDevHlpDBGFInfoRegister(pDevIns, "pirq", "Display PIRQ state. (no arguments)", devpciR3InfoPIRQ);
1386	PDMDevHlpDBGFInfoRegister(pDevIns, "irqroute", "Display PCI IRQ routing. (no arguments)", pciR3IrqRouteInfo);
1387
1388	return VINF_SUCCESS;
1389	}
1390
1391	#else /* !IN_RING3 */
1392
1393	/**
1394	* @interface_method_impl{PDMDEVREGR0,pfnConstruct}
1395	*/
1396	static DECLCALLBACK(int) pciRZRootConstruct(PPDMDEVINS pDevIns)
1397	{
1398	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
1399	PDEVPCIROOT pGlobals = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
1400	PDEVPCIBUSCC pBusCC = PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC);
1401
1402	/* Mirror the ring-3 device lock disabling: */
1403	int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
1404	AssertRCReturn(rc, rc);
1405
1406	/* Set up the RZ PCI bus callbacks: */
1407	PDMPCIBUSREGCC PciBusReg;
1408	PciBusReg.u32Version = PDM_PCIBUSREGCC_VERSION;
1409	PciBusReg.iBus = pGlobals->PciBus.iBus;
1410	PciBusReg.pfnSetIrq = pciSetIrq;
1411	PciBusReg.u32EndVersion = PDM_PCIBUSREGCC_VERSION;
1412	rc = PDMDevHlpPCIBusSetUpContext(pDevIns, &PciBusReg, &pBusCC->CTX_SUFF(pPciHlp));
1413	AssertRCReturn(rc, rc);
1414
1415	/* Set up I/O port callbacks, except for the magic port: */
1416	rc = PDMDevHlpIoPortSetUpContext(pDevIns, pGlobals->hIoPortAddress, pciIOPortAddressWrite, pciIOPortAddressRead, NULL);
1417	AssertLogRelRCReturn(rc, rc);
1418
1419	rc = PDMDevHlpIoPortSetUpContext(pDevIns, pGlobals->hIoPortData, pciIOPortDataWrite, pciIOPortDataRead, NULL);
1420	AssertLogRelRCReturn(rc, rc);
1421
1422	return rc;
1423	}
1424
1425	#endif /* !IN_RING3 */
1426
1427	/**
1428	* The device registration structure.
1429	*/
1430	const PDMDEVREG g_DevicePCI =
1431	{
1432	/* .u32Version = */ PDM_DEVREG_VERSION,
1433	/* .uReserved0 = */ 0,
1434	/* .szName = */ "pci",
1435	/* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RZ \| PDM_DEVREG_FLAGS_NEW_STYLE,
1436	/* .fClass = */ PDM_DEVREG_CLASS_BUS_PCI,
1437	/* .cMaxInstances = */ 1,
1438	/* .uSharedVersion = */ 42,
1439	/* .cbInstanceShared = */ sizeof(DEVPCIROOT),
1440	/* .cbInstanceCC = */ sizeof(CTX_SUFF(DEVPCIBUS)),
1441	/* .cbInstanceRC = */ sizeof(DEVPCIBUSRC),
1442	/* .cMaxPciDevices = */ 2,
1443	/* .cMaxMsixVectors = */ 0,
1444	/* .pszDescription = */ "i440FX PCI bridge and PIIX3 ISA bridge.",
1445	#if defined(IN_RING3)
1446	/* .pszRCMod = */ "VBoxDDRC.rc",
1447	/* .pszR0Mod = */ "VBoxDDR0.r0",
1448	/* .pfnConstruct = */ pciR3Construct,
1449	/* .pfnDestruct = */ pciR3Destruct,
1450	/* .pfnRelocate = */ NULL,
1451	/* .pfnMemSetup = */ NULL,
1452	/* .pfnPowerOn = */ NULL,
1453	/* .pfnReset = */ pciR3Reset,
1454	/* .pfnSuspend = */ NULL,
1455	/* .pfnResume = */ NULL,
1456	/* .pfnAttach = */ NULL,
1457	/* .pfnDetach = */ NULL,
1458	/* .pfnQueryInterface = */ NULL,
1459	/* .pfnInitComplete = */ NULL,
1460	/* .pfnPowerOff = */ NULL,
1461	/* .pfnSoftReset = */ NULL,
1462	/* .pfnReserved0 = */ NULL,
1463	/* .pfnReserved1 = */ NULL,
1464	/* .pfnReserved2 = */ NULL,
1465	/* .pfnReserved3 = */ NULL,
1466	/* .pfnReserved4 = */ NULL,
1467	/* .pfnReserved5 = */ NULL,
1468	/* .pfnReserved6 = */ NULL,
1469	/* .pfnReserved7 = */ NULL,
1470	#elif defined(IN_RING0)
1471	/* .pfnEarlyConstruct = */ NULL,
1472	/* .pfnConstruct = */ pciRZRootConstruct,
1473	/* .pfnDestruct = */ NULL,
1474	/* .pfnFinalDestruct = */ NULL,
1475	/* .pfnRequest = */ NULL,
1476	/* .pfnReserved0 = */ NULL,
1477	/* .pfnReserved1 = */ NULL,
1478	/* .pfnReserved2 = */ NULL,
1479	/* .pfnReserved3 = */ NULL,
1480	/* .pfnReserved4 = */ NULL,
1481	/* .pfnReserved5 = */ NULL,
1482	/* .pfnReserved6 = */ NULL,
1483	/* .pfnReserved7 = */ NULL,
1484	#elif defined(IN_RC)
1485	/* .pfnConstruct = */ pciRZRootConstruct,
1486	/* .pfnReserved0 = */ NULL,
1487	/* .pfnReserved1 = */ NULL,
1488	/* .pfnReserved2 = */ NULL,
1489	/* .pfnReserved3 = */ NULL,
1490	/* .pfnReserved4 = */ NULL,
1491	/* .pfnReserved5 = */ NULL,
1492	/* .pfnReserved6 = */ NULL,
1493	/* .pfnReserved7 = */ NULL,
1494	#else
1495	# error "Not in IN_RING3, IN_RING0 or IN_RC!"
1496	#endif
1497	/* .u32VersionEnd = */ PDM_DEVREG_VERSION
1498
1499	};
1500
1501
1502
1503	/* -=-=-=-=-=- The PCI bridge specific bits -=-=-=-=-=- */
1504
1505	/**
1506	* @interface_method_impl{PDMPCIBUSREGR3,pfnSetIrqR3}
1507	*/
1508	static DECLCALLBACK(void) pcibridgeSetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc)
1509	{
1510	LogFlow(("pcibridgeSetIrq: %p %u %u %#x\n", pPciDev, iIrq, iLevel, uTagSrc));
1511
1512	/*
1513	* The PCI-to-PCI bridge specification defines how the interrupt pins
1514	* are routed from the secondary to the primary bus (see chapter 9).
1515	* iIrq gives the interrupt pin the pci device asserted.
1516	* We change iIrq here according to the spec and call the SetIrq function
1517	* of our parent passing the device which asserted the interrupt instead of the device of the bridge.
1518	*/
1519	PDEVPCIBUS pBus;
1520	uint8_t uDevFnBridge;
1521	int iIrqPinBridge;
1522	PPDMDEVINS pDevInsBus = devpcibridgeCommonSetIrqRootWalk(pDevIns, pPciDev, iIrq, &pBus, &uDevFnBridge, &iIrqPinBridge);
1523	AssertReturnVoid(pDevInsBus);
1524	AssertMsg(pBus->iBus == 0, ("This is not the host pci bus iBus=%d\n", pBus->iBus));
1525	Assert(pDevInsBus->pReg == &g_DevicePCI);
1526
1527	pciSetIrqInternal(pDevInsBus, DEVPCIBUS_2_DEVPCIROOT(pBus), PDMINS_2_DATA_CC(pDevInsBus, PDEVPCIBUSCC),
1528	uDevFnBridge, pPciDev, iIrqPinBridge, iLevel, uTagSrc);
1529	}
1530
1531	#ifdef IN_RING3
1532
1533	/**
1534	* @callback_method_impl{FNPCIBRIDGECONFIGWRITE}
1535	*/
1536	static DECLCALLBACK(VBOXSTRICTRC) pcibridgeR3ConfigWrite(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice,
1537	uint32_t u32Address, unsigned cb, uint32_t u32Value)
1538	{
1539	LogFlowFunc(("pDevIns=%p iBus=%d iDevice=%d u32Address=%u cb=%d u32Value=%u\n", pDevIns, iBus, iDevice, u32Address, cb, u32Value));
1540	PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
1541	VBOXSTRICTRC rcStrict = VINF_SUCCESS;
1542
1543	/* If the current bus is not the target bus search for the bus which contains the device. */
1544	if (iBus != pDevIns->apPciDevs[0]->abConfig[VBOX_PCI_SECONDARY_BUS])
1545	{
1546	PPDMPCIDEV pBridgeDevice = pciR3FindBridge(pBus, iBus);
1547	if (pBridgeDevice)
1548	{
1549	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigWrite);
1550	rcStrict = pBridgeDevice->Int.s.pfnBridgeConfigWrite(pBridgeDevice->Int.s.CTX_SUFF(pDevIns), iBus, iDevice,
1551	u32Address, cb, u32Value);
1552	}
1553	}
1554	else
1555	{
1556	/* This is the target bus, pass the write to the device. */
1557	PPDMPCIDEV pPciDev = pBus->apDevices[iDevice];
1558	if (pPciDev)
1559	{
1560	LogFunc(("%s: addr=%02x val=%08x len=%d\n", pPciDev->pszNameR3, u32Address, u32Value, cb));
1561	rcStrict = VINF_PDM_PCI_DO_DEFAULT;
1562	if (pPciDev->Int.s.pfnConfigWrite)
1563	rcStrict = pPciDev->Int.s.pfnConfigWrite(pPciDev->Int.s.CTX_SUFF(pDevIns), pPciDev, u32Address, cb, u32Value);
1564	if (rcStrict == VINF_PDM_PCI_DO_DEFAULT)
1565	rcStrict = devpciR3CommonConfigWriteWorker(pDevIns, PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC),
1566	pPciDev, u32Address, cb, u32Value);
1567	}
1568	}
1569	return rcStrict;
1570	}
1571
1572
1573	/**
1574	* @callback_method_impl{FNPCIBRIDGECONFIGREAD}
1575	*/
1576	static DECLCALLBACK(VBOXSTRICTRC) pcibridgeR3ConfigRead(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice,
1577	uint32_t u32Address, unsigned cb, uint32_t *pu32Value)
1578	{
1579	LogFlowFunc(("pDevIns=%p iBus=%d iDevice=%d u32Address=%u cb=%d\n", pDevIns, iBus, iDevice, u32Address, cb));
1580	PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
1581	VBOXSTRICTRC rcStrict = VINF_SUCCESS;
1582
1583	/* If the current bus is not the target bus search for the bus which contains the device. */
1584	if (iBus != pDevIns->apPciDevs[0]->abConfig[VBOX_PCI_SECONDARY_BUS])
1585	{
1586	PPDMPCIDEV pBridgeDevice = pciR3FindBridge(pBus, iBus);
1587	if (pBridgeDevice)
1588	{
1589	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigRead);
1590	rcStrict = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->Int.s.CTX_SUFF(pDevIns),
1591	iBus, iDevice, u32Address, cb, pu32Value);
1592	}
1593	else
1594	*pu32Value = UINT32_MAX;
1595	}
1596	else
1597	{
1598	/* This is the target bus, pass the read to the device. */
1599	PPDMPCIDEV pPciDev = pBus->apDevices[iDevice];
1600	if (pPciDev)
1601	{
1602	rcStrict = VINF_PDM_PCI_DO_DEFAULT;
1603	if (pPciDev->Int.s.pfnConfigRead)
1604	rcStrict = pPciDev->Int.s.pfnConfigRead(pPciDev->Int.s.CTX_SUFF(pDevIns), pPciDev, u32Address, cb, pu32Value);
1605	if (rcStrict == VINF_PDM_PCI_DO_DEFAULT)
1606	rcStrict = devpciR3CommonConfigReadWorker(pPciDev, u32Address, cb, pu32Value);
1607
1608	LogFunc(("%s: u32Address=%02x u32Value=%08x cb=%d\n", pPciDev->pszNameR3, u32Address, *pu32Value, cb));
1609	}
1610	else
1611	*pu32Value = UINT32_MAX;
1612	}
1613
1614	return rcStrict;
1615	}
1616
1617
1618	/**
1619	* @callback_method_impl{FNSSMDEVSAVEEXEC}
1620	*/
1621	static DECLCALLBACK(int) pcibridgeR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
1622	{
1623	return pciR3CommonSaveExec(pDevIns->pHlpR3, PDMINS_2_DATA(pDevIns, PDEVPCIBUS), pSSM);
1624	}
1625
1626
1627	/**
1628	* @callback_method_impl{FNSSMDEVLOADEXEC}
1629	*/
1630	static DECLCALLBACK(int) pcibridgeR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1631	{
1632	PDEVPCIBUS pThis = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
1633	if (uVersion > VBOX_PCI_SAVED_STATE_VERSION)
1634	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1635	return pciR3CommonLoadExec(pDevIns, pThis, pSSM, uVersion, uPass);
1636	}
1637
1638
1639	/**
1640	* @interface_method_impl{PDMDEVREG,pfnReset}
1641	*/
1642	static DECLCALLBACK(void) pcibridgeR3Reset(PPDMDEVINS pDevIns)
1643	{
1644	/* Reset config space to default values. */
1645	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1646	pPciDev->abConfig[VBOX_PCI_PRIMARY_BUS] = 0;
1647	pPciDev->abConfig[VBOX_PCI_SECONDARY_BUS] = 0;
1648	pPciDev->abConfig[VBOX_PCI_SUBORDINATE_BUS] = 0;
1649	}
1650
1651
1652	/**
1653	* @interface_method_impl{PDMDEVREG,pfnDestruct}
1654	*/
1655	static DECLCALLBACK(int) pcibridgeR3Destruct(PPDMDEVINS pDevIns)
1656	{
1657	PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
1658	if (pBus->papBridgesR3)
1659	{
1660	PDMDevHlpMMHeapFree(pDevIns, pBus->papBridgesR3);
1661	pBus->papBridgesR3 = NULL;
1662	}
1663	return VINF_SUCCESS;
1664	}
1665
1666
1667	/**
1668	* @interface_method_impl{PDMDEVREG,pfnConstruct}
1669	*/
1670	static DECLCALLBACK(int) pcibridgeR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
1671	{
1672	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
1673	RT_NOREF(iInstance, pCfg);
1674	PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
1675	PDEVPCIBUSCC pBusCC = PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC);
1676
1677	/*
1678	* Validate and read configuration (none left).
1679	*/
1680	PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "", "");
1681	Log(("PCI: fRCEnabled=%RTbool fR0Enabled=%RTbool\n", pDevIns->fRCEnabled, pDevIns->fR0Enabled));
1682
1683	/*
1684	* Init data and register the PCI bus.
1685	*/
1686	pBus->fTypePiix3 = true;
1687	pBus->fTypeIch9 = false;
1688	pBus->fPureBridge = true;
1689	pBus->papBridgesR3 = (PPDMPCIDEV )PDMDevHlpMMHeapAllocZ(pDevIns, sizeof(PPDMPCIDEV) RT_ELEMENTS(pBus->apDevices));
1690	AssertLogRelReturn(pBus->papBridgesR3, VERR_NO_MEMORY);
1691
1692	PDMPCIBUSREGCC PciBusReg;
1693	PciBusReg.u32Version = PDM_PCIBUSREGCC_VERSION;
1694	PciBusReg.pfnRegisterR3 = devpcibridgeR3CommonRegisterDevice;
1695	PciBusReg.pfnRegisterMsiR3 = NULL;
1696	PciBusReg.pfnIORegionRegisterR3 = devpciR3CommonIORegionRegister;
1697	PciBusReg.pfnInterceptConfigAccesses = devpciR3CommonInterceptConfigAccesses;
1698	PciBusReg.pfnConfigWrite = devpciR3CommonConfigWrite;
1699	PciBusReg.pfnConfigRead = devpciR3CommonConfigRead;
1700	PciBusReg.pfnSetIrqR3 = pcibridgeSetIrq;
1701	PciBusReg.u32EndVersion = PDM_PCIBUSREGCC_VERSION;
1702	int rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBusCC->pPciHlpR3, &pBus->iBus);
1703	if (RT_FAILURE(rc))
1704	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to register ourselves as a PCI Bus"));
1705	Assert(pBus->iBus == (uint32_t)iInstance + 1); /* Can be removed when adding support for multiple bridge implementations. */
1706	if (pBusCC->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
1707	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
1708	N_("PCI helper version mismatch; got %#x expected %#x"),
1709	pBusCC->pPciHlpR3->u32Version, PDM_PCIHLPR3_VERSION);
1710
1711	/*
1712	* Fill in PCI configs and add them to the bus.
1713	*/
1714	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1715	PCIDevSetVendorId( pPciDev, 0x8086); /* Intel */
1716	PCIDevSetDeviceId( pPciDev, 0x2448); /* 82801 Mobile PCI bridge. */
1717	PCIDevSetRevisionId(pPciDev, 0xf2);
1718	PCIDevSetClassSub( pPciDev, 0x04); /* pci2pci */
1719	PCIDevSetClassBase( pPciDev, 0x06); /* PCI_bridge */
1720	PCIDevSetClassProg( pPciDev, 0x01); /* Supports subtractive decoding. */
1721	PCIDevSetHeaderType(pPciDev, 0x01); /* Single function device which adheres to the PCI-to-PCI bridge spec. */
1722	PCIDevSetCommand( pPciDev, 0x0000);
1723	PCIDevSetStatus( pPciDev, 0x0020); /* 66MHz Capable. */
1724	PCIDevSetInterruptLine(pPciDev, 0x00); /* This device does not assert interrupts. */
1725
1726	/*
1727	* This device does not generate interrupts. Interrupt delivery from
1728	* devices attached to the bus is unaffected.
1729	*/
1730	PCIDevSetInterruptPin(pPciDev, 0x00);
1731
1732	/*
1733	* Register this PCI bridge. The called function will take care on which bus we will get registered.
1734	*/
1735	rc = PDMDevHlpPCIRegisterEx(pDevIns, pPciDev, PDMPCIDEVREG_F_PCI_BRIDGE, PDMPCIDEVREG_DEV_NO_FIRST_UNUSED,
1736	PDMPCIDEVREG_FUN_NO_FIRST_UNUSED, "pcibridge");
1737	if (RT_FAILURE(rc))
1738	return rc;
1739	pPciDev->Int.s.pfnBridgeConfigRead = pcibridgeR3ConfigRead;
1740	pPciDev->Int.s.pfnBridgeConfigWrite = pcibridgeR3ConfigWrite;
1741
1742	pBus->iDevSearch = 0;
1743
1744	/*
1745	* Register SSM handlers. We use the same saved state version as for the host bridge
1746	* to make changes easier.
1747	*/
1748	rc = PDMDevHlpSSMRegisterEx(pDevIns, VBOX_PCI_SAVED_STATE_VERSION, sizeof(pBus) + 16128, "pgm",
1749	NULL, NULL, NULL,
1750	NULL, pcibridgeR3SaveExec, NULL,
1751	NULL, pcibridgeR3LoadExec, NULL);
1752	if (RT_FAILURE(rc))
1753	return rc;
1754
1755	return VINF_SUCCESS;
1756	}
1757
1758	#else /* !IN_RING3 */
1759
1760	/**
1761	* @interface_method_impl{PDMDEVREGR0,pfnConstruct}
1762	*/
1763	static DECLCALLBACK(int) pcibridgeRZConstruct(PPDMDEVINS pDevIns)
1764	{
1765	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
1766	PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
1767	PDEVPCIBUSCC pBusCC = PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC);
1768
1769	PDMPCIBUSREGCC PciBusReg;
1770	PciBusReg.u32Version = PDM_PCIBUSREGCC_VERSION;
1771	PciBusReg.iBus = pBus->iBus;
1772	PciBusReg.pfnSetIrq = pcibridgeSetIrq;
1773	PciBusReg.u32EndVersion = PDM_PCIBUSREGCC_VERSION;
1774	int rc = PDMDevHlpPCIBusSetUpContext(pDevIns, &PciBusReg, &pBusCC->CTX_SUFF(pPciHlp));
1775	AssertRC(rc);
1776
1777	return rc;
1778	}
1779
1780	#endif /* !IN_RING3 */
1781
1782	/**
1783	* The device registration structure
1784	* for the PCI-to-PCI bridge.
1785	*/
1786	const PDMDEVREG g_DevicePCIBridge =
1787	{
1788	/* .u32Version = */ PDM_DEVREG_VERSION,
1789	/* .uReserved0 = */ 0,
1790	/* .szName = */ "pcibridge",
1791	/* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RZ \| PDM_DEVREG_FLAGS_NEW_STYLE,
1792	/* .fClass = */ PDM_DEVREG_CLASS_BUS_PCI,
1793	/* .cMaxInstances = */ ~0U,
1794	/* .uSharedVersion = */ 42,
1795	/* .cbInstanceShared = */ sizeof(DEVPCIBUS),
1796	/* .cbInstanceCC = */ sizeof(CTX_SUFF(DEVPCIBUS)),
1797	/* .cbInstanceRC = */ 0,
1798	/* .cMaxPciDevices = */ 1,
1799	/* .cMaxMsixVectors = */ 0,
1800	/* .pszDescription = */ "82801 Mobile PCI to PCI bridge",
1801	#if defined(IN_RING3)
1802	/* .pszRCMod = */ "VBoxDDRC.rc",
1803	/* .pszR0Mod = */ "VBoxDDR0.r0",
1804	/* .pfnConstruct = */ pcibridgeR3Construct,
1805	/* .pfnDestruct = */ pcibridgeR3Destruct,
1806	/* .pfnRelocate = */ NULL,
1807	/* .pfnMemSetup = */ NULL,
1808	/* .pfnPowerOn = */ NULL,
1809	/* .pfnReset = */ pcibridgeR3Reset,
1810	/* .pfnSuspend = */ NULL,
1811	/* .pfnResume = */ NULL,
1812	/* .pfnAttach = */ NULL,
1813	/* .pfnDetach = */ NULL,
1814	/* .pfnQueryInterface = */ NULL,
1815	/* .pfnInitComplete = */ NULL,
1816	/* .pfnPowerOff = */ NULL,
1817	/* .pfnSoftReset = */ NULL,
1818	/* .pfnReserved0 = */ NULL,
1819	/* .pfnReserved1 = */ NULL,
1820	/* .pfnReserved2 = */ NULL,
1821	/* .pfnReserved3 = */ NULL,
1822	/* .pfnReserved4 = */ NULL,
1823	/* .pfnReserved5 = */ NULL,
1824	/* .pfnReserved6 = */ NULL,
1825	/* .pfnReserved7 = */ NULL,
1826	#elif defined(IN_RING0)
1827	/* .pfnEarlyConstruct = */ NULL,
1828	/* .pfnConstruct = */ pcibridgeRZConstruct,
1829	/* .pfnDestruct = */ NULL,
1830	/* .pfnFinalDestruct = */ NULL,
1831	/* .pfnRequest = */ NULL,
1832	/* .pfnReserved0 = */ NULL,
1833	/* .pfnReserved1 = */ NULL,
1834	/* .pfnReserved2 = */ NULL,
1835	/* .pfnReserved3 = */ NULL,
1836	/* .pfnReserved4 = */ NULL,
1837	/* .pfnReserved5 = */ NULL,
1838	/* .pfnReserved6 = */ NULL,
1839	/* .pfnReserved7 = */ NULL,
1840	#elif defined(IN_RC)
1841	/* .pfnConstruct = */ pcibridgeRZConstruct,
1842	/* .pfnReserved0 = */ NULL,
1843	/* .pfnReserved1 = */ NULL,
1844	/* .pfnReserved2 = */ NULL,
1845	/* .pfnReserved3 = */ NULL,
1846	/* .pfnReserved4 = */ NULL,
1847	/* .pfnReserved5 = */ NULL,
1848	/* .pfnReserved6 = */ NULL,
1849	/* .pfnReserved7 = */ NULL,
1850	#else
1851	# error "Not in IN_RING3, IN_RING0 or IN_RC!"
1852	#endif
1853	/* .u32VersionEnd = */ PDM_DEVREG_VERSION
1854	};
1855

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source: vbox/trunk/src/VBox/Devices/Bus/DevPCI.cpp@ 86728

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