DevPCI.cpp@ 91605

Last change on this file since 91605 was 90436, checked in by vboxsync, 3 years ago
VMM,Dev*: Handle PDMCritSectEnter failures in relation to the PDM critsect. bugref:6695
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File size: 75.1 KB

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1	/* $Id: DevPCI.cpp 90436 2021-07-30 16:03:48Z vboxsync $ */
2	/** @file
3	* DevPCI - PCI BUS Device.
4	*
5	* @remarks New code shall be added to DevPciIch9.cpp as that will become
6	* the common PCI bus code soon. Don't fix code in both DevPCI.cpp
7	* and DevPciIch9.cpp when it's possible to just make the latter
8	* version common. Common code uses the 'devpci' prefix, is
9	* prototyped in DevPciInternal.h, and is defined in DevPciIch9.cpp.
10	*/
11
12	/*
13	* Copyright (C) 2006-2020 Oracle Corporation
14	*
15	* This file is part of VirtualBox Open Source Edition (OSE), as
16	* available from http://www.virtualbox.org. This file is free software;
17	* you can redistribute it and/or modify it under the terms of the GNU
18	* General Public License (GPL) as published by the Free Software
19	* Foundation, in version 2 as it comes in the "COPYING" file of the
20	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
21	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
22	* --------------------------------------------------------------------
23	*
24	* This code is based on:
25	*
26	* QEMU PCI bus manager
27	*
28	* Copyright (c) 2004 Fabrice Bellard
29	*
30	* Permission is hereby granted, free of charge, to any person obtaining a copy
31	* of this software and associated documentation files (the "Software"), to deal
32	* in the Software without restriction, including without limitation the rights
33	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
34	* copies of the Software, and to permit persons to whom the Software is
35	* furnished to do so, subject to the following conditions:
36	*
37	* The above copyright notice and this permission notice shall be included in
38	* all copies or substantial portions of the Software.
39	*
40	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
41	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
42	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
43	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
44	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
45	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
46	* THE SOFTWARE.
47	*/
48
49
50	/*********************************************************************************************************************************
51	* Header Files *
52	*********************************************************************************************************************************/
53	#define LOG_GROUP LOG_GROUP_DEV_PCI
54	#define PDMPCIDEV_INCLUDE_PRIVATE /* Hack to get pdmpcidevint.h included at the right point. */
55	#include <VBox/vmm/pdmpcidev.h>
56	#include <VBox/vmm/pdmdev.h>
57	#include <VBox/vmm/mm.h>
58	#include <iprt/asm.h>
59	#include <iprt/assert.h>
60	#include <iprt/string.h>
61
62	#include "PciInline.h"
63	#include "VBoxDD.h"
64	#include "DevPciInternal.h"
65
66
67	/*********************************************************************************************************************************
68	* Defined Constants And Macros *
69	*********************************************************************************************************************************/
70	/** Saved state version of the PCI bus device. */
71	#define VBOX_PCI_SAVED_STATE_VERSION VBOX_PCI_SAVED_STATE_VERSION_REGION_SIZES
72	/** Adds I/O region types and sizes for dealing changes in resource regions. */
73	#define VBOX_PCI_SAVED_STATE_VERSION_REGION_SIZES 4
74	/** Before region sizes, the first named one.
75	* Looking at the code though, we support even older version. */
76	#define VBOX_PCI_SAVED_STATE_VERSION_IRQ_STATES 3
77	/** Notes whether we use the I/O APIC. */
78	#define VBOX_PCI_SAVED_STATE_VERSION_USE_IO_APIC 2
79
80
81	/*********************************************************************************************************************************
82	* Internal Functions *
83	*********************************************************************************************************************************/
84	RT_C_DECLS_BEGIN
85
86	static DECLCALLBACK(void) pcibridgeSetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTag);
87
88	#ifdef IN_RING3
89	DECLINLINE(PPDMPCIDEV) pciR3FindBridge(PDEVPCIBUS pBus, uint8_t iBus);
90	#endif
91
92	RT_C_DECLS_END
93
94	#define DEBUG_PCI
95
96	#define PCI_VENDOR_ID 0x00 /* 16 bits */
97	#define PCI_DEVICE_ID 0x02 /* 16 bits */
98	#define PCI_COMMAND 0x04 /* 16 bits */
99	#define PCI_COMMAND_IO 0x01 /* Enable response in I/O space */
100	#define PCI_COMMAND_MEMORY 0x02 /* Enable response in Memory space */
101	#define PCI_CLASS_DEVICE 0x0a /* Device class */
102	#define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
103	#define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
104	#define PCI_MIN_GNT 0x3e /* 8 bits */
105	#define PCI_MAX_LAT 0x3f /* 8 bits */
106
107
108	static VBOXSTRICTRC pci_data_write(PPDMDEVINS pDevIns, PDEVPCIROOT pGlobals, uint32_t addr, uint32_t u32Value, int cb)
109	{
110	LogFunc(("addr=%08x u32Value=%08x cb=%d\n", pGlobals->uConfigReg, u32Value, cb));
111
112	if (!(pGlobals->uConfigReg & (1 << 31)))
113	return VINF_SUCCESS;
114	if ((pGlobals->uConfigReg & 0x3) != 0)
115	return VINF_SUCCESS;
116
117	uint8_t const iBus = (pGlobals->uConfigReg >> 16) & 0xff;
118	uint8_t const iDevice = (pGlobals->uConfigReg >> 8) & 0xff;
119	#ifdef IN_RING3
120	uint32_t const config_addr = (pGlobals->uConfigReg & 0xfc) \| (addr & 3);
121	#endif
122	RT_UNTRUSTED_VALIDATED_FENCE(); /* paranoia */
123
124	VBOXSTRICTRC rcStrict = VINF_SUCCESS;
125	if (iBus != 0)
126	{
127	if (pGlobals->PciBus.cBridges)
128	{
129	#ifdef IN_RING3 /** @todo do lookup in R0/RC too! */
130	PPDMPCIDEV pBridgeDevice = pciR3FindBridge(&pGlobals->PciBus, iBus);
131	if (pBridgeDevice)
132	{
133	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigWrite);
134	rcStrict = pBridgeDevice->Int.s.pfnBridgeConfigWrite(pBridgeDevice->Int.s.CTX_SUFF(pDevIns), iBus,
135	iDevice, config_addr, cb, u32Value);
136	}
137	#else
138	RT_NOREF(pDevIns, addr, u32Value, cb);
139	rcStrict = VINF_IOM_R3_IOPORT_WRITE;
140	#endif
141	}
142	}
143	else
144	{
145	R3PTRTYPE(PDMPCIDEV *) pPciDev = pGlobals->PciBus.apDevices[iDevice];
146	if (pPciDev)
147	{
148	#ifdef IN_RING3
149	LogFunc(("%s: addr=%02x u32Value=%08x cb=%d\n", pPciDev->pszNameR3, config_addr, u32Value, cb));
150	rcStrict = VINF_PDM_PCI_DO_DEFAULT;
151	if (pPciDev->Int.s.pfnConfigWrite)
152	rcStrict = pPciDev->Int.s.pfnConfigWrite(pPciDev->Int.s.CTX_SUFF(pDevIns), pPciDev, config_addr, cb, u32Value);
153	if (rcStrict == VINF_PDM_PCI_DO_DEFAULT)
154	rcStrict = devpciR3CommonConfigWriteWorker(pDevIns, PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC),
155	pPciDev, config_addr, cb, u32Value);
156	#else
157	rcStrict = VINF_IOM_R3_IOPORT_WRITE;
158	#endif
159	}
160	}
161	return rcStrict;
162	}
163
164	static VBOXSTRICTRC pci_data_read(PDEVPCIROOT pGlobals, uint32_t addr, int cb, uint32_t *pu32Value)
165	{
166	*pu32Value = UINT32_MAX;
167
168	if (!(pGlobals->uConfigReg & (1 << 31)))
169	return VINF_SUCCESS;
170	if ((pGlobals->uConfigReg & 0x3) != 0)
171	return VINF_SUCCESS;
172	uint8_t const iBus = (pGlobals->uConfigReg >> 16) & 0xff;
173	uint8_t const iDevice = (pGlobals->uConfigReg >> 8) & 0xff;
174	#ifdef IN_RING3
175	uint32_t const config_addr = (pGlobals->uConfigReg & 0xfc) \| (addr & 3);
176	#endif
177	RT_UNTRUSTED_VALIDATED_FENCE();
178
179	VBOXSTRICTRC rcStrict = VINF_SUCCESS;
180	if (iBus != 0)
181	{
182	if (pGlobals->PciBus.cBridges)
183	{
184	#ifdef IN_RING3 /** @todo do lookup in R0/RC too! */
185	PPDMPCIDEV pBridgeDevice = pciR3FindBridge(&pGlobals->PciBus, iBus);
186	if (pBridgeDevice)
187	{
188	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigRead);
189	rcStrict = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->Int.s.CTX_SUFF(pDevIns),
190	iBus, iDevice, config_addr, cb, pu32Value);
191	}
192	#else
193	RT_NOREF(addr, cb);
194	rcStrict = VINF_IOM_R3_IOPORT_READ;
195	#endif
196	}
197	}
198	else
199	{
200	R3PTRTYPE(PDMPCIDEV *) pPciDev = pGlobals->PciBus.apDevices[iDevice];
201	if (pPciDev)
202	{
203	#ifdef IN_RING3
204	rcStrict = VINF_PDM_PCI_DO_DEFAULT;
205	if (pPciDev->Int.s.pfnConfigRead)
206	rcStrict = pPciDev->Int.s.pfnConfigRead(pPciDev->Int.s.CTX_SUFF(pDevIns), pPciDev, config_addr, cb, pu32Value);
207	if (rcStrict == VINF_PDM_PCI_DO_DEFAULT)
208	rcStrict = devpciR3CommonConfigReadWorker(pPciDev, config_addr, cb, pu32Value);
209	LogFunc(("%s: addr=%02x val=%08x cb=%d\n", pPciDev->pszNameR3, config_addr, *pu32Value, cb));
210	#else
211	NOREF(cb);
212	rcStrict = VINF_IOM_R3_IOPORT_READ;
213	#endif
214	}
215	}
216
217	return rcStrict;
218	}
219
220
221
222	/* return the global irq number corresponding to a given device irq
223	pin. We could also use the bus number to have a more precise
224	mapping.
225	This is the implementation note described in the PCI spec chapter 2.2.6 */
226	static inline int pci_slot_get_pirq(uint8_t uDevFn, int irq_num)
227	{
228	int slot_addend;
229	slot_addend = (uDevFn >> 3) - 1;
230	return (irq_num + slot_addend) & 3;
231	}
232
233	static inline int pci_slot_get_apic_pirq(uint8_t uDevFn, int irq_num)
234	{
235	return (irq_num + (uDevFn >> 3)) & 7;
236	}
237
238	static inline int get_pci_irq_apic_level(PDEVPCIROOT pGlobals, int irq_num)
239	{
240	return (pGlobals->auPciApicIrqLevels[irq_num] != 0);
241	}
242
243	static void apic_set_irq(PPDMDEVINS pDevIns, PDEVPCIBUS pBus, PDEVPCIBUSCC pBusCC,
244	uint8_t uDevFn, PDMPCIDEV *pPciDev, int irq_num1, int iLevel, int iAcpiIrq, uint32_t uTagSrc)
245	{
246	/* This is only allowed to be called with a pointer to the host bus. */
247	AssertMsg(pBus->iBus == 0, ("iBus=%u\n", pBus->iBus));
248	uint16_t const uBusDevFn = PCIBDF_MAKE(pBus->iBus, uDevFn);
249
250	if (iAcpiIrq == -1) {
251	int apic_irq, apic_level;
252	PDEVPCIROOT pGlobals = DEVPCIBUS_2_DEVPCIROOT(pBus);
253	int irq_num = pci_slot_get_apic_pirq(uDevFn, irq_num1);
254
255	if ((iLevel & PDM_IRQ_LEVEL_HIGH) == PDM_IRQ_LEVEL_HIGH)
256	ASMAtomicIncU32(&pGlobals->auPciApicIrqLevels[irq_num]);
257	else if ((iLevel & PDM_IRQ_LEVEL_HIGH) == PDM_IRQ_LEVEL_LOW)
258	ASMAtomicDecU32(&pGlobals->auPciApicIrqLevels[irq_num]);
259
260	apic_irq = irq_num + 0x10;
261	apic_level = get_pci_irq_apic_level(pGlobals, irq_num);
262	Log3Func(("%s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d\n",
263	R3STRING(pPciDev->pszNameR3), irq_num1, iLevel, apic_irq, apic_level, irq_num));
264	pBusCC->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pDevIns, uBusDevFn, apic_irq, apic_level, uTagSrc);
265
266	if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP) {
267	ASMAtomicDecU32(&pGlobals->auPciApicIrqLevels[irq_num]);
268	pPciDev->Int.s.uIrqPinState = PDM_IRQ_LEVEL_LOW;
269	apic_level = get_pci_irq_apic_level(pGlobals, irq_num);
270	Log3Func(("%s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d (flop)\n",
271	R3STRING(pPciDev->pszNameR3), irq_num1, iLevel, apic_irq, apic_level, irq_num));
272	pBusCC->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pDevIns, uBusDevFn, apic_irq, apic_level, uTagSrc);
273	}
274	} else {
275	Log3Func(("%s: irq_num1=%d level=%d iAcpiIrq=%d\n", R3STRING(pPciDev->pszNameR3), irq_num1, iLevel, iAcpiIrq));
276	pBusCC->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pDevIns, uBusDevFn, iAcpiIrq, iLevel, uTagSrc);
277	}
278	}
279
280	DECLINLINE(int) get_pci_irq_level(PDEVPCIROOT pGlobals, int irq_num)
281	{
282	return (pGlobals->Piix3.auPciLegacyIrqLevels[irq_num] != 0);
283	}
284
285	/**
286	* Set the IRQ for a PCI device on the host bus - shared by host bus and bridge.
287	*
288	* @param pDevIns The PDM device instance for the PCI bus.
289	* @param pGlobals Device instance of the host PCI bus.
290	* @param pBusCC Context specific data for the PCI bus.
291	* @param uDevFn The device number on the host bus which will raise the IRQ
292	* @param pPciDev The PCI device structure which raised the interrupt.
293	* @param iIrq IRQ number to set.
294	* @param iLevel IRQ level.
295	* @param uTagSrc The IRQ tag and source ID (for tracing).
296	* @remark uDevFn and pPciDev->uDevFn are not the same if the device is behind
297	* a bridge. In that case uDevFn will be the slot of the bridge which
298	* is needed to calculate the PIRQ value.
299	*/
300	static void pciSetIrqInternal(PPDMDEVINS pDevIns, PDEVPCIROOT pGlobals, PDEVPCIBUSCC pBusCC,
301	uint8_t uDevFn, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc)
302	{
303	PDEVPCIBUS pBus = &pGlobals->PciBus;
304	uint8_t *pbCfg = pDevIns->apPciDevs[1]->abConfig;
305	const bool fIsAcpiDevice = pPciDev->abConfig[2] == 0x13 && pPciDev->abConfig[3] == 0x71;
306	/* If the two configuration space bytes at 0xde, 0xad are set to 0xbe, 0xef, a back door
307	* is opened to route PCI interrupts directly to the I/O APIC and bypass the PIC.
308	* See the \_SB_.PCI0._PRT method in vbox.dsl.
309	*/
310	const bool fIsApicEnabled = pGlobals->fUseIoApic && pbCfg[0xde] == 0xbe && pbCfg[0xad] == 0xef;
311	int pic_irq, pic_level;
312
313	/* Check if the state changed. */
314	if (pPciDev->Int.s.uIrqPinState != iLevel)
315	{
316	pPciDev->Int.s.uIrqPinState = (iLevel & PDM_IRQ_LEVEL_HIGH);
317
318	/* Send interrupt to I/O APIC only. */
319	if (fIsApicEnabled)
320	{
321	if (fIsAcpiDevice)
322	/*
323	* ACPI needs special treatment since SCI is hardwired and
324	* should not be affected by PCI IRQ routing tables at the
325	* same time SCI IRQ is shared in PCI sense hence this
326	* kludge (i.e. we fetch the hardwired value from ACPIs
327	* PCI device configuration space).
328	*/
329	apic_set_irq(pDevIns, pBus, pBusCC, uDevFn, pPciDev, -1, iLevel, pPciDev->abConfig[PCI_INTERRUPT_LINE], uTagSrc);
330	else
331	apic_set_irq(pDevIns, pBus, pBusCC, uDevFn, pPciDev, iIrq, iLevel, -1, uTagSrc);
332	return;
333	}
334
335	if (fIsAcpiDevice)
336	{
337	/* As per above treat ACPI in a special way */
338	pic_irq = pPciDev->abConfig[PCI_INTERRUPT_LINE];
339	pGlobals->Piix3.iAcpiIrq = pic_irq;
340	pGlobals->Piix3.iAcpiIrqLevel = iLevel & PDM_IRQ_LEVEL_HIGH;
341	}
342	else
343	{
344	int irq_num;
345	irq_num = pci_slot_get_pirq(uDevFn, iIrq);
346
347	if (pPciDev->Int.s.uIrqPinState == PDM_IRQ_LEVEL_HIGH)
348	ASMAtomicIncU32(&pGlobals->Piix3.auPciLegacyIrqLevels[irq_num]);
349	else if (pPciDev->Int.s.uIrqPinState == PDM_IRQ_LEVEL_LOW)
350	ASMAtomicDecU32(&pGlobals->Piix3.auPciLegacyIrqLevels[irq_num]);
351
352	/* now we change the pic irq level according to the piix irq mappings */
353	pic_irq = pbCfg[0x60 + irq_num];
354	if (pic_irq >= 16)
355	{
356	if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP)
357	{
358	ASMAtomicDecU32(&pGlobals->Piix3.auPciLegacyIrqLevels[irq_num]);
359	pPciDev->Int.s.uIrqPinState = PDM_IRQ_LEVEL_LOW;
360	}
361
362	return;
363	}
364	}
365
366	/* the pic level is the logical OR of all the PCI irqs mapped to it */
367	pic_level = 0;
368	if (pic_irq == pbCfg[0x60])
369	pic_level \|= get_pci_irq_level(pGlobals, 0); /* PIRQA */
370	if (pic_irq == pbCfg[0x61])
371	pic_level \|= get_pci_irq_level(pGlobals, 1); /* PIRQB */
372	if (pic_irq == pbCfg[0x62])
373	pic_level \|= get_pci_irq_level(pGlobals, 2); /* PIRQC */
374	if (pic_irq == pbCfg[0x63])
375	pic_level \|= get_pci_irq_level(pGlobals, 3); /* PIRQD */
376	if (pic_irq == pGlobals->Piix3.iAcpiIrq)
377	pic_level \|= pGlobals->Piix3.iAcpiIrqLevel;
378
379	Log3Func(("%s: iLevel=%d iIrq=%d pic_irq=%d pic_level=%d uTagSrc=%#x\n",
380	R3STRING(pPciDev->pszNameR3), iLevel, iIrq, pic_irq, pic_level, uTagSrc));
381	pBusCC->CTX_SUFF(pPciHlp)->pfnIsaSetIrq(pDevIns, pic_irq, pic_level, uTagSrc);
382
383	/** @todo optimize pci irq flip-flop some rainy day. */
384	if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP)
385	pciSetIrqInternal(pDevIns, pGlobals, pBusCC, uDevFn, pPciDev, iIrq, PDM_IRQ_LEVEL_LOW, uTagSrc);
386	}
387	}
388
389
390	/**
391	* @interface_method_impl{PDMPCIBUSREGR3,pfnSetIrqR3}
392	*/
393	static DECLCALLBACK(void) pciSetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc)
394	{
395	PDEVPCIROOT pBus = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
396	PDEVPCIBUSCC pBusCC = PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC);
397	LogFlow(("pciSetIrq: %p %u %u %#x\n", pPciDev, iIrq, iLevel, uTagSrc));
398	pciSetIrqInternal(pDevIns, pBus, pBusCC, pPciDev->uDevFn, pPciDev, iIrq, iLevel, uTagSrc);
399	}
400
401	#ifdef IN_RING3
402
403	/**
404	* Finds a bridge on the bus which contains the destination bus.
405	*
406	* @return Pointer to the device instance data of the bus or
407	* NULL if no bridge was found.
408	* @param pBus Pointer to the bus to search on.
409	* @param iBus Destination bus number.
410	*/
411	DECLINLINE(PPDMPCIDEV) pciR3FindBridge(PDEVPCIBUS pBus, uint8_t iBus)
412	{
413	/* Search for a fitting bridge. */
414	for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
415	{
416	/*
417	* Examine secondary and subordinate bus number.
418	* If the target bus is in the range we pass the request on to the bridge.
419	*/
420	PPDMPCIDEV pBridgeTemp = pBus->papBridgesR3[iBridge];
421	AssertMsg(pBridgeTemp && pciDevIsPci2PciBridge(pBridgeTemp),
422	("Device is not a PCI bridge but on the list of PCI bridges\n"));
423
424	if ( iBus >= pBridgeTemp->abConfig[VBOX_PCI_SECONDARY_BUS]
425	&& iBus <= pBridgeTemp->abConfig[VBOX_PCI_SUBORDINATE_BUS])
426	return pBridgeTemp;
427	}
428
429	/* Nothing found. */
430	return NULL;
431	}
432
433	static void pciR3Piix3Reset(PPDMPCIDEV pPiix3PciDev)
434	{
435	uint8_t *pci_conf = pPiix3PciDev->abConfig;
436
437	pci_conf[0x04] = 0x07; /* master, memory and I/O */
438	pci_conf[0x05] = 0x00;
439	pci_conf[0x06] = 0x00;
440	pci_conf[0x07] = 0x02; /* PCI_status_devsel_medium */
441	pci_conf[0x4c] = 0x4d;
442	pci_conf[0x4e] = 0x03;
443	pci_conf[0x4f] = 0x00;
444	pci_conf[0x60] = 0x80;
445	pci_conf[0x69] = 0x02;
446	pci_conf[0x70] = 0x80;
447	pci_conf[0x76] = 0x0c;
448	pci_conf[0x77] = 0x0c;
449	pci_conf[0x78] = 0x02;
450	pci_conf[0x79] = 0x00;
451	pci_conf[0x80] = 0x00;
452	pci_conf[0x82] = 0x02; /* Get rid of the Linux guest "Enabling Passive Release" PCI quirk warning. */
453	pci_conf[0xa0] = 0x08;
454	pci_conf[0xa2] = 0x00;
455	pci_conf[0xa3] = 0x00;
456	pci_conf[0xa4] = 0x00;
457	pci_conf[0xa5] = 0x00;
458	pci_conf[0xa6] = 0x00;
459	pci_conf[0xa7] = 0x00;
460	pci_conf[0xa8] = 0x0f;
461	pci_conf[0xaa] = 0x00;
462	pci_conf[0xab] = 0x00;
463	pci_conf[0xac] = 0x00;
464	pci_conf[0xae] = 0x00;
465	}
466
467	/* host irqs corresponding to PCI irqs A-D */
468	static const uint8_t pci_irqs[4] = { 11, 10, 9, 11 }; /* bird: added const */
469
470	static void pci_bios_init_device(PPDMDEVINS pDevIns, PDEVPCIROOT pGlobals, PDEVPCIBUS pBus,
471	PPDMPCIDEV pPciDev, uint8_t cBridgeDepth, uint8_t *paBridgePositions)
472	{
473	uint32_t uPciBiosSpecialVRAM = 0xe0000000;
474	uint32_t *paddr;
475	int pin, pic_irq;
476	uint16_t devclass, vendor_id, device_id;
477
478	devclass = devpciR3GetWord(pPciDev, PCI_CLASS_DEVICE);
479	vendor_id = devpciR3GetWord(pPciDev, PCI_VENDOR_ID);
480	device_id = devpciR3GetWord(pPciDev, PCI_DEVICE_ID);
481
482	/* Check if device is present. */
483	if (vendor_id != 0xffff)
484	{
485	switch (devclass)
486	{
487	case 0x0101:
488	if ( (vendor_id == 0x8086)
489	&& (device_id == 0x7010 \|\| device_id == 0x7111 \|\| device_id == 0x269e))
490	{
491	/* PIIX3, PIIX4 or ICH6 IDE */
492	devpciR3SetWord(pDevIns, pPciDev, 0x40, 0x8011); /* enable IDE0 + fast timing */
493	devpciR3SetWord(pDevIns, pPciDev, 0x42, 0x8011); /* enable IDE1 + fast timing */
494	goto default_map;
495	}
496	else
497	{
498	/* IDE: we map it as in ISA mode */
499	devpciR3BiosInitSetRegionAddress(pDevIns, pBus, pPciDev, 0, 0x1f0);
500	devpciR3BiosInitSetRegionAddress(pDevIns, pBus, pPciDev, 1, 0x3f4);
501	devpciR3BiosInitSetRegionAddress(pDevIns, pBus, pPciDev, 2, 0x170);
502	devpciR3BiosInitSetRegionAddress(pDevIns, pBus, pPciDev, 3, 0x374);
503	devpciR3SetWord(pDevIns, pPciDev, PCI_COMMAND,
504	devpciR3GetWord(pPciDev, PCI_COMMAND)
505	\| PCI_COMMAND_IOACCESS);
506	}
507	break;
508	case 0x0800:
509	/* PIC */
510	vendor_id = devpciR3GetWord(pPciDev, PCI_VENDOR_ID);
511	device_id = devpciR3GetWord(pPciDev, PCI_DEVICE_ID);
512	if (vendor_id == 0x1014)
513	{
514	/* IBM */
515	if (device_id == 0x0046 \|\| device_id == 0xFFFF)
516	{
517	/* MPIC & MPIC2 */
518	devpciR3BiosInitSetRegionAddress(pDevIns, pBus, pPciDev, 0, 0x80800000 + 0x00040000);
519	devpciR3SetWord(pDevIns, pPciDev, PCI_COMMAND,
520	devpciR3GetWord(pPciDev, PCI_COMMAND)
521	\| PCI_COMMAND_MEMACCESS);
522	}
523	}
524	break;
525	case 0xff00:
526	if ( (vendor_id == 0x0106b)
527	&& (device_id == 0x0017 \|\| device_id == 0x0022))
528	{
529	/* macio bridge */
530	devpciR3BiosInitSetRegionAddress(pDevIns, pBus, pPciDev, 0, 0x80800000);
531	devpciR3SetWord(pDevIns, pPciDev, PCI_COMMAND,
532	devpciR3GetWord(pPciDev, PCI_COMMAND)
533	\| PCI_COMMAND_MEMACCESS);
534	}
535	break;
536	case 0x0604:
537	{
538	/* Init PCI-to-PCI bridge. */
539	devpciR3SetByte(pDevIns, pPciDev, VBOX_PCI_PRIMARY_BUS, pBus->iBus);
540
541	AssertMsg(pGlobals->uPciBiosBus < 255, ("Too many bridges on the bus\n"));
542	pGlobals->uPciBiosBus++;
543	devpciR3SetByte(pDevIns, pPciDev, VBOX_PCI_SECONDARY_BUS, pGlobals->uPciBiosBus);
544	devpciR3SetByte(pDevIns, pPciDev, VBOX_PCI_SUBORDINATE_BUS, 0xff); /* Temporary until we know how many other bridges are behind this one. */
545
546	/* Add position of this bridge into the array. */
547	paBridgePositions[cBridgeDepth+1] = (pPciDev->uDevFn >> 3);
548
549	/*
550	* The I/O range for the bridge must be aligned to a 4KB boundary.
551	* This does not change anything really as the access to the device is not going
552	* through the bridge but we want to be compliant to the spec.
553	*/
554	if ((pGlobals->uPciBiosIo % _4K) != 0)
555	pGlobals->uPciBiosIo = RT_ALIGN_32(pGlobals->uPciBiosIo, _4K);
556	LogFunc(("Aligned I/O start address. New address %#x\n", pGlobals->uPciBiosIo));
557	devpciR3SetByte(pDevIns, pPciDev, VBOX_PCI_IO_BASE, (pGlobals->uPciBiosIo >> 8) & 0xf0);
558
559	/* The MMIO range for the bridge must be aligned to a 1MB boundary. */
560	if ((pGlobals->uPciBiosMmio % _1M) != 0)
561	pGlobals->uPciBiosMmio = RT_ALIGN_32(pGlobals->uPciBiosMmio, _1M);
562	LogFunc(("Aligned MMIO start address. New address %#x\n", pGlobals->uPciBiosMmio));
563	devpciR3SetWord(pDevIns, pPciDev, VBOX_PCI_MEMORY_BASE, (pGlobals->uPciBiosMmio >> 16) & UINT32_C(0xffff0));
564
565	/* Save values to compare later to. */
566	uint32_t u32IoAddressBase = pGlobals->uPciBiosIo;
567	uint32_t u32MMIOAddressBase = pGlobals->uPciBiosMmio;
568
569	/* Init devices behind the bridge and possibly other bridges as well. */
570	PDEVPCIBUS pChildBus = PDMINS_2_DATA(pPciDev->Int.s.CTX_SUFF(pDevIns), PDEVPCIBUS);
571	for (uint32_t uDevFn = 0; uDevFn < RT_ELEMENTS(pChildBus->apDevices); uDevFn++)
572	{
573	PPDMPCIDEV pChildPciDev = pChildBus->apDevices[uDevFn];
574	if (pChildPciDev)
575	pci_bios_init_device(pDevIns, pGlobals, pChildBus, pChildPciDev, cBridgeDepth + 1, paBridgePositions);
576	}
577
578	/* The number of bridges behind the this one is now available. */
579	devpciR3SetByte(pDevIns, pPciDev, VBOX_PCI_SUBORDINATE_BUS, pGlobals->uPciBiosBus);
580
581	/*
582	* Set I/O limit register. If there is no device with I/O space behind the bridge
583	* we set a lower value than in the base register.
584	* The result with a real bridge is that no I/O transactions are passed to the secondary
585	* interface. Again this doesn't really matter here but we want to be compliant to the spec.
586	*/
587	if ((u32IoAddressBase != pGlobals->uPciBiosIo) && ((pGlobals->uPciBiosIo % _4K) != 0))
588	{
589	/* The upper boundary must be one byte less than a 4KB boundary. */
590	pGlobals->uPciBiosIo = RT_ALIGN_32(pGlobals->uPciBiosIo, _4K);
591	}
592	devpciR3SetByte(pDevIns, pPciDev, VBOX_PCI_IO_LIMIT, ((pGlobals->uPciBiosIo >> 8) & 0xf0) - 1);
593
594	/* Same with the MMIO limit register but with 1MB boundary here. */
595	if ((u32MMIOAddressBase != pGlobals->uPciBiosMmio) && ((pGlobals->uPciBiosMmio % _1M) != 0))
596	{
597	/* The upper boundary must be one byte less than a 1MB boundary. */
598	pGlobals->uPciBiosMmio = RT_ALIGN_32(pGlobals->uPciBiosMmio, _1M);
599	}
600	devpciR3SetWord(pDevIns, pPciDev, VBOX_PCI_MEMORY_LIMIT, ((pGlobals->uPciBiosMmio >> 16) & UINT32_C(0xfff0)) - 1);
601
602	/*
603	* Set the prefetch base and limit registers. We currently have no device with a prefetchable region
604	* which may be behind a bridge. That's why it is unconditionally disabled here atm by writing a higher value into
605	* the base register than in the limit register.
606	*/
607	devpciR3SetWord(pDevIns, pPciDev, VBOX_PCI_PREF_MEMORY_BASE, 0xfff0);
608	devpciR3SetWord(pDevIns, pPciDev, VBOX_PCI_PREF_MEMORY_LIMIT, 0x0);
609	devpciR3SetDWord(pDevIns, pPciDev, VBOX_PCI_PREF_BASE_UPPER32, 0x00);
610	devpciR3SetDWord(pDevIns, pPciDev, VBOX_PCI_PREF_LIMIT_UPPER32, 0x00);
611	break;
612	}
613	default:
614	default_map:
615	{
616	/* default memory mappings */
617	bool fActiveMemRegion = false;
618	bool fActiveIORegion = false;
619	/*
620	* PCI_NUM_REGIONS is 7 because of the rom region but there are only 6 base address register defined by the PCI spec.
621	* Leaving only PCI_NUM_REGIONS would cause reading another and enabling a memory region which does not exist.
622	*/
623	for (unsigned i = 0; i < (PCI_NUM_REGIONS-1); i++)
624	{
625	uint32_t u32Size;
626	uint8_t u8ResourceType;
627	uint32_t u32Address = 0x10 + i * 4;
628
629	/* Calculate size. */
630	u8ResourceType = devpciR3GetByte(pPciDev, u32Address);
631	devpciR3SetDWord(pDevIns, pPciDev, u32Address, UINT32_C(0xffffffff));
632	u32Size = devpciR3GetDWord(pPciDev, u32Address);
633	bool fIsPio = ((u8ResourceType & PCI_COMMAND_IOACCESS) == PCI_COMMAND_IOACCESS);
634	/* Clear resource information depending on resource type. */
635	if (fIsPio) /* I/O */
636	u32Size &= ~(0x01);
637	else /* MMIO */
638	u32Size &= ~(0x0f);
639
640	/*
641	* Invert all bits and add 1 to get size of the region.
642	* (From PCI implementation note)
643	*/
644	if (fIsPio && (u32Size & UINT32_C(0xffff0000)) == 0)
645	u32Size = (~(u32Size \| UINT32_C(0xffff0000))) + 1;
646	else
647	u32Size = (~u32Size) + 1;
648
649	Log2Func(("Size of region %u for device %d on bus %d is %u\n", i, pPciDev->uDevFn, pBus->iBus, u32Size));
650
651	if (u32Size)
652	{
653	if (fIsPio)
654	paddr = &pGlobals->uPciBiosIo;
655	else
656	{
657	paddr = &pGlobals->uPciBiosMmio;
658	if (devclass == 0x0300)
659	{
660	/*
661	* Because legacy VGA I/O ports are implicitly decoded
662	* by a VGA class device without needing a BAR, we must
663	* enable I/O decoding for such devices.
664	*/
665	fActiveIORegion = true;
666
667	if (vendor_id == 0x80ee \|\| vendor_id == 0x15ad)
668	{
669	bool fPrefetch = (u8ResourceType & ((uint8_t)(PCI_ADDRESS_SPACE_MEM_PREFETCH \| PCI_ADDRESS_SPACE_IO)))
670	== PCI_ADDRESS_SPACE_MEM_PREFETCH;
671	/* VGA: map frame buffer to default Bochs VBE address. Only
672	* needed for legacy guest drivers. */
673	if (fPrefetch)
674	paddr = &uPciBiosSpecialVRAM;
675	}
676	}
677	}
678	uint32_t uNew = *paddr;
679	uNew = (uNew + u32Size - 1) & ~(u32Size - 1);
680	if (fIsPio)
681	uNew &= UINT32_C(0xffff);
682	/* Unconditionally exclude I/O-APIC/HPET/ROM. Pessimistic, but better than causing a mess. */
683	if (!uNew \|\| (uNew <= UINT32_C(0xffffffff) && uNew + u32Size - 1 >= UINT32_C(0xfec00000)))
684	{
685	LogRel(("PCI: no space left for BAR%u of device %u/%u/%u (vendor=%#06x device=%#06x)\n",
686	i, pBus->iBus, pPciDev->uDevFn >> 3, pPciDev->uDevFn & 7, vendor_id, device_id)); /** @todo make this a VM start failure later. */
687	/* Undo the mapping mess caused by the size probing. */
688	devpciR3SetDWord(pDevIns, pPciDev, u32Address, UINT32_C(0));
689	}
690	else
691	{
692	LogFunc(("Start address of %s region %u is %#x\n", (fIsPio ? "I/O" : "MMIO"), i, uNew));
693	devpciR3BiosInitSetRegionAddress(pDevIns, pBus, pPciDev, i, uNew);
694	if (fIsPio)
695	fActiveIORegion = true;
696	else
697	fActiveMemRegion = true;
698	*paddr = uNew + u32Size;
699	Log2Func(("New address is %#x\n", *paddr));
700	}
701	}
702	}
703
704	/* Update the command word appropriately. */
705	devpciR3SetWord(pDevIns, pPciDev, PCI_COMMAND,
706	devpciR3GetWord(pPciDev, PCI_COMMAND)
707	\| (fActiveMemRegion ? PCI_COMMAND_MEMACCESS : 0)
708	\| (fActiveIORegion ? PCI_COMMAND_IOACCESS : 0));
709
710	break;
711	}
712	}
713
714	/* map the interrupt */
715	pin = devpciR3GetByte(pPciDev, PCI_INTERRUPT_PIN);
716	if (pin != 0)
717	{
718	uint8_t uBridgeDevFn = pPciDev->uDevFn;
719	pin--;
720
721	/* We need to go up to the host bus to see which irq this device will assert there. */
722	while (cBridgeDepth != 0)
723	{
724	/* Get the pin the device would assert on the bridge. */
725	pin = ((uBridgeDevFn >> 3) + pin) & 3;
726	uBridgeDevFn = paBridgePositions[cBridgeDepth];
727	cBridgeDepth--;
728	}
729
730	pin = pci_slot_get_pirq(pPciDev->uDevFn, pin);
731	pic_irq = pci_irqs[pin];
732	devpciR3SetByte(pDevIns, pPciDev, PCI_INTERRUPT_LINE, pic_irq);
733	}
734	}
735	}
736
737	/**
738	* Worker for Fake PCI BIOS config, triggered by magic port access by BIOS.
739	*
740	* @returns VBox status code.
741	*
742	* @param pDevIns i440FX device instance.
743	*/
744	static int pciR3FakePCIBIOS(PPDMDEVINS pDevIns)
745	{
746	uint8_t elcr[2] = {0, 0};
747	PDEVPCIROOT pGlobals = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
748	PVM pVM = PDMDevHlpGetVM(pDevIns); Assert(pVM);
749	PVMCPU pVCpu = PDMDevHlpGetVMCPU(pDevIns); Assert(pVM);
750	uint32_t const cbBelow4GB = MMR3PhysGetRamSizeBelow4GB(pVM);
751	uint64_t const cbAbove4GB = MMR3PhysGetRamSizeAbove4GB(pVM);
752	RT_NOREF(cbBelow4GB, cbAbove4GB);
753
754	LogRel(("PCI: Setting up resources and interrupts\n"));
755
756	/*
757	* Set the start addresses.
758	*/
759	pGlobals->uPciBiosBus = 0;
760	pGlobals->uPciBiosIo = 0xd000;
761	pGlobals->uPciBiosMmio = UINT32_C(0xf0000000);
762
763	/*
764	* Activate IRQ mappings.
765	*/
766	PPDMPCIDEV pPIIX3 = pDevIns->apPciDevs[1];
767	for (unsigned i = 0; i < 4; i++)
768	{
769	uint8_t irq = pci_irqs[i];
770	/* Set to trigger level. */
771	elcr[irq >> 3] \|= (1 << (irq & 7));
772	/* Activate irq remapping in PIIX3. */
773	devpciR3SetByte(pDevIns, pPIIX3, 0x60 + i, irq);
774	}
775
776	/* Tell to the PIC. */
777	VBOXSTRICTRC rcStrict = IOMIOPortWrite(pVM, pVCpu, 0x4d0, elcr[0], sizeof(uint8_t));
778	if (rcStrict == VINF_SUCCESS)
779	rcStrict = IOMIOPortWrite(pVM, pVCpu, 0x4d1, elcr[1], sizeof(uint8_t));
780	if (rcStrict != VINF_SUCCESS)
781	{
782	AssertMsgFailed(("Writing to PIC failed! rcStrict=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
783	return RT_SUCCESS(rcStrict) ? VERR_INTERNAL_ERROR : VBOXSTRICTRC_VAL(rcStrict);
784	}
785
786	/*
787	* Init the devices.
788	*/
789	PDEVPCIBUS pBus = &pGlobals->PciBus;
790	for (uint32_t uDevFn = 0; uDevFn < RT_ELEMENTS(pBus->apDevices); uDevFn++)
791	{
792	PPDMPCIDEV pPciDev = pBus->apDevices[uDevFn];
793	if (pPciDev)
794	{
795	Log2(("PCI: Initializing device %d (%#x)\n", uDevFn, 0x80000000 \| (uDevFn << 8)));
796	uint8_t aBridgePositions[256];
797	RT_ZERO(aBridgePositions);
798	pci_bios_init_device(pDevIns, pGlobals, pBus, pPciDev, 0, aBridgePositions);
799	}
800	}
801
802	return VINF_SUCCESS;
803	}
804
805	#endif /* IN_RING3 */
806
807
808	/* -=-=-=-=-=- I/O ports -=-=-=-=-=- */
809
810	/**
811	* @callback_method_impl{FNIOMIOPORTNEWOUT, PCI address}
812	*/
813	static DECLCALLBACK(VBOXSTRICTRC)
814	pciIOPortAddressWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
815	{
816	LogFunc(("offPort=%#x u32=%#x cb=%d\n", offPort, u32, cb));
817	Assert(offPort == 0); RT_NOREF2(offPort, pvUser);
818	if (cb == 4)
819	{
820	PDEVPCIROOT pThis = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
821	PCI_LOCK_RET(pDevIns, VINF_IOM_R3_IOPORT_WRITE);
822	pThis->uConfigReg = u32 & ~3; /* Bits 0-1 are reserved and we silently clear them */
823	PCI_UNLOCK(pDevIns);
824	}
825	/* else: 440FX does "pass through to the bus" for other writes, what ever that means.
826	* Linux probes for cmd640 using byte writes/reads during ide init. We'll just ignore it. */
827	return VINF_SUCCESS;
828	}
829
830
831	/**
832	* @callback_method_impl{FNIOMIOPORTNEWIN, PCI address}
833	*/
834	static DECLCALLBACK(VBOXSTRICTRC)
835	pciIOPortAddressRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT offPort, uint32_t pu32, unsigned cb)
836	{
837	Assert(offPort == 0); RT_NOREF2(offPort, pvUser);
838	if (cb == 4)
839	{
840	PDEVPCIROOT pThis = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
841	PCI_LOCK_RET(pDevIns, VINF_IOM_R3_IOPORT_READ);
842	*pu32 = pThis->uConfigReg;
843	PCI_UNLOCK(pDevIns);
844	LogFunc(("offPort=%#x cb=%d -> %#x\n", offPort, cb, *pu32));
845	return VINF_SUCCESS;
846	}
847	/* else: 440FX does "pass through to the bus" for other writes, what ever that means.
848	* Linux probes for cmd640 using byte writes/reads during ide init. We'll just ignore it. */
849	LogFunc(("offPort=%#x cb=%d VERR_IOM_IOPORT_UNUSED\n", offPort, cb));
850	return VERR_IOM_IOPORT_UNUSED;
851	}
852
853
854	/**
855	* @callback_method_impl{FNIOMIOPORTNEWOUT, PCI data}
856	*/
857	static DECLCALLBACK(VBOXSTRICTRC)
858	pciIOPortDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
859	{
860	LogFunc(("offPort=%#x u32=%#x cb=%d\n", offPort, u32, cb));
861	Assert(offPort < 4); NOREF(pvUser);
862	VBOXSTRICTRC rcStrict = VINF_SUCCESS;
863	if (!(offPort % cb))
864	{
865	PCI_LOCK_RET(pDevIns, VINF_IOM_R3_IOPORT_WRITE);
866	rcStrict = pci_data_write(pDevIns, PDMINS_2_DATA(pDevIns, PDEVPCIROOT), offPort, u32, cb);
867	PCI_UNLOCK(pDevIns);
868	}
869	else
870	AssertMsgFailed(("Write to port %#x u32=%#x cb=%d\n", offPort, u32, cb));
871	return rcStrict;
872	}
873
874
875	/**
876	* @callback_method_impl{FNIOMIOPORTNEWIN, PCI data}
877	*/
878	static DECLCALLBACK(VBOXSTRICTRC)
879	pciIOPortDataRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT offPort, uint32_t pu32, unsigned cb)
880	{
881	Assert(offPort < 4); NOREF(pvUser);
882	if (!(offPort % cb))
883	{
884	PCI_LOCK_RET(pDevIns, VINF_IOM_R3_IOPORT_READ);
885	VBOXSTRICTRC rcStrict = pci_data_read(PDMINS_2_DATA(pDevIns, PDEVPCIROOT), offPort, cb, pu32);
886	PCI_UNLOCK(pDevIns);
887	LogFunc(("offPort=%#x cb=%#x -> %#x (%Rrc)\n", offPort, cb, *pu32, VBOXSTRICTRC_VAL(rcStrict)));
888	return rcStrict;
889	}
890	AssertMsgFailed(("Read from port %#x cb=%d\n", offPort, cb));
891	return VERR_IOM_IOPORT_UNUSED;
892	}
893
894	#ifdef IN_RING3
895
896	/**
897	* @callback_method_impl{FNIOMIOPORTNEWOUT, PCI data}
898	*/
899	static DECLCALLBACK(VBOXSTRICTRC)
900	pciR3IOPortMagicPCIWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
901	{
902	Assert(offPort == 0); RT_NOREF2(pvUser, offPort);
903	LogFunc(("offPort=%#x u32=%#x cb=%d\n", offPort, u32, cb));
904	if (cb == 4)
905	{
906	if (u32 == UINT32_C(19200509)) // Richard Adams - Note! In decimal rather hex.
907	{
908	int rc = pciR3FakePCIBIOS(pDevIns);
909	AssertRC(rc);
910	}
911	}
912
913	return VINF_SUCCESS;
914	}
915
916	/**
917	* @callback_method_impl{FNIOMIOPORTNEWIN, PCI data}
918	*/
919	static DECLCALLBACK(VBOXSTRICTRC)
920	pciR3IOPortMagicPCIRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT offPort, uint32_t pu32, unsigned cb)
921	{
922	Assert(offPort == 0); RT_NOREF5(pDevIns, pvUser, offPort, pu32, cb);
923	LogFunc(("offPort=%#x cb=%d VERR_IOM_IOPORT_UNUSED\n", offPort, cb));
924	return VERR_IOM_IOPORT_UNUSED;
925	}
926
927
928	/* -=-=-=-=-=- Saved state -=-=-=-=-=- */
929
930	/**
931	* Common worker for pciR3SaveExec and pcibridgeR3SaveExec.
932	*
933	* @returns VBox status code.
934	* @param pHlp The device helpers.
935	* @param pBus The bus to save.
936	* @param pSSM The saved state handle.
937	*/
938	static int pciR3CommonSaveExec(PCPDMDEVHLPR3 pHlp, PDEVPCIBUS pBus, PSSMHANDLE pSSM)
939	{
940	/*
941	* Iterate thru all the devices.
942	*/
943	for (uint32_t uDevFn = 0; uDevFn < RT_ELEMENTS(pBus->apDevices); uDevFn++)
944	{
945	PPDMPCIDEV pDev = pBus->apDevices[uDevFn];
946	if (pDev)
947	{
948	pHlp->pfnSSMPutU32(pSSM, uDevFn);
949	pHlp->pfnSSMPutMem(pSSM, pDev->abConfig, 256); /* Only save 256 bytes here! */
950
951	pHlp->pfnSSMPutS32(pSSM, pDev->Int.s.uIrqPinState);
952
953	/* Save the type an size of all the regions. */
954	for (uint32_t iRegion = 0; iRegion < VBOX_PCI_NUM_REGIONS; iRegion++)
955	{
956	pHlp->pfnSSMPutU8(pSSM, pDev->Int.s.aIORegions[iRegion].type);
957	pHlp->pfnSSMPutU64(pSSM, pDev->Int.s.aIORegions[iRegion].size);
958	}
959	}
960	}
961	return pHlp->pfnSSMPutU32(pSSM, UINT32_MAX); /* terminator */
962	}
963
964
965	/**
966	* @callback_method_impl{FNSSMDEVSAVEEXEC}
967	*/
968	static DECLCALLBACK(int) pciR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
969	{
970	PDEVPCIROOT pThis = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
971	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
972
973	/*
974	* Bus state data.
975	*/
976	pHlp->pfnSSMPutU32(pSSM, pThis->uConfigReg);
977	pHlp->pfnSSMPutBool(pSSM, pThis->fUseIoApic);
978
979	/*
980	* Save IRQ states.
981	*/
982	for (unsigned i = 0; i < RT_ELEMENTS(pThis->Piix3.auPciLegacyIrqLevels); i++)
983	pHlp->pfnSSMPutU32(pSSM, pThis->Piix3.auPciLegacyIrqLevels[i]);
984	for (unsigned i = 0; i < RT_ELEMENTS(pThis->auPciApicIrqLevels); i++)
985	pHlp->pfnSSMPutU32(pSSM, pThis->auPciApicIrqLevels[i]);
986
987	pHlp->pfnSSMPutU32(pSSM, pThis->Piix3.iAcpiIrqLevel);
988	pHlp->pfnSSMPutS32(pSSM, pThis->Piix3.iAcpiIrq);
989
990	pHlp->pfnSSMPutU32(pSSM, UINT32_MAX); /* separator */
991
992	/*
993	* Join paths with pcibridgeR3SaveExec.
994	*/
995	return pciR3CommonSaveExec(pHlp, &pThis->PciBus, pSSM);
996	}
997
998
999	/**
1000	* Common worker for pciR3LoadExec and pcibridgeR3LoadExec.
1001	*
1002	* @returns VBox status code.
1003	* @param pDevIns The device instance.
1004	* @param pBus The bus which data is being loaded.
1005	* @param pSSM The saved state handle.
1006	* @param uVersion The data version.
1007	* @param uPass The pass.
1008	*/
1009	static int pciR3CommonLoadExec(PPDMDEVINS pDevIns, PDEVPCIBUS pBus, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1010	{
1011	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
1012	uint32_t u32;
1013	int rc;
1014
1015	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
1016
1017	/*
1018	* Iterate thru all the devices and write 0 to the COMMAND register so
1019	* that all the memory is unmapped before we start restoring the saved
1020	* mapping locations.
1021	*
1022	* The register value is restored afterwards so we can do proper
1023	* LogRels in devpciR3CommonRestoreConfig.
1024	*/
1025	for (uint32_t uDevFn = 0; uDevFn < RT_ELEMENTS(pBus->apDevices); uDevFn++)
1026	{
1027	PPDMPCIDEV pDev = pBus->apDevices[uDevFn];
1028	if (pDev)
1029	{
1030	uint16_t u16 = PCIDevGetCommand(pDev);
1031	devpciR3SetCfg(pDevIns, pDev, VBOX_PCI_COMMAND, 0 /u32Value/, 2 /cb/);
1032	PCIDevSetCommand(pDev, u16);
1033	Assert(PCIDevGetCommand(pDev) == u16);
1034	}
1035	}
1036
1037	/*
1038	* Iterate all the devices.
1039	*/
1040	for (uint32_t uDevFn = 0;; uDevFn++)
1041	{
1042	/* index / terminator */
1043	rc = pHlp->pfnSSMGetU32(pSSM, &u32);
1044	if (RT_FAILURE(rc))
1045	return rc;
1046	if (u32 == UINT32_MAX)
1047	break;
1048	if ( u32 >= RT_ELEMENTS(pBus->apDevices)
1049	\|\| u32 < uDevFn)
1050	{
1051	AssertMsgFailed(("u32=%#x uDevFn=%#x\n", u32, uDevFn));
1052	return rc;
1053	}
1054
1055	/* skip forward to the device checking that no new devices are present. */
1056	for (; uDevFn < u32; uDevFn++)
1057	{
1058	if (pBus->apDevices[uDevFn])
1059	{
1060	LogRel(("PCI: New device in slot %#x, %s (vendor=%#06x device=%#06x)\n", uDevFn, pBus->apDevices[uDevFn]->pszNameR3,
1061	PCIDevGetVendorId(pBus->apDevices[uDevFn]), PCIDevGetDeviceId(pBus->apDevices[uDevFn])));
1062	if (pHlp->pfnSSMHandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT)
1063	return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS, N_("New device in slot %#x, %s (vendor=%#06x device=%#06x)"),
1064	uDevFn, pBus->apDevices[uDevFn]->pszNameR3, PCIDevGetVendorId(pBus->apDevices[uDevFn]), PCIDevGetDeviceId(pBus->apDevices[uDevFn]));
1065	}
1066	}
1067
1068	/* get the data */
1069	union
1070	{
1071	PDMPCIDEV DevTmp;
1072	uint8_t abDevTmpPadding[RT_UOFFSETOF(PDMPCIDEV, abMsixState)];
1073	} u;
1074	RT_ZERO(u.DevTmp);
1075	u.DevTmp.Int.s.uIrqPinState = ~0; /* Invalid value in case we have an older saved state to force a state change in pciSetIrq. */
1076	pHlp->pfnSSMGetMem(pSSM, u.DevTmp.abConfig, 256);
1077	if (uVersion < VBOX_PCI_SAVED_STATE_VERSION_IRQ_STATES)
1078	{
1079	int32_t i32Temp;
1080	/* Irq value not needed anymore. */
1081	rc = pHlp->pfnSSMGetS32(pSSM, &i32Temp);
1082	if (RT_FAILURE(rc))
1083	return rc;
1084	}
1085	else
1086	{
1087	rc = pHlp->pfnSSMGetS32(pSSM, &u.DevTmp.Int.s.uIrqPinState);
1088	if (RT_FAILURE(rc))
1089	return rc;
1090	}
1091
1092	/* Load the region types and sizes. */
1093	if (uVersion >= VBOX_PCI_SAVED_STATE_VERSION_REGION_SIZES)
1094	{
1095	for (uint32_t iRegion = 0; iRegion < VBOX_PCI_NUM_REGIONS; iRegion++)
1096	{
1097	pHlp->pfnSSMGetU8(pSSM, &u.DevTmp.Int.s.aIORegions[iRegion].type);
1098	rc = pHlp->pfnSSMGetU64(pSSM, &u.DevTmp.Int.s.aIORegions[iRegion].size);
1099	AssertLogRelRCReturn(rc, rc);
1100	}
1101	}
1102
1103	/* check that it's still around. */
1104	PPDMPCIDEV pDev = pBus->apDevices[uDevFn];
1105	if (!pDev)
1106	{
1107	LogRel(("PCI: Device in slot %#x has been removed! vendor=%#06x device=%#06x\n", uDevFn,
1108	PCIDevGetVendorId(&u.DevTmp), PCIDevGetDeviceId(&u.DevTmp)));
1109	if (pHlp->pfnSSMHandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT)
1110	return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS, N_("Device in slot %#x has been removed! vendor=%#06x device=%#06x"),
1111	uDevFn, PCIDevGetVendorId(&u.DevTmp), PCIDevGetDeviceId(&u.DevTmp));
1112	continue;
1113	}
1114
1115	/* match the vendor id assuming that this will never be changed. */
1116	if ( u.DevTmp.abConfig[0] != pDev->abConfig[0]
1117	\|\| u.DevTmp.abConfig[1] != pDev->abConfig[1])
1118	return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS,
1119	N_("Device in slot %#x (%s) vendor id mismatch! saved=%.4Rhxs current=%.4Rhxs"),
1120	uDevFn, pDev->pszNameR3, u.DevTmp.abConfig, pDev->abConfig);
1121
1122	/* commit the loaded device config. */
1123	rc = devpciR3CommonRestoreRegions(pSSM, pDev, u.DevTmp.Int.s.aIORegions,
1124	uVersion >= VBOX_PCI_SAVED_STATE_VERSION_REGION_SIZES);
1125	if (RT_FAILURE(rc))
1126	break;
1127	devpciR3CommonRestoreConfig(pDevIns, pDev, &u.DevTmp.abConfig[0]);
1128
1129	pDev->Int.s.uIrqPinState = u.DevTmp.Int.s.uIrqPinState;
1130	}
1131
1132	return VINF_SUCCESS;
1133	}
1134
1135
1136	/**
1137	* @callback_method_impl{FNSSMDEVLOADEXEC}
1138	*/
1139	static DECLCALLBACK(int) pciR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1140	{
1141	PDEVPCIROOT pThis = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
1142	PDEVPCIBUS pBus = &pThis->PciBus;
1143	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
1144	uint32_t u32;
1145	int rc;
1146
1147	/*
1148	* Check the version.
1149	*/
1150	if (uVersion > VBOX_PCI_SAVED_STATE_VERSION)
1151	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1152	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
1153
1154	/*
1155	* Bus state data.
1156	*/
1157	pHlp->pfnSSMGetU32(pSSM, &pThis->uConfigReg);
1158	if (uVersion >= VBOX_PCI_SAVED_STATE_VERSION_USE_IO_APIC)
1159	pHlp->pfnSSMGetBool(pSSM, &pThis->fUseIoApic);
1160
1161	/* Load IRQ states. */
1162	if (uVersion >= VBOX_PCI_SAVED_STATE_VERSION_IRQ_STATES)
1163	{
1164	for (uint8_t i = 0; i < RT_ELEMENTS(pThis->Piix3.auPciLegacyIrqLevels); i++)
1165	pHlp->pfnSSMGetU32V(pSSM, &pThis->Piix3.auPciLegacyIrqLevels[i]);
1166	for (uint8_t i = 0; i < RT_ELEMENTS(pThis->auPciApicIrqLevels); i++)
1167	pHlp->pfnSSMGetU32V(pSSM, &pThis->auPciApicIrqLevels[i]);
1168
1169	pHlp->pfnSSMGetU32(pSSM, &pThis->Piix3.iAcpiIrqLevel);
1170	pHlp->pfnSSMGetS32(pSSM, &pThis->Piix3.iAcpiIrq);
1171	}
1172
1173	/* separator */
1174	rc = pHlp->pfnSSMGetU32(pSSM, &u32);
1175	if (RT_FAILURE(rc))
1176	return rc;
1177	if (u32 != UINT32_MAX)
1178	AssertMsgFailedReturn(("u32=%#x\n", u32), rc);
1179
1180	/*
1181	* The devices.
1182	*/
1183	return pciR3CommonLoadExec(pDevIns, pBus, pSSM, uVersion, uPass);
1184	}
1185
1186
1187	/* -=-=-=-=-=- PCI Bus Interface Methods (PDMPCIBUSREG) -=-=-=-=-=- */
1188
1189
1190	/* -=-=-=-=-=- Debug Info Handlers -=-=-=-=-=- */
1191
1192	/**
1193	* @callback_method_impl{FNDBGFHANDLERDEV}
1194	*/
1195	static DECLCALLBACK(void) pciR3IrqRouteInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
1196	{
1197	PPDMPCIDEV pPIIX3 = pDevIns->apPciDevs[1];
1198	NOREF(pszArgs);
1199
1200	uint16_t router = pPIIX3->uDevFn;
1201	pHlp->pfnPrintf(pHlp, "PCI interrupt router at: %02X:%02X:%X\n",
1202	router >> 8, (router >> 3) & 0x1f, router & 0x7);
1203
1204	for (int i = 0; i < 4; ++i)
1205	{
1206	uint8_t irq_map = devpciR3GetByte(pPIIX3, 0x60 + i);
1207	if (irq_map & 0x80)
1208	pHlp->pfnPrintf(pHlp, "PIRQ%c disabled\n", 'A' + i);
1209	else
1210	pHlp->pfnPrintf(pHlp, "PIRQ%c -> IRQ%d\n", 'A' + i, irq_map & 0xf);
1211	}
1212	}
1213
1214	/**
1215	* @callback_method_impl{FNDBGFHANDLERDEV, 'pirq'}
1216	*/
1217	DECLCALLBACK(void) devpciR3InfoPIRQ(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
1218	{
1219	PDEVPCIROOT pGlobals = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
1220	NOREF(pszArgs);
1221
1222	pHlp->pfnPrintf(pHlp, "PCI IRQ levels:\n");
1223	for (int i = 0; i < DEVPCI_LEGACY_IRQ_PINS; ++i)
1224	pHlp->pfnPrintf(pHlp, " IRQ%c: %u\n", 'A' + i, pGlobals->Piix3.auPciLegacyIrqLevels[i]);
1225	}
1226
1227
1228	/* -=-=-=-=-=- PDMDEVREG -=-=-=-=-=- */
1229
1230	/**
1231	* @interface_method_impl{PDMDEVREG,pfnReset}
1232	*/
1233	static DECLCALLBACK(void) pciR3Reset(PPDMDEVINS pDevIns)
1234	{
1235	PDEVPCIROOT pGlobals = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
1236	PDEVPCIBUS pBus = &pGlobals->PciBus;
1237
1238	/* PCI-specific reset for each device. */
1239	for (uint32_t uDevFn = 0; uDevFn < RT_ELEMENTS(pBus->apDevices); uDevFn++)
1240	{
1241	if (pBus->apDevices[uDevFn])
1242	devpciR3ResetDevice(pDevIns, pBus->apDevices[uDevFn]);
1243	}
1244
1245	pciR3Piix3Reset(pDevIns->apPciDevs[1]);
1246	}
1247
1248
1249	/**
1250	* @interface_method_impl{PDMDEVREG,pfnDestruct}
1251	*/
1252	static DECLCALLBACK(int) pciR3Destruct(PPDMDEVINS pDevIns)
1253	{
1254	PDEVPCIROOT pGlobals = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
1255	if (pGlobals->PciBus.papBridgesR3)
1256	{
1257	PDMDevHlpMMHeapFree(pDevIns, pGlobals->PciBus.papBridgesR3);
1258	pGlobals->PciBus.papBridgesR3 = NULL;
1259	}
1260	return VINF_SUCCESS;
1261	}
1262
1263
1264	/**
1265	* @interface_method_impl{PDMDEVREG,pfnConstruct}
1266	*/
1267	static DECLCALLBACK(int) pciR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
1268	{
1269	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
1270	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
1271	PDEVPCIBUSCC pBusCC = PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC);
1272	PDEVPCIROOT pGlobals = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
1273	RT_NOREF(iInstance);
1274	Assert(iInstance == 0);
1275
1276	/*
1277	* Validate and read configuration.
1278	*/
1279	PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "IOAPIC", "");
1280
1281	/* query whether we got an IOAPIC */
1282	bool fUseIoApic;
1283	int rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "IOAPIC", &fUseIoApic, false);
1284	if (RT_FAILURE(rc))
1285	return PDMDEV_SET_ERROR(pDevIns, rc,
1286	N_("Configuration error: Failed to query boolean value \"IOAPIC\""));
1287
1288	Log(("PCI: fUseIoApic=%RTbool fR0Enabled=%RTbool fRCEnabled=%RTbool\n", fUseIoApic, pDevIns->fR0Enabled, pDevIns->fRCEnabled));
1289
1290	/*
1291	* Init data and register the PCI bus.
1292	*/
1293	pGlobals->uPciBiosIo = 0xc000;
1294	pGlobals->uPciBiosMmio = 0xf0000000;
1295	memset((void *)&pGlobals->Piix3.auPciLegacyIrqLevels, 0, sizeof(pGlobals->Piix3.auPciLegacyIrqLevels));
1296	pGlobals->fUseIoApic = fUseIoApic;
1297	memset((void *)&pGlobals->auPciApicIrqLevels, 0, sizeof(pGlobals->auPciApicIrqLevels));
1298
1299	pGlobals->PciBus.fTypePiix3 = true;
1300	pGlobals->PciBus.fTypeIch9 = false;
1301	pGlobals->PciBus.fPureBridge = false;
1302	pGlobals->PciBus.papBridgesR3 = (PPDMPCIDEV *)PDMDevHlpMMHeapAllocZ(pDevIns,
1303	sizeof(PPDMPCIDEV)
1304	* RT_ELEMENTS(pGlobals->PciBus.apDevices));
1305	AssertLogRelReturn(pGlobals->PciBus.papBridgesR3, VERR_NO_MEMORY);
1306
1307	PDEVPCIBUS pBus = &pGlobals->PciBus;
1308	PDMPCIBUSREGCC PciBusReg;
1309	PciBusReg.u32Version = PDM_PCIBUSREGCC_VERSION;
1310	PciBusReg.pfnRegisterR3 = devpciR3CommonRegisterDevice;
1311	PciBusReg.pfnRegisterMsiR3 = NULL;
1312	PciBusReg.pfnIORegionRegisterR3 = devpciR3CommonIORegionRegister;
1313	PciBusReg.pfnInterceptConfigAccesses = devpciR3CommonInterceptConfigAccesses;
1314	PciBusReg.pfnConfigRead = devpciR3CommonConfigRead;
1315	PciBusReg.pfnConfigWrite = devpciR3CommonConfigWrite;
1316	PciBusReg.pfnSetIrqR3 = pciSetIrq;
1317	PciBusReg.u32EndVersion = PDM_PCIBUSREGCC_VERSION;
1318	rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBusCC->pPciHlpR3, &pBus->iBus);
1319	if (RT_FAILURE(rc))
1320	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to register ourselves as a PCI Bus"));
1321	Assert(pBus->iBus == 0);
1322	if (pBusCC->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
1323	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
1324	N_("PCI helper version mismatch; got %#x expected %#x"),
1325	pBusCC->pPciHlpR3->u32Version, PDM_PCIHLPR3_VERSION);
1326
1327	/* Disable default device locking. */
1328	rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
1329	AssertRCReturn(rc, rc);
1330
1331	/*
1332	* Fill in PCI configs and add them to the bus.
1333	*/
1334	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1335	AssertPtr(pPciDev);
1336
1337	/* i440FX */
1338	PCIDevSetVendorId( pPciDev, 0x8086); /* Intel */
1339	PCIDevSetDeviceId( pPciDev, 0x1237);
1340	PCIDevSetRevisionId(pPciDev, 0x02);
1341	PCIDevSetClassSub( pPciDev, 0x00); /* host2pci */
1342	PCIDevSetClassBase( pPciDev, 0x06); /* PCI_bridge */
1343	PCIDevSetHeaderType(pPciDev, 0x00);
1344	rc = PDMDevHlpPCIRegisterEx(pDevIns, pPciDev, 0 /fFlags/, 0 /uPciDevNo/, 0 /uPciFunNo/, "i440FX");
1345	AssertLogRelRCReturn(rc, rc);
1346
1347	/* PIIX3 */
1348	PPDMPCIDEV pPiix3PciDev = pDevIns->apPciDevs[1];
1349	PCIDevSetVendorId( pPiix3PciDev, 0x8086); /* Intel */
1350	PCIDevSetDeviceId( pPiix3PciDev, 0x7000); /* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */
1351	PCIDevSetClassSub( pPiix3PciDev, 0x01); /* PCI_ISA */
1352	PCIDevSetClassBase( pPiix3PciDev, 0x06); /* PCI_bridge */
1353	PCIDevSetHeaderType(pPiix3PciDev, 0x80); /* PCI_multifunction, generic */
1354	rc = PDMDevHlpPCIRegisterEx(pDevIns, pPiix3PciDev, 0 /fFlags/, 1 /uPciDevNo/, 0 /uPciFunNo/, "PIIX3");
1355	AssertLogRelRCReturn(rc, rc);
1356	pciR3Piix3Reset(pDevIns->apPciDevs[1]);
1357
1358	pBus->iDevSearch = 16;
1359
1360	/*
1361	* Register I/O ports and save state.
1362	*/
1363	static const IOMIOPORTDESC s_aAddrDesc[] = { { "PCI address", "PCI address", NULL, NULL }, { NULL, NULL, NULL, NULL } };
1364	rc = PDMDevHlpIoPortCreateAndMap(pDevIns, 0x0cf8, 1, pciIOPortAddressWrite, pciIOPortAddressRead, "i440FX (PCI)", s_aAddrDesc,
1365	&pGlobals->hIoPortAddress);
1366	AssertLogRelRCReturn(rc, rc);
1367
1368	static const IOMIOPORTDESC s_aDataDesc[] = { { "PCI data", "PCI data", NULL, NULL }, { NULL, NULL, NULL, NULL } };
1369	rc = PDMDevHlpIoPortCreateAndMap(pDevIns, 0x0cfc, 4, pciIOPortDataWrite, pciIOPortDataRead, "i440FX (PCI)", s_aDataDesc,
1370	&pGlobals->hIoPortData);
1371	AssertLogRelRCReturn(rc, rc);
1372
1373	static const IOMIOPORTDESC s_aMagicDesc[] = { { "PCI magic", NULL, NULL, NULL }, { NULL, NULL, NULL, NULL } };
1374	rc = PDMDevHlpIoPortCreateAndMap(pDevIns, 0x0410, 1, pciR3IOPortMagicPCIWrite, pciR3IOPortMagicPCIRead,
1375	"i440FX (Fake PCI BIOS trigger)", s_aMagicDesc, &pGlobals->hIoPortMagic);
1376	AssertLogRelRCReturn(rc, rc);
1377
1378
1379	rc = PDMDevHlpSSMRegisterEx(pDevIns, VBOX_PCI_SAVED_STATE_VERSION, sizeof(pBus) + 16128, "pgm",
1380	NULL, NULL, NULL,
1381	NULL, pciR3SaveExec, NULL,
1382	NULL, pciR3LoadExec, NULL);
1383	AssertLogRelRCReturn(rc, rc);
1384
1385	PDMDevHlpDBGFInfoRegister(pDevIns, "pci",
1386	"Display PCI bus status. Recognizes 'basic' or 'verbose' as arguments, defaults to 'basic'.",
1387	devpciR3InfoPci);
1388	PDMDevHlpDBGFInfoRegister(pDevIns, "pciirq", "Display PCI IRQ state. (no arguments)", devpciR3InfoPciIrq);
1389	PDMDevHlpDBGFInfoRegister(pDevIns, "pirq", "Display PIRQ state. (no arguments)", devpciR3InfoPIRQ);
1390	PDMDevHlpDBGFInfoRegister(pDevIns, "irqroute", "Display PCI IRQ routing. (no arguments)", pciR3IrqRouteInfo);
1391
1392	return VINF_SUCCESS;
1393	}
1394
1395	#else /* !IN_RING3 */
1396
1397	/**
1398	* @interface_method_impl{PDMDEVREGR0,pfnConstruct}
1399	*/
1400	static DECLCALLBACK(int) pciRZRootConstruct(PPDMDEVINS pDevIns)
1401	{
1402	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
1403	PDEVPCIROOT pGlobals = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
1404	PDEVPCIBUSCC pBusCC = PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC);
1405
1406	/* Mirror the ring-3 device lock disabling: */
1407	int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
1408	AssertRCReturn(rc, rc);
1409
1410	/* Set up the RZ PCI bus callbacks: */
1411	PDMPCIBUSREGCC PciBusReg;
1412	PciBusReg.u32Version = PDM_PCIBUSREGCC_VERSION;
1413	PciBusReg.iBus = pGlobals->PciBus.iBus;
1414	PciBusReg.pfnSetIrq = pciSetIrq;
1415	PciBusReg.u32EndVersion = PDM_PCIBUSREGCC_VERSION;
1416	rc = PDMDevHlpPCIBusSetUpContext(pDevIns, &PciBusReg, &pBusCC->CTX_SUFF(pPciHlp));
1417	AssertRCReturn(rc, rc);
1418
1419	/* Set up I/O port callbacks, except for the magic port: */
1420	rc = PDMDevHlpIoPortSetUpContext(pDevIns, pGlobals->hIoPortAddress, pciIOPortAddressWrite, pciIOPortAddressRead, NULL);
1421	AssertLogRelRCReturn(rc, rc);
1422
1423	rc = PDMDevHlpIoPortSetUpContext(pDevIns, pGlobals->hIoPortData, pciIOPortDataWrite, pciIOPortDataRead, NULL);
1424	AssertLogRelRCReturn(rc, rc);
1425
1426	return rc;
1427	}
1428
1429	#endif /* !IN_RING3 */
1430
1431	/**
1432	* The device registration structure.
1433	*/
1434	const PDMDEVREG g_DevicePCI =
1435	{
1436	/* .u32Version = */ PDM_DEVREG_VERSION,
1437	/* .uReserved0 = */ 0,
1438	/* .szName = */ "pci",
1439	/* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RZ \| PDM_DEVREG_FLAGS_NEW_STYLE,
1440	/* .fClass = */ PDM_DEVREG_CLASS_BUS_PCI,
1441	/* .cMaxInstances = */ 1,
1442	/* .uSharedVersion = */ 42,
1443	/* .cbInstanceShared = */ sizeof(DEVPCIROOT),
1444	/* .cbInstanceCC = */ sizeof(CTX_SUFF(DEVPCIBUS)),
1445	/* .cbInstanceRC = */ sizeof(DEVPCIBUSRC),
1446	/* .cMaxPciDevices = */ 2,
1447	/* .cMaxMsixVectors = */ 0,
1448	/* .pszDescription = */ "i440FX PCI bridge and PIIX3 ISA bridge.",
1449	#if defined(IN_RING3)
1450	/* .pszRCMod = */ "VBoxDDRC.rc",
1451	/* .pszR0Mod = */ "VBoxDDR0.r0",
1452	/* .pfnConstruct = */ pciR3Construct,
1453	/* .pfnDestruct = */ pciR3Destruct,
1454	/* .pfnRelocate = */ NULL,
1455	/* .pfnMemSetup = */ NULL,
1456	/* .pfnPowerOn = */ NULL,
1457	/* .pfnReset = */ pciR3Reset,
1458	/* .pfnSuspend = */ NULL,
1459	/* .pfnResume = */ NULL,
1460	/* .pfnAttach = */ NULL,
1461	/* .pfnDetach = */ NULL,
1462	/* .pfnQueryInterface = */ NULL,
1463	/* .pfnInitComplete = */ NULL,
1464	/* .pfnPowerOff = */ NULL,
1465	/* .pfnSoftReset = */ NULL,
1466	/* .pfnReserved0 = */ NULL,
1467	/* .pfnReserved1 = */ NULL,
1468	/* .pfnReserved2 = */ NULL,
1469	/* .pfnReserved3 = */ NULL,
1470	/* .pfnReserved4 = */ NULL,
1471	/* .pfnReserved5 = */ NULL,
1472	/* .pfnReserved6 = */ NULL,
1473	/* .pfnReserved7 = */ NULL,
1474	#elif defined(IN_RING0)
1475	/* .pfnEarlyConstruct = */ NULL,
1476	/* .pfnConstruct = */ pciRZRootConstruct,
1477	/* .pfnDestruct = */ NULL,
1478	/* .pfnFinalDestruct = */ NULL,
1479	/* .pfnRequest = */ NULL,
1480	/* .pfnReserved0 = */ NULL,
1481	/* .pfnReserved1 = */ NULL,
1482	/* .pfnReserved2 = */ NULL,
1483	/* .pfnReserved3 = */ NULL,
1484	/* .pfnReserved4 = */ NULL,
1485	/* .pfnReserved5 = */ NULL,
1486	/* .pfnReserved6 = */ NULL,
1487	/* .pfnReserved7 = */ NULL,
1488	#elif defined(IN_RC)
1489	/* .pfnConstruct = */ pciRZRootConstruct,
1490	/* .pfnReserved0 = */ NULL,
1491	/* .pfnReserved1 = */ NULL,
1492	/* .pfnReserved2 = */ NULL,
1493	/* .pfnReserved3 = */ NULL,
1494	/* .pfnReserved4 = */ NULL,
1495	/* .pfnReserved5 = */ NULL,
1496	/* .pfnReserved6 = */ NULL,
1497	/* .pfnReserved7 = */ NULL,
1498	#else
1499	# error "Not in IN_RING3, IN_RING0 or IN_RC!"
1500	#endif
1501	/* .u32VersionEnd = */ PDM_DEVREG_VERSION
1502
1503	};
1504
1505
1506
1507	/* -=-=-=-=-=- The PCI bridge specific bits -=-=-=-=-=- */
1508
1509	/**
1510	* @interface_method_impl{PDMPCIBUSREGR3,pfnSetIrqR3}
1511	*/
1512	static DECLCALLBACK(void) pcibridgeSetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc)
1513	{
1514	LogFlow(("pcibridgeSetIrq: %p %u %u %#x\n", pPciDev, iIrq, iLevel, uTagSrc));
1515
1516	/*
1517	* The PCI-to-PCI bridge specification defines how the interrupt pins
1518	* are routed from the secondary to the primary bus (see chapter 9).
1519	* iIrq gives the interrupt pin the pci device asserted.
1520	* We change iIrq here according to the spec and call the SetIrq function
1521	* of our parent passing the device which asserted the interrupt instead of the device of the bridge.
1522	*/
1523	PDEVPCIBUS pBus;
1524	uint8_t uDevFnBridge;
1525	int iIrqPinBridge;
1526	PPDMDEVINS pDevInsBus = devpcibridgeCommonSetIrqRootWalk(pDevIns, pPciDev, iIrq, &pBus, &uDevFnBridge, &iIrqPinBridge);
1527	AssertReturnVoid(pDevInsBus);
1528	AssertMsg(pBus->iBus == 0, ("This is not the host pci bus iBus=%d\n", pBus->iBus));
1529	Assert(pDevInsBus->pReg == &g_DevicePCI);
1530
1531	pciSetIrqInternal(pDevInsBus, DEVPCIBUS_2_DEVPCIROOT(pBus), PDMINS_2_DATA_CC(pDevInsBus, PDEVPCIBUSCC),
1532	uDevFnBridge, pPciDev, iIrqPinBridge, iLevel, uTagSrc);
1533	}
1534
1535	#ifdef IN_RING3
1536
1537	/**
1538	* @callback_method_impl{FNPCIBRIDGECONFIGWRITE}
1539	*/
1540	static DECLCALLBACK(VBOXSTRICTRC) pcibridgeR3ConfigWrite(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice,
1541	uint32_t u32Address, unsigned cb, uint32_t u32Value)
1542	{
1543	LogFlowFunc(("pDevIns=%p iBus=%d iDevice=%d u32Address=%u cb=%d u32Value=%u\n", pDevIns, iBus, iDevice, u32Address, cb, u32Value));
1544	PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
1545	VBOXSTRICTRC rcStrict = VINF_SUCCESS;
1546
1547	/* If the current bus is not the target bus search for the bus which contains the device. */
1548	if (iBus != pDevIns->apPciDevs[0]->abConfig[VBOX_PCI_SECONDARY_BUS])
1549	{
1550	PPDMPCIDEV pBridgeDevice = pciR3FindBridge(pBus, iBus);
1551	if (pBridgeDevice)
1552	{
1553	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigWrite);
1554	rcStrict = pBridgeDevice->Int.s.pfnBridgeConfigWrite(pBridgeDevice->Int.s.CTX_SUFF(pDevIns), iBus, iDevice,
1555	u32Address, cb, u32Value);
1556	}
1557	}
1558	else
1559	{
1560	/* This is the target bus, pass the write to the device. */
1561	PPDMPCIDEV pPciDev = pBus->apDevices[iDevice];
1562	if (pPciDev)
1563	{
1564	LogFunc(("%s: addr=%02x val=%08x len=%d\n", pPciDev->pszNameR3, u32Address, u32Value, cb));
1565	rcStrict = VINF_PDM_PCI_DO_DEFAULT;
1566	if (pPciDev->Int.s.pfnConfigWrite)
1567	rcStrict = pPciDev->Int.s.pfnConfigWrite(pPciDev->Int.s.CTX_SUFF(pDevIns), pPciDev, u32Address, cb, u32Value);
1568	if (rcStrict == VINF_PDM_PCI_DO_DEFAULT)
1569	rcStrict = devpciR3CommonConfigWriteWorker(pDevIns, PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC),
1570	pPciDev, u32Address, cb, u32Value);
1571	}
1572	}
1573	return rcStrict;
1574	}
1575
1576
1577	/**
1578	* @callback_method_impl{FNPCIBRIDGECONFIGREAD}
1579	*/
1580	static DECLCALLBACK(VBOXSTRICTRC) pcibridgeR3ConfigRead(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice,
1581	uint32_t u32Address, unsigned cb, uint32_t *pu32Value)
1582	{
1583	LogFlowFunc(("pDevIns=%p iBus=%d iDevice=%d u32Address=%u cb=%d\n", pDevIns, iBus, iDevice, u32Address, cb));
1584	PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
1585	VBOXSTRICTRC rcStrict = VINF_SUCCESS;
1586
1587	/* If the current bus is not the target bus search for the bus which contains the device. */
1588	if (iBus != pDevIns->apPciDevs[0]->abConfig[VBOX_PCI_SECONDARY_BUS])
1589	{
1590	PPDMPCIDEV pBridgeDevice = pciR3FindBridge(pBus, iBus);
1591	if (pBridgeDevice)
1592	{
1593	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigRead);
1594	rcStrict = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->Int.s.CTX_SUFF(pDevIns),
1595	iBus, iDevice, u32Address, cb, pu32Value);
1596	}
1597	else
1598	*pu32Value = UINT32_MAX;
1599	}
1600	else
1601	{
1602	/* This is the target bus, pass the read to the device. */
1603	PPDMPCIDEV pPciDev = pBus->apDevices[iDevice];
1604	if (pPciDev)
1605	{
1606	rcStrict = VINF_PDM_PCI_DO_DEFAULT;
1607	if (pPciDev->Int.s.pfnConfigRead)
1608	rcStrict = pPciDev->Int.s.pfnConfigRead(pPciDev->Int.s.CTX_SUFF(pDevIns), pPciDev, u32Address, cb, pu32Value);
1609	if (rcStrict == VINF_PDM_PCI_DO_DEFAULT)
1610	rcStrict = devpciR3CommonConfigReadWorker(pPciDev, u32Address, cb, pu32Value);
1611
1612	LogFunc(("%s: u32Address=%02x u32Value=%08x cb=%d\n", pPciDev->pszNameR3, u32Address, *pu32Value, cb));
1613	}
1614	else
1615	*pu32Value = UINT32_MAX;
1616	}
1617
1618	return rcStrict;
1619	}
1620
1621
1622	/**
1623	* @callback_method_impl{FNSSMDEVSAVEEXEC}
1624	*/
1625	static DECLCALLBACK(int) pcibridgeR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
1626	{
1627	return pciR3CommonSaveExec(pDevIns->pHlpR3, PDMINS_2_DATA(pDevIns, PDEVPCIBUS), pSSM);
1628	}
1629
1630
1631	/**
1632	* @callback_method_impl{FNSSMDEVLOADEXEC}
1633	*/
1634	static DECLCALLBACK(int) pcibridgeR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1635	{
1636	PDEVPCIBUS pThis = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
1637	if (uVersion > VBOX_PCI_SAVED_STATE_VERSION)
1638	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1639	return pciR3CommonLoadExec(pDevIns, pThis, pSSM, uVersion, uPass);
1640	}
1641
1642
1643	/**
1644	* @interface_method_impl{PDMDEVREG,pfnReset}
1645	*/
1646	static DECLCALLBACK(void) pcibridgeR3Reset(PPDMDEVINS pDevIns)
1647	{
1648	/* Reset config space to default values. */
1649	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1650	pPciDev->abConfig[VBOX_PCI_PRIMARY_BUS] = 0;
1651	pPciDev->abConfig[VBOX_PCI_SECONDARY_BUS] = 0;
1652	pPciDev->abConfig[VBOX_PCI_SUBORDINATE_BUS] = 0;
1653	}
1654
1655
1656	/**
1657	* @interface_method_impl{PDMDEVREG,pfnDestruct}
1658	*/
1659	static DECLCALLBACK(int) pcibridgeR3Destruct(PPDMDEVINS pDevIns)
1660	{
1661	PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
1662	if (pBus->papBridgesR3)
1663	{
1664	PDMDevHlpMMHeapFree(pDevIns, pBus->papBridgesR3);
1665	pBus->papBridgesR3 = NULL;
1666	}
1667	return VINF_SUCCESS;
1668	}
1669
1670
1671	/**
1672	* @interface_method_impl{PDMDEVREG,pfnConstruct}
1673	*/
1674	static DECLCALLBACK(int) pcibridgeR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
1675	{
1676	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
1677	RT_NOREF(iInstance, pCfg);
1678	PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
1679	PDEVPCIBUSCC pBusCC = PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC);
1680
1681	/*
1682	* Validate and read configuration (none left).
1683	*/
1684	PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "", "");
1685	Log(("PCI: fRCEnabled=%RTbool fR0Enabled=%RTbool\n", pDevIns->fRCEnabled, pDevIns->fR0Enabled));
1686
1687	/*
1688	* Init data and register the PCI bus.
1689	*/
1690	pBus->fTypePiix3 = true;
1691	pBus->fTypeIch9 = false;
1692	pBus->fPureBridge = true;
1693	pBus->papBridgesR3 = (PPDMPCIDEV )PDMDevHlpMMHeapAllocZ(pDevIns, sizeof(PPDMPCIDEV) RT_ELEMENTS(pBus->apDevices));
1694	AssertLogRelReturn(pBus->papBridgesR3, VERR_NO_MEMORY);
1695
1696	PDMPCIBUSREGCC PciBusReg;
1697	PciBusReg.u32Version = PDM_PCIBUSREGCC_VERSION;
1698	PciBusReg.pfnRegisterR3 = devpcibridgeR3CommonRegisterDevice;
1699	PciBusReg.pfnRegisterMsiR3 = NULL;
1700	PciBusReg.pfnIORegionRegisterR3 = devpciR3CommonIORegionRegister;
1701	PciBusReg.pfnInterceptConfigAccesses = devpciR3CommonInterceptConfigAccesses;
1702	PciBusReg.pfnConfigWrite = devpciR3CommonConfigWrite;
1703	PciBusReg.pfnConfigRead = devpciR3CommonConfigRead;
1704	PciBusReg.pfnSetIrqR3 = pcibridgeSetIrq;
1705	PciBusReg.u32EndVersion = PDM_PCIBUSREGCC_VERSION;
1706	int rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBusCC->pPciHlpR3, &pBus->iBus);
1707	if (RT_FAILURE(rc))
1708	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to register ourselves as a PCI Bus"));
1709	Assert(pBus->iBus == (uint32_t)iInstance + 1); /* Can be removed when adding support for multiple bridge implementations. */
1710	if (pBusCC->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
1711	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
1712	N_("PCI helper version mismatch; got %#x expected %#x"),
1713	pBusCC->pPciHlpR3->u32Version, PDM_PCIHLPR3_VERSION);
1714
1715	/*
1716	* Fill in PCI configs and add them to the bus.
1717	*/
1718	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1719	PCIDevSetVendorId( pPciDev, 0x8086); /* Intel */
1720	PCIDevSetDeviceId( pPciDev, 0x2448); /* 82801 Mobile PCI bridge. */
1721	PCIDevSetRevisionId(pPciDev, 0xf2);
1722	PCIDevSetClassSub( pPciDev, 0x04); /* pci2pci */
1723	PCIDevSetClassBase( pPciDev, 0x06); /* PCI_bridge */
1724	PCIDevSetClassProg( pPciDev, 0x01); /* Supports subtractive decoding. */
1725	PCIDevSetHeaderType(pPciDev, 0x01); /* Single function device which adheres to the PCI-to-PCI bridge spec. */
1726	PCIDevSetCommand( pPciDev, 0x0000);
1727	PCIDevSetStatus( pPciDev, 0x0020); /* 66MHz Capable. */
1728	PCIDevSetInterruptLine(pPciDev, 0x00); /* This device does not assert interrupts. */
1729
1730	/*
1731	* This device does not generate interrupts. Interrupt delivery from
1732	* devices attached to the bus is unaffected.
1733	*/
1734	PCIDevSetInterruptPin(pPciDev, 0x00);
1735
1736	/*
1737	* Register this PCI bridge. The called function will take care on which bus we will get registered.
1738	*/
1739	rc = PDMDevHlpPCIRegisterEx(pDevIns, pPciDev, PDMPCIDEVREG_F_PCI_BRIDGE, PDMPCIDEVREG_DEV_NO_FIRST_UNUSED,
1740	PDMPCIDEVREG_FUN_NO_FIRST_UNUSED, "pcibridge");
1741	if (RT_FAILURE(rc))
1742	return rc;
1743	pPciDev->Int.s.pfnBridgeConfigRead = pcibridgeR3ConfigRead;
1744	pPciDev->Int.s.pfnBridgeConfigWrite = pcibridgeR3ConfigWrite;
1745
1746	pBus->iDevSearch = 0;
1747
1748	/*
1749	* Register SSM handlers. We use the same saved state version as for the host bridge
1750	* to make changes easier.
1751	*/
1752	rc = PDMDevHlpSSMRegisterEx(pDevIns, VBOX_PCI_SAVED_STATE_VERSION, sizeof(pBus) + 16128, "pgm",
1753	NULL, NULL, NULL,
1754	NULL, pcibridgeR3SaveExec, NULL,
1755	NULL, pcibridgeR3LoadExec, NULL);
1756	if (RT_FAILURE(rc))
1757	return rc;
1758
1759	return VINF_SUCCESS;
1760	}
1761
1762	#else /* !IN_RING3 */
1763
1764	/**
1765	* @interface_method_impl{PDMDEVREGR0,pfnConstruct}
1766	*/
1767	static DECLCALLBACK(int) pcibridgeRZConstruct(PPDMDEVINS pDevIns)
1768	{
1769	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
1770	PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
1771	PDEVPCIBUSCC pBusCC = PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC);
1772
1773	PDMPCIBUSREGCC PciBusReg;
1774	PciBusReg.u32Version = PDM_PCIBUSREGCC_VERSION;
1775	PciBusReg.iBus = pBus->iBus;
1776	PciBusReg.pfnSetIrq = pcibridgeSetIrq;
1777	PciBusReg.u32EndVersion = PDM_PCIBUSREGCC_VERSION;
1778	int rc = PDMDevHlpPCIBusSetUpContext(pDevIns, &PciBusReg, &pBusCC->CTX_SUFF(pPciHlp));
1779	AssertRC(rc);
1780
1781	return rc;
1782	}
1783
1784	#endif /* !IN_RING3 */
1785
1786	/**
1787	* The device registration structure
1788	* for the PCI-to-PCI bridge.
1789	*/
1790	const PDMDEVREG g_DevicePCIBridge =
1791	{
1792	/* .u32Version = */ PDM_DEVREG_VERSION,
1793	/* .uReserved0 = */ 0,
1794	/* .szName = */ "pcibridge",
1795	/* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RZ \| PDM_DEVREG_FLAGS_NEW_STYLE,
1796	/* .fClass = */ PDM_DEVREG_CLASS_BUS_PCI,
1797	/* .cMaxInstances = */ ~0U,
1798	/* .uSharedVersion = */ 42,
1799	/* .cbInstanceShared = */ sizeof(DEVPCIBUS),
1800	/* .cbInstanceCC = */ sizeof(CTX_SUFF(DEVPCIBUS)),
1801	/* .cbInstanceRC = */ 0,
1802	/* .cMaxPciDevices = */ 1,
1803	/* .cMaxMsixVectors = */ 0,
1804	/* .pszDescription = */ "82801 Mobile PCI to PCI bridge",
1805	#if defined(IN_RING3)
1806	/* .pszRCMod = */ "VBoxDDRC.rc",
1807	/* .pszR0Mod = */ "VBoxDDR0.r0",
1808	/* .pfnConstruct = */ pcibridgeR3Construct,
1809	/* .pfnDestruct = */ pcibridgeR3Destruct,
1810	/* .pfnRelocate = */ NULL,
1811	/* .pfnMemSetup = */ NULL,
1812	/* .pfnPowerOn = */ NULL,
1813	/* .pfnReset = */ pcibridgeR3Reset,
1814	/* .pfnSuspend = */ NULL,
1815	/* .pfnResume = */ NULL,
1816	/* .pfnAttach = */ NULL,
1817	/* .pfnDetach = */ NULL,
1818	/* .pfnQueryInterface = */ NULL,
1819	/* .pfnInitComplete = */ NULL,
1820	/* .pfnPowerOff = */ NULL,
1821	/* .pfnSoftReset = */ NULL,
1822	/* .pfnReserved0 = */ NULL,
1823	/* .pfnReserved1 = */ NULL,
1824	/* .pfnReserved2 = */ NULL,
1825	/* .pfnReserved3 = */ NULL,
1826	/* .pfnReserved4 = */ NULL,
1827	/* .pfnReserved5 = */ NULL,
1828	/* .pfnReserved6 = */ NULL,
1829	/* .pfnReserved7 = */ NULL,
1830	#elif defined(IN_RING0)
1831	/* .pfnEarlyConstruct = */ NULL,
1832	/* .pfnConstruct = */ pcibridgeRZConstruct,
1833	/* .pfnDestruct = */ NULL,
1834	/* .pfnFinalDestruct = */ NULL,
1835	/* .pfnRequest = */ NULL,
1836	/* .pfnReserved0 = */ NULL,
1837	/* .pfnReserved1 = */ NULL,
1838	/* .pfnReserved2 = */ NULL,
1839	/* .pfnReserved3 = */ NULL,
1840	/* .pfnReserved4 = */ NULL,
1841	/* .pfnReserved5 = */ NULL,
1842	/* .pfnReserved6 = */ NULL,
1843	/* .pfnReserved7 = */ NULL,
1844	#elif defined(IN_RC)
1845	/* .pfnConstruct = */ pcibridgeRZConstruct,
1846	/* .pfnReserved0 = */ NULL,
1847	/* .pfnReserved1 = */ NULL,
1848	/* .pfnReserved2 = */ NULL,
1849	/* .pfnReserved3 = */ NULL,
1850	/* .pfnReserved4 = */ NULL,
1851	/* .pfnReserved5 = */ NULL,
1852	/* .pfnReserved6 = */ NULL,
1853	/* .pfnReserved7 = */ NULL,
1854	#else
1855	# error "Not in IN_RING3, IN_RING0 or IN_RC!"
1856	#endif
1857	/* .u32VersionEnd = */ PDM_DEVREG_VERSION
1858	};
1859

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source: vbox/trunk/src/VBox/Devices/Bus/DevPCI.cpp@ 91605

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