VirtualBox

source: vbox/trunk/src/VBox/Devices/Bus/DevPciGenericEcam.cpp@ 99775

Last change on this file since 99775 was 99752, checked in by vboxsync, 2 years ago

Devices/Bus: Started a basic PCI bus implementation suitable for ARMv8, devices are detected by a Linux guest but interrupts don't work right now. The implementation shares most code with ICH9 PCI device, bugref:10445 [scm]
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1/* $Id: DevPciGenericEcam.cpp 99752 2023-05-11 13:43:32Z vboxsync $ */
2/** @file
3 * DevPciGeneric - Generic host to PCIe bridge emulation.
4 */
5
6/*
7 * Copyright (C) 2023 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28
29/*********************************************************************************************************************************
30* Header Files *
31*********************************************************************************************************************************/
32#define LOG_GROUP LOG_GROUP_DEV_PCI
33#define PDMPCIDEV_INCLUDE_PRIVATE /* Hack to get pdmpcidevint.h included at the right point. */
34#include <VBox/vmm/pdmpcidev.h>
35
36#include <VBox/AssertGuest.h>
37#include <VBox/msi.h>
38#include <VBox/vmm/pdmdev.h>
39#include <VBox/vmm/mm.h>
40#include <iprt/asm.h>
41#include <iprt/assert.h>
42#include <iprt/string.h>
43#ifdef IN_RING3
44# include <iprt/mem.h>
45# include <iprt/uuid.h>
46#endif
47
48#include "PciInline.h"
49#include "VBoxDD.h"
50#include "MsiCommon.h"
51#include "DevPciInternal.h"
52
53
54/*********************************************************************************************************************************
55* Structures and Typedefs *
56*********************************************************************************************************************************/
57
58
59/*********************************************************************************************************************************
60* Defined Constants And Macros *
61*********************************************************************************************************************************/
62/** Saved state version of the generic ECAM PCI bus device. */
63#define VBOX_PCIGENECAM_SAVED_STATE_VERSION 1
64
65
66/*********************************************************************************************************************************
67* Internal Functions *
68*********************************************************************************************************************************/
69
70static DECLCALLBACK(void) pciGenEcamSetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc)
71{
72 PDEVPCIROOT pPciRoot = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
73 PDEVPCIBUSCC pBusCC = PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC);
74 uint8_t uDevFn = pPciDev->uDevFn;
75
76 LogFlowFunc(("invoked by %p/%d: iIrq=%d iLevel=%d uTagSrc=%#x\n", pDevIns, pDevIns->iInstance, iIrq, iLevel, uTagSrc));
77
78 /* If MSI or MSI-X is enabled, PCI INTx# signals are disabled regardless of the PCI command
79 * register interrupt bit state.
80 * PCI 3.0 (section 6.8) forbids MSI and MSI-X to be enabled at the same time and makes
81 * that undefined behavior. We check for MSI first, then MSI-X.
82 */
83 if (MsiIsEnabled(pPciDev))
84 {
85 Assert(!MsixIsEnabled(pPciDev)); /* Not allowed -- see note above. */
86 LogFlowFunc(("PCI Dev %p : MSI\n", pPciDev));
87 MsiNotify(pDevIns, pBusCC->CTX_SUFF(pPciHlp), pPciDev, iIrq, iLevel, uTagSrc);
88 return;
89 }
90
91 if (MsixIsEnabled(pPciDev))
92 {
93 LogFlowFunc(("PCI Dev %p : MSI-X\n", pPciDev));
94 MsixNotify(pDevIns, pBusCC->CTX_SUFF(pPciHlp), pPciDev, iIrq, iLevel, uTagSrc);
95 return;
96 }
97
98 PDEVPCIBUS pBus = &pPciRoot->PciBus;
99 LogFlowFunc(("PCI Dev %p : IRQ\n", pPciDev));
100
101 /* Check if the state changed. */
102 if (pPciDev->Int.s.uIrqPinState != iLevel)
103 {
104 pPciDev->Int.s.uIrqPinState = (iLevel & PDM_IRQ_LEVEL_HIGH);
105
106 /** @todo */
107 }
108}
109
110
111/**
112 * @callback_method_impl{FNIOMMMIONEWWRITE,
113 * Emulates writes to configuration space.}
114 */
115static DECLCALLBACK(VBOXSTRICTRC) pciHostR3MmioPioWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void const *pv, unsigned cb)
116{
117 Log2Func(("%RGp LB %d\n", off, cb));
118 RT_NOREF(pvUser);
119
120 AssertReturn(off < _64K, VERR_INVALID_PARAMETER);
121 AssertReturn(cb <= 4, VERR_INVALID_PARAMETER);
122
123 /* Get the value. */
124 uint32_t u32;
125 switch (cb)
126 {
127 case 1:
128 u32 = *(uint8_t const *)pv;
129 break;
130 case 2:
131 u32 = *(uint16_t const *)pv;
132 break;
133 case 4:
134 u32 = *(uint32_t const *)pv;
135 break;
136 default:
137 ASSERT_GUEST_MSG_FAILED(("cb=%u off=%RGp\n", cb, off)); /** @todo how the heck should this work? Split it, right? */
138 u32 = 0;
139 break;
140 }
141
142 return PDMDevHlpIoPortWrite(pDevIns, (RTIOPORT)off, u32, cb);
143}
144
145
146/**
147 * @callback_method_impl{FNIOMMMIONEWWRITE,
148 * Emulates reads from configuration space.}
149 */
150static DECLCALLBACK(VBOXSTRICTRC) pciHostR3MmioPioRead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void *pv, unsigned cb)
151{
152 LogFlowFunc(("%RGp LB %u\n", off, cb));
153 RT_NOREF(pvUser);
154
155 AssertReturn(off < _64K, VERR_INVALID_PARAMETER);
156 AssertReturn(cb <= 4, VERR_INVALID_PARAMETER);
157
158 /* Perform configuration space read */
159 uint32_t u32Value = 0;
160 VBOXSTRICTRC rcStrict = PDMDevHlpIoPortRead(pDevIns, (RTIOPORT)off, &u32Value, cb);
161
162 if (RT_SUCCESS(rcStrict))
163 {
164 switch (cb)
165 {
166 case 1:
167 *(uint8_t *)pv = (uint8_t)u32Value;
168 break;
169 case 2:
170 *(uint16_t *)pv = (uint16_t)u32Value;
171 break;
172 case 4:
173 *(uint32_t *)pv = u32Value;
174 break;
175 default:
176 ASSERT_GUEST_MSG_FAILED(("cb=%u off=%RGp\n", cb, off)); /** @todo how the heck should this work? Split it, right? */
177 break;
178 }
179 }
180
181 return rcStrict;
182}
183
184
185#ifdef IN_RING3
186
187/* -=-=-=-=-=- PCI Config Space -=-=-=-=-=- */
188
189
190/**
191 * @interface_method_impl{PDMDEVREG,pfnConstruct}
192 */
193static DECLCALLBACK(int) pciGenEcamR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
194{
195 RT_NOREF1(iInstance);
196 Assert(iInstance == 0);
197 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
198
199 PDEVPCIBUSCC pBusCC = PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC);
200 PDEVPCIROOT pPciRoot = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
201 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
202 PDEVPCIBUS pBus = &pPciRoot->PciBus;
203
204 /*
205 * Validate and read configuration.
206 */
207 PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "MmioEcamBase|MmioEcamLength|MmioPioBase|MmioPioSize", "");
208
209 int rc = pHlp->pfnCFGMQueryU64Def(pCfg, "MmioEcamBase", &pPciRoot->u64PciConfigMMioAddress, 0);
210 AssertRCReturn(rc, PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"McfgBase\"")));
211
212 rc = pHlp->pfnCFGMQueryU64Def(pCfg, "MmioEcamLength", &pPciRoot->u64PciConfigMMioLength, 0);
213 AssertRCReturn(rc, PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"McfgLength\"")));
214
215 rc = pHlp->pfnCFGMQueryU64Def(pCfg, "MmioPioBase", &pPciRoot->GCPhysMmioPioEmuBase, 0);
216 AssertRCReturn(rc, PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"MmioPioBase\"")));
217
218 rc = pHlp->pfnCFGMQueryU64Def(pCfg, "MmioPioSize", &pPciRoot->GCPhysMmioPioEmuSize, 0);
219 AssertRCReturn(rc, PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"MmioPioSize\"")));
220
221 Log(("PCI: fUseIoApic=%RTbool McfgBase=%#RX64 McfgLength=%#RX64 fR0Enabled=%RTbool fRCEnabled=%RTbool\n", pPciRoot->fUseIoApic,
222 pPciRoot->u64PciConfigMMioAddress, pPciRoot->u64PciConfigMMioLength, pDevIns->fR0Enabled, pDevIns->fRCEnabled));
223
224 /*
225 * Init data.
226 */
227 /* And fill values */
228 pBusCC->pDevInsR3 = pDevIns;
229 pPciRoot->hIoPortAddress = NIL_IOMIOPORTHANDLE;
230 pPciRoot->hIoPortData = NIL_IOMIOPORTHANDLE;
231 pPciRoot->hIoPortMagic = NIL_IOMIOPORTHANDLE;
232 pPciRoot->hMmioMcfg = NIL_IOMMMIOHANDLE;
233 pPciRoot->hMmioPioEmu = NIL_IOMMMIOHANDLE;
234 pPciRoot->PciBus.enmType = DEVPCIBUSTYPE_GENERIC_ECAM;
235 pPciRoot->PciBus.fPureBridge = false;
236 pPciRoot->PciBus.papBridgesR3 = (PPDMPCIDEV *)PDMDevHlpMMHeapAllocZ(pDevIns, sizeof(PPDMPCIDEV) * RT_ELEMENTS(pPciRoot->PciBus.apDevices));
237 AssertLogRelReturn(pPciRoot->PciBus.papBridgesR3, VERR_NO_MEMORY);
238
239 /*
240 * Disable default device locking.
241 */
242 rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
243 AssertRCReturn(rc, rc);
244
245 /*
246 * Register bus
247 */
248 PDMPCIBUSREGCC PciBusReg;
249 PciBusReg.u32Version = PDM_PCIBUSREGCC_VERSION;
250 PciBusReg.pfnRegisterR3 = devpciR3CommonRegisterDevice;
251 PciBusReg.pfnRegisterMsiR3 = NULL;
252 PciBusReg.pfnIORegionRegisterR3 = devpciR3CommonIORegionRegister;
253 PciBusReg.pfnInterceptConfigAccesses = devpciR3CommonInterceptConfigAccesses;
254 PciBusReg.pfnConfigRead = devpciR3CommonConfigRead;
255 PciBusReg.pfnConfigWrite = devpciR3CommonConfigWrite;
256 PciBusReg.pfnSetIrqR3 = pciGenEcamSetIrq;
257 PciBusReg.u32EndVersion = PDM_PCIBUSREGCC_VERSION;
258 rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBusCC->pPciHlpR3, &pBus->iBus);
259 if (RT_FAILURE(rc))
260 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to register ourselves as a PCI Bus"));
261 Assert(pBus->iBus == 0);
262 if (pBusCC->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
263 return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
264 N_("PCI helper version mismatch; got %#x expected %#x"),
265 pBusCC->pPciHlpR3->u32Version, PDM_PCIHLPR3_VERSION);
266
267 /*
268 * Fill in PCI configs and add them to the bus.
269 */
270#if 0
271 /* Host bridge device */
272 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
273 AssertPtr(pPciDev);
274 PDMPciDevSetVendorId( pPciDev, 0x8086); /** @todo Intel */
275 PDMPciDevSetDeviceId( pPciDev, 0x29e0); /** @todo Desktop */
276 PDMPciDevSetRevisionId(pPciDev, 0x01); /* rev. 01 */
277 PDMPciDevSetClassBase( pPciDev, 0x06); /* bridge */
278 PDMPciDevSetClassSub( pPciDev, 0x00); /* Host/PCI bridge */
279 PDMPciDevSetClassProg( pPciDev, 0x00); /* Host/PCI bridge */
280 PDMPciDevSetHeaderType(pPciDev, 0x00); /* bridge */
281 PDMPciDevSetWord(pPciDev, VBOX_PCI_SEC_STATUS, 0x0280); /* secondary status */
282
283 rc = PDMDevHlpPCIRegisterEx(pDevIns, pPciDev, 0 /*fFlags*/, 0 /*uPciDevNo*/, 0 /*uPciFunNo*/, "Host");
284 AssertLogRelRCReturn(rc, rc);
285#endif
286
287 /*
288 * MMIO handlers.
289 */
290 if (pPciRoot->u64PciConfigMMioAddress != 0)
291 {
292 rc = PDMDevHlpMmioCreateAndMap(pDevIns, pPciRoot->u64PciConfigMMioAddress, pPciRoot->u64PciConfigMMioLength,
293 devpciCommonMcfgMmioWrite, devpciCommonMcfgMmioRead,
294 IOMMMIO_FLAGS_READ_PASSTHRU | IOMMMIO_FLAGS_WRITE_PASSTHRU,
295 "ECAM window", &pPciRoot->hMmioMcfg);
296 AssertMsgRCReturn(rc, ("rc=%Rrc %#RX64/%#RX64\n", rc, pPciRoot->u64PciConfigMMioAddress, pPciRoot->u64PciConfigMMioLength), rc);
297 }
298
299 if (pPciRoot->GCPhysMmioPioEmuBase != 0)
300 {
301 rc = PDMDevHlpMmioCreateAndMap(pDevIns, pPciRoot->GCPhysMmioPioEmuBase, pPciRoot->GCPhysMmioPioEmuSize,
302 pciHostR3MmioPioWrite, pciHostR3MmioPioRead,
303 IOMMMIO_FLAGS_READ_PASSTHRU | IOMMMIO_FLAGS_WRITE_PASSTHRU,
304 "PIO range", &pPciRoot->hMmioPioEmu);
305 AssertMsgRCReturn(rc, ("rc=%Rrc %#RGp/%#RGp\n", rc, pPciRoot->GCPhysMmioPioEmuBase, pPciRoot->GCPhysMmioPioEmuSize), rc);
306 }
307
308 /*
309 * Saved state and info handlers.
310 */
311 rc = PDMDevHlpSSMRegisterEx(pDevIns, VBOX_PCIGENECAM_SAVED_STATE_VERSION,
312 sizeof(*pBus) + 16*128, "pgm",
313 NULL, NULL, NULL,
314 NULL, devpciR3CommonSaveExec, NULL,
315 NULL, devpciR3CommonLoadExec, NULL);
316 AssertRCReturn(rc, rc);
317
318 PDMDevHlpDBGFInfoRegister(pDevIns, "pci",
319 "Display PCI bus status. Recognizes 'basic' or 'verbose' as arguments, defaults to 'basic'.",
320 devpciR3InfoPci);
321 PDMDevHlpDBGFInfoRegister(pDevIns, "pciirq", "Display PCI IRQ state. (no arguments)", devpciR3InfoPciIrq);
322
323 return VINF_SUCCESS;
324}
325
326
327/**
328 * @interface_method_impl{PDMDEVREG,pfnDestruct}
329 */
330static DECLCALLBACK(int) pciGenEcamR3Destruct(PPDMDEVINS pDevIns)
331{
332 PDEVPCIROOT pPciRoot = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
333 if (pPciRoot->PciBus.papBridgesR3)
334 {
335 PDMDevHlpMMHeapFree(pDevIns, pPciRoot->PciBus.papBridgesR3);
336 pPciRoot->PciBus.papBridgesR3 = NULL;
337 }
338 return VINF_SUCCESS;
339}
340
341
342/**
343 * @interface_method_impl{PDMDEVREG,pfnReset}
344 */
345static DECLCALLBACK(void) pciGenEcamR3Reset(PPDMDEVINS pDevIns)
346{
347 /* Reset everything under the root bridge. */
348 devpciR3CommonResetBridge(pDevIns);
349}
350
351#else /* !IN_RING3 */
352
353/**
354 * @interface_method_impl{PDMDEVREGR0,pfnConstruct}
355 */
356DECLCALLBACK(int) pciGenEcamRZConstruct(PPDMDEVINS pDevIns)
357{
358 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
359 PDEVPCIROOT pPciRoot = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
360 PDEVPCIBUSCC pBusCC = PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC);
361
362 /* Mirror the ring-3 device lock disabling: */
363 int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
364 AssertRCReturn(rc, rc);
365
366 /* Set up the RZ PCI bus callbacks: */
367 PDMPCIBUSREGCC PciBusReg;
368 PciBusReg.u32Version = PDM_PCIBUSREGCC_VERSION;
369 PciBusReg.iBus = pPciRoot->PciBus.iBus;
370 PciBusReg.pfnSetIrq = pciGenEcamSetIrq;
371 PciBusReg.u32EndVersion = PDM_PCIBUSREGCC_VERSION;
372 rc = PDMDevHlpPCIBusSetUpContext(pDevIns, &PciBusReg, &pBusCC->CTX_SUFF(pPciHlp));
373 AssertRCReturn(rc, rc);
374
375 /* Set up MMIO callbacks: */
376 if (pPciRoot->hMmioMcfg != NIL_IOMMMIOHANDLE)
377 {
378 rc = PDMDevHlpMmioSetUpContext(pDevIns, pPciRoot->hMmioMcfg, devpciCommonMcfgMmioWrite, devpciCommonMcfgMmioRead, NULL /*pvUser*/);
379 AssertLogRelRCReturn(rc, rc);
380 }
381
382 return rc;
383}
384
385#endif /* !IN_RING3 */
386
387/**
388 * The PCI bus device registration structure.
389 */
390const PDMDEVREG g_DevicePciGenericEcam =
391{
392 /* .u32Version = */ PDM_DEVREG_VERSION,
393 /* .uReserved0 = */ 0,
394 /* .szName = */ "pci-generic-ecam",
395 /* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RZ | PDM_DEVREG_FLAGS_NEW_STYLE,
396 /* .fClass = */ PDM_DEVREG_CLASS_BUS_PCI,
397 /* .cMaxInstances = */ 1,
398 /* .uSharedVersion = */ 42,
399 /* .cbInstanceShared = */ sizeof(DEVPCIROOT),
400 /* .cbInstanceCC = */ sizeof(CTX_SUFF(DEVPCIBUS)),
401 /* .cbInstanceRC = */ sizeof(DEVPCIBUSRC),
402 /* .cMaxPciDevices = */ 1,
403 /* .cMaxMsixVectors = */ 0,
404 /* .pszDescription = */ "Generic PCI host bridge (working with pci-host-ecam-generic driver)",
405#if defined(IN_RING3)
406 /* .pszRCMod = */ "VBoxDDRC.rc",
407 /* .pszR0Mod = */ "VBoxDDR0.r0",
408 /* .pfnConstruct = */ pciGenEcamR3Construct,
409 /* .pfnDestruct = */ pciGenEcamR3Destruct,
410 /* .pfnRelocate = */ NULL,
411 /* .pfnMemSetup = */ NULL,
412 /* .pfnPowerOn = */ NULL,
413 /* .pfnReset = */ pciGenEcamR3Reset,
414 /* .pfnSuspend = */ NULL,
415 /* .pfnResume = */ NULL,
416 /* .pfnAttach = */ NULL,
417 /* .pfnDetach = */ NULL,
418 /* .pfnQueryInterface = */ NULL,
419 /* .pfnInitComplete = */ NULL,
420 /* .pfnPowerOff = */ NULL,
421 /* .pfnSoftReset = */ NULL,
422 /* .pfnReserved0 = */ NULL,
423 /* .pfnReserved1 = */ NULL,
424 /* .pfnReserved2 = */ NULL,
425 /* .pfnReserved3 = */ NULL,
426 /* .pfnReserved4 = */ NULL,
427 /* .pfnReserved5 = */ NULL,
428 /* .pfnReserved6 = */ NULL,
429 /* .pfnReserved7 = */ NULL,
430#elif defined(IN_RING0)
431 /* .pfnEarlyConstruct = */ NULL,
432 /* .pfnConstruct = */ pciGenEcamRZConstruct,
433 /* .pfnDestruct = */ NULL,
434 /* .pfnFinalDestruct = */ NULL,
435 /* .pfnRequest = */ NULL,
436 /* .pfnReserved0 = */ NULL,
437 /* .pfnReserved1 = */ NULL,
438 /* .pfnReserved2 = */ NULL,
439 /* .pfnReserved3 = */ NULL,
440 /* .pfnReserved4 = */ NULL,
441 /* .pfnReserved5 = */ NULL,
442 /* .pfnReserved6 = */ NULL,
443 /* .pfnReserved7 = */ NULL,
444#elif defined(IN_RC)
445 /* .pfnConstruct = */ pciGenEcamRZConstruct,
446 /* .pfnReserved0 = */ NULL,
447 /* .pfnReserved1 = */ NULL,
448 /* .pfnReserved2 = */ NULL,
449 /* .pfnReserved3 = */ NULL,
450 /* .pfnReserved4 = */ NULL,
451 /* .pfnReserved5 = */ NULL,
452 /* .pfnReserved6 = */ NULL,
453 /* .pfnReserved7 = */ NULL,
454#else
455# error "Not in IN_RING3, IN_RING0 or IN_RC!"
456#endif
457 /* .u32VersionEnd = */ PDM_DEVREG_VERSION
458};
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