VirtualBox

source: vbox/trunk/src/VBox/Devices/Bus/DevPciIch9.cpp@ 32037

Last change on this file since 32037 was 32037, checked in by vboxsync, 15 years ago

PCI work: make ICH9 PCI an additional device, not alternative implementation
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 8.9 KB
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1/* $Id: DevPciIch9.cpp 32037 2010-08-27 10:23:14Z vboxsync $ */
2/** @file
3 * DevPCI - ICH9 southbridge PCI bus emulation Device.
4 */
5
6/*
7 * Copyright (C) 2010 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/*******************************************************************************
19 * Header Files *
20 *******************************************************************************/
21#define LOG_GROUP LOG_GROUP_DEV_PCI
22/* Hack to get PCIDEVICEINT declare at the right point - include "PCIInternal.h". */
23#define PCI_INCLUDE_PRIVATE
24#include <VBox/pci.h>
25#include <VBox/pdmdev.h>
26#include <iprt/asm.h>
27#include <iprt/assert.h>
28#include <iprt/string.h>
29
30#include "../Builtins.h"
31
32/**
33 * PCI Bus instance.
34 */
35typedef struct
36{
37 /** Bus number. */
38 int32_t iBus;
39 /** Number of bridges attached to the bus. */
40 uint32_t cBridges;
41
42 /** Array of PCI devices. */
43 R3PTRTYPE(PPCIDEVICE) devices[256];
44 /** Array of bridges attached to the bus. */
45 R3PTRTYPE(PPCIDEVICE *) papBridgesR3;
46
47 /** R3 pointer to the device instance. */
48 PPDMDEVINSR3 pDevInsR3;
49 /** Pointer to the PCI R3 helpers. */
50 PCPDMPCIHLPR3 pPciHlpR3;
51
52 /** R0 pointer to the device instance. */
53 PPDMDEVINSR0 pDevInsR0;
54 /** Pointer to the PCI R0 helpers. */
55 PCPDMPCIHLPR0 pPciHlpR0;
56
57 /** RC pointer to the device instance. */
58 PPDMDEVINSRC pDevInsRC;
59 /** Pointer to the PCI RC helpers. */
60 PCPDMPCIHLPRC pPciHlpRC;
61
62 /** The PCI device for the PCI bridge. */
63 PCIDEVICE PciDev;
64
65} PCIBUS, *PPCIBUS;
66
67
68/** @def PCI_IRQ_PINS
69 * Number of pins for interrupts (PIRQ#0...PIRQ#3)
70 */
71#define PCI_IRQ_PINS 4
72
73/** @def PCI_APIC_IRQ_PINS
74 * Number of pins for interrupts if the APIC is used.
75 */
76#define PCI_APIC_IRQ_PINS 8
77
78/**
79 * PCI Globals - This is the host-to-pci bridge and the root bus.
80 */
81typedef struct PCIGLOBALS
82{
83 /** I/O APIC usage flag */
84 bool fUseIoApic;
85
86 /** R3 pointer to the device instance. */
87 PPDMDEVINSR3 pDevInsR3;
88 /** R0 pointer to the device instance. */
89 PPDMDEVINSR0 pDevInsR0;
90 /** RC pointer to the device instance. */
91 PPDMDEVINSRC pDevInsRC;
92
93#if HC_ARCH_BITS == 64
94 uint32_t Alignment0;
95#endif
96
97 /** PCI bus which is attached to the host-to-PCI bridge. */
98 PCIBUS PciBus;
99
100} PCIGLOBALS;
101/** Pointer to per VM data. */
102typedef PCIGLOBALS *PPCIGLOBALS;
103
104/*******************************************************************************
105 * Defined Constants And Macros *
106 *******************************************************************************/
107
108/** Converts a bus instance pointer to a device instance pointer. */
109#define PCIBUS_2_DEVINS(pPciBus) ((pPciBus)->CTX_SUFF(pDevIns))
110/** Converts a device instance pointer to a PCIGLOBALS pointer. */
111#define DEVINS_2_PCIGLOBALS(pDevIns) ((PPCIGLOBALS)(PDMINS_2_DATA(pDevIns, PPCIGLOBALS)))
112/** Converts a device instance pointer to a PCIBUS pointer. */
113#define DEVINS_2_PCIBUS(pDevIns) ((PPCIBUS)(&PDMINS_2_DATA(pDevIns, PPCIGLOBALS)->PciBus))
114
115#ifndef VBOX_DEVICE_STRUCT_TESTCASE
116
117#ifdef IN_RING3
118
119static DECLCALLBACK(int) ich9pciConstruct(PPDMDEVINS pDevIns,
120 int iInstance,
121 PCFGMNODE pCfg)
122{
123 int rc;
124 Assert(iInstance == 0);
125
126 /*
127 * Validate and read configuration.
128 */
129 if (!CFGMR3AreValuesValid(pCfg, "IOAPIC\0" "GCEnabled\0" "R0Enabled\0"))
130 return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
131
132 /* query whether we got an IOAPIC */
133 bool fUseIoApic;
134 rc = CFGMR3QueryBoolDef(pCfg, "IOAPIC", &fUseIoApic, false);
135 if (RT_FAILURE(rc))
136 return PDMDEV_SET_ERROR(pDevIns, rc,
137 N_("Configuration error: Failed to query boolean value \"IOAPIC\""));
138
139 /* check if RC code is enabled. */
140 bool fGCEnabled;
141 rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
142 if (RT_FAILURE(rc))
143 return PDMDEV_SET_ERROR(pDevIns, rc,
144 N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
145
146 /* check if R0 code is enabled. */
147 bool fR0Enabled;
148 rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
149 if (RT_FAILURE(rc))
150 return PDMDEV_SET_ERROR(pDevIns, rc,
151 N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
152 Log(("PCI: fUseIoApic=%RTbool fGCEnabled=%RTbool fR0Enabled=%RTbool\n", fUseIoApic, fGCEnabled, fR0Enabled));
153
154 /*
155 * Init data and register the PCI bus.
156 */
157 PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
158 pGlobals->fUseIoApic = fUseIoApic;
159
160 return VINF_SUCCESS;
161}
162
163/**
164 * @copydoc FNPDMDEVRELOCATE
165 */
166static DECLCALLBACK(void) ich9pciRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
167{
168}
169
170/**
171 * @interface_method_impl{PDMDEVREG,pfnConstruct}
172 */
173static DECLCALLBACK(int) ich9pcibridgeConstruct(PPDMDEVINS pDevIns,
174 int iInstance,
175 PCFGMNODE pCfg)
176{
177 int rc;
178
179 /*
180 * Validate and read configuration.
181 */
182 if (!CFGMR3AreValuesValid(pCfg, "GCEnabled\0" "R0Enabled\0"))
183 return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
184
185 /* check if RC code is enabled. */
186 bool fGCEnabled;
187 rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
188 if (RT_FAILURE(rc))
189 return PDMDEV_SET_ERROR(pDevIns, rc,
190 N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
191
192 /* check if R0 code is enabled. */
193 bool fR0Enabled;
194 rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
195 if (RT_FAILURE(rc))
196 return PDMDEV_SET_ERROR(pDevIns, rc,
197 N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
198 Log(("PCI: fGCEnabled=%RTbool fR0Enabled=%RTbool\n", fGCEnabled, fR0Enabled));
199
200 return VINF_SUCCESS;
201}
202
203/**
204 * @copydoc FNPDMDEVRESET
205 */
206static DECLCALLBACK(void) ich9pcibridgeReset(PPDMDEVINS pDevIns)
207{
208}
209
210
211/**
212 * @copydoc FNPDMDEVRELOCATE
213 */
214static DECLCALLBACK(void) ich9pcibridgeRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
215{
216}
217
218/**
219 * The PCI bus device registration structure.
220 */
221const PDMDEVREG g_DevicePciIch9 =
222{
223 /* u32Version */
224 PDM_DEVREG_VERSION,
225 /* szName */
226 "ich9pci",
227 /* szRCMod */
228 "VBoxDDGC.gc",
229 /* szR0Mod */
230 "VBoxDDR0.r0",
231 /* pszDescription */
232 "ICH9 PCI bridge",
233 /* fFlags */
234 PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0,
235 /* fClass */
236 PDM_DEVREG_CLASS_BUS_PCI | PDM_DEVREG_CLASS_BUS_ISA,
237 /* cMaxInstances */
238 1,
239 /* cbInstance */
240 sizeof(PCIGLOBALS),
241 /* pfnConstruct */
242 ich9pciConstruct,
243 /* pfnDestruct */
244 NULL,
245 /* pfnRelocate */
246 ich9pciRelocate,
247 /* pfnIOCtl */
248 NULL,
249 /* pfnPowerOn */
250 NULL,
251 /* pfnReset */
252 NULL,
253 /* pfnSuspend */
254 NULL,
255 /* pfnResume */
256 NULL,
257 /* pfnAttach */
258 NULL,
259 /* pfnDetach */
260 NULL,
261 /* pfnQueryInterface */
262 NULL,
263 /* pfnInitComplete */
264 NULL,
265 /* pfnPowerOff */
266 NULL,
267 /* pfnSoftReset */
268 NULL,
269 /* u32VersionEnd */
270 PDM_DEVREG_VERSION
271};
272
273/**
274 * The device registration structure
275 * for the PCI-to-PCI bridge.
276 */
277const PDMDEVREG g_DevicePciIch9Bridge =
278{
279 /* u32Version */
280 PDM_DEVREG_VERSION,
281 /* szName */
282 "ich9pcibridge",
283 /* szRCMod */
284 "VBoxDDGC.gc",
285 /* szR0Mod */
286 "VBoxDDR0.r0",
287 /* pszDescription */
288 "ICH9 PCI to PCI bridge",
289 /* fFlags */
290 PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0,
291 /* fClass */
292 PDM_DEVREG_CLASS_BUS_PCI,
293 /* cMaxInstances */
294 ~0,
295 /* cbInstance */
296 sizeof(PCIBUS),
297 /* pfnConstruct */
298 ich9pcibridgeConstruct,
299 /* pfnDestruct */
300 NULL,
301 /* pfnRelocate */
302 ich9pcibridgeRelocate,
303 /* pfnIOCtl */
304 NULL,
305 /* pfnPowerOn */
306 NULL,
307 /* pfnReset */
308 ich9pcibridgeReset,
309 /* pfnSuspend */
310 NULL,
311 /* pfnResume */
312 NULL,
313 /* pfnAttach */
314 NULL,
315 /* pfnDetach */
316 NULL,
317 /* pfnQueryInterface */
318 NULL,
319 /* pfnInitComplete */
320 NULL,
321 /* pfnPowerOff */
322 NULL,
323 /* pfnSoftReset */
324 NULL,
325 /* u32VersionEnd */
326 PDM_DEVREG_VERSION
327};
328
329#endif /* IN_RING3 */
330#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
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