DevPciIch9.cpp@ 32598

Last change on this file since 32598 was 32557, checked in by vboxsync, 15 years ago
PCI: saved state code in ICH9
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1	/* $Id: DevPciIch9.cpp 32557 2010-09-16 12:35:25Z vboxsync $ */
2	/** @file
3	* DevPCI - ICH9 southbridge PCI bus emulation Device.
4	*/
5
6	/*
7	* Copyright (C) 2010 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/*******************************************************************************
19	* Header Files *
20	*******************************************************************************/
21	#define LOG_GROUP LOG_GROUP_DEV_PCI
22	/* Hack to get PCIDEVICEINT declare at the right point - include "PCIInternal.h". */
23	#define PCI_INCLUDE_PRIVATE
24	#include <VBox/pci.h>
25	#include <VBox/pdmdev.h>
26	#include <iprt/asm.h>
27	#include <iprt/assert.h>
28	#include <iprt/string.h>
29
30	#include "../Builtins.h"
31
32	/**
33	* PCI Bus instance.
34	*/
35	typedef struct PCIBus
36	{
37	/** Bus number. */
38	int32_t iBus;
39	/** Number of bridges attached to the bus. */
40	uint32_t cBridges;
41
42	/** Array of PCI devices. We assume 32 slots, each with 8 functions. */
43	R3PTRTYPE(PPCIDEVICE) apDevices[256];
44	/** Array of bridges attached to the bus. */
45	R3PTRTYPE(PPCIDEVICE *) papBridgesR3;
46
47	/** R3 pointer to the device instance. */
48	PPDMDEVINSR3 pDevInsR3;
49	/** Pointer to the PCI R3 helpers. */
50	PCPDMPCIHLPR3 pPciHlpR3;
51
52	/** R0 pointer to the device instance. */
53	PPDMDEVINSR0 pDevInsR0;
54	/** Pointer to the PCI R0 helpers. */
55	PCPDMPCIHLPR0 pPciHlpR0;
56
57	/** RC pointer to the device instance. */
58	PPDMDEVINSRC pDevInsRC;
59	/** Pointer to the PCI RC helpers. */
60	PCPDMPCIHLPRC pPciHlpRC;
61
62	/** The PCI device for the PCI bridge. */
63	PCIDEVICE aPciDev;
64
65	} PCIBUS, *PPCIBUS;
66
67
68	/** @def PCI_IRQ_PINS
69	* Number of pins for interrupts (PIRQ#0...PIRQ#3)
70	*/
71	#define PCI_IRQ_PINS 4
72
73	/** @def PCI_APIC_IRQ_PINS
74	* Number of pins for interrupts if the APIC is used.
75	*/
76	#define PCI_APIC_IRQ_PINS 8
77
78	/**
79	* PCI Globals - This is the host-to-pci bridge and the root bus.
80	*/
81	typedef struct
82	{
83	/** R3 pointer to the device instance. */
84	PPDMDEVINSR3 pDevInsR3;
85	/** R0 pointer to the device instance. */
86	PPDMDEVINSR0 pDevInsR0;
87	/** RC pointer to the device instance. */
88	PPDMDEVINSRC pDevInsRC;
89
90	#if HC_ARCH_BITS == 64
91	uint32_t Alignment0;
92	#endif
93
94	/** I/O APIC irq levels */
95	volatile uint32_t uaPciApicIrqLevels[PCI_APIC_IRQ_PINS];
96
97	#if 1 /* Will be moved into the BIOS soon. */
98	/** The next I/O port address which the PCI BIOS will use. */
99	uint32_t uPciBiosIo;
100	/** The next MMIO address which the PCI BIOS will use. */
101	uint32_t uPciBiosMmio;
102	/** Actual bus number. */
103	uint8_t uBus;
104	#endif
105
106
107	/** Config register. */
108	uint32_t uConfigReg;
109
110	/** PCI bus which is attached to the host-to-PCI bridge. */
111	PCIBUS aPciBus;
112
113	} PCIGLOBALS, *PPCIGLOBALS;
114
115
116	/*******************************************************************************
117	* Defined Constants And Macros *
118	*******************************************************************************/
119
120	/** @def VBOX_ICH9PCI_SAVED_STATE_VERSION
121	* Saved state version of the ICH9 PCI bus device.
122	*/
123	#define VBOX_ICH9PCI_SAVED_STATE_VERSION 1
124
125	/** Converts a bus instance pointer to a device instance pointer. */
126	#define PCIBUS_2_DEVINS(pPciBus) ((pPciBus)->CTX_SUFF(pDevIns))
127	/** Converts a device instance pointer to a PCIGLOBALS pointer. */
128	#define DEVINS_2_PCIGLOBALS(pDevIns) ((PPCIGLOBALS)(PDMINS_2_DATA(pDevIns, PPCIGLOBALS)))
129	/** Converts a device instance pointer to a PCIBUS pointer. */
130	#define DEVINS_2_PCIBUS(pDevIns) ((PPCIBUS)(&PDMINS_2_DATA(pDevIns, PPCIGLOBALS)->aPciBus))
131	/** Converts a pointer to a PCI root bus instance to a PCIGLOBALS pointer.
132	*/
133	#define PCIROOTBUS_2_PCIGLOBALS(pPciBus) ( (PPCIGLOBALS)((uintptr_t)(pPciBus) - RT_OFFSETOF(PCIGLOBALS, aPciBus)) )
134
135
136	/** @def PCI_LOCK
137	* Acquires the PDM lock. This is a NOP if locking is disabled. */
138	/** @def PCI_UNLOCK
139	* Releases the PDM lock. This is a NOP if locking is disabled. */
140	#define PCI_LOCK(pDevIns, rc) \
141	do { \
142	int rc2 = DEVINS_2_PCIBUS(pDevIns)->CTX_SUFF(pPciHlp)->pfnLock((pDevIns), rc); \
143	if (rc2 != VINF_SUCCESS) \
144	return rc2; \
145	} while (0)
146	#define PCI_UNLOCK(pDevIns) \
147	DEVINS_2_PCIBUS(pDevIns)->CTX_SUFF(pPciHlp)->pfnUnlock(pDevIns)
148
149	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
150
151	RT_C_DECLS_BEGIN
152
153	PDMBOTHCBDECL(void) ich9pciSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel);
154	PDMBOTHCBDECL(void) ich9pcibridgeSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel);
155	PDMBOTHCBDECL(int) ich9pciIOPortAddressWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
156	PDMBOTHCBDECL(int) ich9pciIOPortAddressRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb);
157	PDMBOTHCBDECL(int) ich9pciIOPortDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
158	PDMBOTHCBDECL(int) ich9pciIOPortDataRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb);
159
160	RT_C_DECLS_END
161
162	/* Prototypes */
163	static void ich9pciSetIrqInternal(PPCIGLOBALS pGlobals, uint8_t uDevFn, PPCIDEVICE pPciDev, int iIrq, int iLevel);
164	#ifdef IN_RING3
165	static int ich9pciRegisterInternal(PPCIBUS pBus, int iDev, PPCIDEVICE pPciDev, const char *pszName);
166	static void ich9pciUpdateMappings(PCIDevice *d);
167	static DECLCALLBACK(uint32_t) ich9pciConfigRead(PCIDevice *aDev, uint32_t u32Address, unsigned len);
168	DECLINLINE(PPCIDEVICE) ich9pciFindBridge(PPCIBUS pBus, uint8_t iBus);
169	static void ich9pciBiosInitDevice(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint8_t cBridgeDepth, uint8_t *paBridgePositions);
170	#endif
171
172	PDMBOTHCBDECL(void) ich9pciSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel)
173	{
174	ich9pciSetIrqInternal(PDMINS_2_DATA(pDevIns, PPCIGLOBALS), pPciDev->devfn, pPciDev, iIrq, iLevel);
175	}
176
177	PDMBOTHCBDECL(void) ich9pcibridgeSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel)
178	{
179	/*
180	* The PCI-to-PCI bridge specification defines how the interrupt pins
181	* are routed from the secondary to the primary bus (see chapter 9).
182	* iIrq gives the interrupt pin the pci device asserted.
183	* We change iIrq here according to the spec and call the SetIrq function
184	* of our parent passing the device which asserted the interrupt instead of the device of the bridge.
185	*/
186	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
187	PPCIDEVICE pPciDevBus = pPciDev;
188	int iIrqPinBridge = iIrq;
189	uint8_t uDevFnBridge = 0;
190
191	/* Walk the chain until we reach the host bus. */
192	do
193	{
194	uDevFnBridge = pBus->aPciDev.devfn;
195	iIrqPinBridge = ((pPciDevBus->devfn >> 3) + iIrqPinBridge) & 3;
196
197	/* Get the parent. */
198	pBus = pBus->aPciDev.Int.s.CTX_SUFF(pBus);
199	pPciDevBus = &pBus->aPciDev;
200	} while (pBus->iBus != 0);
201
202	AssertMsgReturnVoid(pBus->iBus == 0, ("This is not the host pci bus iBus=%d\n", pBus->iBus));
203	ich9pciSetIrqInternal(PCIROOTBUS_2_PCIGLOBALS(pBus), uDevFnBridge, pPciDev, iIrqPinBridge, iLevel);
204	}
205
206	/**
207	* Port I/O Handler for PCI address OUT operations.
208	*
209	* @returns VBox status code.
210	*
211	* @param pDevIns The device instance.
212	* @param pvUser User argument - ignored.
213	* @param uPort Port number used for the OUT operation.
214	* @param u32 The value to output.
215	* @param cb The value size in bytes.
216	*/
217	PDMBOTHCBDECL(int) ich9pciIOPortAddressWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
218	{
219	Log(("ich9pciIOPortAddressWrite: Port=%#x u32=%#x cb=%d\n", Port, u32, cb));
220	NOREF(pvUser);
221	if (cb == 4)
222	{
223	PPCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
224	PCI_LOCK(pDevIns, VINF_IOM_HC_IOPORT_WRITE);
225	pThis->uConfigReg = u32 & ~3; /* Bits 0-1 are reserved and we silently clear them */
226	PCI_UNLOCK(pDevIns);
227	}
228	return VINF_SUCCESS;
229	}
230
231	/**
232	* Port I/O Handler for PCI address IN operations.
233	*
234	* @returns VBox status code.
235	*
236	* @param pDevIns The device instance.
237	* @param pvUser User argument - ignored.
238	* @param uPort Port number used for the IN operation.
239	* @param pu32 Where to store the result.
240	* @param cb Number of bytes read.
241	*/
242	PDMBOTHCBDECL(int) ich9pciIOPortAddressRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
243	{
244	NOREF(pvUser);
245	if (cb == 4)
246	{
247	PPCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
248	PCI_LOCK(pDevIns, VINF_IOM_HC_IOPORT_READ);
249	*pu32 = pThis->uConfigReg;
250	PCI_UNLOCK(pDevIns);
251	Log(("pciIOPortAddressRead: Port=%#x cb=%d -> %#x\n", Port, cb, *pu32));
252	return VINF_SUCCESS;
253	}
254
255	Log(("ich9pciIOPortAddressRead: Port=%#x cb=%d VERR_IOM_IOPORT_UNUSED\n", Port, cb));
256
257	return VERR_IOM_IOPORT_UNUSED;
258	}
259
260	static int ich9pciDataWrite(PPCIGLOBALS pGlobals, uint32_t addr, uint32_t val, int len)
261	{
262	uint8_t iBus, iDevice;
263	uint32_t uConfigReg;
264
265	Log(("ich9pciDataWrite: addr=%08x val=%08x len=%d\n", pGlobals->uConfigReg, val, len));
266
267	if (!(pGlobals->uConfigReg & (1 << 31)))
268	return VINF_SUCCESS;
269
270	if ((pGlobals->uConfigReg & 0x3) != 0)
271	return VINF_SUCCESS;
272
273	/* Compute destination device */
274	iBus = (pGlobals->uConfigReg >> 16) & 0xff;
275	iDevice = (pGlobals->uConfigReg >> 8) & 0xff;
276	/* And config register */
277	uConfigReg = (pGlobals->uConfigReg & 0xfc) \| (addr & 3);
278	if (iBus != 0)
279	{
280	if (pGlobals->aPciBus.cBridges)
281	{
282	#ifdef IN_RING3 /** @todo do lookup in R0/RC too! */
283	PPCIDEVICE pBridgeDevice = ich9pciFindBridge(&pGlobals->aPciBus, iBus);
284	if (pBridgeDevice)
285	{
286	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigWrite);
287	pBridgeDevice->Int.s.pfnBridgeConfigWrite(pBridgeDevice->pDevIns, iBus, iDevice, uConfigReg, val, len);
288	}
289	#else
290	return VINF_IOM_HC_IOPORT_WRITE;
291	#endif
292	}
293	}
294	else
295	{
296	if (pGlobals->aPciBus.apDevices[iDevice])
297	{
298	#ifdef IN_RING3
299	R3PTRTYPE(PCIDevice *) aDev = pGlobals->aPciBus.apDevices[iDevice];
300	Log(("ich9pciConfigWrite: %s: addr=%02x val=%08x len=%d\n", aDev->name, uConfigReg, val, len));
301	aDev->Int.s.pfnConfigWrite(aDev, uConfigReg, val, len);
302	#else
303	return VINF_IOM_HC_IOPORT_WRITE;
304	#endif
305	}
306	}
307	return VINF_SUCCESS;
308	}
309
310	/**
311	* Port I/O Handler for PCI data OUT operations.
312	*
313	* @returns VBox status code.
314	*
315	* @param pDevIns The device instance.
316	* @param pvUser User argument - ignored.
317	* @param uPort Port number used for the OUT operation.
318	* @param u32 The value to output.
319	* @param cb The value size in bytes.
320	*/
321	PDMBOTHCBDECL(int) ich9pciIOPortDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
322	{
323	Log(("pciIOPortDataWrite: Port=%#x u32=%#x cb=%d\n", Port, u32, cb));
324	NOREF(pvUser);
325	int rc = VINF_SUCCESS;
326	if (!(Port % cb))
327	{
328	PCI_LOCK(pDevIns, VINF_IOM_HC_IOPORT_WRITE);
329	rc = ich9pciDataWrite(PDMINS_2_DATA(pDevIns, PPCIGLOBALS), Port, u32, cb);
330	PCI_UNLOCK(pDevIns);
331	}
332	else
333	AssertMsgFailed(("Unaligned write to port %#x u32=%#x cb=%d\n", Port, u32, cb));
334	return rc;
335	}
336
337	static int ich9pciDataRead(PPCIGLOBALS pGlobals, uint32_t addr, int len, uint32_t *pu32)
338	{
339	uint8_t iBus, iDevice;
340	uint32_t uConfigReg;
341
342	*pu32 = 0xffffffff;
343
344	if (!(pGlobals->uConfigReg & (1 << 31)))
345	return VINF_SUCCESS;
346
347	if ((pGlobals->uConfigReg & 0x3) != 0)
348	return VINF_SUCCESS;
349
350	/* Compute destination device */
351	iBus = (pGlobals->uConfigReg >> 16) & 0xff;
352	iDevice = (pGlobals->uConfigReg >> 8) & 0xff;
353	/* And config register */
354	uConfigReg = (pGlobals->uConfigReg & 0xfc) \| (addr & 3);
355	if (iBus != 0)
356	{
357	if (pGlobals->aPciBus.cBridges)
358	{
359	#ifdef IN_RING3 /** @todo do lookup in R0/RC too! */
360	PPCIDEVICE pBridgeDevice = ich9pciFindBridge(&pGlobals->aPciBus, iBus);
361	if (pBridgeDevice)
362	{
363	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigRead);
364	*pu32 = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->pDevIns, iBus, iDevice, uConfigReg, len);
365	}
366	#else
367	return VINF_IOM_HC_IOPORT_READ;
368	#endif
369	}
370	}
371	else
372	{
373	if (pGlobals->aPciBus.apDevices[iDevice])
374	{
375	#ifdef IN_RING3
376	R3PTRTYPE(PCIDevice *) aDev = pGlobals->aPciBus.apDevices[iDevice];
377	*pu32 = aDev->Int.s.pfnConfigRead(aDev, uConfigReg, len);
378	Log(("ich9pciConfigRead: %s: addr=%02x val=%08x len=%d\n", aDev->name, uConfigReg, *pu32, len));
379	#else
380	return VINF_IOM_HC_IOPORT_READ;
381	#endif
382	}
383	}
384
385	return VINF_SUCCESS;
386	}
387
388	/**
389	* Port I/O Handler for PCI data IN operations.
390	*
391	* @returns VBox status code.
392	*
393	* @param pDevIns The device instance.
394	* @param pvUser User argument - ignored.
395	* @param uPort Port number used for the IN operation.
396	* @param pu32 Where to store the result.
397	* @param cb Number of bytes read.
398	*/
399	PDMBOTHCBDECL(int) ich9pciIOPortDataRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
400	{
401	NOREF(pvUser);
402	if (!(Port % cb))
403	{
404	PCI_LOCK(pDevIns, VINF_IOM_HC_IOPORT_READ);
405	int rc = ich9pciDataRead(PDMINS_2_DATA(pDevIns, PPCIGLOBALS), Port, cb, pu32);
406	PCI_UNLOCK(pDevIns);
407	Log(("pciIOPortDataRead: Port=%#x cb=%#x -> %#x (%Rrc)\n", Port, cb, *pu32, rc));
408	return rc;
409	}
410	AssertMsgFailed(("Unaligned read from port %#x cb=%d\n", Port, cb));
411	return VERR_IOM_IOPORT_UNUSED;
412	}
413
414	/* Compute mapping of PCI slot and IRQ number to APIC interrupt line */
415	static inline int ich9pciSlot2ApicIrq(uint8_t uSlot, int irq_num)
416	{
417	return (irq_num + uSlot) & 7;
418	}
419
420	/* Add one more level up request on APIC input line */
421	static inline void ich9pciApicLevelUp(PPCIGLOBALS pGlobals, int irq_num)
422	{
423	ASMAtomicIncU32(&pGlobals->uaPciApicIrqLevels[irq_num]);
424	}
425
426	/* Remove one level up request on APIC input line */
427	static inline void ich9pciApicLevelDown(PPCIGLOBALS pGlobals, int irq_num)
428	{
429	ASMAtomicDecU32(&pGlobals->uaPciApicIrqLevels[irq_num]);
430	}
431
432	static void ich9pciApicSetIrq(PPCIBUS pBus, uint8_t uDevFn, PCIDevice *pPciDev, int irq_num1, int iLevel, int iForcedIrq)
433	{
434	/* This is only allowed to be called with a pointer to the root bus. */
435	AssertMsg(pBus->iBus == 0, ("iBus=%u\n", pBus->iBus));
436
437	if (iForcedIrq == -1)
438	{
439	int apic_irq, apic_level;
440	PPCIGLOBALS pGlobals = PCIROOTBUS_2_PCIGLOBALS(pBus);
441	int irq_num = ich9pciSlot2ApicIrq(uDevFn >> 3, irq_num1);
442
443	if ((iLevel & PDM_IRQ_LEVEL_HIGH) == PDM_IRQ_LEVEL_HIGH)
444	ich9pciApicLevelUp(pGlobals, irq_num);
445	else if ((iLevel & PDM_IRQ_LEVEL_HIGH) == PDM_IRQ_LEVEL_LOW)
446	ich9pciApicLevelDown(pGlobals, irq_num);
447
448	apic_irq = irq_num + 0x10;
449	apic_level = pGlobals->uaPciApicIrqLevels[irq_num] != 0;
450	Log3(("ich9pciApicSetIrq: %s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d\n",
451	R3STRING(pPciDev->name), irq_num1, iLevel, apic_irq, apic_level, irq_num));
452	pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), apic_irq, apic_level);
453
454	if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP)
455	{
456	/**
457	* we raised it few lines above, as PDM_IRQ_LEVEL_FLIP_FLOP has
458	* PDM_IRQ_LEVEL_HIGH bit set
459	*/
460	ich9pciApicLevelDown(pGlobals, irq_num);
461	pPciDev->Int.s.uIrqPinState = PDM_IRQ_LEVEL_LOW;
462	apic_level = pGlobals->uaPciApicIrqLevels[irq_num] != 0;
463	Log3(("ich9pciApicSetIrq: %s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d (flop)\n",
464	R3STRING(pPciDev->name), irq_num1, iLevel, apic_irq, apic_level, irq_num));
465	pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), apic_irq, apic_level);
466	}
467	} else {
468	Log3(("ich9pciApicSetIrq: %s: irq_num1=%d level=%d acpi_irq=%d\n",
469	R3STRING(pPciDev->name), irq_num1, iLevel, iForcedIrq));
470	pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), iForcedIrq, iLevel);
471	}
472	}
473
474	static void ich9pciSetIrqInternal(PPCIGLOBALS pGlobals, uint8_t uDevFn, PPCIDEVICE pPciDev, int iIrq, int iLevel)
475	{
476	PPCIBUS pBus = &pGlobals->aPciBus;
477	const bool fIsAcpiDevice = PCIDevGetDeviceId(pPciDev) == 0x7113;
478
479	/* Check if the state changed. */
480	if (pPciDev->Int.s.uIrqPinState != iLevel)
481	{
482	pPciDev->Int.s.uIrqPinState = (iLevel & PDM_IRQ_LEVEL_HIGH);
483
484	/* Send interrupt to I/O APIC only now. */
485	if (fIsAcpiDevice)
486	/*
487	* ACPI needs special treatment since SCI is hardwired and
488	* should not be affected by PCI IRQ routing tables at the
489	* same time SCI IRQ is shared in PCI sense hence this
490	* kludge (i.e. we fetch the hardwired value from ACPIs
491	* PCI device configuration space).
492	*/
493	ich9pciApicSetIrq(pBus, uDevFn, pPciDev, -1, iLevel, PCIDevGetInterruptLine(pPciDev));
494	else
495	ich9pciApicSetIrq(pBus, uDevFn, pPciDev, iIrq, iLevel, -1);
496	}
497	}
498
499	#ifdef IN_RING3
500	DECLINLINE(PPCIDEVICE) ich9pciFindBridge(PPCIBUS pBus, uint8_t iBus)
501	{
502	/* Search for a fitting bridge. */
503	for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
504	{
505	/*
506	* Examine secondary and subordinate bus number.
507	* If the target bus is in the range we pass the request on to the bridge.
508	*/
509	PPCIDEVICE pBridgeTemp = pBus->papBridgesR3[iBridge];
510	AssertMsg(pBridgeTemp && pBridgeTemp->Int.s.fPciToPciBridge,
511	("Device is not a PCI bridge but on the list of PCI bridges\n"));
512
513	if ( iBus >= pBridgeTemp->config[VBOX_PCI_SECONDARY_BUS]
514	&& iBus <= pBridgeTemp->config[VBOX_PCI_SUBORDINATE_BUS])
515	return pBridgeTemp;
516	}
517
518	/* Nothing found. */
519	return NULL;
520	}
521
522	static inline uint32_t ich9pciGetRegionReg(int iRegion)
523	{
524	return (iRegion == PCI_ROM_SLOT) ?
525	VBOX_PCI_ROM_ADDRESS : (VBOX_PCI_BASE_ADDRESS_0 + iRegion * 4);
526	}
527
528	#define INVALID_PCI_ADDRESS ~0U
529
530	static void ich9pciUpdateMappings(PCIDevice* pDev)
531	{
532	PPCIBUS pBus = pDev->Int.s.CTX_SUFF(pBus);
533	uint32_t uLast, uNew;
534
535	int iCmd = PCIDevGetCommand(pDev);
536	for (int iRegion = 0; iRegion < PCI_NUM_REGIONS; iRegion++)
537	{
538	PCIIORegion* pRegion = &pDev->Int.s.aIORegions[iRegion];
539	uint32_t uConfigReg = ich9pciGetRegionReg(iRegion);
540	int32_t iRegionSize = pRegion->size;
541	int rc;
542
543	if (iRegionSize == 0)
544	continue;
545
546	if (pRegion->type & PCI_ADDRESS_SPACE_IO)
547	{
548	/* port IO region */
549	if (iCmd & PCI_COMMAND_IOACCESS)
550	{
551	/* IO access allowed */
552	uNew = ich9pciConfigRead(pDev, uConfigReg, 4);
553	uNew &= ~(iRegionSize - 1);
554	uLast = uNew + iRegionSize - 1;
555	/* only 64K ioports on PC */
556	if (uLast <= uNew \|\| uNew == 0 \|\| uLast >= 0x10000)
557	uNew = INVALID_PCI_ADDRESS;
558	} else
559	uNew = INVALID_PCI_ADDRESS;
560	}
561	else
562	{
563	/* MMIO region */
564	if (iCmd & PCI_COMMAND_MEMACCESS)
565	{
566	uNew = ich9pciConfigRead(pDev, uConfigReg, 4);
567	/* the ROM slot has a specific enable bit */
568	if (iRegion == PCI_ROM_SLOT && !(uNew & 1))
569	uNew = INVALID_PCI_ADDRESS;
570	else
571	{
572	uNew &= ~(iRegionSize - 1);
573	uLast = uNew + iRegionSize - 1;
574	/* NOTE: we do not support wrapping */
575	/* XXX: as we cannot support really dynamic
576	mappings, we handle specific values as invalid
577	mappings. */
578	if (uLast <= uNew \|\| uNew == 0 \|\| uLast == ~0U)
579	uNew = INVALID_PCI_ADDRESS;
580	}
581	} else
582	uNew = INVALID_PCI_ADDRESS;
583	}
584	/* now do the real mapping */
585	if (uNew != pRegion->addr)
586	{
587	if (pRegion->addr != INVALID_PCI_ADDRESS)
588	{
589	if (pRegion->type & PCI_ADDRESS_SPACE_IO)
590	{
591	/* Port IO */
592	int devclass;
593	/* NOTE: specific hack for IDE in PC case:
594	only one byte must be mapped. */
595	/// @todo: do we need it?
596	devclass = pDev->config[0x0a] \| (pDev->config[0x0b] << 8);
597	if (devclass == 0x0101 && iRegionSize == 4)
598	{
599	rc = PDMDevHlpIOPortDeregister(pDev->pDevIns, pRegion->addr + 2, 1);
600	AssertRC(rc);
601	}
602	else
603	{
604	rc = PDMDevHlpIOPortDeregister(pDev->pDevIns, pRegion->addr, pRegion->size);
605	AssertRC(rc);
606	}
607	}
608	else
609	{
610	RTGCPHYS GCPhysBase = pRegion->addr;
611	if (pBus->pPciHlpR3->pfnIsMMIO2Base(pBus->pDevInsR3, pDev->pDevIns, GCPhysBase))
612	{
613	/* unmap it. */
614	rc = pRegion->map_func(pDev, iRegion, NIL_RTGCPHYS, pRegion->size, (PCIADDRESSSPACE)(pRegion->type));
615	AssertRC(rc);
616	rc = PDMDevHlpMMIO2Unmap(pDev->pDevIns, iRegion, GCPhysBase);
617	}
618	else
619	rc = PDMDevHlpMMIODeregister(pDev->pDevIns, GCPhysBase, pRegion->size);
620	AssertMsgRC(rc, ("rc=%Rrc d=%s i=%d GCPhysBase=%RGp size=%#x\n", rc, pDev->name, iRegion, GCPhysBase, pRegion->size));
621	}
622	}
623	pRegion->addr = uNew;
624	if (pRegion->addr != INVALID_PCI_ADDRESS)
625	{
626	/* finally, map the region */
627	rc = pRegion->map_func(pDev, iRegion,
628	pRegion->addr, pRegion->size,
629	(PCIADDRESSSPACE)(pRegion->type));
630	AssertRC(rc);
631	}
632	}
633	}
634	}
635
636	static DECLCALLBACK(int) ich9pciRegister(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, const char *pszName, int iDev)
637	{
638	PPCIBUS pBus = DEVINS_2_PCIBUS(pDevIns);
639
640	/*
641	* Check input.
642	*/
643	if ( !pszName
644	\|\| !pPciDev
645	\|\| iDev >= (int)RT_ELEMENTS(pBus->apDevices)
646	)
647	{
648	AssertMsgFailed(("Invalid argument! pszName=%s pPciDev=%p iDev=%d\n", pszName, pPciDev, iDev));
649	return VERR_INVALID_PARAMETER;
650	}
651
652	/*
653	* Register the device.
654	*/
655	return ich9pciRegisterInternal(pBus, iDev, pPciDev, pszName);
656	}
657
658	static DECLCALLBACK(int) ich9pcibridgeRegister(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, const char *pszName, int iDev)
659	{
660	return 0;
661	}
662
663	static DECLCALLBACK(int) ich9pciIORegionRegister(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iRegion, uint32_t cbRegion, PCIADDRESSSPACE enmType, PFNPCIIOREGIONMAP pfnCallback)
664	{
665	/*
666	* Validate.
667	*/
668	AssertMsgReturn( enmType == PCI_ADDRESS_SPACE_MEM
669	\|\| enmType == PCI_ADDRESS_SPACE_IO
670	\|\| enmType == PCI_ADDRESS_SPACE_MEM_PREFETCH,
671	("Invalid enmType=%#x? Or was this a bitmask after all...\n", enmType),
672	VERR_INVALID_PARAMETER);
673	AssertMsgReturn((unsigned)iRegion < PCI_NUM_REGIONS,
674	("Invalid iRegion=%d PCI_NUM_REGIONS=%d\n", iRegion, PCI_NUM_REGIONS),
675	VERR_INVALID_PARAMETER);
676	int iLastSet = ASMBitLastSetU32(cbRegion);
677	AssertMsgReturn( iLastSet != 0
678	&& RT_BIT_32(iLastSet - 1) == cbRegion,
679	("Invalid cbRegion=%#x iLastSet=%#x (not a power of 2 or 0)\n", cbRegion, iLastSet),
680	VERR_INVALID_PARAMETER);
681
682	/*
683	* Register the I/O region.
684	*/
685	PPCIIOREGION pRegion = &pPciDev->Int.s.aIORegions[iRegion];
686	pRegion->addr = ~0U;
687	pRegion->size = cbRegion;
688	pRegion->type = enmType;
689	pRegion->map_func = pfnCallback;
690
691	/* Set type in the config space. */
692	uint32_t u32Address = ich9pciGetRegionReg(iRegion);
693	uint32_t u32Value = (enmType == PCI_ADDRESS_SPACE_MEM_PREFETCH ? (1 << 3) : 0)
694	\| (enmType == PCI_ADDRESS_SPACE_IO ? 1 : 0);
695	(uint32_t )(pPciDev->config + u32Address) = RT_H2LE_U32(u32Value);
696
697	return VINF_SUCCESS;
698	}
699
700	static DECLCALLBACK(void) ich9pciSetConfigCallbacks(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PFNPCICONFIGREAD pfnRead, PPFNPCICONFIGREAD ppfnReadOld,
701	PFNPCICONFIGWRITE pfnWrite, PPFNPCICONFIGWRITE ppfnWriteOld)
702	{
703	if (ppfnReadOld)
704	*ppfnReadOld = pPciDev->Int.s.pfnConfigRead;
705	pPciDev->Int.s.pfnConfigRead = pfnRead;
706
707	if (ppfnWriteOld)
708	*ppfnWriteOld = pPciDev->Int.s.pfnConfigWrite;
709	pPciDev->Int.s.pfnConfigWrite = pfnWrite;
710	}
711
712	/**
713	* Saves a state of the PCI device.
714	*
715	* @returns VBox status code.
716	* @param pDevIns Device instance of the PCI Bus.
717	* @param pPciDev Pointer to PCI device.
718	* @param pSSM The handle to save the state to.
719	*/
720	static DECLCALLBACK(int) pciGenericSaveExec(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PSSMHANDLE pSSM)
721	{
722	return SSMR3PutMem(pSSM, &pPciDev->config[0], sizeof(pPciDev->config));
723	}
724
725	static int pciR3CommonSaveExec(PPCIBUS pBus, PSSMHANDLE pSSM)
726	{
727	/*
728	* Iterate thru all the devices.
729	*/
730	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
731	{
732	PPCIDEVICE pDev = pBus->apDevices[i];
733	if (pDev)
734	{
735	/* Device position */
736	SSMR3PutU32(pSSM, i);
737	/* PCI config registers */
738	SSMR3PutMem(pSSM, pDev->config, sizeof(pDev->config));
739
740	/* IRQ pin state */
741	int rc = SSMR3PutS32(pSSM, pDev->Int.s.uIrqPinState);
742	if (RT_FAILURE(rc))
743	return rc;
744	}
745	}
746	return SSMR3PutU32(pSSM, UINT32_MAX); /* terminator */
747	}
748
749	static DECLCALLBACK(int) pciR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
750	{
751	PPCIBUS pThis = PDMINS_2_DATA(pDevIns, PPCIBUS);
752	return pciR3CommonSaveExec(pThis, pSSM);
753	}
754
755
756	static DECLCALLBACK(int) pcibridgeR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
757	{
758	PPCIBUS pThis = PDMINS_2_DATA(pDevIns, PPCIBUS);
759	return pciR3CommonSaveExec(pThis, pSSM);
760	}
761
762
763	/**
764	* Common routine for restoring the config registers of a PCI device.
765	*
766	* @param pDev The PCI device.
767	* @param pbSrcConfig The configuration register values to be loaded.
768	* @param fIsBridge Whether this is a bridge device or not.
769	*/
770	static void pciR3CommonRestoreConfig(PPCIDEVICE pDev, uint8_t const *pbSrcConfig, bool fIsBridge)
771	{
772	/*
773	* This table defines the fields for normal devices and bridge devices, and
774	* the order in which they need to be restored.
775	*/
776	static const struct PciField
777	{
778	uint8_t off;
779	uint8_t cb;
780	uint8_t fWritable;
781	uint8_t fBridge;
782	const char *pszName;
783	} s_aFields[] =
784	{
785	/* off,cb,fW,fB, pszName */
786	{ VBOX_PCI_VENDOR_ID, 2, 0, 3, "VENDOR_ID" },
787	{ VBOX_PCI_DEVICE_ID, 2, 0, 3, "DEVICE_ID" },
788	{ VBOX_PCI_STATUS, 2, 1, 3, "STATUS" },
789	{ VBOX_PCI_REVISION_ID, 1, 0, 3, "REVISION_ID" },
790	{ VBOX_PCI_CLASS_PROG, 1, 0, 3, "CLASS_PROG" },
791	{ VBOX_PCI_CLASS_SUB, 1, 0, 3, "CLASS_SUB" },
792	{ VBOX_PCI_CLASS_DEVICE, 1, 0, 3, "CLASS_BASE" },
793	{ VBOX_PCI_CACHE_LINE_SIZE, 1, 1, 3, "CACHE_LINE_SIZE" },
794	{ VBOX_PCI_LATENCY_TIMER, 1, 1, 3, "LATENCY_TIMER" },
795	{ VBOX_PCI_HEADER_TYPE, 1, 0, 3, "HEADER_TYPE" },
796	{ VBOX_PCI_BIST, 1, 1, 3, "BIST" },
797	{ VBOX_PCI_BASE_ADDRESS_0, 4, 1, 3, "BASE_ADDRESS_0" },
798	{ VBOX_PCI_BASE_ADDRESS_1, 4, 1, 3, "BASE_ADDRESS_1" },
799	{ VBOX_PCI_BASE_ADDRESS_2, 4, 1, 1, "BASE_ADDRESS_2" },
800	{ VBOX_PCI_PRIMARY_BUS, 1, 1, 2, "PRIMARY_BUS" }, // fWritable = ??
801	{ VBOX_PCI_SECONDARY_BUS, 1, 1, 2, "SECONDARY_BUS" }, // fWritable = ??
802	{ VBOX_PCI_SUBORDINATE_BUS, 1, 1, 2, "SUBORDINATE_BUS" }, // fWritable = ??
803	{ VBOX_PCI_SEC_LATENCY_TIMER, 1, 1, 2, "SEC_LATENCY_TIMER" }, // fWritable = ??
804	{ VBOX_PCI_BASE_ADDRESS_3, 4, 1, 1, "BASE_ADDRESS_3" },
805	{ VBOX_PCI_IO_BASE, 1, 1, 2, "IO_BASE" }, // fWritable = ??
806	{ VBOX_PCI_IO_LIMIT, 1, 1, 2, "IO_LIMIT" }, // fWritable = ??
807	{ VBOX_PCI_SEC_STATUS, 2, 1, 2, "SEC_STATUS" }, // fWritable = ??
808	{ VBOX_PCI_BASE_ADDRESS_4, 4, 1, 1, "BASE_ADDRESS_4" },
809	{ VBOX_PCI_MEMORY_BASE, 2, 1, 2, "MEMORY_BASE" }, // fWritable = ??
810	{ VBOX_PCI_MEMORY_LIMIT, 2, 1, 2, "MEMORY_LIMIT" }, // fWritable = ??
811	{ VBOX_PCI_BASE_ADDRESS_4, 4, 1, 1, "BASE_ADDRESS_4" },
812	{ VBOX_PCI_PREF_MEMORY_BASE, 2, 1, 2, "PREF_MEMORY_BASE" }, // fWritable = ??
813	{ VBOX_PCI_PREF_MEMORY_LIMIT, 2, 1, 2, "PREF_MEMORY_LIMIT" }, // fWritable = ??
814	{ VBOX_PCI_CARDBUS_CIS, 4, 1, 1, "CARDBUS_CIS" }, // fWritable = ??
815	{ VBOX_PCI_PREF_BASE_UPPER32, 4, 1, 2, "PREF_BASE_UPPER32" }, // fWritable = ??
816	{ VBOX_PCI_SUBSYSTEM_VENDOR_ID, 2, 0, 1, "SUBSYSTEM_VENDOR_ID" },// fWritable = !?
817	{ VBOX_PCI_PREF_LIMIT_UPPER32, 4, 1, 2, "PREF_LIMIT_UPPER32" },// fWritable = ??
818	{ VBOX_PCI_SUBSYSTEM_ID, 2, 0, 1, "SUBSYSTEM_ID" }, // fWritable = !?
819	{ VBOX_PCI_ROM_ADDRESS, 4, 1, 1, "ROM_ADDRESS" }, // fWritable = ?!
820	{ VBOX_PCI_IO_BASE_UPPER16, 2, 1, 2, "IO_BASE_UPPER16" }, // fWritable = ?!
821	{ VBOX_PCI_IO_LIMIT_UPPER16, 2, 1, 2, "IO_LIMIT_UPPER16" }, // fWritable = ?!
822	{ VBOX_PCI_CAPABILITY_LIST, 4, 0, 3, "CAPABILITY_LIST" }, // fWritable = !? cb=!?
823	{ VBOX_PCI_RESERVED_38, 4, 1, 1, "RESERVED_38" }, // ???
824	{ VBOX_PCI_ROM_ADDRESS_BR, 4, 1, 2, "ROM_ADDRESS_BR" }, // fWritable = !? cb=!? fBridge=!?
825	{ VBOX_PCI_INTERRUPT_LINE, 1, 1, 3, "INTERRUPT_LINE" }, // fBridge=??
826	{ VBOX_PCI_INTERRUPT_PIN, 1, 0, 3, "INTERRUPT_PIN" }, // fBridge=??
827	{ VBOX_PCI_MIN_GNT, 1, 0, 1, "MIN_GNT" },
828	{ VBOX_PCI_BRIDGE_CONTROL, 2, 1, 2, "BRIDGE_CONTROL" }, // fWritable = !?
829	{ VBOX_PCI_MAX_LAT, 1, 0, 3, "MAX_LAT" }, // fBridge=!?
830	/* The COMMAND register must come last as it requires the ADDRESS
831	registers to be restored before we pretent to change it from 0 to
832	whatever value the guest assigned it. */
833	{ VBOX_PCI_COMMAND, 2, 1, 3, "COMMAND" },
834	};
835
836	#ifdef RT_STRICT
837	/* Check that we've got full register coverage. */
838	uint32_t bmDevice[0x40 / 32];
839	uint32_t bmBridge[0x40 / 32];
840	RT_ZERO(bmDevice);
841	RT_ZERO(bmBridge);
842	for (uint32_t i = 0; i < RT_ELEMENTS(s_aFields); i++)
843	{
844	uint8_t off = s_aFields[i].off;
845	uint8_t cb = s_aFields[i].cb;
846	uint8_t f = s_aFields[i].fBridge;
847	while (cb-- > 0)
848	{
849	if (f & 1) AssertMsg(!ASMBitTest(bmDevice, off), ("%#x\n", off));
850	if (f & 2) AssertMsg(!ASMBitTest(bmBridge, off), ("%#x\n", off));
851	if (f & 1) ASMBitSet(bmDevice, off);
852	if (f & 2) ASMBitSet(bmBridge, off);
853	off++;
854	}
855	}
856	for (uint32_t off = 0; off < 0x40; off++)
857	{
858	AssertMsg(ASMBitTest(bmDevice, off), ("%#x\n", off));
859	AssertMsg(ASMBitTest(bmBridge, off), ("%#x\n", off));
860	}
861	#endif
862
863	/*
864	* Loop thru the fields covering the 64 bytes of standard registers.
865	*/
866	uint8_t const fBridge = fIsBridge ? 2 : 1;
867	uint8_t *pbDstConfig = &pDev->config[0];
868	for (uint32_t i = 0; i < RT_ELEMENTS(s_aFields); i++)
869	if (s_aFields[i].fBridge & fBridge)
870	{
871	uint8_t const off = s_aFields[i].off;
872	uint8_t const cb = s_aFields[i].cb;
873	uint32_t u32Src;
874	uint32_t u32Dst;
875	switch (cb)
876	{
877	case 1:
878	u32Src = pbSrcConfig[off];
879	u32Dst = pbDstConfig[off];
880	break;
881	case 2:
882	u32Src = (uint16_t const )&pbSrcConfig[off];
883	u32Dst = (uint16_t const )&pbDstConfig[off];
884	break;
885	case 4:
886	u32Src = (uint32_t const )&pbSrcConfig[off];
887	u32Dst = (uint32_t const )&pbDstConfig[off];
888	break;
889	default:
890	AssertFailed();
891	continue;
892	}
893
894	if ( u32Src != u32Dst
895	\|\| off == VBOX_PCI_COMMAND)
896	{
897	if (u32Src != u32Dst)
898	{
899	if (!s_aFields[i].fWritable)
900	LogRel(("PCI: %8s/%u: %2u-bit field %s: %x -> %x - !READ ONLY!\n",
901	pDev->name, pDev->pDevIns->iInstance, cb*8, s_aFields[i].pszName, u32Dst, u32Src));
902	else
903	LogRel(("PCI: %8s/%u: %2u-bit field %s: %x -> %x\n",
904	pDev->name, pDev->pDevIns->iInstance, cb*8, s_aFields[i].pszName, u32Dst, u32Src));
905	}
906	if (off == VBOX_PCI_COMMAND)
907	PCIDevSetCommand(pDev, 0); /* For remapping, see pciR3CommonLoadExec. */
908	pDev->Int.s.pfnConfigWrite(pDev, off, u32Src, cb);
909	}
910	}
911
912	/*
913	* The device dependent registers.
914	*
915	* We will not use ConfigWrite here as we have no clue about the size
916	* of the registers, so the device is responsible for correctly
917	* restoring functionality governed by these registers.
918	*/
919	for (uint32_t off = 0x40; off < sizeof(pDev->config); off++)
920	if (pbDstConfig[off] != pbSrcConfig[off])
921	{
922	LogRel(("PCI: %8s/%u: register %02x: %02x -> %02x\n",
923	pDev->name, pDev->pDevIns->iInstance, off, pbDstConfig[off], pbSrcConfig[off])); /** @todo make this Log() later. */
924	pbDstConfig[off] = pbSrcConfig[off];
925	}
926	}
927
928	/**
929	* Common worker for pciR3LoadExec and pcibridgeR3LoadExec.
930	*
931	* @returns VBox status code.
932	* @param pBus The bus which data is being loaded.
933	* @param pSSM The saved state handle.
934	* @param uVersion The data version.
935	* @param uPass The pass.
936	*/
937	static DECLCALLBACK(int) pciR3CommonLoadExec(PPCIBUS pBus, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
938	{
939	uint32_t u32;
940	uint32_t i;
941	int rc;
942
943	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
944
945	/*
946	* Iterate thru all the devices and write 0 to the COMMAND register so
947	* that all the memory is unmapped before we start restoring the saved
948	* mapping locations.
949	*
950	* The register value is restored afterwards so we can do proper
951	* LogRels in pciR3CommonRestoreConfig.
952	*/
953	for (i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
954	{
955	PPCIDEVICE pDev = pBus->apDevices[i];
956	if (pDev)
957	{
958	uint16_t u16 = PCIDevGetCommand(pDev);
959	pDev->Int.s.pfnConfigWrite(pDev, VBOX_PCI_COMMAND, 0, 2);
960	PCIDevSetCommand(pDev, u16);
961	Assert(PCIDevGetCommand(pDev) == u16);
962	}
963	}
964
965	/*
966	* Iterate all the devices.
967	*/
968	for (i = 0;; i++)
969	{
970	PCIDEVICE DevTmp;
971	PPCIDEVICE pDev;
972
973	/* index / terminator */
974	rc = SSMR3GetU32(pSSM, &u32);
975	if (RT_FAILURE(rc))
976	return rc;
977	if (u32 == (uint32_t)~0)
978	break;
979	if ( u32 >= RT_ELEMENTS(pBus->apDevices)
980	\|\| u32 < i)
981	{
982	AssertMsgFailed(("u32=%#x i=%#x\n", u32, i));
983	return rc;
984	}
985
986	/* skip forward to the device checking that no new devices are present. */
987	for (; i < u32; i++)
988	{
989	pDev = pBus->apDevices[i];
990	if (pDev)
991	{
992	LogRel(("New device in slot %#x, %s (vendor=%#06x device=%#06x)\n", i, pDev->name,
993	PCIDevGetVendorId(pDev), PCIDevGetDeviceId(pDev)));
994	if (SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT)
995	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("New device in slot %#x, %s (vendor=%#06x device=%#06x)"),
996	i, pDev->name, PCIDevGetVendorId(pDev), PCIDevGetDeviceId(pDev));
997	}
998	}
999
1000	/* get the data */
1001	DevTmp.Int.s.uIrqPinState = ~0; /* Invalid value in case we have an older saved state to force a state change in pciSetIrq. */
1002	SSMR3GetMem(pSSM, DevTmp.config, sizeof(DevTmp.config));
1003
1004	rc = SSMR3GetS32(pSSM, &DevTmp.Int.s.uIrqPinState);
1005	if (RT_FAILURE(rc))
1006	return rc;
1007
1008	/* check that it's still around. */
1009	pDev = pBus->apDevices[i];
1010	if (!pDev)
1011	{
1012	LogRel(("Device in slot %#x has been removed! vendor=%#06x device=%#06x\n", i,
1013	PCIDevGetVendorId(&DevTmp), PCIDevGetDeviceId(&DevTmp)));
1014	if (SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT)
1015	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Device in slot %#x has been removed! vendor=%#06x device=%#06x"),
1016	i, PCIDevGetVendorId(&DevTmp), PCIDevGetDeviceId(&DevTmp));
1017	continue;
1018	}
1019
1020	/* match the vendor id assuming that this will never be changed. */
1021	if ( DevTmp.config[0] != pDev->config[0]
1022	\|\| DevTmp.config[1] != pDev->config[1])
1023	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Device in slot %#x (%s) vendor id mismatch! saved=%.4Rhxs current=%.4Rhxs"),
1024	i, pDev->name, DevTmp.config, pDev->config);
1025
1026	/* commit the loaded device config. */
1027	pciR3CommonRestoreConfig(pDev, &DevTmp.config[0], false ); /** @todo fix bridge fun! */
1028
1029	pDev->Int.s.uIrqPinState = DevTmp.Int.s.uIrqPinState;
1030	}
1031
1032	return VINF_SUCCESS;
1033	}
1034
1035	/**
1036	* Loads a saved PCI device state.
1037	*
1038	* @returns VBox status code.
1039	* @param pDevIns Device instance of the PCI Bus.
1040	* @param pPciDev Pointer to PCI device.
1041	* @param pSSM The handle to the saved state.
1042	*/
1043	static DECLCALLBACK(int) pciGenericLoadExec(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PSSMHANDLE pSSM)
1044	{
1045	return SSMR3GetMem(pSSM, &pPciDev->config[0], sizeof(pPciDev->config));
1046	}
1047
1048	static DECLCALLBACK(int) pciR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1049	{
1050	PPCIBUS pThis = PDMINS_2_DATA(pDevIns, PPCIBUS);
1051	if (uVersion > VBOX_ICH9PCI_SAVED_STATE_VERSION)
1052	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1053	return pciR3CommonLoadExec(pThis, pSSM, uVersion, uPass);
1054	}
1055
1056	static DECLCALLBACK(int) pcibridgeR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1057	{
1058	PPCIBUS pThis = PDMINS_2_DATA(pDevIns, PPCIBUS);
1059	if (uVersion > VBOX_ICH9PCI_SAVED_STATE_VERSION)
1060	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1061	return pciR3CommonLoadExec(pThis, pSSM, uVersion, uPass);
1062	}
1063
1064	static uint32_t ich9pciConfigRead(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t len)
1065	{
1066	/* Set destination address */
1067	/// @todo: device locking?
1068	pGlobals->uConfigReg = 0x80000000 \| (uBus << 16) \|
1069	(uDevFn << 8) \| (addr & ~3);
1070	uint32_t u32Val;
1071	int rc = ich9pciDataRead(pGlobals, addr & 3, len, &u32Val);
1072	AssertRC(rc);
1073	switch (len)
1074	{
1075	case 1:
1076	u32Val &= 0xff;
1077	break;
1078	case 2:
1079	u32Val &= 0xffff;
1080	break;
1081	}
1082	return u32Val;
1083	}
1084
1085	static void ich9pciConfigWrite(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t val, uint32_t len)
1086	{
1087	/* Set destination address */
1088	/// @todo: device locking?
1089	pGlobals->uConfigReg = 0x80000000 \| (uBus << 16) \|
1090	(uDevFn << 8) \| addr;
1091	ich9pciDataWrite(pGlobals, 0, val, len);
1092	}
1093
1094	static void ich9pciSetRegionAddress(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, int iRegion, uint32_t addr)
1095	{
1096	uint32_t uReg = ich9pciGetRegionReg(iRegion);
1097
1098	/* Read memory type first. */
1099	uint8_t uResourceType = ich9pciConfigRead(pGlobals, uBus, uDevFn, uReg, 1);
1100	/* Read command register. */
1101	uint16_t uCmd = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_COMMAND, 2);
1102
1103	if ( iRegion == PCI_ROM_SLOT )
1104	uCmd \|= PCI_COMMAND_MEMACCESS;
1105	else if ((uResourceType & PCI_ADDRESS_SPACE_IO) == PCI_ADDRESS_SPACE_IO)
1106	uCmd \|= PCI_COMMAND_IOACCESS; /* Enable I/O space access. */
1107	else /* The region is MMIO. */
1108	uCmd \|= PCI_COMMAND_MEMACCESS; /* Enable MMIO access. */
1109
1110	/* Write address of the device. */
1111	ich9pciConfigWrite(pGlobals, uBus, uDevFn, uReg, addr, 4);
1112
1113	/* enable memory mappings */
1114	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_COMMAND, uCmd, 2);
1115	}
1116
1117
1118	static void ich9pciBiosInitBridge(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint8_t cBridgeDepth, uint8_t *paBridgePositions)
1119	{
1120	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_SECONDARY_BUS, pGlobals->uBus, 1);
1121	/* Temporary until we know how many other bridges are behind this one. */
1122	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_SUBORDINATE_BUS, 0xff, 1);
1123
1124	/* Add position of this bridge into the array. */
1125	paBridgePositions[cBridgeDepth+1] = (uDevFn >> 3);
1126
1127	/*
1128	* The I/O range for the bridge must be aligned to a 4KB boundary.
1129	* This does not change anything really as the access to the device is not going
1130	* through the bridge but we want to be compliant to the spec.
1131	*/
1132	if ((pGlobals->uPciBiosIo % 4096) != 0)
1133	{
1134	pGlobals->uPciBiosIo = RT_ALIGN_32(pGlobals->uPciBiosIo, 4*1024);
1135	Log(("%s: Aligned I/O start address. New address %#x\n", __FUNCTION__, pGlobals->uPciBiosIo));
1136	}
1137	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_IO_BASE, (pGlobals->uPciBiosIo >> 8) & 0xf0, 1);
1138
1139	/* The MMIO range for the bridge must be aligned to a 1MB boundary. */
1140	if ((pGlobals->uPciBiosMmio % (1024 * 1024)) != 0)
1141	{
1142	pGlobals->uPciBiosMmio = RT_ALIGN_32(pGlobals->uPciBiosMmio, 1024*1024);
1143	Log(("%s: Aligned MMIO start address. New address %#x\n", __FUNCTION__, pGlobals->uPciBiosMmio));
1144	}
1145	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_MEMORY_BASE, (pGlobals->uPciBiosMmio >> 16) & UINT32_C(0xffff0), 2);
1146
1147	/* Save values to compare later to. */
1148	uint32_t u32IoAddressBase = pGlobals->uPciBiosIo;
1149	uint32_t u32MMIOAddressBase = pGlobals->uPciBiosMmio;
1150
1151	/* Init devices behind the bridge and possibly other bridges as well. */
1152	for (int iDev = 0; iDev <= 255; iDev++)
1153	ich9pciBiosInitDevice(pGlobals, uBus + 1, iDev, cBridgeDepth + 1, paBridgePositions);
1154
1155	/* The number of bridges behind the this one is now available. */
1156	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_SUBORDINATE_BUS, pGlobals->uBus, 1);
1157
1158	/*
1159	* Set I/O limit register. If there is no device with I/O space behind the bridge
1160	* we set a lower value than in the base register.
1161	* The result with a real bridge is that no I/O transactions are passed to the secondary
1162	* interface. Again this doesn't really matter here but we want to be compliant to the spec.
1163	*/
1164	if ((u32IoAddressBase != pGlobals->uPciBiosIo) && ((pGlobals->uPciBiosIo % 4096) != 0))
1165	{
1166	/* The upper boundary must be one byte less than a 4KB boundary. */
1167	pGlobals->uPciBiosIo = RT_ALIGN_32(pGlobals->uPciBiosIo, 4*1024);
1168	}
1169
1170	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_IO_LIMIT, ((pGlobals->uPciBiosIo >> 8) & 0xf0) - 1, 1);
1171
1172	/* Same with the MMIO limit register but with 1MB boundary here. */
1173	if ((u32MMIOAddressBase != pGlobals->uPciBiosMmio) && ((pGlobals->uPciBiosMmio % (1024 * 1024)) != 0))
1174	{
1175	/* The upper boundary must be one byte less than a 1MB boundary. */
1176	pGlobals->uPciBiosMmio = RT_ALIGN_32(pGlobals->uPciBiosMmio, 1024*1024);
1177	}
1178	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_MEMORY_LIMIT, ((pGlobals->uPciBiosMmio >> 16) & UINT32_C(0xfff0)) - 1, 2);
1179
1180	/*
1181	* Set the prefetch base and limit registers. We currently have no device with a prefetchable region
1182	* which may be behind a bridge. Thatswhy it is unconditionally disabled here atm by writing a higher value into
1183	* the base register than in the limit register.
1184	*/
1185	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_MEMORY_BASE, 0xfff0, 2);
1186	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_MEMORY_LIMIT, 0x0, 2);
1187	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_BASE_UPPER32, 0x00, 4);
1188	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_LIMIT_UPPER32, 0x00, 4);
1189	}
1190
1191	static void ich9pciBiosInitDevice(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint8_t cBridgeDepth, uint8_t *paBridgePositions)
1192	{
1193	uint32_t *paddr;
1194	uint16_t uDevClass, uVendor, uDevice;
1195	uint8_t uCmd;
1196
1197	uDevClass = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_CLASS_DEVICE, 2);
1198	uVendor = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_VENDOR_ID, 2);
1199	uDevice = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_DEVICE_ID, 2);
1200
1201	/* If device is present */
1202	if (uVendor == 0xffff)
1203	return;
1204
1205	switch (uDevClass)
1206	{
1207	case 0x0101:
1208	/* IDE controller */
1209	ich9pciConfigWrite(pGlobals, uBus, uDevFn, 0x40, 0x8000, 2); /* enable IDE0 */
1210	ich9pciConfigWrite(pGlobals, uBus, uDevFn, 0x42, 0x8000, 2); /* enable IDE1 */
1211	goto default_map;
1212	break;
1213	case 0x0300:
1214	/* VGA controller */
1215	if (uVendor != 0x80ee)
1216	goto default_map;
1217	/* VGA: map frame buffer to default Bochs VBE address */
1218	ich9pciSetRegionAddress(pGlobals, uBus, uDevFn, 0, 0xE0000000);
1219	/*
1220	* Legacy VGA I/O ports are implicitly decoded by a VGA class device. But
1221	* only the framebuffer (i.e., a memory region) is explicitly registered via
1222	* ich9pciSetRegionAddress, so I/O decoding must be enabled manually.
1223	*/
1224	uCmd = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_COMMAND, 1);
1225	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_COMMAND,
1226	/* Enable I/O space access. */
1227	uCmd \| PCI_COMMAND_IOACCESS,
1228	1);
1229	break;
1230	case 0x0800:
1231	/* PIC */
1232	if (uVendor == 0x1014)
1233	{
1234	/* IBM */
1235	if (uDevice == 0x0046 \|\| uDevice == 0xFFFF)
1236	/* MPIC & MPIC2 */
1237	ich9pciSetRegionAddress(pGlobals, uBus, uDevFn, 0, 0x80800000 + 0x00040000);
1238	}
1239	break;
1240	case 0xff00:
1241	if ((uVendor == 0x0106b)
1242	&& (uDevice == 0x0017 \|\| uDevice == 0x0022))
1243	{
1244	/* macio bridge */
1245	ich9pciSetRegionAddress(pGlobals, uBus, uDevFn, 0, 0x80800000);
1246	}
1247	break;
1248	case 0x0604:
1249	/* PCI-to-PCI bridge. */
1250	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_PRIMARY_BUS, uBus, 1);
1251
1252	AssertMsg(pGlobals->uBus < 255, ("Too many bridges on the bus\n"));
1253	pGlobals->uBus++;
1254	ich9pciBiosInitBridge(pGlobals, uBus, uDevFn, cBridgeDepth, paBridgePositions);
1255	break;
1256	default:
1257	default_map:
1258	{
1259	/* default memory mappings */
1260	/*
1261	* We ignore ROM region here.
1262	*/
1263	for (int iRegion = 0; iRegion < (PCI_NUM_REGIONS-1); iRegion++)
1264	{
1265	uint32_t u32Address = ich9pciGetRegionReg(iRegion);
1266
1267	/* Calculate size. */
1268	uint8_t u8ResourceType = ich9pciConfigRead(pGlobals, uBus, uDevFn, u32Address, 1);
1269	ich9pciConfigWrite(pGlobals, uBus, uDevFn, u32Address, UINT32_C(0xffffffff), 4);
1270	uint32_t u32Size = ich9pciConfigRead(pGlobals, uBus, uDevFn, u32Address, 4);
1271	/* Clear resource information depending on resource type. */
1272	if ((u8ResourceType & PCI_COMMAND_IOACCESS) == PCI_COMMAND_IOACCESS) /* I/O */
1273	u32Size &= ~(0x01);
1274	else /* MMIO */
1275	u32Size &= ~(0x0f);
1276
1277	bool fIsPio = ((u8ResourceType & PCI_COMMAND_IOACCESS) == PCI_COMMAND_IOACCESS);
1278	/*
1279	* Invert all bits and add 1 to get size of the region.
1280	* (From PCI implementation note)
1281	*/
1282	if (fIsPio && (u32Size & UINT32_C(0xffff0000)) == 0)
1283	u32Size = (~(u32Size \| UINT32_C(0xffff0000))) + 1;
1284	else
1285	u32Size = (~u32Size) + 1;
1286
1287	Log(("%s: Size of region %u for device %d on bus %d is %u\n", __FUNCTION__, iRegion, uDevFn, uBus, u32Size));
1288
1289	if (u32Size)
1290	{
1291	paddr = fIsPio ? &pGlobals->uPciBiosIo : &pGlobals->uPciBiosMmio;
1292	paddr = (paddr + u32Size - 1) & ~(u32Size - 1);
1293	Log(("%s: Start address of %s region %u is %#x\n", __FUNCTION__, (fIsPio ? "I/O" : "MMIO"), iRegion, *paddr));
1294	ich9pciSetRegionAddress(pGlobals, uBus, uDevFn, iRegion, *paddr);
1295	*paddr += u32Size;
1296	Log(("%s: New address is %#x\n", __FUNCTION__, *paddr));
1297	}
1298	}
1299	break;
1300	}
1301	}
1302
1303	/* map the interrupt */
1304	uint32_t uPin = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_INTERRUPT_PIN, 1);
1305	if (uPin != 0)
1306	{
1307	uint8_t uBridgeDevFn = uDevFn;
1308	uPin--;
1309
1310	/* We need to go up to the host bus to see which irq this device will assert there. */
1311	while (cBridgeDepth != 0)
1312	{
1313	/* Get the pin the device would assert on the bridge. */
1314	uPin = ((uBridgeDevFn >> 3) + uPin) & 3;
1315	uBridgeDevFn = paBridgePositions[cBridgeDepth];
1316	cBridgeDepth--;
1317	}
1318	#if 0
1319	uPin = pci_slot_get_pirq(uDevFn, pin);
1320	pic_irq = pci_irqs[pin];
1321	ich9pciConfigWrite(pGlobals, uBus, uDevFn, PCI_INTERRUPT_LINE, pic_irq);
1322	#endif
1323	}
1324	}
1325
1326	static const uint8_t auPciIrqs[4] = { 11, 9, 11, 9 };
1327
1328	static DECLCALLBACK(int) ich9pciFakePCIBIOS(PPDMDEVINS pDevIns)
1329	{
1330	unsigned i;
1331	uint8_t elcr[2] = {0, 0};
1332	PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
1333	PVM pVM = PDMDevHlpGetVM(pDevIns);
1334	Assert(pVM);
1335
1336	/*
1337	* Set the start addresses.
1338	*/
1339	pGlobals->uPciBiosIo = 0xd000;
1340	pGlobals->uPciBiosMmio = UINT32_C(0xf0000000);
1341	pGlobals->uBus = 0;
1342
1343	/*
1344	* Activate IRQ mappings.
1345	*/
1346	for (i = 0; i < 4; i++)
1347	{
1348	uint8_t irq = auPciIrqs[i];
1349	/* Set to trigger level. */
1350	elcr[irq >> 3] \|= (1 << (irq & 7));
1351	}
1352
1353	/* Tell to the PIC. */
1354	VBOXSTRICTRC rcStrict = IOMIOPortWrite(pVM, 0x4d0, elcr[0], sizeof(uint8_t));
1355	if (rcStrict == VINF_SUCCESS)
1356	rcStrict = IOMIOPortWrite(pVM, 0x4d1, elcr[1], sizeof(uint8_t));
1357	if (rcStrict != VINF_SUCCESS)
1358	{
1359	AssertMsgFailed(("Writing to PIC failed! rcStrict=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
1360	return RT_SUCCESS(rcStrict) ? VERR_INTERNAL_ERROR : VBOXSTRICTRC_VAL(rcStrict);
1361	}
1362
1363	/*
1364	* Init the devices.
1365	*/
1366	for (i = 0; i < 256; i++)
1367	{
1368	uint8_t aBridgePositions[256];
1369
1370	memset(aBridgePositions, 0, sizeof(aBridgePositions));
1371	Log2(("PCI: Initializing device %d (%#x)\n",
1372	i, 0x80000000 \| (i << 8)));
1373	ich9pciBiosInitDevice(pGlobals, 0, i, 0, aBridgePositions);
1374	}
1375
1376	return VINF_SUCCESS;
1377	}
1378
1379	static DECLCALLBACK(uint32_t) ich9pciConfigRead(PCIDevice *aDev, uint32_t u32Address, unsigned len)
1380	{
1381	AssertMsgReturn(u32Address + len <= 256, ("Read after end of PCI config space\n"),
1382	0);
1383	switch (len)
1384	{
1385	case 1:
1386	return aDev->config[u32Address];
1387	case 2:
1388	return RT_LE2H_U16((uint16_t )(aDev->config + u32Address));
1389	default:
1390	case 4:
1391	return RT_LE2H_U32((uint32_t )(aDev->config + u32Address));
1392	}
1393	}
1394
1395
1396	/**
1397	* See paragraph 7.5 of PCI Express specification (p. 349) for definition of
1398	* registers and their writability policy.
1399	*/
1400	static DECLCALLBACK(void) ich9pciConfigWrite(PCIDevice *aDev, uint32_t u32Address,
1401	uint32_t val, unsigned len)
1402	{
1403	/* Fast case - update one of BARs or ROM address, 'while' only for 'break' */
1404	while ( len == 4
1405	&& ( ( u32Address >= VBOX_PCI_BASE_ADDRESS_0
1406	&& u32Address < VBOX_PCI_BASE_ADDRESS_0 + 6 * 4)
1407	\|\| ( u32Address >= VBOX_PCI_ROM_ADDRESS
1408	&& u32Address < VBOX_PCI_ROM_ADDRESS+4)
1409	)
1410	)
1411	{
1412	PCIIORegion *pRegion;
1413	int reg, regionSize;
1414
1415	reg = (u32Address >= VBOX_PCI_ROM_ADDRESS) ? PCI_ROM_SLOT : (u32Address - VBOX_PCI_BASE_ADDRESS_0) >> 2;
1416	pRegion = &aDev->Int.s.aIORegions[reg];
1417	regionSize = pRegion->size;
1418	if (regionSize == 0)
1419	break;
1420	/* compute the stored value */
1421	if (reg == PCI_ROM_SLOT) {
1422	/* keep ROM enable bit */
1423	val &= (~(regionSize - 1)) \| 1;
1424	} else {
1425	val &= ~(regionSize - 1);
1426	val \|= pRegion->type;
1427	}
1428	(uint32_t )(aDev->config + u32Address) = RT_H2LE_U32(val);
1429	ich9pciUpdateMappings(aDev);
1430	return;
1431	}
1432
1433	uint32_t addr = u32Address;
1434	bool fUpdateMappings = false;
1435	for (uint32_t i = 0; i < len; i++)
1436	{
1437	bool fWritable = false;
1438	switch (PCIDevGetHeaderType(aDev))
1439	{
1440	case 0x00: /* normal device */
1441	case 0x80: /* multi-function device */
1442	switch (addr)
1443	{
1444	/* Read-only registers, see */
1445	case VBOX_PCI_VENDOR_ID: case VBOX_PCI_VENDOR_ID+1:
1446	case VBOX_PCI_DEVICE_ID: case VBOX_PCI_DEVICE_ID+1:
1447	case VBOX_PCI_REVISION_ID:
1448	case VBOX_PCI_CLASS_PROG:
1449	case VBOX_PCI_CLASS_SUB:
1450	case VBOX_PCI_CLASS_BASE:
1451	case VBOX_PCI_HEADER_TYPE:
1452	case VBOX_PCI_BASE_ADDRESS_0: case VBOX_PCI_BASE_ADDRESS_0+1: case VBOX_PCI_BASE_ADDRESS_0+2: case VBOX_PCI_BASE_ADDRESS_0+3:
1453	case VBOX_PCI_BASE_ADDRESS_1: case VBOX_PCI_BASE_ADDRESS_1+1: case VBOX_PCI_BASE_ADDRESS_1+2: case VBOX_PCI_BASE_ADDRESS_1+3:
1454	case VBOX_PCI_BASE_ADDRESS_2: case VBOX_PCI_BASE_ADDRESS_2+1: case VBOX_PCI_BASE_ADDRESS_2+2: case VBOX_PCI_BASE_ADDRESS_2+3:
1455	case VBOX_PCI_BASE_ADDRESS_3: case VBOX_PCI_BASE_ADDRESS_3+1: case VBOX_PCI_BASE_ADDRESS_3+2: case VBOX_PCI_BASE_ADDRESS_3+3:
1456	case VBOX_PCI_BASE_ADDRESS_4: case VBOX_PCI_BASE_ADDRESS_4+1: case VBOX_PCI_BASE_ADDRESS_4+2: case VBOX_PCI_BASE_ADDRESS_4+3:
1457	case VBOX_PCI_BASE_ADDRESS_5: case VBOX_PCI_BASE_ADDRESS_5+1: case VBOX_PCI_BASE_ADDRESS_5+2: case VBOX_PCI_BASE_ADDRESS_5+3:
1458	case VBOX_PCI_SUBSYSTEM_VENDOR_ID: case VBOX_PCI_SUBSYSTEM_VENDOR_ID+1:
1459	case VBOX_PCI_SUBSYSTEM_ID: case VBOX_PCI_SUBSYSTEM_ID+1:
1460	case VBOX_PCI_ROM_ADDRESS: case VBOX_PCI_ROM_ADDRESS+1: case VBOX_PCI_ROM_ADDRESS+2: case VBOX_PCI_ROM_ADDRESS+3:
1461	case VBOX_PCI_CAPABILITY_LIST:
1462	case VBOX_PCI_INTERRUPT_PIN:
1463	fWritable = false;
1464	break;
1465	/* Others can be written */
1466	default:
1467	fWritable = true;
1468	break;
1469	}
1470	break;
1471	default:
1472	case 0x01: /* bridge */
1473	switch (addr)
1474	{
1475	/* Read-only registers */
1476	case VBOX_PCI_VENDOR_ID: case VBOX_PCI_VENDOR_ID+1:
1477	case VBOX_PCI_DEVICE_ID: case VBOX_PCI_DEVICE_ID+1:
1478	case VBOX_PCI_REVISION_ID:
1479	case VBOX_PCI_CLASS_PROG:
1480	case VBOX_PCI_CLASS_SUB:
1481	case VBOX_PCI_CLASS_BASE:
1482	case VBOX_PCI_HEADER_TYPE:
1483	case VBOX_PCI_ROM_ADDRESS_BR: case VBOX_PCI_ROM_ADDRESS_BR+1: case VBOX_PCI_ROM_ADDRESS_BR+2: case VBOX_PCI_ROM_ADDRESS_BR+3:
1484	case VBOX_PCI_INTERRUPT_PIN:
1485	fWritable = false;
1486	break;
1487	default:
1488	fWritable = true;
1489	break;
1490	}
1491	break;
1492	}
1493
1494	switch (addr)
1495	{
1496	case VBOX_PCI_COMMAND: /* Command register, bits 0-7. */
1497	fUpdateMappings = true;
1498	aDev->config[addr] = val;
1499	break;
1500	case VBOX_PCI_COMMAND+1: /* Command register, bits 8-15. */
1501	/* don't change reserved bits (11-15) */
1502	val &= UINT32_C(~0xf8);
1503	fUpdateMappings = true;
1504	aDev->config[addr] = val;
1505	break;
1506	case VBOX_PCI_STATUS: /* Status register, bits 0-7. */
1507	/* don't change read-only bits => actually all lower bits are read-only */
1508	val &= UINT32_C(~0xff);
1509	/* status register, low part: clear bits by writing a '1' to the corresponding bit */
1510	aDev->config[addr] &= ~val;
1511	break;
1512	case VBOX_PCI_STATUS+1: /* Status register, bits 8-15. */
1513	/* don't change read-only bits */
1514	val &= UINT32_C(~0x06);
1515	/* status register, high part: clear bits by writing a '1' to the corresponding bit */
1516	aDev->config[addr] &= ~val;
1517	break;
1518	default:
1519	if (fWritable)
1520	aDev->config[addr] = val;
1521	}
1522	addr++;
1523	val >>= 8;
1524	}
1525
1526	if (fUpdateMappings)
1527	/* if the command register is modified, we must modify the mappings */
1528	ich9pciUpdateMappings(aDev);
1529	}
1530
1531	/* Slot/functions assignment per table at p. 12 of ICH9 family spec update */
1532	static const struct {
1533	const char* pszName;
1534	int32_t iSlot;
1535	int32_t iFunction;
1536	} PciSlotAssignments[] = {
1537	{
1538	"piix3ide", 1, 1 // do we really need it?
1539	},
1540	{
1541	"lan", 25, 0 /* LAN controller */
1542	},
1543	{
1544	"hda", 27, 0 /* High Definition Audio */
1545	},
1546	{
1547	"i82801", 30, 0 /* Host Controller */
1548	},
1549	{
1550	"lpc", 31, 0 /* Low Pin Count bus */
1551	},
1552	{
1553	"ahci", 31, 2 /* SATA controller */
1554	},
1555	{
1556	"smbus", 31, 3 /* System Management Bus */
1557	},
1558	{
1559	"thermal", 31, 6 /* Thermal controller */
1560	},
1561	};
1562
1563	static int assignPosition(PPCIBUS pBus, PPCIDEVICE pPciDev, const char *pszName)
1564	{
1565	/* Hardcoded slots/functions, per chipset spec */
1566	for (size_t i = 0; i < RT_ELEMENTS(PciSlotAssignments); i++)
1567	{
1568	if (!strcmp(pszName, PciSlotAssignments[i].pszName))
1569	{
1570	pPciDev->Int.s.fRequestedDevFn = true;
1571	return (PciSlotAssignments[i].iSlot << 3) + PciSlotAssignments[i].iFunction;
1572	}
1573	}
1574
1575	/* Otherwise when assigning a slot, we need to make sure all its functions are available */
1576	for (int iPos = 0; iPos < (int)RT_ELEMENTS(pBus->apDevices); iPos += 8)
1577	if ( !pBus->apDevices[iPos]
1578	&& !pBus->apDevices[iPos + 1]
1579	&& !pBus->apDevices[iPos + 2]
1580	&& !pBus->apDevices[iPos + 3]
1581	&& !pBus->apDevices[iPos + 4]
1582	&& !pBus->apDevices[iPos + 5]
1583	&& !pBus->apDevices[iPos + 6]
1584	&& !pBus->apDevices[iPos + 7])
1585	{
1586	pPciDev->Int.s.fRequestedDevFn = false;
1587	return iPos;
1588	}
1589
1590	return -1;
1591	}
1592
1593	static bool hasHardAssignedDevsInSlot(PPCIBUS pBus, int iSlot)
1594	{
1595	PCIDevice** aSlot = &pBus->apDevices[iSlot << 3];
1596
1597	return (aSlot[0] && aSlot[0]->Int.s.fRequestedDevFn)
1598	\|\| (aSlot[1] && aSlot[1]->Int.s.fRequestedDevFn)
1599	\|\| (aSlot[2] && aSlot[2]->Int.s.fRequestedDevFn)
1600	\|\| (aSlot[3] && aSlot[3]->Int.s.fRequestedDevFn)
1601	\|\| (aSlot[4] && aSlot[4]->Int.s.fRequestedDevFn)
1602	\|\| (aSlot[5] && aSlot[5]->Int.s.fRequestedDevFn)
1603	\|\| (aSlot[6] && aSlot[6]->Int.s.fRequestedDevFn)
1604	\|\| (aSlot[7] && aSlot[7]->Int.s.fRequestedDevFn)
1605	;
1606	}
1607
1608	static int ich9pciRegisterInternal(PPCIBUS pBus, int iDev, PPCIDEVICE pPciDev, const char *pszName)
1609	{
1610	/*
1611	* Find device position
1612	*/
1613	if (iDev < 0)
1614	{
1615	iDev = assignPosition(pBus, pPciDev, pszName);
1616	if (iDev < 0)
1617	{
1618	AssertMsgFailed(("Couldn't find free spot!\n"));
1619	return VERR_PDM_TOO_PCI_MANY_DEVICES;
1620	}
1621	}
1622
1623	/*
1624	* Check if we can really take this slot, possibly by relocating
1625	* its current habitant, if it wasn't hard assigned too.
1626	*/
1627	if (pPciDev->Int.s.fRequestedDevFn &&
1628	pBus->apDevices[iDev] &&
1629	pBus->apDevices[iDev]->Int.s.fRequestedDevFn)
1630	{
1631	/*
1632	* Smth like hasHardAssignedDevsInSlot(pBus, iDev >> 3) shall be use to make
1633	* it compatible with DevPCI.cpp version, but this way we cannot assign
1634	* in accordance with the chipset spec.
1635	*/
1636	AssertReleaseMsgFailed(("Configuration error:'%s' and '%s' are both configured as device %d\n",
1637	pszName, pBus->apDevices[iDev]->name, iDev));
1638	return VERR_INTERNAL_ERROR;
1639	}
1640
1641	if (pBus->apDevices[iDev])
1642	{
1643	/* if we got here, we shall (and usually can) relocate the device */
1644	int iRelDev = assignPosition(pBus, pBus->apDevices[iDev], pBus->apDevices[iDev]->name);
1645	if (iRelDev < 0 \|\| iRelDev == iDev)
1646	{
1647	AssertMsgFailed(("Couldn't find free spot!\n"));
1648	return VERR_PDM_TOO_PCI_MANY_DEVICES;
1649	}
1650	/* Copy device function by function to its new position */
1651	for (int i = 0; i < 8; i++)
1652	{
1653	if (!pBus->apDevices[iDev + i])
1654	continue;
1655	Log(("PCI: relocating '%s' from slot %#x to %#x\n", pBus->apDevices[iDev + i]->name, iDev + i, iRelDev + i));
1656	pBus->apDevices[iRelDev + i] = pBus->apDevices[iDev + i];
1657	pBus->apDevices[iRelDev + i]->devfn = iRelDev + i;
1658	pBus->apDevices[iDev + i] = NULL;
1659	}
1660	}
1661
1662	/*
1663	* Fill in device information.
1664	*/
1665	pPciDev->devfn = iDev;
1666	pPciDev->name = pszName;
1667	pPciDev->Int.s.pBusR3 = pBus;
1668	pPciDev->Int.s.pBusR0 = MMHyperR3ToR0(PDMDevHlpGetVM(pBus->CTX_SUFF(pDevIns)), pBus);
1669	pPciDev->Int.s.pBusRC = MMHyperR3ToRC(PDMDevHlpGetVM(pBus->CTX_SUFF(pDevIns)), pBus);
1670	pPciDev->Int.s.pfnConfigRead = ich9pciConfigRead;
1671	pPciDev->Int.s.pfnConfigWrite = ich9pciConfigWrite;
1672	pBus->apDevices[iDev] = pPciDev;
1673	if (pPciDev->Int.s.fPciToPciBridge)
1674	{
1675	AssertMsg(pBus->cBridges < RT_ELEMENTS(pBus->apDevices), ("Number of bridges exceeds the number of possible devices on the bus\n"));
1676	AssertMsg(pPciDev->Int.s.pfnBridgeConfigRead && pPciDev->Int.s.pfnBridgeConfigWrite,
1677	("device is a bridge but does not implement read/write functions\n"));
1678	pBus->papBridgesR3[pBus->cBridges] = pPciDev;
1679	pBus->cBridges++;
1680	}
1681
1682	Log(("PCI: Registered device %d function %d (%#x) '%s'.\n",
1683	iDev >> 3, iDev & 7, 0x80000000 \| (iDev << 8), pszName));
1684
1685	return VINF_SUCCESS;
1686	}
1687
1688
1689	/**
1690	* Info handler, device version.
1691	*
1692	* @param pDevIns Device instance which registered the info.
1693	* @param pHlp Callback functions for doing output.
1694	* @param pszArgs Argument string. Optional and specific to the handler.
1695	*/
1696	static DECLCALLBACK(void) ich9pciInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
1697	{
1698	PPCIBUS pBus = DEVINS_2_PCIBUS(pDevIns);
1699	uint32_t iBus = 0, iDev;
1700
1701
1702	for (iDev = 0; iDev < RT_ELEMENTS(pBus->apDevices); iDev++)
1703	{
1704	PPCIDEVICE pPciDev = pBus->apDevices[iDev];
1705	if (pPciDev != NULL)
1706	pHlp->pfnPrintf(pHlp, "%02x:%02x:%02x %s: %x-%x\n",
1707	iBus, (iDev >> 3) & 0xff, iDev & 0x7,
1708	pPciDev->name,
1709	PCIDevGetVendorId(pPciDev), PCIDevGetDeviceId(pPciDev)
1710	);
1711	}
1712	}
1713
1714
1715	static DECLCALLBACK(int) ich9pciConstruct(PPDMDEVINS pDevIns,
1716	int iInstance,
1717	PCFGMNODE pCfg)
1718	{
1719	int rc;
1720	Assert(iInstance == 0);
1721
1722	/*
1723	* Validate and read configuration.
1724	*/
1725	if (!CFGMR3AreValuesValid(pCfg, "IOAPIC\0" "GCEnabled\0" "R0Enabled\0"))
1726	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
1727
1728	/* query whether we got an IOAPIC */
1729	bool fUseIoApic;
1730	rc = CFGMR3QueryBoolDef(pCfg, "IOAPIC", &fUseIoApic, false);
1731	if (RT_FAILURE(rc))
1732	return PDMDEV_SET_ERROR(pDevIns, rc,
1733	N_("Configuration error: Failed to query boolean value \"IOAPIC\""));
1734
1735	/* check if RC code is enabled. */
1736	bool fGCEnabled;
1737	rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
1738	if (RT_FAILURE(rc))
1739	return PDMDEV_SET_ERROR(pDevIns, rc,
1740	N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
1741
1742	/* check if R0 code is enabled. */
1743	bool fR0Enabled;
1744	rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
1745	if (RT_FAILURE(rc))
1746	return PDMDEV_SET_ERROR(pDevIns, rc,
1747	N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
1748	Log(("PCI: fUseIoApic=%RTbool fGCEnabled=%RTbool fR0Enabled=%RTbool\n", fUseIoApic, fGCEnabled, fR0Enabled));
1749
1750	/*
1751	* Init data.
1752	*/
1753	PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
1754	PPCIBUS pBus = &pGlobals->aPciBus;
1755	/* Zero out everything */
1756	memset(pGlobals, 0, sizeof(*pGlobals));
1757	/* And fill values */
1758	if (!fUseIoApic)
1759	return PDMDEV_SET_ERROR(pDevIns, rc,
1760	N_("Must use IO-APIC with ICH9 chipset"));
1761	pGlobals->pDevInsR3 = pDevIns;
1762	pGlobals->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
1763	pGlobals->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
1764
1765	pGlobals->aPciBus.pDevInsR3 = pDevIns;
1766	pGlobals->aPciBus.pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
1767	pGlobals->aPciBus.pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
1768	pGlobals->aPciBus.papBridgesR3 = (PPCIDEVICE )PDMDevHlpMMHeapAllocZ(pDevIns, sizeof(PPCIDEVICE) RT_ELEMENTS(pGlobals->aPciBus.apDevices));
1769
1770	/*
1771	* Register bus
1772	*/
1773	PDMPCIBUSREG PciBusReg;
1774	PciBusReg.u32Version = PDM_PCIBUSREG_VERSION;
1775	PciBusReg.pfnRegisterR3 = ich9pciRegister;
1776	PciBusReg.pfnIORegionRegisterR3 = ich9pciIORegionRegister;
1777	PciBusReg.pfnSetConfigCallbacksR3 = ich9pciSetConfigCallbacks;
1778	PciBusReg.pfnSetIrqR3 = ich9pciSetIrq;
1779	PciBusReg.pfnSaveExecR3 = pciGenericSaveExec;
1780	PciBusReg.pfnLoadExecR3 = pciGenericLoadExec;
1781	PciBusReg.pfnFakePCIBIOSR3 = ich9pciFakePCIBIOS;
1782	PciBusReg.pszSetIrqRC = fGCEnabled ? "ich9pciSetIrq" : NULL;
1783	PciBusReg.pszSetIrqR0 = fR0Enabled ? "ich9pciSetIrq" : NULL;
1784	rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBus->pPciHlpR3);
1785	if (RT_FAILURE(rc))
1786	return PDMDEV_SET_ERROR(pDevIns, rc,
1787	N_("Failed to register ourselves as a PCI Bus"));
1788	if (pBus->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
1789	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
1790	N_("PCI helper version mismatch; got %#x expected %#x"),
1791	pBus->pPciHlpR3->u32Version, PDM_PCIHLPR3_VERSION);
1792
1793	pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
1794	pBus->pPciHlpR0 = pBus->pPciHlpR3->pfnGetR0Helpers(pDevIns);
1795
1796	/*
1797	* Fill in PCI configs and add them to the bus.
1798	*/
1799
1800	/**
1801	* We emulate 82801IB ICH9 IO chip used in Q35,
1802	* see http://ark.intel.com/Product.aspx?id=31892
1803	*
1804	* Stepping S-Spec Top Marking
1805	*
1806	* A2 SLA9M NH82801IB
1807	*/
1808	PCIDevSetVendorId( &pBus->aPciDev, 0x8086); /* Intel */
1809	PCIDevSetDeviceId( &pBus->aPciDev, 0x244e); /* Desktop */
1810	PCIDevSetRevisionId(&pBus->aPciDev, 0x92); /* rev. A2 */
1811	PCIDevSetClassSub( &pBus->aPciDev, 0x00); /* Host/PCI bridge */
1812	PCIDevSetClassBase( &pBus->aPciDev, 0x06); /* bridge */
1813	PCIDevSetHeaderType(&pBus->aPciDev, 0x00); /* normal device */
1814
1815	pBus->aPciDev.pDevIns = pDevIns;
1816	/* We register Host<->PCI controller on the bus */
1817	ich9pciRegisterInternal(pBus, -1, &pBus->aPciDev, "i82801");
1818
1819	/*
1820	* Register I/O ports and save state.
1821	*/
1822	rc = PDMDevHlpIOPortRegister(pDevIns, 0x0cf8, 1, NULL, ich9pciIOPortAddressWrite, ich9pciIOPortAddressRead, NULL, NULL, "ICH9 (PCI)");
1823	if (RT_FAILURE(rc))
1824	return rc;
1825	rc = PDMDevHlpIOPortRegister(pDevIns, 0x0cfc, 4, NULL, ich9pciIOPortDataWrite, ich9pciIOPortDataRead, NULL, NULL, "ICH9 (PCI)");
1826	if (RT_FAILURE(rc))
1827	return rc;
1828	if (fGCEnabled)
1829	{
1830	rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x0cf8, 1, NIL_RTGCPTR, "ich9pciIOPortAddressWrite", "ich9pciIOPortAddressRead", NULL, NULL, "ICH9 (PCI)");
1831	if (RT_FAILURE(rc))
1832	return rc;
1833	rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x0cfc, 4, NIL_RTGCPTR, "ich9pciIOPortDataWrite", "ich9pciIOPortDataRead", NULL, NULL, "ICH9 (PCI)");
1834	if (RT_FAILURE(rc))
1835	return rc;
1836	}
1837	if (fR0Enabled)
1838	{
1839	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x0cf8, 1, NIL_RTR0PTR, "ich9pciIOPortAddressWrite", "ich9pciIOPortAddressRead", NULL, NULL, "ICH9 (PCI)");
1840	if (RT_FAILURE(rc))
1841	return rc;
1842	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x0cfc, 4, NIL_RTR0PTR, "ich9pciIOPortDataWrite", "ich9pciIOPortDataRead", NULL, NULL, "ICH9 (PCI)");
1843	if (RT_FAILURE(rc))
1844	return rc;
1845	}
1846
1847
1848	/** @todo: other chipset devices shall be registered too */
1849	/** @todo: what to with bridges? */
1850
1851	PDMDevHlpDBGFInfoRegister(pDevIns, "pci", "Display PCI bus status. (no arguments)", ich9pciInfo);
1852
1853	return VINF_SUCCESS;
1854	}
1855
1856	/**
1857	* @copydoc FNPDMDEVRELOCATE
1858	*/
1859	static DECLCALLBACK(void) ich9pciRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
1860	{
1861	PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
1862	PPCIBUS pBus = &pGlobals->aPciBus;
1863	pGlobals->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
1864
1865	pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
1866	pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
1867
1868	/* Relocate RC pointers for the attached pci devices. */
1869	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
1870	{
1871	if (pBus->apDevices[i])
1872	pBus->apDevices[i]->Int.s.pBusRC += offDelta;
1873	}
1874
1875	}
1876
1877	/**
1878	* @interface_method_impl{PDMDEVREG,pfnConstruct}
1879	*/
1880	static DECLCALLBACK(int) ich9pcibridgeConstruct(PPDMDEVINS pDevIns,
1881	int iInstance,
1882	PCFGMNODE pCfg)
1883	{
1884	int rc;
1885
1886	/*
1887	* Validate and read configuration.
1888	*/
1889	if (!CFGMR3AreValuesValid(pCfg, "GCEnabled\0" "R0Enabled\0"))
1890	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
1891
1892	/* check if RC code is enabled. */
1893	bool fGCEnabled;
1894	rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
1895	if (RT_FAILURE(rc))
1896	return PDMDEV_SET_ERROR(pDevIns, rc,
1897	N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
1898
1899	/* check if R0 code is enabled. */
1900	bool fR0Enabled;
1901	rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
1902	if (RT_FAILURE(rc))
1903	return PDMDEV_SET_ERROR(pDevIns, rc,
1904	N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
1905	Log(("PCI: fGCEnabled=%RTbool fR0Enabled=%RTbool\n", fGCEnabled, fR0Enabled));
1906
1907	return VINF_SUCCESS;
1908	}
1909
1910	/**
1911	* @copydoc FNPDMDEVRESET
1912	*/
1913	static DECLCALLBACK(void) ich9pcibridgeReset(PPDMDEVINS pDevIns)
1914	{
1915	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
1916
1917	/* Reset config space to default values. */
1918	pBus->aPciDev.config[VBOX_PCI_PRIMARY_BUS] = 0;
1919	pBus->aPciDev.config[VBOX_PCI_SECONDARY_BUS] = 0;
1920	pBus->aPciDev.config[VBOX_PCI_SUBORDINATE_BUS] = 0;
1921	}
1922
1923
1924	/**
1925	* @copydoc FNPDMDEVRELOCATE
1926	*/
1927	static DECLCALLBACK(void) ich9pcibridgeRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
1928	{
1929	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
1930	pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
1931
1932	/* Relocate RC pointers for the attached pci devices. */
1933	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
1934	{
1935	if (pBus->apDevices[i])
1936	pBus->apDevices[i]->Int.s.pBusRC += offDelta;
1937	}
1938
1939	}
1940
1941	/**
1942	* The PCI bus device registration structure.
1943	*/
1944	const PDMDEVREG g_DevicePciIch9 =
1945	{
1946	/* u32Version */
1947	PDM_DEVREG_VERSION,
1948	/* szName */
1949	"ich9pci",
1950	/* szRCMod */
1951	"VBoxDDGC.gc",
1952	/* szR0Mod */
1953	"VBoxDDR0.r0",
1954	/* pszDescription */
1955	"ICH9 PCI bridge",
1956	/* fFlags */
1957	PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
1958	/* fClass */
1959	PDM_DEVREG_CLASS_BUS_PCI \| PDM_DEVREG_CLASS_BUS_ISA,
1960	/* cMaxInstances */
1961	1,
1962	/* cbInstance */
1963	sizeof(PCIGLOBALS),
1964	/* pfnConstruct */
1965	ich9pciConstruct,
1966	/* pfnDestruct */
1967	NULL,
1968	/* pfnRelocate */
1969	ich9pciRelocate,
1970	/* pfnIOCtl */
1971	NULL,
1972	/* pfnPowerOn */
1973	NULL,
1974	/* pfnReset */
1975	NULL,
1976	/* pfnSuspend */
1977	NULL,
1978	/* pfnResume */
1979	NULL,
1980	/* pfnAttach */
1981	NULL,
1982	/* pfnDetach */
1983	NULL,
1984	/* pfnQueryInterface */
1985	NULL,
1986	/* pfnInitComplete */
1987	NULL,
1988	/* pfnPowerOff */
1989	NULL,
1990	/* pfnSoftReset */
1991	NULL,
1992	/* u32VersionEnd */
1993	PDM_DEVREG_VERSION
1994	};
1995
1996	/**
1997	* The device registration structure
1998	* for the PCI-to-PCI bridge.
1999	*/
2000	const PDMDEVREG g_DevicePciIch9Bridge =
2001	{
2002	/* u32Version */
2003	PDM_DEVREG_VERSION,
2004	/* szName */
2005	"ich9pcibridge",
2006	/* szRCMod */
2007	"VBoxDDGC.gc",
2008	/* szR0Mod */
2009	"VBoxDDR0.r0",
2010	/* pszDescription */
2011	"ICH9 PCI to PCI bridge",
2012	/* fFlags */
2013	PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
2014	/* fClass */
2015	PDM_DEVREG_CLASS_BUS_PCI,
2016	/* cMaxInstances */
2017	~0,
2018	/* cbInstance */
2019	sizeof(PCIBUS),
2020	/* pfnConstruct */
2021	ich9pcibridgeConstruct,
2022	/* pfnDestruct */
2023	NULL,
2024	/* pfnRelocate */
2025	ich9pcibridgeRelocate,
2026	/* pfnIOCtl */
2027	NULL,
2028	/* pfnPowerOn */
2029	NULL,
2030	/* pfnReset */
2031	ich9pcibridgeReset,
2032	/* pfnSuspend */
2033	NULL,
2034	/* pfnResume */
2035	NULL,
2036	/* pfnAttach */
2037	NULL,
2038	/* pfnDetach */
2039	NULL,
2040	/* pfnQueryInterface */
2041	NULL,
2042	/* pfnInitComplete */
2043	NULL,
2044	/* pfnPowerOff */
2045	NULL,
2046	/* pfnSoftReset */
2047	NULL,
2048	/* u32VersionEnd */
2049	PDM_DEVREG_VERSION
2050	};
2051
2052	#endif /* IN_RING3 */
2053	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */

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source: vbox/trunk/src/VBox/Devices/Bus/DevPciIch9.cpp@ 32598

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