DevPciIch9.cpp@ 32765

Last change on this file since 32765 was 32765, checked in by vboxsync, 14 years ago
PCI: Linux guests really access extended PCI space
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1	/* $Id: DevPciIch9.cpp 32765 2010-09-24 16:26:32Z vboxsync $ */
2	/** @file
3	* DevPCI - ICH9 southbridge PCI bus emulation Device.
4	*/
5
6	/*
7	* Copyright (C) 2010 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/*******************************************************************************
19	* Header Files *
20	*******************************************************************************/
21	#define LOG_GROUP LOG_GROUP_DEV_PCI
22	/* Hack to get PCIDEVICEINT declare at the right point - include "PCIInternal.h". */
23	#define PCI_INCLUDE_PRIVATE
24	#include <VBox/pci.h>
25	#include <VBox/pdmdev.h>
26	#include <iprt/asm.h>
27	#include <iprt/assert.h>
28	#include <iprt/string.h>
29
30	#include "../Builtins.h"
31
32	/**
33	* PCI Bus instance.
34	*/
35	typedef struct PCIBus
36	{
37	/** Bus number. */
38	int32_t iBus;
39	/** Number of bridges attached to the bus. */
40	uint32_t cBridges;
41
42	/** Array of PCI devices. We assume 32 slots, each with 8 functions. */
43	R3PTRTYPE(PPCIDEVICE) apDevices[256];
44	/** Array of bridges attached to the bus. */
45	R3PTRTYPE(PPCIDEVICE *) papBridgesR3;
46
47	/** R3 pointer to the device instance. */
48	PPDMDEVINSR3 pDevInsR3;
49	/** Pointer to the PCI R3 helpers. */
50	PCPDMPCIHLPR3 pPciHlpR3;
51
52	/** R0 pointer to the device instance. */
53	PPDMDEVINSR0 pDevInsR0;
54	/** Pointer to the PCI R0 helpers. */
55	PCPDMPCIHLPR0 pPciHlpR0;
56
57	/** RC pointer to the device instance. */
58	PPDMDEVINSRC pDevInsRC;
59	/** Pointer to the PCI RC helpers. */
60	PCPDMPCIHLPRC pPciHlpRC;
61
62	/** The PCI device for the PCI bridge. */
63	PCIDEVICE aPciDev;
64
65	} PCIBUS, *PPCIBUS;
66
67
68	/** @def PCI_IRQ_PINS
69	* Number of pins for interrupts (PIRQ#0...PIRQ#3)
70	*/
71	#define PCI_IRQ_PINS 4
72
73	/** @def PCI_APIC_IRQ_PINS
74	* Number of pins for interrupts if the APIC is used.
75	*/
76	#define PCI_APIC_IRQ_PINS 8
77
78	/**
79	* PCI Globals - This is the host-to-pci bridge and the root bus.
80	*/
81	typedef struct
82	{
83	/** R3 pointer to the device instance. */
84	PPDMDEVINSR3 pDevInsR3;
85	/** R0 pointer to the device instance. */
86	PPDMDEVINSR0 pDevInsR0;
87	/** RC pointer to the device instance. */
88	PPDMDEVINSRC pDevInsRC;
89
90	#if HC_ARCH_BITS == 64
91	uint32_t Alignment0;
92	#endif
93
94	/** I/O APIC irq levels */
95	volatile uint32_t uaPciApicIrqLevels[PCI_APIC_IRQ_PINS];
96
97	#if 1 /* Will be moved into the BIOS soon. */
98	/** The next I/O port address which the PCI BIOS will use. */
99	uint32_t uPciBiosIo;
100	/** The next MMIO address which the PCI BIOS will use. */
101	uint32_t uPciBiosMmio;
102	/** Actual bus number. */
103	uint8_t uBus;
104	#endif
105	/* Physical address of PCI config space MMIO region */
106	uint64_t u64PciConfigMMioAddress;
107	/* Length of PCI config space MMIO region */
108	uint64_t u64PciConfigMMioLength;
109
110
111	/** Config register. */
112	uint32_t uConfigReg;
113
114	/** PCI bus which is attached to the host-to-PCI bridge. */
115	PCIBUS aPciBus;
116
117	} PCIGLOBALS, *PPCIGLOBALS;
118
119
120	typedef struct {
121	uint8_t iBus;
122	uint8_t iDeviceFunc;
123	uint16_t iRegister;
124	} PciAddress;
125
126	/*******************************************************************************
127	* Defined Constants And Macros *
128	*******************************************************************************/
129
130	/** @def VBOX_ICH9PCI_SAVED_STATE_VERSION
131	* Saved state version of the ICH9 PCI bus device.
132	*/
133	#define VBOX_ICH9PCI_SAVED_STATE_VERSION 1
134
135	/** Converts a bus instance pointer to a device instance pointer. */
136	#define PCIBUS_2_DEVINS(pPciBus) ((pPciBus)->CTX_SUFF(pDevIns))
137	/** Converts a device instance pointer to a PCIGLOBALS pointer. */
138	#define DEVINS_2_PCIGLOBALS(pDevIns) ((PPCIGLOBALS)(PDMINS_2_DATA(pDevIns, PPCIGLOBALS)))
139	/** Converts a device instance pointer to a PCIBUS pointer. */
140	#define DEVINS_2_PCIBUS(pDevIns) ((PPCIBUS)(&PDMINS_2_DATA(pDevIns, PPCIGLOBALS)->aPciBus))
141	/** Converts a pointer to a PCI root bus instance to a PCIGLOBALS pointer.
142	*/
143	#define PCIROOTBUS_2_PCIGLOBALS(pPciBus) ( (PPCIGLOBALS)((uintptr_t)(pPciBus) - RT_OFFSETOF(PCIGLOBALS, aPciBus)) )
144
145
146	/** @def PCI_LOCK
147	* Acquires the PDM lock. This is a NOP if locking is disabled. */
148	/** @def PCI_UNLOCK
149	* Releases the PDM lock. This is a NOP if locking is disabled. */
150	#define PCI_LOCK(pDevIns, rc) \
151	do { \
152	int rc2 = DEVINS_2_PCIBUS(pDevIns)->CTX_SUFF(pPciHlp)->pfnLock((pDevIns), rc); \
153	if (rc2 != VINF_SUCCESS) \
154	return rc2; \
155	} while (0)
156	#define PCI_UNLOCK(pDevIns) \
157	DEVINS_2_PCIBUS(pDevIns)->CTX_SUFF(pPciHlp)->pfnUnlock(pDevIns)
158
159	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
160
161	RT_C_DECLS_BEGIN
162
163	PDMBOTHCBDECL(void) ich9pciSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel);
164	PDMBOTHCBDECL(void) ich9pcibridgeSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel);
165	PDMBOTHCBDECL(int) ich9pciIOPortAddressWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
166	PDMBOTHCBDECL(int) ich9pciIOPortAddressRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb);
167	PDMBOTHCBDECL(int) ich9pciIOPortDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
168	PDMBOTHCBDECL(int) ich9pciIOPortDataRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb);
169	PDMBOTHCBDECL(int) ich9pciMcfgMMIOWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb);
170	PDMBOTHCBDECL(int) ich9pciMcfgMMIORead (PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb);
171
172	RT_C_DECLS_END
173
174	/* Prototypes */
175	static void ich9pciSetIrqInternal(PPCIGLOBALS pGlobals, uint8_t uDevFn, PPCIDEVICE pPciDev, int iIrq, int iLevel);
176	#ifdef IN_RING3
177	static int ich9pciRegisterInternal(PPCIBUS pBus, int iDev, PPCIDEVICE pPciDev, const char *pszName);
178	static void ich9pciUpdateMappings(PCIDevice *d);
179	static DECLCALLBACK(uint32_t) ich9pciConfigRead(PCIDevice *aDev, uint32_t u32Address, unsigned len);
180	DECLINLINE(PPCIDEVICE) ich9pciFindBridge(PPCIBUS pBus, uint8_t iBus);
181	static void ich9pciBiosInitDevice(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint8_t cBridgeDepth, uint8_t *paBridgePositions);
182	#endif
183
184	// See 7.2.2. PCI Express Enhanced Configuration Mechanism for details of address
185	// mapping, we take n=8 approach
186	DECLINLINE(void) ich9pciPhysToPciAddr(PPCIGLOBALS pGlobals, RTGCPHYS GCPhysAddr, PciAddress* pPciAddr)
187	{
188	GCPhysAddr = GCPhysAddr - pGlobals->u64PciConfigMMioAddress;
189	pPciAddr->iBus = (GCPhysAddr >> 20) & ((1<<8) - 1);
190	pPciAddr->iDeviceFunc = (GCPhysAddr >> 15) & ((1<<(5+3)) - 1); // 5 bits - device, 3 bits - function
191	pPciAddr->iRegister = (GCPhysAddr >> 0) & ((1<<(6+4+2)) - 1); // 6 bits - register, 4 bits - extended register, 2 bits -Byte Enable
192	}
193
194	DECLINLINE(void) ich9pciStateToPciAddr(PPCIGLOBALS pGlobals, RTGCPHYS addr, PciAddress* pPciAddr)
195	{
196	pPciAddr->iBus = (pGlobals->uConfigReg >> 16) & 0xff;
197	pPciAddr->iDeviceFunc = (pGlobals->uConfigReg >> 8) & 0xff;
198	pPciAddr->iRegister = (pGlobals->uConfigReg & 0xfc) \| (addr & 3);
199	}
200
201	PDMBOTHCBDECL(void) ich9pciSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel)
202	{
203	ich9pciSetIrqInternal(PDMINS_2_DATA(pDevIns, PPCIGLOBALS), pPciDev->devfn, pPciDev, iIrq, iLevel);
204	}
205
206	PDMBOTHCBDECL(void) ich9pcibridgeSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel)
207	{
208	/*
209	* The PCI-to-PCI bridge specification defines how the interrupt pins
210	* are routed from the secondary to the primary bus (see chapter 9).
211	* iIrq gives the interrupt pin the pci device asserted.
212	* We change iIrq here according to the spec and call the SetIrq function
213	* of our parent passing the device which asserted the interrupt instead of the device of the bridge.
214	*/
215	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
216	PPCIDEVICE pPciDevBus = pPciDev;
217	int iIrqPinBridge = iIrq;
218	uint8_t uDevFnBridge = 0;
219
220	/* Walk the chain until we reach the host bus. */
221	do
222	{
223	uDevFnBridge = pBus->aPciDev.devfn;
224	iIrqPinBridge = ((pPciDevBus->devfn >> 3) + iIrqPinBridge) & 3;
225
226	/* Get the parent. */
227	pBus = pBus->aPciDev.Int.s.CTX_SUFF(pBus);
228	pPciDevBus = &pBus->aPciDev;
229	} while (pBus->iBus != 0);
230
231	AssertMsgReturnVoid(pBus->iBus == 0, ("This is not the host pci bus iBus=%d\n", pBus->iBus));
232	ich9pciSetIrqInternal(PCIROOTBUS_2_PCIGLOBALS(pBus), uDevFnBridge, pPciDev, iIrqPinBridge, iLevel);
233	}
234
235	/**
236	* Port I/O Handler for PCI address OUT operations.
237	*
238	* @returns VBox status code.
239	*
240	* @param pDevIns The device instance.
241	* @param pvUser User argument - ignored.
242	* @param uPort Port number used for the OUT operation.
243	* @param u32 The value to output.
244	* @param cb The value size in bytes.
245	*/
246	PDMBOTHCBDECL(int) ich9pciIOPortAddressWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
247	{
248	Log(("ich9pciIOPortAddressWrite: Port=%#x u32=%#x cb=%d\n", Port, u32, cb));
249	NOREF(pvUser);
250	if (cb == 4)
251	{
252	PPCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
253	PCI_LOCK(pDevIns, VINF_IOM_HC_IOPORT_WRITE);
254	pThis->uConfigReg = u32 & ~3; /* Bits 0-1 are reserved and we silently clear them */
255	PCI_UNLOCK(pDevIns);
256	}
257	return VINF_SUCCESS;
258	}
259
260	/**
261	* Port I/O Handler for PCI address IN operations.
262	*
263	* @returns VBox status code.
264	*
265	* @param pDevIns The device instance.
266	* @param pvUser User argument - ignored.
267	* @param uPort Port number used for the IN operation.
268	* @param pu32 Where to store the result.
269	* @param cb Number of bytes read.
270	*/
271	PDMBOTHCBDECL(int) ich9pciIOPortAddressRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
272	{
273	NOREF(pvUser);
274	if (cb == 4)
275	{
276	PPCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
277	PCI_LOCK(pDevIns, VINF_IOM_HC_IOPORT_READ);
278	*pu32 = pThis->uConfigReg;
279	PCI_UNLOCK(pDevIns);
280	Log(("pciIOPortAddressRead: Port=%#x cb=%d -> %#x\n", Port, cb, *pu32));
281	return VINF_SUCCESS;
282	}
283
284	Log(("ich9pciIOPortAddressRead: Port=%#x cb=%d VERR_IOM_IOPORT_UNUSED\n", Port, cb));
285
286	return VERR_IOM_IOPORT_UNUSED;
287	}
288
289	static int ich9pciDataWriteAddr(PPCIGLOBALS pGlobals, PciAddress* pAddr, uint32_t val, int len)
290	{
291
292	if (pAddr->iRegister > 0xff)
293	{
294	LogRel(("PCI: attempt to write extended register: %x (%d) <- val\n", pAddr->iRegister, len, val));
295	return 0;
296	}
297
298	if (pAddr->iBus != 0)
299	{
300	if (pGlobals->aPciBus.cBridges)
301	{
302	#ifdef IN_RING3 /** @todo do lookup in R0/RC too! */
303	PPCIDEVICE pBridgeDevice = ich9pciFindBridge(&pGlobals->aPciBus, pAddr->iBus);
304	if (pBridgeDevice)
305	{
306	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigWrite);
307	pBridgeDevice->Int.s.pfnBridgeConfigWrite(pBridgeDevice->pDevIns, pAddr->iBus, pAddr->iDeviceFunc, pAddr->iRegister, val, len);
308	}
309	#else
310	return VINF_IOM_HC_IOPORT_WRITE;
311	#endif
312	}
313	}
314	else
315	{
316	if (pGlobals->aPciBus.apDevices[pAddr->iDeviceFunc])
317	{
318	#ifdef IN_RING3
319	R3PTRTYPE(PCIDevice *) aDev = pGlobals->aPciBus.apDevices[pAddr->iDeviceFunc];
320	Log(("ich9pciConfigWrite: %s: addr=%02x val=%08x len=%d\n", aDev->name, pAddr->iRegister, val, len));
321	aDev->Int.s.pfnConfigWrite(aDev, pAddr->iRegister, val, len);
322	#else
323	return VINF_IOM_HC_IOPORT_WRITE;
324	#endif
325	}
326	}
327	return VINF_SUCCESS;
328	}
329
330	static int ich9pciDataWrite(PPCIGLOBALS pGlobals, uint32_t addr, uint32_t val, int len)
331	{
332	PciAddress aPciAddr;
333
334	Log(("ich9pciDataWrite: addr=%08x val=%08x len=%d\n", pGlobals->uConfigReg, val, len));
335
336	if (!(pGlobals->uConfigReg & (1 << 31)))
337	return VINF_SUCCESS;
338
339	if ((pGlobals->uConfigReg & 0x3) != 0)
340	return VINF_SUCCESS;
341
342	/* Compute destination device */
343	ich9pciStateToPciAddr(pGlobals, addr, &aPciAddr);
344
345	return ich9pciDataWriteAddr(pGlobals, &aPciAddr, val, len);
346	}
347
348	/**
349	* Port I/O Handler for PCI data OUT operations.
350	*
351	* @returns VBox status code.
352	*
353	* @param pDevIns The device instance.
354	* @param pvUser User argument - ignored.
355	* @param uPort Port number used for the OUT operation.
356	* @param u32 The value to output.
357	* @param cb The value size in bytes.
358	*/
359	PDMBOTHCBDECL(int) ich9pciIOPortDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
360	{
361	Log(("pciIOPortDataWrite: Port=%#x u32=%#x cb=%d\n", Port, u32, cb));
362	NOREF(pvUser);
363	int rc = VINF_SUCCESS;
364	if (!(Port % cb))
365	{
366	PCI_LOCK(pDevIns, VINF_IOM_HC_IOPORT_WRITE);
367	rc = ich9pciDataWrite(PDMINS_2_DATA(pDevIns, PPCIGLOBALS), Port, u32, cb);
368	PCI_UNLOCK(pDevIns);
369	}
370	else
371	AssertMsgFailed(("Unaligned write to port %#x u32=%#x cb=%d\n", Port, u32, cb));
372	return rc;
373	}
374
375	static int ich9pciDataReadAddr(PPCIGLOBALS pGlobals, PciAddress* pPciAddr, int len, uint32_t *pu32)
376	{
377	if (pPciAddr->iRegister > 0xff)
378	{
379	LogRel(("PCI: attempt to read extended register: %x\n", pPciAddr->iRegister));
380	*pu32 = 0;
381	return 0;
382	}
383
384
385	if (pPciAddr->iBus != 0)
386	{
387	if (pGlobals->aPciBus.cBridges)
388	{
389	#ifdef IN_RING3 /** @todo do lookup in R0/RC too! */
390	PPCIDEVICE pBridgeDevice = ich9pciFindBridge(&pGlobals->aPciBus, pPciAddr->iBus);
391	if (pBridgeDevice)
392	{
393	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigRead);
394	*pu32 = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->pDevIns, pPciAddr->iBus, pPciAddr->iDeviceFunc, pPciAddr->iRegister, len);
395	}
396	#else
397	return VINF_IOM_HC_IOPORT_READ;
398	#endif
399	}
400	}
401	else
402	{
403	if (pGlobals->aPciBus.apDevices[pPciAddr->iDeviceFunc])
404	{
405	#ifdef IN_RING3
406	R3PTRTYPE(PCIDevice *) aDev = pGlobals->aPciBus.apDevices[pPciAddr->iDeviceFunc];
407	*pu32 = aDev->Int.s.pfnConfigRead(aDev, pPciAddr->iRegister, len);
408	Log(("ich9pciConfigRead: %s: addr=%02x val=%08x len=%d\n", aDev->name, pPciAddr->iRegister, *pu32, len));
409	#else
410	return VINF_IOM_HC_IOPORT_READ;
411	#endif
412	}
413	}
414
415	return VINF_SUCCESS;
416	}
417
418
419	static int ich9pciDataRead(PPCIGLOBALS pGlobals, uint32_t addr, int len, uint32_t *pu32)
420	{
421	PciAddress aPciAddr;
422
423	*pu32 = 0xffffffff;
424
425	if (!(pGlobals->uConfigReg & (1 << 31)))
426	return VINF_SUCCESS;
427
428	if ((pGlobals->uConfigReg & 0x3) != 0)
429	return VINF_SUCCESS;
430
431	/* Compute destination device */
432	ich9pciStateToPciAddr(pGlobals, addr, &aPciAddr);
433
434	return ich9pciDataReadAddr(pGlobals, &aPciAddr, len, pu32);
435	}
436
437	/**
438	* Port I/O Handler for PCI data IN operations.
439	*
440	* @returns VBox status code.
441	*
442	* @param pDevIns The device instance.
443	* @param pvUser User argument - ignored.
444	* @param uPort Port number used for the IN operation.
445	* @param pu32 Where to store the result.
446	* @param cb Number of bytes read.
447	*/
448	PDMBOTHCBDECL(int) ich9pciIOPortDataRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
449	{
450	NOREF(pvUser);
451	if (!(Port % cb))
452	{
453	PCI_LOCK(pDevIns, VINF_IOM_HC_IOPORT_READ);
454	int rc = ich9pciDataRead(PDMINS_2_DATA(pDevIns, PPCIGLOBALS), Port, cb, pu32);
455	PCI_UNLOCK(pDevIns);
456	Log(("pciIOPortDataRead: Port=%#x cb=%#x -> %#x (%Rrc)\n", Port, cb, *pu32, rc));
457	return rc;
458	}
459	AssertMsgFailed(("Unaligned read from port %#x cb=%d\n", Port, cb));
460	return VERR_IOM_IOPORT_UNUSED;
461	}
462
463	/* Compute mapping of PCI slot and IRQ number to APIC interrupt line */
464	static inline int ich9pciSlot2ApicIrq(uint8_t uSlot, int irq_num)
465	{
466	return (irq_num + uSlot) & 7;
467	}
468
469	/* Add one more level up request on APIC input line */
470	static inline void ich9pciApicLevelUp(PPCIGLOBALS pGlobals, int irq_num)
471	{
472	ASMAtomicIncU32(&pGlobals->uaPciApicIrqLevels[irq_num]);
473	}
474
475	/* Remove one level up request on APIC input line */
476	static inline void ich9pciApicLevelDown(PPCIGLOBALS pGlobals, int irq_num)
477	{
478	ASMAtomicDecU32(&pGlobals->uaPciApicIrqLevels[irq_num]);
479	}
480
481	static void ich9pciApicSetIrq(PPCIBUS pBus, uint8_t uDevFn, PCIDevice *pPciDev, int irq_num1, int iLevel, int iForcedIrq)
482	{
483	/* This is only allowed to be called with a pointer to the root bus. */
484	AssertMsg(pBus->iBus == 0, ("iBus=%u\n", pBus->iBus));
485
486	if (iForcedIrq == -1)
487	{
488	int apic_irq, apic_level;
489	PPCIGLOBALS pGlobals = PCIROOTBUS_2_PCIGLOBALS(pBus);
490	int irq_num = ich9pciSlot2ApicIrq(uDevFn >> 3, irq_num1);
491
492	if ((iLevel & PDM_IRQ_LEVEL_HIGH) == PDM_IRQ_LEVEL_HIGH)
493	ich9pciApicLevelUp(pGlobals, irq_num);
494	else if ((iLevel & PDM_IRQ_LEVEL_HIGH) == PDM_IRQ_LEVEL_LOW)
495	ich9pciApicLevelDown(pGlobals, irq_num);
496
497	apic_irq = irq_num + 0x10;
498	apic_level = pGlobals->uaPciApicIrqLevels[irq_num] != 0;
499	Log3(("ich9pciApicSetIrq: %s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d\n",
500	R3STRING(pPciDev->name), irq_num1, iLevel, apic_irq, apic_level, irq_num));
501	pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), apic_irq, apic_level);
502
503	if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP)
504	{
505	/**
506	* we raised it few lines above, as PDM_IRQ_LEVEL_FLIP_FLOP has
507	* PDM_IRQ_LEVEL_HIGH bit set
508	*/
509	ich9pciApicLevelDown(pGlobals, irq_num);
510	pPciDev->Int.s.uIrqPinState = PDM_IRQ_LEVEL_LOW;
511	apic_level = pGlobals->uaPciApicIrqLevels[irq_num] != 0;
512	Log3(("ich9pciApicSetIrq: %s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d (flop)\n",
513	R3STRING(pPciDev->name), irq_num1, iLevel, apic_irq, apic_level, irq_num));
514	pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), apic_irq, apic_level);
515	}
516	} else {
517	Log3(("ich9pciApicSetIrq: %s: irq_num1=%d level=%d acpi_irq=%d\n",
518	R3STRING(pPciDev->name), irq_num1, iLevel, iForcedIrq));
519	pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), iForcedIrq, iLevel);
520	}
521	}
522
523	static void ich9pciSetIrqInternal(PPCIGLOBALS pGlobals, uint8_t uDevFn, PPCIDEVICE pPciDev, int iIrq, int iLevel)
524	{
525	PPCIBUS pBus = &pGlobals->aPciBus;
526	const bool fIsAcpiDevice = PCIDevGetDeviceId(pPciDev) == 0x7113;
527
528	/* Check if the state changed. */
529	if (pPciDev->Int.s.uIrqPinState != iLevel)
530	{
531	pPciDev->Int.s.uIrqPinState = (iLevel & PDM_IRQ_LEVEL_HIGH);
532
533	/* Send interrupt to I/O APIC only now. */
534	if (fIsAcpiDevice)
535	/*
536	* ACPI needs special treatment since SCI is hardwired and
537	* should not be affected by PCI IRQ routing tables at the
538	* same time SCI IRQ is shared in PCI sense hence this
539	* kludge (i.e. we fetch the hardwired value from ACPIs
540	* PCI device configuration space).
541	*/
542	ich9pciApicSetIrq(pBus, uDevFn, pPciDev, -1, iLevel, PCIDevGetInterruptLine(pPciDev));
543	else
544	ich9pciApicSetIrq(pBus, uDevFn, pPciDev, iIrq, iLevel, -1);
545	}
546	}
547
548	PDMBOTHCBDECL(int) ich9pciMcfgMMIOWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb)
549	{
550	PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
551	PciAddress aDest;
552	uint32_t u32 = 0;
553
554	ich9pciPhysToPciAddr(pGlobals, GCPhysAddr, &aDest);
555
556	PCI_LOCK(pDevIns, VINF_IOM_HC_IOPORT_WRITE);
557	switch (cb)
558	{
559	case 1:
560	u32 = (uint8_t)pv;
561	break;
562	case 2:
563	u32 = (uint16_t)pv;
564	break;
565	case 4:
566	u32 = (uint32_t)pv;
567	break;
568	default:
569	Assert(false);
570	break;
571	}
572	int rc = ich9pciDataWriteAddr(pGlobals, &aDest, u32, cb);
573	PCI_UNLOCK(pDevIns);
574
575	return rc;
576	}
577
578	PDMBOTHCBDECL(int) ich9pciMcfgMMIORead (PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb)
579	{
580	PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
581	PciAddress aDest;
582	uint32_t rv = 0;
583
584	ich9pciPhysToPciAddr(pGlobals, GCPhysAddr, &aDest);
585
586	PCI_LOCK(pDevIns, VINF_IOM_HC_IOPORT_WRITE);
587	int rc = ich9pciDataReadAddr(pGlobals, &aDest, cb, &rv);
588	if (rc == VINF_SUCCESS)
589	{
590	switch (cb)
591	{
592	case 1:
593	(uint8_t)pv = (uint8_t)rv;
594	break;
595	case 2:
596	(uint16_t)pv = (uint16_t)rv;
597	break;
598	case 4:
599	(uint32_t)pv = (uint32_t)rv;
600	break;
601	default:
602	Assert(false);
603	break;
604	}
605	}
606	PCI_UNLOCK(pDevIns);
607
608	return rc;
609	}
610
611	#ifdef IN_RING3
612
613	DECLINLINE(PPCIDEVICE) ich9pciFindBridge(PPCIBUS pBus, uint8_t iBus)
614	{
615	/* Search for a fitting bridge. */
616	for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
617	{
618	/*
619	* Examine secondary and subordinate bus number.
620	* If the target bus is in the range we pass the request on to the bridge.
621	*/
622	PPCIDEVICE pBridgeTemp = pBus->papBridgesR3[iBridge];
623	AssertMsg(pBridgeTemp && pBridgeTemp->Int.s.fPciToPciBridge,
624	("Device is not a PCI bridge but on the list of PCI bridges\n"));
625
626	if ( iBus >= pBridgeTemp->config[VBOX_PCI_SECONDARY_BUS]
627	&& iBus <= pBridgeTemp->config[VBOX_PCI_SUBORDINATE_BUS])
628	return pBridgeTemp;
629	}
630
631	/* Nothing found. */
632	return NULL;
633	}
634
635	static inline uint32_t ich9pciGetRegionReg(int iRegion)
636	{
637	return (iRegion == PCI_ROM_SLOT) ?
638	VBOX_PCI_ROM_ADDRESS : (VBOX_PCI_BASE_ADDRESS_0 + iRegion * 4);
639	}
640
641	#define INVALID_PCI_ADDRESS ~0U
642
643	static void ich9pciUpdateMappings(PCIDevice* pDev)
644	{
645	PPCIBUS pBus = pDev->Int.s.CTX_SUFF(pBus);
646	uint32_t uLast, uNew;
647
648	int iCmd = PCIDevGetCommand(pDev);
649	for (int iRegion = 0; iRegion < PCI_NUM_REGIONS; iRegion++)
650	{
651	PCIIORegion* pRegion = &pDev->Int.s.aIORegions[iRegion];
652	uint32_t uConfigReg = ich9pciGetRegionReg(iRegion);
653	int32_t iRegionSize = pRegion->size;
654	int rc;
655
656	if (iRegionSize == 0)
657	continue;
658
659	if (pRegion->type & PCI_ADDRESS_SPACE_IO)
660	{
661	/* port IO region */
662	if (iCmd & PCI_COMMAND_IOACCESS)
663	{
664	/* IO access allowed */
665	uNew = ich9pciConfigRead(pDev, uConfigReg, 4);
666	uNew &= ~(iRegionSize - 1);
667	uLast = uNew + iRegionSize - 1;
668	/* only 64K ioports on PC */
669	if (uLast <= uNew \|\| uNew == 0 \|\| uLast >= 0x10000)
670	uNew = INVALID_PCI_ADDRESS;
671	} else
672	uNew = INVALID_PCI_ADDRESS;
673	}
674	else
675	{
676	/* MMIO region */
677	if (iCmd & PCI_COMMAND_MEMACCESS)
678	{
679	uNew = ich9pciConfigRead(pDev, uConfigReg, 4);
680	/* the ROM slot has a specific enable bit */
681	if (iRegion == PCI_ROM_SLOT && !(uNew & 1))
682	uNew = INVALID_PCI_ADDRESS;
683	else
684	{
685	uNew &= ~(iRegionSize - 1);
686	uLast = uNew + iRegionSize - 1;
687	/* NOTE: we do not support wrapping */
688	/* XXX: as we cannot support really dynamic
689	mappings, we handle specific values as invalid
690	mappings. */
691	if (uLast <= uNew \|\| uNew == 0 \|\| uLast == INVALID_PCI_ADDRESS)
692	uNew = INVALID_PCI_ADDRESS;
693	}
694	} else
695	uNew = INVALID_PCI_ADDRESS;
696	}
697	/* now do the real mapping */
698	if (uNew != pRegion->addr)
699	{
700	if (pRegion->addr != INVALID_PCI_ADDRESS)
701	{
702	if (pRegion->type & PCI_ADDRESS_SPACE_IO)
703	{
704	/* Port IO */
705	int devclass;
706	/* NOTE: specific hack for IDE in PC case:
707	only one byte must be mapped. */
708	/// @todo: do we need it?
709	devclass = pDev->config[0x0a] \| (pDev->config[0x0b] << 8);
710	if (devclass == 0x0101 && iRegionSize == 4)
711	{
712	rc = PDMDevHlpIOPortDeregister(pDev->pDevIns, pRegion->addr + 2, 1);
713	AssertRC(rc);
714	}
715	else
716	{
717	rc = PDMDevHlpIOPortDeregister(pDev->pDevIns, pRegion->addr, pRegion->size);
718	AssertRC(rc);
719	}
720	}
721	else
722	{
723	RTGCPHYS GCPhysBase = pRegion->addr;
724	if (pBus->pPciHlpR3->pfnIsMMIO2Base(pBus->pDevInsR3, pDev->pDevIns, GCPhysBase))
725	{
726	/* unmap it. */
727	rc = pRegion->map_func(pDev, iRegion, NIL_RTGCPHYS, pRegion->size, (PCIADDRESSSPACE)(pRegion->type));
728	AssertRC(rc);
729	rc = PDMDevHlpMMIO2Unmap(pDev->pDevIns, iRegion, GCPhysBase);
730	}
731	else
732	rc = PDMDevHlpMMIODeregister(pDev->pDevIns, GCPhysBase, pRegion->size);
733	AssertMsgRC(rc, ("rc=%Rrc d=%s i=%d GCPhysBase=%RGp size=%#x\n", rc, pDev->name, iRegion, GCPhysBase, pRegion->size));
734	}
735	}
736	pRegion->addr = uNew;
737	if (pRegion->addr != INVALID_PCI_ADDRESS)
738	{
739	/* finally, map the region */
740	rc = pRegion->map_func(pDev, iRegion,
741	pRegion->addr, pRegion->size,
742	(PCIADDRESSSPACE)(pRegion->type));
743	AssertRC(rc);
744	}
745	}
746	}
747	}
748
749	static DECLCALLBACK(int) ich9pciRegister(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, const char *pszName, int iDev)
750	{
751	PPCIBUS pBus = DEVINS_2_PCIBUS(pDevIns);
752
753	/*
754	* Check input.
755	*/
756	if ( !pszName
757	\|\| !pPciDev
758	\|\| iDev >= (int)RT_ELEMENTS(pBus->apDevices)
759	)
760	{
761	AssertMsgFailed(("Invalid argument! pszName=%s pPciDev=%p iDev=%d\n", pszName, pPciDev, iDev));
762	return VERR_INVALID_PARAMETER;
763	}
764
765	/*
766	* Register the device.
767	*/
768	return ich9pciRegisterInternal(pBus, iDev, pPciDev, pszName);
769	}
770
771	static DECLCALLBACK(int) ich9pcibridgeRegister(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, const char *pszName, int iDev)
772	{
773	return 0;
774	}
775
776	static DECLCALLBACK(int) ich9pciIORegionRegister(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iRegion, uint32_t cbRegion, PCIADDRESSSPACE enmType, PFNPCIIOREGIONMAP pfnCallback)
777	{
778	/*
779	* Validate.
780	*/
781	AssertMsgReturn( enmType == PCI_ADDRESS_SPACE_MEM
782	\|\| enmType == PCI_ADDRESS_SPACE_IO
783	\|\| enmType == PCI_ADDRESS_SPACE_MEM_PREFETCH,
784	("Invalid enmType=%#x? Or was this a bitmask after all...\n", enmType),
785	VERR_INVALID_PARAMETER);
786	AssertMsgReturn((unsigned)iRegion < PCI_NUM_REGIONS,
787	("Invalid iRegion=%d PCI_NUM_REGIONS=%d\n", iRegion, PCI_NUM_REGIONS),
788	VERR_INVALID_PARAMETER);
789	int iLastSet = ASMBitLastSetU32(cbRegion);
790	AssertMsgReturn( iLastSet != 0
791	&& RT_BIT_32(iLastSet - 1) == cbRegion,
792	("Invalid cbRegion=%#x iLastSet=%#x (not a power of 2 or 0)\n", cbRegion, iLastSet),
793	VERR_INVALID_PARAMETER);
794
795	/*
796	* Register the I/O region.
797	*/
798	PPCIIOREGION pRegion = &pPciDev->Int.s.aIORegions[iRegion];
799	pRegion->addr = INVALID_PCI_ADDRESS;
800	pRegion->size = cbRegion;
801	pRegion->type = enmType;
802	pRegion->map_func = pfnCallback;
803
804	/* Set type in the config space. */
805	uint32_t u32Address = ich9pciGetRegionReg(iRegion);
806	uint32_t u32Value = (enmType == PCI_ADDRESS_SPACE_MEM_PREFETCH ? (1 << 3) : 0)
807	\| (enmType == PCI_ADDRESS_SPACE_IO ? 1 : 0);
808	(uint32_t )(pPciDev->config + u32Address) = RT_H2LE_U32(u32Value);
809
810	return VINF_SUCCESS;
811	}
812
813	static DECLCALLBACK(void) ich9pciSetConfigCallbacks(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PFNPCICONFIGREAD pfnRead, PPFNPCICONFIGREAD ppfnReadOld,
814	PFNPCICONFIGWRITE pfnWrite, PPFNPCICONFIGWRITE ppfnWriteOld)
815	{
816	if (ppfnReadOld)
817	*ppfnReadOld = pPciDev->Int.s.pfnConfigRead;
818	pPciDev->Int.s.pfnConfigRead = pfnRead;
819
820	if (ppfnWriteOld)
821	*ppfnWriteOld = pPciDev->Int.s.pfnConfigWrite;
822	pPciDev->Int.s.pfnConfigWrite = pfnWrite;
823	}
824
825	/**
826	* Saves a state of the PCI device.
827	*
828	* @returns VBox status code.
829	* @param pDevIns Device instance of the PCI Bus.
830	* @param pPciDev Pointer to PCI device.
831	* @param pSSM The handle to save the state to.
832	*/
833	static DECLCALLBACK(int) pciGenericSaveExec(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PSSMHANDLE pSSM)
834	{
835	return SSMR3PutMem(pSSM, &pPciDev->config[0], sizeof(pPciDev->config));
836	}
837
838	static int pciR3CommonSaveExec(PPCIBUS pBus, PSSMHANDLE pSSM)
839	{
840	/*
841	* Iterate thru all the devices.
842	*/
843	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
844	{
845	PPCIDEVICE pDev = pBus->apDevices[i];
846	if (pDev)
847	{
848	/* Device position */
849	SSMR3PutU32(pSSM, i);
850	/* PCI config registers */
851	SSMR3PutMem(pSSM, pDev->config, sizeof(pDev->config));
852
853	/* IRQ pin state */
854	int rc = SSMR3PutS32(pSSM, pDev->Int.s.uIrqPinState);
855	if (RT_FAILURE(rc))
856	return rc;
857	}
858	}
859	return SSMR3PutU32(pSSM, UINT32_MAX); /* terminator */
860	}
861
862	static DECLCALLBACK(int) pciR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
863	{
864	PPCIBUS pThis = PDMINS_2_DATA(pDevIns, PPCIBUS);
865	return pciR3CommonSaveExec(pThis, pSSM);
866	}
867
868
869	static DECLCALLBACK(int) pcibridgeR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
870	{
871	PPCIBUS pThis = PDMINS_2_DATA(pDevIns, PPCIBUS);
872	return pciR3CommonSaveExec(pThis, pSSM);
873	}
874
875
876	/**
877	* Common routine for restoring the config registers of a PCI device.
878	*
879	* @param pDev The PCI device.
880	* @param pbSrcConfig The configuration register values to be loaded.
881	* @param fIsBridge Whether this is a bridge device or not.
882	*/
883	static void pciR3CommonRestoreConfig(PPCIDEVICE pDev, uint8_t const *pbSrcConfig, bool fIsBridge)
884	{
885	/*
886	* This table defines the fields for normal devices and bridge devices, and
887	* the order in which they need to be restored.
888	*/
889	static const struct PciField
890	{
891	uint8_t off;
892	uint8_t cb;
893	uint8_t fWritable;
894	uint8_t fBridge;
895	const char *pszName;
896	} s_aFields[] =
897	{
898	/* off,cb,fW,fB, pszName */
899	{ VBOX_PCI_VENDOR_ID, 2, 0, 3, "VENDOR_ID" },
900	{ VBOX_PCI_DEVICE_ID, 2, 0, 3, "DEVICE_ID" },
901	{ VBOX_PCI_STATUS, 2, 1, 3, "STATUS" },
902	{ VBOX_PCI_REVISION_ID, 1, 0, 3, "REVISION_ID" },
903	{ VBOX_PCI_CLASS_PROG, 1, 0, 3, "CLASS_PROG" },
904	{ VBOX_PCI_CLASS_SUB, 1, 0, 3, "CLASS_SUB" },
905	{ VBOX_PCI_CLASS_DEVICE, 1, 0, 3, "CLASS_BASE" },
906	{ VBOX_PCI_CACHE_LINE_SIZE, 1, 1, 3, "CACHE_LINE_SIZE" },
907	{ VBOX_PCI_LATENCY_TIMER, 1, 1, 3, "LATENCY_TIMER" },
908	{ VBOX_PCI_HEADER_TYPE, 1, 0, 3, "HEADER_TYPE" },
909	{ VBOX_PCI_BIST, 1, 1, 3, "BIST" },
910	{ VBOX_PCI_BASE_ADDRESS_0, 4, 1, 3, "BASE_ADDRESS_0" },
911	{ VBOX_PCI_BASE_ADDRESS_1, 4, 1, 3, "BASE_ADDRESS_1" },
912	{ VBOX_PCI_BASE_ADDRESS_2, 4, 1, 1, "BASE_ADDRESS_2" },
913	{ VBOX_PCI_PRIMARY_BUS, 1, 1, 2, "PRIMARY_BUS" }, // fWritable = ??
914	{ VBOX_PCI_SECONDARY_BUS, 1, 1, 2, "SECONDARY_BUS" }, // fWritable = ??
915	{ VBOX_PCI_SUBORDINATE_BUS, 1, 1, 2, "SUBORDINATE_BUS" }, // fWritable = ??
916	{ VBOX_PCI_SEC_LATENCY_TIMER, 1, 1, 2, "SEC_LATENCY_TIMER" }, // fWritable = ??
917	{ VBOX_PCI_BASE_ADDRESS_3, 4, 1, 1, "BASE_ADDRESS_3" },
918	{ VBOX_PCI_IO_BASE, 1, 1, 2, "IO_BASE" }, // fWritable = ??
919	{ VBOX_PCI_IO_LIMIT, 1, 1, 2, "IO_LIMIT" }, // fWritable = ??
920	{ VBOX_PCI_SEC_STATUS, 2, 1, 2, "SEC_STATUS" }, // fWritable = ??
921	{ VBOX_PCI_BASE_ADDRESS_4, 4, 1, 1, "BASE_ADDRESS_4" },
922	{ VBOX_PCI_MEMORY_BASE, 2, 1, 2, "MEMORY_BASE" }, // fWritable = ??
923	{ VBOX_PCI_MEMORY_LIMIT, 2, 1, 2, "MEMORY_LIMIT" }, // fWritable = ??
924	{ VBOX_PCI_BASE_ADDRESS_4, 4, 1, 1, "BASE_ADDRESS_4" },
925	{ VBOX_PCI_PREF_MEMORY_BASE, 2, 1, 2, "PREF_MEMORY_BASE" }, // fWritable = ??
926	{ VBOX_PCI_PREF_MEMORY_LIMIT, 2, 1, 2, "PREF_MEMORY_LIMIT" }, // fWritable = ??
927	{ VBOX_PCI_CARDBUS_CIS, 4, 1, 1, "CARDBUS_CIS" }, // fWritable = ??
928	{ VBOX_PCI_PREF_BASE_UPPER32, 4, 1, 2, "PREF_BASE_UPPER32" }, // fWritable = ??
929	{ VBOX_PCI_SUBSYSTEM_VENDOR_ID, 2, 0, 1, "SUBSYSTEM_VENDOR_ID" },// fWritable = !?
930	{ VBOX_PCI_PREF_LIMIT_UPPER32, 4, 1, 2, "PREF_LIMIT_UPPER32" },// fWritable = ??
931	{ VBOX_PCI_SUBSYSTEM_ID, 2, 0, 1, "SUBSYSTEM_ID" }, // fWritable = !?
932	{ VBOX_PCI_ROM_ADDRESS, 4, 1, 1, "ROM_ADDRESS" }, // fWritable = ?!
933	{ VBOX_PCI_IO_BASE_UPPER16, 2, 1, 2, "IO_BASE_UPPER16" }, // fWritable = ?!
934	{ VBOX_PCI_IO_LIMIT_UPPER16, 2, 1, 2, "IO_LIMIT_UPPER16" }, // fWritable = ?!
935	{ VBOX_PCI_CAPABILITY_LIST, 4, 0, 3, "CAPABILITY_LIST" }, // fWritable = !? cb=!?
936	{ VBOX_PCI_RESERVED_38, 4, 1, 1, "RESERVED_38" }, // ???
937	{ VBOX_PCI_ROM_ADDRESS_BR, 4, 1, 2, "ROM_ADDRESS_BR" }, // fWritable = !? cb=!? fBridge=!?
938	{ VBOX_PCI_INTERRUPT_LINE, 1, 1, 3, "INTERRUPT_LINE" }, // fBridge=??
939	{ VBOX_PCI_INTERRUPT_PIN, 1, 0, 3, "INTERRUPT_PIN" }, // fBridge=??
940	{ VBOX_PCI_MIN_GNT, 1, 0, 1, "MIN_GNT" },
941	{ VBOX_PCI_BRIDGE_CONTROL, 2, 1, 2, "BRIDGE_CONTROL" }, // fWritable = !?
942	{ VBOX_PCI_MAX_LAT, 1, 0, 3, "MAX_LAT" }, // fBridge=!?
943	/* The COMMAND register must come last as it requires the ADDRESS
944	registers to be restored before we pretent to change it from 0 to
945	whatever value the guest assigned it. */
946	{ VBOX_PCI_COMMAND, 2, 1, 3, "COMMAND" },
947	};
948
949	#ifdef RT_STRICT
950	/* Check that we've got full register coverage. */
951	uint32_t bmDevice[0x40 / 32];
952	uint32_t bmBridge[0x40 / 32];
953	RT_ZERO(bmDevice);
954	RT_ZERO(bmBridge);
955	for (uint32_t i = 0; i < RT_ELEMENTS(s_aFields); i++)
956	{
957	uint8_t off = s_aFields[i].off;
958	uint8_t cb = s_aFields[i].cb;
959	uint8_t f = s_aFields[i].fBridge;
960	while (cb-- > 0)
961	{
962	if (f & 1) AssertMsg(!ASMBitTest(bmDevice, off), ("%#x\n", off));
963	if (f & 2) AssertMsg(!ASMBitTest(bmBridge, off), ("%#x\n", off));
964	if (f & 1) ASMBitSet(bmDevice, off);
965	if (f & 2) ASMBitSet(bmBridge, off);
966	off++;
967	}
968	}
969	for (uint32_t off = 0; off < 0x40; off++)
970	{
971	AssertMsg(ASMBitTest(bmDevice, off), ("%#x\n", off));
972	AssertMsg(ASMBitTest(bmBridge, off), ("%#x\n", off));
973	}
974	#endif
975
976	/*
977	* Loop thru the fields covering the 64 bytes of standard registers.
978	*/
979	uint8_t const fBridge = fIsBridge ? 2 : 1;
980	uint8_t *pbDstConfig = &pDev->config[0];
981	for (uint32_t i = 0; i < RT_ELEMENTS(s_aFields); i++)
982	if (s_aFields[i].fBridge & fBridge)
983	{
984	uint8_t const off = s_aFields[i].off;
985	uint8_t const cb = s_aFields[i].cb;
986	uint32_t u32Src;
987	uint32_t u32Dst;
988	switch (cb)
989	{
990	case 1:
991	u32Src = pbSrcConfig[off];
992	u32Dst = pbDstConfig[off];
993	break;
994	case 2:
995	u32Src = (uint16_t const )&pbSrcConfig[off];
996	u32Dst = (uint16_t const )&pbDstConfig[off];
997	break;
998	case 4:
999	u32Src = (uint32_t const )&pbSrcConfig[off];
1000	u32Dst = (uint32_t const )&pbDstConfig[off];
1001	break;
1002	default:
1003	AssertFailed();
1004	continue;
1005	}
1006
1007	if ( u32Src != u32Dst
1008	\|\| off == VBOX_PCI_COMMAND)
1009	{
1010	if (u32Src != u32Dst)
1011	{
1012	if (!s_aFields[i].fWritable)
1013	LogRel(("PCI: %8s/%u: %2u-bit field %s: %x -> %x - !READ ONLY!\n",
1014	pDev->name, pDev->pDevIns->iInstance, cb*8, s_aFields[i].pszName, u32Dst, u32Src));
1015	else
1016	LogRel(("PCI: %8s/%u: %2u-bit field %s: %x -> %x\n",
1017	pDev->name, pDev->pDevIns->iInstance, cb*8, s_aFields[i].pszName, u32Dst, u32Src));
1018	}
1019	if (off == VBOX_PCI_COMMAND)
1020	PCIDevSetCommand(pDev, 0); /* For remapping, see pciR3CommonLoadExec. */
1021	pDev->Int.s.pfnConfigWrite(pDev, off, u32Src, cb);
1022	}
1023	}
1024
1025	/*
1026	* The device dependent registers.
1027	*
1028	* We will not use ConfigWrite here as we have no clue about the size
1029	* of the registers, so the device is responsible for correctly
1030	* restoring functionality governed by these registers.
1031	*/
1032	for (uint32_t off = 0x40; off < sizeof(pDev->config); off++)
1033	if (pbDstConfig[off] != pbSrcConfig[off])
1034	{
1035	LogRel(("PCI: %8s/%u: register %02x: %02x -> %02x\n",
1036	pDev->name, pDev->pDevIns->iInstance, off, pbDstConfig[off], pbSrcConfig[off])); /** @todo make this Log() later. */
1037	pbDstConfig[off] = pbSrcConfig[off];
1038	}
1039	}
1040
1041	/**
1042	* Common worker for pciR3LoadExec and pcibridgeR3LoadExec.
1043	*
1044	* @returns VBox status code.
1045	* @param pBus The bus which data is being loaded.
1046	* @param pSSM The saved state handle.
1047	* @param uVersion The data version.
1048	* @param uPass The pass.
1049	*/
1050	static DECLCALLBACK(int) pciR3CommonLoadExec(PPCIBUS pBus, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1051	{
1052	uint32_t u32;
1053	uint32_t i;
1054	int rc;
1055
1056	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
1057
1058	/*
1059	* Iterate thru all the devices and write 0 to the COMMAND register so
1060	* that all the memory is unmapped before we start restoring the saved
1061	* mapping locations.
1062	*
1063	* The register value is restored afterwards so we can do proper
1064	* LogRels in pciR3CommonRestoreConfig.
1065	*/
1066	for (i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
1067	{
1068	PPCIDEVICE pDev = pBus->apDevices[i];
1069	if (pDev)
1070	{
1071	uint16_t u16 = PCIDevGetCommand(pDev);
1072	pDev->Int.s.pfnConfigWrite(pDev, VBOX_PCI_COMMAND, 0, 2);
1073	PCIDevSetCommand(pDev, u16);
1074	Assert(PCIDevGetCommand(pDev) == u16);
1075	}
1076	}
1077
1078	/*
1079	* Iterate all the devices.
1080	*/
1081	for (i = 0;; i++)
1082	{
1083	PCIDEVICE DevTmp;
1084	PPCIDEVICE pDev;
1085
1086	/* index / terminator */
1087	rc = SSMR3GetU32(pSSM, &u32);
1088	if (RT_FAILURE(rc))
1089	return rc;
1090	if (u32 == (uint32_t)~0)
1091	break;
1092	if ( u32 >= RT_ELEMENTS(pBus->apDevices)
1093	\|\| u32 < i)
1094	{
1095	AssertMsgFailed(("u32=%#x i=%#x\n", u32, i));
1096	return rc;
1097	}
1098
1099	/* skip forward to the device checking that no new devices are present. */
1100	for (; i < u32; i++)
1101	{
1102	pDev = pBus->apDevices[i];
1103	if (pDev)
1104	{
1105	LogRel(("New device in slot %#x, %s (vendor=%#06x device=%#06x)\n", i, pDev->name,
1106	PCIDevGetVendorId(pDev), PCIDevGetDeviceId(pDev)));
1107	if (SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT)
1108	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("New device in slot %#x, %s (vendor=%#06x device=%#06x)"),
1109	i, pDev->name, PCIDevGetVendorId(pDev), PCIDevGetDeviceId(pDev));
1110	}
1111	}
1112
1113	/* get the data */
1114	DevTmp.Int.s.uIrqPinState = ~0; /* Invalid value in case we have an older saved state to force a state change in pciSetIrq. */
1115	SSMR3GetMem(pSSM, DevTmp.config, sizeof(DevTmp.config));
1116
1117	rc = SSMR3GetS32(pSSM, &DevTmp.Int.s.uIrqPinState);
1118	if (RT_FAILURE(rc))
1119	return rc;
1120
1121	/* check that it's still around. */
1122	pDev = pBus->apDevices[i];
1123	if (!pDev)
1124	{
1125	LogRel(("Device in slot %#x has been removed! vendor=%#06x device=%#06x\n", i,
1126	PCIDevGetVendorId(&DevTmp), PCIDevGetDeviceId(&DevTmp)));
1127	if (SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT)
1128	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Device in slot %#x has been removed! vendor=%#06x device=%#06x"),
1129	i, PCIDevGetVendorId(&DevTmp), PCIDevGetDeviceId(&DevTmp));
1130	continue;
1131	}
1132
1133	/* match the vendor id assuming that this will never be changed. */
1134	if ( DevTmp.config[0] != pDev->config[0]
1135	\|\| DevTmp.config[1] != pDev->config[1])
1136	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Device in slot %#x (%s) vendor id mismatch! saved=%.4Rhxs current=%.4Rhxs"),
1137	i, pDev->name, DevTmp.config, pDev->config);
1138
1139	/* commit the loaded device config. */
1140	pciR3CommonRestoreConfig(pDev, &DevTmp.config[0], false ); /** @todo fix bridge fun! */
1141
1142	pDev->Int.s.uIrqPinState = DevTmp.Int.s.uIrqPinState;
1143	}
1144
1145	return VINF_SUCCESS;
1146	}
1147
1148	/**
1149	* Loads a saved PCI device state.
1150	*
1151	* @returns VBox status code.
1152	* @param pDevIns Device instance of the PCI Bus.
1153	* @param pPciDev Pointer to PCI device.
1154	* @param pSSM The handle to the saved state.
1155	*/
1156	static DECLCALLBACK(int) pciGenericLoadExec(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PSSMHANDLE pSSM)
1157	{
1158	return SSMR3GetMem(pSSM, &pPciDev->config[0], sizeof(pPciDev->config));
1159	}
1160
1161	static DECLCALLBACK(int) pciR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1162	{
1163	PPCIBUS pThis = PDMINS_2_DATA(pDevIns, PPCIBUS);
1164	if (uVersion > VBOX_ICH9PCI_SAVED_STATE_VERSION)
1165	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1166	return pciR3CommonLoadExec(pThis, pSSM, uVersion, uPass);
1167	}
1168
1169	static DECLCALLBACK(int) pcibridgeR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1170	{
1171	PPCIBUS pThis = PDMINS_2_DATA(pDevIns, PPCIBUS);
1172	if (uVersion > VBOX_ICH9PCI_SAVED_STATE_VERSION)
1173	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1174	return pciR3CommonLoadExec(pThis, pSSM, uVersion, uPass);
1175	}
1176
1177	static uint32_t ich9pciConfigRead(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t len)
1178	{
1179	/* Set destination address */
1180	/// @todo: device locking?
1181	pGlobals->uConfigReg = 0x80000000 \| (uBus << 16) \|
1182	(uDevFn << 8) \| (addr & ~3);
1183	uint32_t u32Val;
1184	int rc = ich9pciDataRead(pGlobals, addr & 3, len, &u32Val);
1185	AssertRC(rc);
1186	switch (len)
1187	{
1188	case 1:
1189	u32Val &= 0xff;
1190	break;
1191	case 2:
1192	u32Val &= 0xffff;
1193	break;
1194	}
1195	return u32Val;
1196	}
1197
1198	static void ich9pciConfigWrite(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t val, uint32_t len)
1199	{
1200	/* Set destination address */
1201	/// @todo: device locking?
1202	pGlobals->uConfigReg = 0x80000000 \| (uBus << 16) \|
1203	(uDevFn << 8) \| addr;
1204	ich9pciDataWrite(pGlobals, 0, val, len);
1205	}
1206
1207	static void ich9pciSetRegionAddress(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, int iRegion, uint32_t addr)
1208	{
1209	uint32_t uReg = ich9pciGetRegionReg(iRegion);
1210
1211	/* Read memory type first. */
1212	uint8_t uResourceType = ich9pciConfigRead(pGlobals, uBus, uDevFn, uReg, 1);
1213	/* Read command register. */
1214	uint16_t uCmd = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_COMMAND, 2);
1215
1216	if ( iRegion == PCI_ROM_SLOT )
1217	uCmd \|= PCI_COMMAND_MEMACCESS;
1218	else if ((uResourceType & PCI_ADDRESS_SPACE_IO) == PCI_ADDRESS_SPACE_IO)
1219	uCmd \|= PCI_COMMAND_IOACCESS; /* Enable I/O space access. */
1220	else /* The region is MMIO. */
1221	uCmd \|= PCI_COMMAND_MEMACCESS; /* Enable MMIO access. */
1222
1223	/* Write address of the device. */
1224	ich9pciConfigWrite(pGlobals, uBus, uDevFn, uReg, addr, 4);
1225
1226	/* enable memory mappings */
1227	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_COMMAND, uCmd, 2);
1228	}
1229
1230
1231	static void ich9pciBiosInitBridge(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint8_t cBridgeDepth, uint8_t *paBridgePositions)
1232	{
1233	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_SECONDARY_BUS, pGlobals->uBus, 1);
1234	/* Temporary until we know how many other bridges are behind this one. */
1235	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_SUBORDINATE_BUS, 0xff, 1);
1236
1237	/* Add position of this bridge into the array. */
1238	paBridgePositions[cBridgeDepth+1] = (uDevFn >> 3);
1239
1240	/*
1241	* The I/O range for the bridge must be aligned to a 4KB boundary.
1242	* This does not change anything really as the access to the device is not going
1243	* through the bridge but we want to be compliant to the spec.
1244	*/
1245	if ((pGlobals->uPciBiosIo % 4096) != 0)
1246	{
1247	pGlobals->uPciBiosIo = RT_ALIGN_32(pGlobals->uPciBiosIo, 4*1024);
1248	Log(("%s: Aligned I/O start address. New address %#x\n", __FUNCTION__, pGlobals->uPciBiosIo));
1249	}
1250	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_IO_BASE, (pGlobals->uPciBiosIo >> 8) & 0xf0, 1);
1251
1252	/* The MMIO range for the bridge must be aligned to a 1MB boundary. */
1253	if ((pGlobals->uPciBiosMmio % (1024 * 1024)) != 0)
1254	{
1255	pGlobals->uPciBiosMmio = RT_ALIGN_32(pGlobals->uPciBiosMmio, 1024*1024);
1256	Log(("%s: Aligned MMIO start address. New address %#x\n", __FUNCTION__, pGlobals->uPciBiosMmio));
1257	}
1258	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_MEMORY_BASE, (pGlobals->uPciBiosMmio >> 16) & UINT32_C(0xffff0), 2);
1259
1260	/* Save values to compare later to. */
1261	uint32_t u32IoAddressBase = pGlobals->uPciBiosIo;
1262	uint32_t u32MMIOAddressBase = pGlobals->uPciBiosMmio;
1263
1264	/* Init devices behind the bridge and possibly other bridges as well. */
1265	for (int iDev = 0; iDev <= 255; iDev++)
1266	ich9pciBiosInitDevice(pGlobals, uBus + 1, iDev, cBridgeDepth + 1, paBridgePositions);
1267
1268	/* The number of bridges behind the this one is now available. */
1269	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_SUBORDINATE_BUS, pGlobals->uBus, 1);
1270
1271	/*
1272	* Set I/O limit register. If there is no device with I/O space behind the bridge
1273	* we set a lower value than in the base register.
1274	* The result with a real bridge is that no I/O transactions are passed to the secondary
1275	* interface. Again this doesn't really matter here but we want to be compliant to the spec.
1276	*/
1277	if ((u32IoAddressBase != pGlobals->uPciBiosIo) && ((pGlobals->uPciBiosIo % 4096) != 0))
1278	{
1279	/* The upper boundary must be one byte less than a 4KB boundary. */
1280	pGlobals->uPciBiosIo = RT_ALIGN_32(pGlobals->uPciBiosIo, 4*1024);
1281	}
1282
1283	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_IO_LIMIT, ((pGlobals->uPciBiosIo >> 8) & 0xf0) - 1, 1);
1284
1285	/* Same with the MMIO limit register but with 1MB boundary here. */
1286	if ((u32MMIOAddressBase != pGlobals->uPciBiosMmio) && ((pGlobals->uPciBiosMmio % (1024 * 1024)) != 0))
1287	{
1288	/* The upper boundary must be one byte less than a 1MB boundary. */
1289	pGlobals->uPciBiosMmio = RT_ALIGN_32(pGlobals->uPciBiosMmio, 1024*1024);
1290	}
1291	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_MEMORY_LIMIT, ((pGlobals->uPciBiosMmio >> 16) & UINT32_C(0xfff0)) - 1, 2);
1292
1293	/*
1294	* Set the prefetch base and limit registers. We currently have no device with a prefetchable region
1295	* which may be behind a bridge. Thatswhy it is unconditionally disabled here atm by writing a higher value into
1296	* the base register than in the limit register.
1297	*/
1298	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_MEMORY_BASE, 0xfff0, 2);
1299	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_MEMORY_LIMIT, 0x0, 2);
1300	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_BASE_UPPER32, 0x00, 4);
1301	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_LIMIT_UPPER32, 0x00, 4);
1302	}
1303
1304	static void ich9pciBiosInitDevice(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint8_t cBridgeDepth, uint8_t *paBridgePositions)
1305	{
1306	uint32_t *paddr;
1307	uint16_t uDevClass, uVendor, uDevice;
1308	uint8_t uCmd;
1309
1310	uDevClass = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_CLASS_DEVICE, 2);
1311	uVendor = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_VENDOR_ID, 2);
1312	uDevice = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_DEVICE_ID, 2);
1313
1314	/* If device is present */
1315	if (uVendor == 0xffff)
1316	return;
1317
1318	switch (uDevClass)
1319	{
1320	case 0x0101:
1321	/* IDE controller */
1322	ich9pciConfigWrite(pGlobals, uBus, uDevFn, 0x40, 0x8000, 2); /* enable IDE0 */
1323	ich9pciConfigWrite(pGlobals, uBus, uDevFn, 0x42, 0x8000, 2); /* enable IDE1 */
1324	goto default_map;
1325	break;
1326	case 0x0300:
1327	/* VGA controller */
1328	if (uVendor != 0x80ee)
1329	goto default_map;
1330	/* VGA: map frame buffer to default Bochs VBE address */
1331	ich9pciSetRegionAddress(pGlobals, uBus, uDevFn, 0, 0xE0000000);
1332	/*
1333	* Legacy VGA I/O ports are implicitly decoded by a VGA class device. But
1334	* only the framebuffer (i.e., a memory region) is explicitly registered via
1335	* ich9pciSetRegionAddress, so I/O decoding must be enabled manually.
1336	*/
1337	uCmd = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_COMMAND, 1);
1338	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_COMMAND,
1339	/* Enable I/O space access. */
1340	uCmd \| PCI_COMMAND_IOACCESS,
1341	1);
1342	break;
1343	case 0x0800:
1344	/* PIC */
1345	if (uVendor == 0x1014)
1346	{
1347	/* IBM */
1348	if (uDevice == 0x0046 \|\| uDevice == 0xFFFF)
1349	/* MPIC & MPIC2 */
1350	ich9pciSetRegionAddress(pGlobals, uBus, uDevFn, 0, 0x80800000 + 0x00040000);
1351	}
1352	break;
1353	case 0xff00:
1354	if ((uVendor == 0x0106b)
1355	&& (uDevice == 0x0017 \|\| uDevice == 0x0022))
1356	{
1357	/* macio bridge */
1358	ich9pciSetRegionAddress(pGlobals, uBus, uDevFn, 0, 0x80800000);
1359	}
1360	break;
1361	case 0x0604:
1362	/* PCI-to-PCI bridge. */
1363	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_PRIMARY_BUS, uBus, 1);
1364
1365	AssertMsg(pGlobals->uBus < 255, ("Too many bridges on the bus\n"));
1366	pGlobals->uBus++;
1367	ich9pciBiosInitBridge(pGlobals, uBus, uDevFn, cBridgeDepth, paBridgePositions);
1368	break;
1369	default:
1370	default_map:
1371	{
1372	/* default memory mappings */
1373	/*
1374	* We ignore ROM region here.
1375	*/
1376	for (int iRegion = 0; iRegion < (PCI_NUM_REGIONS-1); iRegion++)
1377	{
1378	uint32_t u32Address = ich9pciGetRegionReg(iRegion);
1379
1380	/* Calculate size. */
1381	uint8_t u8ResourceType = ich9pciConfigRead(pGlobals, uBus, uDevFn, u32Address, 1);
1382	ich9pciConfigWrite(pGlobals, uBus, uDevFn, u32Address, UINT32_C(0xffffffff), 4);
1383	uint32_t u32Size = ich9pciConfigRead(pGlobals, uBus, uDevFn, u32Address, 4);
1384	/* Clear resource information depending on resource type. */
1385	if ((u8ResourceType & PCI_COMMAND_IOACCESS) == PCI_COMMAND_IOACCESS) /* I/O */
1386	u32Size &= ~(0x01);
1387	else /* MMIO */
1388	u32Size &= ~(0x0f);
1389
1390	bool fIsPio = ((u8ResourceType & PCI_COMMAND_IOACCESS) == PCI_COMMAND_IOACCESS);
1391	/*
1392	* Invert all bits and add 1 to get size of the region.
1393	* (From PCI implementation note)
1394	*/
1395	if (fIsPio && (u32Size & UINT32_C(0xffff0000)) == 0)
1396	u32Size = (~(u32Size \| UINT32_C(0xffff0000))) + 1;
1397	else
1398	u32Size = (~u32Size) + 1;
1399
1400	Log(("%s: Size of region %u for device %d on bus %d is %u\n", __FUNCTION__, iRegion, uDevFn, uBus, u32Size));
1401
1402	if (u32Size)
1403	{
1404	paddr = fIsPio ? &pGlobals->uPciBiosIo : &pGlobals->uPciBiosMmio;
1405	paddr = (paddr + u32Size - 1) & ~(u32Size - 1);
1406	Log(("%s: Start address of %s region %u is %#x\n", __FUNCTION__, (fIsPio ? "I/O" : "MMIO"), iRegion, *paddr));
1407	ich9pciSetRegionAddress(pGlobals, uBus, uDevFn, iRegion, *paddr);
1408	*paddr += u32Size;
1409	Log(("%s: New address is %#x\n", __FUNCTION__, *paddr));
1410	}
1411	}
1412	break;
1413	}
1414	}
1415
1416	/* map the interrupt */
1417	uint32_t uPin = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_INTERRUPT_PIN, 1);
1418	if (uPin != 0)
1419	{
1420	uint8_t uBridgeDevFn = uDevFn;
1421	uPin--;
1422
1423	/* We need to go up to the host bus to see which irq this device will assert there. */
1424	while (cBridgeDepth != 0)
1425	{
1426	/* Get the pin the device would assert on the bridge. */
1427	uPin = ((uBridgeDevFn >> 3) + uPin) & 3;
1428	uBridgeDevFn = paBridgePositions[cBridgeDepth];
1429	cBridgeDepth--;
1430	}
1431	#if 0
1432	uPin = pci_slot_get_pirq(uDevFn, pin);
1433	pic_irq = pci_irqs[pin];
1434	ich9pciConfigWrite(pGlobals, uBus, uDevFn, PCI_INTERRUPT_LINE, pic_irq);
1435	#endif
1436	}
1437	}
1438
1439	static const uint8_t auPciIrqs[4] = { 11, 9, 11, 9 };
1440
1441	static DECLCALLBACK(int) ich9pciFakePCIBIOS(PPDMDEVINS pDevIns)
1442	{
1443	unsigned i;
1444	uint8_t elcr[2] = {0, 0};
1445	PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
1446	PVM pVM = PDMDevHlpGetVM(pDevIns);
1447	Assert(pVM);
1448
1449	/*
1450	* Set the start addresses.
1451	*/
1452	pGlobals->uPciBiosIo = 0xd000;
1453	pGlobals->uPciBiosMmio = UINT32_C(0xf0000000);
1454	pGlobals->uBus = 0;
1455
1456	/*
1457	* Activate IRQ mappings.
1458	*/
1459	for (i = 0; i < 4; i++)
1460	{
1461	uint8_t irq = auPciIrqs[i];
1462	/* Set to trigger level. */
1463	elcr[irq >> 3] \|= (1 << (irq & 7));
1464	}
1465
1466	/* Tell to the PIC. */
1467	VBOXSTRICTRC rcStrict = IOMIOPortWrite(pVM, 0x4d0, elcr[0], sizeof(uint8_t));
1468	if (rcStrict == VINF_SUCCESS)
1469	rcStrict = IOMIOPortWrite(pVM, 0x4d1, elcr[1], sizeof(uint8_t));
1470	if (rcStrict != VINF_SUCCESS)
1471	{
1472	AssertMsgFailed(("Writing to PIC failed! rcStrict=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
1473	return RT_SUCCESS(rcStrict) ? VERR_INTERNAL_ERROR : VBOXSTRICTRC_VAL(rcStrict);
1474	}
1475
1476	/*
1477	* Init the devices.
1478	*/
1479	for (i = 0; i < 256; i++)
1480	{
1481	uint8_t aBridgePositions[256];
1482
1483	memset(aBridgePositions, 0, sizeof(aBridgePositions));
1484	Log2(("PCI: Initializing device %d (%#x)\n",
1485	i, 0x80000000 \| (i << 8)));
1486	ich9pciBiosInitDevice(pGlobals, 0, i, 0, aBridgePositions);
1487	}
1488
1489	return VINF_SUCCESS;
1490	}
1491
1492	static DECLCALLBACK(uint32_t) ich9pciConfigRead(PCIDevice *aDev, uint32_t u32Address, unsigned len)
1493	{
1494	if ((u32Address + len) > 256 && (u32Address + len) < 4096)
1495	{
1496	AssertMsgReturn(false, ("Read from extended registers falled back to generic code\n"), 0);
1497	}
1498
1499	AssertMsgReturn(u32Address + len <= 256, ("Read after end of PCI config space\n"),
1500	0);
1501	switch (len)
1502	{
1503	case 1:
1504	return aDev->config[u32Address];
1505	case 2:
1506	return RT_LE2H_U16((uint16_t )(aDev->config + u32Address));
1507	default:
1508	case 4:
1509	return RT_LE2H_U32((uint32_t )(aDev->config + u32Address));
1510	}
1511	}
1512
1513
1514	/**
1515	* See paragraph 7.5 of PCI Express specification (p. 349) for definition of
1516	* registers and their writability policy.
1517	*/
1518	static DECLCALLBACK(void) ich9pciConfigWrite(PCIDevice *aDev, uint32_t u32Address,
1519	uint32_t val, unsigned len)
1520	{
1521	if ((u32Address + len) > 256 && (u32Address + len) < 4096)
1522	{
1523	AssertMsgReturnVoid(false, ("Write to extended registers falled back to generic code\n"));
1524	}
1525
1526	AssertMsgReturnVoid(u32Address + len <= 256, ("Write after end of PCI config space\n"));
1527
1528	/* Fast case - update one of BARs or ROM address, 'while' only for 'break' */
1529	while ( len == 4
1530	&& ( ( u32Address >= VBOX_PCI_BASE_ADDRESS_0
1531	&& u32Address < VBOX_PCI_BASE_ADDRESS_0 + 6 * 4)
1532	\|\| ( u32Address >= VBOX_PCI_ROM_ADDRESS
1533	&& u32Address < VBOX_PCI_ROM_ADDRESS+4)
1534	)
1535	)
1536	{
1537	PCIIORegion *pRegion;
1538	int reg, regionSize;
1539
1540	reg = (u32Address >= VBOX_PCI_ROM_ADDRESS) ? PCI_ROM_SLOT : (u32Address - VBOX_PCI_BASE_ADDRESS_0) >> 2;
1541	pRegion = &aDev->Int.s.aIORegions[reg];
1542	regionSize = pRegion->size;
1543	if (regionSize == 0)
1544	break;
1545	/* compute the stored value */
1546	if (reg == PCI_ROM_SLOT) {
1547	/* keep ROM enable bit */
1548	val &= (~(regionSize - 1)) \| 1;
1549	} else {
1550	val &= ~(regionSize - 1);
1551	val \|= pRegion->type;
1552	}
1553	(uint32_t )(aDev->config + u32Address) = RT_H2LE_U32(val);
1554	ich9pciUpdateMappings(aDev);
1555	return;
1556	}
1557
1558	uint32_t addr = u32Address;
1559	bool fUpdateMappings = false;
1560	for (uint32_t i = 0; i < len; i++)
1561	{
1562	bool fWritable = false;
1563	switch (PCIDevGetHeaderType(aDev))
1564	{
1565	case 0x00: /* normal device */
1566	case 0x80: /* multi-function device */
1567	switch (addr)
1568	{
1569	/* Read-only registers, see */
1570	case VBOX_PCI_VENDOR_ID: case VBOX_PCI_VENDOR_ID+1:
1571	case VBOX_PCI_DEVICE_ID: case VBOX_PCI_DEVICE_ID+1:
1572	case VBOX_PCI_REVISION_ID:
1573	case VBOX_PCI_CLASS_PROG:
1574	case VBOX_PCI_CLASS_SUB:
1575	case VBOX_PCI_CLASS_BASE:
1576	case VBOX_PCI_HEADER_TYPE:
1577	case VBOX_PCI_BASE_ADDRESS_0: case VBOX_PCI_BASE_ADDRESS_0+1: case VBOX_PCI_BASE_ADDRESS_0+2: case VBOX_PCI_BASE_ADDRESS_0+3:
1578	case VBOX_PCI_BASE_ADDRESS_1: case VBOX_PCI_BASE_ADDRESS_1+1: case VBOX_PCI_BASE_ADDRESS_1+2: case VBOX_PCI_BASE_ADDRESS_1+3:
1579	case VBOX_PCI_BASE_ADDRESS_2: case VBOX_PCI_BASE_ADDRESS_2+1: case VBOX_PCI_BASE_ADDRESS_2+2: case VBOX_PCI_BASE_ADDRESS_2+3:
1580	case VBOX_PCI_BASE_ADDRESS_3: case VBOX_PCI_BASE_ADDRESS_3+1: case VBOX_PCI_BASE_ADDRESS_3+2: case VBOX_PCI_BASE_ADDRESS_3+3:
1581	case VBOX_PCI_BASE_ADDRESS_4: case VBOX_PCI_BASE_ADDRESS_4+1: case VBOX_PCI_BASE_ADDRESS_4+2: case VBOX_PCI_BASE_ADDRESS_4+3:
1582	case VBOX_PCI_BASE_ADDRESS_5: case VBOX_PCI_BASE_ADDRESS_5+1: case VBOX_PCI_BASE_ADDRESS_5+2: case VBOX_PCI_BASE_ADDRESS_5+3:
1583	case VBOX_PCI_SUBSYSTEM_VENDOR_ID: case VBOX_PCI_SUBSYSTEM_VENDOR_ID+1:
1584	case VBOX_PCI_SUBSYSTEM_ID: case VBOX_PCI_SUBSYSTEM_ID+1:
1585	case VBOX_PCI_ROM_ADDRESS: case VBOX_PCI_ROM_ADDRESS+1: case VBOX_PCI_ROM_ADDRESS+2: case VBOX_PCI_ROM_ADDRESS+3:
1586	case VBOX_PCI_CAPABILITY_LIST:
1587	case VBOX_PCI_INTERRUPT_PIN:
1588	fWritable = false;
1589	break;
1590	/* Others can be written */
1591	default:
1592	fWritable = true;
1593	break;
1594	}
1595	break;
1596	default:
1597	case 0x01: /* bridge */
1598	switch (addr)
1599	{
1600	/* Read-only registers */
1601	case VBOX_PCI_VENDOR_ID: case VBOX_PCI_VENDOR_ID+1:
1602	case VBOX_PCI_DEVICE_ID: case VBOX_PCI_DEVICE_ID+1:
1603	case VBOX_PCI_REVISION_ID:
1604	case VBOX_PCI_CLASS_PROG:
1605	case VBOX_PCI_CLASS_SUB:
1606	case VBOX_PCI_CLASS_BASE:
1607	case VBOX_PCI_HEADER_TYPE:
1608	case VBOX_PCI_ROM_ADDRESS_BR: case VBOX_PCI_ROM_ADDRESS_BR+1: case VBOX_PCI_ROM_ADDRESS_BR+2: case VBOX_PCI_ROM_ADDRESS_BR+3:
1609	case VBOX_PCI_INTERRUPT_PIN:
1610	fWritable = false;
1611	break;
1612	default:
1613	fWritable = true;
1614	break;
1615	}
1616	break;
1617	}
1618
1619	switch (addr)
1620	{
1621	case VBOX_PCI_COMMAND: /* Command register, bits 0-7. */
1622	fUpdateMappings = true;
1623	aDev->config[addr] = val;
1624	break;
1625	case VBOX_PCI_COMMAND+1: /* Command register, bits 8-15. */
1626	/* don't change reserved bits (11-15) */
1627	val &= UINT32_C(~0xf8);
1628	fUpdateMappings = true;
1629	aDev->config[addr] = val;
1630	break;
1631	case VBOX_PCI_STATUS: /* Status register, bits 0-7. */
1632	/* don't change read-only bits => actually all lower bits are read-only */
1633	val &= UINT32_C(~0xff);
1634	/* status register, low part: clear bits by writing a '1' to the corresponding bit */
1635	aDev->config[addr] &= ~val;
1636	break;
1637	case VBOX_PCI_STATUS+1: /* Status register, bits 8-15. */
1638	/* don't change read-only bits */
1639	val &= UINT32_C(~0x06);
1640	/* status register, high part: clear bits by writing a '1' to the corresponding bit */
1641	aDev->config[addr] &= ~val;
1642	break;
1643	default:
1644	if (fWritable)
1645	aDev->config[addr] = val;
1646	}
1647	addr++;
1648	val >>= 8;
1649	}
1650
1651	if (fUpdateMappings)
1652	/* if the command register is modified, we must modify the mappings */
1653	ich9pciUpdateMappings(aDev);
1654	}
1655
1656	/* Slot/functions assignment per table at p. 12 of ICH9 family spec update */
1657	static const struct {
1658	const char* pszName;
1659	int32_t iSlot;
1660	int32_t iFunction;
1661	} PciSlotAssignments[] = {
1662	{
1663	"piix3ide", 1, 1 // do we really need it?
1664	},
1665	{
1666	"lan", 25, 0 /* LAN controller */
1667	},
1668	{
1669	"hda", 27, 0 /* High Definition Audio */
1670	},
1671	{
1672	"i82801", 30, 0 /* Host Controller */
1673	},
1674	{
1675	"lpc", 31, 0 /* Low Pin Count bus */
1676	},
1677	{
1678	"ahci", 31, 2 /* SATA controller */
1679	},
1680	{
1681	"smbus", 31, 3 /* System Management Bus */
1682	},
1683	{
1684	"thermal", 31, 6 /* Thermal controller */
1685	},
1686	};
1687
1688	static int assignPosition(PPCIBUS pBus, PPCIDEVICE pPciDev, const char *pszName)
1689	{
1690	/* Hardcoded slots/functions, per chipset spec */
1691	for (size_t i = 0; i < RT_ELEMENTS(PciSlotAssignments); i++)
1692	{
1693	if (!strcmp(pszName, PciSlotAssignments[i].pszName))
1694	{
1695	pPciDev->Int.s.fRequestedDevFn = true;
1696	return (PciSlotAssignments[i].iSlot << 3) + PciSlotAssignments[i].iFunction;
1697	}
1698	}
1699
1700	/* Otherwise when assigning a slot, we need to make sure all its functions are available */
1701	for (int iPos = 0; iPos < (int)RT_ELEMENTS(pBus->apDevices); iPos += 8)
1702	if ( !pBus->apDevices[iPos]
1703	&& !pBus->apDevices[iPos + 1]
1704	&& !pBus->apDevices[iPos + 2]
1705	&& !pBus->apDevices[iPos + 3]
1706	&& !pBus->apDevices[iPos + 4]
1707	&& !pBus->apDevices[iPos + 5]
1708	&& !pBus->apDevices[iPos + 6]
1709	&& !pBus->apDevices[iPos + 7])
1710	{
1711	pPciDev->Int.s.fRequestedDevFn = false;
1712	return iPos;
1713	}
1714
1715	return -1;
1716	}
1717
1718	static bool hasHardAssignedDevsInSlot(PPCIBUS pBus, int iSlot)
1719	{
1720	PCIDevice** aSlot = &pBus->apDevices[iSlot << 3];
1721
1722	return (aSlot[0] && aSlot[0]->Int.s.fRequestedDevFn)
1723	\|\| (aSlot[1] && aSlot[1]->Int.s.fRequestedDevFn)
1724	\|\| (aSlot[2] && aSlot[2]->Int.s.fRequestedDevFn)
1725	\|\| (aSlot[3] && aSlot[3]->Int.s.fRequestedDevFn)
1726	\|\| (aSlot[4] && aSlot[4]->Int.s.fRequestedDevFn)
1727	\|\| (aSlot[5] && aSlot[5]->Int.s.fRequestedDevFn)
1728	\|\| (aSlot[6] && aSlot[6]->Int.s.fRequestedDevFn)
1729	\|\| (aSlot[7] && aSlot[7]->Int.s.fRequestedDevFn)
1730	;
1731	}
1732
1733	static int ich9pciRegisterInternal(PPCIBUS pBus, int iDev, PPCIDEVICE pPciDev, const char *pszName)
1734	{
1735	/*
1736	* Find device position
1737	*/
1738	if (iDev < 0)
1739	{
1740	iDev = assignPosition(pBus, pPciDev, pszName);
1741	if (iDev < 0)
1742	{
1743	AssertMsgFailed(("Couldn't find free spot!\n"));
1744	return VERR_PDM_TOO_PCI_MANY_DEVICES;
1745	}
1746	}
1747
1748	/*
1749	* Check if we can really take this slot, possibly by relocating
1750	* its current habitant, if it wasn't hard assigned too.
1751	*/
1752	if (pPciDev->Int.s.fRequestedDevFn &&
1753	pBus->apDevices[iDev] &&
1754	pBus->apDevices[iDev]->Int.s.fRequestedDevFn)
1755	{
1756	/*
1757	* Smth like hasHardAssignedDevsInSlot(pBus, iDev >> 3) shall be use to make
1758	* it compatible with DevPCI.cpp version, but this way we cannot assign
1759	* in accordance with the chipset spec.
1760	*/
1761	AssertReleaseMsgFailed(("Configuration error:'%s' and '%s' are both configured as device %d\n",
1762	pszName, pBus->apDevices[iDev]->name, iDev));
1763	return VERR_INTERNAL_ERROR;
1764	}
1765
1766	if (pBus->apDevices[iDev])
1767	{
1768	/* if we got here, we shall (and usually can) relocate the device */
1769	int iRelDev = assignPosition(pBus, pBus->apDevices[iDev], pBus->apDevices[iDev]->name);
1770	if (iRelDev < 0 \|\| iRelDev == iDev)
1771	{
1772	AssertMsgFailed(("Couldn't find free spot!\n"));
1773	return VERR_PDM_TOO_PCI_MANY_DEVICES;
1774	}
1775	/* Copy device function by function to its new position */
1776	for (int i = 0; i < 8; i++)
1777	{
1778	if (!pBus->apDevices[iDev + i])
1779	continue;
1780	Log(("PCI: relocating '%s' from slot %#x to %#x\n", pBus->apDevices[iDev + i]->name, iDev + i, iRelDev + i));
1781	pBus->apDevices[iRelDev + i] = pBus->apDevices[iDev + i];
1782	pBus->apDevices[iRelDev + i]->devfn = iRelDev + i;
1783	pBus->apDevices[iDev + i] = NULL;
1784	}
1785	}
1786
1787	/*
1788	* Fill in device information.
1789	*/
1790	pPciDev->devfn = iDev;
1791	pPciDev->name = pszName;
1792	pPciDev->Int.s.pBusR3 = pBus;
1793	pPciDev->Int.s.pBusR0 = MMHyperR3ToR0(PDMDevHlpGetVM(pBus->CTX_SUFF(pDevIns)), pBus);
1794	pPciDev->Int.s.pBusRC = MMHyperR3ToRC(PDMDevHlpGetVM(pBus->CTX_SUFF(pDevIns)), pBus);
1795	pPciDev->Int.s.pfnConfigRead = ich9pciConfigRead;
1796	pPciDev->Int.s.pfnConfigWrite = ich9pciConfigWrite;
1797	pBus->apDevices[iDev] = pPciDev;
1798	if (pPciDev->Int.s.fPciToPciBridge)
1799	{
1800	AssertMsg(pBus->cBridges < RT_ELEMENTS(pBus->apDevices), ("Number of bridges exceeds the number of possible devices on the bus\n"));
1801	AssertMsg(pPciDev->Int.s.pfnBridgeConfigRead && pPciDev->Int.s.pfnBridgeConfigWrite,
1802	("device is a bridge but does not implement read/write functions\n"));
1803	pBus->papBridgesR3[pBus->cBridges] = pPciDev;
1804	pBus->cBridges++;
1805	}
1806
1807	Log(("PCI: Registered device %d function %d (%#x) '%s'.\n",
1808	iDev >> 3, iDev & 7, 0x80000000 \| (iDev << 8), pszName));
1809
1810	return VINF_SUCCESS;
1811	}
1812
1813
1814	/**
1815	* Info handler, device version.
1816	*
1817	* @param pDevIns Device instance which registered the info.
1818	* @param pHlp Callback functions for doing output.
1819	* @param pszArgs Argument string. Optional and specific to the handler.
1820	*/
1821	static DECLCALLBACK(void) ich9pciInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
1822	{
1823	PPCIBUS pBus = DEVINS_2_PCIBUS(pDevIns);
1824	uint32_t iBus = 0, iDev;
1825
1826
1827	for (iDev = 0; iDev < RT_ELEMENTS(pBus->apDevices); iDev++)
1828	{
1829	PPCIDEVICE pPciDev = pBus->apDevices[iDev];
1830	if (pPciDev != NULL)
1831	pHlp->pfnPrintf(pHlp, "%02x:%02x:%02x %s: %x-%x\n",
1832	iBus, (iDev >> 3) & 0xff, iDev & 0x7,
1833	pPciDev->name,
1834	PCIDevGetVendorId(pPciDev), PCIDevGetDeviceId(pPciDev)
1835	);
1836	}
1837	}
1838
1839
1840	static DECLCALLBACK(int) ich9pciConstruct(PPDMDEVINS pDevIns,
1841	int iInstance,
1842	PCFGMNODE pCfg)
1843	{
1844	int rc;
1845	Assert(iInstance == 0);
1846
1847	/*
1848	* Validate and read configuration.
1849	*/
1850	if (!CFGMR3AreValuesValid(pCfg,
1851	"IOAPIC\0"
1852	"GCEnabled\0"
1853	"R0Enabled\0"
1854	"McfgBase\0"
1855	"McfgLength\0"
1856	))
1857	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
1858
1859	/* query whether we got an IOAPIC */
1860	bool fUseIoApic;
1861	rc = CFGMR3QueryBoolDef(pCfg, "IOAPIC", &fUseIoApic, false);
1862	if (RT_FAILURE(rc))
1863	return PDMDEV_SET_ERROR(pDevIns, rc,
1864	N_("Configuration error: Failed to query boolean value \"IOAPIC\""));
1865
1866	/* check if RC code is enabled. */
1867	bool fGCEnabled;
1868	rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
1869	if (RT_FAILURE(rc))
1870	return PDMDEV_SET_ERROR(pDevIns, rc,
1871	N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
1872
1873	/* check if R0 code is enabled. */
1874	bool fR0Enabled;
1875	rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
1876	if (RT_FAILURE(rc))
1877	return PDMDEV_SET_ERROR(pDevIns, rc,
1878	N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
1879
1880	Log(("PCI: fUseIoApic=%RTbool fGCEnabled=%RTbool fR0Enabled=%RTbool\n", fUseIoApic, fGCEnabled, fR0Enabled));
1881
1882	/*
1883	* Init data.
1884	*/
1885	PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
1886	PPCIBUS pBus = &pGlobals->aPciBus;
1887	/* Zero out everything */
1888	memset(pGlobals, 0, sizeof(*pGlobals));
1889	/* And fill values */
1890	if (!fUseIoApic)
1891	return PDMDEV_SET_ERROR(pDevIns, rc,
1892	N_("Must use IO-APIC with ICH9 chipset"));
1893	rc = CFGMR3QueryU64Def(pCfg, "McfgBase", &pGlobals->u64PciConfigMMioAddress, 0);
1894	if (RT_FAILURE(rc))
1895	return PDMDEV_SET_ERROR(pDevIns, rc,
1896	N_("Configuration error: Failed to read \"McfgBase\""));
1897	rc = CFGMR3QueryU64Def(pCfg, "McfgLength", &pGlobals->u64PciConfigMMioLength, 0);
1898	if (RT_FAILURE(rc))
1899	return PDMDEV_SET_ERROR(pDevIns, rc,
1900	N_("Configuration error: Failed to read \"McfgLength\""));
1901
1902	pGlobals->pDevInsR3 = pDevIns;
1903	pGlobals->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
1904	pGlobals->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
1905
1906	pGlobals->aPciBus.pDevInsR3 = pDevIns;
1907	pGlobals->aPciBus.pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
1908	pGlobals->aPciBus.pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
1909	pGlobals->aPciBus.papBridgesR3 = (PPCIDEVICE )PDMDevHlpMMHeapAllocZ(pDevIns, sizeof(PPCIDEVICE) RT_ELEMENTS(pGlobals->aPciBus.apDevices));
1910
1911	/*
1912	* Register bus
1913	*/
1914	PDMPCIBUSREG PciBusReg;
1915	PciBusReg.u32Version = PDM_PCIBUSREG_VERSION;
1916	PciBusReg.pfnRegisterR3 = ich9pciRegister;
1917	PciBusReg.pfnIORegionRegisterR3 = ich9pciIORegionRegister;
1918	PciBusReg.pfnSetConfigCallbacksR3 = ich9pciSetConfigCallbacks;
1919	PciBusReg.pfnSetIrqR3 = ich9pciSetIrq;
1920	PciBusReg.pfnSaveExecR3 = pciGenericSaveExec;
1921	PciBusReg.pfnLoadExecR3 = pciGenericLoadExec;
1922	PciBusReg.pfnFakePCIBIOSR3 = ich9pciFakePCIBIOS;
1923	PciBusReg.pszSetIrqRC = fGCEnabled ? "ich9pciSetIrq" : NULL;
1924	PciBusReg.pszSetIrqR0 = fR0Enabled ? "ich9pciSetIrq" : NULL;
1925	rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBus->pPciHlpR3);
1926	if (RT_FAILURE(rc))
1927	return PDMDEV_SET_ERROR(pDevIns, rc,
1928	N_("Failed to register ourselves as a PCI Bus"));
1929	if (pBus->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
1930	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
1931	N_("PCI helper version mismatch; got %#x expected %#x"),
1932	pBus->pPciHlpR3->u32Version, PDM_PCIHLPR3_VERSION);
1933
1934	pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
1935	pBus->pPciHlpR0 = pBus->pPciHlpR3->pfnGetR0Helpers(pDevIns);
1936
1937	/*
1938	* Fill in PCI configs and add them to the bus.
1939	*/
1940
1941	/**
1942	* We emulate 82801IB ICH9 IO chip used in Q35,
1943	* see http://ark.intel.com/Product.aspx?id=31892
1944	*
1945	* Stepping S-Spec Top Marking
1946	*
1947	* A2 SLA9M NH82801IB
1948	*/
1949	PCIDevSetVendorId( &pBus->aPciDev, 0x8086); /* Intel */
1950	PCIDevSetDeviceId( &pBus->aPciDev, 0x244e); /* Desktop */
1951	PCIDevSetRevisionId(&pBus->aPciDev, 0x92); /* rev. A2 */
1952	PCIDevSetClassSub( &pBus->aPciDev, 0x00); /* Host/PCI bridge */
1953	PCIDevSetClassBase( &pBus->aPciDev, 0x06); /* bridge */
1954	PCIDevSetHeaderType(&pBus->aPciDev, 0x00); /* normal device */
1955
1956	pBus->aPciDev.pDevIns = pDevIns;
1957	/* We register Host<->PCI controller on the bus */
1958	ich9pciRegisterInternal(pBus, -1, &pBus->aPciDev, "i82801");
1959
1960	/*
1961	* Register I/O ports and save state.
1962	*/
1963	rc = PDMDevHlpIOPortRegister(pDevIns, 0x0cf8, 1, NULL, ich9pciIOPortAddressWrite, ich9pciIOPortAddressRead, NULL, NULL, "ICH9 (PCI)");
1964	if (RT_FAILURE(rc))
1965	return rc;
1966	rc = PDMDevHlpIOPortRegister(pDevIns, 0x0cfc, 4, NULL, ich9pciIOPortDataWrite, ich9pciIOPortDataRead, NULL, NULL, "ICH9 (PCI)");
1967	if (RT_FAILURE(rc))
1968	return rc;
1969	if (fGCEnabled)
1970	{
1971	rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x0cf8, 1, NIL_RTGCPTR, "ich9pciIOPortAddressWrite", "ich9pciIOPortAddressRead", NULL, NULL, "ICH9 (PCI)");
1972	if (RT_FAILURE(rc))
1973	return rc;
1974	rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x0cfc, 4, NIL_RTGCPTR, "ich9pciIOPortDataWrite", "ich9pciIOPortDataRead", NULL, NULL, "ICH9 (PCI)");
1975	if (RT_FAILURE(rc))
1976	return rc;
1977	}
1978	if (fR0Enabled)
1979	{
1980	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x0cf8, 1, NIL_RTR0PTR, "ich9pciIOPortAddressWrite", "ich9pciIOPortAddressRead", NULL, NULL, "ICH9 (PCI)");
1981	if (RT_FAILURE(rc))
1982	return rc;
1983	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x0cfc, 4, NIL_RTR0PTR, "ich9pciIOPortDataWrite", "ich9pciIOPortDataRead", NULL, NULL, "ICH9 (PCI)");
1984	if (RT_FAILURE(rc))
1985	return rc;
1986	}
1987
1988	if (pGlobals->u64PciConfigMMioAddress != 0)
1989	{
1990	rc = PDMDevHlpMMIORegister(pDevIns, pGlobals->u64PciConfigMMioAddress, pGlobals->u64PciConfigMMioLength, pGlobals,
1991	ich9pciMcfgMMIOWrite, ich9pciMcfgMMIORead, NULL, "MCFG ranges");
1992	if (RT_FAILURE(rc))
1993	{
1994	AssertMsgRC(rc, ("Cannot register MCFG MMIO: %Rrc\n", rc));
1995	return rc;
1996	}
1997
1998	if (fGCEnabled)
1999	{
2000
2001	rc = PDMDevHlpMMIORegisterRC(pDevIns,
2002	pGlobals->u64PciConfigMMioAddress,
2003	pGlobals->u64PciConfigMMioLength,
2004	0,
2005	"ich9pciMcfgMMIOWrite",
2006	"ich9pciMcfgMMIORead",
2007	NULL);
2008	if (RT_FAILURE(rc))
2009	{
2010	AssertMsgRC(rc, ("Cannot register MCFG MMIO (GC): %Rrc\n", rc));
2011	return rc;
2012	}
2013	}
2014
2015
2016	if (fR0Enabled)
2017	{
2018
2019	rc = PDMDevHlpMMIORegisterR0(pDevIns,
2020	pGlobals->u64PciConfigMMioAddress,
2021	pGlobals->u64PciConfigMMioLength,
2022	0,
2023	"ich9pciMcfgMMIOWrite",
2024	"ich9pciMcfgMMIORead",
2025	NULL);
2026	if (RT_FAILURE(rc))
2027	{
2028	AssertMsgRC(rc, ("Cannot register MCFG MMIO (R0): %Rrc\n", rc));
2029	return rc;
2030	}
2031	}
2032	}
2033
2034
2035	/** @todo: other chipset devices shall be registered too */
2036	/** @todo: what to with bridges? */
2037
2038	PDMDevHlpDBGFInfoRegister(pDevIns, "pci", "Display PCI bus status. (no arguments)", ich9pciInfo);
2039
2040	return VINF_SUCCESS;
2041	}
2042
2043	/**
2044	* @copydoc FNPDMDEVRELOCATE
2045	*/
2046	static DECLCALLBACK(void) ich9pciRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
2047	{
2048	PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
2049	PPCIBUS pBus = &pGlobals->aPciBus;
2050	pGlobals->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2051
2052	pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
2053	pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2054
2055	/* Relocate RC pointers for the attached pci devices. */
2056	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
2057	{
2058	if (pBus->apDevices[i])
2059	pBus->apDevices[i]->Int.s.pBusRC += offDelta;
2060	}
2061
2062	}
2063
2064	/**
2065	* @interface_method_impl{PDMDEVREG,pfnConstruct}
2066	*/
2067	static DECLCALLBACK(int) ich9pcibridgeConstruct(PPDMDEVINS pDevIns,
2068	int iInstance,
2069	PCFGMNODE pCfg)
2070	{
2071	int rc;
2072
2073	/*
2074	* Validate and read configuration.
2075	*/
2076	if (!CFGMR3AreValuesValid(pCfg, "GCEnabled\0" "R0Enabled\0"))
2077	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
2078
2079	/* check if RC code is enabled. */
2080	bool fGCEnabled;
2081	rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
2082	if (RT_FAILURE(rc))
2083	return PDMDEV_SET_ERROR(pDevIns, rc,
2084	N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
2085
2086	/* check if R0 code is enabled. */
2087	bool fR0Enabled;
2088	rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
2089	if (RT_FAILURE(rc))
2090	return PDMDEV_SET_ERROR(pDevIns, rc,
2091	N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
2092	Log(("PCI: fGCEnabled=%RTbool fR0Enabled=%RTbool\n", fGCEnabled, fR0Enabled));
2093
2094	return VINF_SUCCESS;
2095	}
2096
2097	/**
2098	* @copydoc FNPDMDEVRESET
2099	*/
2100	static DECLCALLBACK(void) ich9pcibridgeReset(PPDMDEVINS pDevIns)
2101	{
2102	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
2103
2104	/* Reset config space to default values. */
2105	pBus->aPciDev.config[VBOX_PCI_PRIMARY_BUS] = 0;
2106	pBus->aPciDev.config[VBOX_PCI_SECONDARY_BUS] = 0;
2107	pBus->aPciDev.config[VBOX_PCI_SUBORDINATE_BUS] = 0;
2108	}
2109
2110
2111	/**
2112	* @copydoc FNPDMDEVRELOCATE
2113	*/
2114	static DECLCALLBACK(void) ich9pcibridgeRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
2115	{
2116	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
2117	pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2118
2119	/* Relocate RC pointers for the attached pci devices. */
2120	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
2121	{
2122	if (pBus->apDevices[i])
2123	pBus->apDevices[i]->Int.s.pBusRC += offDelta;
2124	}
2125
2126	}
2127
2128	/**
2129	* The PCI bus device registration structure.
2130	*/
2131	const PDMDEVREG g_DevicePciIch9 =
2132	{
2133	/* u32Version */
2134	PDM_DEVREG_VERSION,
2135	/* szName */
2136	"ich9pci",
2137	/* szRCMod */
2138	"VBoxDDGC.gc",
2139	/* szR0Mod */
2140	"VBoxDDR0.r0",
2141	/* pszDescription */
2142	"ICH9 PCI bridge",
2143	/* fFlags */
2144	PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
2145	/* fClass */
2146	PDM_DEVREG_CLASS_BUS_PCI \| PDM_DEVREG_CLASS_BUS_ISA,
2147	/* cMaxInstances */
2148	1,
2149	/* cbInstance */
2150	sizeof(PCIGLOBALS),
2151	/* pfnConstruct */
2152	ich9pciConstruct,
2153	/* pfnDestruct */
2154	NULL,
2155	/* pfnRelocate */
2156	ich9pciRelocate,
2157	/* pfnIOCtl */
2158	NULL,
2159	/* pfnPowerOn */
2160	NULL,
2161	/* pfnReset */
2162	NULL,
2163	/* pfnSuspend */
2164	NULL,
2165	/* pfnResume */
2166	NULL,
2167	/* pfnAttach */
2168	NULL,
2169	/* pfnDetach */
2170	NULL,
2171	/* pfnQueryInterface */
2172	NULL,
2173	/* pfnInitComplete */
2174	NULL,
2175	/* pfnPowerOff */
2176	NULL,
2177	/* pfnSoftReset */
2178	NULL,
2179	/* u32VersionEnd */
2180	PDM_DEVREG_VERSION
2181	};
2182
2183	/**
2184	* The device registration structure
2185	* for the PCI-to-PCI bridge.
2186	*/
2187	const PDMDEVREG g_DevicePciIch9Bridge =
2188	{
2189	/* u32Version */
2190	PDM_DEVREG_VERSION,
2191	/* szName */
2192	"ich9pcibridge",
2193	/* szRCMod */
2194	"VBoxDDGC.gc",
2195	/* szR0Mod */
2196	"VBoxDDR0.r0",
2197	/* pszDescription */
2198	"ICH9 PCI to PCI bridge",
2199	/* fFlags */
2200	PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
2201	/* fClass */
2202	PDM_DEVREG_CLASS_BUS_PCI,
2203	/* cMaxInstances */
2204	~0,
2205	/* cbInstance */
2206	sizeof(PCIBUS),
2207	/* pfnConstruct */
2208	ich9pcibridgeConstruct,
2209	/* pfnDestruct */
2210	NULL,
2211	/* pfnRelocate */
2212	ich9pcibridgeRelocate,
2213	/* pfnIOCtl */
2214	NULL,
2215	/* pfnPowerOn */
2216	NULL,
2217	/* pfnReset */
2218	ich9pcibridgeReset,
2219	/* pfnSuspend */
2220	NULL,
2221	/* pfnResume */
2222	NULL,
2223	/* pfnAttach */
2224	NULL,
2225	/* pfnDetach */
2226	NULL,
2227	/* pfnQueryInterface */
2228	NULL,
2229	/* pfnInitComplete */
2230	NULL,
2231	/* pfnPowerOff */
2232	NULL,
2233	/* pfnSoftReset */
2234	NULL,
2235	/* u32VersionEnd */
2236	PDM_DEVREG_VERSION
2237	};
2238
2239	#endif /* IN_RING3 */
2240	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */

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source: vbox/trunk/src/VBox/Devices/Bus/DevPciIch9.cpp@ 32765

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