DevPciIch9.cpp@ 33203

Last change on this file since 33203 was 33203, checked in by vboxsync, 14 years ago
PCI: tight packing of builting devices into functions, chipset slot assignment has higher priority than device now
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1	/* $Id: DevPciIch9.cpp 33203 2010-10-18 14:55:53Z vboxsync $ */
2	/** @file
3	* DevPCI - ICH9 southbridge PCI bus emulation Device.
4	*/
5
6	/*
7	* Copyright (C) 2010 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/*******************************************************************************
19	* Header Files *
20	*******************************************************************************/
21	#define LOG_GROUP LOG_GROUP_DEV_PCI
22	/* Hack to get PCIDEVICEINT declare at the right point - include "PCIInternal.h". */
23	#define PCI_INCLUDE_PRIVATE
24	#include <VBox/pci.h>
25	#include <VBox/msi.h>
26	#include <VBox/pdmdev.h>
27	#include <iprt/asm.h>
28	#include <iprt/assert.h>
29	#include <iprt/string.h>
30
31	#include "../Builtins.h"
32
33	#include "MsiCommon.h"
34
35	/**
36	* PCI Bus instance.
37	*/
38	typedef struct PCIBus
39	{
40	/** Bus number. */
41	int32_t iBus;
42	/** Number of bridges attached to the bus. */
43	uint32_t cBridges;
44
45	/** Array of PCI devices. We assume 32 slots, each with 8 functions. */
46	R3PTRTYPE(PPCIDEVICE) apDevices[256];
47	/** Array of bridges attached to the bus. */
48	R3PTRTYPE(PPCIDEVICE *) papBridgesR3;
49
50	/** R3 pointer to the device instance. */
51	PPDMDEVINSR3 pDevInsR3;
52	/** Pointer to the PCI R3 helpers. */
53	PCPDMPCIHLPR3 pPciHlpR3;
54
55	/** R0 pointer to the device instance. */
56	PPDMDEVINSR0 pDevInsR0;
57	/** Pointer to the PCI R0 helpers. */
58	PCPDMPCIHLPR0 pPciHlpR0;
59
60	/** RC pointer to the device instance. */
61	PPDMDEVINSRC pDevInsRC;
62	/** Pointer to the PCI RC helpers. */
63	PCPDMPCIHLPRC pPciHlpRC;
64
65	/** The PCI device for the PCI bridge. */
66	PCIDEVICE aPciDev;
67
68	} PCIBUS, *PPCIBUS;
69
70
71	/** @def PCI_APIC_IRQ_PINS
72	* Number of pins for interrupts if the APIC is used.
73	*/
74	#define PCI_APIC_IRQ_PINS 8
75
76	/**
77	* PCI Globals - This is the host-to-pci bridge and the root bus.
78	*/
79	typedef struct
80	{
81	/** R3 pointer to the device instance. */
82	PPDMDEVINSR3 pDevInsR3;
83	/** R0 pointer to the device instance. */
84	PPDMDEVINSR0 pDevInsR0;
85	/** RC pointer to the device instance. */
86	PPDMDEVINSRC pDevInsRC;
87
88	#if HC_ARCH_BITS == 64
89	uint32_t Alignment0;
90	#endif
91
92	/** I/O APIC irq levels */
93	volatile uint32_t uaPciApicIrqLevels[PCI_APIC_IRQ_PINS];
94
95	#if 1 /* Will be moved into the BIOS soon. */
96	/** The next I/O port address which the PCI BIOS will use. */
97	uint32_t uPciBiosIo;
98	/** The next MMIO address which the PCI BIOS will use. */
99	uint32_t uPciBiosMmio;
100	/** Actual bus number. */
101	uint8_t uBus;
102	#endif
103	/* Physical address of PCI config space MMIO region */
104	uint64_t u64PciConfigMMioAddress;
105	/* Length of PCI config space MMIO region */
106	uint64_t u64PciConfigMMioLength;
107
108
109	/** Config register. */
110	uint32_t uConfigReg;
111
112	/** PCI bus which is attached to the host-to-PCI bridge. */
113	PCIBUS aPciBus;
114
115	} PCIGLOBALS, *PPCIGLOBALS;
116
117
118	typedef struct {
119	uint8_t iBus;
120	uint8_t iDeviceFunc;
121	uint16_t iRegister;
122	} PciAddress;
123
124	/*******************************************************************************
125	* Defined Constants And Macros *
126	*******************************************************************************/
127
128	/** @def VBOX_ICH9PCI_SAVED_STATE_VERSION
129	* Saved state version of the ICH9 PCI bus device.
130	*/
131	#define VBOX_ICH9PCI_SAVED_STATE_VERSION_NOMSI 1
132	#define VBOX_ICH9PCI_SAVED_STATE_VERSION_MSI 2
133	#define VBOX_ICH9PCI_SAVED_STATE_VERSION_CURRENT VBOX_ICH9PCI_SAVED_STATE_VERSION_MSI
134
135	/** Converts a bus instance pointer to a device instance pointer. */
136	#define PCIBUS_2_DEVINS(pPciBus) ((pPciBus)->CTX_SUFF(pDevIns))
137	/** Converts a device instance pointer to a PCIGLOBALS pointer. */
138	#define DEVINS_2_PCIGLOBALS(pDevIns) ((PPCIGLOBALS)(PDMINS_2_DATA(pDevIns, PPCIGLOBALS)))
139	/** Converts a device instance pointer to a PCIBUS pointer. */
140	#define DEVINS_2_PCIBUS(pDevIns) ((PPCIBUS)(&PDMINS_2_DATA(pDevIns, PPCIGLOBALS)->aPciBus))
141	/** Converts a pointer to a PCI root bus instance to a PCIGLOBALS pointer.
142	*/
143	#define PCIROOTBUS_2_PCIGLOBALS(pPciBus) ( (PPCIGLOBALS)((uintptr_t)(pPciBus) - RT_OFFSETOF(PCIGLOBALS, aPciBus)) )
144
145
146	/** @def PCI_LOCK
147	* Acquires the PDM lock. This is a NOP if locking is disabled. */
148	/** @def PCI_UNLOCK
149	* Releases the PDM lock. This is a NOP if locking is disabled. */
150	#define PCI_LOCK(pDevIns, rc) \
151	do { \
152	int rc2 = DEVINS_2_PCIBUS(pDevIns)->CTX_SUFF(pPciHlp)->pfnLock((pDevIns), rc); \
153	if (rc2 != VINF_SUCCESS) \
154	return rc2; \
155	} while (0)
156	#define PCI_UNLOCK(pDevIns) \
157	DEVINS_2_PCIBUS(pDevIns)->CTX_SUFF(pPciHlp)->pfnUnlock(pDevIns)
158
159	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
160
161	RT_C_DECLS_BEGIN
162
163	PDMBOTHCBDECL(void) ich9pciSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel);
164	PDMBOTHCBDECL(void) ich9pcibridgeSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel);
165	PDMBOTHCBDECL(int) ich9pciIOPortAddressWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
166	PDMBOTHCBDECL(int) ich9pciIOPortAddressRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb);
167	PDMBOTHCBDECL(int) ich9pciIOPortDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
168	PDMBOTHCBDECL(int) ich9pciIOPortDataRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb);
169	PDMBOTHCBDECL(int) ich9pciMcfgMMIOWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb);
170	PDMBOTHCBDECL(int) ich9pciMcfgMMIORead (PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb);
171
172	RT_C_DECLS_END
173
174	/* Prototypes */
175	static void ich9pciSetIrqInternal(PPCIGLOBALS pGlobals, uint8_t uDevFn, PPCIDEVICE pPciDev, int iIrq, int iLevel);
176	#ifdef IN_RING3
177	static int ich9pciRegisterInternal(PPCIBUS pBus, int iDev, PPCIDEVICE pPciDev, const char *pszName);
178	static void ich9pciUpdateMappings(PCIDevice *pDev);
179	static DECLCALLBACK(uint32_t) ich9pciConfigReadDev(PCIDevice *aDev, uint32_t u32Address, unsigned len);
180	DECLINLINE(PPCIDEVICE) ich9pciFindBridge(PPCIBUS pBus, uint8_t iBus);
181	static void ich9pciBiosInitDevice(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint8_t cBridgeDepth, uint8_t *paBridgePositions);
182	#endif
183
184	// See 7.2.2. PCI Express Enhanced Configuration Mechanism for details of address
185	// mapping, we take n=6 approach
186	DECLINLINE(void) ich9pciPhysToPciAddr(PPCIGLOBALS pGlobals, RTGCPHYS GCPhysAddr, PciAddress* pPciAddr)
187	{
188	GCPhysAddr = GCPhysAddr - pGlobals->u64PciConfigMMioAddress;
189	pPciAddr->iBus = (GCPhysAddr >> 20) & ((1<<8) - 1);
190	pPciAddr->iDeviceFunc = (GCPhysAddr >> 12) & ((1<<(5+3)) - 1); // 5 bits - device, 3 bits - function
191	pPciAddr->iRegister = (GCPhysAddr >> 0) & ((1<<(6+4+2)) - 1); // 6 bits - register, 4 bits - extended register, 2 bits -Byte Enable
192	}
193
194	DECLINLINE(void) ich9pciStateToPciAddr(PPCIGLOBALS pGlobals, RTGCPHYS addr, PciAddress* pPciAddr)
195	{
196	pPciAddr->iBus = (pGlobals->uConfigReg >> 16) & 0xff;
197	pPciAddr->iDeviceFunc = (pGlobals->uConfigReg >> 8) & 0xff;
198	pPciAddr->iRegister = (pGlobals->uConfigReg & 0xfc) \| (addr & 3);
199	}
200
201	PDMBOTHCBDECL(void) ich9pciSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel)
202	{
203	ich9pciSetIrqInternal(PDMINS_2_DATA(pDevIns, PPCIGLOBALS), pPciDev->devfn, pPciDev, iIrq, iLevel);
204	}
205
206	PDMBOTHCBDECL(void) ich9pcibridgeSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel)
207	{
208	/*
209	* The PCI-to-PCI bridge specification defines how the interrupt pins
210	* are routed from the secondary to the primary bus (see chapter 9).
211	* iIrq gives the interrupt pin the pci device asserted.
212	* We change iIrq here according to the spec and call the SetIrq function
213	* of our parent passing the device which asserted the interrupt instead of the device of the bridge.
214	*/
215	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
216	PPCIDEVICE pPciDevBus = pPciDev;
217	int iIrqPinBridge = iIrq;
218	uint8_t uDevFnBridge = 0;
219
220	/* Walk the chain until we reach the host bus. */
221	do
222	{
223	uDevFnBridge = pBus->aPciDev.devfn;
224	iIrqPinBridge = ((pPciDevBus->devfn >> 3) + iIrqPinBridge) & 3;
225
226	/* Get the parent. */
227	pBus = pBus->aPciDev.Int.s.CTX_SUFF(pBus);
228	pPciDevBus = &pBus->aPciDev;
229	} while (pBus->iBus != 0);
230
231	AssertMsgReturnVoid(pBus->iBus == 0, ("This is not the host pci bus iBus=%d\n", pBus->iBus));
232	ich9pciSetIrqInternal(PCIROOTBUS_2_PCIGLOBALS(pBus), uDevFnBridge, pPciDev, iIrqPinBridge, iLevel);
233	}
234
235	/**
236	* Port I/O Handler for PCI address OUT operations.
237	*
238	* @returns VBox status code.
239	*
240	* @param pDevIns The device instance.
241	* @param pvUser User argument - ignored.
242	* @param uPort Port number used for the OUT operation.
243	* @param u32 The value to output.
244	* @param cb The value size in bytes.
245	*/
246	PDMBOTHCBDECL(int) ich9pciIOPortAddressWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
247	{
248	Log(("ich9pciIOPortAddressWrite: Port=%#x u32=%#x cb=%d\n", Port, u32, cb));
249	NOREF(pvUser);
250	if (cb == 4)
251	{
252	PPCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
253	PCI_LOCK(pDevIns, VINF_IOM_HC_IOPORT_WRITE);
254	pThis->uConfigReg = u32 & ~3; /* Bits 0-1 are reserved and we silently clear them */
255	PCI_UNLOCK(pDevIns);
256	}
257	return VINF_SUCCESS;
258	}
259
260	/**
261	* Port I/O Handler for PCI address IN operations.
262	*
263	* @returns VBox status code.
264	*
265	* @param pDevIns The device instance.
266	* @param pvUser User argument - ignored.
267	* @param uPort Port number used for the IN operation.
268	* @param pu32 Where to store the result.
269	* @param cb Number of bytes read.
270	*/
271	PDMBOTHCBDECL(int) ich9pciIOPortAddressRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
272	{
273	NOREF(pvUser);
274	if (cb == 4)
275	{
276	PPCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
277	PCI_LOCK(pDevIns, VINF_IOM_HC_IOPORT_READ);
278	*pu32 = pThis->uConfigReg;
279	PCI_UNLOCK(pDevIns);
280	Log(("pciIOPortAddressRead: Port=%#x cb=%d -> %#x\n", Port, cb, *pu32));
281	return VINF_SUCCESS;
282	}
283
284	Log(("ich9pciIOPortAddressRead: Port=%#x cb=%d VERR_IOM_IOPORT_UNUSED\n", Port, cb));
285
286	return VERR_IOM_IOPORT_UNUSED;
287	}
288
289	static int ich9pciDataWriteAddr(PPCIGLOBALS pGlobals, PciAddress* pAddr, uint32_t val, int len)
290	{
291
292	if (pAddr->iRegister > 0xff)
293	{
294	LogRel(("PCI: attempt to write extended register: %x (%d) <- val\n", pAddr->iRegister, len, val));
295	return 0;
296	}
297
298	if (pAddr->iBus != 0)
299	{
300	if (pGlobals->aPciBus.cBridges)
301	{
302	#ifdef IN_RING3 /** @todo do lookup in R0/RC too! */
303	PPCIDEVICE pBridgeDevice = ich9pciFindBridge(&pGlobals->aPciBus, pAddr->iBus);
304	if (pBridgeDevice)
305	{
306	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigWrite);
307	pBridgeDevice->Int.s.pfnBridgeConfigWrite(pBridgeDevice->pDevIns, pAddr->iBus, pAddr->iDeviceFunc, pAddr->iRegister, val, len);
308	}
309	#else
310	return VINF_IOM_HC_IOPORT_WRITE;
311	#endif
312	}
313	}
314	else
315	{
316	if (pGlobals->aPciBus.apDevices[pAddr->iDeviceFunc])
317	{
318	#ifdef IN_RING3
319	R3PTRTYPE(PCIDevice *) aDev = pGlobals->aPciBus.apDevices[pAddr->iDeviceFunc];
320	Log(("ich9pciConfigWrite: %s: addr=%02x val=%08x len=%d\n", aDev->name, pAddr->iRegister, val, len));
321	aDev->Int.s.pfnConfigWrite(aDev, pAddr->iRegister, val, len);
322	#else
323	return VINF_IOM_HC_IOPORT_WRITE;
324	#endif
325	}
326	}
327	return VINF_SUCCESS;
328	}
329
330	static int ich9pciDataWrite(PPCIGLOBALS pGlobals, uint32_t addr, uint32_t val, int len)
331	{
332	PciAddress aPciAddr;
333
334	Log(("ich9pciDataWrite: addr=%08x val=%08x len=%d\n", pGlobals->uConfigReg, val, len));
335
336	if (!(pGlobals->uConfigReg & (1 << 31)))
337	return VINF_SUCCESS;
338
339	if ((pGlobals->uConfigReg & 0x3) != 0)
340	return VINF_SUCCESS;
341
342	/* Compute destination device */
343	ich9pciStateToPciAddr(pGlobals, addr, &aPciAddr);
344
345	return ich9pciDataWriteAddr(pGlobals, &aPciAddr, val, len);
346	}
347
348	/**
349	* Port I/O Handler for PCI data OUT operations.
350	*
351	* @returns VBox status code.
352	*
353	* @param pDevIns The device instance.
354	* @param pvUser User argument - ignored.
355	* @param uPort Port number used for the OUT operation.
356	* @param u32 The value to output.
357	* @param cb The value size in bytes.
358	*/
359	PDMBOTHCBDECL(int) ich9pciIOPortDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
360	{
361	Log(("pciIOPortDataWrite: Port=%#x u32=%#x cb=%d\n", Port, u32, cb));
362	NOREF(pvUser);
363	int rc = VINF_SUCCESS;
364	if (!(Port % cb))
365	{
366	PCI_LOCK(pDevIns, VINF_IOM_HC_IOPORT_WRITE);
367	rc = ich9pciDataWrite(PDMINS_2_DATA(pDevIns, PPCIGLOBALS), Port, u32, cb);
368	PCI_UNLOCK(pDevIns);
369	}
370	else
371	AssertMsgFailed(("Unaligned write to port %#x u32=%#x cb=%d\n", Port, u32, cb));
372	return rc;
373	}
374
375	static int ich9pciDataReadAddr(PPCIGLOBALS pGlobals, PciAddress* pPciAddr, int len, uint32_t *pu32)
376	{
377	if (pPciAddr->iRegister > 0xff)
378	{
379	LogRel(("PCI: attempt to read extended register: %x\n", pPciAddr->iRegister));
380	*pu32 = 0;
381	return 0;
382	}
383
384
385	if (pPciAddr->iBus != 0)
386	{
387	if (pGlobals->aPciBus.cBridges)
388	{
389	#ifdef IN_RING3 /** @todo do lookup in R0/RC too! */
390	PPCIDEVICE pBridgeDevice = ich9pciFindBridge(&pGlobals->aPciBus, pPciAddr->iBus);
391	if (pBridgeDevice)
392	{
393	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigRead);
394	*pu32 = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->pDevIns, pPciAddr->iBus, pPciAddr->iDeviceFunc, pPciAddr->iRegister, len);
395	}
396	#else
397	return VINF_IOM_HC_IOPORT_READ;
398	#endif
399	}
400	}
401	else
402	{
403	if (pGlobals->aPciBus.apDevices[pPciAddr->iDeviceFunc])
404	{
405	#ifdef IN_RING3
406	R3PTRTYPE(PCIDevice *) aDev = pGlobals->aPciBus.apDevices[pPciAddr->iDeviceFunc];
407	*pu32 = aDev->Int.s.pfnConfigRead(aDev, pPciAddr->iRegister, len);
408	Log(("ich9pciDataReadAddr: %s: addr=%02x val=%08x len=%d\n", aDev->name, pPciAddr->iRegister, *pu32, len));
409	#else
410	return VINF_IOM_HC_IOPORT_READ;
411	#endif
412	}
413	}
414
415	return VINF_SUCCESS;
416	}
417
418	static int ich9pciDataRead(PPCIGLOBALS pGlobals, uint32_t addr, int len, uint32_t *pu32)
419	{
420	PciAddress aPciAddr;
421
422	*pu32 = 0xffffffff;
423
424	if (!(pGlobals->uConfigReg & (1 << 31)))
425	return VINF_SUCCESS;
426
427	if ((pGlobals->uConfigReg & 0x3) != 0)
428	return VINF_SUCCESS;
429
430	/* Compute destination device */
431	ich9pciStateToPciAddr(pGlobals, addr, &aPciAddr);
432
433	return ich9pciDataReadAddr(pGlobals, &aPciAddr, len, pu32);
434	}
435
436	/**
437	* Port I/O Handler for PCI data IN operations.
438	*
439	* @returns VBox status code.
440	*
441	* @param pDevIns The device instance.
442	* @param pvUser User argument - ignored.
443	* @param uPort Port number used for the IN operation.
444	* @param pu32 Where to store the result.
445	* @param cb Number of bytes read.
446	*/
447	PDMBOTHCBDECL(int) ich9pciIOPortDataRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
448	{
449	NOREF(pvUser);
450	if (!(Port % cb))
451	{
452	PCI_LOCK(pDevIns, VINF_IOM_HC_IOPORT_READ);
453	int rc = ich9pciDataRead(PDMINS_2_DATA(pDevIns, PPCIGLOBALS), Port, cb, pu32);
454	PCI_UNLOCK(pDevIns);
455	Log(("pciIOPortDataRead: Port=%#x cb=%#x -> %#x (%Rrc)\n", Port, cb, *pu32, rc));
456	return rc;
457	}
458	AssertMsgFailed(("Unaligned read from port %#x cb=%d\n", Port, cb));
459	return VERR_IOM_IOPORT_UNUSED;
460	}
461
462	/* Compute mapping of PCI slot and IRQ number to APIC interrupt line */
463	DECLINLINE(int) ich9pciSlot2ApicIrq(uint8_t uSlot, int irq_num)
464	{
465	return (irq_num + uSlot) & 7;
466	}
467
468	/* Add one more level up request on APIC input line */
469	DECLINLINE(void) ich9pciApicLevelUp(PPCIGLOBALS pGlobals, int irq_num)
470	{
471	ASMAtomicIncU32(&pGlobals->uaPciApicIrqLevels[irq_num]);
472	}
473
474	/* Remove one level up request on APIC input line */
475	DECLINLINE(void) ich9pciApicLevelDown(PPCIGLOBALS pGlobals, int irq_num)
476	{
477	ASMAtomicDecU32(&pGlobals->uaPciApicIrqLevels[irq_num]);
478	}
479
480	static void ich9pciApicSetIrq(PPCIBUS pBus, uint8_t uDevFn, PCIDevice *pPciDev, int irq_num1, int iLevel, int iForcedIrq)
481	{
482	/* This is only allowed to be called with a pointer to the root bus. */
483	AssertMsg(pBus->iBus == 0, ("iBus=%u\n", pBus->iBus));
484
485	if (iForcedIrq == -1)
486	{
487	int apic_irq, apic_level;
488	PPCIGLOBALS pGlobals = PCIROOTBUS_2_PCIGLOBALS(pBus);
489	int irq_num = ich9pciSlot2ApicIrq(uDevFn >> 3, irq_num1);
490
491	if ((iLevel & PDM_IRQ_LEVEL_HIGH) == PDM_IRQ_LEVEL_HIGH)
492	ich9pciApicLevelUp(pGlobals, irq_num);
493	else if ((iLevel & PDM_IRQ_LEVEL_HIGH) == PDM_IRQ_LEVEL_LOW)
494	ich9pciApicLevelDown(pGlobals, irq_num);
495
496	apic_irq = irq_num + 0x10;
497	apic_level = pGlobals->uaPciApicIrqLevels[irq_num] != 0;
498	Log3(("ich9pciApicSetIrq: %s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d\n",
499	R3STRING(pPciDev->name), irq_num1, iLevel, apic_irq, apic_level, irq_num));
500	pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), apic_irq, apic_level);
501
502	if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP)
503	{
504	/**
505	* we raised it few lines above, as PDM_IRQ_LEVEL_FLIP_FLOP has
506	* PDM_IRQ_LEVEL_HIGH bit set
507	*/
508	ich9pciApicLevelDown(pGlobals, irq_num);
509	pPciDev->Int.s.uIrqPinState = PDM_IRQ_LEVEL_LOW;
510	apic_level = pGlobals->uaPciApicIrqLevels[irq_num] != 0;
511	Log3(("ich9pciApicSetIrq: %s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d (flop)\n",
512	R3STRING(pPciDev->name), irq_num1, iLevel, apic_irq, apic_level, irq_num));
513	pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), apic_irq, apic_level);
514	}
515	} else {
516	Log3(("ich9pciApicSetIrq: %s: irq_num1=%d level=%d acpi_irq=%d\n",
517	R3STRING(pPciDev->name), irq_num1, iLevel, iForcedIrq));
518	pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), iForcedIrq, iLevel);
519	}
520	}
521
522	static void ich9pciSetIrqInternal(PPCIGLOBALS pGlobals, uint8_t uDevFn, PPCIDEVICE pPciDev, int iIrq, int iLevel)
523	{
524
525	if (PCIDevIsIntxDisabled(pPciDev))
526	{
527	if (MsiIsEnabled(pPciDev))
528	{
529	Log2(("Raise a MSI interrupt: %d\n", iIrq));
530	/* We only trigger MSI on level up, as technically it's matching flip-flop best (maybe even assert that level == PDM_IRQ_LEVEL_FLIP_FLOP) */
531	if ((iLevel & PDM_IRQ_LEVEL_HIGH) != 0)
532	{
533	PPDMDEVINS pDevIns = pGlobals->aPciBus.CTX_SUFF(pDevIns);
534	MsiNotify(pDevIns, pGlobals->aPciBus.CTX_SUFF(pPciHlp), pPciDev, iIrq);
535	}
536	}
537	return;
538	}
539
540	PPCIBUS pBus = &pGlobals->aPciBus;
541	const bool fIsAcpiDevice = PCIDevGetDeviceId(pPciDev) == 0x7113;
542
543	/* Check if the state changed. */
544	if (pPciDev->Int.s.uIrqPinState != iLevel)
545	{
546	pPciDev->Int.s.uIrqPinState = (iLevel & PDM_IRQ_LEVEL_HIGH);
547
548	/* Send interrupt to I/O APIC only now. */
549	if (fIsAcpiDevice)
550	/*
551	* ACPI needs special treatment since SCI is hardwired and
552	* should not be affected by PCI IRQ routing tables at the
553	* same time SCI IRQ is shared in PCI sense hence this
554	* kludge (i.e. we fetch the hardwired value from ACPIs
555	* PCI device configuration space).
556	*/
557	ich9pciApicSetIrq(pBus, uDevFn, pPciDev, -1, iLevel, PCIDevGetInterruptLine(pPciDev));
558	else
559	ich9pciApicSetIrq(pBus, uDevFn, pPciDev, iIrq, iLevel, -1);
560	}
561	}
562
563	PDMBOTHCBDECL(int) ich9pciMcfgMMIOWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb)
564	{
565	PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
566	PciAddress aDest;
567	uint32_t u32 = 0;
568
569	Log2(("ich9pciMcfgMMIOWrite: %p(%d) \n", GCPhysAddr, cb));
570
571	PCI_LOCK(pDevIns, VINF_IOM_HC_IOPORT_WRITE);
572
573	ich9pciPhysToPciAddr(pGlobals, GCPhysAddr, &aDest);
574
575	switch (cb)
576	{
577	case 1:
578	u32 = (uint8_t)pv;
579	break;
580	case 2:
581	u32 = (uint16_t)pv;
582	break;
583	case 4:
584	u32 = (uint32_t)pv;
585	break;
586	default:
587	Assert(false);
588	break;
589	}
590	int rc = ich9pciDataWriteAddr(pGlobals, &aDest, u32, cb);
591	PCI_UNLOCK(pDevIns);
592
593	return rc;
594	}
595
596	PDMBOTHCBDECL(int) ich9pciMcfgMMIORead (PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb)
597	{
598	PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
599	PciAddress aDest;
600	uint32_t rv = 0xffffffff;
601
602	Log2(("ich9pciMcfgMMIORead: %p(%d) \n", GCPhysAddr, cb));
603
604	PCI_LOCK(pDevIns, VINF_IOM_HC_IOPORT_READ);
605
606	ich9pciPhysToPciAddr(pGlobals, GCPhysAddr, &aDest);
607
608	int rc = ich9pciDataReadAddr(pGlobals, &aDest, cb, &rv);
609
610	switch (cb)
611	{
612	case 1:
613	(uint8_t)pv = (uint8_t)rv;
614	break;
615	case 2:
616	(uint16_t)pv = (uint16_t)rv;
617	break;
618	case 4:
619	(uint32_t)pv = (uint32_t)rv;
620	break;
621	default:
622	Assert(false);
623	break;
624	}
625	PCI_UNLOCK(pDevIns);
626
627	return rc;
628	}
629
630	#ifdef IN_RING3
631
632	DECLINLINE(PPCIDEVICE) ich9pciFindBridge(PPCIBUS pBus, uint8_t iBus)
633	{
634	/* Search for a fitting bridge. */
635	for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
636	{
637	/*
638	* Examine secondary and subordinate bus number.
639	* If the target bus is in the range we pass the request on to the bridge.
640	*/
641	PPCIDEVICE pBridgeTemp = pBus->papBridgesR3[iBridge];
642	AssertMsg(pBridgeTemp && PCIIsPci2PciBridge(pBridgeTemp),
643	("Device is not a PCI bridge but on the list of PCI bridges\n"));
644
645	if ( iBus >= PCIDevGetByte(pBridgeTemp, VBOX_PCI_SECONDARY_BUS)
646	&& iBus <= PCIDevGetByte(pBridgeTemp, VBOX_PCI_SUBORDINATE_BUS))
647	return pBridgeTemp;
648	}
649
650	/* Nothing found. */
651	return NULL;
652	}
653
654	DECLINLINE(uint32_t) ich9pciGetRegionReg(int iRegion)
655	{
656	return (iRegion == PCI_ROM_SLOT) ?
657	VBOX_PCI_ROM_ADDRESS : (VBOX_PCI_BASE_ADDRESS_0 + iRegion * 4);
658	}
659
660	#define INVALID_PCI_ADDRESS ~0U
661
662	static void ich9pciUpdateMappings(PCIDevice* pDev)
663	{
664	PPCIBUS pBus = pDev->Int.s.CTX_SUFF(pBus);
665	uint32_t uLast, uNew;
666
667	int iCmd = PCIDevGetCommand(pDev);
668	for (int iRegion = 0; iRegion < PCI_NUM_REGIONS; iRegion++)
669	{
670	PCIIORegion* pRegion = &pDev->Int.s.aIORegions[iRegion];
671	uint32_t uConfigReg = ich9pciGetRegionReg(iRegion);
672	int32_t iRegionSize = pRegion->size;
673	int rc;
674
675	if (iRegionSize == 0)
676	continue;
677
678	if (pRegion->type & PCI_ADDRESS_SPACE_IO)
679	{
680	/* port IO region */
681	if (iCmd & PCI_COMMAND_IOACCESS)
682	{
683	/* IO access allowed */
684	uNew = ich9pciConfigReadDev(pDev, uConfigReg, 4);
685	uNew &= ~(iRegionSize - 1);
686	uLast = uNew + iRegionSize - 1;
687	/* only 64K ioports on PC */
688	if (uLast <= uNew \|\| uNew == 0 \|\| uLast >= 0x10000)
689	uNew = INVALID_PCI_ADDRESS;
690	} else
691	uNew = INVALID_PCI_ADDRESS;
692	}
693	else
694	{
695	/* MMIO region */
696	if (iCmd & PCI_COMMAND_MEMACCESS)
697	{
698	uNew = ich9pciConfigReadDev(pDev, uConfigReg, 4);
699	/* the ROM slot has a specific enable bit */
700	if (iRegion == PCI_ROM_SLOT && !(uNew & 1))
701	uNew = INVALID_PCI_ADDRESS;
702	else
703	{
704	uNew &= ~(iRegionSize - 1);
705	uLast = uNew + iRegionSize - 1;
706	/* NOTE: we do not support wrapping */
707	/* XXX: as we cannot support really dynamic
708	mappings, we handle specific values as invalid
709	mappings. */
710	if (uLast <= uNew \|\| uNew == 0 \|\| uLast == INVALID_PCI_ADDRESS)
711	uNew = INVALID_PCI_ADDRESS;
712	}
713	} else
714	uNew = INVALID_PCI_ADDRESS;
715	}
716	/* now do the real mapping */
717	if (uNew != pRegion->addr)
718	{
719	if (pRegion->addr != INVALID_PCI_ADDRESS)
720	{
721	if (pRegion->type & PCI_ADDRESS_SPACE_IO)
722	{
723	/* Port IO */
724	rc = PDMDevHlpIOPortDeregister(pDev->pDevIns, pRegion->addr, pRegion->size);
725	AssertRC(rc);
726	}
727	else
728	{
729	RTGCPHYS GCPhysBase = pRegion->addr;
730	if (pBus->pPciHlpR3->pfnIsMMIO2Base(pBus->pDevInsR3, pDev->pDevIns, GCPhysBase))
731	{
732	/* unmap it. */
733	rc = pRegion->map_func(pDev, iRegion, NIL_RTGCPHYS, pRegion->size, (PCIADDRESSSPACE)(pRegion->type));
734	AssertRC(rc);
735	rc = PDMDevHlpMMIO2Unmap(pDev->pDevIns, iRegion, GCPhysBase);
736	}
737	else
738	rc = PDMDevHlpMMIODeregister(pDev->pDevIns, GCPhysBase, pRegion->size);
739	AssertMsgRC(rc, ("rc=%Rrc d=%s i=%d GCPhysBase=%RGp size=%#x\n", rc, pDev->name, iRegion, GCPhysBase, pRegion->size));
740	}
741	}
742	pRegion->addr = uNew;
743	if (pRegion->addr != INVALID_PCI_ADDRESS)
744	{
745	/* finally, map the region */
746	rc = pRegion->map_func(pDev, iRegion,
747	pRegion->addr, pRegion->size,
748	(PCIADDRESSSPACE)(pRegion->type));
749	AssertRC(rc);
750	}
751	}
752	}
753	}
754
755	static DECLCALLBACK(int) ich9pciRegister(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, const char *pszName, int iDev)
756	{
757	PPCIBUS pBus = DEVINS_2_PCIBUS(pDevIns);
758
759	/*
760	* Check input.
761	*/
762	if ( !pszName
763	\|\| !pPciDev
764	\|\| iDev >= (int)RT_ELEMENTS(pBus->apDevices)
765	)
766	{
767	AssertMsgFailed(("Invalid argument! pszName=%s pPciDev=%p iDev=%d\n", pszName, pPciDev, iDev));
768	return VERR_INVALID_PARAMETER;
769	}
770
771	/*
772	* Register the device.
773	*/
774	return ich9pciRegisterInternal(pBus, iDev, pPciDev, pszName);
775	}
776
777
778	static DECLCALLBACK(int) ich9pciRegisterMsi(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PPDMMSIREG pMsiReg)
779	{
780	return MsiInit(pPciDev, pMsiReg);
781	}
782
783
784	static DECLCALLBACK(int) ich9pcibridgeRegister(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, const char *pszName, int iDev)
785	{
786
787	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
788
789	/*
790	* Check input.
791	*/
792	if ( !pszName
793	\|\| !pPciDev
794	\|\| iDev >= (int)RT_ELEMENTS(pBus->apDevices))
795	{
796	AssertMsgFailed(("Invalid argument! pszName=%s pPciDev=%p iDev=%d\n", pszName, pPciDev, iDev));
797	return VERR_INVALID_PARAMETER;
798	}
799
800	/*
801	* Register the device.
802	*/
803	return ich9pciRegisterInternal(pBus, iDev, pPciDev, pszName);
804	}
805
806	static DECLCALLBACK(int) ich9pciIORegionRegister(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iRegion, uint32_t cbRegion, PCIADDRESSSPACE enmType, PFNPCIIOREGIONMAP pfnCallback)
807	{
808	/*
809	* Validate.
810	*/
811	AssertMsgReturn( enmType == PCI_ADDRESS_SPACE_MEM
812	\|\| enmType == PCI_ADDRESS_SPACE_IO
813	\|\| enmType == PCI_ADDRESS_SPACE_MEM_PREFETCH,
814	("Invalid enmType=%#x? Or was this a bitmask after all...\n", enmType),
815	VERR_INVALID_PARAMETER);
816	AssertMsgReturn((unsigned)iRegion < PCI_NUM_REGIONS,
817	("Invalid iRegion=%d PCI_NUM_REGIONS=%d\n", iRegion, PCI_NUM_REGIONS),
818	VERR_INVALID_PARAMETER);
819	int iLastSet = ASMBitLastSetU32(cbRegion);
820	AssertMsgReturn( iLastSet != 0
821	&& RT_BIT_32(iLastSet - 1) == cbRegion,
822	("Invalid cbRegion=%#x iLastSet=%#x (not a power of 2 or 0)\n", cbRegion, iLastSet),
823	VERR_INVALID_PARAMETER);
824
825	/*
826	* Register the I/O region.
827	*/
828	PPCIIOREGION pRegion = &pPciDev->Int.s.aIORegions[iRegion];
829	pRegion->addr = INVALID_PCI_ADDRESS;
830	pRegion->size = cbRegion;
831	pRegion->type = enmType;
832	pRegion->map_func = pfnCallback;
833
834	/* Set type in the config space. */
835	uint32_t u32Address = ich9pciGetRegionReg(iRegion);
836	uint32_t u32Value = (enmType == PCI_ADDRESS_SPACE_MEM_PREFETCH ? (1 << 3) : 0)
837	\| (enmType == PCI_ADDRESS_SPACE_IO ? 1 : 0);
838	PCIDevSetDWord(pPciDev, u32Address, u32Value);
839
840	return VINF_SUCCESS;
841	}
842
843	static DECLCALLBACK(void) ich9pciSetConfigCallbacks(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PFNPCICONFIGREAD pfnRead, PPFNPCICONFIGREAD ppfnReadOld,
844	PFNPCICONFIGWRITE pfnWrite, PPFNPCICONFIGWRITE ppfnWriteOld)
845	{
846	if (ppfnReadOld)
847	*ppfnReadOld = pPciDev->Int.s.pfnConfigRead;
848	pPciDev->Int.s.pfnConfigRead = pfnRead;
849
850	if (ppfnWriteOld)
851	*ppfnWriteOld = pPciDev->Int.s.pfnConfigWrite;
852	pPciDev->Int.s.pfnConfigWrite = pfnWrite;
853	}
854
855	/**
856	* Saves a state of the PCI device.
857	*
858	* @returns VBox status code.
859	* @param pDevIns Device instance of the PCI Bus.
860	* @param pPciDev Pointer to PCI device.
861	* @param pSSM The handle to save the state to.
862	*/
863	static DECLCALLBACK(int) ich9pciGenericSaveExec(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PSSMHANDLE pSSM)
864	{
865	return SSMR3PutMem(pSSM, &pPciDev->config[0], sizeof(pPciDev->config));
866	}
867
868	static int ich9pciR3CommonSaveExec(PPCIBUS pBus, PSSMHANDLE pSSM)
869	{
870	/*
871	* Iterate thru all the devices.
872	*/
873	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
874	{
875	PPCIDEVICE pDev = pBus->apDevices[i];
876	if (pDev)
877	{
878	/* Device position */
879	SSMR3PutU32(pSSM, i);
880	/* PCI config registers */
881	SSMR3PutMem(pSSM, pDev->config, sizeof(pDev->config));
882
883	/* Device flags */
884	int rc = SSMR3PutU32(pSSM, pDev->Int.s.uFlags);
885	if (RT_FAILURE(rc))
886	return rc;
887
888	/* IRQ pin state */
889	rc = SSMR3PutS32(pSSM, pDev->Int.s.uIrqPinState);
890	if (RT_FAILURE(rc))
891	return rc;
892
893	/* MSI info */
894	rc = SSMR3PutU8(pSSM, pDev->Int.s.u8MsiCapOffset);
895	if (RT_FAILURE(rc))
896	return rc;
897	rc = SSMR3PutU8(pSSM, pDev->Int.s.u8MsiCapSize);
898	if (RT_FAILURE(rc))
899	return rc;
900
901	/* MSI-X info */
902	rc = SSMR3PutU8(pSSM, pDev->Int.s.u8MsixCapOffset);
903	if (RT_FAILURE(rc))
904	return rc;
905	rc = SSMR3PutU8(pSSM, pDev->Int.s.u8MsixCapSize);
906	if (RT_FAILURE(rc))
907	return rc;
908	}
909	}
910	return SSMR3PutU32(pSSM, UINT32_MAX); /* terminator */
911	}
912
913	static DECLCALLBACK(int) ich9pciR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
914	{
915	PPCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
916
917	/*
918	* Bus state data.
919	*/
920	SSMR3PutU32(pSSM, pThis->uConfigReg);
921
922	/*
923	* Save IRQ states.
924	*/
925	for (int i = 0; i < PCI_APIC_IRQ_PINS; i++)
926	SSMR3PutU32(pSSM, pThis->uaPciApicIrqLevels[i]);
927
928	SSMR3PutU32(pSSM, ~0); /* separator */
929
930	return ich9pciR3CommonSaveExec(&pThis->aPciBus, pSSM);
931	}
932
933
934	static DECLCALLBACK(int) ich9pcibridgeR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
935	{
936	PPCIBUS pThis = PDMINS_2_DATA(pDevIns, PPCIBUS);
937	return ich9pciR3CommonSaveExec(pThis, pSSM);
938	}
939
940
941	static void ich9pcibridgeConfigWrite(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice, uint32_t u32Address, uint32_t u32Value, unsigned cb)
942	{
943	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
944
945	LogFlowFunc((": pDevIns=%p iBus=%d iDevice=%d u32Address=%u u32Value=%u cb=%d\n", pDevIns, iBus, iDevice, u32Address, u32Value, cb));
946
947	/* If the current bus is not the target bus search for the bus which contains the device. */
948	if (iBus != PCIDevGetByte(&pBus->aPciDev, VBOX_PCI_SECONDARY_BUS))
949	{
950	PPCIDEVICE pBridgeDevice = ich9pciFindBridge(pBus, iBus);
951	if (pBridgeDevice)
952	{
953	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigWrite);
954	pBridgeDevice->Int.s.pfnBridgeConfigWrite(pBridgeDevice->pDevIns, iBus, iDevice, u32Address, u32Value, cb);
955	}
956	}
957	else
958	{
959	/* This is the target bus, pass the write to the device. */
960	PPCIDEVICE pPciDev = pBus->apDevices[iDevice];
961	if (pPciDev)
962	{
963	Log(("%s: %s: addr=%02x val=%08x len=%d\n", __FUNCTION__, pPciDev->name, u32Address, u32Value, cb));
964	pPciDev->Int.s.pfnConfigWrite(pPciDev, u32Address, u32Value, cb);
965	}
966	}
967	}
968
969	static uint32_t ich9pcibridgeConfigRead(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice, uint32_t u32Address, unsigned cb)
970	{
971	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
972	uint32_t u32Value = 0xffffffff; /* Return value in case there is no device. */
973
974	LogFlowFunc((": pDevIns=%p iBus=%d iDevice=%d u32Address=%u cb=%d\n", pDevIns, iBus, iDevice, u32Address, cb));
975
976	/* If the current bus is not the target bus search for the bus which contains the device. */
977	if (iBus != PCIDevGetByte(&pBus->aPciDev, VBOX_PCI_SECONDARY_BUS))
978	{
979	PPCIDEVICE pBridgeDevice = ich9pciFindBridge(pBus, iBus);
980	if (pBridgeDevice)
981	{
982	AssertPtr( pBridgeDevice->Int.s.pfnBridgeConfigRead);
983	u32Value = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->pDevIns, iBus, iDevice, u32Address, cb);
984	}
985	}
986	else
987	{
988	/* This is the target bus, pass the read to the device. */
989	PPCIDEVICE pPciDev = pBus->apDevices[iDevice];
990	if (pPciDev)
991	{
992	u32Value = pPciDev->Int.s.pfnConfigRead(pPciDev, u32Address, cb);
993	Log(("%s: %s: u32Address=%02x u32Value=%08x cb=%d\n", __FUNCTION__, pPciDev->name, u32Address, u32Value, cb));
994	}
995	}
996
997	return u32Value;
998	}
999
1000
1001	/**
1002	* Common routine for restoring the config registers of a PCI device.
1003	*
1004	* @param pDev The PCI device.
1005	* @param pbSrcConfig The configuration register values to be loaded.
1006	* @param fIsBridge Whether this is a bridge device or not.
1007	*/
1008	static void pciR3CommonRestoreConfig(PPCIDEVICE pDev, uint8_t const *pbSrcConfig, bool fIsBridge)
1009	{
1010	/*
1011	* This table defines the fields for normal devices and bridge devices, and
1012	* the order in which they need to be restored.
1013	*/
1014	static const struct PciField
1015	{
1016	uint8_t off;
1017	uint8_t cb;
1018	uint8_t fWritable;
1019	uint8_t fBridge;
1020	const char *pszName;
1021	} s_aFields[] =
1022	{
1023	/* off,cb,fW,fB, pszName */
1024	{ VBOX_PCI_VENDOR_ID, 2, 0, 3, "VENDOR_ID" },
1025	{ VBOX_PCI_DEVICE_ID, 2, 0, 3, "DEVICE_ID" },
1026	{ VBOX_PCI_STATUS, 2, 1, 3, "STATUS" },
1027	{ VBOX_PCI_REVISION_ID, 1, 0, 3, "REVISION_ID" },
1028	{ VBOX_PCI_CLASS_PROG, 1, 0, 3, "CLASS_PROG" },
1029	{ VBOX_PCI_CLASS_SUB, 1, 0, 3, "CLASS_SUB" },
1030	{ VBOX_PCI_CLASS_BASE, 1, 0, 3, "CLASS_BASE" },
1031	{ VBOX_PCI_CACHE_LINE_SIZE, 1, 1, 3, "CACHE_LINE_SIZE" },
1032	{ VBOX_PCI_LATENCY_TIMER, 1, 1, 3, "LATENCY_TIMER" },
1033	{ VBOX_PCI_HEADER_TYPE, 1, 0, 3, "HEADER_TYPE" },
1034	{ VBOX_PCI_BIST, 1, 1, 3, "BIST" },
1035	{ VBOX_PCI_BASE_ADDRESS_0, 4, 1, 3, "BASE_ADDRESS_0" },
1036	{ VBOX_PCI_BASE_ADDRESS_1, 4, 1, 3, "BASE_ADDRESS_1" },
1037	{ VBOX_PCI_BASE_ADDRESS_2, 4, 1, 1, "BASE_ADDRESS_2" },
1038	{ VBOX_PCI_PRIMARY_BUS, 1, 1, 2, "PRIMARY_BUS" }, // fWritable = ??
1039	{ VBOX_PCI_SECONDARY_BUS, 1, 1, 2, "SECONDARY_BUS" }, // fWritable = ??
1040	{ VBOX_PCI_SUBORDINATE_BUS, 1, 1, 2, "SUBORDINATE_BUS" }, // fWritable = ??
1041	{ VBOX_PCI_SEC_LATENCY_TIMER, 1, 1, 2, "SEC_LATENCY_TIMER" }, // fWritable = ??
1042	{ VBOX_PCI_BASE_ADDRESS_3, 4, 1, 1, "BASE_ADDRESS_3" },
1043	{ VBOX_PCI_IO_BASE, 1, 1, 2, "IO_BASE" }, // fWritable = ??
1044	{ VBOX_PCI_IO_LIMIT, 1, 1, 2, "IO_LIMIT" }, // fWritable = ??
1045	{ VBOX_PCI_SEC_STATUS, 2, 1, 2, "SEC_STATUS" }, // fWritable = ??
1046	{ VBOX_PCI_BASE_ADDRESS_4, 4, 1, 1, "BASE_ADDRESS_4" },
1047	{ VBOX_PCI_MEMORY_BASE, 2, 1, 2, "MEMORY_BASE" }, // fWritable = ??
1048	{ VBOX_PCI_MEMORY_LIMIT, 2, 1, 2, "MEMORY_LIMIT" }, // fWritable = ??
1049	{ VBOX_PCI_BASE_ADDRESS_5, 4, 1, 1, "BASE_ADDRESS_5" },
1050	{ VBOX_PCI_PREF_MEMORY_BASE, 2, 1, 2, "PREF_MEMORY_BASE" }, // fWritable = ??
1051	{ VBOX_PCI_PREF_MEMORY_LIMIT, 2, 1, 2, "PREF_MEMORY_LIMIT" }, // fWritable = ??
1052	{ VBOX_PCI_CARDBUS_CIS, 4, 1, 1, "CARDBUS_CIS" }, // fWritable = ??
1053	{ VBOX_PCI_PREF_BASE_UPPER32, 4, 1, 2, "PREF_BASE_UPPER32" }, // fWritable = ??
1054	{ VBOX_PCI_SUBSYSTEM_VENDOR_ID, 2, 0, 1, "SUBSYSTEM_VENDOR_ID" },// fWritable = !?
1055	{ VBOX_PCI_PREF_LIMIT_UPPER32, 4, 1, 2, "PREF_LIMIT_UPPER32" },// fWritable = ??
1056	{ VBOX_PCI_SUBSYSTEM_ID, 2, 0, 1, "SUBSYSTEM_ID" }, // fWritable = !?
1057	{ VBOX_PCI_ROM_ADDRESS, 4, 1, 1, "ROM_ADDRESS" }, // fWritable = ?!
1058	{ VBOX_PCI_IO_BASE_UPPER16, 2, 1, 2, "IO_BASE_UPPER16" }, // fWritable = ?!
1059	{ VBOX_PCI_IO_LIMIT_UPPER16, 2, 1, 2, "IO_LIMIT_UPPER16" }, // fWritable = ?!
1060	{ VBOX_PCI_CAPABILITY_LIST, 4, 0, 3, "CAPABILITY_LIST" }, // fWritable = !? cb=!?
1061	{ VBOX_PCI_RESERVED_38, 4, 1, 1, "RESERVED_38" }, // ???
1062	{ VBOX_PCI_ROM_ADDRESS_BR, 4, 1, 2, "ROM_ADDRESS_BR" }, // fWritable = !? cb=!? fBridge=!?
1063	{ VBOX_PCI_INTERRUPT_LINE, 1, 1, 3, "INTERRUPT_LINE" }, // fBridge=??
1064	{ VBOX_PCI_INTERRUPT_PIN, 1, 0, 3, "INTERRUPT_PIN" }, // fBridge=??
1065	{ VBOX_PCI_MIN_GNT, 1, 0, 1, "MIN_GNT" },
1066	{ VBOX_PCI_BRIDGE_CONTROL, 2, 1, 2, "BRIDGE_CONTROL" }, // fWritable = !?
1067	{ VBOX_PCI_MAX_LAT, 1, 0, 1, "MAX_LAT" },
1068	/* The COMMAND register must come last as it requires the ADDRESS
1069	registers to be restored before we pretent to change it from 0 to
1070	whatever value the guest assigned it. */
1071	{ VBOX_PCI_COMMAND, 2, 1, 3, "COMMAND" },
1072	};
1073
1074	#ifdef RT_STRICT
1075	/* Check that we've got full register coverage. */
1076	uint32_t bmDevice[0x40 / 32];
1077	uint32_t bmBridge[0x40 / 32];
1078	RT_ZERO(bmDevice);
1079	RT_ZERO(bmBridge);
1080	for (uint32_t i = 0; i < RT_ELEMENTS(s_aFields); i++)
1081	{
1082	uint8_t off = s_aFields[i].off;
1083	uint8_t cb = s_aFields[i].cb;
1084	uint8_t f = s_aFields[i].fBridge;
1085	while (cb-- > 0)
1086	{
1087	if (f & 1) AssertMsg(!ASMBitTest(bmDevice, off), ("%#x\n", off));
1088	if (f & 2) AssertMsg(!ASMBitTest(bmBridge, off), ("%#x\n", off));
1089	if (f & 1) ASMBitSet(bmDevice, off);
1090	if (f & 2) ASMBitSet(bmBridge, off);
1091	off++;
1092	}
1093	}
1094	for (uint32_t off = 0; off < 0x40; off++)
1095	{
1096	AssertMsg(ASMBitTest(bmDevice, off), ("%#x\n", off));
1097	AssertMsg(ASMBitTest(bmBridge, off), ("%#x\n", off));
1098	}
1099	#endif
1100
1101	/*
1102	* Loop thru the fields covering the 64 bytes of standard registers.
1103	*/
1104	uint8_t const fBridge = fIsBridge ? 2 : 1;
1105	uint8_t *pbDstConfig = &pDev->config[0];
1106	for (uint32_t i = 0; i < RT_ELEMENTS(s_aFields); i++)
1107	if (s_aFields[i].fBridge & fBridge)
1108	{
1109	uint8_t const off = s_aFields[i].off;
1110	uint8_t const cb = s_aFields[i].cb;
1111	uint32_t u32Src;
1112	uint32_t u32Dst;
1113	switch (cb)
1114	{
1115	case 1:
1116	u32Src = pbSrcConfig[off];
1117	u32Dst = pbDstConfig[off];
1118	break;
1119	case 2:
1120	u32Src = (uint16_t const )&pbSrcConfig[off];
1121	u32Dst = (uint16_t const )&pbDstConfig[off];
1122	break;
1123	case 4:
1124	u32Src = (uint32_t const )&pbSrcConfig[off];
1125	u32Dst = (uint32_t const )&pbDstConfig[off];
1126	break;
1127	default:
1128	AssertFailed();
1129	continue;
1130	}
1131
1132	if ( u32Src != u32Dst
1133	\|\| off == VBOX_PCI_COMMAND)
1134	{
1135	if (u32Src != u32Dst)
1136	{
1137	if (!s_aFields[i].fWritable)
1138	LogRel(("PCI: %8s/%u: %2u-bit field %s: %x -> %x - !READ ONLY!\n",
1139	pDev->name, pDev->pDevIns->iInstance, cb*8, s_aFields[i].pszName, u32Dst, u32Src));
1140	else
1141	LogRel(("PCI: %8s/%u: %2u-bit field %s: %x -> %x\n",
1142	pDev->name, pDev->pDevIns->iInstance, cb*8, s_aFields[i].pszName, u32Dst, u32Src));
1143	}
1144	if (off == VBOX_PCI_COMMAND)
1145	PCIDevSetCommand(pDev, 0); /* For remapping, see ich9pciR3CommonLoadExec. */
1146	pDev->Int.s.pfnConfigWrite(pDev, off, u32Src, cb);
1147	}
1148	}
1149
1150	/*
1151	* The device dependent registers.
1152	*
1153	* We will not use ConfigWrite here as we have no clue about the size
1154	* of the registers, so the device is responsible for correctly
1155	* restoring functionality governed by these registers.
1156	*/
1157	for (uint32_t off = 0x40; off < sizeof(pDev->config); off++)
1158	if (pbDstConfig[off] != pbSrcConfig[off])
1159	{
1160	LogRel(("PCI: %8s/%u: register %02x: %02x -> %02x\n",
1161	pDev->name, pDev->pDevIns->iInstance, off, pbDstConfig[off], pbSrcConfig[off])); /** @todo make this Log() later. */
1162	pbDstConfig[off] = pbSrcConfig[off];
1163	}
1164	}
1165
1166	/**
1167	* Common worker for ich9pciR3LoadExec and ich9pcibridgeR3LoadExec.
1168	*
1169	* @returns VBox status code.
1170	* @param pBus The bus which data is being loaded.
1171	* @param pSSM The saved state handle.
1172	* @param uVersion The data version.
1173	* @param uPass The pass.
1174	*/
1175	static DECLCALLBACK(int) ich9pciR3CommonLoadExec(PPCIBUS pBus, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1176	{
1177	uint32_t u32;
1178	uint32_t i;
1179	int rc;
1180
1181	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
1182
1183	/*
1184	* Iterate thru all the devices and write 0 to the COMMAND register so
1185	* that all the memory is unmapped before we start restoring the saved
1186	* mapping locations.
1187	*
1188	* The register value is restored afterwards so we can do proper
1189	* LogRels in pciR3CommonRestoreConfig.
1190	*/
1191	for (i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
1192	{
1193	PPCIDEVICE pDev = pBus->apDevices[i];
1194	if (pDev)
1195	{
1196	uint16_t u16 = PCIDevGetCommand(pDev);
1197	pDev->Int.s.pfnConfigWrite(pDev, VBOX_PCI_COMMAND, 0, 2);
1198	PCIDevSetCommand(pDev, u16);
1199	Assert(PCIDevGetCommand(pDev) == u16);
1200	}
1201	}
1202
1203	/*
1204	* Iterate all the devices.
1205	*/
1206	for (i = 0;; i++)
1207	{
1208	PCIDEVICE DevTmp;
1209	PPCIDEVICE pDev;
1210
1211	/* index / terminator */
1212	rc = SSMR3GetU32(pSSM, &u32);
1213	if (RT_FAILURE(rc))
1214	return rc;
1215	if (u32 == (uint32_t)~0)
1216	break;
1217	if ( u32 >= RT_ELEMENTS(pBus->apDevices)
1218	\|\| u32 < i)
1219	{
1220	AssertMsgFailed(("u32=%#x i=%#x\n", u32, i));
1221	return rc;
1222	}
1223
1224	/* skip forward to the device checking that no new devices are present. */
1225	for (; i < u32; i++)
1226	{
1227	pDev = pBus->apDevices[i];
1228	if (pDev)
1229	{
1230	LogRel(("New device in slot %#x, %s (vendor=%#06x device=%#06x)\n", i, pDev->name,
1231	PCIDevGetVendorId(pDev), PCIDevGetDeviceId(pDev)));
1232	if (SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT)
1233	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("New device in slot %#x, %s (vendor=%#06x device=%#06x)"),
1234	i, pDev->name, PCIDevGetVendorId(pDev), PCIDevGetDeviceId(pDev));
1235	}
1236	}
1237
1238	/* get the data */
1239	DevTmp.Int.s.uFlags = 0;
1240	DevTmp.Int.s.u8MsiCapOffset = 0;
1241	DevTmp.Int.s.u8MsiCapSize = 0;
1242	DevTmp.Int.s.u8MsixCapOffset = 0;
1243	DevTmp.Int.s.u8MsixCapSize = 0;
1244	DevTmp.Int.s.uIrqPinState = ~0; /* Invalid value in case we have an older saved state to force a state change in pciSetIrq. */
1245	SSMR3GetMem(pSSM, DevTmp.config, sizeof(DevTmp.config));
1246
1247	rc = SSMR3GetU32(pSSM, &DevTmp.Int.s.uFlags);
1248	if (RT_FAILURE(rc))
1249	return rc;
1250
1251	rc = SSMR3GetS32(pSSM, &DevTmp.Int.s.uIrqPinState);
1252	if (RT_FAILURE(rc))
1253	return rc;
1254
1255	rc = SSMR3GetU8(pSSM, &DevTmp.Int.s.u8MsiCapOffset);
1256	if (RT_FAILURE(rc))
1257	return rc;
1258
1259	rc = SSMR3GetU8(pSSM, &DevTmp.Int.s.u8MsiCapSize);
1260	if (RT_FAILURE(rc))
1261	return rc;
1262
1263	rc = SSMR3GetU8(pSSM, &DevTmp.Int.s.u8MsixCapOffset);
1264	if (RT_FAILURE(rc))
1265	return rc;
1266
1267	rc = SSMR3GetU8(pSSM, &DevTmp.Int.s.u8MsixCapSize);
1268	if (RT_FAILURE(rc))
1269	return rc;
1270
1271	/* check that it's still around. */
1272	pDev = pBus->apDevices[i];
1273	if (!pDev)
1274	{
1275	LogRel(("Device in slot %#x has been removed! vendor=%#06x device=%#06x\n", i,
1276	PCIDevGetVendorId(&DevTmp), PCIDevGetDeviceId(&DevTmp)));
1277	if (SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT)
1278	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Device in slot %#x has been removed! vendor=%#06x device=%#06x"),
1279	i, PCIDevGetVendorId(&DevTmp), PCIDevGetDeviceId(&DevTmp));
1280	continue;
1281	}
1282
1283	/* match the vendor id assuming that this will never be changed. */
1284	if ( PCIDevGetVendorId(&DevTmp) != PCIDevGetVendorId(pDev))
1285	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Device in slot %#x (%s) vendor id mismatch! saved=%.4Rhxs current=%.4Rhxs"),
1286	i, pDev->name, PCIDevGetVendorId(&DevTmp), PCIDevGetVendorId(pDev));
1287
1288	/* commit the loaded device config. */
1289	pciR3CommonRestoreConfig(pDev, &DevTmp.config[0], false ); /** @todo fix bridge fun! */
1290
1291	pDev->Int.s.uIrqPinState = DevTmp.Int.s.uIrqPinState;
1292	}
1293
1294	return VINF_SUCCESS;
1295	}
1296
1297	/**
1298	* Loads a saved PCI device state.
1299	*
1300	* @returns VBox status code.
1301	* @param pDevIns Device instance of the PCI Bus.
1302	* @param pPciDev Pointer to PCI device.
1303	* @param pSSM The handle to the saved state.
1304	*/
1305	static DECLCALLBACK(int) ich9pciGenericLoadExec(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PSSMHANDLE pSSM)
1306	{
1307	return SSMR3GetMem(pSSM, &pPciDev->config[0], sizeof(pPciDev->config));
1308	}
1309
1310	static DECLCALLBACK(int) ich9pciR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1311	{
1312	PPCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
1313	PPCIBUS pBus = &pThis->aPciBus;
1314	uint32_t u32;
1315	int rc;
1316
1317	/* We ignore this version as there's no saved state with it anyway */
1318	if (uVersion == VBOX_ICH9PCI_SAVED_STATE_VERSION_NOMSI)
1319	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1320	if (uVersion > VBOX_ICH9PCI_SAVED_STATE_VERSION_MSI)
1321	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1322
1323	/*
1324	* Bus state data.
1325	*/
1326	SSMR3GetU32(pSSM, &pThis->uConfigReg);
1327
1328	/*
1329	* Load IRQ states.
1330	*/
1331	for (int i = 0; i < PCI_APIC_IRQ_PINS; i++)
1332	SSMR3GetU32(pSSM, (uint32_t*)&pThis->uaPciApicIrqLevels[i]);
1333
1334	/* separator */
1335	rc = SSMR3GetU32(pSSM, &u32);
1336	if (RT_FAILURE(rc))
1337	return rc;
1338	if (u32 != (uint32_t)~0)
1339	AssertMsgFailedReturn(("u32=%#x\n", u32), rc);
1340
1341	return ich9pciR3CommonLoadExec(pBus, pSSM, uVersion, uPass);
1342	}
1343
1344	static DECLCALLBACK(int) ich9pcibridgeR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1345	{
1346	PPCIBUS pThis = PDMINS_2_DATA(pDevIns, PPCIBUS);
1347	if (uVersion > VBOX_ICH9PCI_SAVED_STATE_VERSION_MSI)
1348	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1349	return ich9pciR3CommonLoadExec(pThis, pSSM, uVersion, uPass);
1350	}
1351
1352	static uint32_t ich9pciConfigRead(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t len)
1353	{
1354	uint32_t u32Val = 0xffffffff;
1355	PciAddress aPciAddr;
1356
1357	aPciAddr.iBus = uBus;
1358	aPciAddr.iDeviceFunc = uDevFn;
1359	aPciAddr.iRegister = addr;
1360
1361	int rc = ich9pciDataReadAddr(pGlobals, &aPciAddr, len, &u32Val);
1362	AssertRC(rc);
1363	switch (len)
1364	{
1365	case 1:
1366	u32Val &= 0xff;
1367	break;
1368	case 2:
1369	u32Val &= 0xffff;
1370	break;
1371	}
1372	return u32Val;
1373	}
1374
1375	static void ich9pciConfigWrite(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t val, uint32_t len)
1376	{
1377	PciAddress aPciAddr;
1378
1379	aPciAddr.iBus = uBus;
1380	aPciAddr.iDeviceFunc = uDevFn;
1381	aPciAddr.iRegister = addr;
1382
1383	ich9pciDataWriteAddr(pGlobals, &aPciAddr, val, len);
1384	}
1385
1386	static void ich9pciSetRegionAddress(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, int iRegion, uint32_t addr)
1387	{
1388	uint32_t uReg = ich9pciGetRegionReg(iRegion);
1389
1390	/* Read memory type first. */
1391	uint8_t uResourceType = ich9pciConfigRead(pGlobals, uBus, uDevFn, uReg, 1);
1392	/* Read command register. */
1393	uint16_t uCmd = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_COMMAND, 2);
1394
1395	if ( iRegion == PCI_ROM_SLOT )
1396	uCmd \|= PCI_COMMAND_MEMACCESS;
1397	else if ((uResourceType & PCI_ADDRESS_SPACE_IO) == PCI_ADDRESS_SPACE_IO)
1398	uCmd \|= PCI_COMMAND_IOACCESS; /* Enable I/O space access. */
1399	else /* The region is MMIO. */
1400	uCmd \|= PCI_COMMAND_MEMACCESS; /* Enable MMIO access. */
1401
1402	/* Write address of the device. */
1403	ich9pciConfigWrite(pGlobals, uBus, uDevFn, uReg, addr, 4);
1404
1405	/* enable memory mappings */
1406	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_COMMAND, uCmd, 2);
1407	}
1408
1409
1410	static void ich9pciBiosInitBridge(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint8_t cBridgeDepth, uint8_t *paBridgePositions)
1411	{
1412	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_SECONDARY_BUS, pGlobals->uBus, 1);
1413	/* Temporary until we know how many other bridges are behind this one. */
1414	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_SUBORDINATE_BUS, 0xff, 1);
1415
1416	/* Add position of this bridge into the array. */
1417	paBridgePositions[cBridgeDepth+1] = (uDevFn >> 3);
1418
1419	/*
1420	* The I/O range for the bridge must be aligned to a 4KB boundary.
1421	* This does not change anything really as the access to the device is not going
1422	* through the bridge but we want to be compliant to the spec.
1423	*/
1424	if ((pGlobals->uPciBiosIo % 4096) != 0)
1425	{
1426	pGlobals->uPciBiosIo = RT_ALIGN_32(pGlobals->uPciBiosIo, 4*1024);
1427	Log(("%s: Aligned I/O start address. New address %#x\n", __FUNCTION__, pGlobals->uPciBiosIo));
1428	}
1429	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_IO_BASE, (pGlobals->uPciBiosIo >> 8) & 0xf0, 1);
1430
1431	/* The MMIO range for the bridge must be aligned to a 1MB boundary. */
1432	if ((pGlobals->uPciBiosMmio % (1024 * 1024)) != 0)
1433	{
1434	pGlobals->uPciBiosMmio = RT_ALIGN_32(pGlobals->uPciBiosMmio, 1024*1024);
1435	Log(("%s: Aligned MMIO start address. New address %#x\n", __FUNCTION__, pGlobals->uPciBiosMmio));
1436	}
1437	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_MEMORY_BASE, (pGlobals->uPciBiosMmio >> 16) & UINT32_C(0xffff0), 2);
1438
1439	/* Save values to compare later to. */
1440	uint32_t u32IoAddressBase = pGlobals->uPciBiosIo;
1441	uint32_t u32MMIOAddressBase = pGlobals->uPciBiosMmio;
1442
1443	/* Init devices behind the bridge and possibly other bridges as well. */
1444	for (int iDev = 0; iDev <= 255; iDev++)
1445	ich9pciBiosInitDevice(pGlobals, uBus + 1, iDev, cBridgeDepth + 1, paBridgePositions);
1446
1447	/* The number of bridges behind the this one is now available. */
1448	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_SUBORDINATE_BUS, pGlobals->uBus, 1);
1449
1450	/*
1451	* Set I/O limit register. If there is no device with I/O space behind the bridge
1452	* we set a lower value than in the base register.
1453	* The result with a real bridge is that no I/O transactions are passed to the secondary
1454	* interface. Again this doesn't really matter here but we want to be compliant to the spec.
1455	*/
1456	if ((u32IoAddressBase != pGlobals->uPciBiosIo) && ((pGlobals->uPciBiosIo % 4096) != 0))
1457	{
1458	/* The upper boundary must be one byte less than a 4KB boundary. */
1459	pGlobals->uPciBiosIo = RT_ALIGN_32(pGlobals->uPciBiosIo, 4*1024);
1460	}
1461
1462	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_IO_LIMIT, ((pGlobals->uPciBiosIo >> 8) & 0xf0) - 1, 1);
1463
1464	/* Same with the MMIO limit register but with 1MB boundary here. */
1465	if ((u32MMIOAddressBase != pGlobals->uPciBiosMmio) && ((pGlobals->uPciBiosMmio % (1024 * 1024)) != 0))
1466	{
1467	/* The upper boundary must be one byte less than a 1MB boundary. */
1468	pGlobals->uPciBiosMmio = RT_ALIGN_32(pGlobals->uPciBiosMmio, 1024*1024);
1469	}
1470	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_MEMORY_LIMIT, ((pGlobals->uPciBiosMmio >> 16) & UINT32_C(0xfff0)) - 1, 2);
1471
1472	/*
1473	* Set the prefetch base and limit registers. We currently have no device with a prefetchable region
1474	* which may be behind a bridge. Thatswhy it is unconditionally disabled here atm by writing a higher value into
1475	* the base register than in the limit register.
1476	*/
1477	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_MEMORY_BASE, 0xfff0, 2);
1478	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_MEMORY_LIMIT, 0x0, 2);
1479	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_BASE_UPPER32, 0x00, 4);
1480	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_LIMIT_UPPER32, 0x00, 4);
1481	}
1482
1483	static void ich9pciBiosInitDevice(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint8_t cBridgeDepth, uint8_t *paBridgePositions)
1484	{
1485	uint32_t *paddr;
1486	uint16_t uDevClass, uVendor, uDevice;
1487	uint8_t uCmd;
1488
1489	uDevClass = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_CLASS_DEVICE, 2);
1490	uVendor = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_VENDOR_ID, 2);
1491	uDevice = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_DEVICE_ID, 2);
1492
1493	/* If device is present */
1494	if (uVendor == 0xffff)
1495	return;
1496
1497	switch (uDevClass)
1498	{
1499	case 0x0101:
1500	/* IDE controller */
1501	ich9pciConfigWrite(pGlobals, uBus, uDevFn, 0x40, 0x8000, 2); /* enable IDE0 */
1502	ich9pciConfigWrite(pGlobals, uBus, uDevFn, 0x42, 0x8000, 2); /* enable IDE1 */
1503	goto default_map;
1504	break;
1505	case 0x0300:
1506	/* VGA controller */
1507	if (uVendor != 0x80ee)
1508	goto default_map;
1509	/* VGA: map frame buffer to default Bochs VBE address */
1510	ich9pciSetRegionAddress(pGlobals, uBus, uDevFn, 0, 0xE0000000);
1511	/*
1512	* Legacy VGA I/O ports are implicitly decoded by a VGA class device. But
1513	* only the framebuffer (i.e., a memory region) is explicitly registered via
1514	* ich9pciSetRegionAddress, so I/O decoding must be enabled manually.
1515	*/
1516	uCmd = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_COMMAND, 1);
1517	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_COMMAND,
1518	/* Enable I/O space access. */
1519	uCmd \| PCI_COMMAND_IOACCESS,
1520	1);
1521	break;
1522	case 0x0800:
1523	/* PIC */
1524	if (uVendor == 0x1014)
1525	{
1526	/* IBM */
1527	if (uDevice == 0x0046 \|\| uDevice == 0xFFFF)
1528	/* MPIC & MPIC2 */
1529	ich9pciSetRegionAddress(pGlobals, uBus, uDevFn, 0, 0x80800000 + 0x00040000);
1530	}
1531	break;
1532	case 0xff00:
1533	if ((uVendor == 0x0106b)
1534	&& (uDevice == 0x0017 \|\| uDevice == 0x0022))
1535	{
1536	/* macio bridge */
1537	ich9pciSetRegionAddress(pGlobals, uBus, uDevFn, 0, 0x80800000);
1538	}
1539	break;
1540	case 0x0604:
1541	/* PCI-to-PCI bridge. */
1542	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_PRIMARY_BUS, uBus, 1);
1543
1544	AssertMsg(pGlobals->uBus < 255, ("Too many bridges on the bus\n"));
1545	pGlobals->uBus++;
1546	ich9pciBiosInitBridge(pGlobals, uBus, uDevFn, cBridgeDepth, paBridgePositions);
1547	break;
1548	default:
1549	default_map:
1550	{
1551	/* default memory mappings */
1552	/*
1553	* We ignore ROM region here.
1554	*/
1555	for (int iRegion = 0; iRegion < (PCI_NUM_REGIONS-1); iRegion++)
1556	{
1557	uint32_t u32Address = ich9pciGetRegionReg(iRegion);
1558
1559	/* Calculate size. */
1560	uint8_t u8ResourceType = ich9pciConfigRead(pGlobals, uBus, uDevFn, u32Address, 1);
1561	ich9pciConfigWrite(pGlobals, uBus, uDevFn, u32Address, UINT32_C(0xffffffff), 4);
1562	uint32_t u32Size = ich9pciConfigRead(pGlobals, uBus, uDevFn, u32Address, 4);
1563	/* Clear resource information depending on resource type. */
1564	if ((u8ResourceType & PCI_COMMAND_IOACCESS) == PCI_COMMAND_IOACCESS) /* I/O */
1565	u32Size &= ~(0x01);
1566	else /* MMIO */
1567	u32Size &= ~(0x0f);
1568
1569	bool fIsPio = ((u8ResourceType & PCI_COMMAND_IOACCESS) == PCI_COMMAND_IOACCESS);
1570	/*
1571	* Invert all bits and add 1 to get size of the region.
1572	* (From PCI implementation note)
1573	*/
1574	if (fIsPio && (u32Size & UINT32_C(0xffff0000)) == 0)
1575	u32Size = (~(u32Size \| UINT32_C(0xffff0000))) + 1;
1576	else
1577	u32Size = (~u32Size) + 1;
1578
1579	Log(("%s: Size of region %u for device %d on bus %d is %u\n", __FUNCTION__, iRegion, uDevFn, uBus, u32Size));
1580
1581	if (u32Size)
1582	{
1583	paddr = fIsPio ? &pGlobals->uPciBiosIo : &pGlobals->uPciBiosMmio;
1584	paddr = (paddr + u32Size - 1) & ~(u32Size - 1);
1585	Log(("%s: Start address of %s region %u is %#x\n", __FUNCTION__, (fIsPio ? "I/O" : "MMIO"), iRegion, *paddr));
1586	ich9pciSetRegionAddress(pGlobals, uBus, uDevFn, iRegion, *paddr);
1587	*paddr += u32Size;
1588	Log(("%s: New address is %#x\n", __FUNCTION__, *paddr));
1589	}
1590	}
1591	break;
1592	}
1593	}
1594
1595	/* map the interrupt */
1596	uint32_t uPin = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_INTERRUPT_PIN, 1);
1597	if (uPin != 0)
1598	{
1599	uint8_t uBridgeDevFn = uDevFn;
1600	uPin--;
1601
1602	/* We need to go up to the host bus to see which irq this device will assert there. */
1603	while (cBridgeDepth != 0)
1604	{
1605	/* Get the pin the device would assert on the bridge. */
1606	uPin = ((uBridgeDevFn >> 3) + uPin) & 3;
1607	uBridgeDevFn = paBridgePositions[cBridgeDepth];
1608	cBridgeDepth--;
1609	}
1610	}
1611	}
1612
1613	static const uint8_t auPciIrqs[4] = { 11, 9, 11, 9 };
1614
1615	static DECLCALLBACK(int) ich9pciFakePCIBIOS(PPDMDEVINS pDevIns)
1616	{
1617	unsigned i;
1618	uint8_t elcr[2] = {0, 0};
1619	PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
1620	PVM pVM = PDMDevHlpGetVM(pDevIns);
1621	Assert(pVM);
1622
1623	/*
1624	* Set the start addresses.
1625	*/
1626	pGlobals->uPciBiosIo = 0xd000;
1627	pGlobals->uPciBiosMmio = UINT32_C(0xf0000000);
1628	pGlobals->uBus = 0;
1629
1630	/*
1631	* Activate IRQ mappings.
1632	*/
1633	for (i = 0; i < 4; i++)
1634	{
1635	uint8_t irq = auPciIrqs[i];
1636	/* Set to trigger level. */
1637	elcr[irq >> 3] \|= (1 << (irq & 7));
1638	}
1639
1640	/* Tell to the PIC. */
1641	VBOXSTRICTRC rcStrict = IOMIOPortWrite(pVM, 0x4d0, elcr[0], sizeof(uint8_t));
1642	if (rcStrict == VINF_SUCCESS)
1643	rcStrict = IOMIOPortWrite(pVM, 0x4d1, elcr[1], sizeof(uint8_t));
1644	if (rcStrict != VINF_SUCCESS)
1645	{
1646	AssertMsgFailed(("Writing to PIC failed! rcStrict=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
1647	return RT_SUCCESS(rcStrict) ? VERR_INTERNAL_ERROR : VBOXSTRICTRC_VAL(rcStrict);
1648	}
1649
1650	/*
1651	* Init the devices.
1652	*/
1653	for (i = 0; i < 256; i++)
1654	{
1655	uint8_t aBridgePositions[256];
1656
1657	memset(aBridgePositions, 0, sizeof(aBridgePositions));
1658	Log2(("PCI: Initializing device %d (%#x)\n",
1659	i, 0x80000000 \| (i << 8)));
1660	ich9pciBiosInitDevice(pGlobals, 0, i, 0, aBridgePositions);
1661	}
1662
1663	return VINF_SUCCESS;
1664	}
1665
1666	static DECLCALLBACK(uint32_t) ich9pciConfigReadDev(PCIDevice *aDev, uint32_t u32Address, unsigned len)
1667	{
1668	if ((u32Address + len) > 256 && (u32Address + len) < 4096)
1669	{
1670	AssertMsgReturn(false, ("Read from extended registers falled back to generic code\n"), 0);
1671	}
1672
1673	if ( PCIIsMsiCapable(aDev)
1674	&& (u32Address >= aDev->Int.s.u8MsiCapOffset)
1675	&& (u32Address < aDev->Int.s.u8MsiCapOffset + aDev->Int.s.u8MsiCapSize)
1676	)
1677	{
1678	return MsiPciConfigRead(aDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pDevIns), aDev, u32Address, len);
1679	}
1680
1681	AssertMsgReturn(u32Address + len <= 256, ("Read after end of PCI config space\n"),
1682	0);
1683	switch (len)
1684	{
1685	case 1:
1686	return PCIDevGetByte(aDev, u32Address);
1687	case 2:
1688	return PCIDevGetWord(aDev, u32Address);
1689	case 4:
1690	return PCIDevGetDWord(aDev, u32Address);
1691	default:
1692	Assert(false);
1693	return 0;
1694	}
1695	}
1696
1697
1698	/**
1699	* See paragraph 7.5 of PCI Express specification (p. 349) for definition of
1700	* registers and their writability policy.
1701	*/
1702	static DECLCALLBACK(void) ich9pciConfigWriteDev(PCIDevice *aDev, uint32_t u32Address,
1703	uint32_t val, unsigned len)
1704	{
1705	Assert(len <= 4);
1706
1707	if ((u32Address + len) > 256 && (u32Address + len) < 4096)
1708	{
1709	AssertMsgReturnVoid(false, ("Write to extended registers falled back to generic code\n"));
1710	}
1711
1712	AssertMsgReturnVoid(u32Address + len <= 256, ("Write after end of PCI config space\n"));
1713
1714	if ( PCIIsMsiCapable(aDev)
1715	&& (u32Address >= aDev->Int.s.u8MsiCapOffset)
1716	&& (u32Address < aDev->Int.s.u8MsiCapOffset + aDev->Int.s.u8MsiCapSize)
1717	)
1718	{
1719	MsiPciConfigWrite(aDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pDevIns),
1720	aDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pPciHlp),
1721	aDev, u32Address, val, len);
1722	return;
1723	}
1724
1725
1726	/* Fast case - update one of BARs or ROM address, 'while' only for 'break' */
1727	while ( len == 4
1728	&& ( ( u32Address >= VBOX_PCI_BASE_ADDRESS_0
1729	&& u32Address < VBOX_PCI_BASE_ADDRESS_0 + 6 * 4)
1730	\|\| ( u32Address >= VBOX_PCI_ROM_ADDRESS
1731	&& u32Address < VBOX_PCI_ROM_ADDRESS+4)
1732	)
1733	)
1734	{
1735	PCIIORegion *pRegion;
1736	int reg, regionSize;
1737
1738	reg = (u32Address >= VBOX_PCI_ROM_ADDRESS) ? PCI_ROM_SLOT : (u32Address - VBOX_PCI_BASE_ADDRESS_0) >> 2;
1739	pRegion = &aDev->Int.s.aIORegions[reg];
1740	regionSize = pRegion->size;
1741	if (regionSize == 0)
1742	break;
1743	/* compute the stored value */
1744	if (reg == PCI_ROM_SLOT) {
1745	/* keep ROM enable bit */
1746	val &= (~(regionSize - 1)) \| 1;
1747	} else {
1748	val &= ~(regionSize - 1);
1749	val \|= pRegion->type;
1750	}
1751	PCIDevSetDWord(aDev, u32Address, val);
1752	ich9pciUpdateMappings(aDev);
1753	return;
1754	}
1755
1756	uint32_t addr = u32Address;
1757	bool fUpdateMappings = false;
1758	for (uint32_t i = 0; i < len; i++)
1759	{
1760	bool fWritable = false;
1761	switch (PCIDevGetHeaderType(aDev))
1762	{
1763	case 0x00: /* normal device */
1764	case 0x80: /* multi-function device */
1765	switch (addr)
1766	{
1767	/* Read-only registers */
1768	case VBOX_PCI_VENDOR_ID: case VBOX_PCI_VENDOR_ID+1:
1769	case VBOX_PCI_DEVICE_ID: case VBOX_PCI_DEVICE_ID+1:
1770	case VBOX_PCI_REVISION_ID:
1771	case VBOX_PCI_CLASS_PROG:
1772	case VBOX_PCI_CLASS_SUB:
1773	case VBOX_PCI_CLASS_BASE:
1774	case VBOX_PCI_HEADER_TYPE:
1775	case VBOX_PCI_BASE_ADDRESS_0: case VBOX_PCI_BASE_ADDRESS_0+1: case VBOX_PCI_BASE_ADDRESS_0+2: case VBOX_PCI_BASE_ADDRESS_0+3:
1776	case VBOX_PCI_BASE_ADDRESS_1: case VBOX_PCI_BASE_ADDRESS_1+1: case VBOX_PCI_BASE_ADDRESS_1+2: case VBOX_PCI_BASE_ADDRESS_1+3:
1777	case VBOX_PCI_BASE_ADDRESS_2: case VBOX_PCI_BASE_ADDRESS_2+1: case VBOX_PCI_BASE_ADDRESS_2+2: case VBOX_PCI_BASE_ADDRESS_2+3:
1778	case VBOX_PCI_BASE_ADDRESS_3: case VBOX_PCI_BASE_ADDRESS_3+1: case VBOX_PCI_BASE_ADDRESS_3+2: case VBOX_PCI_BASE_ADDRESS_3+3:
1779	case VBOX_PCI_BASE_ADDRESS_4: case VBOX_PCI_BASE_ADDRESS_4+1: case VBOX_PCI_BASE_ADDRESS_4+2: case VBOX_PCI_BASE_ADDRESS_4+3:
1780	case VBOX_PCI_BASE_ADDRESS_5: case VBOX_PCI_BASE_ADDRESS_5+1: case VBOX_PCI_BASE_ADDRESS_5+2: case VBOX_PCI_BASE_ADDRESS_5+3:
1781	case VBOX_PCI_SUBSYSTEM_VENDOR_ID: case VBOX_PCI_SUBSYSTEM_VENDOR_ID+1:
1782	case VBOX_PCI_SUBSYSTEM_ID: case VBOX_PCI_SUBSYSTEM_ID+1:
1783	case VBOX_PCI_ROM_ADDRESS: case VBOX_PCI_ROM_ADDRESS+1: case VBOX_PCI_ROM_ADDRESS+2: case VBOX_PCI_ROM_ADDRESS+3:
1784	case VBOX_PCI_CAPABILITY_LIST:
1785	case VBOX_PCI_INTERRUPT_PIN:
1786	fWritable = false;
1787	break;
1788	/* Others can be written */
1789	default:
1790	fWritable = true;
1791	break;
1792	}
1793	break;
1794	default:
1795	case 0x01: /* PCI-PCI bridge */
1796	switch (addr)
1797	{
1798	/* Read-only registers */
1799	case VBOX_PCI_VENDOR_ID: case VBOX_PCI_VENDOR_ID+1:
1800	case VBOX_PCI_DEVICE_ID: case VBOX_PCI_DEVICE_ID+1:
1801	case VBOX_PCI_REVISION_ID:
1802	case VBOX_PCI_CLASS_PROG:
1803	case VBOX_PCI_CLASS_SUB:
1804	case VBOX_PCI_CLASS_BASE:
1805	case VBOX_PCI_HEADER_TYPE:
1806	case VBOX_PCI_ROM_ADDRESS_BR: case VBOX_PCI_ROM_ADDRESS_BR+1: case VBOX_PCI_ROM_ADDRESS_BR+2: case VBOX_PCI_ROM_ADDRESS_BR+3:
1807	case VBOX_PCI_INTERRUPT_PIN:
1808	fWritable = false;
1809	break;
1810	default:
1811	fWritable = true;
1812	break;
1813	}
1814	break;
1815	}
1816
1817	uint8_t u8Val = (uint8_t)val;
1818
1819	switch (addr)
1820	{
1821	case VBOX_PCI_COMMAND: /* Command register, bits 0-7. */
1822	fUpdateMappings = true;
1823	PCIDevSetByte(aDev, addr, u8Val);
1824	break;
1825	case VBOX_PCI_COMMAND+1: /* Command register, bits 8-15. */
1826	/* don't change reserved bits (11-15) */
1827	u8Val &= UINT32_C(~0xf8);
1828	fUpdateMappings = true;
1829	PCIDevSetByte(aDev, addr, u8Val);
1830	break;
1831	case VBOX_PCI_STATUS: /* Status register, bits 0-7. */
1832	/* don't change read-only bits => actually all lower bits are read-only */
1833	u8Val &= UINT32_C(~0xff);
1834	/* status register, low part: clear bits by writing a '1' to the corresponding bit */
1835	aDev->config[addr] &= ~u8Val;
1836	break;
1837	case VBOX_PCI_STATUS+1: /* Status register, bits 8-15. */
1838	/* don't change read-only bits */
1839	u8Val &= UINT32_C(~0x06);
1840	/* status register, high part: clear bits by writing a '1' to the corresponding bit */
1841	aDev->config[addr] &= ~u8Val;
1842	break;
1843	default:
1844	if (fWritable)
1845	PCIDevSetByte(aDev, addr, u8Val);
1846	}
1847	addr++;
1848	val >>= 8;
1849	}
1850
1851	if (fUpdateMappings)
1852	/* if the command register is modified, we must modify the mappings */
1853	ich9pciUpdateMappings(aDev);
1854	}
1855
1856	/* Slot/functions assignment per table at p. 12 of ICH9 family spec update */
1857	static const struct {
1858	const char* pszName;
1859	int32_t iSlot;
1860	int32_t iFunction;
1861	} PciSlotAssignments[] = {
1862	{
1863	"lan", 25, 0 /* LAN controller */
1864	},
1865	{
1866	"hda", 27, 0 /* High Definition Audio */
1867	},
1868	{
1869	"i82801", 30, 0 /* Host Controller */
1870	},
1871	/**
1872	* Please note, that for devices being functions, like we do here, device 0
1873	* must be multifunction, i.e. have header type 0x80. Our LPC device is.
1874	* Alternative approach is to assign separate slot to each device.
1875	*/
1876	{
1877	"lpc", 31, 0 /* Low Pin Count bus */
1878	},
1879	{
1880	"piix3ide", 31, 1 /* IDE controller */
1881	},
1882	/* Disable, if we may wish to have multiple AHCI controllers */
1883	#if 1
1884	{
1885	"ahci", 31, 2 /* SATA controller */
1886	},
1887	#endif
1888	{
1889	"smbus", 31, 3 /* System Management Bus */
1890	},
1891	{
1892	"usb-ohci", 31, 4 /* OHCI USB controller */
1893	},
1894	{
1895	"usb-ehci", 31, 5 /* EHCI USB controller */
1896	},
1897	{
1898	"thermal", 31, 6 /* Thermal controller */
1899	},
1900	};
1901
1902	static int assignPosition(PPCIBUS pBus, PPCIDEVICE pPciDev, const char *pszName, int iDevFn)
1903	{
1904	/* Hardcoded slots/functions, per chipset spec */
1905	for (size_t i = 0; i < RT_ELEMENTS(PciSlotAssignments); i++)
1906	{
1907	if (!strcmp(pszName, PciSlotAssignments[i].pszName))
1908	{
1909	PCISetRequestedDevfunc(pPciDev);
1910	return (PciSlotAssignments[i].iSlot << 3) + PciSlotAssignments[i].iFunction;
1911	}
1912	}
1913
1914	if (iDevFn >=0 && iDevFn < (int)RT_ELEMENTS(pBus->apDevices))
1915	return iDevFn;
1916
1917	/* Otherwise when assigning a slot, we need to make sure all its functions are available */
1918	for (int iPos = 0; iPos < (int)RT_ELEMENTS(pBus->apDevices); iPos += 8)
1919	{
1920	if ( !pBus->apDevices[iPos]
1921	&& !pBus->apDevices[iPos + 1]
1922	&& !pBus->apDevices[iPos + 2]
1923	&& !pBus->apDevices[iPos + 3]
1924	&& !pBus->apDevices[iPos + 4]
1925	&& !pBus->apDevices[iPos + 5]
1926	&& !pBus->apDevices[iPos + 6]
1927	&& !pBus->apDevices[iPos + 7])
1928	{
1929	PCIClearRequestedDevfunc(pPciDev);
1930	return iPos;
1931	}
1932	}
1933
1934	return -1;
1935	}
1936
1937	static bool hasHardAssignedDevsInSlot(PPCIBUS pBus, int iSlot)
1938	{
1939	PCIDevice** aSlot = &pBus->apDevices[iSlot << 3];
1940
1941	return (aSlot[0] && PCIIsRequestedDevfunc(aSlot[0]))
1942	\|\| (aSlot[1] && PCIIsRequestedDevfunc(aSlot[1]))
1943	\|\| (aSlot[2] && PCIIsRequestedDevfunc(aSlot[2]))
1944	\|\| (aSlot[3] && PCIIsRequestedDevfunc(aSlot[3]))
1945	\|\| (aSlot[4] && PCIIsRequestedDevfunc(aSlot[4]))
1946	\|\| (aSlot[5] && PCIIsRequestedDevfunc(aSlot[5]))
1947	\|\| (aSlot[6] && PCIIsRequestedDevfunc(aSlot[6]))
1948	\|\| (aSlot[7] && PCIIsRequestedDevfunc(aSlot[7]))
1949	;
1950	}
1951
1952	static int ich9pciRegisterInternal(PPCIBUS pBus, int iDev, PPCIDEVICE pPciDev, const char *pszName)
1953	{
1954	/*
1955	* Find device position
1956	*/
1957	iDev = assignPosition(pBus, pPciDev, pszName, iDev);
1958	if (iDev < 0)
1959	{
1960	AssertMsgFailed(("Couldn't find free spot!\n"));
1961	return VERR_PDM_TOO_PCI_MANY_DEVICES;
1962	}
1963
1964	/*
1965	* Check if we can really take this slot, possibly by relocating
1966	* its current habitant, if it wasn't hard assigned too.
1967	*/
1968	if (PCIIsRequestedDevfunc(pPciDev) &&
1969	pBus->apDevices[iDev] &&
1970	PCIIsRequestedDevfunc(pBus->apDevices[iDev]))
1971	{
1972	AssertReleaseMsgFailed(("Configuration error:'%s' and '%s' are both configured as device %d\n",
1973	pszName, pBus->apDevices[iDev]->name, iDev));
1974	return VERR_INTERNAL_ERROR;
1975	}
1976
1977	if (pBus->apDevices[iDev])
1978	{
1979	/* if we got here, we shall (and usually can) relocate the device */
1980	int iRelDev = assignPosition(pBus, pBus->apDevices[iDev], pBus->apDevices[iDev]->name, -1);
1981	if (iRelDev < 0 \|\| iRelDev == iDev)
1982	{
1983	AssertMsgFailed(("Couldn't find free spot!\n"));
1984	return VERR_PDM_TOO_PCI_MANY_DEVICES;
1985	}
1986	/* Copy device function by function to its new position */
1987	for (int i = 0; i < 8; i++)
1988	{
1989	if (!pBus->apDevices[iDev + i])
1990	continue;
1991	Log(("PCI: relocating '%s' from slot %#x to %#x\n", pBus->apDevices[iDev + i]->name, iDev + i, iRelDev + i));
1992	pBus->apDevices[iRelDev + i] = pBus->apDevices[iDev + i];
1993	pBus->apDevices[iRelDev + i]->devfn = iRelDev + i;
1994	pBus->apDevices[iDev + i] = NULL;
1995	}
1996	}
1997
1998	/*
1999	* Fill in device information.
2000	*/
2001	pPciDev->devfn = iDev;
2002	pPciDev->name = pszName;
2003	pPciDev->Int.s.pBusR3 = pBus;
2004	pPciDev->Int.s.pBusR0 = MMHyperR3ToR0(PDMDevHlpGetVM(pBus->CTX_SUFF(pDevIns)), pBus);
2005	pPciDev->Int.s.pBusRC = MMHyperR3ToRC(PDMDevHlpGetVM(pBus->CTX_SUFF(pDevIns)), pBus);
2006	pPciDev->Int.s.pfnConfigRead = ich9pciConfigReadDev;
2007	pPciDev->Int.s.pfnConfigWrite = ich9pciConfigWriteDev;
2008	pBus->apDevices[iDev] = pPciDev;
2009	if (PCIIsPci2PciBridge(pPciDev))
2010	{
2011	AssertMsg(pBus->cBridges < RT_ELEMENTS(pBus->apDevices), ("Number of bridges exceeds the number of possible devices on the bus\n"));
2012	AssertMsg(pPciDev->Int.s.pfnBridgeConfigRead && pPciDev->Int.s.pfnBridgeConfigWrite,
2013	("device is a bridge but does not implement read/write functions\n"));
2014	pBus->papBridgesR3[pBus->cBridges] = pPciDev;
2015	pBus->cBridges++;
2016	}
2017
2018	Log(("PCI: Registered device %d function %d (%#x) '%s'.\n",
2019	iDev >> 3, iDev & 7, 0x80000000 \| (iDev << 8), pszName));
2020
2021	return VINF_SUCCESS;
2022	}
2023
2024
2025	/**
2026	* Info handler, device version.
2027	*
2028	* @param pDevIns Device instance which registered the info.
2029	* @param pHlp Callback functions for doing output.
2030	* @param pszArgs Argument string. Optional and specific to the handler.
2031	*/
2032	static DECLCALLBACK(void) ich9pciInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
2033	{
2034	PPCIBUS pBus = DEVINS_2_PCIBUS(pDevIns);
2035	uint32_t iBus = 0, iDev;
2036
2037
2038	for (iDev = 0; iDev < RT_ELEMENTS(pBus->apDevices); iDev++)
2039	{
2040	PPCIDEVICE pPciDev = pBus->apDevices[iDev];
2041	if (pPciDev != NULL)
2042	pHlp->pfnPrintf(pHlp, "%02x:%02x:%02x %s: %x-%x\n",
2043	iBus, (iDev >> 3) & 0xff, iDev & 0x7,
2044	pPciDev->name,
2045	PCIDevGetVendorId(pPciDev), PCIDevGetDeviceId(pPciDev)
2046	);
2047	}
2048	}
2049
2050
2051	static DECLCALLBACK(int) ich9pciConstruct(PPDMDEVINS pDevIns,
2052	int iInstance,
2053	PCFGMNODE pCfg)
2054	{
2055	int rc;
2056	Assert(iInstance == 0);
2057
2058	/*
2059	* Validate and read configuration.
2060	*/
2061	if (!CFGMR3AreValuesValid(pCfg,
2062	"IOAPIC\0"
2063	"GCEnabled\0"
2064	"R0Enabled\0"
2065	"McfgBase\0"
2066	"McfgLength\0"
2067	))
2068	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
2069
2070	/* query whether we got an IOAPIC */
2071	bool fUseIoApic;
2072	rc = CFGMR3QueryBoolDef(pCfg, "IOAPIC", &fUseIoApic, false);
2073	if (RT_FAILURE(rc))
2074	return PDMDEV_SET_ERROR(pDevIns, rc,
2075	N_("Configuration error: Failed to query boolean value \"IOAPIC\""));
2076
2077	/* check if RC code is enabled. */
2078	bool fGCEnabled;
2079	rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
2080	if (RT_FAILURE(rc))
2081	return PDMDEV_SET_ERROR(pDevIns, rc,
2082	N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
2083
2084	/* check if R0 code is enabled. */
2085	bool fR0Enabled;
2086	rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
2087	if (RT_FAILURE(rc))
2088	return PDMDEV_SET_ERROR(pDevIns, rc,
2089	N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
2090
2091	Log(("PCI: fUseIoApic=%RTbool fGCEnabled=%RTbool fR0Enabled=%RTbool\n", fUseIoApic, fGCEnabled, fR0Enabled));
2092
2093	/*
2094	* Init data.
2095	*/
2096	PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
2097	PPCIBUS pBus = &pGlobals->aPciBus;
2098	/* Zero out everything */
2099	memset(pGlobals, 0, sizeof(*pGlobals));
2100	/* And fill values */
2101	if (!fUseIoApic)
2102	return PDMDEV_SET_ERROR(pDevIns, rc,
2103	N_("Must use IO-APIC with ICH9 chipset"));
2104	rc = CFGMR3QueryU64Def(pCfg, "McfgBase", &pGlobals->u64PciConfigMMioAddress, 0);
2105	if (RT_FAILURE(rc))
2106	return PDMDEV_SET_ERROR(pDevIns, rc,
2107	N_("Configuration error: Failed to read \"McfgBase\""));
2108	rc = CFGMR3QueryU64Def(pCfg, "McfgLength", &pGlobals->u64PciConfigMMioLength, 0);
2109	if (RT_FAILURE(rc))
2110	return PDMDEV_SET_ERROR(pDevIns, rc,
2111	N_("Configuration error: Failed to read \"McfgLength\""));
2112
2113	pGlobals->pDevInsR3 = pDevIns;
2114	pGlobals->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2115	pGlobals->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2116
2117	pGlobals->aPciBus.pDevInsR3 = pDevIns;
2118	pGlobals->aPciBus.pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2119	pGlobals->aPciBus.pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2120	pGlobals->aPciBus.papBridgesR3 = (PPCIDEVICE )PDMDevHlpMMHeapAllocZ(pDevIns, sizeof(PPCIDEVICE) RT_ELEMENTS(pGlobals->aPciBus.apDevices));
2121
2122	/*
2123	* Register bus
2124	*/
2125	PDMPCIBUSREG PciBusReg;
2126	PciBusReg.u32Version = PDM_PCIBUSREG_VERSION;
2127	PciBusReg.pfnRegisterR3 = ich9pciRegister;
2128	PciBusReg.pfnRegisterMsiR3 = ich9pciRegisterMsi;
2129	PciBusReg.pfnIORegionRegisterR3 = ich9pciIORegionRegister;
2130	PciBusReg.pfnSetConfigCallbacksR3 = ich9pciSetConfigCallbacks;
2131	PciBusReg.pfnSetIrqR3 = ich9pciSetIrq;
2132	PciBusReg.pfnSaveExecR3 = ich9pciGenericSaveExec;
2133	PciBusReg.pfnLoadExecR3 = ich9pciGenericLoadExec;
2134	PciBusReg.pfnFakePCIBIOSR3 = ich9pciFakePCIBIOS;
2135	PciBusReg.pszSetIrqRC = fGCEnabled ? "ich9pciSetIrq" : NULL;
2136	PciBusReg.pszSetIrqR0 = fR0Enabled ? "ich9pciSetIrq" : NULL;
2137	rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBus->pPciHlpR3);
2138	if (RT_FAILURE(rc))
2139	return PDMDEV_SET_ERROR(pDevIns, rc,
2140	N_("Failed to register ourselves as a PCI Bus"));
2141	if (pBus->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
2142	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
2143	N_("PCI helper version mismatch; got %#x expected %#x"),
2144	pBus->pPciHlpR3->u32Version, PDM_PCIHLPR3_VERSION);
2145
2146	pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
2147	pBus->pPciHlpR0 = pBus->pPciHlpR3->pfnGetR0Helpers(pDevIns);
2148
2149	/*
2150	* Fill in PCI configs and add them to the bus.
2151	*/
2152
2153	/**
2154	* We emulate 82801IB ICH9 IO chip used in Q35,
2155	* see http://ark.intel.com/Product.aspx?id=31892
2156	*
2157	* Stepping S-Spec Top Marking
2158	*
2159	* A2 SLA9M NH82801IB
2160	*/
2161	PCIDevSetVendorId( &pBus->aPciDev, 0x8086); /* Intel */
2162	PCIDevSetDeviceId( &pBus->aPciDev, 0x244e); /* Desktop */
2163	PCIDevSetRevisionId(&pBus->aPciDev, 0x92); /* rev. A2 */
2164	PCIDevSetClassSub( &pBus->aPciDev, 0x00); /* Host/PCI bridge */
2165	PCIDevSetClassBase( &pBus->aPciDev, 0x06); /* bridge */
2166	PCIDevSetHeaderType(&pBus->aPciDev, 0x00); /* normal device */
2167
2168	pBus->aPciDev.pDevIns = pDevIns;
2169	/* We register Host<->PCI controller on the bus */
2170	ich9pciRegisterInternal(pBus, -1, &pBus->aPciDev, "i82801");
2171
2172	/*
2173	* Register I/O ports and save state.
2174	*/
2175	rc = PDMDevHlpIOPortRegister(pDevIns, 0x0cf8, 1, NULL, ich9pciIOPortAddressWrite, ich9pciIOPortAddressRead, NULL, NULL, "ICH9 (PCI)");
2176	if (RT_FAILURE(rc))
2177	return rc;
2178	rc = PDMDevHlpIOPortRegister(pDevIns, 0x0cfc, 4, NULL, ich9pciIOPortDataWrite, ich9pciIOPortDataRead, NULL, NULL, "ICH9 (PCI)");
2179	if (RT_FAILURE(rc))
2180	return rc;
2181	if (fGCEnabled)
2182	{
2183	rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x0cf8, 1, NIL_RTGCPTR, "ich9pciIOPortAddressWrite", "ich9pciIOPortAddressRead", NULL, NULL, "ICH9 (PCI)");
2184	if (RT_FAILURE(rc))
2185	return rc;
2186	rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x0cfc, 4, NIL_RTGCPTR, "ich9pciIOPortDataWrite", "ich9pciIOPortDataRead", NULL, NULL, "ICH9 (PCI)");
2187	if (RT_FAILURE(rc))
2188	return rc;
2189	}
2190	if (fR0Enabled)
2191	{
2192	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x0cf8, 1, NIL_RTR0PTR, "ich9pciIOPortAddressWrite", "ich9pciIOPortAddressRead", NULL, NULL, "ICH9 (PCI)");
2193	if (RT_FAILURE(rc))
2194	return rc;
2195	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x0cfc, 4, NIL_RTR0PTR, "ich9pciIOPortDataWrite", "ich9pciIOPortDataRead", NULL, NULL, "ICH9 (PCI)");
2196	if (RT_FAILURE(rc))
2197	return rc;
2198	}
2199
2200	if (pGlobals->u64PciConfigMMioAddress != 0)
2201	{
2202	rc = PDMDevHlpMMIORegister(pDevIns,
2203	pGlobals->u64PciConfigMMioAddress,
2204	pGlobals->u64PciConfigMMioLength,
2205	0,
2206	ich9pciMcfgMMIOWrite,
2207	ich9pciMcfgMMIORead,
2208	NULL /* fill */,
2209	"MCFG ranges");
2210	if (RT_FAILURE(rc))
2211	{
2212	AssertMsgRC(rc, ("Cannot register MCFG MMIO: %Rrc\n", rc));
2213	return rc;
2214	}
2215
2216	if (fGCEnabled)
2217	{
2218
2219	rc = PDMDevHlpMMIORegisterRC(pDevIns,
2220	pGlobals->u64PciConfigMMioAddress,
2221	pGlobals->u64PciConfigMMioLength,
2222	0,
2223	"ich9pciMcfgMMIOWrite",
2224	"ich9pciMcfgMMIORead",
2225	NULL /* fill */);
2226	if (RT_FAILURE(rc))
2227	{
2228	AssertMsgRC(rc, ("Cannot register MCFG MMIO (GC): %Rrc\n", rc));
2229	return rc;
2230	}
2231	}
2232
2233
2234	if (fR0Enabled)
2235	{
2236
2237	rc = PDMDevHlpMMIORegisterR0(pDevIns,
2238	pGlobals->u64PciConfigMMioAddress,
2239	pGlobals->u64PciConfigMMioLength,
2240	0,
2241	"ich9pciMcfgMMIOWrite",
2242	"ich9pciMcfgMMIORead",
2243	NULL /* fill */);
2244	if (RT_FAILURE(rc))
2245	{
2246	AssertMsgRC(rc, ("Cannot register MCFG MMIO (R0): %Rrc\n", rc));
2247	return rc;
2248	}
2249	}
2250	}
2251
2252	rc = PDMDevHlpSSMRegisterEx(pDevIns, VBOX_ICH9PCI_SAVED_STATE_VERSION_CURRENT,
2253	sizeof(pBus) + 16128, "pgm",
2254	NULL, NULL, NULL,
2255	NULL, ich9pciR3SaveExec, NULL,
2256	NULL, ich9pciR3LoadExec, NULL);
2257	if (RT_FAILURE(rc))
2258	return rc;
2259
2260
2261	/** @todo: other chipset devices shall be registered too */
2262	/** @todo: what to with bridges? */
2263
2264	PDMDevHlpDBGFInfoRegister(pDevIns, "pci", "Display PCI bus status. (no arguments)", ich9pciInfo);
2265
2266	return VINF_SUCCESS;
2267	}
2268
2269	static void ich9pciResetDevice(PPCIDEVICE pDev)
2270	{
2271	pDev->config[VBOX_PCI_COMMAND] &= ~(VBOX_PCI_COMMAND_IO \| VBOX_PCI_COMMAND_MEMORY \|
2272	VBOX_PCI_COMMAND_MASTER);
2273
2274	if (!PCIIsPci2PciBridge(pDev))
2275	{
2276	PCIDevSetByte(pDev, VBOX_PCI_CACHE_LINE_SIZE, 0x0);
2277	PCIDevSetByte(pDev, VBOX_PCI_INTERRUPT_LINE, 0x0);
2278	}
2279	/* Regions ? */
2280	}
2281
2282
2283	/**
2284	* @copydoc FNPDMDEVRESET
2285	*/
2286	static DECLCALLBACK(void) ich9pciReset(PPDMDEVINS pDevIns)
2287	{
2288	PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
2289	PPCIBUS pBus = &pGlobals->aPciBus;
2290
2291	/* Relocate RC pointers for the attached pci devices. */
2292	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
2293	{
2294	if (pBus->apDevices[i])
2295	ich9pciResetDevice(pBus->apDevices[i]);
2296	}
2297	}
2298
2299	/**
2300	* @copydoc FNPDMDEVRELOCATE
2301	*/
2302	static DECLCALLBACK(void) ich9pciRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
2303	{
2304	PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
2305	PPCIBUS pBus = &pGlobals->aPciBus;
2306	pGlobals->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2307
2308	pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
2309	pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2310
2311	/* Relocate RC pointers for the attached pci devices. */
2312	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
2313	{
2314	if (pBus->apDevices[i])
2315	pBus->apDevices[i]->Int.s.pBusRC += offDelta;
2316	}
2317
2318	}
2319
2320	/**
2321	* @interface_method_impl{PDMDEVREG,pfnConstruct}
2322	*/
2323	static DECLCALLBACK(int) ich9pcibridgeConstruct(PPDMDEVINS pDevIns,
2324	int iInstance,
2325	PCFGMNODE pCfg)
2326	{
2327	int rc;
2328
2329	/*
2330	* Validate and read configuration.
2331	*/
2332	if (!CFGMR3AreValuesValid(pCfg, "GCEnabled\0" "R0Enabled\0"))
2333	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
2334
2335	/* check if RC code is enabled. */
2336	bool fGCEnabled;
2337	rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
2338	if (RT_FAILURE(rc))
2339	return PDMDEV_SET_ERROR(pDevIns, rc,
2340	N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
2341
2342	/* check if R0 code is enabled. */
2343	bool fR0Enabled;
2344	rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
2345	if (RT_FAILURE(rc))
2346	return PDMDEV_SET_ERROR(pDevIns, rc,
2347	N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
2348	Log(("PCI: fGCEnabled=%RTbool fR0Enabled=%RTbool\n", fGCEnabled, fR0Enabled));
2349
2350	/*
2351	* Init data and register the PCI bus.
2352	*/
2353	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
2354	pBus->pDevInsR3 = pDevIns;
2355	pBus->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2356	pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2357	pBus->papBridgesR3 = (PPCIDEVICE )PDMDevHlpMMHeapAllocZ(pDevIns, sizeof(PPCIDEVICE) RT_ELEMENTS(pBus->apDevices));
2358
2359	PDMPCIBUSREG PciBusReg;
2360	PciBusReg.u32Version = PDM_PCIBUSREG_VERSION;
2361	PciBusReg.pfnRegisterR3 = ich9pcibridgeRegister;
2362	PciBusReg.pfnRegisterMsiR3 = ich9pciRegisterMsi;
2363	PciBusReg.pfnIORegionRegisterR3 = ich9pciIORegionRegister;
2364	PciBusReg.pfnSetConfigCallbacksR3 = ich9pciSetConfigCallbacks;
2365	PciBusReg.pfnSetIrqR3 = ich9pcibridgeSetIrq;
2366	PciBusReg.pfnSaveExecR3 = ich9pciGenericSaveExec;
2367	PciBusReg.pfnLoadExecR3 = ich9pciGenericLoadExec;
2368	PciBusReg.pfnFakePCIBIOSR3 = NULL; /* Only needed for the first bus. */
2369	PciBusReg.pszSetIrqRC = fGCEnabled ? "ich9pcibridgeSetIrq" : NULL;
2370	PciBusReg.pszSetIrqR0 = fR0Enabled ? "ich9pcibridgeSetIrq" : NULL;
2371	rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBus->pPciHlpR3);
2372	if (RT_FAILURE(rc))
2373	return PDMDEV_SET_ERROR(pDevIns, rc,
2374	N_("Failed to register ourselves as a PCI Bus"));
2375	if (pBus->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
2376	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
2377	N_("PCI helper version mismatch; got %#x expected %#x"),
2378	pBus->pPciHlpR3->u32Version, PDM_PCIHLPR3_VERSION);
2379
2380	pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
2381	pBus->pPciHlpR0 = pBus->pPciHlpR3->pfnGetR0Helpers(pDevIns);
2382
2383	/*
2384	* Fill in PCI configs and add them to the bus.
2385	*/
2386	PCIDevSetVendorId( &pBus->aPciDev, 0x8086); /* Intel */
2387	PCIDevSetDeviceId( &pBus->aPciDev, 0x2448); /* 82801 Mobile PCI bridge. */
2388	PCIDevSetRevisionId(&pBus->aPciDev, 0xf2);
2389	PCIDevSetClassSub( &pBus->aPciDev, 0x04); /* pci2pci */
2390	PCIDevSetClassBase( &pBus->aPciDev, 0x06); /* PCI_bridge */
2391	PCIDevSetClassProg( &pBus->aPciDev, 0x01); /* Supports subtractive decoding. */
2392	PCIDevSetHeaderType(&pBus->aPciDev, 0x01); /* Single function device which adheres to the PCI-to-PCI bridge spec. */
2393	PCIDevSetCommand( &pBus->aPciDev, 0x00);
2394	PCIDevSetStatus( &pBus->aPciDev, 0x20); /* 66MHz Capable. */
2395	PCIDevSetInterruptLine(&pBus->aPciDev, 0x00); /* This device does not assert interrupts. */
2396
2397	/*
2398	* This device does not generate interrupts. Interrupt delivery from
2399	* devices attached to the bus is unaffected.
2400	*/
2401	PCIDevSetInterruptPin (&pBus->aPciDev, 0x00);
2402
2403	pBus->aPciDev.pDevIns = pDevIns;
2404
2405	/* Bridge-specific data */
2406	PCISetPci2PciBridge(&pBus->aPciDev);
2407	pBus->aPciDev.Int.s.pfnBridgeConfigRead = ich9pcibridgeConfigRead;
2408	pBus->aPciDev.Int.s.pfnBridgeConfigWrite = ich9pcibridgeConfigWrite;
2409
2410	/*
2411	* Register this PCI bridge. The called function will take care on which bus we will get registered.
2412	*/
2413	rc = PDMDevHlpPCIRegister (pDevIns, &pBus->aPciDev);
2414	if (RT_FAILURE(rc))
2415	return rc;
2416
2417	/*
2418	* The iBus property doesn't really represent the bus number
2419	* because the guest and the BIOS can choose different bus numbers
2420	* for them.
2421	* The bus number is mainly for the setIrq function to indicate
2422	* when the host bus is reached which will have iBus = 0.
2423	* Thathswhy the + 1.
2424	*/
2425	pBus->iBus = iInstance + 1;
2426
2427	/*
2428	* Register SSM handlers. We use the same saved state version as for the host bridge
2429	* to make changes easier.
2430	*/
2431	rc = PDMDevHlpSSMRegisterEx(pDevIns, VBOX_ICH9PCI_SAVED_STATE_VERSION_CURRENT,
2432	sizeof(pBus) + 16128,
2433	"pgm" /* before */,
2434	NULL, NULL, NULL,
2435	NULL, ich9pcibridgeR3SaveExec, NULL,
2436	NULL, ich9pcibridgeR3LoadExec, NULL);
2437	if (RT_FAILURE(rc))
2438	return rc;
2439
2440
2441	return VINF_SUCCESS;
2442	}
2443
2444	/**
2445	* @copydoc FNPDMDEVRESET
2446	*/
2447	static DECLCALLBACK(void) ich9pcibridgeReset(PPDMDEVINS pDevIns)
2448	{
2449	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
2450
2451	/* Reset config space to default values. */
2452	PCIDevSetByte(&pBus->aPciDev, VBOX_PCI_PRIMARY_BUS, 0);
2453	PCIDevSetByte(&pBus->aPciDev, VBOX_PCI_SECONDARY_BUS, 0);
2454	PCIDevSetByte(&pBus->aPciDev, VBOX_PCI_SUBORDINATE_BUS, 0);
2455	}
2456
2457
2458	/**
2459	* @copydoc FNPDMDEVRELOCATE
2460	*/
2461	static DECLCALLBACK(void) ich9pcibridgeRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
2462	{
2463	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
2464	pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2465
2466	/* Relocate RC pointers for the attached pci devices. */
2467	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
2468	{
2469	if (pBus->apDevices[i])
2470	pBus->apDevices[i]->Int.s.pBusRC += offDelta;
2471	}
2472
2473	}
2474
2475	/**
2476	* The PCI bus device registration structure.
2477	*/
2478	const PDMDEVREG g_DevicePciIch9 =
2479	{
2480	/* u32Version */
2481	PDM_DEVREG_VERSION,
2482	/* szName */
2483	"ich9pci",
2484	/* szRCMod */
2485	"VBoxDDGC.gc",
2486	/* szR0Mod */
2487	"VBoxDDR0.r0",
2488	/* pszDescription */
2489	"ICH9 PCI bridge",
2490	/* fFlags */
2491	PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
2492	/* fClass */
2493	PDM_DEVREG_CLASS_BUS_PCI \| PDM_DEVREG_CLASS_BUS_ISA,
2494	/* cMaxInstances */
2495	1,
2496	/* cbInstance */
2497	sizeof(PCIGLOBALS),
2498	/* pfnConstruct */
2499	ich9pciConstruct,
2500	/* pfnDestruct */
2501	NULL,
2502	/* pfnRelocate */
2503	ich9pciRelocate,
2504	/* pfnIOCtl */
2505	NULL,
2506	/* pfnPowerOn */
2507	NULL,
2508	/* pfnReset */
2509	ich9pciReset,
2510	/* pfnSuspend */
2511	NULL,
2512	/* pfnResume */
2513	NULL,
2514	/* pfnAttach */
2515	NULL,
2516	/* pfnDetach */
2517	NULL,
2518	/* pfnQueryInterface */
2519	NULL,
2520	/* pfnInitComplete */
2521	NULL,
2522	/* pfnPowerOff */
2523	NULL,
2524	/* pfnSoftReset */
2525	NULL,
2526	/* u32VersionEnd */
2527	PDM_DEVREG_VERSION
2528	};
2529
2530	/**
2531	* The device registration structure
2532	* for the PCI-to-PCI bridge.
2533	*/
2534	const PDMDEVREG g_DevicePciIch9Bridge =
2535	{
2536	/* u32Version */
2537	PDM_DEVREG_VERSION,
2538	/* szName */
2539	"ich9pcibridge",
2540	/* szRCMod */
2541	"VBoxDDGC.gc",
2542	/* szR0Mod */
2543	"VBoxDDR0.r0",
2544	/* pszDescription */
2545	"ICH9 PCI to PCI bridge",
2546	/* fFlags */
2547	PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
2548	/* fClass */
2549	PDM_DEVREG_CLASS_BUS_PCI,
2550	/* cMaxInstances */
2551	~0,
2552	/* cbInstance */
2553	sizeof(PCIBUS),
2554	/* pfnConstruct */
2555	ich9pcibridgeConstruct,
2556	/* pfnDestruct */
2557	NULL,
2558	/* pfnRelocate */
2559	ich9pcibridgeRelocate,
2560	/* pfnIOCtl */
2561	NULL,
2562	/* pfnPowerOn */
2563	NULL,
2564	/* pfnReset */
2565	ich9pcibridgeReset,
2566	/* pfnSuspend */
2567	NULL,
2568	/* pfnResume */
2569	NULL,
2570	/* pfnAttach */
2571	NULL,
2572	/* pfnDetach */
2573	NULL,
2574	/* pfnQueryInterface */
2575	NULL,
2576	/* pfnInitComplete */
2577	NULL,
2578	/* pfnPowerOff */
2579	NULL,
2580	/* pfnSoftReset */
2581	NULL,
2582	/* u32VersionEnd */
2583	PDM_DEVREG_VERSION
2584	};
2585
2586	#endif /* IN_RING3 */
2587	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */

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source: vbox/trunk/src/VBox/Devices/Bus/DevPciIch9.cpp@ 33203

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