DevPciIch9.cpp@ 33215

Last change on this file since 33215 was 33215, checked in by vboxsync, 14 years ago
PCI: fixed few MSI-related bugs, now SLES boots fine with MSI SATA
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1	/* $Id: DevPciIch9.cpp 33215 2010-10-18 17:51:24Z vboxsync $ */
2	/** @file
3	* DevPCI - ICH9 southbridge PCI bus emulation Device.
4	*/
5
6	/*
7	* Copyright (C) 2010 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/*******************************************************************************
19	* Header Files *
20	*******************************************************************************/
21	#define LOG_GROUP LOG_GROUP_DEV_PCI
22	/* Hack to get PCIDEVICEINT declare at the right point - include "PCIInternal.h". */
23	#define PCI_INCLUDE_PRIVATE
24	#include <VBox/pci.h>
25	#include <VBox/msi.h>
26	#include <VBox/pdmdev.h>
27	#include <iprt/asm.h>
28	#include <iprt/assert.h>
29	#include <iprt/string.h>
30
31	#include "../Builtins.h"
32
33	#include "MsiCommon.h"
34
35	/**
36	* PCI Bus instance.
37	*/
38	typedef struct PCIBus
39	{
40	/** Bus number. */
41	int32_t iBus;
42	/** Number of bridges attached to the bus. */
43	uint32_t cBridges;
44
45	/** Array of PCI devices. We assume 32 slots, each with 8 functions. */
46	R3PTRTYPE(PPCIDEVICE) apDevices[256];
47	/** Array of bridges attached to the bus. */
48	R3PTRTYPE(PPCIDEVICE *) papBridgesR3;
49
50	/** R3 pointer to the device instance. */
51	PPDMDEVINSR3 pDevInsR3;
52	/** Pointer to the PCI R3 helpers. */
53	PCPDMPCIHLPR3 pPciHlpR3;
54
55	/** R0 pointer to the device instance. */
56	PPDMDEVINSR0 pDevInsR0;
57	/** Pointer to the PCI R0 helpers. */
58	PCPDMPCIHLPR0 pPciHlpR0;
59
60	/** RC pointer to the device instance. */
61	PPDMDEVINSRC pDevInsRC;
62	/** Pointer to the PCI RC helpers. */
63	PCPDMPCIHLPRC pPciHlpRC;
64
65	/** The PCI device for the PCI bridge. */
66	PCIDEVICE aPciDev;
67
68	} PCIBUS, *PPCIBUS;
69
70
71	/** @def PCI_APIC_IRQ_PINS
72	* Number of pins for interrupts if the APIC is used.
73	*/
74	#define PCI_APIC_IRQ_PINS 8
75
76	/**
77	* PCI Globals - This is the host-to-pci bridge and the root bus.
78	*/
79	typedef struct
80	{
81	/** R3 pointer to the device instance. */
82	PPDMDEVINSR3 pDevInsR3;
83	/** R0 pointer to the device instance. */
84	PPDMDEVINSR0 pDevInsR0;
85	/** RC pointer to the device instance. */
86	PPDMDEVINSRC pDevInsRC;
87
88	#if HC_ARCH_BITS == 64
89	uint32_t Alignment0;
90	#endif
91
92	/** I/O APIC irq levels */
93	volatile uint32_t uaPciApicIrqLevels[PCI_APIC_IRQ_PINS];
94
95	#if 1 /* Will be moved into the BIOS soon. */
96	/** The next I/O port address which the PCI BIOS will use. */
97	uint32_t uPciBiosIo;
98	/** The next MMIO address which the PCI BIOS will use. */
99	uint32_t uPciBiosMmio;
100	/** Actual bus number. */
101	uint8_t uBus;
102	#endif
103	/* Physical address of PCI config space MMIO region */
104	uint64_t u64PciConfigMMioAddress;
105	/* Length of PCI config space MMIO region */
106	uint64_t u64PciConfigMMioLength;
107
108
109	/** Config register. */
110	uint32_t uConfigReg;
111
112	/** PCI bus which is attached to the host-to-PCI bridge. */
113	PCIBUS aPciBus;
114
115	} PCIGLOBALS, *PPCIGLOBALS;
116
117
118	typedef struct {
119	uint8_t iBus;
120	uint8_t iDeviceFunc;
121	uint16_t iRegister;
122	} PciAddress;
123
124	/*******************************************************************************
125	* Defined Constants And Macros *
126	*******************************************************************************/
127
128	/** @def VBOX_ICH9PCI_SAVED_STATE_VERSION
129	* Saved state version of the ICH9 PCI bus device.
130	*/
131	#define VBOX_ICH9PCI_SAVED_STATE_VERSION_NOMSI 1
132	#define VBOX_ICH9PCI_SAVED_STATE_VERSION_MSI 2
133	#define VBOX_ICH9PCI_SAVED_STATE_VERSION_CURRENT VBOX_ICH9PCI_SAVED_STATE_VERSION_MSI
134
135	/** Converts a bus instance pointer to a device instance pointer. */
136	#define PCIBUS_2_DEVINS(pPciBus) ((pPciBus)->CTX_SUFF(pDevIns))
137	/** Converts a device instance pointer to a PCIGLOBALS pointer. */
138	#define DEVINS_2_PCIGLOBALS(pDevIns) ((PPCIGLOBALS)(PDMINS_2_DATA(pDevIns, PPCIGLOBALS)))
139	/** Converts a device instance pointer to a PCIBUS pointer. */
140	#define DEVINS_2_PCIBUS(pDevIns) ((PPCIBUS)(&PDMINS_2_DATA(pDevIns, PPCIGLOBALS)->aPciBus))
141	/** Converts a pointer to a PCI root bus instance to a PCIGLOBALS pointer.
142	*/
143	#define PCIROOTBUS_2_PCIGLOBALS(pPciBus) ( (PPCIGLOBALS)((uintptr_t)(pPciBus) - RT_OFFSETOF(PCIGLOBALS, aPciBus)) )
144
145
146	/** @def PCI_LOCK
147	* Acquires the PDM lock. This is a NOP if locking is disabled. */
148	/** @def PCI_UNLOCK
149	* Releases the PDM lock. This is a NOP if locking is disabled. */
150	#define PCI_LOCK(pDevIns, rc) \
151	do { \
152	int rc2 = DEVINS_2_PCIBUS(pDevIns)->CTX_SUFF(pPciHlp)->pfnLock((pDevIns), rc); \
153	if (rc2 != VINF_SUCCESS) \
154	return rc2; \
155	} while (0)
156	#define PCI_UNLOCK(pDevIns) \
157	DEVINS_2_PCIBUS(pDevIns)->CTX_SUFF(pPciHlp)->pfnUnlock(pDevIns)
158
159	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
160
161	RT_C_DECLS_BEGIN
162
163	PDMBOTHCBDECL(void) ich9pciSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel);
164	PDMBOTHCBDECL(void) ich9pcibridgeSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel);
165	PDMBOTHCBDECL(int) ich9pciIOPortAddressWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
166	PDMBOTHCBDECL(int) ich9pciIOPortAddressRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb);
167	PDMBOTHCBDECL(int) ich9pciIOPortDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
168	PDMBOTHCBDECL(int) ich9pciIOPortDataRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb);
169	PDMBOTHCBDECL(int) ich9pciMcfgMMIOWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb);
170	PDMBOTHCBDECL(int) ich9pciMcfgMMIORead (PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb);
171
172	RT_C_DECLS_END
173
174	/* Prototypes */
175	static void ich9pciSetIrqInternal(PPCIGLOBALS pGlobals, uint8_t uDevFn, PPCIDEVICE pPciDev, int iIrq, int iLevel);
176	#ifdef IN_RING3
177	static int ich9pciRegisterInternal(PPCIBUS pBus, int iDev, PPCIDEVICE pPciDev, const char *pszName);
178	static void ich9pciUpdateMappings(PCIDevice *pDev);
179	static DECLCALLBACK(uint32_t) ich9pciConfigReadDev(PCIDevice *aDev, uint32_t u32Address, unsigned len);
180	DECLINLINE(PPCIDEVICE) ich9pciFindBridge(PPCIBUS pBus, uint8_t iBus);
181	static void ich9pciBiosInitDevice(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint8_t cBridgeDepth, uint8_t *paBridgePositions);
182	#endif
183
184	// See 7.2.2. PCI Express Enhanced Configuration Mechanism for details of address
185	// mapping, we take n=6 approach
186	DECLINLINE(void) ich9pciPhysToPciAddr(PPCIGLOBALS pGlobals, RTGCPHYS GCPhysAddr, PciAddress* pPciAddr)
187	{
188	GCPhysAddr = GCPhysAddr - pGlobals->u64PciConfigMMioAddress;
189	pPciAddr->iBus = (GCPhysAddr >> 20) & ((1<<8) - 1);
190	pPciAddr->iDeviceFunc = (GCPhysAddr >> 12) & ((1<<(5+3)) - 1); // 5 bits - device, 3 bits - function
191	pPciAddr->iRegister = (GCPhysAddr >> 0) & ((1<<(6+4+2)) - 1); // 6 bits - register, 4 bits - extended register, 2 bits -Byte Enable
192	}
193
194	DECLINLINE(void) ich9pciStateToPciAddr(PPCIGLOBALS pGlobals, RTGCPHYS addr, PciAddress* pPciAddr)
195	{
196	pPciAddr->iBus = (pGlobals->uConfigReg >> 16) & 0xff;
197	pPciAddr->iDeviceFunc = (pGlobals->uConfigReg >> 8) & 0xff;
198	pPciAddr->iRegister = (pGlobals->uConfigReg & 0xfc) \| (addr & 3);
199	}
200
201	PDMBOTHCBDECL(void) ich9pciSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel)
202	{
203	ich9pciSetIrqInternal(PDMINS_2_DATA(pDevIns, PPCIGLOBALS), pPciDev->devfn, pPciDev, iIrq, iLevel);
204	}
205
206	PDMBOTHCBDECL(void) ich9pcibridgeSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel)
207	{
208	/*
209	* The PCI-to-PCI bridge specification defines how the interrupt pins
210	* are routed from the secondary to the primary bus (see chapter 9).
211	* iIrq gives the interrupt pin the pci device asserted.
212	* We change iIrq here according to the spec and call the SetIrq function
213	* of our parent passing the device which asserted the interrupt instead of the device of the bridge.
214	*/
215	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
216	PPCIDEVICE pPciDevBus = pPciDev;
217	int iIrqPinBridge = iIrq;
218	uint8_t uDevFnBridge = 0;
219
220	/* Walk the chain until we reach the host bus. */
221	do
222	{
223	uDevFnBridge = pBus->aPciDev.devfn;
224	iIrqPinBridge = ((pPciDevBus->devfn >> 3) + iIrqPinBridge) & 3;
225
226	/* Get the parent. */
227	pBus = pBus->aPciDev.Int.s.CTX_SUFF(pBus);
228	pPciDevBus = &pBus->aPciDev;
229	} while (pBus->iBus != 0);
230
231	AssertMsgReturnVoid(pBus->iBus == 0, ("This is not the host pci bus iBus=%d\n", pBus->iBus));
232	ich9pciSetIrqInternal(PCIROOTBUS_2_PCIGLOBALS(pBus), uDevFnBridge, pPciDev, iIrqPinBridge, iLevel);
233	}
234
235	/**
236	* Port I/O Handler for PCI address OUT operations.
237	*
238	* @returns VBox status code.
239	*
240	* @param pDevIns The device instance.
241	* @param pvUser User argument - ignored.
242	* @param uPort Port number used for the OUT operation.
243	* @param u32 The value to output.
244	* @param cb The value size in bytes.
245	*/
246	PDMBOTHCBDECL(int) ich9pciIOPortAddressWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
247	{
248	Log(("ich9pciIOPortAddressWrite: Port=%#x u32=%#x cb=%d\n", Port, u32, cb));
249	NOREF(pvUser);
250	if (cb == 4)
251	{
252	PPCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
253	PCI_LOCK(pDevIns, VINF_IOM_HC_IOPORT_WRITE);
254	pThis->uConfigReg = u32 & ~3; /* Bits 0-1 are reserved and we silently clear them */
255	PCI_UNLOCK(pDevIns);
256	}
257	return VINF_SUCCESS;
258	}
259
260	/**
261	* Port I/O Handler for PCI address IN operations.
262	*
263	* @returns VBox status code.
264	*
265	* @param pDevIns The device instance.
266	* @param pvUser User argument - ignored.
267	* @param uPort Port number used for the IN operation.
268	* @param pu32 Where to store the result.
269	* @param cb Number of bytes read.
270	*/
271	PDMBOTHCBDECL(int) ich9pciIOPortAddressRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
272	{
273	NOREF(pvUser);
274	if (cb == 4)
275	{
276	PPCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
277	PCI_LOCK(pDevIns, VINF_IOM_HC_IOPORT_READ);
278	*pu32 = pThis->uConfigReg;
279	PCI_UNLOCK(pDevIns);
280	Log(("pciIOPortAddressRead: Port=%#x cb=%d -> %#x\n", Port, cb, *pu32));
281	return VINF_SUCCESS;
282	}
283
284	Log(("ich9pciIOPortAddressRead: Port=%#x cb=%d VERR_IOM_IOPORT_UNUSED\n", Port, cb));
285
286	return VERR_IOM_IOPORT_UNUSED;
287	}
288
289	static int ich9pciDataWriteAddr(PPCIGLOBALS pGlobals, PciAddress* pAddr, uint32_t val, int len)
290	{
291
292	if (pAddr->iRegister > 0xff)
293	{
294	LogRel(("PCI: attempt to write extended register: %x (%d) <- val\n", pAddr->iRegister, len, val));
295	return 0;
296	}
297
298	if (pAddr->iBus != 0)
299	{
300	if (pGlobals->aPciBus.cBridges)
301	{
302	#ifdef IN_RING3 /** @todo do lookup in R0/RC too! */
303	PPCIDEVICE pBridgeDevice = ich9pciFindBridge(&pGlobals->aPciBus, pAddr->iBus);
304	if (pBridgeDevice)
305	{
306	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigWrite);
307	pBridgeDevice->Int.s.pfnBridgeConfigWrite(pBridgeDevice->pDevIns, pAddr->iBus, pAddr->iDeviceFunc, pAddr->iRegister, val, len);
308	}
309	#else
310	return VINF_IOM_HC_IOPORT_WRITE;
311	#endif
312	}
313	}
314	else
315	{
316	if (pGlobals->aPciBus.apDevices[pAddr->iDeviceFunc])
317	{
318	#ifdef IN_RING3
319	R3PTRTYPE(PCIDevice *) aDev = pGlobals->aPciBus.apDevices[pAddr->iDeviceFunc];
320	Log(("ich9pciConfigWrite: %s: addr=%02x val=%08x len=%d\n", aDev->name, pAddr->iRegister, val, len));
321	aDev->Int.s.pfnConfigWrite(aDev, pAddr->iRegister, val, len);
322	#else
323	return VINF_IOM_HC_IOPORT_WRITE;
324	#endif
325	}
326	}
327	return VINF_SUCCESS;
328	}
329
330	static int ich9pciDataWrite(PPCIGLOBALS pGlobals, uint32_t addr, uint32_t val, int len)
331	{
332	PciAddress aPciAddr;
333
334	Log(("ich9pciDataWrite: addr=%08x val=%08x len=%d\n", pGlobals->uConfigReg, val, len));
335
336	if (!(pGlobals->uConfigReg & (1 << 31)))
337	return VINF_SUCCESS;
338
339	if ((pGlobals->uConfigReg & 0x3) != 0)
340	return VINF_SUCCESS;
341
342	/* Compute destination device */
343	ich9pciStateToPciAddr(pGlobals, addr, &aPciAddr);
344
345	return ich9pciDataWriteAddr(pGlobals, &aPciAddr, val, len);
346	}
347
348	/**
349	* Port I/O Handler for PCI data OUT operations.
350	*
351	* @returns VBox status code.
352	*
353	* @param pDevIns The device instance.
354	* @param pvUser User argument - ignored.
355	* @param uPort Port number used for the OUT operation.
356	* @param u32 The value to output.
357	* @param cb The value size in bytes.
358	*/
359	PDMBOTHCBDECL(int) ich9pciIOPortDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
360	{
361	Log(("pciIOPortDataWrite: Port=%#x u32=%#x cb=%d\n", Port, u32, cb));
362	NOREF(pvUser);
363	int rc = VINF_SUCCESS;
364	if (!(Port % cb))
365	{
366	PCI_LOCK(pDevIns, VINF_IOM_HC_IOPORT_WRITE);
367	rc = ich9pciDataWrite(PDMINS_2_DATA(pDevIns, PPCIGLOBALS), Port, u32, cb);
368	PCI_UNLOCK(pDevIns);
369	}
370	else
371	AssertMsgFailed(("Unaligned write to port %#x u32=%#x cb=%d\n", Port, u32, cb));
372	return rc;
373	}
374
375	static int ich9pciDataReadAddr(PPCIGLOBALS pGlobals, PciAddress* pPciAddr, int len, uint32_t *pu32)
376	{
377	if (pPciAddr->iRegister > 0xff)
378	{
379	LogRel(("PCI: attempt to read extended register: %x\n", pPciAddr->iRegister));
380	*pu32 = 0;
381	return 0;
382	}
383
384
385	if (pPciAddr->iBus != 0)
386	{
387	if (pGlobals->aPciBus.cBridges)
388	{
389	#ifdef IN_RING3 /** @todo do lookup in R0/RC too! */
390	PPCIDEVICE pBridgeDevice = ich9pciFindBridge(&pGlobals->aPciBus, pPciAddr->iBus);
391	if (pBridgeDevice)
392	{
393	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigRead);
394	*pu32 = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->pDevIns, pPciAddr->iBus, pPciAddr->iDeviceFunc, pPciAddr->iRegister, len);
395	}
396	#else
397	return VINF_IOM_HC_IOPORT_READ;
398	#endif
399	}
400	}
401	else
402	{
403	if (pGlobals->aPciBus.apDevices[pPciAddr->iDeviceFunc])
404	{
405	#ifdef IN_RING3
406	R3PTRTYPE(PCIDevice *) aDev = pGlobals->aPciBus.apDevices[pPciAddr->iDeviceFunc];
407	*pu32 = aDev->Int.s.pfnConfigRead(aDev, pPciAddr->iRegister, len);
408	Log(("ich9pciDataReadAddr: %s: addr=%02x val=%08x len=%d\n", aDev->name, pPciAddr->iRegister, *pu32, len));
409	#else
410	return VINF_IOM_HC_IOPORT_READ;
411	#endif
412	}
413	}
414
415	return VINF_SUCCESS;
416	}
417
418	static int ich9pciDataRead(PPCIGLOBALS pGlobals, uint32_t addr, int len, uint32_t *pu32)
419	{
420	PciAddress aPciAddr;
421
422	*pu32 = 0xffffffff;
423
424	if (!(pGlobals->uConfigReg & (1 << 31)))
425	return VINF_SUCCESS;
426
427	if ((pGlobals->uConfigReg & 0x3) != 0)
428	return VINF_SUCCESS;
429
430	/* Compute destination device */
431	ich9pciStateToPciAddr(pGlobals, addr, &aPciAddr);
432
433	return ich9pciDataReadAddr(pGlobals, &aPciAddr, len, pu32);
434	}
435
436	/**
437	* Port I/O Handler for PCI data IN operations.
438	*
439	* @returns VBox status code.
440	*
441	* @param pDevIns The device instance.
442	* @param pvUser User argument - ignored.
443	* @param uPort Port number used for the IN operation.
444	* @param pu32 Where to store the result.
445	* @param cb Number of bytes read.
446	*/
447	PDMBOTHCBDECL(int) ich9pciIOPortDataRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
448	{
449	NOREF(pvUser);
450	if (!(Port % cb))
451	{
452	PCI_LOCK(pDevIns, VINF_IOM_HC_IOPORT_READ);
453	int rc = ich9pciDataRead(PDMINS_2_DATA(pDevIns, PPCIGLOBALS), Port, cb, pu32);
454	PCI_UNLOCK(pDevIns);
455	Log(("pciIOPortDataRead: Port=%#x cb=%#x -> %#x (%Rrc)\n", Port, cb, *pu32, rc));
456	return rc;
457	}
458	AssertMsgFailed(("Unaligned read from port %#x cb=%d\n", Port, cb));
459	return VERR_IOM_IOPORT_UNUSED;
460	}
461
462	/* Compute mapping of PCI slot and IRQ number to APIC interrupt line */
463	DECLINLINE(int) ich9pciSlot2ApicIrq(uint8_t uSlot, int irq_num)
464	{
465	return (irq_num + uSlot) & 7;
466	}
467
468	/* Add one more level up request on APIC input line */
469	DECLINLINE(void) ich9pciApicLevelUp(PPCIGLOBALS pGlobals, int irq_num)
470	{
471	ASMAtomicIncU32(&pGlobals->uaPciApicIrqLevels[irq_num]);
472	}
473
474	/* Remove one level up request on APIC input line */
475	DECLINLINE(void) ich9pciApicLevelDown(PPCIGLOBALS pGlobals, int irq_num)
476	{
477	ASMAtomicDecU32(&pGlobals->uaPciApicIrqLevels[irq_num]);
478	}
479
480	static void ich9pciApicSetIrq(PPCIBUS pBus, uint8_t uDevFn, PCIDevice *pPciDev, int irq_num1, int iLevel, int iForcedIrq)
481	{
482	/* This is only allowed to be called with a pointer to the root bus. */
483	AssertMsg(pBus->iBus == 0, ("iBus=%u\n", pBus->iBus));
484
485	if (iForcedIrq == -1)
486	{
487	int apic_irq, apic_level;
488	PPCIGLOBALS pGlobals = PCIROOTBUS_2_PCIGLOBALS(pBus);
489	int irq_num = ich9pciSlot2ApicIrq(uDevFn >> 3, irq_num1);
490
491	if ((iLevel & PDM_IRQ_LEVEL_HIGH) == PDM_IRQ_LEVEL_HIGH)
492	ich9pciApicLevelUp(pGlobals, irq_num);
493	else if ((iLevel & PDM_IRQ_LEVEL_HIGH) == PDM_IRQ_LEVEL_LOW)
494	ich9pciApicLevelDown(pGlobals, irq_num);
495
496	apic_irq = irq_num + 0x10;
497	apic_level = pGlobals->uaPciApicIrqLevels[irq_num] != 0;
498	Log3(("ich9pciApicSetIrq: %s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d\n",
499	R3STRING(pPciDev->name), irq_num1, iLevel, apic_irq, apic_level, irq_num));
500	pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), apic_irq, apic_level);
501
502	if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP)
503	{
504	/**
505	* we raised it few lines above, as PDM_IRQ_LEVEL_FLIP_FLOP has
506	* PDM_IRQ_LEVEL_HIGH bit set
507	*/
508	ich9pciApicLevelDown(pGlobals, irq_num);
509	pPciDev->Int.s.uIrqPinState = PDM_IRQ_LEVEL_LOW;
510	apic_level = pGlobals->uaPciApicIrqLevels[irq_num] != 0;
511	Log3(("ich9pciApicSetIrq: %s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d (flop)\n",
512	R3STRING(pPciDev->name), irq_num1, iLevel, apic_irq, apic_level, irq_num));
513	pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), apic_irq, apic_level);
514	}
515	} else {
516	Log3(("ich9pciApicSetIrq: %s: irq_num1=%d level=%d acpi_irq=%d\n",
517	R3STRING(pPciDev->name), irq_num1, iLevel, iForcedIrq));
518	pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), iForcedIrq, iLevel);
519	}
520	}
521
522	static void ich9pciSetIrqInternal(PPCIGLOBALS pGlobals, uint8_t uDevFn, PPCIDEVICE pPciDev, int iIrq, int iLevel)
523	{
524
525	if (PCIDevIsIntxDisabled(pPciDev))
526	{
527	if (MsiIsEnabled(pPciDev))
528	{
529	Log2(("MSI interrupt: %d level=%d\n", iIrq, iLevel));
530	PPDMDEVINS pDevIns = pGlobals->aPciBus.CTX_SUFF(pDevIns);
531	MsiNotify(pDevIns, pGlobals->aPciBus.CTX_SUFF(pPciHlp), pPciDev, iIrq, iLevel);
532	}
533	return;
534	}
535
536	PPCIBUS pBus = &pGlobals->aPciBus;
537	const bool fIsAcpiDevice = PCIDevGetDeviceId(pPciDev) == 0x7113;
538
539	/* Check if the state changed. */
540	if (pPciDev->Int.s.uIrqPinState != iLevel)
541	{
542	pPciDev->Int.s.uIrqPinState = (iLevel & PDM_IRQ_LEVEL_HIGH);
543
544	/* Send interrupt to I/O APIC only now. */
545	if (fIsAcpiDevice)
546	/*
547	* ACPI needs special treatment since SCI is hardwired and
548	* should not be affected by PCI IRQ routing tables at the
549	* same time SCI IRQ is shared in PCI sense hence this
550	* kludge (i.e. we fetch the hardwired value from ACPIs
551	* PCI device configuration space).
552	*/
553	ich9pciApicSetIrq(pBus, uDevFn, pPciDev, -1, iLevel, PCIDevGetInterruptLine(pPciDev));
554	else
555	ich9pciApicSetIrq(pBus, uDevFn, pPciDev, iIrq, iLevel, -1);
556	}
557	}
558
559	PDMBOTHCBDECL(int) ich9pciMcfgMMIOWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb)
560	{
561	PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
562	PciAddress aDest;
563	uint32_t u32 = 0;
564
565	Log2(("ich9pciMcfgMMIOWrite: %p(%d) \n", GCPhysAddr, cb));
566
567	PCI_LOCK(pDevIns, VINF_IOM_HC_IOPORT_WRITE);
568
569	ich9pciPhysToPciAddr(pGlobals, GCPhysAddr, &aDest);
570
571	switch (cb)
572	{
573	case 1:
574	u32 = (uint8_t)pv;
575	break;
576	case 2:
577	u32 = (uint16_t)pv;
578	break;
579	case 4:
580	u32 = (uint32_t)pv;
581	break;
582	default:
583	Assert(false);
584	break;
585	}
586	int rc = ich9pciDataWriteAddr(pGlobals, &aDest, u32, cb);
587	PCI_UNLOCK(pDevIns);
588
589	return rc;
590	}
591
592	PDMBOTHCBDECL(int) ich9pciMcfgMMIORead (PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb)
593	{
594	PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
595	PciAddress aDest;
596	uint32_t rv = 0xffffffff;
597
598	Log2(("ich9pciMcfgMMIORead: %p(%d) \n", GCPhysAddr, cb));
599
600	PCI_LOCK(pDevIns, VINF_IOM_HC_IOPORT_READ);
601
602	ich9pciPhysToPciAddr(pGlobals, GCPhysAddr, &aDest);
603
604	int rc = ich9pciDataReadAddr(pGlobals, &aDest, cb, &rv);
605
606	switch (cb)
607	{
608	case 1:
609	(uint8_t)pv = (uint8_t)rv;
610	break;
611	case 2:
612	(uint16_t)pv = (uint16_t)rv;
613	break;
614	case 4:
615	(uint32_t)pv = (uint32_t)rv;
616	break;
617	default:
618	Assert(false);
619	break;
620	}
621	PCI_UNLOCK(pDevIns);
622
623	return rc;
624	}
625
626	#ifdef IN_RING3
627
628	DECLINLINE(PPCIDEVICE) ich9pciFindBridge(PPCIBUS pBus, uint8_t iBus)
629	{
630	/* Search for a fitting bridge. */
631	for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
632	{
633	/*
634	* Examine secondary and subordinate bus number.
635	* If the target bus is in the range we pass the request on to the bridge.
636	*/
637	PPCIDEVICE pBridgeTemp = pBus->papBridgesR3[iBridge];
638	AssertMsg(pBridgeTemp && PCIIsPci2PciBridge(pBridgeTemp),
639	("Device is not a PCI bridge but on the list of PCI bridges\n"));
640
641	if ( iBus >= PCIDevGetByte(pBridgeTemp, VBOX_PCI_SECONDARY_BUS)
642	&& iBus <= PCIDevGetByte(pBridgeTemp, VBOX_PCI_SUBORDINATE_BUS))
643	return pBridgeTemp;
644	}
645
646	/* Nothing found. */
647	return NULL;
648	}
649
650	DECLINLINE(uint32_t) ich9pciGetRegionReg(int iRegion)
651	{
652	return (iRegion == PCI_ROM_SLOT) ?
653	VBOX_PCI_ROM_ADDRESS : (VBOX_PCI_BASE_ADDRESS_0 + iRegion * 4);
654	}
655
656	#define INVALID_PCI_ADDRESS ~0U
657
658	static void ich9pciUpdateMappings(PCIDevice* pDev)
659	{
660	PPCIBUS pBus = pDev->Int.s.CTX_SUFF(pBus);
661	uint32_t uLast, uNew;
662
663	int iCmd = PCIDevGetCommand(pDev);
664	for (int iRegion = 0; iRegion < PCI_NUM_REGIONS; iRegion++)
665	{
666	PCIIORegion* pRegion = &pDev->Int.s.aIORegions[iRegion];
667	uint32_t uConfigReg = ich9pciGetRegionReg(iRegion);
668	int32_t iRegionSize = pRegion->size;
669	int rc;
670
671	if (iRegionSize == 0)
672	continue;
673
674	if (pRegion->type & PCI_ADDRESS_SPACE_IO)
675	{
676	/* port IO region */
677	if (iCmd & PCI_COMMAND_IOACCESS)
678	{
679	/* IO access allowed */
680	uNew = ich9pciConfigReadDev(pDev, uConfigReg, 4);
681	uNew &= ~(iRegionSize - 1);
682	uLast = uNew + iRegionSize - 1;
683	/* only 64K ioports on PC */
684	if (uLast <= uNew \|\| uNew == 0 \|\| uLast >= 0x10000)
685	uNew = INVALID_PCI_ADDRESS;
686	} else
687	uNew = INVALID_PCI_ADDRESS;
688	}
689	else
690	{
691	/* MMIO region */
692	if (iCmd & PCI_COMMAND_MEMACCESS)
693	{
694	uNew = ich9pciConfigReadDev(pDev, uConfigReg, 4);
695	/* the ROM slot has a specific enable bit */
696	if (iRegion == PCI_ROM_SLOT && !(uNew & 1))
697	uNew = INVALID_PCI_ADDRESS;
698	else
699	{
700	uNew &= ~(iRegionSize - 1);
701	uLast = uNew + iRegionSize - 1;
702	/* NOTE: we do not support wrapping */
703	/* XXX: as we cannot support really dynamic
704	mappings, we handle specific values as invalid
705	mappings. */
706	if (uLast <= uNew \|\| uNew == 0 \|\| uLast == INVALID_PCI_ADDRESS)
707	uNew = INVALID_PCI_ADDRESS;
708	}
709	} else
710	uNew = INVALID_PCI_ADDRESS;
711	}
712	/* now do the real mapping */
713	if (uNew != pRegion->addr)
714	{
715	if (pRegion->addr != INVALID_PCI_ADDRESS)
716	{
717	if (pRegion->type & PCI_ADDRESS_SPACE_IO)
718	{
719	/* Port IO */
720	rc = PDMDevHlpIOPortDeregister(pDev->pDevIns, pRegion->addr, pRegion->size);
721	AssertRC(rc);
722	}
723	else
724	{
725	RTGCPHYS GCPhysBase = pRegion->addr;
726	if (pBus->pPciHlpR3->pfnIsMMIO2Base(pBus->pDevInsR3, pDev->pDevIns, GCPhysBase))
727	{
728	/* unmap it. */
729	rc = pRegion->map_func(pDev, iRegion, NIL_RTGCPHYS, pRegion->size, (PCIADDRESSSPACE)(pRegion->type));
730	AssertRC(rc);
731	rc = PDMDevHlpMMIO2Unmap(pDev->pDevIns, iRegion, GCPhysBase);
732	}
733	else
734	rc = PDMDevHlpMMIODeregister(pDev->pDevIns, GCPhysBase, pRegion->size);
735	AssertMsgRC(rc, ("rc=%Rrc d=%s i=%d GCPhysBase=%RGp size=%#x\n", rc, pDev->name, iRegion, GCPhysBase, pRegion->size));
736	}
737	}
738	pRegion->addr = uNew;
739	if (pRegion->addr != INVALID_PCI_ADDRESS)
740	{
741	/* finally, map the region */
742	rc = pRegion->map_func(pDev, iRegion,
743	pRegion->addr, pRegion->size,
744	(PCIADDRESSSPACE)(pRegion->type));
745	AssertRC(rc);
746	}
747	}
748	}
749	}
750
751	static DECLCALLBACK(int) ich9pciRegister(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, const char *pszName, int iDev)
752	{
753	PPCIBUS pBus = DEVINS_2_PCIBUS(pDevIns);
754
755	/*
756	* Check input.
757	*/
758	if ( !pszName
759	\|\| !pPciDev
760	\|\| iDev >= (int)RT_ELEMENTS(pBus->apDevices)
761	)
762	{
763	AssertMsgFailed(("Invalid argument! pszName=%s pPciDev=%p iDev=%d\n", pszName, pPciDev, iDev));
764	return VERR_INVALID_PARAMETER;
765	}
766
767	/*
768	* Register the device.
769	*/
770	return ich9pciRegisterInternal(pBus, iDev, pPciDev, pszName);
771	}
772
773
774	static DECLCALLBACK(int) ich9pciRegisterMsi(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PPDMMSIREG pMsiReg)
775	{
776	return MsiInit(pPciDev, pMsiReg);
777	}
778
779
780	static DECLCALLBACK(int) ich9pcibridgeRegister(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, const char *pszName, int iDev)
781	{
782
783	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
784
785	/*
786	* Check input.
787	*/
788	if ( !pszName
789	\|\| !pPciDev
790	\|\| iDev >= (int)RT_ELEMENTS(pBus->apDevices))
791	{
792	AssertMsgFailed(("Invalid argument! pszName=%s pPciDev=%p iDev=%d\n", pszName, pPciDev, iDev));
793	return VERR_INVALID_PARAMETER;
794	}
795
796	/*
797	* Register the device.
798	*/
799	return ich9pciRegisterInternal(pBus, iDev, pPciDev, pszName);
800	}
801
802	static DECLCALLBACK(int) ich9pciIORegionRegister(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iRegion, uint32_t cbRegion, PCIADDRESSSPACE enmType, PFNPCIIOREGIONMAP pfnCallback)
803	{
804	/*
805	* Validate.
806	*/
807	AssertMsgReturn( enmType == PCI_ADDRESS_SPACE_MEM
808	\|\| enmType == PCI_ADDRESS_SPACE_IO
809	\|\| enmType == PCI_ADDRESS_SPACE_MEM_PREFETCH,
810	("Invalid enmType=%#x? Or was this a bitmask after all...\n", enmType),
811	VERR_INVALID_PARAMETER);
812	AssertMsgReturn((unsigned)iRegion < PCI_NUM_REGIONS,
813	("Invalid iRegion=%d PCI_NUM_REGIONS=%d\n", iRegion, PCI_NUM_REGIONS),
814	VERR_INVALID_PARAMETER);
815	int iLastSet = ASMBitLastSetU32(cbRegion);
816	AssertMsgReturn( iLastSet != 0
817	&& RT_BIT_32(iLastSet - 1) == cbRegion,
818	("Invalid cbRegion=%#x iLastSet=%#x (not a power of 2 or 0)\n", cbRegion, iLastSet),
819	VERR_INVALID_PARAMETER);
820
821	/*
822	* Register the I/O region.
823	*/
824	PPCIIOREGION pRegion = &pPciDev->Int.s.aIORegions[iRegion];
825	pRegion->addr = INVALID_PCI_ADDRESS;
826	pRegion->size = cbRegion;
827	pRegion->type = enmType;
828	pRegion->map_func = pfnCallback;
829
830	/* Set type in the config space. */
831	uint32_t u32Address = ich9pciGetRegionReg(iRegion);
832	uint32_t u32Value = (enmType == PCI_ADDRESS_SPACE_MEM_PREFETCH ? (1 << 3) : 0)
833	\| (enmType == PCI_ADDRESS_SPACE_IO ? 1 : 0);
834	PCIDevSetDWord(pPciDev, u32Address, u32Value);
835
836	return VINF_SUCCESS;
837	}
838
839	static DECLCALLBACK(void) ich9pciSetConfigCallbacks(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PFNPCICONFIGREAD pfnRead, PPFNPCICONFIGREAD ppfnReadOld,
840	PFNPCICONFIGWRITE pfnWrite, PPFNPCICONFIGWRITE ppfnWriteOld)
841	{
842	if (ppfnReadOld)
843	*ppfnReadOld = pPciDev->Int.s.pfnConfigRead;
844	pPciDev->Int.s.pfnConfigRead = pfnRead;
845
846	if (ppfnWriteOld)
847	*ppfnWriteOld = pPciDev->Int.s.pfnConfigWrite;
848	pPciDev->Int.s.pfnConfigWrite = pfnWrite;
849	}
850
851	/**
852	* Saves a state of the PCI device.
853	*
854	* @returns VBox status code.
855	* @param pDevIns Device instance of the PCI Bus.
856	* @param pPciDev Pointer to PCI device.
857	* @param pSSM The handle to save the state to.
858	*/
859	static DECLCALLBACK(int) ich9pciGenericSaveExec(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PSSMHANDLE pSSM)
860	{
861	return SSMR3PutMem(pSSM, &pPciDev->config[0], sizeof(pPciDev->config));
862	}
863
864	static int ich9pciR3CommonSaveExec(PPCIBUS pBus, PSSMHANDLE pSSM)
865	{
866	/*
867	* Iterate thru all the devices.
868	*/
869	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
870	{
871	PPCIDEVICE pDev = pBus->apDevices[i];
872	if (pDev)
873	{
874	/* Device position */
875	SSMR3PutU32(pSSM, i);
876	/* PCI config registers */
877	SSMR3PutMem(pSSM, pDev->config, sizeof(pDev->config));
878
879	/* Device flags */
880	int rc = SSMR3PutU32(pSSM, pDev->Int.s.uFlags);
881	if (RT_FAILURE(rc))
882	return rc;
883
884	/* IRQ pin state */
885	rc = SSMR3PutS32(pSSM, pDev->Int.s.uIrqPinState);
886	if (RT_FAILURE(rc))
887	return rc;
888
889	/* MSI info */
890	rc = SSMR3PutU8(pSSM, pDev->Int.s.u8MsiCapOffset);
891	if (RT_FAILURE(rc))
892	return rc;
893	rc = SSMR3PutU8(pSSM, pDev->Int.s.u8MsiCapSize);
894	if (RT_FAILURE(rc))
895	return rc;
896
897	/* MSI-X info */
898	rc = SSMR3PutU8(pSSM, pDev->Int.s.u8MsixCapOffset);
899	if (RT_FAILURE(rc))
900	return rc;
901	rc = SSMR3PutU8(pSSM, pDev->Int.s.u8MsixCapSize);
902	if (RT_FAILURE(rc))
903	return rc;
904	}
905	}
906	return SSMR3PutU32(pSSM, UINT32_MAX); /* terminator */
907	}
908
909	static DECLCALLBACK(int) ich9pciR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
910	{
911	PPCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
912
913	/*
914	* Bus state data.
915	*/
916	SSMR3PutU32(pSSM, pThis->uConfigReg);
917
918	/*
919	* Save IRQ states.
920	*/
921	for (int i = 0; i < PCI_APIC_IRQ_PINS; i++)
922	SSMR3PutU32(pSSM, pThis->uaPciApicIrqLevels[i]);
923
924	SSMR3PutU32(pSSM, ~0); /* separator */
925
926	return ich9pciR3CommonSaveExec(&pThis->aPciBus, pSSM);
927	}
928
929
930	static DECLCALLBACK(int) ich9pcibridgeR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
931	{
932	PPCIBUS pThis = PDMINS_2_DATA(pDevIns, PPCIBUS);
933	return ich9pciR3CommonSaveExec(pThis, pSSM);
934	}
935
936
937	static void ich9pcibridgeConfigWrite(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice, uint32_t u32Address, uint32_t u32Value, unsigned cb)
938	{
939	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
940
941	LogFlowFunc((": pDevIns=%p iBus=%d iDevice=%d u32Address=%u u32Value=%u cb=%d\n", pDevIns, iBus, iDevice, u32Address, u32Value, cb));
942
943	/* If the current bus is not the target bus search for the bus which contains the device. */
944	if (iBus != PCIDevGetByte(&pBus->aPciDev, VBOX_PCI_SECONDARY_BUS))
945	{
946	PPCIDEVICE pBridgeDevice = ich9pciFindBridge(pBus, iBus);
947	if (pBridgeDevice)
948	{
949	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigWrite);
950	pBridgeDevice->Int.s.pfnBridgeConfigWrite(pBridgeDevice->pDevIns, iBus, iDevice, u32Address, u32Value, cb);
951	}
952	}
953	else
954	{
955	/* This is the target bus, pass the write to the device. */
956	PPCIDEVICE pPciDev = pBus->apDevices[iDevice];
957	if (pPciDev)
958	{
959	Log(("%s: %s: addr=%02x val=%08x len=%d\n", __FUNCTION__, pPciDev->name, u32Address, u32Value, cb));
960	pPciDev->Int.s.pfnConfigWrite(pPciDev, u32Address, u32Value, cb);
961	}
962	}
963	}
964
965	static uint32_t ich9pcibridgeConfigRead(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice, uint32_t u32Address, unsigned cb)
966	{
967	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
968	uint32_t u32Value = 0xffffffff; /* Return value in case there is no device. */
969
970	LogFlowFunc((": pDevIns=%p iBus=%d iDevice=%d u32Address=%u cb=%d\n", pDevIns, iBus, iDevice, u32Address, cb));
971
972	/* If the current bus is not the target bus search for the bus which contains the device. */
973	if (iBus != PCIDevGetByte(&pBus->aPciDev, VBOX_PCI_SECONDARY_BUS))
974	{
975	PPCIDEVICE pBridgeDevice = ich9pciFindBridge(pBus, iBus);
976	if (pBridgeDevice)
977	{
978	AssertPtr( pBridgeDevice->Int.s.pfnBridgeConfigRead);
979	u32Value = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->pDevIns, iBus, iDevice, u32Address, cb);
980	}
981	}
982	else
983	{
984	/* This is the target bus, pass the read to the device. */
985	PPCIDEVICE pPciDev = pBus->apDevices[iDevice];
986	if (pPciDev)
987	{
988	u32Value = pPciDev->Int.s.pfnConfigRead(pPciDev, u32Address, cb);
989	Log(("%s: %s: u32Address=%02x u32Value=%08x cb=%d\n", __FUNCTION__, pPciDev->name, u32Address, u32Value, cb));
990	}
991	}
992
993	return u32Value;
994	}
995
996
997	/**
998	* Common routine for restoring the config registers of a PCI device.
999	*
1000	* @param pDev The PCI device.
1001	* @param pbSrcConfig The configuration register values to be loaded.
1002	* @param fIsBridge Whether this is a bridge device or not.
1003	*/
1004	static void pciR3CommonRestoreConfig(PPCIDEVICE pDev, uint8_t const *pbSrcConfig, bool fIsBridge)
1005	{
1006	/*
1007	* This table defines the fields for normal devices and bridge devices, and
1008	* the order in which they need to be restored.
1009	*/
1010	static const struct PciField
1011	{
1012	uint8_t off;
1013	uint8_t cb;
1014	uint8_t fWritable;
1015	uint8_t fBridge;
1016	const char *pszName;
1017	} s_aFields[] =
1018	{
1019	/* off,cb,fW,fB, pszName */
1020	{ VBOX_PCI_VENDOR_ID, 2, 0, 3, "VENDOR_ID" },
1021	{ VBOX_PCI_DEVICE_ID, 2, 0, 3, "DEVICE_ID" },
1022	{ VBOX_PCI_STATUS, 2, 1, 3, "STATUS" },
1023	{ VBOX_PCI_REVISION_ID, 1, 0, 3, "REVISION_ID" },
1024	{ VBOX_PCI_CLASS_PROG, 1, 0, 3, "CLASS_PROG" },
1025	{ VBOX_PCI_CLASS_SUB, 1, 0, 3, "CLASS_SUB" },
1026	{ VBOX_PCI_CLASS_BASE, 1, 0, 3, "CLASS_BASE" },
1027	{ VBOX_PCI_CACHE_LINE_SIZE, 1, 1, 3, "CACHE_LINE_SIZE" },
1028	{ VBOX_PCI_LATENCY_TIMER, 1, 1, 3, "LATENCY_TIMER" },
1029	{ VBOX_PCI_HEADER_TYPE, 1, 0, 3, "HEADER_TYPE" },
1030	{ VBOX_PCI_BIST, 1, 1, 3, "BIST" },
1031	{ VBOX_PCI_BASE_ADDRESS_0, 4, 1, 3, "BASE_ADDRESS_0" },
1032	{ VBOX_PCI_BASE_ADDRESS_1, 4, 1, 3, "BASE_ADDRESS_1" },
1033	{ VBOX_PCI_BASE_ADDRESS_2, 4, 1, 1, "BASE_ADDRESS_2" },
1034	{ VBOX_PCI_PRIMARY_BUS, 1, 1, 2, "PRIMARY_BUS" }, // fWritable = ??
1035	{ VBOX_PCI_SECONDARY_BUS, 1, 1, 2, "SECONDARY_BUS" }, // fWritable = ??
1036	{ VBOX_PCI_SUBORDINATE_BUS, 1, 1, 2, "SUBORDINATE_BUS" }, // fWritable = ??
1037	{ VBOX_PCI_SEC_LATENCY_TIMER, 1, 1, 2, "SEC_LATENCY_TIMER" }, // fWritable = ??
1038	{ VBOX_PCI_BASE_ADDRESS_3, 4, 1, 1, "BASE_ADDRESS_3" },
1039	{ VBOX_PCI_IO_BASE, 1, 1, 2, "IO_BASE" }, // fWritable = ??
1040	{ VBOX_PCI_IO_LIMIT, 1, 1, 2, "IO_LIMIT" }, // fWritable = ??
1041	{ VBOX_PCI_SEC_STATUS, 2, 1, 2, "SEC_STATUS" }, // fWritable = ??
1042	{ VBOX_PCI_BASE_ADDRESS_4, 4, 1, 1, "BASE_ADDRESS_4" },
1043	{ VBOX_PCI_MEMORY_BASE, 2, 1, 2, "MEMORY_BASE" }, // fWritable = ??
1044	{ VBOX_PCI_MEMORY_LIMIT, 2, 1, 2, "MEMORY_LIMIT" }, // fWritable = ??
1045	{ VBOX_PCI_BASE_ADDRESS_5, 4, 1, 1, "BASE_ADDRESS_5" },
1046	{ VBOX_PCI_PREF_MEMORY_BASE, 2, 1, 2, "PREF_MEMORY_BASE" }, // fWritable = ??
1047	{ VBOX_PCI_PREF_MEMORY_LIMIT, 2, 1, 2, "PREF_MEMORY_LIMIT" }, // fWritable = ??
1048	{ VBOX_PCI_CARDBUS_CIS, 4, 1, 1, "CARDBUS_CIS" }, // fWritable = ??
1049	{ VBOX_PCI_PREF_BASE_UPPER32, 4, 1, 2, "PREF_BASE_UPPER32" }, // fWritable = ??
1050	{ VBOX_PCI_SUBSYSTEM_VENDOR_ID, 2, 0, 1, "SUBSYSTEM_VENDOR_ID" },// fWritable = !?
1051	{ VBOX_PCI_PREF_LIMIT_UPPER32, 4, 1, 2, "PREF_LIMIT_UPPER32" },// fWritable = ??
1052	{ VBOX_PCI_SUBSYSTEM_ID, 2, 0, 1, "SUBSYSTEM_ID" }, // fWritable = !?
1053	{ VBOX_PCI_ROM_ADDRESS, 4, 1, 1, "ROM_ADDRESS" }, // fWritable = ?!
1054	{ VBOX_PCI_IO_BASE_UPPER16, 2, 1, 2, "IO_BASE_UPPER16" }, // fWritable = ?!
1055	{ VBOX_PCI_IO_LIMIT_UPPER16, 2, 1, 2, "IO_LIMIT_UPPER16" }, // fWritable = ?!
1056	{ VBOX_PCI_CAPABILITY_LIST, 4, 0, 3, "CAPABILITY_LIST" }, // fWritable = !? cb=!?
1057	{ VBOX_PCI_RESERVED_38, 4, 1, 1, "RESERVED_38" }, // ???
1058	{ VBOX_PCI_ROM_ADDRESS_BR, 4, 1, 2, "ROM_ADDRESS_BR" }, // fWritable = !? cb=!? fBridge=!?
1059	{ VBOX_PCI_INTERRUPT_LINE, 1, 1, 3, "INTERRUPT_LINE" }, // fBridge=??
1060	{ VBOX_PCI_INTERRUPT_PIN, 1, 0, 3, "INTERRUPT_PIN" }, // fBridge=??
1061	{ VBOX_PCI_MIN_GNT, 1, 0, 1, "MIN_GNT" },
1062	{ VBOX_PCI_BRIDGE_CONTROL, 2, 1, 2, "BRIDGE_CONTROL" }, // fWritable = !?
1063	{ VBOX_PCI_MAX_LAT, 1, 0, 1, "MAX_LAT" },
1064	/* The COMMAND register must come last as it requires the ADDRESS
1065	registers to be restored before we pretent to change it from 0 to
1066	whatever value the guest assigned it. */
1067	{ VBOX_PCI_COMMAND, 2, 1, 3, "COMMAND" },
1068	};
1069
1070	#ifdef RT_STRICT
1071	/* Check that we've got full register coverage. */
1072	uint32_t bmDevice[0x40 / 32];
1073	uint32_t bmBridge[0x40 / 32];
1074	RT_ZERO(bmDevice);
1075	RT_ZERO(bmBridge);
1076	for (uint32_t i = 0; i < RT_ELEMENTS(s_aFields); i++)
1077	{
1078	uint8_t off = s_aFields[i].off;
1079	uint8_t cb = s_aFields[i].cb;
1080	uint8_t f = s_aFields[i].fBridge;
1081	while (cb-- > 0)
1082	{
1083	if (f & 1) AssertMsg(!ASMBitTest(bmDevice, off), ("%#x\n", off));
1084	if (f & 2) AssertMsg(!ASMBitTest(bmBridge, off), ("%#x\n", off));
1085	if (f & 1) ASMBitSet(bmDevice, off);
1086	if (f & 2) ASMBitSet(bmBridge, off);
1087	off++;
1088	}
1089	}
1090	for (uint32_t off = 0; off < 0x40; off++)
1091	{
1092	AssertMsg(ASMBitTest(bmDevice, off), ("%#x\n", off));
1093	AssertMsg(ASMBitTest(bmBridge, off), ("%#x\n", off));
1094	}
1095	#endif
1096
1097	/*
1098	* Loop thru the fields covering the 64 bytes of standard registers.
1099	*/
1100	uint8_t const fBridge = fIsBridge ? 2 : 1;
1101	uint8_t *pbDstConfig = &pDev->config[0];
1102	for (uint32_t i = 0; i < RT_ELEMENTS(s_aFields); i++)
1103	if (s_aFields[i].fBridge & fBridge)
1104	{
1105	uint8_t const off = s_aFields[i].off;
1106	uint8_t const cb = s_aFields[i].cb;
1107	uint32_t u32Src;
1108	uint32_t u32Dst;
1109	switch (cb)
1110	{
1111	case 1:
1112	u32Src = pbSrcConfig[off];
1113	u32Dst = pbDstConfig[off];
1114	break;
1115	case 2:
1116	u32Src = (uint16_t const )&pbSrcConfig[off];
1117	u32Dst = (uint16_t const )&pbDstConfig[off];
1118	break;
1119	case 4:
1120	u32Src = (uint32_t const )&pbSrcConfig[off];
1121	u32Dst = (uint32_t const )&pbDstConfig[off];
1122	break;
1123	default:
1124	AssertFailed();
1125	continue;
1126	}
1127
1128	if ( u32Src != u32Dst
1129	\|\| off == VBOX_PCI_COMMAND)
1130	{
1131	if (u32Src != u32Dst)
1132	{
1133	if (!s_aFields[i].fWritable)
1134	LogRel(("PCI: %8s/%u: %2u-bit field %s: %x -> %x - !READ ONLY!\n",
1135	pDev->name, pDev->pDevIns->iInstance, cb*8, s_aFields[i].pszName, u32Dst, u32Src));
1136	else
1137	LogRel(("PCI: %8s/%u: %2u-bit field %s: %x -> %x\n",
1138	pDev->name, pDev->pDevIns->iInstance, cb*8, s_aFields[i].pszName, u32Dst, u32Src));
1139	}
1140	if (off == VBOX_PCI_COMMAND)
1141	PCIDevSetCommand(pDev, 0); /* For remapping, see ich9pciR3CommonLoadExec. */
1142	pDev->Int.s.pfnConfigWrite(pDev, off, u32Src, cb);
1143	}
1144	}
1145
1146	/*
1147	* The device dependent registers.
1148	*
1149	* We will not use ConfigWrite here as we have no clue about the size
1150	* of the registers, so the device is responsible for correctly
1151	* restoring functionality governed by these registers.
1152	*/
1153	for (uint32_t off = 0x40; off < sizeof(pDev->config); off++)
1154	if (pbDstConfig[off] != pbSrcConfig[off])
1155	{
1156	LogRel(("PCI: %8s/%u: register %02x: %02x -> %02x\n",
1157	pDev->name, pDev->pDevIns->iInstance, off, pbDstConfig[off], pbSrcConfig[off])); /** @todo make this Log() later. */
1158	pbDstConfig[off] = pbSrcConfig[off];
1159	}
1160	}
1161
1162	/**
1163	* Common worker for ich9pciR3LoadExec and ich9pcibridgeR3LoadExec.
1164	*
1165	* @returns VBox status code.
1166	* @param pBus The bus which data is being loaded.
1167	* @param pSSM The saved state handle.
1168	* @param uVersion The data version.
1169	* @param uPass The pass.
1170	*/
1171	static DECLCALLBACK(int) ich9pciR3CommonLoadExec(PPCIBUS pBus, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1172	{
1173	uint32_t u32;
1174	uint32_t i;
1175	int rc;
1176
1177	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
1178
1179	/*
1180	* Iterate thru all the devices and write 0 to the COMMAND register so
1181	* that all the memory is unmapped before we start restoring the saved
1182	* mapping locations.
1183	*
1184	* The register value is restored afterwards so we can do proper
1185	* LogRels in pciR3CommonRestoreConfig.
1186	*/
1187	for (i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
1188	{
1189	PPCIDEVICE pDev = pBus->apDevices[i];
1190	if (pDev)
1191	{
1192	uint16_t u16 = PCIDevGetCommand(pDev);
1193	pDev->Int.s.pfnConfigWrite(pDev, VBOX_PCI_COMMAND, 0, 2);
1194	PCIDevSetCommand(pDev, u16);
1195	Assert(PCIDevGetCommand(pDev) == u16);
1196	}
1197	}
1198
1199	/*
1200	* Iterate all the devices.
1201	*/
1202	for (i = 0;; i++)
1203	{
1204	PCIDEVICE DevTmp;
1205	PPCIDEVICE pDev;
1206
1207	/* index / terminator */
1208	rc = SSMR3GetU32(pSSM, &u32);
1209	if (RT_FAILURE(rc))
1210	return rc;
1211	if (u32 == (uint32_t)~0)
1212	break;
1213	if ( u32 >= RT_ELEMENTS(pBus->apDevices)
1214	\|\| u32 < i)
1215	{
1216	AssertMsgFailed(("u32=%#x i=%#x\n", u32, i));
1217	return rc;
1218	}
1219
1220	/* skip forward to the device checking that no new devices are present. */
1221	for (; i < u32; i++)
1222	{
1223	pDev = pBus->apDevices[i];
1224	if (pDev)
1225	{
1226	LogRel(("New device in slot %#x, %s (vendor=%#06x device=%#06x)\n", i, pDev->name,
1227	PCIDevGetVendorId(pDev), PCIDevGetDeviceId(pDev)));
1228	if (SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT)
1229	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("New device in slot %#x, %s (vendor=%#06x device=%#06x)"),
1230	i, pDev->name, PCIDevGetVendorId(pDev), PCIDevGetDeviceId(pDev));
1231	}
1232	}
1233
1234	/* get the data */
1235	DevTmp.Int.s.uFlags = 0;
1236	DevTmp.Int.s.u8MsiCapOffset = 0;
1237	DevTmp.Int.s.u8MsiCapSize = 0;
1238	DevTmp.Int.s.u8MsixCapOffset = 0;
1239	DevTmp.Int.s.u8MsixCapSize = 0;
1240	DevTmp.Int.s.uIrqPinState = ~0; /* Invalid value in case we have an older saved state to force a state change in pciSetIrq. */
1241	SSMR3GetMem(pSSM, DevTmp.config, sizeof(DevTmp.config));
1242
1243	rc = SSMR3GetU32(pSSM, &DevTmp.Int.s.uFlags);
1244	if (RT_FAILURE(rc))
1245	return rc;
1246
1247	rc = SSMR3GetS32(pSSM, &DevTmp.Int.s.uIrqPinState);
1248	if (RT_FAILURE(rc))
1249	return rc;
1250
1251	rc = SSMR3GetU8(pSSM, &DevTmp.Int.s.u8MsiCapOffset);
1252	if (RT_FAILURE(rc))
1253	return rc;
1254
1255	rc = SSMR3GetU8(pSSM, &DevTmp.Int.s.u8MsiCapSize);
1256	if (RT_FAILURE(rc))
1257	return rc;
1258
1259	rc = SSMR3GetU8(pSSM, &DevTmp.Int.s.u8MsixCapOffset);
1260	if (RT_FAILURE(rc))
1261	return rc;
1262
1263	rc = SSMR3GetU8(pSSM, &DevTmp.Int.s.u8MsixCapSize);
1264	if (RT_FAILURE(rc))
1265	return rc;
1266
1267	/* check that it's still around. */
1268	pDev = pBus->apDevices[i];
1269	if (!pDev)
1270	{
1271	LogRel(("Device in slot %#x has been removed! vendor=%#06x device=%#06x\n", i,
1272	PCIDevGetVendorId(&DevTmp), PCIDevGetDeviceId(&DevTmp)));
1273	if (SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT)
1274	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Device in slot %#x has been removed! vendor=%#06x device=%#06x"),
1275	i, PCIDevGetVendorId(&DevTmp), PCIDevGetDeviceId(&DevTmp));
1276	continue;
1277	}
1278
1279	/* match the vendor id assuming that this will never be changed. */
1280	if ( PCIDevGetVendorId(&DevTmp) != PCIDevGetVendorId(pDev))
1281	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Device in slot %#x (%s) vendor id mismatch! saved=%.4Rhxs current=%.4Rhxs"),
1282	i, pDev->name, PCIDevGetVendorId(&DevTmp), PCIDevGetVendorId(pDev));
1283
1284	/* commit the loaded device config. */
1285	pciR3CommonRestoreConfig(pDev, &DevTmp.config[0], false ); /** @todo fix bridge fun! */
1286
1287	pDev->Int.s.uIrqPinState = DevTmp.Int.s.uIrqPinState;
1288	}
1289
1290	return VINF_SUCCESS;
1291	}
1292
1293	/**
1294	* Loads a saved PCI device state.
1295	*
1296	* @returns VBox status code.
1297	* @param pDevIns Device instance of the PCI Bus.
1298	* @param pPciDev Pointer to PCI device.
1299	* @param pSSM The handle to the saved state.
1300	*/
1301	static DECLCALLBACK(int) ich9pciGenericLoadExec(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PSSMHANDLE pSSM)
1302	{
1303	return SSMR3GetMem(pSSM, &pPciDev->config[0], sizeof(pPciDev->config));
1304	}
1305
1306	static DECLCALLBACK(int) ich9pciR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1307	{
1308	PPCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
1309	PPCIBUS pBus = &pThis->aPciBus;
1310	uint32_t u32;
1311	int rc;
1312
1313	/* We ignore this version as there's no saved state with it anyway */
1314	if (uVersion == VBOX_ICH9PCI_SAVED_STATE_VERSION_NOMSI)
1315	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1316	if (uVersion > VBOX_ICH9PCI_SAVED_STATE_VERSION_MSI)
1317	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1318
1319	/*
1320	* Bus state data.
1321	*/
1322	SSMR3GetU32(pSSM, &pThis->uConfigReg);
1323
1324	/*
1325	* Load IRQ states.
1326	*/
1327	for (int i = 0; i < PCI_APIC_IRQ_PINS; i++)
1328	SSMR3GetU32(pSSM, (uint32_t*)&pThis->uaPciApicIrqLevels[i]);
1329
1330	/* separator */
1331	rc = SSMR3GetU32(pSSM, &u32);
1332	if (RT_FAILURE(rc))
1333	return rc;
1334	if (u32 != (uint32_t)~0)
1335	AssertMsgFailedReturn(("u32=%#x\n", u32), rc);
1336
1337	return ich9pciR3CommonLoadExec(pBus, pSSM, uVersion, uPass);
1338	}
1339
1340	static DECLCALLBACK(int) ich9pcibridgeR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1341	{
1342	PPCIBUS pThis = PDMINS_2_DATA(pDevIns, PPCIBUS);
1343	if (uVersion > VBOX_ICH9PCI_SAVED_STATE_VERSION_MSI)
1344	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1345	return ich9pciR3CommonLoadExec(pThis, pSSM, uVersion, uPass);
1346	}
1347
1348	static uint32_t ich9pciConfigRead(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t len)
1349	{
1350	uint32_t u32Val = 0xffffffff;
1351	PciAddress aPciAddr;
1352
1353	aPciAddr.iBus = uBus;
1354	aPciAddr.iDeviceFunc = uDevFn;
1355	aPciAddr.iRegister = addr;
1356
1357	int rc = ich9pciDataReadAddr(pGlobals, &aPciAddr, len, &u32Val);
1358	AssertRC(rc);
1359	switch (len)
1360	{
1361	case 1:
1362	u32Val &= 0xff;
1363	break;
1364	case 2:
1365	u32Val &= 0xffff;
1366	break;
1367	}
1368	return u32Val;
1369	}
1370
1371	static void ich9pciConfigWrite(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t val, uint32_t len)
1372	{
1373	PciAddress aPciAddr;
1374
1375	aPciAddr.iBus = uBus;
1376	aPciAddr.iDeviceFunc = uDevFn;
1377	aPciAddr.iRegister = addr;
1378
1379	ich9pciDataWriteAddr(pGlobals, &aPciAddr, val, len);
1380	}
1381
1382	static void ich9pciSetRegionAddress(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, int iRegion, uint32_t addr)
1383	{
1384	uint32_t uReg = ich9pciGetRegionReg(iRegion);
1385
1386	/* Read memory type first. */
1387	uint8_t uResourceType = ich9pciConfigRead(pGlobals, uBus, uDevFn, uReg, 1);
1388	/* Read command register. */
1389	uint16_t uCmd = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_COMMAND, 2);
1390
1391	if ( iRegion == PCI_ROM_SLOT )
1392	uCmd \|= PCI_COMMAND_MEMACCESS;
1393	else if ((uResourceType & PCI_ADDRESS_SPACE_IO) == PCI_ADDRESS_SPACE_IO)
1394	uCmd \|= PCI_COMMAND_IOACCESS; /* Enable I/O space access. */
1395	else /* The region is MMIO. */
1396	uCmd \|= PCI_COMMAND_MEMACCESS; /* Enable MMIO access. */
1397
1398	/* Write address of the device. */
1399	ich9pciConfigWrite(pGlobals, uBus, uDevFn, uReg, addr, 4);
1400
1401	/* enable memory mappings */
1402	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_COMMAND, uCmd, 2);
1403	}
1404
1405
1406	static void ich9pciBiosInitBridge(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint8_t cBridgeDepth, uint8_t *paBridgePositions)
1407	{
1408	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_SECONDARY_BUS, pGlobals->uBus, 1);
1409	/* Temporary until we know how many other bridges are behind this one. */
1410	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_SUBORDINATE_BUS, 0xff, 1);
1411
1412	/* Add position of this bridge into the array. */
1413	paBridgePositions[cBridgeDepth+1] = (uDevFn >> 3);
1414
1415	/*
1416	* The I/O range for the bridge must be aligned to a 4KB boundary.
1417	* This does not change anything really as the access to the device is not going
1418	* through the bridge but we want to be compliant to the spec.
1419	*/
1420	if ((pGlobals->uPciBiosIo % 4096) != 0)
1421	{
1422	pGlobals->uPciBiosIo = RT_ALIGN_32(pGlobals->uPciBiosIo, 4*1024);
1423	Log(("%s: Aligned I/O start address. New address %#x\n", __FUNCTION__, pGlobals->uPciBiosIo));
1424	}
1425	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_IO_BASE, (pGlobals->uPciBiosIo >> 8) & 0xf0, 1);
1426
1427	/* The MMIO range for the bridge must be aligned to a 1MB boundary. */
1428	if ((pGlobals->uPciBiosMmio % (1024 * 1024)) != 0)
1429	{
1430	pGlobals->uPciBiosMmio = RT_ALIGN_32(pGlobals->uPciBiosMmio, 1024*1024);
1431	Log(("%s: Aligned MMIO start address. New address %#x\n", __FUNCTION__, pGlobals->uPciBiosMmio));
1432	}
1433	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_MEMORY_BASE, (pGlobals->uPciBiosMmio >> 16) & UINT32_C(0xffff0), 2);
1434
1435	/* Save values to compare later to. */
1436	uint32_t u32IoAddressBase = pGlobals->uPciBiosIo;
1437	uint32_t u32MMIOAddressBase = pGlobals->uPciBiosMmio;
1438
1439	/* Init devices behind the bridge and possibly other bridges as well. */
1440	for (int iDev = 0; iDev <= 255; iDev++)
1441	ich9pciBiosInitDevice(pGlobals, uBus + 1, iDev, cBridgeDepth + 1, paBridgePositions);
1442
1443	/* The number of bridges behind the this one is now available. */
1444	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_SUBORDINATE_BUS, pGlobals->uBus, 1);
1445
1446	/*
1447	* Set I/O limit register. If there is no device with I/O space behind the bridge
1448	* we set a lower value than in the base register.
1449	* The result with a real bridge is that no I/O transactions are passed to the secondary
1450	* interface. Again this doesn't really matter here but we want to be compliant to the spec.
1451	*/
1452	if ((u32IoAddressBase != pGlobals->uPciBiosIo) && ((pGlobals->uPciBiosIo % 4096) != 0))
1453	{
1454	/* The upper boundary must be one byte less than a 4KB boundary. */
1455	pGlobals->uPciBiosIo = RT_ALIGN_32(pGlobals->uPciBiosIo, 4*1024);
1456	}
1457
1458	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_IO_LIMIT, ((pGlobals->uPciBiosIo >> 8) & 0xf0) - 1, 1);
1459
1460	/* Same with the MMIO limit register but with 1MB boundary here. */
1461	if ((u32MMIOAddressBase != pGlobals->uPciBiosMmio) && ((pGlobals->uPciBiosMmio % (1024 * 1024)) != 0))
1462	{
1463	/* The upper boundary must be one byte less than a 1MB boundary. */
1464	pGlobals->uPciBiosMmio = RT_ALIGN_32(pGlobals->uPciBiosMmio, 1024*1024);
1465	}
1466	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_MEMORY_LIMIT, ((pGlobals->uPciBiosMmio >> 16) & UINT32_C(0xfff0)) - 1, 2);
1467
1468	/*
1469	* Set the prefetch base and limit registers. We currently have no device with a prefetchable region
1470	* which may be behind a bridge. Thatswhy it is unconditionally disabled here atm by writing a higher value into
1471	* the base register than in the limit register.
1472	*/
1473	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_MEMORY_BASE, 0xfff0, 2);
1474	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_MEMORY_LIMIT, 0x0, 2);
1475	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_BASE_UPPER32, 0x00, 4);
1476	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_LIMIT_UPPER32, 0x00, 4);
1477	}
1478
1479	static void ich9pciBiosInitDevice(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint8_t cBridgeDepth, uint8_t *paBridgePositions)
1480	{
1481	uint32_t *paddr;
1482	uint16_t uDevClass, uVendor, uDevice;
1483	uint8_t uCmd;
1484
1485	uDevClass = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_CLASS_DEVICE, 2);
1486	uVendor = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_VENDOR_ID, 2);
1487	uDevice = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_DEVICE_ID, 2);
1488
1489	/* If device is present */
1490	if (uVendor == 0xffff)
1491	return;
1492
1493	switch (uDevClass)
1494	{
1495	case 0x0101:
1496	/* IDE controller */
1497	ich9pciConfigWrite(pGlobals, uBus, uDevFn, 0x40, 0x8000, 2); /* enable IDE0 */
1498	ich9pciConfigWrite(pGlobals, uBus, uDevFn, 0x42, 0x8000, 2); /* enable IDE1 */
1499	goto default_map;
1500	break;
1501	case 0x0300:
1502	/* VGA controller */
1503	if (uVendor != 0x80ee)
1504	goto default_map;
1505	/* VGA: map frame buffer to default Bochs VBE address */
1506	ich9pciSetRegionAddress(pGlobals, uBus, uDevFn, 0, 0xE0000000);
1507	/*
1508	* Legacy VGA I/O ports are implicitly decoded by a VGA class device. But
1509	* only the framebuffer (i.e., a memory region) is explicitly registered via
1510	* ich9pciSetRegionAddress, so I/O decoding must be enabled manually.
1511	*/
1512	uCmd = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_COMMAND, 1);
1513	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_COMMAND,
1514	/* Enable I/O space access. */
1515	uCmd \| PCI_COMMAND_IOACCESS,
1516	1);
1517	break;
1518	case 0x0800:
1519	/* PIC */
1520	if (uVendor == 0x1014)
1521	{
1522	/* IBM */
1523	if (uDevice == 0x0046 \|\| uDevice == 0xFFFF)
1524	/* MPIC & MPIC2 */
1525	ich9pciSetRegionAddress(pGlobals, uBus, uDevFn, 0, 0x80800000 + 0x00040000);
1526	}
1527	break;
1528	case 0xff00:
1529	if ((uVendor == 0x0106b)
1530	&& (uDevice == 0x0017 \|\| uDevice == 0x0022))
1531	{
1532	/* macio bridge */
1533	ich9pciSetRegionAddress(pGlobals, uBus, uDevFn, 0, 0x80800000);
1534	}
1535	break;
1536	case 0x0604:
1537	/* PCI-to-PCI bridge. */
1538	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_PRIMARY_BUS, uBus, 1);
1539
1540	AssertMsg(pGlobals->uBus < 255, ("Too many bridges on the bus\n"));
1541	pGlobals->uBus++;
1542	ich9pciBiosInitBridge(pGlobals, uBus, uDevFn, cBridgeDepth, paBridgePositions);
1543	break;
1544	default:
1545	default_map:
1546	{
1547	/* default memory mappings */
1548	/*
1549	* We ignore ROM region here.
1550	*/
1551	for (int iRegion = 0; iRegion < (PCI_NUM_REGIONS-1); iRegion++)
1552	{
1553	uint32_t u32Address = ich9pciGetRegionReg(iRegion);
1554
1555	/* Calculate size. */
1556	uint8_t u8ResourceType = ich9pciConfigRead(pGlobals, uBus, uDevFn, u32Address, 1);
1557	ich9pciConfigWrite(pGlobals, uBus, uDevFn, u32Address, UINT32_C(0xffffffff), 4);
1558	uint32_t u32Size = ich9pciConfigRead(pGlobals, uBus, uDevFn, u32Address, 4);
1559	/* Clear resource information depending on resource type. */
1560	if ((u8ResourceType & PCI_COMMAND_IOACCESS) == PCI_COMMAND_IOACCESS) /* I/O */
1561	u32Size &= ~(0x01);
1562	else /* MMIO */
1563	u32Size &= ~(0x0f);
1564
1565	bool fIsPio = ((u8ResourceType & PCI_COMMAND_IOACCESS) == PCI_COMMAND_IOACCESS);
1566	/*
1567	* Invert all bits and add 1 to get size of the region.
1568	* (From PCI implementation note)
1569	*/
1570	if (fIsPio && (u32Size & UINT32_C(0xffff0000)) == 0)
1571	u32Size = (~(u32Size \| UINT32_C(0xffff0000))) + 1;
1572	else
1573	u32Size = (~u32Size) + 1;
1574
1575	Log(("%s: Size of region %u for device %d on bus %d is %u\n", __FUNCTION__, iRegion, uDevFn, uBus, u32Size));
1576
1577	if (u32Size)
1578	{
1579	paddr = fIsPio ? &pGlobals->uPciBiosIo : &pGlobals->uPciBiosMmio;
1580	paddr = (paddr + u32Size - 1) & ~(u32Size - 1);
1581	Log(("%s: Start address of %s region %u is %#x\n", __FUNCTION__, (fIsPio ? "I/O" : "MMIO"), iRegion, *paddr));
1582	ich9pciSetRegionAddress(pGlobals, uBus, uDevFn, iRegion, *paddr);
1583	*paddr += u32Size;
1584	Log(("%s: New address is %#x\n", __FUNCTION__, *paddr));
1585	}
1586	}
1587	break;
1588	}
1589	}
1590
1591	/* map the interrupt */
1592	uint32_t uPin = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_INTERRUPT_PIN, 1);
1593	if (uPin != 0)
1594	{
1595	uint8_t uBridgeDevFn = uDevFn;
1596	uPin--;
1597
1598	/* We need to go up to the host bus to see which irq this device will assert there. */
1599	while (cBridgeDepth != 0)
1600	{
1601	/* Get the pin the device would assert on the bridge. */
1602	uPin = ((uBridgeDevFn >> 3) + uPin) & 3;
1603	uBridgeDevFn = paBridgePositions[cBridgeDepth];
1604	cBridgeDepth--;
1605	}
1606	}
1607	}
1608
1609	static const uint8_t auPciIrqs[4] = { 11, 9, 11, 9 };
1610
1611	static DECLCALLBACK(int) ich9pciFakePCIBIOS(PPDMDEVINS pDevIns)
1612	{
1613	unsigned i;
1614	uint8_t elcr[2] = {0, 0};
1615	PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
1616	PVM pVM = PDMDevHlpGetVM(pDevIns);
1617	Assert(pVM);
1618
1619	/*
1620	* Set the start addresses.
1621	*/
1622	pGlobals->uPciBiosIo = 0xd000;
1623	pGlobals->uPciBiosMmio = UINT32_C(0xf0000000);
1624	pGlobals->uBus = 0;
1625
1626	/*
1627	* Activate IRQ mappings.
1628	*/
1629	for (i = 0; i < 4; i++)
1630	{
1631	uint8_t irq = auPciIrqs[i];
1632	/* Set to trigger level. */
1633	elcr[irq >> 3] \|= (1 << (irq & 7));
1634	}
1635
1636	/* Tell to the PIC. */
1637	VBOXSTRICTRC rcStrict = IOMIOPortWrite(pVM, 0x4d0, elcr[0], sizeof(uint8_t));
1638	if (rcStrict == VINF_SUCCESS)
1639	rcStrict = IOMIOPortWrite(pVM, 0x4d1, elcr[1], sizeof(uint8_t));
1640	if (rcStrict != VINF_SUCCESS)
1641	{
1642	AssertMsgFailed(("Writing to PIC failed! rcStrict=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
1643	return RT_SUCCESS(rcStrict) ? VERR_INTERNAL_ERROR : VBOXSTRICTRC_VAL(rcStrict);
1644	}
1645
1646	/*
1647	* Init the devices.
1648	*/
1649	for (i = 0; i < 256; i++)
1650	{
1651	uint8_t aBridgePositions[256];
1652
1653	memset(aBridgePositions, 0, sizeof(aBridgePositions));
1654	Log2(("PCI: Initializing device %d (%#x)\n",
1655	i, 0x80000000 \| (i << 8)));
1656	ich9pciBiosInitDevice(pGlobals, 0, i, 0, aBridgePositions);
1657	}
1658
1659	return VINF_SUCCESS;
1660	}
1661
1662	static DECLCALLBACK(uint32_t) ich9pciConfigReadDev(PCIDevice *aDev, uint32_t u32Address, unsigned len)
1663	{
1664	if ((u32Address + len) > 256 && (u32Address + len) < 4096)
1665	{
1666	AssertMsgReturn(false, ("Read from extended registers falled back to generic code\n"), 0);
1667	}
1668
1669	if ( PCIIsMsiCapable(aDev)
1670	&& (u32Address >= aDev->Int.s.u8MsiCapOffset)
1671	&& (u32Address < aDev->Int.s.u8MsiCapOffset + aDev->Int.s.u8MsiCapSize)
1672	)
1673	{
1674	return MsiPciConfigRead(aDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pDevIns), aDev, u32Address, len);
1675	}
1676
1677	AssertMsgReturn(u32Address + len <= 256, ("Read after end of PCI config space\n"),
1678	0);
1679	switch (len)
1680	{
1681	case 1:
1682	return PCIDevGetByte(aDev, u32Address);
1683	case 2:
1684	return PCIDevGetWord(aDev, u32Address);
1685	case 4:
1686	return PCIDevGetDWord(aDev, u32Address);
1687	default:
1688	Assert(false);
1689	return 0;
1690	}
1691	}
1692
1693
1694	/**
1695	* See paragraph 7.5 of PCI Express specification (p. 349) for definition of
1696	* registers and their writability policy.
1697	*/
1698	static DECLCALLBACK(void) ich9pciConfigWriteDev(PCIDevice *aDev, uint32_t u32Address,
1699	uint32_t val, unsigned len)
1700	{
1701	Assert(len <= 4);
1702
1703	if ((u32Address + len) > 256 && (u32Address + len) < 4096)
1704	{
1705	AssertMsgReturnVoid(false, ("Write to extended registers falled back to generic code\n"));
1706	}
1707
1708	AssertMsgReturnVoid(u32Address + len <= 256, ("Write after end of PCI config space\n"));
1709
1710	if ( PCIIsMsiCapable(aDev)
1711	&& (u32Address >= aDev->Int.s.u8MsiCapOffset)
1712	&& (u32Address < aDev->Int.s.u8MsiCapOffset + aDev->Int.s.u8MsiCapSize)
1713	)
1714	{
1715	MsiPciConfigWrite(aDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pDevIns),
1716	aDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pPciHlp),
1717	aDev, u32Address, val, len);
1718	return;
1719	}
1720
1721
1722	/* Fast case - update one of BARs or ROM address, 'while' only for 'break' */
1723	while ( len == 4
1724	&& ( ( u32Address >= VBOX_PCI_BASE_ADDRESS_0
1725	&& u32Address < VBOX_PCI_BASE_ADDRESS_0 + 6 * 4)
1726	\|\| ( u32Address >= VBOX_PCI_ROM_ADDRESS
1727	&& u32Address < VBOX_PCI_ROM_ADDRESS+4)
1728	)
1729	)
1730	{
1731	PCIIORegion *pRegion;
1732	int reg, regionSize;
1733
1734	reg = (u32Address >= VBOX_PCI_ROM_ADDRESS) ? PCI_ROM_SLOT : (u32Address - VBOX_PCI_BASE_ADDRESS_0) >> 2;
1735	pRegion = &aDev->Int.s.aIORegions[reg];
1736	regionSize = pRegion->size;
1737	if (regionSize == 0)
1738	break;
1739	/* compute the stored value */
1740	if (reg == PCI_ROM_SLOT) {
1741	/* keep ROM enable bit */
1742	val &= (~(regionSize - 1)) \| 1;
1743	} else {
1744	val &= ~(regionSize - 1);
1745	val \|= pRegion->type;
1746	}
1747	PCIDevSetDWord(aDev, u32Address, val);
1748	ich9pciUpdateMappings(aDev);
1749	return;
1750	}
1751
1752	uint32_t addr = u32Address;
1753	bool fUpdateMappings = false;
1754	for (uint32_t i = 0; i < len; i++)
1755	{
1756	bool fWritable = false;
1757	switch (PCIDevGetHeaderType(aDev))
1758	{
1759	case 0x00: /* normal device */
1760	case 0x80: /* multi-function device */
1761	switch (addr)
1762	{
1763	/* Read-only registers */
1764	case VBOX_PCI_VENDOR_ID: case VBOX_PCI_VENDOR_ID+1:
1765	case VBOX_PCI_DEVICE_ID: case VBOX_PCI_DEVICE_ID+1:
1766	case VBOX_PCI_REVISION_ID:
1767	case VBOX_PCI_CLASS_PROG:
1768	case VBOX_PCI_CLASS_SUB:
1769	case VBOX_PCI_CLASS_BASE:
1770	case VBOX_PCI_HEADER_TYPE:
1771	case VBOX_PCI_BASE_ADDRESS_0: case VBOX_PCI_BASE_ADDRESS_0+1: case VBOX_PCI_BASE_ADDRESS_0+2: case VBOX_PCI_BASE_ADDRESS_0+3:
1772	case VBOX_PCI_BASE_ADDRESS_1: case VBOX_PCI_BASE_ADDRESS_1+1: case VBOX_PCI_BASE_ADDRESS_1+2: case VBOX_PCI_BASE_ADDRESS_1+3:
1773	case VBOX_PCI_BASE_ADDRESS_2: case VBOX_PCI_BASE_ADDRESS_2+1: case VBOX_PCI_BASE_ADDRESS_2+2: case VBOX_PCI_BASE_ADDRESS_2+3:
1774	case VBOX_PCI_BASE_ADDRESS_3: case VBOX_PCI_BASE_ADDRESS_3+1: case VBOX_PCI_BASE_ADDRESS_3+2: case VBOX_PCI_BASE_ADDRESS_3+3:
1775	case VBOX_PCI_BASE_ADDRESS_4: case VBOX_PCI_BASE_ADDRESS_4+1: case VBOX_PCI_BASE_ADDRESS_4+2: case VBOX_PCI_BASE_ADDRESS_4+3:
1776	case VBOX_PCI_BASE_ADDRESS_5: case VBOX_PCI_BASE_ADDRESS_5+1: case VBOX_PCI_BASE_ADDRESS_5+2: case VBOX_PCI_BASE_ADDRESS_5+3:
1777	case VBOX_PCI_SUBSYSTEM_VENDOR_ID: case VBOX_PCI_SUBSYSTEM_VENDOR_ID+1:
1778	case VBOX_PCI_SUBSYSTEM_ID: case VBOX_PCI_SUBSYSTEM_ID+1:
1779	case VBOX_PCI_ROM_ADDRESS: case VBOX_PCI_ROM_ADDRESS+1: case VBOX_PCI_ROM_ADDRESS+2: case VBOX_PCI_ROM_ADDRESS+3:
1780	case VBOX_PCI_CAPABILITY_LIST:
1781	case VBOX_PCI_INTERRUPT_PIN:
1782	fWritable = false;
1783	break;
1784	/* Others can be written */
1785	default:
1786	fWritable = true;
1787	break;
1788	}
1789	break;
1790	default:
1791	case 0x01: /* PCI-PCI bridge */
1792	switch (addr)
1793	{
1794	/* Read-only registers */
1795	case VBOX_PCI_VENDOR_ID: case VBOX_PCI_VENDOR_ID+1:
1796	case VBOX_PCI_DEVICE_ID: case VBOX_PCI_DEVICE_ID+1:
1797	case VBOX_PCI_REVISION_ID:
1798	case VBOX_PCI_CLASS_PROG:
1799	case VBOX_PCI_CLASS_SUB:
1800	case VBOX_PCI_CLASS_BASE:
1801	case VBOX_PCI_HEADER_TYPE:
1802	case VBOX_PCI_ROM_ADDRESS_BR: case VBOX_PCI_ROM_ADDRESS_BR+1: case VBOX_PCI_ROM_ADDRESS_BR+2: case VBOX_PCI_ROM_ADDRESS_BR+3:
1803	case VBOX_PCI_INTERRUPT_PIN:
1804	fWritable = false;
1805	break;
1806	default:
1807	fWritable = true;
1808	break;
1809	}
1810	break;
1811	}
1812
1813	uint8_t u8Val = (uint8_t)val;
1814
1815	switch (addr)
1816	{
1817	case VBOX_PCI_COMMAND: /* Command register, bits 0-7. */
1818	fUpdateMappings = true;
1819	PCIDevSetByte(aDev, addr, u8Val);
1820	break;
1821	case VBOX_PCI_COMMAND+1: /* Command register, bits 8-15. */
1822	/* don't change reserved bits (11-15) */
1823	u8Val &= UINT32_C(~0xf8);
1824	fUpdateMappings = true;
1825	PCIDevSetByte(aDev, addr, u8Val);
1826	break;
1827	case VBOX_PCI_STATUS: /* Status register, bits 0-7. */
1828	/* don't change read-only bits => actually all lower bits are read-only */
1829	u8Val &= UINT32_C(~0xff);
1830	/* status register, low part: clear bits by writing a '1' to the corresponding bit */
1831	aDev->config[addr] &= ~u8Val;
1832	break;
1833	case VBOX_PCI_STATUS+1: /* Status register, bits 8-15. */
1834	/* don't change read-only bits */
1835	u8Val &= UINT32_C(~0x06);
1836	/* status register, high part: clear bits by writing a '1' to the corresponding bit */
1837	aDev->config[addr] &= ~u8Val;
1838	break;
1839	default:
1840	if (fWritable)
1841	PCIDevSetByte(aDev, addr, u8Val);
1842	}
1843	addr++;
1844	val >>= 8;
1845	}
1846
1847	if (fUpdateMappings)
1848	/* if the command register is modified, we must modify the mappings */
1849	ich9pciUpdateMappings(aDev);
1850	}
1851
1852	/* Slot/functions assignment per table at p. 12 of ICH9 family spec update */
1853	static const struct {
1854	const char* pszName;
1855	int32_t iSlot;
1856	int32_t iFunction;
1857	} PciSlotAssignments[] = {
1858	{
1859	"lan", 25, 0 /* LAN controller */
1860	},
1861	{
1862	"hda", 27, 0 /* High Definition Audio */
1863	},
1864	{
1865	"i82801", 30, 0 /* Host Controller */
1866	},
1867	/**
1868	* Please note, that for devices being functions, like we do here, device 0
1869	* must be multifunction, i.e. have header type 0x80. Our LPC device is.
1870	* Alternative approach is to assign separate slot to each device.
1871	*/
1872	{
1873	"lpc", 31, 0 /* Low Pin Count bus */
1874	},
1875	{
1876	"piix3ide", 31, 1 /* IDE controller */
1877	},
1878	/* Disable, if we may wish to have multiple AHCI controllers */
1879	#if 1
1880	{
1881	"ahci", 31, 2 /* SATA controller */
1882	},
1883	#endif
1884	{
1885	"smbus", 31, 3 /* System Management Bus */
1886	},
1887	{
1888	"usb-ohci", 31, 4 /* OHCI USB controller */
1889	},
1890	{
1891	"usb-ehci", 31, 5 /* EHCI USB controller */
1892	},
1893	{
1894	"thermal", 31, 6 /* Thermal controller */
1895	},
1896	};
1897
1898	static int assignPosition(PPCIBUS pBus, PPCIDEVICE pPciDev, const char *pszName, int iDevFn)
1899	{
1900	/* Hardcoded slots/functions, per chipset spec */
1901	for (size_t i = 0; i < RT_ELEMENTS(PciSlotAssignments); i++)
1902	{
1903	if (!strcmp(pszName, PciSlotAssignments[i].pszName))
1904	{
1905	PCISetRequestedDevfunc(pPciDev);
1906	return (PciSlotAssignments[i].iSlot << 3) + PciSlotAssignments[i].iFunction;
1907	}
1908	}
1909
1910	if (iDevFn >=0 && iDevFn < (int)RT_ELEMENTS(pBus->apDevices))
1911	return iDevFn;
1912
1913	/* Otherwise when assigning a slot, we need to make sure all its functions are available */
1914	for (int iPos = 0; iPos < (int)RT_ELEMENTS(pBus->apDevices); iPos += 8)
1915	{
1916	if ( !pBus->apDevices[iPos]
1917	&& !pBus->apDevices[iPos + 1]
1918	&& !pBus->apDevices[iPos + 2]
1919	&& !pBus->apDevices[iPos + 3]
1920	&& !pBus->apDevices[iPos + 4]
1921	&& !pBus->apDevices[iPos + 5]
1922	&& !pBus->apDevices[iPos + 6]
1923	&& !pBus->apDevices[iPos + 7])
1924	{
1925	PCIClearRequestedDevfunc(pPciDev);
1926	return iPos;
1927	}
1928	}
1929
1930	return -1;
1931	}
1932
1933	static bool hasHardAssignedDevsInSlot(PPCIBUS pBus, int iSlot)
1934	{
1935	PCIDevice** aSlot = &pBus->apDevices[iSlot << 3];
1936
1937	return (aSlot[0] && PCIIsRequestedDevfunc(aSlot[0]))
1938	\|\| (aSlot[1] && PCIIsRequestedDevfunc(aSlot[1]))
1939	\|\| (aSlot[2] && PCIIsRequestedDevfunc(aSlot[2]))
1940	\|\| (aSlot[3] && PCIIsRequestedDevfunc(aSlot[3]))
1941	\|\| (aSlot[4] && PCIIsRequestedDevfunc(aSlot[4]))
1942	\|\| (aSlot[5] && PCIIsRequestedDevfunc(aSlot[5]))
1943	\|\| (aSlot[6] && PCIIsRequestedDevfunc(aSlot[6]))
1944	\|\| (aSlot[7] && PCIIsRequestedDevfunc(aSlot[7]))
1945	;
1946	}
1947
1948	static int ich9pciRegisterInternal(PPCIBUS pBus, int iDev, PPCIDEVICE pPciDev, const char *pszName)
1949	{
1950	/*
1951	* Find device position
1952	*/
1953	iDev = assignPosition(pBus, pPciDev, pszName, iDev);
1954	if (iDev < 0)
1955	{
1956	AssertMsgFailed(("Couldn't find free spot!\n"));
1957	return VERR_PDM_TOO_PCI_MANY_DEVICES;
1958	}
1959
1960	/*
1961	* Check if we can really take this slot, possibly by relocating
1962	* its current habitant, if it wasn't hard assigned too.
1963	*/
1964	if (PCIIsRequestedDevfunc(pPciDev) &&
1965	pBus->apDevices[iDev] &&
1966	PCIIsRequestedDevfunc(pBus->apDevices[iDev]))
1967	{
1968	AssertReleaseMsgFailed(("Configuration error:'%s' and '%s' are both configured as device %d\n",
1969	pszName, pBus->apDevices[iDev]->name, iDev));
1970	return VERR_INTERNAL_ERROR;
1971	}
1972
1973	if (pBus->apDevices[iDev])
1974	{
1975	/* if we got here, we shall (and usually can) relocate the device */
1976	int iRelDev = assignPosition(pBus, pBus->apDevices[iDev], pBus->apDevices[iDev]->name, -1);
1977	if (iRelDev < 0 \|\| iRelDev == iDev)
1978	{
1979	AssertMsgFailed(("Couldn't find free spot!\n"));
1980	return VERR_PDM_TOO_PCI_MANY_DEVICES;
1981	}
1982	/* Copy device function by function to its new position */
1983	for (int i = 0; i < 8; i++)
1984	{
1985	if (!pBus->apDevices[iDev + i])
1986	continue;
1987	Log(("PCI: relocating '%s' from slot %#x to %#x\n", pBus->apDevices[iDev + i]->name, iDev + i, iRelDev + i));
1988	pBus->apDevices[iRelDev + i] = pBus->apDevices[iDev + i];
1989	pBus->apDevices[iRelDev + i]->devfn = iRelDev + i;
1990	pBus->apDevices[iDev + i] = NULL;
1991	}
1992	}
1993
1994	/*
1995	* Fill in device information.
1996	*/
1997	pPciDev->devfn = iDev;
1998	pPciDev->name = pszName;
1999	pPciDev->Int.s.pBusR3 = pBus;
2000	pPciDev->Int.s.pBusR0 = MMHyperR3ToR0(PDMDevHlpGetVM(pBus->CTX_SUFF(pDevIns)), pBus);
2001	pPciDev->Int.s.pBusRC = MMHyperR3ToRC(PDMDevHlpGetVM(pBus->CTX_SUFF(pDevIns)), pBus);
2002	pPciDev->Int.s.pfnConfigRead = ich9pciConfigReadDev;
2003	pPciDev->Int.s.pfnConfigWrite = ich9pciConfigWriteDev;
2004	pBus->apDevices[iDev] = pPciDev;
2005	if (PCIIsPci2PciBridge(pPciDev))
2006	{
2007	AssertMsg(pBus->cBridges < RT_ELEMENTS(pBus->apDevices), ("Number of bridges exceeds the number of possible devices on the bus\n"));
2008	AssertMsg(pPciDev->Int.s.pfnBridgeConfigRead && pPciDev->Int.s.pfnBridgeConfigWrite,
2009	("device is a bridge but does not implement read/write functions\n"));
2010	pBus->papBridgesR3[pBus->cBridges] = pPciDev;
2011	pBus->cBridges++;
2012	}
2013
2014	Log(("PCI: Registered device %d function %d (%#x) '%s'.\n",
2015	iDev >> 3, iDev & 7, 0x80000000 \| (iDev << 8), pszName));
2016
2017	return VINF_SUCCESS;
2018	}
2019
2020
2021	/**
2022	* Info handler, device version.
2023	*
2024	* @param pDevIns Device instance which registered the info.
2025	* @param pHlp Callback functions for doing output.
2026	* @param pszArgs Argument string. Optional and specific to the handler.
2027	*/
2028	static DECLCALLBACK(void) ich9pciInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
2029	{
2030	PPCIBUS pBus = DEVINS_2_PCIBUS(pDevIns);
2031	uint32_t iBus = 0, iDev;
2032
2033
2034	for (iDev = 0; iDev < RT_ELEMENTS(pBus->apDevices); iDev++)
2035	{
2036	PPCIDEVICE pPciDev = pBus->apDevices[iDev];
2037	if (pPciDev != NULL)
2038	pHlp->pfnPrintf(pHlp, "%02x:%02x:%02x %s: %x-%x\n",
2039	iBus, (iDev >> 3) & 0xff, iDev & 0x7,
2040	pPciDev->name,
2041	PCIDevGetVendorId(pPciDev), PCIDevGetDeviceId(pPciDev)
2042	);
2043	}
2044	}
2045
2046
2047	static DECLCALLBACK(int) ich9pciConstruct(PPDMDEVINS pDevIns,
2048	int iInstance,
2049	PCFGMNODE pCfg)
2050	{
2051	int rc;
2052	Assert(iInstance == 0);
2053
2054	/*
2055	* Validate and read configuration.
2056	*/
2057	if (!CFGMR3AreValuesValid(pCfg,
2058	"IOAPIC\0"
2059	"GCEnabled\0"
2060	"R0Enabled\0"
2061	"McfgBase\0"
2062	"McfgLength\0"
2063	))
2064	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
2065
2066	/* query whether we got an IOAPIC */
2067	bool fUseIoApic;
2068	rc = CFGMR3QueryBoolDef(pCfg, "IOAPIC", &fUseIoApic, false);
2069	if (RT_FAILURE(rc))
2070	return PDMDEV_SET_ERROR(pDevIns, rc,
2071	N_("Configuration error: Failed to query boolean value \"IOAPIC\""));
2072
2073	/* check if RC code is enabled. */
2074	bool fGCEnabled;
2075	rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
2076	if (RT_FAILURE(rc))
2077	return PDMDEV_SET_ERROR(pDevIns, rc,
2078	N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
2079
2080	/* check if R0 code is enabled. */
2081	bool fR0Enabled;
2082	rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
2083	if (RT_FAILURE(rc))
2084	return PDMDEV_SET_ERROR(pDevIns, rc,
2085	N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
2086
2087	Log(("PCI: fUseIoApic=%RTbool fGCEnabled=%RTbool fR0Enabled=%RTbool\n", fUseIoApic, fGCEnabled, fR0Enabled));
2088
2089	/*
2090	* Init data.
2091	*/
2092	PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
2093	PPCIBUS pBus = &pGlobals->aPciBus;
2094	/* Zero out everything */
2095	memset(pGlobals, 0, sizeof(*pGlobals));
2096	/* And fill values */
2097	if (!fUseIoApic)
2098	return PDMDEV_SET_ERROR(pDevIns, rc,
2099	N_("Must use IO-APIC with ICH9 chipset"));
2100	rc = CFGMR3QueryU64Def(pCfg, "McfgBase", &pGlobals->u64PciConfigMMioAddress, 0);
2101	if (RT_FAILURE(rc))
2102	return PDMDEV_SET_ERROR(pDevIns, rc,
2103	N_("Configuration error: Failed to read \"McfgBase\""));
2104	rc = CFGMR3QueryU64Def(pCfg, "McfgLength", &pGlobals->u64PciConfigMMioLength, 0);
2105	if (RT_FAILURE(rc))
2106	return PDMDEV_SET_ERROR(pDevIns, rc,
2107	N_("Configuration error: Failed to read \"McfgLength\""));
2108
2109	pGlobals->pDevInsR3 = pDevIns;
2110	pGlobals->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2111	pGlobals->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2112
2113	pGlobals->aPciBus.pDevInsR3 = pDevIns;
2114	pGlobals->aPciBus.pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2115	pGlobals->aPciBus.pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2116	pGlobals->aPciBus.papBridgesR3 = (PPCIDEVICE )PDMDevHlpMMHeapAllocZ(pDevIns, sizeof(PPCIDEVICE) RT_ELEMENTS(pGlobals->aPciBus.apDevices));
2117
2118	/*
2119	* Register bus
2120	*/
2121	PDMPCIBUSREG PciBusReg;
2122	PciBusReg.u32Version = PDM_PCIBUSREG_VERSION;
2123	PciBusReg.pfnRegisterR3 = ich9pciRegister;
2124	PciBusReg.pfnRegisterMsiR3 = ich9pciRegisterMsi;
2125	PciBusReg.pfnIORegionRegisterR3 = ich9pciIORegionRegister;
2126	PciBusReg.pfnSetConfigCallbacksR3 = ich9pciSetConfigCallbacks;
2127	PciBusReg.pfnSetIrqR3 = ich9pciSetIrq;
2128	PciBusReg.pfnSaveExecR3 = ich9pciGenericSaveExec;
2129	PciBusReg.pfnLoadExecR3 = ich9pciGenericLoadExec;
2130	PciBusReg.pfnFakePCIBIOSR3 = ich9pciFakePCIBIOS;
2131	PciBusReg.pszSetIrqRC = fGCEnabled ? "ich9pciSetIrq" : NULL;
2132	PciBusReg.pszSetIrqR0 = fR0Enabled ? "ich9pciSetIrq" : NULL;
2133	rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBus->pPciHlpR3);
2134	if (RT_FAILURE(rc))
2135	return PDMDEV_SET_ERROR(pDevIns, rc,
2136	N_("Failed to register ourselves as a PCI Bus"));
2137	if (pBus->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
2138	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
2139	N_("PCI helper version mismatch; got %#x expected %#x"),
2140	pBus->pPciHlpR3->u32Version, PDM_PCIHLPR3_VERSION);
2141
2142	pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
2143	pBus->pPciHlpR0 = pBus->pPciHlpR3->pfnGetR0Helpers(pDevIns);
2144
2145	/*
2146	* Fill in PCI configs and add them to the bus.
2147	*/
2148
2149	/**
2150	* We emulate 82801IB ICH9 IO chip used in Q35,
2151	* see http://ark.intel.com/Product.aspx?id=31892
2152	*
2153	* Stepping S-Spec Top Marking
2154	*
2155	* A2 SLA9M NH82801IB
2156	*/
2157	PCIDevSetVendorId( &pBus->aPciDev, 0x8086); /* Intel */
2158	PCIDevSetDeviceId( &pBus->aPciDev, 0x244e); /* Desktop */
2159	PCIDevSetRevisionId(&pBus->aPciDev, 0x92); /* rev. A2 */
2160	PCIDevSetClassSub( &pBus->aPciDev, 0x00); /* Host/PCI bridge */
2161	PCIDevSetClassBase( &pBus->aPciDev, 0x06); /* bridge */
2162	PCIDevSetHeaderType(&pBus->aPciDev, 0x00); /* normal device */
2163
2164	pBus->aPciDev.pDevIns = pDevIns;
2165	/* We register Host<->PCI controller on the bus */
2166	ich9pciRegisterInternal(pBus, -1, &pBus->aPciDev, "i82801");
2167
2168	/*
2169	* Register I/O ports and save state.
2170	*/
2171	rc = PDMDevHlpIOPortRegister(pDevIns, 0x0cf8, 1, NULL, ich9pciIOPortAddressWrite, ich9pciIOPortAddressRead, NULL, NULL, "ICH9 (PCI)");
2172	if (RT_FAILURE(rc))
2173	return rc;
2174	rc = PDMDevHlpIOPortRegister(pDevIns, 0x0cfc, 4, NULL, ich9pciIOPortDataWrite, ich9pciIOPortDataRead, NULL, NULL, "ICH9 (PCI)");
2175	if (RT_FAILURE(rc))
2176	return rc;
2177	if (fGCEnabled)
2178	{
2179	rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x0cf8, 1, NIL_RTGCPTR, "ich9pciIOPortAddressWrite", "ich9pciIOPortAddressRead", NULL, NULL, "ICH9 (PCI)");
2180	if (RT_FAILURE(rc))
2181	return rc;
2182	rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x0cfc, 4, NIL_RTGCPTR, "ich9pciIOPortDataWrite", "ich9pciIOPortDataRead", NULL, NULL, "ICH9 (PCI)");
2183	if (RT_FAILURE(rc))
2184	return rc;
2185	}
2186	if (fR0Enabled)
2187	{
2188	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x0cf8, 1, NIL_RTR0PTR, "ich9pciIOPortAddressWrite", "ich9pciIOPortAddressRead", NULL, NULL, "ICH9 (PCI)");
2189	if (RT_FAILURE(rc))
2190	return rc;
2191	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x0cfc, 4, NIL_RTR0PTR, "ich9pciIOPortDataWrite", "ich9pciIOPortDataRead", NULL, NULL, "ICH9 (PCI)");
2192	if (RT_FAILURE(rc))
2193	return rc;
2194	}
2195
2196	if (pGlobals->u64PciConfigMMioAddress != 0)
2197	{
2198	rc = PDMDevHlpMMIORegister(pDevIns,
2199	pGlobals->u64PciConfigMMioAddress,
2200	pGlobals->u64PciConfigMMioLength,
2201	0,
2202	ich9pciMcfgMMIOWrite,
2203	ich9pciMcfgMMIORead,
2204	NULL /* fill */,
2205	"MCFG ranges");
2206	if (RT_FAILURE(rc))
2207	{
2208	AssertMsgRC(rc, ("Cannot register MCFG MMIO: %Rrc\n", rc));
2209	return rc;
2210	}
2211
2212	if (fGCEnabled)
2213	{
2214
2215	rc = PDMDevHlpMMIORegisterRC(pDevIns,
2216	pGlobals->u64PciConfigMMioAddress,
2217	pGlobals->u64PciConfigMMioLength,
2218	0,
2219	"ich9pciMcfgMMIOWrite",
2220	"ich9pciMcfgMMIORead",
2221	NULL /* fill */);
2222	if (RT_FAILURE(rc))
2223	{
2224	AssertMsgRC(rc, ("Cannot register MCFG MMIO (GC): %Rrc\n", rc));
2225	return rc;
2226	}
2227	}
2228
2229
2230	if (fR0Enabled)
2231	{
2232
2233	rc = PDMDevHlpMMIORegisterR0(pDevIns,
2234	pGlobals->u64PciConfigMMioAddress,
2235	pGlobals->u64PciConfigMMioLength,
2236	0,
2237	"ich9pciMcfgMMIOWrite",
2238	"ich9pciMcfgMMIORead",
2239	NULL /* fill */);
2240	if (RT_FAILURE(rc))
2241	{
2242	AssertMsgRC(rc, ("Cannot register MCFG MMIO (R0): %Rrc\n", rc));
2243	return rc;
2244	}
2245	}
2246	}
2247
2248	rc = PDMDevHlpSSMRegisterEx(pDevIns, VBOX_ICH9PCI_SAVED_STATE_VERSION_CURRENT,
2249	sizeof(pBus) + 16128, "pgm",
2250	NULL, NULL, NULL,
2251	NULL, ich9pciR3SaveExec, NULL,
2252	NULL, ich9pciR3LoadExec, NULL);
2253	if (RT_FAILURE(rc))
2254	return rc;
2255
2256
2257	/** @todo: other chipset devices shall be registered too */
2258	/** @todo: what to with bridges? */
2259
2260	PDMDevHlpDBGFInfoRegister(pDevIns, "pci", "Display PCI bus status. (no arguments)", ich9pciInfo);
2261
2262	return VINF_SUCCESS;
2263	}
2264
2265	static void ich9pciResetDevice(PPCIDEVICE pDev)
2266	{
2267	pDev->config[VBOX_PCI_COMMAND] &= ~(VBOX_PCI_COMMAND_IO \| VBOX_PCI_COMMAND_MEMORY \|
2268	VBOX_PCI_COMMAND_MASTER);
2269
2270	if (!PCIIsPci2PciBridge(pDev))
2271	{
2272	PCIDevSetByte(pDev, VBOX_PCI_CACHE_LINE_SIZE, 0x0);
2273	PCIDevSetByte(pDev, VBOX_PCI_INTERRUPT_LINE, 0x0);
2274	}
2275	/* Regions ? */
2276	}
2277
2278
2279	/**
2280	* @copydoc FNPDMDEVRESET
2281	*/
2282	static DECLCALLBACK(void) ich9pciReset(PPDMDEVINS pDevIns)
2283	{
2284	PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
2285	PPCIBUS pBus = &pGlobals->aPciBus;
2286
2287	/* Relocate RC pointers for the attached pci devices. */
2288	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
2289	{
2290	if (pBus->apDevices[i])
2291	ich9pciResetDevice(pBus->apDevices[i]);
2292	}
2293	}
2294
2295	/**
2296	* @copydoc FNPDMDEVRELOCATE
2297	*/
2298	static DECLCALLBACK(void) ich9pciRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
2299	{
2300	PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
2301	PPCIBUS pBus = &pGlobals->aPciBus;
2302	pGlobals->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2303
2304	pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
2305	pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2306
2307	/* Relocate RC pointers for the attached pci devices. */
2308	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
2309	{
2310	if (pBus->apDevices[i])
2311	pBus->apDevices[i]->Int.s.pBusRC += offDelta;
2312	}
2313
2314	}
2315
2316	/**
2317	* @interface_method_impl{PDMDEVREG,pfnConstruct}
2318	*/
2319	static DECLCALLBACK(int) ich9pcibridgeConstruct(PPDMDEVINS pDevIns,
2320	int iInstance,
2321	PCFGMNODE pCfg)
2322	{
2323	int rc;
2324
2325	/*
2326	* Validate and read configuration.
2327	*/
2328	if (!CFGMR3AreValuesValid(pCfg, "GCEnabled\0" "R0Enabled\0"))
2329	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
2330
2331	/* check if RC code is enabled. */
2332	bool fGCEnabled;
2333	rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
2334	if (RT_FAILURE(rc))
2335	return PDMDEV_SET_ERROR(pDevIns, rc,
2336	N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
2337
2338	/* check if R0 code is enabled. */
2339	bool fR0Enabled;
2340	rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
2341	if (RT_FAILURE(rc))
2342	return PDMDEV_SET_ERROR(pDevIns, rc,
2343	N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
2344	Log(("PCI: fGCEnabled=%RTbool fR0Enabled=%RTbool\n", fGCEnabled, fR0Enabled));
2345
2346	/*
2347	* Init data and register the PCI bus.
2348	*/
2349	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
2350	pBus->pDevInsR3 = pDevIns;
2351	pBus->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2352	pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2353	pBus->papBridgesR3 = (PPCIDEVICE )PDMDevHlpMMHeapAllocZ(pDevIns, sizeof(PPCIDEVICE) RT_ELEMENTS(pBus->apDevices));
2354
2355	PDMPCIBUSREG PciBusReg;
2356	PciBusReg.u32Version = PDM_PCIBUSREG_VERSION;
2357	PciBusReg.pfnRegisterR3 = ich9pcibridgeRegister;
2358	PciBusReg.pfnRegisterMsiR3 = ich9pciRegisterMsi;
2359	PciBusReg.pfnIORegionRegisterR3 = ich9pciIORegionRegister;
2360	PciBusReg.pfnSetConfigCallbacksR3 = ich9pciSetConfigCallbacks;
2361	PciBusReg.pfnSetIrqR3 = ich9pcibridgeSetIrq;
2362	PciBusReg.pfnSaveExecR3 = ich9pciGenericSaveExec;
2363	PciBusReg.pfnLoadExecR3 = ich9pciGenericLoadExec;
2364	PciBusReg.pfnFakePCIBIOSR3 = NULL; /* Only needed for the first bus. */
2365	PciBusReg.pszSetIrqRC = fGCEnabled ? "ich9pcibridgeSetIrq" : NULL;
2366	PciBusReg.pszSetIrqR0 = fR0Enabled ? "ich9pcibridgeSetIrq" : NULL;
2367	rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBus->pPciHlpR3);
2368	if (RT_FAILURE(rc))
2369	return PDMDEV_SET_ERROR(pDevIns, rc,
2370	N_("Failed to register ourselves as a PCI Bus"));
2371	if (pBus->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
2372	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
2373	N_("PCI helper version mismatch; got %#x expected %#x"),
2374	pBus->pPciHlpR3->u32Version, PDM_PCIHLPR3_VERSION);
2375
2376	pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
2377	pBus->pPciHlpR0 = pBus->pPciHlpR3->pfnGetR0Helpers(pDevIns);
2378
2379	/*
2380	* Fill in PCI configs and add them to the bus.
2381	*/
2382	PCIDevSetVendorId( &pBus->aPciDev, 0x8086); /* Intel */
2383	PCIDevSetDeviceId( &pBus->aPciDev, 0x2448); /* 82801 Mobile PCI bridge. */
2384	PCIDevSetRevisionId(&pBus->aPciDev, 0xf2);
2385	PCIDevSetClassSub( &pBus->aPciDev, 0x04); /* pci2pci */
2386	PCIDevSetClassBase( &pBus->aPciDev, 0x06); /* PCI_bridge */
2387	PCIDevSetClassProg( &pBus->aPciDev, 0x01); /* Supports subtractive decoding. */
2388	PCIDevSetHeaderType(&pBus->aPciDev, 0x01); /* Single function device which adheres to the PCI-to-PCI bridge spec. */
2389	PCIDevSetCommand( &pBus->aPciDev, 0x00);
2390	PCIDevSetStatus( &pBus->aPciDev, 0x20); /* 66MHz Capable. */
2391	PCIDevSetInterruptLine(&pBus->aPciDev, 0x00); /* This device does not assert interrupts. */
2392
2393	/*
2394	* This device does not generate interrupts. Interrupt delivery from
2395	* devices attached to the bus is unaffected.
2396	*/
2397	PCIDevSetInterruptPin (&pBus->aPciDev, 0x00);
2398
2399	pBus->aPciDev.pDevIns = pDevIns;
2400
2401	/* Bridge-specific data */
2402	PCISetPci2PciBridge(&pBus->aPciDev);
2403	pBus->aPciDev.Int.s.pfnBridgeConfigRead = ich9pcibridgeConfigRead;
2404	pBus->aPciDev.Int.s.pfnBridgeConfigWrite = ich9pcibridgeConfigWrite;
2405
2406	/*
2407	* Register this PCI bridge. The called function will take care on which bus we will get registered.
2408	*/
2409	rc = PDMDevHlpPCIRegister (pDevIns, &pBus->aPciDev);
2410	if (RT_FAILURE(rc))
2411	return rc;
2412
2413	/*
2414	* The iBus property doesn't really represent the bus number
2415	* because the guest and the BIOS can choose different bus numbers
2416	* for them.
2417	* The bus number is mainly for the setIrq function to indicate
2418	* when the host bus is reached which will have iBus = 0.
2419	* Thathswhy the + 1.
2420	*/
2421	pBus->iBus = iInstance + 1;
2422
2423	/*
2424	* Register SSM handlers. We use the same saved state version as for the host bridge
2425	* to make changes easier.
2426	*/
2427	rc = PDMDevHlpSSMRegisterEx(pDevIns, VBOX_ICH9PCI_SAVED_STATE_VERSION_CURRENT,
2428	sizeof(pBus) + 16128,
2429	"pgm" /* before */,
2430	NULL, NULL, NULL,
2431	NULL, ich9pcibridgeR3SaveExec, NULL,
2432	NULL, ich9pcibridgeR3LoadExec, NULL);
2433	if (RT_FAILURE(rc))
2434	return rc;
2435
2436
2437	return VINF_SUCCESS;
2438	}
2439
2440	/**
2441	* @copydoc FNPDMDEVRESET
2442	*/
2443	static DECLCALLBACK(void) ich9pcibridgeReset(PPDMDEVINS pDevIns)
2444	{
2445	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
2446
2447	/* Reset config space to default values. */
2448	PCIDevSetByte(&pBus->aPciDev, VBOX_PCI_PRIMARY_BUS, 0);
2449	PCIDevSetByte(&pBus->aPciDev, VBOX_PCI_SECONDARY_BUS, 0);
2450	PCIDevSetByte(&pBus->aPciDev, VBOX_PCI_SUBORDINATE_BUS, 0);
2451	}
2452
2453
2454	/**
2455	* @copydoc FNPDMDEVRELOCATE
2456	*/
2457	static DECLCALLBACK(void) ich9pcibridgeRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
2458	{
2459	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
2460	pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2461
2462	/* Relocate RC pointers for the attached pci devices. */
2463	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
2464	{
2465	if (pBus->apDevices[i])
2466	pBus->apDevices[i]->Int.s.pBusRC += offDelta;
2467	}
2468
2469	}
2470
2471	/**
2472	* The PCI bus device registration structure.
2473	*/
2474	const PDMDEVREG g_DevicePciIch9 =
2475	{
2476	/* u32Version */
2477	PDM_DEVREG_VERSION,
2478	/* szName */
2479	"ich9pci",
2480	/* szRCMod */
2481	"VBoxDDGC.gc",
2482	/* szR0Mod */
2483	"VBoxDDR0.r0",
2484	/* pszDescription */
2485	"ICH9 PCI bridge",
2486	/* fFlags */
2487	PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
2488	/* fClass */
2489	PDM_DEVREG_CLASS_BUS_PCI \| PDM_DEVREG_CLASS_BUS_ISA,
2490	/* cMaxInstances */
2491	1,
2492	/* cbInstance */
2493	sizeof(PCIGLOBALS),
2494	/* pfnConstruct */
2495	ich9pciConstruct,
2496	/* pfnDestruct */
2497	NULL,
2498	/* pfnRelocate */
2499	ich9pciRelocate,
2500	/* pfnIOCtl */
2501	NULL,
2502	/* pfnPowerOn */
2503	NULL,
2504	/* pfnReset */
2505	ich9pciReset,
2506	/* pfnSuspend */
2507	NULL,
2508	/* pfnResume */
2509	NULL,
2510	/* pfnAttach */
2511	NULL,
2512	/* pfnDetach */
2513	NULL,
2514	/* pfnQueryInterface */
2515	NULL,
2516	/* pfnInitComplete */
2517	NULL,
2518	/* pfnPowerOff */
2519	NULL,
2520	/* pfnSoftReset */
2521	NULL,
2522	/* u32VersionEnd */
2523	PDM_DEVREG_VERSION
2524	};
2525
2526	/**
2527	* The device registration structure
2528	* for the PCI-to-PCI bridge.
2529	*/
2530	const PDMDEVREG g_DevicePciIch9Bridge =
2531	{
2532	/* u32Version */
2533	PDM_DEVREG_VERSION,
2534	/* szName */
2535	"ich9pcibridge",
2536	/* szRCMod */
2537	"VBoxDDGC.gc",
2538	/* szR0Mod */
2539	"VBoxDDR0.r0",
2540	/* pszDescription */
2541	"ICH9 PCI to PCI bridge",
2542	/* fFlags */
2543	PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
2544	/* fClass */
2545	PDM_DEVREG_CLASS_BUS_PCI,
2546	/* cMaxInstances */
2547	~0,
2548	/* cbInstance */
2549	sizeof(PCIBUS),
2550	/* pfnConstruct */
2551	ich9pcibridgeConstruct,
2552	/* pfnDestruct */
2553	NULL,
2554	/* pfnRelocate */
2555	ich9pcibridgeRelocate,
2556	/* pfnIOCtl */
2557	NULL,
2558	/* pfnPowerOn */
2559	NULL,
2560	/* pfnReset */
2561	ich9pcibridgeReset,
2562	/* pfnSuspend */
2563	NULL,
2564	/* pfnResume */
2565	NULL,
2566	/* pfnAttach */
2567	NULL,
2568	/* pfnDetach */
2569	NULL,
2570	/* pfnQueryInterface */
2571	NULL,
2572	/* pfnInitComplete */
2573	NULL,
2574	/* pfnPowerOff */
2575	NULL,
2576	/* pfnSoftReset */
2577	NULL,
2578	/* u32VersionEnd */
2579	PDM_DEVREG_VERSION
2580	};
2581
2582	#endif /* IN_RING3 */
2583	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */

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source: vbox/trunk/src/VBox/Devices/Bus/DevPciIch9.cpp@ 33215

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