DevPciIch9.cpp@ 33419

Last change on this file since 33419 was 33419, checked in by vboxsync, 14 years ago
PDM, PCI: save MSI-X page in saved state, multiple vectors in MSI, tweaks
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1	/* $Id: DevPciIch9.cpp 33419 2010-10-25 12:45:01Z vboxsync $ */
2	/** @file
3	* DevPCI - ICH9 southbridge PCI bus emulation Device.
4	*/
5
6	/*
7	* Copyright (C) 2010 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/*******************************************************************************
19	* Header Files *
20	*******************************************************************************/
21	#define LOG_GROUP LOG_GROUP_DEV_PCI
22	/* Hack to get PCIDEVICEINT declare at the right point - include "PCIInternal.h". */
23	#define PCI_INCLUDE_PRIVATE
24	#include <VBox/pci.h>
25	#include <VBox/msi.h>
26	#include <VBox/pdmdev.h>
27	#include <iprt/asm.h>
28	#include <iprt/assert.h>
29	#include <iprt/string.h>
30	#ifdef IN_RING3
31	#include <iprt/alloc.h>
32	#endif
33
34	#include "../Builtins.h"
35
36	#include "MsiCommon.h"
37
38	/**
39	* PCI Bus instance.
40	*/
41	typedef struct PCIBus
42	{
43	/** Bus number. */
44	int32_t iBus;
45	/** Number of bridges attached to the bus. */
46	uint32_t cBridges;
47
48	/** Array of PCI devices. We assume 32 slots, each with 8 functions. */
49	R3PTRTYPE(PPCIDEVICE) apDevices[256];
50	/** Array of bridges attached to the bus. */
51	R3PTRTYPE(PPCIDEVICE *) papBridgesR3;
52
53	/** R3 pointer to the device instance. */
54	PPDMDEVINSR3 pDevInsR3;
55	/** Pointer to the PCI R3 helpers. */
56	PCPDMPCIHLPR3 pPciHlpR3;
57
58	/** R0 pointer to the device instance. */
59	PPDMDEVINSR0 pDevInsR0;
60	/** Pointer to the PCI R0 helpers. */
61	PCPDMPCIHLPR0 pPciHlpR0;
62
63	/** RC pointer to the device instance. */
64	PPDMDEVINSRC pDevInsRC;
65	/** Pointer to the PCI RC helpers. */
66	PCPDMPCIHLPRC pPciHlpRC;
67
68	/** The PCI device for the PCI bridge. */
69	PCIDEVICE aPciDev;
70
71	} PCIBUS, *PPCIBUS;
72
73
74	/** @def PCI_APIC_IRQ_PINS
75	* Number of pins for interrupts if the APIC is used.
76	*/
77	#define PCI_APIC_IRQ_PINS 8
78
79	/**
80	* PCI Globals - This is the host-to-pci bridge and the root bus.
81	*/
82	typedef struct
83	{
84	/** R3 pointer to the device instance. */
85	PPDMDEVINSR3 pDevInsR3;
86	/** R0 pointer to the device instance. */
87	PPDMDEVINSR0 pDevInsR0;
88	/** RC pointer to the device instance. */
89	PPDMDEVINSRC pDevInsRC;
90
91	#if HC_ARCH_BITS == 64
92	uint32_t Alignment0;
93	#endif
94
95	/** I/O APIC irq levels */
96	volatile uint32_t uaPciApicIrqLevels[PCI_APIC_IRQ_PINS];
97
98	#if 1 /* Will be moved into the BIOS soon. */
99	/** The next I/O port address which the PCI BIOS will use. */
100	uint32_t uPciBiosIo;
101	/** The next MMIO address which the PCI BIOS will use. */
102	uint32_t uPciBiosMmio;
103	/** Actual bus number. */
104	uint8_t uBus;
105	#endif
106	/* Physical address of PCI config space MMIO region */
107	uint64_t u64PciConfigMMioAddress;
108	/* Length of PCI config space MMIO region */
109	uint64_t u64PciConfigMMioLength;
110
111
112	/** Config register. */
113	uint32_t uConfigReg;
114
115	/** PCI bus which is attached to the host-to-PCI bridge. */
116	PCIBUS aPciBus;
117
118	} PCIGLOBALS, *PPCIGLOBALS;
119
120
121	typedef struct {
122	uint8_t iBus;
123	uint8_t iDeviceFunc;
124	uint16_t iRegister;
125	} PciAddress;
126
127	/*******************************************************************************
128	* Defined Constants And Macros *
129	*******************************************************************************/
130
131	/** @def VBOX_ICH9PCI_SAVED_STATE_VERSION
132	* Saved state version of the ICH9 PCI bus device.
133	*/
134	#define VBOX_ICH9PCI_SAVED_STATE_VERSION_NOMSI 1
135	#define VBOX_ICH9PCI_SAVED_STATE_VERSION_MSI 2
136	#define VBOX_ICH9PCI_SAVED_STATE_VERSION_CURRENT VBOX_ICH9PCI_SAVED_STATE_VERSION_MSI
137
138	/** Converts a bus instance pointer to a device instance pointer. */
139	#define PCIBUS_2_DEVINS(pPciBus) ((pPciBus)->CTX_SUFF(pDevIns))
140	/** Converts a device instance pointer to a PCIGLOBALS pointer. */
141	#define DEVINS_2_PCIGLOBALS(pDevIns) ((PPCIGLOBALS)(PDMINS_2_DATA(pDevIns, PPCIGLOBALS)))
142	/** Converts a device instance pointer to a PCIBUS pointer. */
143	#define DEVINS_2_PCIBUS(pDevIns) ((PPCIBUS)(&PDMINS_2_DATA(pDevIns, PPCIGLOBALS)->aPciBus))
144	/** Converts a pointer to a PCI root bus instance to a PCIGLOBALS pointer.
145	*/
146	#define PCIROOTBUS_2_PCIGLOBALS(pPciBus) ( (PPCIGLOBALS)((uintptr_t)(pPciBus) - RT_OFFSETOF(PCIGLOBALS, aPciBus)) )
147
148
149	/** @def PCI_LOCK
150	* Acquires the PDM lock. This is a NOP if locking is disabled. */
151	/** @def PCI_UNLOCK
152	* Releases the PDM lock. This is a NOP if locking is disabled. */
153	#define PCI_LOCK(pDevIns, rc) \
154	do { \
155	int rc2 = DEVINS_2_PCIBUS(pDevIns)->CTX_SUFF(pPciHlp)->pfnLock((pDevIns), rc); \
156	if (rc2 != VINF_SUCCESS) \
157	return rc2; \
158	} while (0)
159	#define PCI_UNLOCK(pDevIns) \
160	DEVINS_2_PCIBUS(pDevIns)->CTX_SUFF(pPciHlp)->pfnUnlock(pDevIns)
161
162	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
163
164	RT_C_DECLS_BEGIN
165
166	PDMBOTHCBDECL(void) ich9pciSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel);
167	PDMBOTHCBDECL(void) ich9pcibridgeSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel);
168	PDMBOTHCBDECL(int) ich9pciIOPortAddressWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
169	PDMBOTHCBDECL(int) ich9pciIOPortAddressRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb);
170	PDMBOTHCBDECL(int) ich9pciIOPortDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
171	PDMBOTHCBDECL(int) ich9pciIOPortDataRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb);
172	PDMBOTHCBDECL(int) ich9pciMcfgMMIOWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb);
173	PDMBOTHCBDECL(int) ich9pciMcfgMMIORead (PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb);
174
175	RT_C_DECLS_END
176
177	/* Prototypes */
178	static void ich9pciSetIrqInternal(PPCIGLOBALS pGlobals, uint8_t uDevFn, PPCIDEVICE pPciDev, int iIrq, int iLevel);
179	#ifdef IN_RING3
180	static int ich9pciRegisterInternal(PPCIBUS pBus, int iDev, PPCIDEVICE pPciDev, const char *pszName);
181	static void ich9pciUpdateMappings(PCIDevice *pDev);
182	static DECLCALLBACK(uint32_t) ich9pciConfigReadDev(PCIDevice *aDev, uint32_t u32Address, unsigned len);
183	DECLINLINE(PPCIDEVICE) ich9pciFindBridge(PPCIBUS pBus, uint8_t iBus);
184	static void ich9pciBiosInitDevice(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint8_t cBridgeDepth, uint8_t *paBridgePositions);
185	#endif
186
187	// See 7.2.2. PCI Express Enhanced Configuration Mechanism for details of address
188	// mapping, we take n=6 approach
189	DECLINLINE(void) ich9pciPhysToPciAddr(PPCIGLOBALS pGlobals, RTGCPHYS GCPhysAddr, PciAddress* pPciAddr)
190	{
191	GCPhysAddr = GCPhysAddr - pGlobals->u64PciConfigMMioAddress;
192	pPciAddr->iBus = (GCPhysAddr >> 20) & ((1<<8) - 1);
193	pPciAddr->iDeviceFunc = (GCPhysAddr >> 12) & ((1<<(5+3)) - 1); // 5 bits - device, 3 bits - function
194	pPciAddr->iRegister = (GCPhysAddr >> 0) & ((1<<(6+4+2)) - 1); // 6 bits - register, 4 bits - extended register, 2 bits -Byte Enable
195	}
196
197	DECLINLINE(void) ich9pciStateToPciAddr(PPCIGLOBALS pGlobals, RTGCPHYS addr, PciAddress* pPciAddr)
198	{
199	pPciAddr->iBus = (pGlobals->uConfigReg >> 16) & 0xff;
200	pPciAddr->iDeviceFunc = (pGlobals->uConfigReg >> 8) & 0xff;
201	pPciAddr->iRegister = (pGlobals->uConfigReg & 0xfc) \| (addr & 3);
202	}
203
204	PDMBOTHCBDECL(void) ich9pciSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel)
205	{
206	ich9pciSetIrqInternal(PDMINS_2_DATA(pDevIns, PPCIGLOBALS), pPciDev->devfn, pPciDev, iIrq, iLevel);
207	}
208
209	PDMBOTHCBDECL(void) ich9pcibridgeSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel)
210	{
211	/*
212	* The PCI-to-PCI bridge specification defines how the interrupt pins
213	* are routed from the secondary to the primary bus (see chapter 9).
214	* iIrq gives the interrupt pin the pci device asserted.
215	* We change iIrq here according to the spec and call the SetIrq function
216	* of our parent passing the device which asserted the interrupt instead of the device of the bridge.
217	*/
218	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
219	PPCIDEVICE pPciDevBus = pPciDev;
220	int iIrqPinBridge = iIrq;
221	uint8_t uDevFnBridge = 0;
222
223	/* Walk the chain until we reach the host bus. */
224	do
225	{
226	uDevFnBridge = pBus->aPciDev.devfn;
227	iIrqPinBridge = ((pPciDevBus->devfn >> 3) + iIrqPinBridge) & 3;
228
229	/* Get the parent. */
230	pBus = pBus->aPciDev.Int.s.CTX_SUFF(pBus);
231	pPciDevBus = &pBus->aPciDev;
232	} while (pBus->iBus != 0);
233
234	AssertMsgReturnVoid(pBus->iBus == 0, ("This is not the host pci bus iBus=%d\n", pBus->iBus));
235	ich9pciSetIrqInternal(PCIROOTBUS_2_PCIGLOBALS(pBus), uDevFnBridge, pPciDev, iIrqPinBridge, iLevel);
236	}
237
238	/**
239	* Port I/O Handler for PCI address OUT operations.
240	*
241	* @returns VBox status code.
242	*
243	* @param pDevIns The device instance.
244	* @param pvUser User argument - ignored.
245	* @param uPort Port number used for the OUT operation.
246	* @param u32 The value to output.
247	* @param cb The value size in bytes.
248	*/
249	PDMBOTHCBDECL(int) ich9pciIOPortAddressWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
250	{
251	Log(("ich9pciIOPortAddressWrite: Port=%#x u32=%#x cb=%d\n", Port, u32, cb));
252	NOREF(pvUser);
253	if (cb == 4)
254	{
255	PPCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
256	PCI_LOCK(pDevIns, VINF_IOM_HC_IOPORT_WRITE);
257	pThis->uConfigReg = u32 & ~3; /* Bits 0-1 are reserved and we silently clear them */
258	PCI_UNLOCK(pDevIns);
259	}
260	return VINF_SUCCESS;
261	}
262
263	/**
264	* Port I/O Handler for PCI address IN operations.
265	*
266	* @returns VBox status code.
267	*
268	* @param pDevIns The device instance.
269	* @param pvUser User argument - ignored.
270	* @param uPort Port number used for the IN operation.
271	* @param pu32 Where to store the result.
272	* @param cb Number of bytes read.
273	*/
274	PDMBOTHCBDECL(int) ich9pciIOPortAddressRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
275	{
276	NOREF(pvUser);
277	if (cb == 4)
278	{
279	PPCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
280	PCI_LOCK(pDevIns, VINF_IOM_HC_IOPORT_READ);
281	*pu32 = pThis->uConfigReg;
282	PCI_UNLOCK(pDevIns);
283	Log(("pciIOPortAddressRead: Port=%#x cb=%d -> %#x\n", Port, cb, *pu32));
284	return VINF_SUCCESS;
285	}
286
287	Log(("ich9pciIOPortAddressRead: Port=%#x cb=%d VERR_IOM_IOPORT_UNUSED\n", Port, cb));
288
289	return VERR_IOM_IOPORT_UNUSED;
290	}
291
292	static int ich9pciDataWriteAddr(PPCIGLOBALS pGlobals, PciAddress* pAddr, uint32_t val, int len)
293	{
294
295	if (pAddr->iRegister > 0xff)
296	{
297	LogRel(("PCI: attempt to write extended register: %x (%d) <- val\n", pAddr->iRegister, len, val));
298	return 0;
299	}
300
301	if (pAddr->iBus != 0)
302	{
303	if (pGlobals->aPciBus.cBridges)
304	{
305	#ifdef IN_RING3 /** @todo do lookup in R0/RC too! */
306	PPCIDEVICE pBridgeDevice = ich9pciFindBridge(&pGlobals->aPciBus, pAddr->iBus);
307	if (pBridgeDevice)
308	{
309	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigWrite);
310	pBridgeDevice->Int.s.pfnBridgeConfigWrite(pBridgeDevice->pDevIns, pAddr->iBus, pAddr->iDeviceFunc, pAddr->iRegister, val, len);
311	}
312	#else
313	return VINF_IOM_HC_IOPORT_WRITE;
314	#endif
315	}
316	}
317	else
318	{
319	if (pGlobals->aPciBus.apDevices[pAddr->iDeviceFunc])
320	{
321	#ifdef IN_RING3
322	R3PTRTYPE(PCIDevice *) aDev = pGlobals->aPciBus.apDevices[pAddr->iDeviceFunc];
323	Log(("ich9pciConfigWrite: %s: addr=%02x val=%08x len=%d\n", aDev->name, pAddr->iRegister, val, len));
324	aDev->Int.s.pfnConfigWrite(aDev, pAddr->iRegister, val, len);
325	#else
326	return VINF_IOM_HC_IOPORT_WRITE;
327	#endif
328	}
329	}
330	return VINF_SUCCESS;
331	}
332
333	static int ich9pciDataWrite(PPCIGLOBALS pGlobals, uint32_t addr, uint32_t val, int len)
334	{
335	PciAddress aPciAddr;
336
337	Log(("ich9pciDataWrite: addr=%08x val=%08x len=%d\n", pGlobals->uConfigReg, val, len));
338
339	if (!(pGlobals->uConfigReg & (1 << 31)))
340	return VINF_SUCCESS;
341
342	if ((pGlobals->uConfigReg & 0x3) != 0)
343	return VINF_SUCCESS;
344
345	/* Compute destination device */
346	ich9pciStateToPciAddr(pGlobals, addr, &aPciAddr);
347
348	return ich9pciDataWriteAddr(pGlobals, &aPciAddr, val, len);
349	}
350
351	/**
352	* Port I/O Handler for PCI data OUT operations.
353	*
354	* @returns VBox status code.
355	*
356	* @param pDevIns The device instance.
357	* @param pvUser User argument - ignored.
358	* @param uPort Port number used for the OUT operation.
359	* @param u32 The value to output.
360	* @param cb The value size in bytes.
361	*/
362	PDMBOTHCBDECL(int) ich9pciIOPortDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
363	{
364	Log(("pciIOPortDataWrite: Port=%#x u32=%#x cb=%d\n", Port, u32, cb));
365	NOREF(pvUser);
366	int rc = VINF_SUCCESS;
367	if (!(Port % cb))
368	{
369	PCI_LOCK(pDevIns, VINF_IOM_HC_IOPORT_WRITE);
370	rc = ich9pciDataWrite(PDMINS_2_DATA(pDevIns, PPCIGLOBALS), Port, u32, cb);
371	PCI_UNLOCK(pDevIns);
372	}
373	else
374	AssertMsgFailed(("Unaligned write to port %#x u32=%#x cb=%d\n", Port, u32, cb));
375	return rc;
376	}
377
378	static int ich9pciDataReadAddr(PPCIGLOBALS pGlobals, PciAddress* pPciAddr, int len, uint32_t *pu32)
379	{
380	if (pPciAddr->iRegister > 0xff)
381	{
382	LogRel(("PCI: attempt to read extended register: %x\n", pPciAddr->iRegister));
383	*pu32 = 0;
384	return 0;
385	}
386
387
388	if (pPciAddr->iBus != 0)
389	{
390	if (pGlobals->aPciBus.cBridges)
391	{
392	#ifdef IN_RING3 /** @todo do lookup in R0/RC too! */
393	PPCIDEVICE pBridgeDevice = ich9pciFindBridge(&pGlobals->aPciBus, pPciAddr->iBus);
394	if (pBridgeDevice)
395	{
396	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigRead);
397	*pu32 = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->pDevIns, pPciAddr->iBus, pPciAddr->iDeviceFunc, pPciAddr->iRegister, len);
398	}
399	#else
400	return VINF_IOM_HC_IOPORT_READ;
401	#endif
402	}
403	}
404	else
405	{
406	if (pGlobals->aPciBus.apDevices[pPciAddr->iDeviceFunc])
407	{
408	#ifdef IN_RING3
409	R3PTRTYPE(PCIDevice *) aDev = pGlobals->aPciBus.apDevices[pPciAddr->iDeviceFunc];
410	*pu32 = aDev->Int.s.pfnConfigRead(aDev, pPciAddr->iRegister, len);
411	Log(("ich9pciDataReadAddr: %s: addr=%02x val=%08x len=%d\n", aDev->name, pPciAddr->iRegister, *pu32, len));
412	#else
413	return VINF_IOM_HC_IOPORT_READ;
414	#endif
415	}
416	}
417
418	return VINF_SUCCESS;
419	}
420
421	static int ich9pciDataRead(PPCIGLOBALS pGlobals, uint32_t addr, int len, uint32_t *pu32)
422	{
423	PciAddress aPciAddr;
424
425	*pu32 = 0xffffffff;
426
427	if (!(pGlobals->uConfigReg & (1 << 31)))
428	return VINF_SUCCESS;
429
430	if ((pGlobals->uConfigReg & 0x3) != 0)
431	return VINF_SUCCESS;
432
433	/* Compute destination device */
434	ich9pciStateToPciAddr(pGlobals, addr, &aPciAddr);
435
436	return ich9pciDataReadAddr(pGlobals, &aPciAddr, len, pu32);
437	}
438
439	/**
440	* Port I/O Handler for PCI data IN operations.
441	*
442	* @returns VBox status code.
443	*
444	* @param pDevIns The device instance.
445	* @param pvUser User argument - ignored.
446	* @param uPort Port number used for the IN operation.
447	* @param pu32 Where to store the result.
448	* @param cb Number of bytes read.
449	*/
450	PDMBOTHCBDECL(int) ich9pciIOPortDataRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
451	{
452	NOREF(pvUser);
453	if (!(Port % cb))
454	{
455	PCI_LOCK(pDevIns, VINF_IOM_HC_IOPORT_READ);
456	int rc = ich9pciDataRead(PDMINS_2_DATA(pDevIns, PPCIGLOBALS), Port, cb, pu32);
457	PCI_UNLOCK(pDevIns);
458	Log(("pciIOPortDataRead: Port=%#x cb=%#x -> %#x (%Rrc)\n", Port, cb, *pu32, rc));
459	return rc;
460	}
461	AssertMsgFailed(("Unaligned read from port %#x cb=%d\n", Port, cb));
462	return VERR_IOM_IOPORT_UNUSED;
463	}
464
465	/* Compute mapping of PCI slot and IRQ number to APIC interrupt line */
466	DECLINLINE(int) ich9pciSlot2ApicIrq(uint8_t uSlot, int irq_num)
467	{
468	return (irq_num + uSlot) & 7;
469	}
470
471	/* Add one more level up request on APIC input line */
472	DECLINLINE(void) ich9pciApicLevelUp(PPCIGLOBALS pGlobals, int irq_num)
473	{
474	ASMAtomicIncU32(&pGlobals->uaPciApicIrqLevels[irq_num]);
475	}
476
477	/* Remove one level up request on APIC input line */
478	DECLINLINE(void) ich9pciApicLevelDown(PPCIGLOBALS pGlobals, int irq_num)
479	{
480	ASMAtomicDecU32(&pGlobals->uaPciApicIrqLevels[irq_num]);
481	}
482
483	static void ich9pciApicSetIrq(PPCIBUS pBus, uint8_t uDevFn, PCIDevice *pPciDev, int irq_num1, int iLevel, int iForcedIrq)
484	{
485	/* This is only allowed to be called with a pointer to the root bus. */
486	AssertMsg(pBus->iBus == 0, ("iBus=%u\n", pBus->iBus));
487
488	if (iForcedIrq == -1)
489	{
490	int apic_irq, apic_level;
491	PPCIGLOBALS pGlobals = PCIROOTBUS_2_PCIGLOBALS(pBus);
492	int irq_num = ich9pciSlot2ApicIrq(uDevFn >> 3, irq_num1);
493
494	if ((iLevel & PDM_IRQ_LEVEL_HIGH) == PDM_IRQ_LEVEL_HIGH)
495	ich9pciApicLevelUp(pGlobals, irq_num);
496	else if ((iLevel & PDM_IRQ_LEVEL_HIGH) == PDM_IRQ_LEVEL_LOW)
497	ich9pciApicLevelDown(pGlobals, irq_num);
498
499	apic_irq = irq_num + 0x10;
500	apic_level = pGlobals->uaPciApicIrqLevels[irq_num] != 0;
501	Log3(("ich9pciApicSetIrq: %s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d\n",
502	R3STRING(pPciDev->name), irq_num1, iLevel, apic_irq, apic_level, irq_num));
503	pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), apic_irq, apic_level);
504
505	if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP)
506	{
507	/**
508	* we raised it few lines above, as PDM_IRQ_LEVEL_FLIP_FLOP has
509	* PDM_IRQ_LEVEL_HIGH bit set
510	*/
511	ich9pciApicLevelDown(pGlobals, irq_num);
512	pPciDev->Int.s.uIrqPinState = PDM_IRQ_LEVEL_LOW;
513	apic_level = pGlobals->uaPciApicIrqLevels[irq_num] != 0;
514	Log3(("ich9pciApicSetIrq: %s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d (flop)\n",
515	R3STRING(pPciDev->name), irq_num1, iLevel, apic_irq, apic_level, irq_num));
516	pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), apic_irq, apic_level);
517	}
518	} else {
519	Log3(("ich9pciApicSetIrq: %s: irq_num1=%d level=%d acpi_irq=%d\n",
520	R3STRING(pPciDev->name), irq_num1, iLevel, iForcedIrq));
521	pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), iForcedIrq, iLevel);
522	}
523	}
524
525	static void ich9pciSetIrqInternal(PPCIGLOBALS pGlobals, uint8_t uDevFn, PPCIDEVICE pPciDev, int iIrq, int iLevel)
526	{
527
528	if (PCIDevIsIntxDisabled(pPciDev))
529	{
530	if (MsiIsEnabled(pPciDev))
531	{
532	PPDMDEVINS pDevIns = pGlobals->aPciBus.CTX_SUFF(pDevIns);
533	MsiNotify(pDevIns, pGlobals->aPciBus.CTX_SUFF(pPciHlp), pPciDev, iIrq, iLevel);
534	}
535
536	if (MsixIsEnabled(pPciDev))
537	{
538	PPDMDEVINS pDevIns = pGlobals->aPciBus.CTX_SUFF(pDevIns);
539	MsixNotify(pDevIns, pGlobals->aPciBus.CTX_SUFF(pPciHlp), pPciDev, iIrq, iLevel);
540	}
541	return;
542	}
543
544	PPCIBUS pBus = &pGlobals->aPciBus;
545	const bool fIsAcpiDevice = PCIDevGetDeviceId(pPciDev) == 0x7113;
546
547	/* Check if the state changed. */
548	if (pPciDev->Int.s.uIrqPinState != iLevel)
549	{
550	pPciDev->Int.s.uIrqPinState = (iLevel & PDM_IRQ_LEVEL_HIGH);
551
552	/* Send interrupt to I/O APIC only now. */
553	if (fIsAcpiDevice)
554	/*
555	* ACPI needs special treatment since SCI is hardwired and
556	* should not be affected by PCI IRQ routing tables at the
557	* same time SCI IRQ is shared in PCI sense hence this
558	* kludge (i.e. we fetch the hardwired value from ACPIs
559	* PCI device configuration space).
560	*/
561	ich9pciApicSetIrq(pBus, uDevFn, pPciDev, -1, iLevel, PCIDevGetInterruptLine(pPciDev));
562	else
563	ich9pciApicSetIrq(pBus, uDevFn, pPciDev, iIrq, iLevel, -1);
564	}
565	}
566
567	PDMBOTHCBDECL(int) ich9pciMcfgMMIOWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb)
568	{
569	PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
570	PciAddress aDest;
571	uint32_t u32 = 0;
572
573	Log2(("ich9pciMcfgMMIOWrite: %p(%d) \n", GCPhysAddr, cb));
574
575	PCI_LOCK(pDevIns, VINF_IOM_HC_IOPORT_WRITE);
576
577	ich9pciPhysToPciAddr(pGlobals, GCPhysAddr, &aDest);
578
579	switch (cb)
580	{
581	case 1:
582	u32 = (uint8_t)pv;
583	break;
584	case 2:
585	u32 = (uint16_t)pv;
586	break;
587	case 4:
588	u32 = (uint32_t)pv;
589	break;
590	default:
591	Assert(false);
592	break;
593	}
594	int rc = ich9pciDataWriteAddr(pGlobals, &aDest, u32, cb);
595	PCI_UNLOCK(pDevIns);
596
597	return rc;
598	}
599
600	PDMBOTHCBDECL(int) ich9pciMcfgMMIORead (PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb)
601	{
602	PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
603	PciAddress aDest;
604	uint32_t rv = 0xffffffff;
605
606	Log2(("ich9pciMcfgMMIORead: %p(%d) \n", GCPhysAddr, cb));
607
608	PCI_LOCK(pDevIns, VINF_IOM_HC_IOPORT_READ);
609
610	ich9pciPhysToPciAddr(pGlobals, GCPhysAddr, &aDest);
611
612	int rc = ich9pciDataReadAddr(pGlobals, &aDest, cb, &rv);
613
614	switch (cb)
615	{
616	case 1:
617	(uint8_t)pv = (uint8_t)rv;
618	break;
619	case 2:
620	(uint16_t)pv = (uint16_t)rv;
621	break;
622	case 4:
623	(uint32_t)pv = (uint32_t)rv;
624	break;
625	default:
626	Assert(false);
627	break;
628	}
629	PCI_UNLOCK(pDevIns);
630
631	return rc;
632	}
633
634	#ifdef IN_RING3
635
636	DECLINLINE(PPCIDEVICE) ich9pciFindBridge(PPCIBUS pBus, uint8_t iBus)
637	{
638	/* Search for a fitting bridge. */
639	for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
640	{
641	/*
642	* Examine secondary and subordinate bus number.
643	* If the target bus is in the range we pass the request on to the bridge.
644	*/
645	PPCIDEVICE pBridgeTemp = pBus->papBridgesR3[iBridge];
646	AssertMsg(pBridgeTemp && PCIIsPci2PciBridge(pBridgeTemp),
647	("Device is not a PCI bridge but on the list of PCI bridges\n"));
648
649	if ( iBus >= PCIDevGetByte(pBridgeTemp, VBOX_PCI_SECONDARY_BUS)
650	&& iBus <= PCIDevGetByte(pBridgeTemp, VBOX_PCI_SUBORDINATE_BUS))
651	return pBridgeTemp;
652	}
653
654	/* Nothing found. */
655	return NULL;
656	}
657
658	DECLINLINE(uint32_t) ich9pciGetRegionReg(int iRegion)
659	{
660	return (iRegion == PCI_ROM_SLOT) ?
661	VBOX_PCI_ROM_ADDRESS : (VBOX_PCI_BASE_ADDRESS_0 + iRegion * 4);
662	}
663
664	#define INVALID_PCI_ADDRESS ~0U
665
666	static void ich9pciUpdateMappings(PCIDevice* pDev)
667	{
668	PPCIBUS pBus = pDev->Int.s.CTX_SUFF(pBus);
669	uint32_t uLast, uNew;
670
671	int iCmd = PCIDevGetCommand(pDev);
672	for (int iRegion = 0; iRegion < PCI_NUM_REGIONS; iRegion++)
673	{
674	PCIIORegion* pRegion = &pDev->Int.s.aIORegions[iRegion];
675	uint32_t uConfigReg = ich9pciGetRegionReg(iRegion);
676	int32_t iRegionSize = pRegion->size;
677	int rc;
678
679	if (iRegionSize == 0)
680	continue;
681
682	if (pRegion->type & PCI_ADDRESS_SPACE_IO)
683	{
684	/* port IO region */
685	if (iCmd & PCI_COMMAND_IOACCESS)
686	{
687	/* IO access allowed */
688	uNew = ich9pciConfigReadDev(pDev, uConfigReg, 4);
689	uNew &= ~(iRegionSize - 1);
690	uLast = uNew + iRegionSize - 1;
691	/* only 64K ioports on PC */
692	if (uLast <= uNew \|\| uNew == 0 \|\| uLast >= 0x10000)
693	uNew = INVALID_PCI_ADDRESS;
694	} else
695	uNew = INVALID_PCI_ADDRESS;
696	}
697	else
698	{
699	/* MMIO region */
700	if (iCmd & PCI_COMMAND_MEMACCESS)
701	{
702	uNew = ich9pciConfigReadDev(pDev, uConfigReg, 4);
703	/* the ROM slot has a specific enable bit */
704	if (iRegion == PCI_ROM_SLOT && !(uNew & 1))
705	uNew = INVALID_PCI_ADDRESS;
706	else
707	{
708	uNew &= ~(iRegionSize - 1);
709	uLast = uNew + iRegionSize - 1;
710	/* NOTE: we do not support wrapping */
711	/* XXX: as we cannot support really dynamic
712	mappings, we handle specific values as invalid
713	mappings. */
714	if (uLast <= uNew \|\| uNew == 0 \|\| uLast == INVALID_PCI_ADDRESS)
715	uNew = INVALID_PCI_ADDRESS;
716	}
717	} else
718	uNew = INVALID_PCI_ADDRESS;
719	}
720	/* now do the real mapping */
721	if (uNew != pRegion->addr)
722	{
723	if (pRegion->addr != INVALID_PCI_ADDRESS)
724	{
725	if (pRegion->type & PCI_ADDRESS_SPACE_IO)
726	{
727	/* Port IO */
728	rc = PDMDevHlpIOPortDeregister(pDev->pDevIns, pRegion->addr, pRegion->size);
729	AssertRC(rc);
730	}
731	else
732	{
733	RTGCPHYS GCPhysBase = pRegion->addr;
734	if (pBus->pPciHlpR3->pfnIsMMIO2Base(pBus->pDevInsR3, pDev->pDevIns, GCPhysBase))
735	{
736	/* unmap it. */
737	rc = pRegion->map_func(pDev, iRegion, NIL_RTGCPHYS, pRegion->size, (PCIADDRESSSPACE)(pRegion->type));
738	AssertRC(rc);
739	rc = PDMDevHlpMMIO2Unmap(pDev->pDevIns, iRegion, GCPhysBase);
740	}
741	else
742	rc = PDMDevHlpMMIODeregister(pDev->pDevIns, GCPhysBase, pRegion->size);
743	AssertMsgRC(rc, ("rc=%Rrc d=%s i=%d GCPhysBase=%RGp size=%#x\n", rc, pDev->name, iRegion, GCPhysBase, pRegion->size));
744	}
745	}
746	pRegion->addr = uNew;
747	if (pRegion->addr != INVALID_PCI_ADDRESS)
748	{
749	/* finally, map the region */
750	rc = pRegion->map_func(pDev, iRegion,
751	pRegion->addr, pRegion->size,
752	(PCIADDRESSSPACE)(pRegion->type));
753	AssertRC(rc);
754	}
755	}
756	}
757	}
758
759	static DECLCALLBACK(int) ich9pciRegister(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, const char *pszName, int iDev)
760	{
761	PPCIBUS pBus = DEVINS_2_PCIBUS(pDevIns);
762
763	/*
764	* Check input.
765	*/
766	if ( !pszName
767	\|\| !pPciDev
768	\|\| iDev >= (int)RT_ELEMENTS(pBus->apDevices)
769	)
770	{
771	AssertMsgFailed(("Invalid argument! pszName=%s pPciDev=%p iDev=%d\n", pszName, pPciDev, iDev));
772	return VERR_INVALID_PARAMETER;
773	}
774
775	/*
776	* Register the device.
777	*/
778	return ich9pciRegisterInternal(pBus, iDev, pPciDev, pszName);
779	}
780
781
782	static DECLCALLBACK(int) ich9pciRegisterMsi(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PPDMMSIREG pMsiReg)
783	{
784	int rc;
785
786	rc = MsiInit(pPciDev, pMsiReg);
787	if (rc != VINF_SUCCESS)
788	return rc;
789
790	rc = MsixInit(pPciDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pPciHlp), pPciDev, pMsiReg);
791	if (rc != VINF_SUCCESS)
792	return rc;
793
794	return rc;
795	}
796
797
798	static DECLCALLBACK(int) ich9pcibridgeRegister(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, const char *pszName, int iDev)
799	{
800
801	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
802
803	/*
804	* Check input.
805	*/
806	if ( !pszName
807	\|\| !pPciDev
808	\|\| iDev >= (int)RT_ELEMENTS(pBus->apDevices))
809	{
810	AssertMsgFailed(("Invalid argument! pszName=%s pPciDev=%p iDev=%d\n", pszName, pPciDev, iDev));
811	return VERR_INVALID_PARAMETER;
812	}
813
814	/*
815	* Register the device.
816	*/
817	return ich9pciRegisterInternal(pBus, iDev, pPciDev, pszName);
818	}
819
820	static DECLCALLBACK(int) ich9pciIORegionRegister(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iRegion, uint32_t cbRegion, PCIADDRESSSPACE enmType, PFNPCIIOREGIONMAP pfnCallback)
821	{
822	/*
823	* Validate.
824	*/
825	AssertMsgReturn( enmType == PCI_ADDRESS_SPACE_MEM
826	\|\| enmType == PCI_ADDRESS_SPACE_IO
827	\|\| enmType == PCI_ADDRESS_SPACE_MEM_PREFETCH,
828	("Invalid enmType=%#x? Or was this a bitmask after all...\n", enmType),
829	VERR_INVALID_PARAMETER);
830	AssertMsgReturn((unsigned)iRegion < PCI_NUM_REGIONS,
831	("Invalid iRegion=%d PCI_NUM_REGIONS=%d\n", iRegion, PCI_NUM_REGIONS),
832	VERR_INVALID_PARAMETER);
833	int iLastSet = ASMBitLastSetU32(cbRegion);
834	AssertMsgReturn( iLastSet != 0
835	&& RT_BIT_32(iLastSet - 1) == cbRegion,
836	("Invalid cbRegion=%#x iLastSet=%#x (not a power of 2 or 0)\n", cbRegion, iLastSet),
837	VERR_INVALID_PARAMETER);
838
839	/*
840	* Register the I/O region.
841	*/
842	PPCIIOREGION pRegion = &pPciDev->Int.s.aIORegions[iRegion];
843	pRegion->addr = INVALID_PCI_ADDRESS;
844	pRegion->size = cbRegion;
845	pRegion->type = enmType;
846	pRegion->map_func = pfnCallback;
847
848	/* Set type in the config space. */
849	uint32_t u32Address = ich9pciGetRegionReg(iRegion);
850	uint32_t u32Value = (enmType == PCI_ADDRESS_SPACE_MEM_PREFETCH ? (1 << 3) : 0)
851	\| (enmType == PCI_ADDRESS_SPACE_IO ? 1 : 0);
852	PCIDevSetDWord(pPciDev, u32Address, u32Value);
853
854	return VINF_SUCCESS;
855	}
856
857	static DECLCALLBACK(void) ich9pciSetConfigCallbacks(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PFNPCICONFIGREAD pfnRead, PPFNPCICONFIGREAD ppfnReadOld,
858	PFNPCICONFIGWRITE pfnWrite, PPFNPCICONFIGWRITE ppfnWriteOld)
859	{
860	if (ppfnReadOld)
861	*ppfnReadOld = pPciDev->Int.s.pfnConfigRead;
862	pPciDev->Int.s.pfnConfigRead = pfnRead;
863
864	if (ppfnWriteOld)
865	*ppfnWriteOld = pPciDev->Int.s.pfnConfigWrite;
866	pPciDev->Int.s.pfnConfigWrite = pfnWrite;
867	}
868
869	/**
870	* Saves a state of the PCI device.
871	*
872	* @returns VBox status code.
873	* @param pDevIns Device instance of the PCI Bus.
874	* @param pPciDev Pointer to PCI device.
875	* @param pSSM The handle to save the state to.
876	*/
877	static DECLCALLBACK(int) ich9pciGenericSaveExec(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PSSMHANDLE pSSM)
878	{
879	return SSMR3PutMem(pSSM, &pPciDev->config[0], sizeof(pPciDev->config));
880	}
881
882	static int ich9pciR3CommonSaveExec(PPCIBUS pBus, PSSMHANDLE pSSM)
883	{
884	/*
885	* Iterate thru all the devices.
886	*/
887	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
888	{
889	PPCIDEVICE pDev = pBus->apDevices[i];
890	if (pDev)
891	{
892	/* Device position */
893	SSMR3PutU32(pSSM, i);
894	/* PCI config registers */
895	SSMR3PutMem(pSSM, pDev->config, sizeof(pDev->config));
896
897	/* Device flags */
898	int rc = SSMR3PutU32(pSSM, pDev->Int.s.uFlags);
899	if (RT_FAILURE(rc))
900	return rc;
901
902	/* IRQ pin state */
903	rc = SSMR3PutS32(pSSM, pDev->Int.s.uIrqPinState);
904	if (RT_FAILURE(rc))
905	return rc;
906
907	/* MSI info */
908	rc = SSMR3PutU8(pSSM, pDev->Int.s.u8MsiCapOffset);
909	if (RT_FAILURE(rc))
910	return rc;
911	rc = SSMR3PutU8(pSSM, pDev->Int.s.u8MsiCapSize);
912	if (RT_FAILURE(rc))
913	return rc;
914
915	/* MSI-X info */
916	rc = SSMR3PutU8(pSSM, pDev->Int.s.u8MsixCapOffset);
917	if (RT_FAILURE(rc))
918	return rc;
919	rc = SSMR3PutU8(pSSM, pDev->Int.s.u8MsixCapSize);
920	if (RT_FAILURE(rc))
921	return rc;
922	/* Save MSI-X page state */
923	if (pDev->Int.s.u8MsixCapOffset != 0)
924	{
925	Assert(pDev->Int.s.pMsixPageR3 != NULL);
926	SSMR3PutMem(pSSM, pDev->Int.s.pMsixPageR3, 0x1000);
927	if (RT_FAILURE(rc))
928	return rc;
929	}
930	}
931	}
932	return SSMR3PutU32(pSSM, UINT32_MAX); /* terminator */
933	}
934
935	static DECLCALLBACK(int) ich9pciR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
936	{
937	PPCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
938
939	/*
940	* Bus state data.
941	*/
942	SSMR3PutU32(pSSM, pThis->uConfigReg);
943
944	/*
945	* Save IRQ states.
946	*/
947	for (int i = 0; i < PCI_APIC_IRQ_PINS; i++)
948	SSMR3PutU32(pSSM, pThis->uaPciApicIrqLevels[i]);
949
950	SSMR3PutU32(pSSM, ~0); /* separator */
951
952	return ich9pciR3CommonSaveExec(&pThis->aPciBus, pSSM);
953	}
954
955
956	static DECLCALLBACK(int) ich9pcibridgeR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
957	{
958	PPCIBUS pThis = PDMINS_2_DATA(pDevIns, PPCIBUS);
959	return ich9pciR3CommonSaveExec(pThis, pSSM);
960	}
961
962
963	static void ich9pcibridgeConfigWrite(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice, uint32_t u32Address, uint32_t u32Value, unsigned cb)
964	{
965	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
966
967	LogFlowFunc((": pDevIns=%p iBus=%d iDevice=%d u32Address=%u u32Value=%u cb=%d\n", pDevIns, iBus, iDevice, u32Address, u32Value, cb));
968
969	/* If the current bus is not the target bus search for the bus which contains the device. */
970	if (iBus != PCIDevGetByte(&pBus->aPciDev, VBOX_PCI_SECONDARY_BUS))
971	{
972	PPCIDEVICE pBridgeDevice = ich9pciFindBridge(pBus, iBus);
973	if (pBridgeDevice)
974	{
975	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigWrite);
976	pBridgeDevice->Int.s.pfnBridgeConfigWrite(pBridgeDevice->pDevIns, iBus, iDevice, u32Address, u32Value, cb);
977	}
978	}
979	else
980	{
981	/* This is the target bus, pass the write to the device. */
982	PPCIDEVICE pPciDev = pBus->apDevices[iDevice];
983	if (pPciDev)
984	{
985	Log(("%s: %s: addr=%02x val=%08x len=%d\n", __FUNCTION__, pPciDev->name, u32Address, u32Value, cb));
986	pPciDev->Int.s.pfnConfigWrite(pPciDev, u32Address, u32Value, cb);
987	}
988	}
989	}
990
991	static uint32_t ich9pcibridgeConfigRead(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice, uint32_t u32Address, unsigned cb)
992	{
993	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
994	uint32_t u32Value = 0xffffffff; /* Return value in case there is no device. */
995
996	LogFlowFunc((": pDevIns=%p iBus=%d iDevice=%d u32Address=%u cb=%d\n", pDevIns, iBus, iDevice, u32Address, cb));
997
998	/* If the current bus is not the target bus search for the bus which contains the device. */
999	if (iBus != PCIDevGetByte(&pBus->aPciDev, VBOX_PCI_SECONDARY_BUS))
1000	{
1001	PPCIDEVICE pBridgeDevice = ich9pciFindBridge(pBus, iBus);
1002	if (pBridgeDevice)
1003	{
1004	AssertPtr( pBridgeDevice->Int.s.pfnBridgeConfigRead);
1005	u32Value = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->pDevIns, iBus, iDevice, u32Address, cb);
1006	}
1007	}
1008	else
1009	{
1010	/* This is the target bus, pass the read to the device. */
1011	PPCIDEVICE pPciDev = pBus->apDevices[iDevice];
1012	if (pPciDev)
1013	{
1014	u32Value = pPciDev->Int.s.pfnConfigRead(pPciDev, u32Address, cb);
1015	Log(("%s: %s: u32Address=%02x u32Value=%08x cb=%d\n", __FUNCTION__, pPciDev->name, u32Address, u32Value, cb));
1016	}
1017	}
1018
1019	return u32Value;
1020	}
1021
1022
1023	/**
1024	* Common routine for restoring the config registers of a PCI device.
1025	*
1026	* @param pDev The PCI device.
1027	* @param pbSrcConfig The configuration register values to be loaded.
1028	* @param fIsBridge Whether this is a bridge device or not.
1029	*/
1030	static void pciR3CommonRestoreConfig(PPCIDEVICE pDev, uint8_t const *pbSrcConfig, bool fIsBridge)
1031	{
1032	/*
1033	* This table defines the fields for normal devices and bridge devices, and
1034	* the order in which they need to be restored.
1035	*/
1036	static const struct PciField
1037	{
1038	uint8_t off;
1039	uint8_t cb;
1040	uint8_t fWritable;
1041	uint8_t fBridge;
1042	const char *pszName;
1043	} s_aFields[] =
1044	{
1045	/* off,cb,fW,fB, pszName */
1046	{ VBOX_PCI_VENDOR_ID, 2, 0, 3, "VENDOR_ID" },
1047	{ VBOX_PCI_DEVICE_ID, 2, 0, 3, "DEVICE_ID" },
1048	{ VBOX_PCI_STATUS, 2, 1, 3, "STATUS" },
1049	{ VBOX_PCI_REVISION_ID, 1, 0, 3, "REVISION_ID" },
1050	{ VBOX_PCI_CLASS_PROG, 1, 0, 3, "CLASS_PROG" },
1051	{ VBOX_PCI_CLASS_SUB, 1, 0, 3, "CLASS_SUB" },
1052	{ VBOX_PCI_CLASS_BASE, 1, 0, 3, "CLASS_BASE" },
1053	{ VBOX_PCI_CACHE_LINE_SIZE, 1, 1, 3, "CACHE_LINE_SIZE" },
1054	{ VBOX_PCI_LATENCY_TIMER, 1, 1, 3, "LATENCY_TIMER" },
1055	{ VBOX_PCI_HEADER_TYPE, 1, 0, 3, "HEADER_TYPE" },
1056	{ VBOX_PCI_BIST, 1, 1, 3, "BIST" },
1057	{ VBOX_PCI_BASE_ADDRESS_0, 4, 1, 3, "BASE_ADDRESS_0" },
1058	{ VBOX_PCI_BASE_ADDRESS_1, 4, 1, 3, "BASE_ADDRESS_1" },
1059	{ VBOX_PCI_BASE_ADDRESS_2, 4, 1, 1, "BASE_ADDRESS_2" },
1060	{ VBOX_PCI_PRIMARY_BUS, 1, 1, 2, "PRIMARY_BUS" }, // fWritable = ??
1061	{ VBOX_PCI_SECONDARY_BUS, 1, 1, 2, "SECONDARY_BUS" }, // fWritable = ??
1062	{ VBOX_PCI_SUBORDINATE_BUS, 1, 1, 2, "SUBORDINATE_BUS" }, // fWritable = ??
1063	{ VBOX_PCI_SEC_LATENCY_TIMER, 1, 1, 2, "SEC_LATENCY_TIMER" }, // fWritable = ??
1064	{ VBOX_PCI_BASE_ADDRESS_3, 4, 1, 1, "BASE_ADDRESS_3" },
1065	{ VBOX_PCI_IO_BASE, 1, 1, 2, "IO_BASE" }, // fWritable = ??
1066	{ VBOX_PCI_IO_LIMIT, 1, 1, 2, "IO_LIMIT" }, // fWritable = ??
1067	{ VBOX_PCI_SEC_STATUS, 2, 1, 2, "SEC_STATUS" }, // fWritable = ??
1068	{ VBOX_PCI_BASE_ADDRESS_4, 4, 1, 1, "BASE_ADDRESS_4" },
1069	{ VBOX_PCI_MEMORY_BASE, 2, 1, 2, "MEMORY_BASE" }, // fWritable = ??
1070	{ VBOX_PCI_MEMORY_LIMIT, 2, 1, 2, "MEMORY_LIMIT" }, // fWritable = ??
1071	{ VBOX_PCI_BASE_ADDRESS_5, 4, 1, 1, "BASE_ADDRESS_5" },
1072	{ VBOX_PCI_PREF_MEMORY_BASE, 2, 1, 2, "PREF_MEMORY_BASE" }, // fWritable = ??
1073	{ VBOX_PCI_PREF_MEMORY_LIMIT, 2, 1, 2, "PREF_MEMORY_LIMIT" }, // fWritable = ??
1074	{ VBOX_PCI_CARDBUS_CIS, 4, 1, 1, "CARDBUS_CIS" }, // fWritable = ??
1075	{ VBOX_PCI_PREF_BASE_UPPER32, 4, 1, 2, "PREF_BASE_UPPER32" }, // fWritable = ??
1076	{ VBOX_PCI_SUBSYSTEM_VENDOR_ID, 2, 0, 1, "SUBSYSTEM_VENDOR_ID" },// fWritable = !?
1077	{ VBOX_PCI_PREF_LIMIT_UPPER32, 4, 1, 2, "PREF_LIMIT_UPPER32" },// fWritable = ??
1078	{ VBOX_PCI_SUBSYSTEM_ID, 2, 0, 1, "SUBSYSTEM_ID" }, // fWritable = !?
1079	{ VBOX_PCI_ROM_ADDRESS, 4, 1, 1, "ROM_ADDRESS" }, // fWritable = ?!
1080	{ VBOX_PCI_IO_BASE_UPPER16, 2, 1, 2, "IO_BASE_UPPER16" }, // fWritable = ?!
1081	{ VBOX_PCI_IO_LIMIT_UPPER16, 2, 1, 2, "IO_LIMIT_UPPER16" }, // fWritable = ?!
1082	{ VBOX_PCI_CAPABILITY_LIST, 4, 0, 3, "CAPABILITY_LIST" }, // fWritable = !? cb=!?
1083	{ VBOX_PCI_RESERVED_38, 4, 1, 1, "RESERVED_38" }, // ???
1084	{ VBOX_PCI_ROM_ADDRESS_BR, 4, 1, 2, "ROM_ADDRESS_BR" }, // fWritable = !? cb=!? fBridge=!?
1085	{ VBOX_PCI_INTERRUPT_LINE, 1, 1, 3, "INTERRUPT_LINE" }, // fBridge=??
1086	{ VBOX_PCI_INTERRUPT_PIN, 1, 0, 3, "INTERRUPT_PIN" }, // fBridge=??
1087	{ VBOX_PCI_MIN_GNT, 1, 0, 1, "MIN_GNT" },
1088	{ VBOX_PCI_BRIDGE_CONTROL, 2, 1, 2, "BRIDGE_CONTROL" }, // fWritable = !?
1089	{ VBOX_PCI_MAX_LAT, 1, 0, 1, "MAX_LAT" },
1090	/* The COMMAND register must come last as it requires the ADDRESS
1091	registers to be restored before we pretent to change it from 0 to
1092	whatever value the guest assigned it. */
1093	{ VBOX_PCI_COMMAND, 2, 1, 3, "COMMAND" },
1094	};
1095
1096	#ifdef RT_STRICT
1097	/* Check that we've got full register coverage. */
1098	uint32_t bmDevice[0x40 / 32];
1099	uint32_t bmBridge[0x40 / 32];
1100	RT_ZERO(bmDevice);
1101	RT_ZERO(bmBridge);
1102	for (uint32_t i = 0; i < RT_ELEMENTS(s_aFields); i++)
1103	{
1104	uint8_t off = s_aFields[i].off;
1105	uint8_t cb = s_aFields[i].cb;
1106	uint8_t f = s_aFields[i].fBridge;
1107	while (cb-- > 0)
1108	{
1109	if (f & 1) AssertMsg(!ASMBitTest(bmDevice, off), ("%#x\n", off));
1110	if (f & 2) AssertMsg(!ASMBitTest(bmBridge, off), ("%#x\n", off));
1111	if (f & 1) ASMBitSet(bmDevice, off);
1112	if (f & 2) ASMBitSet(bmBridge, off);
1113	off++;
1114	}
1115	}
1116	for (uint32_t off = 0; off < 0x40; off++)
1117	{
1118	AssertMsg(ASMBitTest(bmDevice, off), ("%#x\n", off));
1119	AssertMsg(ASMBitTest(bmBridge, off), ("%#x\n", off));
1120	}
1121	#endif
1122
1123	/*
1124	* Loop thru the fields covering the 64 bytes of standard registers.
1125	*/
1126	uint8_t const fBridge = fIsBridge ? 2 : 1;
1127	uint8_t *pbDstConfig = &pDev->config[0];
1128	for (uint32_t i = 0; i < RT_ELEMENTS(s_aFields); i++)
1129	if (s_aFields[i].fBridge & fBridge)
1130	{
1131	uint8_t const off = s_aFields[i].off;
1132	uint8_t const cb = s_aFields[i].cb;
1133	uint32_t u32Src;
1134	uint32_t u32Dst;
1135	switch (cb)
1136	{
1137	case 1:
1138	u32Src = pbSrcConfig[off];
1139	u32Dst = pbDstConfig[off];
1140	break;
1141	case 2:
1142	u32Src = (uint16_t const )&pbSrcConfig[off];
1143	u32Dst = (uint16_t const )&pbDstConfig[off];
1144	break;
1145	case 4:
1146	u32Src = (uint32_t const )&pbSrcConfig[off];
1147	u32Dst = (uint32_t const )&pbDstConfig[off];
1148	break;
1149	default:
1150	AssertFailed();
1151	continue;
1152	}
1153
1154	if ( u32Src != u32Dst
1155	\|\| off == VBOX_PCI_COMMAND)
1156	{
1157	if (u32Src != u32Dst)
1158	{
1159	if (!s_aFields[i].fWritable)
1160	LogRel(("PCI: %8s/%u: %2u-bit field %s: %x -> %x - !READ ONLY!\n",
1161	pDev->name, pDev->pDevIns->iInstance, cb*8, s_aFields[i].pszName, u32Dst, u32Src));
1162	else
1163	LogRel(("PCI: %8s/%u: %2u-bit field %s: %x -> %x\n",
1164	pDev->name, pDev->pDevIns->iInstance, cb*8, s_aFields[i].pszName, u32Dst, u32Src));
1165	}
1166	if (off == VBOX_PCI_COMMAND)
1167	PCIDevSetCommand(pDev, 0); /* For remapping, see ich9pciR3CommonLoadExec. */
1168	pDev->Int.s.pfnConfigWrite(pDev, off, u32Src, cb);
1169	}
1170	}
1171
1172	/*
1173	* The device dependent registers.
1174	*
1175	* We will not use ConfigWrite here as we have no clue about the size
1176	* of the registers, so the device is responsible for correctly
1177	* restoring functionality governed by these registers.
1178	*/
1179	for (uint32_t off = 0x40; off < sizeof(pDev->config); off++)
1180	if (pbDstConfig[off] != pbSrcConfig[off])
1181	{
1182	LogRel(("PCI: %8s/%u: register %02x: %02x -> %02x\n",
1183	pDev->name, pDev->pDevIns->iInstance, off, pbDstConfig[off], pbSrcConfig[off])); /** @todo make this Log() later. */
1184	pbDstConfig[off] = pbSrcConfig[off];
1185	}
1186	}
1187
1188	/**
1189	* Common worker for ich9pciR3LoadExec and ich9pcibridgeR3LoadExec.
1190	*
1191	* @returns VBox status code.
1192	* @param pBus The bus which data is being loaded.
1193	* @param pSSM The saved state handle.
1194	* @param uVersion The data version.
1195	* @param uPass The pass.
1196	*/
1197	static DECLCALLBACK(int) ich9pciR3CommonLoadExec(PPCIBUS pBus, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1198	{
1199	uint32_t u32;
1200	uint32_t i;
1201	int rc;
1202
1203	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
1204
1205	/*
1206	* Iterate thru all the devices and write 0 to the COMMAND register so
1207	* that all the memory is unmapped before we start restoring the saved
1208	* mapping locations.
1209	*
1210	* The register value is restored afterwards so we can do proper
1211	* LogRels in pciR3CommonRestoreConfig.
1212	*/
1213	for (i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
1214	{
1215	PPCIDEVICE pDev = pBus->apDevices[i];
1216	if (pDev)
1217	{
1218	uint16_t u16 = PCIDevGetCommand(pDev);
1219	pDev->Int.s.pfnConfigWrite(pDev, VBOX_PCI_COMMAND, 0, 2);
1220	PCIDevSetCommand(pDev, u16);
1221	Assert(PCIDevGetCommand(pDev) == u16);
1222	}
1223	}
1224
1225	void* pvMsixPage = RTMemTmpAllocZ(0x1000);
1226	/*
1227	* Iterate all the devices.
1228	*/
1229	for (i = 0;; i++)
1230	{
1231	PPCIDEVICE pDev;
1232	PCIDEVICE DevTmp;
1233
1234	/* index / terminator */
1235	rc = SSMR3GetU32(pSSM, &u32);
1236	if (RT_FAILURE(rc))
1237	return rc;
1238	if (u32 == (uint32_t)~0)
1239	break;
1240	if ( u32 >= RT_ELEMENTS(pBus->apDevices)
1241	\|\| u32 < i)
1242	{
1243	AssertMsgFailed(("u32=%#x i=%#x\n", u32, i));
1244	goto out;
1245	}
1246
1247	/* skip forward to the device checking that no new devices are present. */
1248	for (; i < u32; i++)
1249	{
1250	pDev = pBus->apDevices[i];
1251	if (pDev)
1252	{
1253	LogRel(("New device in slot %#x, %s (vendor=%#06x device=%#06x)\n", i, pDev->name,
1254	PCIDevGetVendorId(pDev), PCIDevGetDeviceId(pDev)));
1255	if (SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT)
1256	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("New device in slot %#x, %s (vendor=%#06x device=%#06x)"),
1257	i, pDev->name, PCIDevGetVendorId(pDev), PCIDevGetDeviceId(pDev));
1258	}
1259	}
1260
1261	/* get the data */
1262	DevTmp.Int.s.uFlags = 0;
1263	DevTmp.Int.s.u8MsiCapOffset = 0;
1264	DevTmp.Int.s.u8MsiCapSize = 0;
1265	DevTmp.Int.s.u8MsixCapOffset = 0;
1266	DevTmp.Int.s.u8MsixCapSize = 0;
1267	DevTmp.Int.s.uIrqPinState = ~0; /* Invalid value in case we have an older saved state to force a state change in pciSetIrq. */
1268	SSMR3GetMem(pSSM, DevTmp.config, sizeof(DevTmp.config));
1269
1270	rc = SSMR3GetU32(pSSM, &DevTmp.Int.s.uFlags);
1271	if (RT_FAILURE(rc))
1272	goto out;
1273
1274	rc = SSMR3GetS32(pSSM, &DevTmp.Int.s.uIrqPinState);
1275	if (RT_FAILURE(rc))
1276	goto out;
1277
1278	rc = SSMR3GetU8(pSSM, &DevTmp.Int.s.u8MsiCapOffset);
1279	if (RT_FAILURE(rc))
1280	goto out;
1281
1282	rc = SSMR3GetU8(pSSM, &DevTmp.Int.s.u8MsiCapSize);
1283	if (RT_FAILURE(rc))
1284	goto out;
1285
1286	rc = SSMR3GetU8(pSSM, &DevTmp.Int.s.u8MsixCapOffset);
1287	if (RT_FAILURE(rc))
1288	goto out;
1289
1290	rc = SSMR3GetU8(pSSM, &DevTmp.Int.s.u8MsixCapSize);
1291	if (RT_FAILURE(rc))
1292	goto out;
1293
1294	/* Load MSI-X page state */
1295	if (DevTmp.Int.s.u8MsixCapOffset != 0)
1296	{
1297	Assert(pvMsixPage != NULL);
1298	SSMR3GetMem(pSSM, pvMsixPage, 0x1000);
1299	if (RT_FAILURE(rc))
1300	goto out;
1301	}
1302
1303	/* check that it's still around. */
1304	pDev = pBus->apDevices[i];
1305	if (!pDev)
1306	{
1307	LogRel(("Device in slot %#x has been removed! vendor=%#06x device=%#06x\n", i,
1308	PCIDevGetVendorId(&DevTmp), PCIDevGetDeviceId(&DevTmp)));
1309	if (SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT)
1310	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Device in slot %#x has been removed! vendor=%#06x device=%#06x"),
1311	i, PCIDevGetVendorId(&DevTmp), PCIDevGetDeviceId(&DevTmp));
1312	continue;
1313	}
1314
1315	/* match the vendor id assuming that this will never be changed. */
1316	if ( PCIDevGetVendorId(&DevTmp) != PCIDevGetVendorId(pDev))
1317	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Device in slot %#x (%s) vendor id mismatch! saved=%.4Rhxs current=%.4Rhxs"),
1318	i, pDev->name, PCIDevGetVendorId(&DevTmp), PCIDevGetVendorId(pDev));
1319
1320	/* commit the loaded device config. */
1321	pciR3CommonRestoreConfig(pDev, &DevTmp.config[0], false ); /** @todo fix bridge fun! */
1322
1323	pDev->Int.s.uIrqPinState = DevTmp.Int.s.uIrqPinState;
1324	pDev->Int.s.u8MsiCapOffset = DevTmp.Int.s.u8MsiCapOffset;
1325	pDev->Int.s.u8MsiCapSize = DevTmp.Int.s.u8MsiCapSize;
1326	pDev->Int.s.u8MsixCapOffset = DevTmp.Int.s.u8MsixCapOffset;
1327	pDev->Int.s.u8MsixCapSize = DevTmp.Int.s.u8MsixCapSize;
1328	if (DevTmp.Int.s.u8MsixCapSize != 0)
1329	{
1330	Assert(pDev->Int.s.pMsixPageR3 != NULL);
1331	memcpy(pDev->Int.s.pMsixPageR3, pvMsixPage, 0x1000);
1332	}
1333	}
1334
1335	out:
1336	if (pvMsixPage)
1337	RTMemTmpFree(pvMsixPage);
1338
1339	return rc;
1340	}
1341
1342	/**
1343	* Loads a saved PCI device state.
1344	*
1345	* @returns VBox status code.
1346	* @param pDevIns Device instance of the PCI Bus.
1347	* @param pPciDev Pointer to PCI device.
1348	* @param pSSM The handle to the saved state.
1349	*/
1350	static DECLCALLBACK(int) ich9pciGenericLoadExec(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PSSMHANDLE pSSM)
1351	{
1352	return SSMR3GetMem(pSSM, &pPciDev->config[0], sizeof(pPciDev->config));
1353	}
1354
1355	static DECLCALLBACK(int) ich9pciR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1356	{
1357	PPCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
1358	PPCIBUS pBus = &pThis->aPciBus;
1359	uint32_t u32;
1360	int rc;
1361
1362	/* We ignore this version as there's no saved state with it anyway */
1363	if (uVersion == VBOX_ICH9PCI_SAVED_STATE_VERSION_NOMSI)
1364	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1365	if (uVersion > VBOX_ICH9PCI_SAVED_STATE_VERSION_MSI)
1366	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1367
1368	/*
1369	* Bus state data.
1370	*/
1371	SSMR3GetU32(pSSM, &pThis->uConfigReg);
1372
1373	/*
1374	* Load IRQ states.
1375	*/
1376	for (int i = 0; i < PCI_APIC_IRQ_PINS; i++)
1377	SSMR3GetU32(pSSM, (uint32_t*)&pThis->uaPciApicIrqLevels[i]);
1378
1379	/* separator */
1380	rc = SSMR3GetU32(pSSM, &u32);
1381	if (RT_FAILURE(rc))
1382	return rc;
1383	if (u32 != (uint32_t)~0)
1384	AssertMsgFailedReturn(("u32=%#x\n", u32), rc);
1385
1386	return ich9pciR3CommonLoadExec(pBus, pSSM, uVersion, uPass);
1387	}
1388
1389	static DECLCALLBACK(int) ich9pcibridgeR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1390	{
1391	PPCIBUS pThis = PDMINS_2_DATA(pDevIns, PPCIBUS);
1392	if (uVersion > VBOX_ICH9PCI_SAVED_STATE_VERSION_MSI)
1393	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1394	return ich9pciR3CommonLoadExec(pThis, pSSM, uVersion, uPass);
1395	}
1396
1397	static uint32_t ich9pciConfigRead(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t len)
1398	{
1399	uint32_t u32Val = 0xffffffff;
1400	PciAddress aPciAddr;
1401
1402	aPciAddr.iBus = uBus;
1403	aPciAddr.iDeviceFunc = uDevFn;
1404	aPciAddr.iRegister = addr;
1405
1406	int rc = ich9pciDataReadAddr(pGlobals, &aPciAddr, len, &u32Val);
1407	AssertRC(rc);
1408	switch (len)
1409	{
1410	case 1:
1411	u32Val &= 0xff;
1412	break;
1413	case 2:
1414	u32Val &= 0xffff;
1415	break;
1416	}
1417	return u32Val;
1418	}
1419
1420	static void ich9pciConfigWrite(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t val, uint32_t len)
1421	{
1422	PciAddress aPciAddr;
1423
1424	aPciAddr.iBus = uBus;
1425	aPciAddr.iDeviceFunc = uDevFn;
1426	aPciAddr.iRegister = addr;
1427
1428	ich9pciDataWriteAddr(pGlobals, &aPciAddr, val, len);
1429	}
1430
1431	static void ich9pciSetRegionAddress(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, int iRegion, uint32_t addr)
1432	{
1433	uint32_t uReg = ich9pciGetRegionReg(iRegion);
1434
1435	/* Read memory type first. */
1436	uint8_t uResourceType = ich9pciConfigRead(pGlobals, uBus, uDevFn, uReg, 1);
1437	/* Read command register. */
1438	uint16_t uCmd = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_COMMAND, 2);
1439
1440	if ( iRegion == PCI_ROM_SLOT )
1441	uCmd \|= PCI_COMMAND_MEMACCESS;
1442	else if ((uResourceType & PCI_ADDRESS_SPACE_IO) == PCI_ADDRESS_SPACE_IO)
1443	uCmd \|= PCI_COMMAND_IOACCESS; /* Enable I/O space access. */
1444	else /* The region is MMIO. */
1445	uCmd \|= PCI_COMMAND_MEMACCESS; /* Enable MMIO access. */
1446
1447	/* Write address of the device. */
1448	ich9pciConfigWrite(pGlobals, uBus, uDevFn, uReg, addr, 4);
1449
1450	/* enable memory mappings */
1451	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_COMMAND, uCmd, 2);
1452	}
1453
1454
1455	static void ich9pciBiosInitBridge(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint8_t cBridgeDepth, uint8_t *paBridgePositions)
1456	{
1457	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_SECONDARY_BUS, pGlobals->uBus, 1);
1458	/* Temporary until we know how many other bridges are behind this one. */
1459	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_SUBORDINATE_BUS, 0xff, 1);
1460
1461	/* Add position of this bridge into the array. */
1462	paBridgePositions[cBridgeDepth+1] = (uDevFn >> 3);
1463
1464	/*
1465	* The I/O range for the bridge must be aligned to a 4KB boundary.
1466	* This does not change anything really as the access to the device is not going
1467	* through the bridge but we want to be compliant to the spec.
1468	*/
1469	if ((pGlobals->uPciBiosIo % 4096) != 0)
1470	{
1471	pGlobals->uPciBiosIo = RT_ALIGN_32(pGlobals->uPciBiosIo, 4*1024);
1472	Log(("%s: Aligned I/O start address. New address %#x\n", __FUNCTION__, pGlobals->uPciBiosIo));
1473	}
1474	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_IO_BASE, (pGlobals->uPciBiosIo >> 8) & 0xf0, 1);
1475
1476	/* The MMIO range for the bridge must be aligned to a 1MB boundary. */
1477	if ((pGlobals->uPciBiosMmio % (1024 * 1024)) != 0)
1478	{
1479	pGlobals->uPciBiosMmio = RT_ALIGN_32(pGlobals->uPciBiosMmio, 1024*1024);
1480	Log(("%s: Aligned MMIO start address. New address %#x\n", __FUNCTION__, pGlobals->uPciBiosMmio));
1481	}
1482	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_MEMORY_BASE, (pGlobals->uPciBiosMmio >> 16) & UINT32_C(0xffff0), 2);
1483
1484	/* Save values to compare later to. */
1485	uint32_t u32IoAddressBase = pGlobals->uPciBiosIo;
1486	uint32_t u32MMIOAddressBase = pGlobals->uPciBiosMmio;
1487
1488	/* Init devices behind the bridge and possibly other bridges as well. */
1489	for (int iDev = 0; iDev <= 255; iDev++)
1490	ich9pciBiosInitDevice(pGlobals, uBus + 1, iDev, cBridgeDepth + 1, paBridgePositions);
1491
1492	/* The number of bridges behind the this one is now available. */
1493	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_SUBORDINATE_BUS, pGlobals->uBus, 1);
1494
1495	/*
1496	* Set I/O limit register. If there is no device with I/O space behind the bridge
1497	* we set a lower value than in the base register.
1498	* The result with a real bridge is that no I/O transactions are passed to the secondary
1499	* interface. Again this doesn't really matter here but we want to be compliant to the spec.
1500	*/
1501	if ((u32IoAddressBase != pGlobals->uPciBiosIo) && ((pGlobals->uPciBiosIo % 4096) != 0))
1502	{
1503	/* The upper boundary must be one byte less than a 4KB boundary. */
1504	pGlobals->uPciBiosIo = RT_ALIGN_32(pGlobals->uPciBiosIo, 4*1024);
1505	}
1506
1507	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_IO_LIMIT, ((pGlobals->uPciBiosIo >> 8) & 0xf0) - 1, 1);
1508
1509	/* Same with the MMIO limit register but with 1MB boundary here. */
1510	if ((u32MMIOAddressBase != pGlobals->uPciBiosMmio) && ((pGlobals->uPciBiosMmio % (1024 * 1024)) != 0))
1511	{
1512	/* The upper boundary must be one byte less than a 1MB boundary. */
1513	pGlobals->uPciBiosMmio = RT_ALIGN_32(pGlobals->uPciBiosMmio, 1024*1024);
1514	}
1515	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_MEMORY_LIMIT, ((pGlobals->uPciBiosMmio >> 16) & UINT32_C(0xfff0)) - 1, 2);
1516
1517	/*
1518	* Set the prefetch base and limit registers. We currently have no device with a prefetchable region
1519	* which may be behind a bridge. Thatswhy it is unconditionally disabled here atm by writing a higher value into
1520	* the base register than in the limit register.
1521	*/
1522	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_MEMORY_BASE, 0xfff0, 2);
1523	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_MEMORY_LIMIT, 0x0, 2);
1524	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_BASE_UPPER32, 0x00, 4);
1525	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_LIMIT_UPPER32, 0x00, 4);
1526	}
1527
1528	static void ich9pciBiosInitDevice(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint8_t cBridgeDepth, uint8_t *paBridgePositions)
1529	{
1530	uint32_t *paddr;
1531	uint16_t uDevClass, uVendor, uDevice;
1532	uint8_t uCmd;
1533
1534	uDevClass = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_CLASS_DEVICE, 2);
1535	uVendor = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_VENDOR_ID, 2);
1536	uDevice = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_DEVICE_ID, 2);
1537
1538	/* If device is present */
1539	if (uVendor == 0xffff)
1540	return;
1541
1542	switch (uDevClass)
1543	{
1544	case 0x0101:
1545	/* IDE controller */
1546	ich9pciConfigWrite(pGlobals, uBus, uDevFn, 0x40, 0x8000, 2); /* enable IDE0 */
1547	ich9pciConfigWrite(pGlobals, uBus, uDevFn, 0x42, 0x8000, 2); /* enable IDE1 */
1548	goto default_map;
1549	break;
1550	case 0x0300:
1551	/* VGA controller */
1552	if (uVendor != 0x80ee)
1553	goto default_map;
1554	/* VGA: map frame buffer to default Bochs VBE address */
1555	ich9pciSetRegionAddress(pGlobals, uBus, uDevFn, 0, 0xE0000000);
1556	/*
1557	* Legacy VGA I/O ports are implicitly decoded by a VGA class device. But
1558	* only the framebuffer (i.e., a memory region) is explicitly registered via
1559	* ich9pciSetRegionAddress, so I/O decoding must be enabled manually.
1560	*/
1561	uCmd = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_COMMAND, 1);
1562	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_COMMAND,
1563	/* Enable I/O space access. */
1564	uCmd \| PCI_COMMAND_IOACCESS,
1565	1);
1566	break;
1567	case 0x0800:
1568	/* PIC */
1569	if (uVendor == 0x1014)
1570	{
1571	/* IBM */
1572	if (uDevice == 0x0046 \|\| uDevice == 0xFFFF)
1573	/* MPIC & MPIC2 */
1574	ich9pciSetRegionAddress(pGlobals, uBus, uDevFn, 0, 0x80800000 + 0x00040000);
1575	}
1576	break;
1577	case 0xff00:
1578	if ((uVendor == 0x0106b)
1579	&& (uDevice == 0x0017 \|\| uDevice == 0x0022))
1580	{
1581	/* macio bridge */
1582	ich9pciSetRegionAddress(pGlobals, uBus, uDevFn, 0, 0x80800000);
1583	}
1584	break;
1585	case 0x0604:
1586	/* PCI-to-PCI bridge. */
1587	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_PRIMARY_BUS, uBus, 1);
1588
1589	AssertMsg(pGlobals->uBus < 255, ("Too many bridges on the bus\n"));
1590	pGlobals->uBus++;
1591	ich9pciBiosInitBridge(pGlobals, uBus, uDevFn, cBridgeDepth, paBridgePositions);
1592	break;
1593	default:
1594	default_map:
1595	{
1596	/* default memory mappings */
1597	/*
1598	* We ignore ROM region here.
1599	*/
1600	for (int iRegion = 0; iRegion < (PCI_NUM_REGIONS-1); iRegion++)
1601	{
1602	uint32_t u32Address = ich9pciGetRegionReg(iRegion);
1603
1604	/* Calculate size. */
1605	uint8_t u8ResourceType = ich9pciConfigRead(pGlobals, uBus, uDevFn, u32Address, 1);
1606	ich9pciConfigWrite(pGlobals, uBus, uDevFn, u32Address, UINT32_C(0xffffffff), 4);
1607	uint32_t u32Size = ich9pciConfigRead(pGlobals, uBus, uDevFn, u32Address, 4);
1608	/* Clear resource information depending on resource type. */
1609	if ((u8ResourceType & PCI_COMMAND_IOACCESS) == PCI_COMMAND_IOACCESS) /* I/O */
1610	u32Size &= ~(0x01);
1611	else /* MMIO */
1612	u32Size &= ~(0x0f);
1613
1614	bool fIsPio = ((u8ResourceType & PCI_COMMAND_IOACCESS) == PCI_COMMAND_IOACCESS);
1615	/*
1616	* Invert all bits and add 1 to get size of the region.
1617	* (From PCI implementation note)
1618	*/
1619	if (fIsPio && (u32Size & UINT32_C(0xffff0000)) == 0)
1620	u32Size = (~(u32Size \| UINT32_C(0xffff0000))) + 1;
1621	else
1622	u32Size = (~u32Size) + 1;
1623
1624	Log(("%s: Size of region %u for device %d on bus %d is %u\n", __FUNCTION__, iRegion, uDevFn, uBus, u32Size));
1625
1626	if (u32Size)
1627	{
1628	paddr = fIsPio ? &pGlobals->uPciBiosIo : &pGlobals->uPciBiosMmio;
1629	paddr = (paddr + u32Size - 1) & ~(u32Size - 1);
1630	Log(("%s: Start address of %s region %u is %#x\n", __FUNCTION__, (fIsPio ? "I/O" : "MMIO"), iRegion, *paddr));
1631	ich9pciSetRegionAddress(pGlobals, uBus, uDevFn, iRegion, *paddr);
1632	*paddr += u32Size;
1633	Log(("%s: New address is %#x\n", __FUNCTION__, *paddr));
1634	}
1635	}
1636	break;
1637	}
1638	}
1639
1640	/* map the interrupt */
1641	uint32_t uPin = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_INTERRUPT_PIN, 1);
1642	if (uPin != 0)
1643	{
1644	uint8_t uBridgeDevFn = uDevFn;
1645	uPin--;
1646
1647	/* We need to go up to the host bus to see which irq this device will assert there. */
1648	while (cBridgeDepth != 0)
1649	{
1650	/* Get the pin the device would assert on the bridge. */
1651	uPin = ((uBridgeDevFn >> 3) + uPin) & 3;
1652	uBridgeDevFn = paBridgePositions[cBridgeDepth];
1653	cBridgeDepth--;
1654	}
1655	}
1656	}
1657
1658	static const uint8_t auPciIrqs[4] = { 11, 9, 11, 9 };
1659
1660	static DECLCALLBACK(int) ich9pciFakePCIBIOS(PPDMDEVINS pDevIns)
1661	{
1662	unsigned i;
1663	uint8_t elcr[2] = {0, 0};
1664	PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
1665	PVM pVM = PDMDevHlpGetVM(pDevIns);
1666	Assert(pVM);
1667
1668	/*
1669	* Set the start addresses.
1670	*/
1671	pGlobals->uPciBiosIo = 0xd000;
1672	pGlobals->uPciBiosMmio = UINT32_C(0xf0000000);
1673	pGlobals->uBus = 0;
1674
1675	/*
1676	* Activate IRQ mappings.
1677	*/
1678	for (i = 0; i < 4; i++)
1679	{
1680	uint8_t irq = auPciIrqs[i];
1681	/* Set to trigger level. */
1682	elcr[irq >> 3] \|= (1 << (irq & 7));
1683	}
1684
1685	/* Tell to the PIC. */
1686	VBOXSTRICTRC rcStrict = IOMIOPortWrite(pVM, 0x4d0, elcr[0], sizeof(uint8_t));
1687	if (rcStrict == VINF_SUCCESS)
1688	rcStrict = IOMIOPortWrite(pVM, 0x4d1, elcr[1], sizeof(uint8_t));
1689	if (rcStrict != VINF_SUCCESS)
1690	{
1691	AssertMsgFailed(("Writing to PIC failed! rcStrict=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
1692	return RT_SUCCESS(rcStrict) ? VERR_INTERNAL_ERROR : VBOXSTRICTRC_VAL(rcStrict);
1693	}
1694
1695	/*
1696	* Init the devices.
1697	*/
1698	for (i = 0; i < 256; i++)
1699	{
1700	uint8_t aBridgePositions[256];
1701
1702	memset(aBridgePositions, 0, sizeof(aBridgePositions));
1703	Log2(("PCI: Initializing device %d (%#x)\n",
1704	i, 0x80000000 \| (i << 8)));
1705	ich9pciBiosInitDevice(pGlobals, 0, i, 0, aBridgePositions);
1706	}
1707
1708	return VINF_SUCCESS;
1709	}
1710
1711	static DECLCALLBACK(uint32_t) ich9pciConfigReadDev(PCIDevice *aDev, uint32_t u32Address, unsigned len)
1712	{
1713	if ((u32Address + len) > 256 && (u32Address + len) < 4096)
1714	{
1715	AssertMsgReturn(false, ("Read from extended registers falled back to generic code\n"), 0);
1716	}
1717
1718	if ( PCIIsMsiCapable(aDev)
1719	&& (u32Address >= aDev->Int.s.u8MsiCapOffset)
1720	&& (u32Address < aDev->Int.s.u8MsiCapOffset + aDev->Int.s.u8MsiCapSize)
1721	)
1722	{
1723	return MsiPciConfigRead(aDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pDevIns), aDev, u32Address, len);
1724	}
1725
1726	if ( PCIIsMsixCapable(aDev)
1727	&& (u32Address >= aDev->Int.s.u8MsixCapOffset)
1728	&& (u32Address < aDev->Int.s.u8MsixCapOffset + aDev->Int.s.u8MsixCapSize)
1729	)
1730	{
1731	return MsixPciConfigRead(aDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pDevIns), aDev, u32Address, len);
1732	}
1733
1734	AssertMsgReturn(u32Address + len <= 256, ("Read after end of PCI config space\n"),
1735	0);
1736	switch (len)
1737	{
1738	case 1:
1739	return PCIDevGetByte(aDev, u32Address);
1740	case 2:
1741	return PCIDevGetWord(aDev, u32Address);
1742	case 4:
1743	return PCIDevGetDWord(aDev, u32Address);
1744	default:
1745	Assert(false);
1746	return 0;
1747	}
1748	}
1749
1750
1751	/**
1752	* See paragraph 7.5 of PCI Express specification (p. 349) for definition of
1753	* registers and their writability policy.
1754	*/
1755	static DECLCALLBACK(void) ich9pciConfigWriteDev(PCIDevice *aDev, uint32_t u32Address,
1756	uint32_t val, unsigned len)
1757	{
1758	Assert(len <= 4);
1759
1760	if ((u32Address + len) > 256 && (u32Address + len) < 4096)
1761	{
1762	AssertMsgReturnVoid(false, ("Write to extended registers falled back to generic code\n"));
1763	}
1764
1765	AssertMsgReturnVoid(u32Address + len <= 256, ("Write after end of PCI config space\n"));
1766
1767	if ( PCIIsMsiCapable(aDev)
1768	&& (u32Address >= aDev->Int.s.u8MsiCapOffset)
1769	&& (u32Address < aDev->Int.s.u8MsiCapOffset + aDev->Int.s.u8MsiCapSize)
1770	)
1771	{
1772	MsiPciConfigWrite(aDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pDevIns),
1773	aDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pPciHlp),
1774	aDev, u32Address, val, len);
1775	return;
1776	}
1777
1778	if ( PCIIsMsixCapable(aDev)
1779	&& (u32Address >= aDev->Int.s.u8MsixCapOffset)
1780	&& (u32Address < aDev->Int.s.u8MsixCapOffset + aDev->Int.s.u8MsixCapSize)
1781	)
1782	{
1783	MsixPciConfigWrite(aDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pDevIns),
1784	aDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pPciHlp),
1785	aDev, u32Address, val, len);
1786	return;
1787	}
1788
1789
1790	/* Fast case - update one of BARs or ROM address, 'while' only for 'break' */
1791	while ( len == 4
1792	&& ( ( u32Address >= VBOX_PCI_BASE_ADDRESS_0
1793	&& u32Address < VBOX_PCI_BASE_ADDRESS_0 + 6 * 4)
1794	\|\| ( u32Address >= VBOX_PCI_ROM_ADDRESS
1795	&& u32Address < VBOX_PCI_ROM_ADDRESS+4)
1796	)
1797	)
1798	{
1799	PCIIORegion *pRegion;
1800	int reg, regionSize;
1801
1802	reg = (u32Address >= VBOX_PCI_ROM_ADDRESS) ? PCI_ROM_SLOT : (u32Address - VBOX_PCI_BASE_ADDRESS_0) >> 2;
1803	pRegion = &aDev->Int.s.aIORegions[reg];
1804	regionSize = pRegion->size;
1805	if (regionSize == 0)
1806	break;
1807	/* compute the stored value */
1808	if (reg == PCI_ROM_SLOT) {
1809	/* keep ROM enable bit */
1810	val &= (~(regionSize - 1)) \| 1;
1811	} else {
1812	val &= ~(regionSize - 1);
1813	val \|= pRegion->type;
1814	}
1815	PCIDevSetDWord(aDev, u32Address, val);
1816	ich9pciUpdateMappings(aDev);
1817	return;
1818	}
1819
1820	uint32_t addr = u32Address;
1821	bool fUpdateMappings = false;
1822	for (uint32_t i = 0; i < len; i++)
1823	{
1824	bool fWritable = false;
1825	switch (PCIDevGetHeaderType(aDev))
1826	{
1827	case 0x00: /* normal device */
1828	case 0x80: /* multi-function device */
1829	switch (addr)
1830	{
1831	/* Read-only registers */
1832	case VBOX_PCI_VENDOR_ID: case VBOX_PCI_VENDOR_ID+1:
1833	case VBOX_PCI_DEVICE_ID: case VBOX_PCI_DEVICE_ID+1:
1834	case VBOX_PCI_REVISION_ID:
1835	case VBOX_PCI_CLASS_PROG:
1836	case VBOX_PCI_CLASS_SUB:
1837	case VBOX_PCI_CLASS_BASE:
1838	case VBOX_PCI_HEADER_TYPE:
1839	case VBOX_PCI_BASE_ADDRESS_0: case VBOX_PCI_BASE_ADDRESS_0+1: case VBOX_PCI_BASE_ADDRESS_0+2: case VBOX_PCI_BASE_ADDRESS_0+3:
1840	case VBOX_PCI_BASE_ADDRESS_1: case VBOX_PCI_BASE_ADDRESS_1+1: case VBOX_PCI_BASE_ADDRESS_1+2: case VBOX_PCI_BASE_ADDRESS_1+3:
1841	case VBOX_PCI_BASE_ADDRESS_2: case VBOX_PCI_BASE_ADDRESS_2+1: case VBOX_PCI_BASE_ADDRESS_2+2: case VBOX_PCI_BASE_ADDRESS_2+3:
1842	case VBOX_PCI_BASE_ADDRESS_3: case VBOX_PCI_BASE_ADDRESS_3+1: case VBOX_PCI_BASE_ADDRESS_3+2: case VBOX_PCI_BASE_ADDRESS_3+3:
1843	case VBOX_PCI_BASE_ADDRESS_4: case VBOX_PCI_BASE_ADDRESS_4+1: case VBOX_PCI_BASE_ADDRESS_4+2: case VBOX_PCI_BASE_ADDRESS_4+3:
1844	case VBOX_PCI_BASE_ADDRESS_5: case VBOX_PCI_BASE_ADDRESS_5+1: case VBOX_PCI_BASE_ADDRESS_5+2: case VBOX_PCI_BASE_ADDRESS_5+3:
1845	case VBOX_PCI_SUBSYSTEM_VENDOR_ID: case VBOX_PCI_SUBSYSTEM_VENDOR_ID+1:
1846	case VBOX_PCI_SUBSYSTEM_ID: case VBOX_PCI_SUBSYSTEM_ID+1:
1847	case VBOX_PCI_ROM_ADDRESS: case VBOX_PCI_ROM_ADDRESS+1: case VBOX_PCI_ROM_ADDRESS+2: case VBOX_PCI_ROM_ADDRESS+3:
1848	case VBOX_PCI_CAPABILITY_LIST:
1849	case VBOX_PCI_INTERRUPT_PIN:
1850	fWritable = false;
1851	break;
1852	/* Others can be written */
1853	default:
1854	fWritable = true;
1855	break;
1856	}
1857	break;
1858	default:
1859	case 0x01: /* PCI-PCI bridge */
1860	switch (addr)
1861	{
1862	/* Read-only registers */
1863	case VBOX_PCI_VENDOR_ID: case VBOX_PCI_VENDOR_ID+1:
1864	case VBOX_PCI_DEVICE_ID: case VBOX_PCI_DEVICE_ID+1:
1865	case VBOX_PCI_REVISION_ID:
1866	case VBOX_PCI_CLASS_PROG:
1867	case VBOX_PCI_CLASS_SUB:
1868	case VBOX_PCI_CLASS_BASE:
1869	case VBOX_PCI_HEADER_TYPE:
1870	case VBOX_PCI_ROM_ADDRESS_BR: case VBOX_PCI_ROM_ADDRESS_BR+1: case VBOX_PCI_ROM_ADDRESS_BR+2: case VBOX_PCI_ROM_ADDRESS_BR+3:
1871	case VBOX_PCI_INTERRUPT_PIN:
1872	fWritable = false;
1873	break;
1874	default:
1875	fWritable = true;
1876	break;
1877	}
1878	break;
1879	}
1880
1881	uint8_t u8Val = (uint8_t)val;
1882
1883	switch (addr)
1884	{
1885	case VBOX_PCI_COMMAND: /* Command register, bits 0-7. */
1886	fUpdateMappings = true;
1887	PCIDevSetByte(aDev, addr, u8Val);
1888	break;
1889	case VBOX_PCI_COMMAND+1: /* Command register, bits 8-15. */
1890	/* don't change reserved bits (11-15) */
1891	u8Val &= UINT32_C(~0xf8);
1892	fUpdateMappings = true;
1893	PCIDevSetByte(aDev, addr, u8Val);
1894	break;
1895	case VBOX_PCI_STATUS: /* Status register, bits 0-7. */
1896	/* don't change read-only bits => actually all lower bits are read-only */
1897	u8Val &= UINT32_C(~0xff);
1898	/* status register, low part: clear bits by writing a '1' to the corresponding bit */
1899	aDev->config[addr] &= ~u8Val;
1900	break;
1901	case VBOX_PCI_STATUS+1: /* Status register, bits 8-15. */
1902	/* don't change read-only bits */
1903	u8Val &= UINT32_C(~0x06);
1904	/* status register, high part: clear bits by writing a '1' to the corresponding bit */
1905	aDev->config[addr] &= ~u8Val;
1906	break;
1907	default:
1908	if (fWritable)
1909	PCIDevSetByte(aDev, addr, u8Val);
1910	}
1911	addr++;
1912	val >>= 8;
1913	}
1914
1915	if (fUpdateMappings)
1916	/* if the command register is modified, we must modify the mappings */
1917	ich9pciUpdateMappings(aDev);
1918	}
1919
1920	/* Slot/functions assignment per table at p. 12 of ICH9 family spec update */
1921	static const struct {
1922	const char* pszName;
1923	int32_t iSlot;
1924	int32_t iFunction;
1925	} PciSlotAssignments[] = {
1926	/* Due to somewhat inflexible PCI bus configuration, ConsoleImpl hardcodes 0:5:0 as HDA address, so we shalln't put elsewhere */
1927	#if 0
1928	{
1929	"lan", 25, 0 /* LAN controller */
1930	},
1931	{
1932	"hda", 27, 0 /* High Definition Audio */
1933	},
1934	#endif
1935	{
1936	"i82801", 30, 0 /* Host Controller */
1937	},
1938	/**
1939	* Please note, that for devices being functions, like we do here, device 0
1940	* must be multifunction, i.e. have header type 0x80. Our LPC device is.
1941	* Alternative approach is to assign separate slot to each device.
1942	*/
1943	{
1944	"lpc", 31, 0 /* Low Pin Count bus */
1945	},
1946	{
1947	"piix3ide", 31, 1 /* IDE controller */
1948	},
1949	/* Disable, if we may wish to have multiple AHCI controllers */
1950	#if 1
1951	{
1952	"ahci", 31, 2 /* SATA controller */
1953	},
1954	#endif
1955	{
1956	"smbus", 31, 3 /* System Management Bus */
1957	},
1958	{
1959	"usb-ohci", 31, 4 /* OHCI USB controller */
1960	},
1961	{
1962	"usb-ehci", 31, 5 /* EHCI USB controller */
1963	},
1964	{
1965	"thermal", 31, 6 /* Thermal controller */
1966	},
1967	};
1968
1969	static bool assignPosition(PPCIBUS pBus, PPCIDEVICE pPciDev, const char pszName, int iDevFn, PciAddress aPosition)
1970	{
1971	aPosition->iBus = 0;
1972	aPosition->iDeviceFunc = iDevFn;
1973	aPosition->iRegister = 0; /* N/A */
1974
1975	/* Hardcoded slots/functions, per chipset spec */
1976	for (size_t i = 0; i < RT_ELEMENTS(PciSlotAssignments); i++)
1977	{
1978	if (!strcmp(pszName, PciSlotAssignments[i].pszName))
1979	{
1980	PCISetRequestedDevfunc(pPciDev);
1981	aPosition->iDeviceFunc =
1982	(PciSlotAssignments[i].iSlot << 3) + PciSlotAssignments[i].iFunction;
1983	return true;
1984	}
1985	}
1986
1987	/* Explicit slot request */
1988	if (iDevFn >=0 && iDevFn < (int)RT_ELEMENTS(pBus->apDevices))
1989	return true;
1990
1991	/* Otherwise when assigning a slot, we need to make sure all its functions are available */
1992	for (int iPos = 0; iPos < (int)RT_ELEMENTS(pBus->apDevices); iPos += 8)
1993	{
1994	if ( !pBus->apDevices[iPos]
1995	&& !pBus->apDevices[iPos + 1]
1996	&& !pBus->apDevices[iPos + 2]
1997	&& !pBus->apDevices[iPos + 3]
1998	&& !pBus->apDevices[iPos + 4]
1999	&& !pBus->apDevices[iPos + 5]
2000	&& !pBus->apDevices[iPos + 6]
2001	&& !pBus->apDevices[iPos + 7])
2002	{
2003	PCIClearRequestedDevfunc(pPciDev);
2004	aPosition->iDeviceFunc = iPos;
2005	return true;
2006	}
2007	}
2008
2009	return false;
2010	}
2011
2012	static bool hasHardAssignedDevsInSlot(PPCIBUS pBus, int iSlot)
2013	{
2014	PCIDevice** aSlot = &pBus->apDevices[iSlot << 3];
2015
2016	return (aSlot[0] && PCIIsRequestedDevfunc(aSlot[0]))
2017	\|\| (aSlot[1] && PCIIsRequestedDevfunc(aSlot[1]))
2018	\|\| (aSlot[2] && PCIIsRequestedDevfunc(aSlot[2]))
2019	\|\| (aSlot[3] && PCIIsRequestedDevfunc(aSlot[3]))
2020	\|\| (aSlot[4] && PCIIsRequestedDevfunc(aSlot[4]))
2021	\|\| (aSlot[5] && PCIIsRequestedDevfunc(aSlot[5]))
2022	\|\| (aSlot[6] && PCIIsRequestedDevfunc(aSlot[6]))
2023	\|\| (aSlot[7] && PCIIsRequestedDevfunc(aSlot[7]))
2024	;
2025	}
2026
2027	static int ich9pciRegisterInternal(PPCIBUS pBus, int iDev, PPCIDEVICE pPciDev, const char *pszName)
2028	{
2029	PciAddress aPosition = {0, 0, 0};
2030
2031	/*
2032	* Find device position
2033	*/
2034	if (!assignPosition(pBus, pPciDev, pszName, iDev, &aPosition))
2035	{
2036	AssertMsgFailed(("Couldn't asssign position!\n"));
2037	return VERR_PDM_TOO_PCI_MANY_DEVICES;
2038	}
2039
2040	AssertMsgReturn(aPosition.iBus == 0,
2041	("Assigning behind the bridge not implemented yet\n"),
2042	VERR_PDM_TOO_PCI_MANY_DEVICES);
2043
2044
2045	iDev = aPosition.iDeviceFunc;
2046	/*
2047	* Check if we can really take this slot, possibly by relocating
2048	* its current habitant, if it wasn't hard assigned too.
2049	*/
2050	if (PCIIsRequestedDevfunc(pPciDev) &&
2051	pBus->apDevices[iDev] &&
2052	PCIIsRequestedDevfunc(pBus->apDevices[iDev]))
2053	{
2054	AssertReleaseMsgFailed(("Configuration error:'%s' and '%s' are both configured as device %d\n",
2055	pszName, pBus->apDevices[iDev]->name, iDev));
2056	return VERR_INTERNAL_ERROR;
2057	}
2058
2059	if (pBus->apDevices[iDev])
2060	{
2061	/* if we got here, we shall (and usually can) relocate the device */
2062	bool assigned = assignPosition(pBus, pBus->apDevices[iDev], pBus->apDevices[iDev]->name, -1, &aPosition);
2063	AssertMsgReturn(aPosition.iBus == 0,
2064	("Assigning behind the bridge not implemented yet\n"),
2065	VERR_PDM_TOO_PCI_MANY_DEVICES);
2066	int iRelDev = aPosition.iDeviceFunc;
2067	if (!assigned \|\| iRelDev == iDev)
2068	{
2069	AssertMsgFailed(("Couldn't find free spot!\n"));
2070	return VERR_PDM_TOO_PCI_MANY_DEVICES;
2071	}
2072	/* Copy device function by function to its new position */
2073	for (int i = 0; i < 8; i++)
2074	{
2075	if (!pBus->apDevices[iDev + i])
2076	continue;
2077	Log(("PCI: relocating '%s' from slot %#x to %#x\n", pBus->apDevices[iDev + i]->name, iDev + i, iRelDev + i));
2078	pBus->apDevices[iRelDev + i] = pBus->apDevices[iDev + i];
2079	pBus->apDevices[iRelDev + i]->devfn = iRelDev + i;
2080	pBus->apDevices[iDev + i] = NULL;
2081	}
2082	}
2083
2084	/*
2085	* Fill in device information.
2086	*/
2087	pPciDev->devfn = iDev;
2088	pPciDev->name = pszName;
2089	pPciDev->Int.s.pBusR3 = pBus;
2090	pPciDev->Int.s.pBusR0 = MMHyperR3ToR0(PDMDevHlpGetVM(pBus->CTX_SUFF(pDevIns)), pBus);
2091	pPciDev->Int.s.pBusRC = MMHyperR3ToRC(PDMDevHlpGetVM(pBus->CTX_SUFF(pDevIns)), pBus);
2092	pPciDev->Int.s.pfnConfigRead = ich9pciConfigReadDev;
2093	pPciDev->Int.s.pfnConfigWrite = ich9pciConfigWriteDev;
2094	pBus->apDevices[iDev] = pPciDev;
2095	if (PCIIsPci2PciBridge(pPciDev))
2096	{
2097	AssertMsg(pBus->cBridges < RT_ELEMENTS(pBus->apDevices), ("Number of bridges exceeds the number of possible devices on the bus\n"));
2098	AssertMsg(pPciDev->Int.s.pfnBridgeConfigRead && pPciDev->Int.s.pfnBridgeConfigWrite,
2099	("device is a bridge but does not implement read/write functions\n"));
2100	pBus->papBridgesR3[pBus->cBridges] = pPciDev;
2101	pBus->cBridges++;
2102	}
2103
2104	Log(("PCI: Registered device %d function %d (%#x) '%s'.\n",
2105	iDev >> 3, iDev & 7, 0x80000000 \| (iDev << 8), pszName));
2106
2107	return VINF_SUCCESS;
2108	}
2109
2110
2111	/**
2112	* Info handler, device version.
2113	*
2114	* @param pDevIns Device instance which registered the info.
2115	* @param pHlp Callback functions for doing output.
2116	* @param pszArgs Argument string. Optional and specific to the handler.
2117	*/
2118	static DECLCALLBACK(void) ich9pciInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
2119	{
2120	PPCIBUS pBus = DEVINS_2_PCIBUS(pDevIns);
2121	uint32_t iBus = 0, iDev;
2122
2123
2124	for (iDev = 0; iDev < RT_ELEMENTS(pBus->apDevices); iDev++)
2125	{
2126	PPCIDEVICE pPciDev = pBus->apDevices[iDev];
2127	if (pPciDev != NULL)
2128	pHlp->pfnPrintf(pHlp, "%02x:%02x:%02x %s: %x-%x\n",
2129	iBus, (iDev >> 3) & 0xff, iDev & 0x7,
2130	pPciDev->name,
2131	PCIDevGetVendorId(pPciDev), PCIDevGetDeviceId(pPciDev)
2132	);
2133	}
2134	}
2135
2136
2137	static DECLCALLBACK(int) ich9pciConstruct(PPDMDEVINS pDevIns,
2138	int iInstance,
2139	PCFGMNODE pCfg)
2140	{
2141	int rc;
2142	Assert(iInstance == 0);
2143
2144	/*
2145	* Validate and read configuration.
2146	*/
2147	if (!CFGMR3AreValuesValid(pCfg,
2148	"IOAPIC\0"
2149	"GCEnabled\0"
2150	"R0Enabled\0"
2151	"McfgBase\0"
2152	"McfgLength\0"
2153	))
2154	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
2155
2156	/* query whether we got an IOAPIC */
2157	bool fUseIoApic;
2158	rc = CFGMR3QueryBoolDef(pCfg, "IOAPIC", &fUseIoApic, false);
2159	if (RT_FAILURE(rc))
2160	return PDMDEV_SET_ERROR(pDevIns, rc,
2161	N_("Configuration error: Failed to query boolean value \"IOAPIC\""));
2162
2163	/* check if RC code is enabled. */
2164	bool fGCEnabled;
2165	rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
2166	if (RT_FAILURE(rc))
2167	return PDMDEV_SET_ERROR(pDevIns, rc,
2168	N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
2169
2170	/* check if R0 code is enabled. */
2171	bool fR0Enabled;
2172	rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
2173	if (RT_FAILURE(rc))
2174	return PDMDEV_SET_ERROR(pDevIns, rc,
2175	N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
2176
2177	Log(("PCI: fUseIoApic=%RTbool fGCEnabled=%RTbool fR0Enabled=%RTbool\n", fUseIoApic, fGCEnabled, fR0Enabled));
2178
2179	/*
2180	* Init data.
2181	*/
2182	PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
2183	PPCIBUS pBus = &pGlobals->aPciBus;
2184	/* Zero out everything */
2185	memset(pGlobals, 0, sizeof(*pGlobals));
2186	/* And fill values */
2187	if (!fUseIoApic)
2188	return PDMDEV_SET_ERROR(pDevIns, rc,
2189	N_("Must use IO-APIC with ICH9 chipset"));
2190	rc = CFGMR3QueryU64Def(pCfg, "McfgBase", &pGlobals->u64PciConfigMMioAddress, 0);
2191	if (RT_FAILURE(rc))
2192	return PDMDEV_SET_ERROR(pDevIns, rc,
2193	N_("Configuration error: Failed to read \"McfgBase\""));
2194	rc = CFGMR3QueryU64Def(pCfg, "McfgLength", &pGlobals->u64PciConfigMMioLength, 0);
2195	if (RT_FAILURE(rc))
2196	return PDMDEV_SET_ERROR(pDevIns, rc,
2197	N_("Configuration error: Failed to read \"McfgLength\""));
2198
2199	pGlobals->pDevInsR3 = pDevIns;
2200	pGlobals->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2201	pGlobals->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2202
2203	pGlobals->aPciBus.pDevInsR3 = pDevIns;
2204	pGlobals->aPciBus.pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2205	pGlobals->aPciBus.pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2206	pGlobals->aPciBus.papBridgesR3 = (PPCIDEVICE )PDMDevHlpMMHeapAllocZ(pDevIns, sizeof(PPCIDEVICE) RT_ELEMENTS(pGlobals->aPciBus.apDevices));
2207
2208	/*
2209	* Register bus
2210	*/
2211	PDMPCIBUSREG PciBusReg;
2212	PciBusReg.u32Version = PDM_PCIBUSREG_VERSION;
2213	PciBusReg.pfnRegisterR3 = ich9pciRegister;
2214	PciBusReg.pfnRegisterMsiR3 = ich9pciRegisterMsi;
2215	PciBusReg.pfnIORegionRegisterR3 = ich9pciIORegionRegister;
2216	PciBusReg.pfnSetConfigCallbacksR3 = ich9pciSetConfigCallbacks;
2217	PciBusReg.pfnSetIrqR3 = ich9pciSetIrq;
2218	PciBusReg.pfnSaveExecR3 = ich9pciGenericSaveExec;
2219	PciBusReg.pfnLoadExecR3 = ich9pciGenericLoadExec;
2220	PciBusReg.pfnFakePCIBIOSR3 = ich9pciFakePCIBIOS;
2221	PciBusReg.pszSetIrqRC = fGCEnabled ? "ich9pciSetIrq" : NULL;
2222	PciBusReg.pszSetIrqR0 = fR0Enabled ? "ich9pciSetIrq" : NULL;
2223	rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBus->pPciHlpR3);
2224	if (RT_FAILURE(rc))
2225	return PDMDEV_SET_ERROR(pDevIns, rc,
2226	N_("Failed to register ourselves as a PCI Bus"));
2227	if (pBus->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
2228	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
2229	N_("PCI helper version mismatch; got %#x expected %#x"),
2230	pBus->pPciHlpR3->u32Version, PDM_PCIHLPR3_VERSION);
2231
2232	pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
2233	pBus->pPciHlpR0 = pBus->pPciHlpR3->pfnGetR0Helpers(pDevIns);
2234
2235	/*
2236	* Fill in PCI configs and add them to the bus.
2237	*/
2238
2239	/**
2240	* We emulate 82801IB ICH9 IO chip used in Q35,
2241	* see http://ark.intel.com/Product.aspx?id=31892
2242	*
2243	* Stepping S-Spec Top Marking
2244	*
2245	* A2 SLA9M NH82801IB
2246	*/
2247	PCIDevSetVendorId( &pBus->aPciDev, 0x8086); /* Intel */
2248	PCIDevSetDeviceId( &pBus->aPciDev, 0x244e); /* Desktop */
2249	PCIDevSetRevisionId(&pBus->aPciDev, 0x92); /* rev. A2 */
2250	PCIDevSetClassSub( &pBus->aPciDev, 0x00); /* Host/PCI bridge */
2251	PCIDevSetClassBase( &pBus->aPciDev, 0x06); /* bridge */
2252	PCIDevSetHeaderType(&pBus->aPciDev, 0x00); /* normal device */
2253
2254	pBus->aPciDev.pDevIns = pDevIns;
2255	/* We register Host<->PCI controller on the bus */
2256	ich9pciRegisterInternal(pBus, -1, &pBus->aPciDev, "i82801");
2257
2258	/*
2259	* Register I/O ports and save state.
2260	*/
2261	rc = PDMDevHlpIOPortRegister(pDevIns, 0x0cf8, 1, NULL, ich9pciIOPortAddressWrite, ich9pciIOPortAddressRead, NULL, NULL, "ICH9 (PCI)");
2262	if (RT_FAILURE(rc))
2263	return rc;
2264	rc = PDMDevHlpIOPortRegister(pDevIns, 0x0cfc, 4, NULL, ich9pciIOPortDataWrite, ich9pciIOPortDataRead, NULL, NULL, "ICH9 (PCI)");
2265	if (RT_FAILURE(rc))
2266	return rc;
2267	if (fGCEnabled)
2268	{
2269	rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x0cf8, 1, NIL_RTGCPTR, "ich9pciIOPortAddressWrite", "ich9pciIOPortAddressRead", NULL, NULL, "ICH9 (PCI)");
2270	if (RT_FAILURE(rc))
2271	return rc;
2272	rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x0cfc, 4, NIL_RTGCPTR, "ich9pciIOPortDataWrite", "ich9pciIOPortDataRead", NULL, NULL, "ICH9 (PCI)");
2273	if (RT_FAILURE(rc))
2274	return rc;
2275	}
2276	if (fR0Enabled)
2277	{
2278	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x0cf8, 1, NIL_RTR0PTR, "ich9pciIOPortAddressWrite", "ich9pciIOPortAddressRead", NULL, NULL, "ICH9 (PCI)");
2279	if (RT_FAILURE(rc))
2280	return rc;
2281	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x0cfc, 4, NIL_RTR0PTR, "ich9pciIOPortDataWrite", "ich9pciIOPortDataRead", NULL, NULL, "ICH9 (PCI)");
2282	if (RT_FAILURE(rc))
2283	return rc;
2284	}
2285
2286	if (pGlobals->u64PciConfigMMioAddress != 0)
2287	{
2288	rc = PDMDevHlpMMIORegister(pDevIns,
2289	pGlobals->u64PciConfigMMioAddress,
2290	pGlobals->u64PciConfigMMioLength,
2291	0,
2292	ich9pciMcfgMMIOWrite,
2293	ich9pciMcfgMMIORead,
2294	NULL /* fill */,
2295	"MCFG ranges");
2296	if (RT_FAILURE(rc))
2297	{
2298	AssertMsgRC(rc, ("Cannot register MCFG MMIO: %Rrc\n", rc));
2299	return rc;
2300	}
2301
2302	if (fGCEnabled)
2303	{
2304
2305	rc = PDMDevHlpMMIORegisterRC(pDevIns,
2306	pGlobals->u64PciConfigMMioAddress,
2307	pGlobals->u64PciConfigMMioLength,
2308	0,
2309	"ich9pciMcfgMMIOWrite",
2310	"ich9pciMcfgMMIORead",
2311	NULL /* fill */);
2312	if (RT_FAILURE(rc))
2313	{
2314	AssertMsgRC(rc, ("Cannot register MCFG MMIO (GC): %Rrc\n", rc));
2315	return rc;
2316	}
2317	}
2318
2319
2320	if (fR0Enabled)
2321	{
2322
2323	rc = PDMDevHlpMMIORegisterR0(pDevIns,
2324	pGlobals->u64PciConfigMMioAddress,
2325	pGlobals->u64PciConfigMMioLength,
2326	0,
2327	"ich9pciMcfgMMIOWrite",
2328	"ich9pciMcfgMMIORead",
2329	NULL /* fill */);
2330	if (RT_FAILURE(rc))
2331	{
2332	AssertMsgRC(rc, ("Cannot register MCFG MMIO (R0): %Rrc\n", rc));
2333	return rc;
2334	}
2335	}
2336	}
2337
2338	rc = PDMDevHlpSSMRegisterEx(pDevIns, VBOX_ICH9PCI_SAVED_STATE_VERSION_CURRENT,
2339	sizeof(pBus) + 16128, "pgm",
2340	NULL, NULL, NULL,
2341	NULL, ich9pciR3SaveExec, NULL,
2342	NULL, ich9pciR3LoadExec, NULL);
2343	if (RT_FAILURE(rc))
2344	return rc;
2345
2346
2347	/** @todo: other chipset devices shall be registered too */
2348	/** @todo: what to with bridges? */
2349
2350	PDMDevHlpDBGFInfoRegister(pDevIns, "pci", "Display PCI bus status. (no arguments)", ich9pciInfo);
2351
2352	return VINF_SUCCESS;
2353	}
2354
2355	static void ich9pciResetDevice(PPCIDEVICE pDev)
2356	{
2357	pDev->config[VBOX_PCI_COMMAND] &= ~(VBOX_PCI_COMMAND_IO \| VBOX_PCI_COMMAND_MEMORY \|
2358	VBOX_PCI_COMMAND_MASTER);
2359
2360	if (!PCIIsPci2PciBridge(pDev))
2361	{
2362	PCIDevSetByte(pDev, VBOX_PCI_CACHE_LINE_SIZE, 0x0);
2363	PCIDevSetByte(pDev, VBOX_PCI_INTERRUPT_LINE, 0x0);
2364	}
2365	/* Regions ? */
2366	}
2367
2368
2369	/**
2370	* @copydoc FNPDMDEVRESET
2371	*/
2372	static DECLCALLBACK(void) ich9pciReset(PPDMDEVINS pDevIns)
2373	{
2374	PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
2375	PPCIBUS pBus = &pGlobals->aPciBus;
2376
2377	/* Relocate RC pointers for the attached pci devices. */
2378	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
2379	{
2380	if (pBus->apDevices[i])
2381	ich9pciResetDevice(pBus->apDevices[i]);
2382	}
2383	}
2384
2385	/**
2386	* @copydoc FNPDMDEVRELOCATE
2387	*/
2388	static DECLCALLBACK(void) ich9pciRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
2389	{
2390	PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
2391	PPCIBUS pBus = &pGlobals->aPciBus;
2392	pGlobals->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2393
2394	pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
2395	pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2396
2397	/* Relocate RC pointers for the attached pci devices. */
2398	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
2399	{
2400	if (pBus->apDevices[i])
2401	pBus->apDevices[i]->Int.s.pBusRC += offDelta;
2402	}
2403
2404	}
2405
2406	/**
2407	* @interface_method_impl{PDMDEVREG,pfnConstruct}
2408	*/
2409	static DECLCALLBACK(int) ich9pcibridgeConstruct(PPDMDEVINS pDevIns,
2410	int iInstance,
2411	PCFGMNODE pCfg)
2412	{
2413	int rc;
2414
2415	/*
2416	* Validate and read configuration.
2417	*/
2418	if (!CFGMR3AreValuesValid(pCfg, "GCEnabled\0" "R0Enabled\0"))
2419	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
2420
2421	/* check if RC code is enabled. */
2422	bool fGCEnabled;
2423	rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
2424	if (RT_FAILURE(rc))
2425	return PDMDEV_SET_ERROR(pDevIns, rc,
2426	N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
2427
2428	/* check if R0 code is enabled. */
2429	bool fR0Enabled;
2430	rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
2431	if (RT_FAILURE(rc))
2432	return PDMDEV_SET_ERROR(pDevIns, rc,
2433	N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
2434	Log(("PCI: fGCEnabled=%RTbool fR0Enabled=%RTbool\n", fGCEnabled, fR0Enabled));
2435
2436	/*
2437	* Init data and register the PCI bus.
2438	*/
2439	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
2440	pBus->pDevInsR3 = pDevIns;
2441	pBus->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2442	pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2443	pBus->papBridgesR3 = (PPCIDEVICE )PDMDevHlpMMHeapAllocZ(pDevIns, sizeof(PPCIDEVICE) RT_ELEMENTS(pBus->apDevices));
2444
2445	PDMPCIBUSREG PciBusReg;
2446	PciBusReg.u32Version = PDM_PCIBUSREG_VERSION;
2447	PciBusReg.pfnRegisterR3 = ich9pcibridgeRegister;
2448	PciBusReg.pfnRegisterMsiR3 = ich9pciRegisterMsi;
2449	PciBusReg.pfnIORegionRegisterR3 = ich9pciIORegionRegister;
2450	PciBusReg.pfnSetConfigCallbacksR3 = ich9pciSetConfigCallbacks;
2451	PciBusReg.pfnSetIrqR3 = ich9pcibridgeSetIrq;
2452	PciBusReg.pfnSaveExecR3 = ich9pciGenericSaveExec;
2453	PciBusReg.pfnLoadExecR3 = ich9pciGenericLoadExec;
2454	PciBusReg.pfnFakePCIBIOSR3 = NULL; /* Only needed for the first bus. */
2455	PciBusReg.pszSetIrqRC = fGCEnabled ? "ich9pcibridgeSetIrq" : NULL;
2456	PciBusReg.pszSetIrqR0 = fR0Enabled ? "ich9pcibridgeSetIrq" : NULL;
2457	rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBus->pPciHlpR3);
2458	if (RT_FAILURE(rc))
2459	return PDMDEV_SET_ERROR(pDevIns, rc,
2460	N_("Failed to register ourselves as a PCI Bus"));
2461	if (pBus->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
2462	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
2463	N_("PCI helper version mismatch; got %#x expected %#x"),
2464	pBus->pPciHlpR3->u32Version, PDM_PCIHLPR3_VERSION);
2465
2466	pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
2467	pBus->pPciHlpR0 = pBus->pPciHlpR3->pfnGetR0Helpers(pDevIns);
2468
2469	/*
2470	* Fill in PCI configs and add them to the bus.
2471	*/
2472	PCIDevSetVendorId( &pBus->aPciDev, 0x8086); /* Intel */
2473	PCIDevSetDeviceId( &pBus->aPciDev, 0x2448); /* 82801 Mobile PCI bridge. */
2474	PCIDevSetRevisionId(&pBus->aPciDev, 0xf2);
2475	PCIDevSetClassSub( &pBus->aPciDev, 0x04); /* pci2pci */
2476	PCIDevSetClassBase( &pBus->aPciDev, 0x06); /* PCI_bridge */
2477	PCIDevSetClassProg( &pBus->aPciDev, 0x01); /* Supports subtractive decoding. */
2478	PCIDevSetHeaderType(&pBus->aPciDev, 0x01); /* Single function device which adheres to the PCI-to-PCI bridge spec. */
2479	PCIDevSetCommand( &pBus->aPciDev, 0x00);
2480	PCIDevSetStatus( &pBus->aPciDev, 0x20); /* 66MHz Capable. */
2481	PCIDevSetInterruptLine(&pBus->aPciDev, 0x00); /* This device does not assert interrupts. */
2482
2483	/*
2484	* This device does not generate interrupts. Interrupt delivery from
2485	* devices attached to the bus is unaffected.
2486	*/
2487	PCIDevSetInterruptPin (&pBus->aPciDev, 0x00);
2488
2489	pBus->aPciDev.pDevIns = pDevIns;
2490
2491	/* Bridge-specific data */
2492	PCISetPci2PciBridge(&pBus->aPciDev);
2493	pBus->aPciDev.Int.s.pfnBridgeConfigRead = ich9pcibridgeConfigRead;
2494	pBus->aPciDev.Int.s.pfnBridgeConfigWrite = ich9pcibridgeConfigWrite;
2495
2496	/*
2497	* Register this PCI bridge. The called function will take care on which bus we will get registered.
2498	*/
2499	rc = PDMDevHlpPCIRegister (pDevIns, &pBus->aPciDev);
2500	if (RT_FAILURE(rc))
2501	return rc;
2502
2503	/*
2504	* The iBus property doesn't really represent the bus number
2505	* because the guest and the BIOS can choose different bus numbers
2506	* for them.
2507	* The bus number is mainly for the setIrq function to indicate
2508	* when the host bus is reached which will have iBus = 0.
2509	* Thathswhy the + 1.
2510	*/
2511	pBus->iBus = iInstance + 1;
2512
2513	/*
2514	* Register SSM handlers. We use the same saved state version as for the host bridge
2515	* to make changes easier.
2516	*/
2517	rc = PDMDevHlpSSMRegisterEx(pDevIns, VBOX_ICH9PCI_SAVED_STATE_VERSION_CURRENT,
2518	sizeof(pBus) + 16128,
2519	"pgm" /* before */,
2520	NULL, NULL, NULL,
2521	NULL, ich9pcibridgeR3SaveExec, NULL,
2522	NULL, ich9pcibridgeR3LoadExec, NULL);
2523	if (RT_FAILURE(rc))
2524	return rc;
2525
2526
2527	return VINF_SUCCESS;
2528	}
2529
2530	/**
2531	* @copydoc FNPDMDEVRESET
2532	*/
2533	static DECLCALLBACK(void) ich9pcibridgeReset(PPDMDEVINS pDevIns)
2534	{
2535	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
2536
2537	/* Reset config space to default values. */
2538	PCIDevSetByte(&pBus->aPciDev, VBOX_PCI_PRIMARY_BUS, 0);
2539	PCIDevSetByte(&pBus->aPciDev, VBOX_PCI_SECONDARY_BUS, 0);
2540	PCIDevSetByte(&pBus->aPciDev, VBOX_PCI_SUBORDINATE_BUS, 0);
2541	}
2542
2543
2544	/**
2545	* @copydoc FNPDMDEVRELOCATE
2546	*/
2547	static DECLCALLBACK(void) ich9pcibridgeRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
2548	{
2549	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
2550	pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2551
2552	/* Relocate RC pointers for the attached pci devices. */
2553	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
2554	{
2555	if (pBus->apDevices[i])
2556	pBus->apDevices[i]->Int.s.pBusRC += offDelta;
2557	}
2558
2559	}
2560
2561	/**
2562	* The PCI bus device registration structure.
2563	*/
2564	const PDMDEVREG g_DevicePciIch9 =
2565	{
2566	/* u32Version */
2567	PDM_DEVREG_VERSION,
2568	/* szName */
2569	"ich9pci",
2570	/* szRCMod */
2571	"VBoxDDGC.gc",
2572	/* szR0Mod */
2573	"VBoxDDR0.r0",
2574	/* pszDescription */
2575	"ICH9 PCI bridge",
2576	/* fFlags */
2577	PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
2578	/* fClass */
2579	PDM_DEVREG_CLASS_BUS_PCI \| PDM_DEVREG_CLASS_BUS_ISA,
2580	/* cMaxInstances */
2581	1,
2582	/* cbInstance */
2583	sizeof(PCIGLOBALS),
2584	/* pfnConstruct */
2585	ich9pciConstruct,
2586	/* pfnDestruct */
2587	NULL,
2588	/* pfnRelocate */
2589	ich9pciRelocate,
2590	/* pfnIOCtl */
2591	NULL,
2592	/* pfnPowerOn */
2593	NULL,
2594	/* pfnReset */
2595	ich9pciReset,
2596	/* pfnSuspend */
2597	NULL,
2598	/* pfnResume */
2599	NULL,
2600	/* pfnAttach */
2601	NULL,
2602	/* pfnDetach */
2603	NULL,
2604	/* pfnQueryInterface */
2605	NULL,
2606	/* pfnInitComplete */
2607	NULL,
2608	/* pfnPowerOff */
2609	NULL,
2610	/* pfnSoftReset */
2611	NULL,
2612	/* u32VersionEnd */
2613	PDM_DEVREG_VERSION
2614	};
2615
2616	/**
2617	* The device registration structure
2618	* for the PCI-to-PCI bridge.
2619	*/
2620	const PDMDEVREG g_DevicePciIch9Bridge =
2621	{
2622	/* u32Version */
2623	PDM_DEVREG_VERSION,
2624	/* szName */
2625	"ich9pcibridge",
2626	/* szRCMod */
2627	"VBoxDDGC.gc",
2628	/* szR0Mod */
2629	"VBoxDDR0.r0",
2630	/* pszDescription */
2631	"ICH9 PCI to PCI bridge",
2632	/* fFlags */
2633	PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
2634	/* fClass */
2635	PDM_DEVREG_CLASS_BUS_PCI,
2636	/* cMaxInstances */
2637	~0,
2638	/* cbInstance */
2639	sizeof(PCIBUS),
2640	/* pfnConstruct */
2641	ich9pcibridgeConstruct,
2642	/* pfnDestruct */
2643	NULL,
2644	/* pfnRelocate */
2645	ich9pcibridgeRelocate,
2646	/* pfnIOCtl */
2647	NULL,
2648	/* pfnPowerOn */
2649	NULL,
2650	/* pfnReset */
2651	ich9pcibridgeReset,
2652	/* pfnSuspend */
2653	NULL,
2654	/* pfnResume */
2655	NULL,
2656	/* pfnAttach */
2657	NULL,
2658	/* pfnDetach */
2659	NULL,
2660	/* pfnQueryInterface */
2661	NULL,
2662	/* pfnInitComplete */
2663	NULL,
2664	/* pfnPowerOff */
2665	NULL,
2666	/* pfnSoftReset */
2667	NULL,
2668	/* u32VersionEnd */
2669	PDM_DEVREG_VERSION
2670	};
2671
2672	#endif /* IN_RING3 */
2673	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */

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source: vbox/trunk/src/VBox/Devices/Bus/DevPciIch9.cpp@ 33419

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