DevPciIch9.cpp@ 34836

Last change on this file since 34836 was 34836, checked in by vboxsync, 14 years ago
PCI: fix Windows device manage question marks
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1	/* $Id: DevPciIch9.cpp 34836 2010-12-08 14:18:29Z vboxsync $ */
2	/** @file
3	* DevPCI - ICH9 southbridge PCI bus emulation Device.
4	*/
5
6	/*
7	* Copyright (C) 2010 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/*******************************************************************************
19	* Header Files *
20	*******************************************************************************/
21	#define LOG_GROUP LOG_GROUP_DEV_PCI
22	/* Hack to get PCIDEVICEINT declare at the right point - include "PCIInternal.h". */
23	#define PCI_INCLUDE_PRIVATE
24	#include <VBox/pci.h>
25	#include <VBox/msi.h>
26	#include <VBox/pdmdev.h>
27	#include <iprt/asm.h>
28	#include <iprt/assert.h>
29	#include <iprt/string.h>
30	#ifdef IN_RING3
31	#include <iprt/alloc.h>
32	#endif
33
34	#include "../Builtins.h"
35
36	#include "MsiCommon.h"
37
38	/**
39	* PCI Bus instance.
40	*/
41	typedef struct PCIBus
42	{
43	/** Bus number. */
44	int32_t iBus;
45	/** Number of bridges attached to the bus. */
46	uint32_t cBridges;
47
48	/** Array of PCI devices. We assume 32 slots, each with 8 functions. */
49	R3PTRTYPE(PPCIDEVICE) apDevices[256];
50	/** Array of bridges attached to the bus. */
51	R3PTRTYPE(PPCIDEVICE *) papBridgesR3;
52
53	/** R3 pointer to the device instance. */
54	PPDMDEVINSR3 pDevInsR3;
55	/** Pointer to the PCI R3 helpers. */
56	PCPDMPCIHLPR3 pPciHlpR3;
57
58	/** R0 pointer to the device instance. */
59	PPDMDEVINSR0 pDevInsR0;
60	/** Pointer to the PCI R0 helpers. */
61	PCPDMPCIHLPR0 pPciHlpR0;
62
63	/** RC pointer to the device instance. */
64	PPDMDEVINSRC pDevInsRC;
65	/** Pointer to the PCI RC helpers. */
66	PCPDMPCIHLPRC pPciHlpRC;
67
68	/** The PCI device for the PCI bridge. */
69	PCIDEVICE aPciDev;
70
71	} PCIBUS, *PPCIBUS;
72
73
74	/** @def PCI_APIC_IRQ_PINS
75	* Number of pins for interrupts if the APIC is used.
76	*/
77	#define PCI_APIC_IRQ_PINS 8
78
79	/**
80	* PCI Globals - This is the host-to-pci bridge and the root bus.
81	*/
82	typedef struct
83	{
84	/** R3 pointer to the device instance. */
85	PPDMDEVINSR3 pDevInsR3;
86	/** R0 pointer to the device instance. */
87	PPDMDEVINSR0 pDevInsR0;
88	/** RC pointer to the device instance. */
89	PPDMDEVINSRC pDevInsRC;
90
91	#if HC_ARCH_BITS == 64
92	uint32_t Alignment0;
93	#endif
94
95	/** PCI bus which is attached to the host-to-PCI bridge. */
96	PCIBUS aPciBus;
97
98
99	/** I/O APIC irq levels */
100	volatile uint32_t uaPciApicIrqLevels[PCI_APIC_IRQ_PINS];
101
102	#if 1 /* Will be moved into the BIOS soon. */
103	/** The next I/O port address which the PCI BIOS will use. */
104	uint32_t uPciBiosIo;
105	/** The next MMIO address which the PCI BIOS will use. */
106	uint32_t uPciBiosMmio;
107	/** Actual bus number. */
108	uint8_t uBus;
109	#endif
110	/* Physical address of PCI config space MMIO region */
111	uint64_t u64PciConfigMMioAddress;
112	/* Length of PCI config space MMIO region */
113	uint64_t u64PciConfigMMioLength;
114
115
116	/** Config register. */
117	uint32_t uConfigReg;
118	} PCIGLOBALS, *PPCIGLOBALS;
119
120
121	typedef struct {
122	uint8_t iBus;
123	uint8_t iDeviceFunc;
124	uint16_t iRegister;
125	} PciAddress;
126
127	/*******************************************************************************
128	* Defined Constants And Macros *
129	*******************************************************************************/
130
131	/** @def VBOX_ICH9PCI_SAVED_STATE_VERSION
132	* Saved state version of the ICH9 PCI bus device.
133	*/
134	#define VBOX_ICH9PCI_SAVED_STATE_VERSION_NOMSI 1
135	#define VBOX_ICH9PCI_SAVED_STATE_VERSION_MSI 2
136	#define VBOX_ICH9PCI_SAVED_STATE_VERSION_CURRENT VBOX_ICH9PCI_SAVED_STATE_VERSION_MSI
137
138	/** Converts a bus instance pointer to a device instance pointer. */
139	#define PCIBUS_2_DEVINS(pPciBus) ((pPciBus)->CTX_SUFF(pDevIns))
140	/** Converts a device instance pointer to a PCIGLOBALS pointer. */
141	#define DEVINS_2_PCIGLOBALS(pDevIns) ((PPCIGLOBALS)(PDMINS_2_DATA(pDevIns, PPCIGLOBALS)))
142	/** Converts a device instance pointer to a PCIBUS pointer. */
143	#define DEVINS_2_PCIBUS(pDevIns) ((PPCIBUS)(&PDMINS_2_DATA(pDevIns, PPCIGLOBALS)->aPciBus))
144	/** Converts a pointer to a PCI root bus instance to a PCIGLOBALS pointer.
145	*/
146	#define PCIROOTBUS_2_PCIGLOBALS(pPciBus) ( (PPCIGLOBALS)((uintptr_t)(pPciBus) - RT_OFFSETOF(PCIGLOBALS, aPciBus)) )
147
148
149	/** @def PCI_LOCK
150	* Acquires the PDM lock. This is a NOP if locking is disabled. */
151	/** @def PCI_UNLOCK
152	* Releases the PDM lock. This is a NOP if locking is disabled. */
153	#define PCI_LOCK(pDevIns, rc) \
154	do { \
155	int rc2 = DEVINS_2_PCIBUS(pDevIns)->CTX_SUFF(pPciHlp)->pfnLock((pDevIns), rc); \
156	if (rc2 != VINF_SUCCESS) \
157	return rc2; \
158	} while (0)
159	#define PCI_UNLOCK(pDevIns) \
160	DEVINS_2_PCIBUS(pDevIns)->CTX_SUFF(pPciHlp)->pfnUnlock(pDevIns)
161
162	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
163
164	RT_C_DECLS_BEGIN
165
166	PDMBOTHCBDECL(void) ich9pciSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel);
167	PDMBOTHCBDECL(void) ich9pcibridgeSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel);
168	PDMBOTHCBDECL(int) ich9pciIOPortAddressWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
169	PDMBOTHCBDECL(int) ich9pciIOPortAddressRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb);
170	PDMBOTHCBDECL(int) ich9pciIOPortDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
171	PDMBOTHCBDECL(int) ich9pciIOPortDataRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb);
172	PDMBOTHCBDECL(int) ich9pciMcfgMMIOWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb);
173	PDMBOTHCBDECL(int) ich9pciMcfgMMIORead (PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb);
174
175	RT_C_DECLS_END
176
177	/* Prototypes */
178	static void ich9pciSetIrqInternal(PPCIGLOBALS pGlobals, uint8_t uDevFn, PPCIDEVICE pPciDev, int iIrq, int iLevel);
179	#ifdef IN_RING3
180	static void ich9pcibridgeReset(PPDMDEVINS pDevIns);
181	static int ich9pciRegisterInternal(PPCIBUS pBus, int iDev, PPCIDEVICE pPciDev, const char *pszName);
182	static void ich9pciUpdateMappings(PCIDevice *pDev);
183	static DECLCALLBACK(uint32_t) ich9pciConfigReadDev(PCIDevice *aDev, uint32_t u32Address, unsigned len);
184	DECLINLINE(PPCIDEVICE) ich9pciFindBridge(PPCIBUS pBus, uint8_t iBus);
185	static void ich9pciBiosInitDevice(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint8_t cBridgeDepth, uint8_t *paBridgePositions);
186	#endif
187
188	// See 7.2.2. PCI Express Enhanced Configuration Mechanism for details of address
189	// mapping, we take n=6 approach
190	DECLINLINE(void) ich9pciPhysToPciAddr(PPCIGLOBALS pGlobals, RTGCPHYS GCPhysAddr, PciAddress* pPciAddr)
191	{
192	pPciAddr->iBus = (GCPhysAddr >> 20) & ((1<<6) - 1);
193	pPciAddr->iDeviceFunc = (GCPhysAddr >> 12) & ((1<<(5+3)) - 1); // 5 bits - device, 3 bits - function
194	pPciAddr->iRegister = (GCPhysAddr >> 0) & ((1<<(6+4+2)) - 1); // 6 bits - register, 4 bits - extended register, 2 bits -Byte Enable
195	}
196
197	DECLINLINE(void) ich9pciStateToPciAddr(PPCIGLOBALS pGlobals, RTGCPHYS addr, PciAddress* pPciAddr)
198	{
199	pPciAddr->iBus = (pGlobals->uConfigReg >> 16) & 0xff;
200	pPciAddr->iDeviceFunc = (pGlobals->uConfigReg >> 8) & 0xff;
201	pPciAddr->iRegister = (pGlobals->uConfigReg & 0xfc) \| (addr & 3);
202	}
203
204	PDMBOTHCBDECL(void) ich9pciSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel)
205	{
206	ich9pciSetIrqInternal(PDMINS_2_DATA(pDevIns, PPCIGLOBALS), pPciDev->devfn, pPciDev, iIrq, iLevel);
207	}
208
209	PDMBOTHCBDECL(void) ich9pcibridgeSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel)
210	{
211	/*
212	* The PCI-to-PCI bridge specification defines how the interrupt pins
213	* are routed from the secondary to the primary bus (see chapter 9).
214	* iIrq gives the interrupt pin the pci device asserted.
215	* We change iIrq here according to the spec and call the SetIrq function
216	* of our parent passing the device which asserted the interrupt instead of the device of the bridge.
217	*/
218	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
219	PPCIDEVICE pPciDevBus = pPciDev;
220	int iIrqPinBridge = iIrq;
221	uint8_t uDevFnBridge = 0;
222
223	/* Walk the chain until we reach the host bus. */
224	do
225	{
226	uDevFnBridge = pBus->aPciDev.devfn;
227	iIrqPinBridge = ((pPciDevBus->devfn >> 3) + iIrqPinBridge) & 3;
228
229	/* Get the parent. */
230	pBus = pBus->aPciDev.Int.s.CTX_SUFF(pBus);
231	pPciDevBus = &pBus->aPciDev;
232	} while (pBus->iBus != 0);
233
234	AssertMsgReturnVoid(pBus->iBus == 0, ("This is not the host pci bus iBus=%d\n", pBus->iBus));
235	ich9pciSetIrqInternal(PCIROOTBUS_2_PCIGLOBALS(pBus), uDevFnBridge, pPciDev, iIrqPinBridge, iLevel);
236	}
237
238	/**
239	* Port I/O Handler for PCI address OUT operations.
240	*
241	* @returns VBox status code.
242	*
243	* @param pDevIns The device instance.
244	* @param pvUser User argument - ignored.
245	* @param uPort Port number used for the OUT operation.
246	* @param u32 The value to output.
247	* @param cb The value size in bytes.
248	*/
249	PDMBOTHCBDECL(int) ich9pciIOPortAddressWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
250	{
251	Log(("ich9pciIOPortAddressWrite: Port=%#x u32=%#x cb=%d\n", Port, u32, cb));
252	NOREF(pvUser);
253	if (cb == 4)
254	{
255	PPCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
256
257	PCI_LOCK(pDevIns, VINF_IOM_HC_IOPORT_WRITE);
258	pThis->uConfigReg = u32 & ~3; /* Bits 0-1 are reserved and we silently clear them */
259	PCI_UNLOCK(pDevIns);
260	}
261
262	return VINF_SUCCESS;
263	}
264
265	/**
266	* Port I/O Handler for PCI address IN operations.
267	*
268	* @returns VBox status code.
269	*
270	* @param pDevIns The device instance.
271	* @param pvUser User argument - ignored.
272	* @param uPort Port number used for the IN operation.
273	* @param pu32 Where to store the result.
274	* @param cb Number of bytes read.
275	*/
276	PDMBOTHCBDECL(int) ich9pciIOPortAddressRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
277	{
278	NOREF(pvUser);
279	if (cb == 4)
280	{
281	PPCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
282	PCI_LOCK(pDevIns, VINF_IOM_HC_IOPORT_READ);
283	*pu32 = pThis->uConfigReg;
284	PCI_UNLOCK(pDevIns);
285	Log(("pciIOPortAddressRead: Port=%#x cb=%d -> %#x\n", Port, cb, *pu32));
286	return VINF_SUCCESS;
287	}
288
289	Log(("ich9pciIOPortAddressRead: Port=%#x cb=%d VERR_IOM_IOPORT_UNUSED\n", Port, cb));
290
291	return VERR_IOM_IOPORT_UNUSED;
292	}
293
294	static int ich9pciDataWriteAddr(PPCIGLOBALS pGlobals, PciAddress* pAddr,
295	uint32_t val, int cb, int rcReschedule)
296	{
297	int rc = VINF_SUCCESS;
298
299	if (pAddr->iRegister > 0xff)
300	{
301	LogRel(("PCI: attempt to write extended register: %x (%d) <- val\n", pAddr->iRegister, cb, val));
302	goto out;
303	}
304
305	if (pAddr->iBus != 0)
306	{
307	if (pGlobals->aPciBus.cBridges)
308	{
309	#ifdef IN_RING3 /** @todo do lookup in R0/RC too! */
310	PPCIDEVICE pBridgeDevice = ich9pciFindBridge(&pGlobals->aPciBus, pAddr->iBus);
311	if (pBridgeDevice)
312	{
313	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigWrite);
314	pBridgeDevice->Int.s.pfnBridgeConfigWrite(pBridgeDevice->pDevIns, pAddr->iBus, pAddr->iDeviceFunc, pAddr->iRegister, val, cb);
315	}
316	else
317	{
318	// do nothing, bridge not found
319	}
320	#else
321	rc = rcReschedule;
322	goto out;
323	#endif
324	}
325	}
326	else
327	{
328	if (pGlobals->aPciBus.apDevices[pAddr->iDeviceFunc])
329	{
330	#ifdef IN_RING3
331	R3PTRTYPE(PCIDevice *) aDev = pGlobals->aPciBus.apDevices[pAddr->iDeviceFunc];
332	Log(("ich9pciConfigWrite: %s: addr=%02x val=%08x len=%d\n", aDev->name, pAddr->iRegister, val, cb));
333	aDev->Int.s.pfnConfigWrite(aDev, pAddr->iRegister, val, cb);
334	#else
335	rc = rcReschedule;
336	goto out;
337	#endif
338	}
339	}
340
341	out:
342	Log2(("ich9pciDataWriteAddr: %02x:%02x:%02x reg %x(%d) %x %Rrc\n",
343	pAddr->iBus, pAddr->iDeviceFunc >> 3, pAddr->iDeviceFunc & 0x7, pAddr->iRegister,
344	cb, val, rc));
345
346	return rc;
347	}
348
349	static int ich9pciDataWrite(PPCIGLOBALS pGlobals, uint32_t addr, uint32_t val, int len)
350	{
351	PciAddress aPciAddr;
352
353	LogFlow(("ich9pciDataWrite: config=%08x val=%08x len=%d\n", pGlobals->uConfigReg, val, len));
354
355	if (!(pGlobals->uConfigReg & (1 << 31)))
356	return VINF_SUCCESS;
357
358	if ((pGlobals->uConfigReg & 0x3) != 0)
359	return VINF_SUCCESS;
360
361	/* Compute destination device */
362	ich9pciStateToPciAddr(pGlobals, addr, &aPciAddr);
363
364	return ich9pciDataWriteAddr(pGlobals, &aPciAddr, val, len, VINF_IOM_HC_IOPORT_WRITE);
365	}
366
367	static void ich9pciNoMem(void* ptr, int cb)
368	{
369	for (int i = 0; i < cb; i++)
370	((uint8_t*)ptr)[i] = 0xff;
371	}
372
373	/**
374	* Port I/O Handler for PCI data OUT operations.
375	*
376	* @returns VBox status code.
377	*
378	* @param pDevIns The device instance.
379	* @param pvUser User argument - ignored.
380	* @param uPort Port number used for the OUT operation.
381	* @param u32 The value to output.
382	* @param cb The value size in bytes.
383	*/
384	PDMBOTHCBDECL(int) ich9pciIOPortDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
385	{
386	Log(("pciIOPortDataWrite: Port=%#x u32=%#x cb=%d\n", Port, u32, cb));
387	NOREF(pvUser);
388	int rc = VINF_SUCCESS;
389	if (!(Port % cb))
390	{
391	PCI_LOCK(pDevIns, VINF_IOM_HC_IOPORT_WRITE);
392	rc = ich9pciDataWrite(PDMINS_2_DATA(pDevIns, PPCIGLOBALS), Port, u32, cb);
393	PCI_UNLOCK(pDevIns);
394	}
395	else
396	AssertMsgFailed(("Unaligned write to port %#x u32=%#x cb=%d\n", Port, u32, cb));
397	return rc;
398	}
399
400	static int ich9pciDataReadAddr(PPCIGLOBALS pGlobals, PciAddress* pPciAddr, int cb,
401	uint32_t *pu32, int rcReschedule)
402	{
403	int rc = VINF_SUCCESS;
404
405	if (pPciAddr->iRegister > 0xff)
406	{
407	LogRel(("PCI: attempt to read extended register: %x\n", pPciAddr->iRegister));
408	ich9pciNoMem(pu32, cb);
409	goto out;
410	}
411
412
413	if (pPciAddr->iBus != 0)
414	{
415	if (pGlobals->aPciBus.cBridges)
416	{
417	#ifdef IN_RING3 /** @todo do lookup in R0/RC too! */
418	PPCIDEVICE pBridgeDevice = ich9pciFindBridge(&pGlobals->aPciBus, pPciAddr->iBus);
419	if (pBridgeDevice)
420	{
421	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigRead);
422	*pu32 = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->pDevIns, pPciAddr->iBus, pPciAddr->iDeviceFunc, pPciAddr->iRegister, cb);
423	}
424	else
425	ich9pciNoMem(pu32, cb);
426	#else
427	rc = rcReschedule;
428	goto out;
429	#endif
430	} else
431	ich9pciNoMem(pu32, cb);
432	}
433	else
434	{
435	if (pGlobals->aPciBus.apDevices[pPciAddr->iDeviceFunc])
436	{
437	#ifdef IN_RING3
438	R3PTRTYPE(PCIDevice *) aDev = pGlobals->aPciBus.apDevices[pPciAddr->iDeviceFunc];
439	*pu32 = aDev->Int.s.pfnConfigRead(aDev, pPciAddr->iRegister, cb);
440	Log(("ich9pciDataReadAddr: %s: addr=%02x val=%08x len=%d\n", aDev->name, pPciAddr->iRegister, *pu32, cb));
441	#else
442	rc = rcReschedule;
443	goto out;
444	#endif
445	}
446	else
447	ich9pciNoMem(pu32, cb);
448	}
449
450	out:
451	Log2(("ich9pciDataReadAddr: %02x:%02x:%02x reg %x(%d) gave %x %Rrc\n",
452	pPciAddr->iBus, pPciAddr->iDeviceFunc >> 3, pPciAddr->iDeviceFunc & 0x7, pPciAddr->iRegister,
453	cb, *pu32, rc));
454
455	return rc;
456	}
457
458	static int ich9pciDataRead(PPCIGLOBALS pGlobals, uint32_t addr, int cb, uint32_t *pu32)
459	{
460	PciAddress aPciAddr;
461
462	LogFlow(("ich9pciDataRead: config=%x cb=%d\n", pGlobals->uConfigReg, cb));
463
464	*pu32 = 0xffffffff;
465
466	if (!(pGlobals->uConfigReg & (1 << 31)))
467	return VINF_SUCCESS;
468
469	if ((pGlobals->uConfigReg & 0x3) != 0)
470	return VINF_SUCCESS;
471
472	/* Compute destination device */
473	ich9pciStateToPciAddr(pGlobals, addr, &aPciAddr);
474
475	return ich9pciDataReadAddr(pGlobals, &aPciAddr, cb, pu32, VINF_IOM_HC_IOPORT_READ);
476	}
477
478	/**
479	* Port I/O Handler for PCI data IN operations.
480	*
481	* @returns VBox status code.
482	*
483	* @param pDevIns The device instance.
484	* @param pvUser User argument - ignored.
485	* @param uPort Port number used for the IN operation.
486	* @param pu32 Where to store the result.
487	* @param cb Number of bytes read.
488	*/
489	PDMBOTHCBDECL(int) ich9pciIOPortDataRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
490	{
491	NOREF(pvUser);
492	if (!(Port % cb))
493	{
494	PCI_LOCK(pDevIns, VINF_IOM_HC_IOPORT_READ);
495	int rc = ich9pciDataRead(PDMINS_2_DATA(pDevIns, PPCIGLOBALS), Port, cb, pu32);
496	PCI_UNLOCK(pDevIns);
497	Log(("pciIOPortDataRead: Port=%#x cb=%#x -> %#x (%Rrc)\n", Port, cb, *pu32, rc));
498	return rc;
499	}
500	AssertMsgFailed(("Unaligned read from port %#x cb=%d\n", Port, cb));
501	return VERR_IOM_IOPORT_UNUSED;
502	}
503
504	/* Compute mapping of PCI slot and IRQ number to APIC interrupt line */
505	DECLINLINE(int) ich9pciSlot2ApicIrq(uint8_t uSlot, int irq_num)
506	{
507	return (irq_num + uSlot) & 7;
508	}
509
510	/* return the global irq number corresponding to a given device irq
511	pin. We could also use the bus number to have a more precise
512	mapping. This is the implementation note described in the PCI spec chapter 2.2.6 */
513	DECLINLINE(int) ich9pciSlotGetPirq(uint8_t uBus, uint8_t uDevFn, int iIrqNum)
514	{
515	int iSlotAddend = (uDevFn >> 3) - 1;
516	return (iIrqNum + iSlotAddend) & 3;
517	}
518
519	/* irqs corresponding to PCI irqs A-D */
520	static const uint8_t aPciIrqs[4] = { 11, 9, 11, 9 };
521
522	/* Add one more level up request on APIC input line */
523	DECLINLINE(void) ich9pciApicLevelUp(PPCIGLOBALS pGlobals, int irq_num)
524	{
525	ASMAtomicIncU32(&pGlobals->uaPciApicIrqLevels[irq_num]);
526	}
527
528	/* Remove one level up request on APIC input line */
529	DECLINLINE(void) ich9pciApicLevelDown(PPCIGLOBALS pGlobals, int irq_num)
530	{
531	ASMAtomicDecU32(&pGlobals->uaPciApicIrqLevels[irq_num]);
532	}
533
534	static void ich9pciApicSetIrq(PPCIBUS pBus, uint8_t uDevFn, PCIDevice *pPciDev, int irq_num1, int iLevel, int iForcedIrq)
535	{
536	/* This is only allowed to be called with a pointer to the root bus. */
537	AssertMsg(pBus->iBus == 0, ("iBus=%u\n", pBus->iBus));
538
539	if (iForcedIrq == -1)
540	{
541	int apic_irq, apic_level;
542	PPCIGLOBALS pGlobals = PCIROOTBUS_2_PCIGLOBALS(pBus);
543	int irq_num = ich9pciSlot2ApicIrq(uDevFn >> 3, irq_num1);
544
545	if ((iLevel & PDM_IRQ_LEVEL_HIGH) == PDM_IRQ_LEVEL_HIGH)
546	ich9pciApicLevelUp(pGlobals, irq_num);
547	else if ((iLevel & PDM_IRQ_LEVEL_HIGH) == PDM_IRQ_LEVEL_LOW)
548	ich9pciApicLevelDown(pGlobals, irq_num);
549
550	apic_irq = irq_num + 0x10;
551	apic_level = pGlobals->uaPciApicIrqLevels[irq_num] != 0;
552	Log3(("ich9pciApicSetIrq: %s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d\n",
553	R3STRING(pPciDev->name), irq_num1, iLevel, apic_irq, apic_level, irq_num));
554	pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), apic_irq, apic_level);
555
556	if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP)
557	{
558	/**
559	* we raised it few lines above, as PDM_IRQ_LEVEL_FLIP_FLOP has
560	* PDM_IRQ_LEVEL_HIGH bit set
561	*/
562	ich9pciApicLevelDown(pGlobals, irq_num);
563	pPciDev->Int.s.uIrqPinState = PDM_IRQ_LEVEL_LOW;
564	apic_level = pGlobals->uaPciApicIrqLevels[irq_num] != 0;
565	Log3(("ich9pciApicSetIrq: %s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d (flop)\n",
566	R3STRING(pPciDev->name), irq_num1, iLevel, apic_irq, apic_level, irq_num));
567	pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), apic_irq, apic_level);
568	}
569	} else {
570	Log3(("ich9pciApicSetIrq: (forced) %s: irq_num1=%d level=%d acpi_irq=%d\n",
571	R3STRING(pPciDev->name), irq_num1, iLevel, iForcedIrq));
572	pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), iForcedIrq, iLevel);
573	}
574	}
575
576	static void ich9pciSetIrqInternal(PPCIGLOBALS pGlobals, uint8_t uDevFn, PPCIDEVICE pPciDev, int iIrq, int iLevel)
577	{
578
579	if (PCIDevIsIntxDisabled(pPciDev))
580	{
581	if (MsiIsEnabled(pPciDev))
582	{
583	PPDMDEVINS pDevIns = pGlobals->aPciBus.CTX_SUFF(pDevIns);
584	MsiNotify(pDevIns, pGlobals->aPciBus.CTX_SUFF(pPciHlp), pPciDev, iIrq, iLevel);
585	}
586
587	if (MsixIsEnabled(pPciDev))
588	{
589	PPDMDEVINS pDevIns = pGlobals->aPciBus.CTX_SUFF(pDevIns);
590	MsixNotify(pDevIns, pGlobals->aPciBus.CTX_SUFF(pPciHlp), pPciDev, iIrq, iLevel);
591	}
592	return;
593	}
594
595	PPCIBUS pBus = &pGlobals->aPciBus;
596	const bool fIsAcpiDevice = PCIDevGetDeviceId(pPciDev) == 0x7113;
597
598	/* Check if the state changed. */
599	if (pPciDev->Int.s.uIrqPinState != iLevel)
600	{
601	pPciDev->Int.s.uIrqPinState = (iLevel & PDM_IRQ_LEVEL_HIGH);
602
603	/* Send interrupt to I/O APIC only now. */
604	if (fIsAcpiDevice)
605	/*
606	* ACPI needs special treatment since SCI is hardwired and
607	* should not be affected by PCI IRQ routing tables at the
608	* same time SCI IRQ is shared in PCI sense hence this
609	* kludge (i.e. we fetch the hardwired value from ACPIs
610	* PCI device configuration space).
611	*/
612	ich9pciApicSetIrq(pBus, uDevFn, pPciDev, -1, iLevel, PCIDevGetInterruptLine(pPciDev));
613	else
614	ich9pciApicSetIrq(pBus, uDevFn, pPciDev, iIrq, iLevel, -1);
615	}
616	}
617
618	PDMBOTHCBDECL(int) ich9pciMcfgMMIOWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb)
619	{
620	PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
621	PciAddress aDest;
622	uint32_t u32 = 0;
623
624	Log2(("ich9pciMcfgMMIOWrite: %RGp(%d) \n", GCPhysAddr, cb));
625
626	PCI_LOCK(pDevIns, VINF_IOM_HC_MMIO_WRITE);
627
628	ich9pciPhysToPciAddr(pGlobals, GCPhysAddr, &aDest);
629
630	switch (cb)
631	{
632	case 1:
633	u32 = (uint8_t)pv;
634	break;
635	case 2:
636	u32 = (uint16_t)pv;
637	break;
638	case 4:
639	u32 = (uint32_t)pv;
640	break;
641	default:
642	Assert(false);
643	break;
644	}
645	int rc = ich9pciDataWriteAddr(pGlobals, &aDest, u32, cb, VINF_IOM_HC_MMIO_WRITE);
646	PCI_UNLOCK(pDevIns);
647
648	return rc;
649	}
650
651	PDMBOTHCBDECL(int) ich9pciMcfgMMIORead (PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb)
652	{
653	PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
654	PciAddress aDest;
655	uint32_t rv;
656
657	LogFlow(("ich9pciMcfgMMIORead: %RGp(%d) \n", GCPhysAddr, cb));
658
659	PCI_LOCK(pDevIns, VINF_IOM_HC_MMIO_READ);
660
661	ich9pciPhysToPciAddr(pGlobals, GCPhysAddr, &aDest);
662
663	int rc = ich9pciDataReadAddr(pGlobals, &aDest, cb, &rv, VINF_IOM_HC_MMIO_READ);
664
665	if (RT_SUCCESS(rc))
666	{
667	switch (cb)
668	{
669	case 1:
670	(uint8_t)pv = (uint8_t)rv;
671	break;
672	case 2:
673	(uint16_t)pv = (uint16_t)rv;
674	break;
675	case 4:
676	(uint32_t)pv = (uint32_t)rv;
677	break;
678	default:
679	Assert(false);
680	break;
681	}
682	}
683	PCI_UNLOCK(pDevIns);
684
685	return rc;
686	}
687
688	#ifdef IN_RING3
689
690	DECLINLINE(PPCIDEVICE) ich9pciFindBridge(PPCIBUS pBus, uint8_t iBus)
691	{
692	/* Search for a fitting bridge. */
693	for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
694	{
695	/*
696	* Examine secondary and subordinate bus number.
697	* If the target bus is in the range we pass the request on to the bridge.
698	*/
699	PPCIDEVICE pBridgeTemp = pBus->papBridgesR3[iBridge];
700	AssertMsg(pBridgeTemp && PCIIsPci2PciBridge(pBridgeTemp),
701	("Device is not a PCI bridge but on the list of PCI bridges\n"));
702
703	if ( iBus >= PCIDevGetByte(pBridgeTemp, VBOX_PCI_SECONDARY_BUS)
704	&& iBus <= PCIDevGetByte(pBridgeTemp, VBOX_PCI_SUBORDINATE_BUS))
705	return pBridgeTemp;
706	}
707
708	/* Nothing found. */
709	return NULL;
710	}
711
712	DECLINLINE(uint32_t) ich9pciGetRegionReg(int iRegion)
713	{
714	return (iRegion == VBOX_PCI_ROM_SLOT) ?
715	VBOX_PCI_ROM_ADDRESS : (VBOX_PCI_BASE_ADDRESS_0 + iRegion * 4);
716	}
717
718	#define INVALID_PCI_ADDRESS ~0U
719
720	static void ich9pciUpdateMappings(PCIDevice* pDev)
721	{
722	PPCIBUS pBus = pDev->Int.s.CTX_SUFF(pBus);
723	uint32_t uLast, uNew;
724
725	int iCmd = PCIDevGetCommand(pDev);
726	for (int iRegion = 0; iRegion < PCI_NUM_REGIONS; iRegion++)
727	{
728	PCIIORegion* pRegion = &pDev->Int.s.aIORegions[iRegion];
729	uint32_t uConfigReg = ich9pciGetRegionReg(iRegion);
730	int32_t iRegionSize = pRegion->size;
731	int rc;
732
733	if (iRegionSize == 0)
734	continue;
735
736	AssertMsg((pRegion->type & PCI_ADDRESS_SPACE_BAR64) == 0, ("64-bit BARs not yet implemented\n"));
737
738	if (pRegion->type & PCI_ADDRESS_SPACE_IO)
739	{
740	/* port IO region */
741	if (iCmd & PCI_COMMAND_IOACCESS)
742	{
743	/* IO access allowed */
744	uNew = ich9pciConfigReadDev(pDev, uConfigReg, 4);
745	uNew &= ~(iRegionSize - 1);
746	uLast = uNew + iRegionSize - 1;
747	/* only 64K ioports on PC */
748	if (uLast <= uNew \|\| uNew == 0 \|\| uLast >= 0x10000)
749	uNew = INVALID_PCI_ADDRESS;
750	} else
751	uNew = INVALID_PCI_ADDRESS;
752	}
753	else
754	{
755	/* MMIO region */
756	if (iCmd & PCI_COMMAND_MEMACCESS)
757	{
758	uNew = ich9pciConfigReadDev(pDev, uConfigReg, 4);
759	/* the ROM slot has a specific enable bit */
760	if (iRegion == PCI_ROM_SLOT && !(uNew & 1))
761	uNew = INVALID_PCI_ADDRESS;
762	else
763	{
764	uNew &= ~(iRegionSize - 1);
765	uLast = uNew + iRegionSize - 1;
766	/* NOTE: we do not support wrapping */
767	/* XXX: as we cannot support really dynamic
768	mappings, we handle specific values as invalid
769	mappings. */
770	if (uLast <= uNew \|\| uNew == 0 \|\| uLast == INVALID_PCI_ADDRESS)
771	uNew = INVALID_PCI_ADDRESS;
772	}
773	} else
774	uNew = INVALID_PCI_ADDRESS;
775	}
776	/* now do the real mapping */
777	if (uNew != pRegion->addr)
778	{
779	if (pRegion->addr != INVALID_PCI_ADDRESS)
780	{
781	if (pRegion->type & PCI_ADDRESS_SPACE_IO)
782	{
783	/* Port IO */
784	rc = PDMDevHlpIOPortDeregister(pDev->pDevIns, pRegion->addr, pRegion->size);
785	AssertRC(rc);
786	}
787	else
788	{
789	RTGCPHYS GCPhysBase = pRegion->addr;
790	if (pBus->pPciHlpR3->pfnIsMMIO2Base(pBus->pDevInsR3, pDev->pDevIns, GCPhysBase))
791	{
792	/* unmap it. */
793	rc = pRegion->map_func(pDev, iRegion, NIL_RTGCPHYS, pRegion->size, (PCIADDRESSSPACE)(pRegion->type));
794	AssertRC(rc);
795	rc = PDMDevHlpMMIO2Unmap(pDev->pDevIns, iRegion, GCPhysBase);
796	}
797	else
798	rc = PDMDevHlpMMIODeregister(pDev->pDevIns, GCPhysBase, pRegion->size);
799	AssertMsgRC(rc, ("rc=%Rrc d=%s i=%d GCPhysBase=%RGp size=%#x\n", rc, pDev->name, iRegion, GCPhysBase, pRegion->size));
800	}
801	}
802	pRegion->addr = uNew;
803	if (pRegion->addr != INVALID_PCI_ADDRESS)
804	{
805	/* finally, map the region */
806	rc = pRegion->map_func(pDev, iRegion,
807	pRegion->addr, pRegion->size,
808	(PCIADDRESSSPACE)(pRegion->type));
809	AssertRC(rc);
810	}
811	}
812	}
813	}
814
815	static DECLCALLBACK(int) ich9pciRegister(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, const char *pszName, int iDev)
816	{
817	PPCIBUS pBus = DEVINS_2_PCIBUS(pDevIns);
818
819	/*
820	* Check input.
821	*/
822	if ( !pszName
823	\|\| !pPciDev
824	\|\| iDev >= (int)RT_ELEMENTS(pBus->apDevices)
825	)
826	{
827	AssertMsgFailed(("Invalid argument! pszName=%s pPciDev=%p iDev=%d\n", pszName, pPciDev, iDev));
828	return VERR_INVALID_PARAMETER;
829	}
830
831	/*
832	* Register the device.
833	*/
834	return ich9pciRegisterInternal(pBus, iDev, pPciDev, pszName);
835	}
836
837
838	static DECLCALLBACK(int) ich9pciRegisterMsi(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PPDMMSIREG pMsiReg)
839	{
840	int rc;
841
842	rc = MsiInit(pPciDev, pMsiReg);
843	if (rc != VINF_SUCCESS)
844	return rc;
845
846	rc = MsixInit(pPciDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pPciHlp), pPciDev, pMsiReg);
847	if (rc != VINF_SUCCESS)
848	return rc;
849
850	return rc;
851	}
852
853
854	static DECLCALLBACK(int) ich9pcibridgeRegister(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, const char *pszName, int iDev)
855	{
856
857	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
858
859	/*
860	* Check input.
861	*/
862	if ( !pszName
863	\|\| !pPciDev
864	\|\| iDev >= (int)RT_ELEMENTS(pBus->apDevices))
865	{
866	AssertMsgFailed(("Invalid argument! pszName=%s pPciDev=%p iDev=%d\n", pszName, pPciDev, iDev));
867	return VERR_INVALID_PARAMETER;
868	}
869
870	/*
871	* Register the device.
872	*/
873	return ich9pciRegisterInternal(pBus, iDev, pPciDev, pszName);
874	}
875
876	static DECLCALLBACK(int) ich9pciIORegionRegister(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iRegion, uint32_t cbRegion, PCIADDRESSSPACE enmType, PFNPCIIOREGIONMAP pfnCallback)
877	{
878	/*
879	* Validate.
880	*/
881	AssertMsgReturn( enmType == PCI_ADDRESS_SPACE_MEM
882	\|\| enmType == PCI_ADDRESS_SPACE_IO
883	\|\| enmType == PCI_ADDRESS_SPACE_MEM_PREFETCH,
884	("Invalid enmType=%#x? Or was this a bitmask after all...\n", enmType),
885	VERR_INVALID_PARAMETER);
886	AssertMsgReturn((unsigned)iRegion < PCI_NUM_REGIONS,
887	("Invalid iRegion=%d PCI_NUM_REGIONS=%d\n", iRegion, PCI_NUM_REGIONS),
888	VERR_INVALID_PARAMETER);
889	int iLastSet = ASMBitLastSetU32(cbRegion);
890	AssertMsgReturn( iLastSet != 0
891	&& RT_BIT_32(iLastSet - 1) == cbRegion,
892	("Invalid cbRegion=%#x iLastSet=%#x (not a power of 2 or 0)\n", cbRegion, iLastSet),
893	VERR_INVALID_PARAMETER);
894
895	/*
896	* Register the I/O region.
897	*/
898	PPCIIOREGION pRegion = &pPciDev->Int.s.aIORegions[iRegion];
899	pRegion->addr = INVALID_PCI_ADDRESS;
900	pRegion->size = cbRegion;
901	pRegion->type = enmType;
902	pRegion->map_func = pfnCallback;
903
904	/* Set type in the config space. */
905	uint32_t u32Address = ich9pciGetRegionReg(iRegion);
906	uint32_t u32Value = (enmType == PCI_ADDRESS_SPACE_MEM_PREFETCH ? (1 << 3) : 0)
907	\| (enmType == PCI_ADDRESS_SPACE_IO ? 1 : 0);
908	PCIDevSetDWord(pPciDev, u32Address, u32Value);
909
910	return VINF_SUCCESS;
911	}
912
913	static DECLCALLBACK(void) ich9pciSetConfigCallbacks(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PFNPCICONFIGREAD pfnRead, PPFNPCICONFIGREAD ppfnReadOld,
914	PFNPCICONFIGWRITE pfnWrite, PPFNPCICONFIGWRITE ppfnWriteOld)
915	{
916	if (ppfnReadOld)
917	*ppfnReadOld = pPciDev->Int.s.pfnConfigRead;
918	pPciDev->Int.s.pfnConfigRead = pfnRead;
919
920	if (ppfnWriteOld)
921	*ppfnWriteOld = pPciDev->Int.s.pfnConfigWrite;
922	pPciDev->Int.s.pfnConfigWrite = pfnWrite;
923	}
924
925	/**
926	* Saves a state of the PCI device.
927	*
928	* @returns VBox status code.
929	* @param pDevIns Device instance of the PCI Bus.
930	* @param pPciDev Pointer to PCI device.
931	* @param pSSM The handle to save the state to.
932	*/
933	static DECLCALLBACK(int) ich9pciGenericSaveExec(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PSSMHANDLE pSSM)
934	{
935	return SSMR3PutMem(pSSM, &pPciDev->config[0], sizeof(pPciDev->config));
936	}
937
938	static int ich9pciR3CommonSaveExec(PPCIBUS pBus, PSSMHANDLE pSSM)
939	{
940	/*
941	* Iterate thru all the devices.
942	*/
943	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
944	{
945	PPCIDEVICE pDev = pBus->apDevices[i];
946	if (pDev)
947	{
948	/* Device position */
949	SSMR3PutU32(pSSM, i);
950	/* PCI config registers */
951	SSMR3PutMem(pSSM, pDev->config, sizeof(pDev->config));
952
953	/* Device flags */
954	int rc = SSMR3PutU32(pSSM, pDev->Int.s.uFlags);
955	if (RT_FAILURE(rc))
956	return rc;
957
958	/* IRQ pin state */
959	rc = SSMR3PutS32(pSSM, pDev->Int.s.uIrqPinState);
960	if (RT_FAILURE(rc))
961	return rc;
962
963	/* MSI info */
964	rc = SSMR3PutU8(pSSM, pDev->Int.s.u8MsiCapOffset);
965	if (RT_FAILURE(rc))
966	return rc;
967	rc = SSMR3PutU8(pSSM, pDev->Int.s.u8MsiCapSize);
968	if (RT_FAILURE(rc))
969	return rc;
970
971	/* MSI-X info */
972	rc = SSMR3PutU8(pSSM, pDev->Int.s.u8MsixCapOffset);
973	if (RT_FAILURE(rc))
974	return rc;
975	rc = SSMR3PutU8(pSSM, pDev->Int.s.u8MsixCapSize);
976	if (RT_FAILURE(rc))
977	return rc;
978	/* Save MSI-X page state */
979	if (pDev->Int.s.u8MsixCapOffset != 0)
980	{
981	Assert(pDev->Int.s.pMsixPageR3 != NULL);
982	SSMR3PutMem(pSSM, pDev->Int.s.pMsixPageR3, 0x1000);
983	if (RT_FAILURE(rc))
984	return rc;
985	}
986	}
987	}
988	return SSMR3PutU32(pSSM, UINT32_MAX); /* terminator */
989	}
990
991	static DECLCALLBACK(int) ich9pciR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
992	{
993	PPCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
994
995	/*
996	* Bus state data.
997	*/
998	SSMR3PutU32(pSSM, pThis->uConfigReg);
999
1000	/*
1001	* Save IRQ states.
1002	*/
1003	for (int i = 0; i < PCI_APIC_IRQ_PINS; i++)
1004	SSMR3PutU32(pSSM, pThis->uaPciApicIrqLevels[i]);
1005
1006	SSMR3PutU32(pSSM, ~0); /* separator */
1007
1008	return ich9pciR3CommonSaveExec(&pThis->aPciBus, pSSM);
1009	}
1010
1011
1012	static DECLCALLBACK(int) ich9pcibridgeR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
1013	{
1014	PPCIBUS pThis = PDMINS_2_DATA(pDevIns, PPCIBUS);
1015	return ich9pciR3CommonSaveExec(pThis, pSSM);
1016	}
1017
1018
1019	static void ich9pcibridgeConfigWrite(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice, uint32_t u32Address, uint32_t u32Value, unsigned cb)
1020	{
1021	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
1022
1023	LogFlowFunc((": pDevIns=%p iBus=%d iDevice=%d u32Address=%u u32Value=%u cb=%d\n", pDevIns, iBus, iDevice, u32Address, u32Value, cb));
1024
1025	/* If the current bus is not the target bus search for the bus which contains the device. */
1026	if (iBus != PCIDevGetByte(&pBus->aPciDev, VBOX_PCI_SECONDARY_BUS))
1027	{
1028	PPCIDEVICE pBridgeDevice = ich9pciFindBridge(pBus, iBus);
1029	if (pBridgeDevice)
1030	{
1031	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigWrite);
1032	pBridgeDevice->Int.s.pfnBridgeConfigWrite(pBridgeDevice->pDevIns, iBus, iDevice, u32Address, u32Value, cb);
1033	}
1034	}
1035	else
1036	{
1037	/* This is the target bus, pass the write to the device. */
1038	PPCIDEVICE pPciDev = pBus->apDevices[iDevice];
1039	if (pPciDev)
1040	{
1041	Log(("%s: %s: addr=%02x val=%08x len=%d\n", __FUNCTION__, pPciDev->name, u32Address, u32Value, cb));
1042	pPciDev->Int.s.pfnConfigWrite(pPciDev, u32Address, u32Value, cb);
1043	}
1044	}
1045	}
1046
1047	static uint32_t ich9pcibridgeConfigRead(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice, uint32_t u32Address, unsigned cb)
1048	{
1049	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
1050	uint32_t u32Value;
1051
1052	LogFlowFunc((": pDevIns=%p iBus=%d iDevice=%d u32Address=%u cb=%d\n", pDevIns, iBus, iDevice, u32Address, cb));
1053
1054	/* If the current bus is not the target bus search for the bus which contains the device. */
1055	if (iBus != PCIDevGetByte(&pBus->aPciDev, VBOX_PCI_SECONDARY_BUS))
1056	{
1057	PPCIDEVICE pBridgeDevice = ich9pciFindBridge(pBus, iBus);
1058	if (pBridgeDevice)
1059	{
1060	AssertPtr( pBridgeDevice->Int.s.pfnBridgeConfigRead);
1061	u32Value = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->pDevIns, iBus, iDevice, u32Address, cb);
1062	}
1063	else
1064	ich9pciNoMem(&u32Value, 4);
1065	}
1066	else
1067	{
1068	/* This is the target bus, pass the read to the device. */
1069	PPCIDEVICE pPciDev = pBus->apDevices[iDevice];
1070	if (pPciDev)
1071	{
1072	u32Value = pPciDev->Int.s.pfnConfigRead(pPciDev, u32Address, cb);
1073	Log(("%s: %s: u32Address=%02x u32Value=%08x cb=%d\n", __FUNCTION__, pPciDev->name, u32Address, u32Value, cb));
1074	}
1075	else
1076	ich9pciNoMem(&u32Value, 4);
1077	}
1078
1079	return u32Value;
1080	}
1081
1082
1083	/**
1084	* Common routine for restoring the config registers of a PCI device.
1085	*
1086	* @param pDev The PCI device.
1087	* @param pbSrcConfig The configuration register values to be loaded.
1088	* @param fIsBridge Whether this is a bridge device or not.
1089	*/
1090	static void pciR3CommonRestoreConfig(PPCIDEVICE pDev, uint8_t const *pbSrcConfig, bool fIsBridge)
1091	{
1092	/*
1093	* This table defines the fields for normal devices and bridge devices, and
1094	* the order in which they need to be restored.
1095	*/
1096	static const struct PciField
1097	{
1098	uint8_t off;
1099	uint8_t cb;
1100	uint8_t fWritable;
1101	uint8_t fBridge;
1102	const char *pszName;
1103	} s_aFields[] =
1104	{
1105	/* off,cb,fW,fB, pszName */
1106	{ VBOX_PCI_VENDOR_ID, 2, 0, 3, "VENDOR_ID" },
1107	{ VBOX_PCI_DEVICE_ID, 2, 0, 3, "DEVICE_ID" },
1108	{ VBOX_PCI_STATUS, 2, 1, 3, "STATUS" },
1109	{ VBOX_PCI_REVISION_ID, 1, 0, 3, "REVISION_ID" },
1110	{ VBOX_PCI_CLASS_PROG, 1, 0, 3, "CLASS_PROG" },
1111	{ VBOX_PCI_CLASS_SUB, 1, 0, 3, "CLASS_SUB" },
1112	{ VBOX_PCI_CLASS_BASE, 1, 0, 3, "CLASS_BASE" },
1113	{ VBOX_PCI_CACHE_LINE_SIZE, 1, 1, 3, "CACHE_LINE_SIZE" },
1114	{ VBOX_PCI_LATENCY_TIMER, 1, 1, 3, "LATENCY_TIMER" },
1115	{ VBOX_PCI_HEADER_TYPE, 1, 0, 3, "HEADER_TYPE" },
1116	{ VBOX_PCI_BIST, 1, 1, 3, "BIST" },
1117	{ VBOX_PCI_BASE_ADDRESS_0, 4, 1, 3, "BASE_ADDRESS_0" },
1118	{ VBOX_PCI_BASE_ADDRESS_1, 4, 1, 3, "BASE_ADDRESS_1" },
1119	{ VBOX_PCI_BASE_ADDRESS_2, 4, 1, 1, "BASE_ADDRESS_2" },
1120	{ VBOX_PCI_PRIMARY_BUS, 1, 1, 2, "PRIMARY_BUS" }, // fWritable = ??
1121	{ VBOX_PCI_SECONDARY_BUS, 1, 1, 2, "SECONDARY_BUS" }, // fWritable = ??
1122	{ VBOX_PCI_SUBORDINATE_BUS, 1, 1, 2, "SUBORDINATE_BUS" }, // fWritable = ??
1123	{ VBOX_PCI_SEC_LATENCY_TIMER, 1, 1, 2, "SEC_LATENCY_TIMER" }, // fWritable = ??
1124	{ VBOX_PCI_BASE_ADDRESS_3, 4, 1, 1, "BASE_ADDRESS_3" },
1125	{ VBOX_PCI_IO_BASE, 1, 1, 2, "IO_BASE" }, // fWritable = ??
1126	{ VBOX_PCI_IO_LIMIT, 1, 1, 2, "IO_LIMIT" }, // fWritable = ??
1127	{ VBOX_PCI_SEC_STATUS, 2, 1, 2, "SEC_STATUS" }, // fWritable = ??
1128	{ VBOX_PCI_BASE_ADDRESS_4, 4, 1, 1, "BASE_ADDRESS_4" },
1129	{ VBOX_PCI_MEMORY_BASE, 2, 1, 2, "MEMORY_BASE" }, // fWritable = ??
1130	{ VBOX_PCI_MEMORY_LIMIT, 2, 1, 2, "MEMORY_LIMIT" }, // fWritable = ??
1131	{ VBOX_PCI_BASE_ADDRESS_5, 4, 1, 1, "BASE_ADDRESS_5" },
1132	{ VBOX_PCI_PREF_MEMORY_BASE, 2, 1, 2, "PREF_MEMORY_BASE" }, // fWritable = ??
1133	{ VBOX_PCI_PREF_MEMORY_LIMIT, 2, 1, 2, "PREF_MEMORY_LIMIT" }, // fWritable = ??
1134	{ VBOX_PCI_CARDBUS_CIS, 4, 1, 1, "CARDBUS_CIS" }, // fWritable = ??
1135	{ VBOX_PCI_PREF_BASE_UPPER32, 4, 1, 2, "PREF_BASE_UPPER32" }, // fWritable = ??
1136	{ VBOX_PCI_SUBSYSTEM_VENDOR_ID, 2, 0, 1, "SUBSYSTEM_VENDOR_ID" },// fWritable = !?
1137	{ VBOX_PCI_PREF_LIMIT_UPPER32, 4, 1, 2, "PREF_LIMIT_UPPER32" },// fWritable = ??
1138	{ VBOX_PCI_SUBSYSTEM_ID, 2, 0, 1, "SUBSYSTEM_ID" }, // fWritable = !?
1139	{ VBOX_PCI_ROM_ADDRESS, 4, 1, 1, "ROM_ADDRESS" }, // fWritable = ?!
1140	{ VBOX_PCI_IO_BASE_UPPER16, 2, 1, 2, "IO_BASE_UPPER16" }, // fWritable = ?!
1141	{ VBOX_PCI_IO_LIMIT_UPPER16, 2, 1, 2, "IO_LIMIT_UPPER16" }, // fWritable = ?!
1142	{ VBOX_PCI_CAPABILITY_LIST, 4, 0, 3, "CAPABILITY_LIST" }, // fWritable = !? cb=!?
1143	{ VBOX_PCI_RESERVED_38, 4, 1, 1, "RESERVED_38" }, // ???
1144	{ VBOX_PCI_ROM_ADDRESS_BR, 4, 1, 2, "ROM_ADDRESS_BR" }, // fWritable = !? cb=!? fBridge=!?
1145	{ VBOX_PCI_INTERRUPT_LINE, 1, 1, 3, "INTERRUPT_LINE" }, // fBridge=??
1146	{ VBOX_PCI_INTERRUPT_PIN, 1, 0, 3, "INTERRUPT_PIN" }, // fBridge=??
1147	{ VBOX_PCI_MIN_GNT, 1, 0, 1, "MIN_GNT" },
1148	{ VBOX_PCI_BRIDGE_CONTROL, 2, 1, 2, "BRIDGE_CONTROL" }, // fWritable = !?
1149	{ VBOX_PCI_MAX_LAT, 1, 0, 1, "MAX_LAT" },
1150	/* The COMMAND register must come last as it requires the ADDRESS
1151	registers to be restored before we pretent to change it from 0 to
1152	whatever value the guest assigned it. */
1153	{ VBOX_PCI_COMMAND, 2, 1, 3, "COMMAND" },
1154	};
1155
1156	#ifdef RT_STRICT
1157	/* Check that we've got full register coverage. */
1158	uint32_t bmDevice[0x40 / 32];
1159	uint32_t bmBridge[0x40 / 32];
1160	RT_ZERO(bmDevice);
1161	RT_ZERO(bmBridge);
1162	for (uint32_t i = 0; i < RT_ELEMENTS(s_aFields); i++)
1163	{
1164	uint8_t off = s_aFields[i].off;
1165	uint8_t cb = s_aFields[i].cb;
1166	uint8_t f = s_aFields[i].fBridge;
1167	while (cb-- > 0)
1168	{
1169	if (f & 1) AssertMsg(!ASMBitTest(bmDevice, off), ("%#x\n", off));
1170	if (f & 2) AssertMsg(!ASMBitTest(bmBridge, off), ("%#x\n", off));
1171	if (f & 1) ASMBitSet(bmDevice, off);
1172	if (f & 2) ASMBitSet(bmBridge, off);
1173	off++;
1174	}
1175	}
1176	for (uint32_t off = 0; off < 0x40; off++)
1177	{
1178	AssertMsg(ASMBitTest(bmDevice, off), ("%#x\n", off));
1179	AssertMsg(ASMBitTest(bmBridge, off), ("%#x\n", off));
1180	}
1181	#endif
1182
1183	/*
1184	* Loop thru the fields covering the 64 bytes of standard registers.
1185	*/
1186	uint8_t const fBridge = fIsBridge ? 2 : 1;
1187	uint8_t *pbDstConfig = &pDev->config[0];
1188	for (uint32_t i = 0; i < RT_ELEMENTS(s_aFields); i++)
1189	if (s_aFields[i].fBridge & fBridge)
1190	{
1191	uint8_t const off = s_aFields[i].off;
1192	uint8_t const cb = s_aFields[i].cb;
1193	uint32_t u32Src;
1194	uint32_t u32Dst;
1195	switch (cb)
1196	{
1197	case 1:
1198	u32Src = pbSrcConfig[off];
1199	u32Dst = pbDstConfig[off];
1200	break;
1201	case 2:
1202	u32Src = (uint16_t const )&pbSrcConfig[off];
1203	u32Dst = (uint16_t const )&pbDstConfig[off];
1204	break;
1205	case 4:
1206	u32Src = (uint32_t const )&pbSrcConfig[off];
1207	u32Dst = (uint32_t const )&pbDstConfig[off];
1208	break;
1209	default:
1210	AssertFailed();
1211	continue;
1212	}
1213
1214	if ( u32Src != u32Dst
1215	\|\| off == VBOX_PCI_COMMAND)
1216	{
1217	if (u32Src != u32Dst)
1218	{
1219	if (!s_aFields[i].fWritable)
1220	LogRel(("PCI: %8s/%u: %2u-bit field %s: %x -> %x - !READ ONLY!\n",
1221	pDev->name, pDev->pDevIns->iInstance, cb*8, s_aFields[i].pszName, u32Dst, u32Src));
1222	else
1223	LogRel(("PCI: %8s/%u: %2u-bit field %s: %x -> %x\n",
1224	pDev->name, pDev->pDevIns->iInstance, cb*8, s_aFields[i].pszName, u32Dst, u32Src));
1225	}
1226	if (off == VBOX_PCI_COMMAND)
1227	PCIDevSetCommand(pDev, 0); /* For remapping, see ich9pciR3CommonLoadExec. */
1228	pDev->Int.s.pfnConfigWrite(pDev, off, u32Src, cb);
1229	}
1230	}
1231
1232	/*
1233	* The device dependent registers.
1234	*
1235	* We will not use ConfigWrite here as we have no clue about the size
1236	* of the registers, so the device is responsible for correctly
1237	* restoring functionality governed by these registers.
1238	*/
1239	for (uint32_t off = 0x40; off < sizeof(pDev->config); off++)
1240	if (pbDstConfig[off] != pbSrcConfig[off])
1241	{
1242	LogRel(("PCI: %8s/%u: register %02x: %02x -> %02x\n",
1243	pDev->name, pDev->pDevIns->iInstance, off, pbDstConfig[off], pbSrcConfig[off])); /** @todo make this Log() later. */
1244	pbDstConfig[off] = pbSrcConfig[off];
1245	}
1246	}
1247
1248	/**
1249	* Common worker for ich9pciR3LoadExec and ich9pcibridgeR3LoadExec.
1250	*
1251	* @returns VBox status code.
1252	* @param pBus The bus which data is being loaded.
1253	* @param pSSM The saved state handle.
1254	* @param uVersion The data version.
1255	* @param uPass The pass.
1256	*/
1257	static DECLCALLBACK(int) ich9pciR3CommonLoadExec(PPCIBUS pBus, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1258	{
1259	uint32_t u32;
1260	uint32_t i;
1261	int rc;
1262
1263	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
1264
1265	/*
1266	* Iterate thru all the devices and write 0 to the COMMAND register so
1267	* that all the memory is unmapped before we start restoring the saved
1268	* mapping locations.
1269	*
1270	* The register value is restored afterwards so we can do proper
1271	* LogRels in pciR3CommonRestoreConfig.
1272	*/
1273	for (i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
1274	{
1275	PPCIDEVICE pDev = pBus->apDevices[i];
1276	if (pDev)
1277	{
1278	uint16_t u16 = PCIDevGetCommand(pDev);
1279	pDev->Int.s.pfnConfigWrite(pDev, VBOX_PCI_COMMAND, 0, 2);
1280	PCIDevSetCommand(pDev, u16);
1281	Assert(PCIDevGetCommand(pDev) == u16);
1282	}
1283	}
1284
1285	void* pvMsixPage = RTMemTmpAllocZ(0x1000);
1286	/*
1287	* Iterate all the devices.
1288	*/
1289	for (i = 0;; i++)
1290	{
1291	PPCIDEVICE pDev;
1292	PCIDEVICE DevTmp;
1293
1294	/* index / terminator */
1295	rc = SSMR3GetU32(pSSM, &u32);
1296	if (RT_FAILURE(rc))
1297	return rc;
1298	if (u32 == (uint32_t)~0)
1299	break;
1300	if ( u32 >= RT_ELEMENTS(pBus->apDevices)
1301	\|\| u32 < i)
1302	{
1303	AssertMsgFailed(("u32=%#x i=%#x\n", u32, i));
1304	goto out;
1305	}
1306
1307	/* skip forward to the device checking that no new devices are present. */
1308	for (; i < u32; i++)
1309	{
1310	pDev = pBus->apDevices[i];
1311	if (pDev)
1312	{
1313	LogRel(("New device in slot %#x, %s (vendor=%#06x device=%#06x)\n", i, pDev->name,
1314	PCIDevGetVendorId(pDev), PCIDevGetDeviceId(pDev)));
1315	if (SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT)
1316	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("New device in slot %#x, %s (vendor=%#06x device=%#06x)"),
1317	i, pDev->name, PCIDevGetVendorId(pDev), PCIDevGetDeviceId(pDev));
1318	}
1319	}
1320
1321	/* get the data */
1322	DevTmp.Int.s.uFlags = 0;
1323	DevTmp.Int.s.u8MsiCapOffset = 0;
1324	DevTmp.Int.s.u8MsiCapSize = 0;
1325	DevTmp.Int.s.u8MsixCapOffset = 0;
1326	DevTmp.Int.s.u8MsixCapSize = 0;
1327	DevTmp.Int.s.uIrqPinState = ~0; /* Invalid value in case we have an older saved state to force a state change in pciSetIrq. */
1328	SSMR3GetMem(pSSM, DevTmp.config, sizeof(DevTmp.config));
1329
1330	rc = SSMR3GetU32(pSSM, &DevTmp.Int.s.uFlags);
1331	if (RT_FAILURE(rc))
1332	goto out;
1333
1334	rc = SSMR3GetS32(pSSM, &DevTmp.Int.s.uIrqPinState);
1335	if (RT_FAILURE(rc))
1336	goto out;
1337
1338	rc = SSMR3GetU8(pSSM, &DevTmp.Int.s.u8MsiCapOffset);
1339	if (RT_FAILURE(rc))
1340	goto out;
1341
1342	rc = SSMR3GetU8(pSSM, &DevTmp.Int.s.u8MsiCapSize);
1343	if (RT_FAILURE(rc))
1344	goto out;
1345
1346	rc = SSMR3GetU8(pSSM, &DevTmp.Int.s.u8MsixCapOffset);
1347	if (RT_FAILURE(rc))
1348	goto out;
1349
1350	rc = SSMR3GetU8(pSSM, &DevTmp.Int.s.u8MsixCapSize);
1351	if (RT_FAILURE(rc))
1352	goto out;
1353
1354	/* Load MSI-X page state */
1355	if (DevTmp.Int.s.u8MsixCapOffset != 0)
1356	{
1357	Assert(pvMsixPage != NULL);
1358	SSMR3GetMem(pSSM, pvMsixPage, 0x1000);
1359	if (RT_FAILURE(rc))
1360	goto out;
1361	}
1362
1363	/* check that it's still around. */
1364	pDev = pBus->apDevices[i];
1365	if (!pDev)
1366	{
1367	LogRel(("Device in slot %#x has been removed! vendor=%#06x device=%#06x\n", i,
1368	PCIDevGetVendorId(&DevTmp), PCIDevGetDeviceId(&DevTmp)));
1369	if (SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT)
1370	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Device in slot %#x has been removed! vendor=%#06x device=%#06x"),
1371	i, PCIDevGetVendorId(&DevTmp), PCIDevGetDeviceId(&DevTmp));
1372	continue;
1373	}
1374
1375	/* match the vendor id assuming that this will never be changed. */
1376	if ( PCIDevGetVendorId(&DevTmp) != PCIDevGetVendorId(pDev))
1377	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Device in slot %#x (%s) vendor id mismatch! saved=%.4Rhxs current=%.4Rhxs"),
1378	i, pDev->name, PCIDevGetVendorId(&DevTmp), PCIDevGetVendorId(pDev));
1379
1380	/* commit the loaded device config. */
1381	pciR3CommonRestoreConfig(pDev, &DevTmp.config[0], false ); /** @todo fix bridge fun! */
1382
1383	pDev->Int.s.uIrqPinState = DevTmp.Int.s.uIrqPinState;
1384	pDev->Int.s.u8MsiCapOffset = DevTmp.Int.s.u8MsiCapOffset;
1385	pDev->Int.s.u8MsiCapSize = DevTmp.Int.s.u8MsiCapSize;
1386	pDev->Int.s.u8MsixCapOffset = DevTmp.Int.s.u8MsixCapOffset;
1387	pDev->Int.s.u8MsixCapSize = DevTmp.Int.s.u8MsixCapSize;
1388	if (DevTmp.Int.s.u8MsixCapSize != 0)
1389	{
1390	Assert(pDev->Int.s.pMsixPageR3 != NULL);
1391	memcpy(pDev->Int.s.pMsixPageR3, pvMsixPage, 0x1000);
1392	}
1393	}
1394
1395	out:
1396	if (pvMsixPage)
1397	RTMemTmpFree(pvMsixPage);
1398
1399	return rc;
1400	}
1401
1402	/**
1403	* Loads a saved PCI device state.
1404	*
1405	* @returns VBox status code.
1406	* @param pDevIns Device instance of the PCI Bus.
1407	* @param pPciDev Pointer to PCI device.
1408	* @param pSSM The handle to the saved state.
1409	*/
1410	static DECLCALLBACK(int) ich9pciGenericLoadExec(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PSSMHANDLE pSSM)
1411	{
1412	return SSMR3GetMem(pSSM, &pPciDev->config[0], sizeof(pPciDev->config));
1413	}
1414
1415	static DECLCALLBACK(int) ich9pciR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1416	{
1417	PPCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
1418	PPCIBUS pBus = &pThis->aPciBus;
1419	uint32_t u32;
1420	int rc;
1421
1422	/* We ignore this version as there's no saved state with it anyway */
1423	if (uVersion == VBOX_ICH9PCI_SAVED_STATE_VERSION_NOMSI)
1424	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1425	if (uVersion > VBOX_ICH9PCI_SAVED_STATE_VERSION_MSI)
1426	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1427
1428	/*
1429	* Bus state data.
1430	*/
1431	SSMR3GetU32(pSSM, &pThis->uConfigReg);
1432
1433	/*
1434	* Load IRQ states.
1435	*/
1436	for (int i = 0; i < PCI_APIC_IRQ_PINS; i++)
1437	SSMR3GetU32(pSSM, (uint32_t*)&pThis->uaPciApicIrqLevels[i]);
1438
1439	/* separator */
1440	rc = SSMR3GetU32(pSSM, &u32);
1441	if (RT_FAILURE(rc))
1442	return rc;
1443	if (u32 != (uint32_t)~0)
1444	AssertMsgFailedReturn(("u32=%#x\n", u32), rc);
1445
1446	return ich9pciR3CommonLoadExec(pBus, pSSM, uVersion, uPass);
1447	}
1448
1449	static DECLCALLBACK(int) ich9pcibridgeR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1450	{
1451	PPCIBUS pThis = PDMINS_2_DATA(pDevIns, PPCIBUS);
1452	if (uVersion > VBOX_ICH9PCI_SAVED_STATE_VERSION_MSI)
1453	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1454	return ich9pciR3CommonLoadExec(pThis, pSSM, uVersion, uPass);
1455	}
1456
1457	static uint32_t ich9pciConfigRead(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t len)
1458	{
1459	/* Will only work in LSB case */
1460	uint32_t u32Val;
1461	PciAddress aPciAddr;
1462
1463	aPciAddr.iBus = uBus;
1464	aPciAddr.iDeviceFunc = uDevFn;
1465	aPciAddr.iRegister = addr;
1466
1467	/* cannot be rescheduled, as already in R3 */
1468	int rc = ich9pciDataReadAddr(pGlobals, &aPciAddr, len, &u32Val, VERR_INTERNAL_ERROR);
1469	AssertRC(rc);
1470	return u32Val;
1471	}
1472
1473	static void ich9pciConfigWrite(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t val, uint32_t len)
1474	{
1475	PciAddress aPciAddr;
1476
1477	aPciAddr.iBus = uBus;
1478	aPciAddr.iDeviceFunc = uDevFn;
1479	aPciAddr.iRegister = addr;
1480
1481	/* cannot be rescheduled, as already in R3 */
1482	int rc = ich9pciDataWriteAddr(pGlobals, &aPciAddr, val, len, VERR_INTERNAL_ERROR);
1483	AssertRC(rc);
1484	}
1485
1486	static void ich9pciSetRegionAddress(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, int iRegion, uint32_t addr)
1487	{
1488	uint32_t uReg = ich9pciGetRegionReg(iRegion);
1489
1490	/* Read memory type first. */
1491	uint8_t uResourceType = ich9pciConfigRead(pGlobals, uBus, uDevFn, uReg, 1);
1492	/* Read command register. */
1493	uint16_t uCmd = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_COMMAND, 2);
1494
1495	if ( iRegion == PCI_ROM_SLOT )
1496	uCmd \|= PCI_COMMAND_MEMACCESS;
1497	else if ((uResourceType & PCI_ADDRESS_SPACE_IO) == PCI_ADDRESS_SPACE_IO)
1498	uCmd \|= PCI_COMMAND_IOACCESS; /* Enable I/O space access. */
1499	else /* The region is MMIO. */
1500	uCmd \|= PCI_COMMAND_MEMACCESS; /* Enable MMIO access. */
1501
1502	/* Write address of the device. */
1503	ich9pciConfigWrite(pGlobals, uBus, uDevFn, uReg, addr, 4);
1504
1505	/* enable memory mappings */
1506	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_COMMAND, uCmd, 2);
1507	}
1508
1509
1510	static void ich9pciBiosInitBridge(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint8_t cBridgeDepth, uint8_t *paBridgePositions)
1511	{
1512	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_SECONDARY_BUS, pGlobals->uBus, 1);
1513	/* Temporary until we know how many other bridges are behind this one. */
1514	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_SUBORDINATE_BUS, 0xff, 1);
1515
1516	/* Add position of this bridge into the array. */
1517	paBridgePositions[cBridgeDepth+1] = (uDevFn >> 3);
1518
1519	/*
1520	* The I/O range for the bridge must be aligned to a 4KB boundary.
1521	* This does not change anything really as the access to the device is not going
1522	* through the bridge but we want to be compliant to the spec.
1523	*/
1524	if ((pGlobals->uPciBiosIo % 4096) != 0)
1525	{
1526	pGlobals->uPciBiosIo = RT_ALIGN_32(pGlobals->uPciBiosIo, 4*1024);
1527	Log(("%s: Aligned I/O start address. New address %#x\n", __FUNCTION__, pGlobals->uPciBiosIo));
1528	}
1529	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_IO_BASE, (pGlobals->uPciBiosIo >> 8) & 0xf0, 1);
1530
1531	/* The MMIO range for the bridge must be aligned to a 1MB boundary. */
1532	if ((pGlobals->uPciBiosMmio % (1024 * 1024)) != 0)
1533	{
1534	pGlobals->uPciBiosMmio = RT_ALIGN_32(pGlobals->uPciBiosMmio, 1024*1024);
1535	Log(("%s: Aligned MMIO start address. New address %#x\n", __FUNCTION__, pGlobals->uPciBiosMmio));
1536	}
1537	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_MEMORY_BASE, (pGlobals->uPciBiosMmio >> 16) & UINT32_C(0xffff0), 2);
1538
1539	/* Save values to compare later to. */
1540	uint32_t u32IoAddressBase = pGlobals->uPciBiosIo;
1541	uint32_t u32MMIOAddressBase = pGlobals->uPciBiosMmio;
1542
1543	/* Init devices behind the bridge and possibly other bridges as well. */
1544	for (int iDev = 0; iDev <= 255; iDev++)
1545	ich9pciBiosInitDevice(pGlobals, uBus + 1, iDev, cBridgeDepth + 1, paBridgePositions);
1546
1547	/* The number of bridges behind the this one is now available. */
1548	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_SUBORDINATE_BUS, pGlobals->uBus, 1);
1549
1550	/*
1551	* Set I/O limit register. If there is no device with I/O space behind the bridge
1552	* we set a lower value than in the base register.
1553	* The result with a real bridge is that no I/O transactions are passed to the secondary
1554	* interface. Again this doesn't really matter here but we want to be compliant to the spec.
1555	*/
1556	if ((u32IoAddressBase != pGlobals->uPciBiosIo) && ((pGlobals->uPciBiosIo % 4096) != 0))
1557	{
1558	/* The upper boundary must be one byte less than a 4KB boundary. */
1559	pGlobals->uPciBiosIo = RT_ALIGN_32(pGlobals->uPciBiosIo, 4*1024);
1560	}
1561
1562	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_IO_LIMIT, ((pGlobals->uPciBiosIo >> 8) & 0xf0) - 1, 1);
1563
1564	/* Same with the MMIO limit register but with 1MB boundary here. */
1565	if ((u32MMIOAddressBase != pGlobals->uPciBiosMmio) && ((pGlobals->uPciBiosMmio % (1024 * 1024)) != 0))
1566	{
1567	/* The upper boundary must be one byte less than a 1MB boundary. */
1568	pGlobals->uPciBiosMmio = RT_ALIGN_32(pGlobals->uPciBiosMmio, 1024*1024);
1569	}
1570	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_MEMORY_LIMIT, ((pGlobals->uPciBiosMmio >> 16) & UINT32_C(0xfff0)) - 1, 2);
1571
1572	/*
1573	* Set the prefetch base and limit registers. We currently have no device with a prefetchable region
1574	* which may be behind a bridge. That's why it is unconditionally disabled here atm by writing a higher value into
1575	* the base register than in the limit register.
1576	*/
1577	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_MEMORY_BASE, 0xfff0, 2);
1578	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_MEMORY_LIMIT, 0x0, 2);
1579	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_BASE_UPPER32, 0x00, 4);
1580	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_LIMIT_UPPER32, 0x00, 4);
1581	}
1582
1583	static void ich9pciBiosInitDevice(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint8_t cBridgeDepth, uint8_t *paBridgePositions)
1584	{
1585	uint32_t *paddr;
1586	uint16_t uDevClass, uVendor, uDevice;
1587	uint8_t uCmd;
1588
1589	uDevClass = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_CLASS_DEVICE, 2);
1590	uVendor = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_VENDOR_ID, 2);
1591	uDevice = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_DEVICE_ID, 2);
1592
1593	/* If device is present */
1594	if (uVendor == 0xffff)
1595	return;
1596
1597	switch (uDevClass)
1598	{
1599	case 0x0101:
1600	/* IDE controller */
1601	ich9pciConfigWrite(pGlobals, uBus, uDevFn, 0x40, 0x8000, 2); /* enable IDE0 */
1602	ich9pciConfigWrite(pGlobals, uBus, uDevFn, 0x42, 0x8000, 2); /* enable IDE1 */
1603	goto default_map;
1604	break;
1605	case 0x0300:
1606	/* VGA controller */
1607	if (uVendor != 0x80ee)
1608	goto default_map;
1609	/* VGA: map frame buffer to default Bochs VBE address */
1610	ich9pciSetRegionAddress(pGlobals, uBus, uDevFn, 0, 0xE0000000);
1611	/*
1612	* Legacy VGA I/O ports are implicitly decoded by a VGA class device. But
1613	* only the framebuffer (i.e., a memory region) is explicitly registered via
1614	* ich9pciSetRegionAddress, so I/O decoding must be enabled manually.
1615	*/
1616	uCmd = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_COMMAND, 1);
1617	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_COMMAND,
1618	/* Enable I/O space access. */
1619	uCmd \| PCI_COMMAND_IOACCESS,
1620	1);
1621	break;
1622	case 0x0604:
1623	/* PCI-to-PCI bridge. */
1624	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_PRIMARY_BUS, uBus, 1);
1625
1626	AssertMsg(pGlobals->uBus < 255, ("Too many bridges on the bus\n"));
1627	pGlobals->uBus++;
1628	ich9pciBiosInitBridge(pGlobals, uBus, uDevFn, cBridgeDepth, paBridgePositions);
1629	break;
1630	default:
1631	default_map:
1632	{
1633	/* default memory mappings */
1634	/*
1635	* We ignore ROM region here.
1636	*/
1637	for (int iRegion = 0; iRegion < (PCI_NUM_REGIONS-1); iRegion++)
1638	{
1639	uint32_t u32Address = ich9pciGetRegionReg(iRegion);
1640
1641	/* Calculate size - we write all 1s into the BAR, and then evaluate which bits
1642	are cleared. . */
1643	uint8_t u8ResourceType = ich9pciConfigRead(pGlobals, uBus, uDevFn, u32Address, 1);
1644	ich9pciConfigWrite(pGlobals, uBus, uDevFn, u32Address, UINT32_C(0xffffffff), 4);
1645	uint32_t u32Size = ich9pciConfigRead(pGlobals, uBus, uDevFn, u32Address, 4);
1646	/* Clear resource information depending on resource type. */
1647	if ((u8ResourceType & PCI_COMMAND_IOACCESS) == PCI_COMMAND_IOACCESS) /* I/O */
1648	u32Size &= ~(0x01);
1649	else /* MMIO */
1650	u32Size &= ~(0x0f);
1651
1652	bool fIsPio = ((u8ResourceType & PCI_COMMAND_IOACCESS) == PCI_COMMAND_IOACCESS);
1653	/*
1654	* Invert all bits and add 1 to get size of the region.
1655	* (From PCI implementation note)
1656	*/
1657	if (fIsPio && (u32Size & UINT32_C(0xffff0000)) == 0)
1658	u32Size = (~(u32Size \| UINT32_C(0xffff0000))) + 1;
1659	else
1660	u32Size = (~u32Size) + 1;
1661
1662	Log(("%s: Size of region %u for device %d on bus %d is %u\n", __FUNCTION__, iRegion, uDevFn, uBus, u32Size));
1663
1664	if (u32Size)
1665	{
1666	paddr = fIsPio ? &pGlobals->uPciBiosIo : &pGlobals->uPciBiosMmio;
1667	paddr = (paddr + u32Size - 1) & ~(u32Size - 1);
1668	Log(("%s: Start address of %s region %u is %#x\n", __FUNCTION__, (fIsPio ? "I/O" : "MMIO"), iRegion, *paddr));
1669	ich9pciSetRegionAddress(pGlobals, uBus, uDevFn, iRegion, *paddr);
1670	*paddr += u32Size;
1671	Log(("%s: New address is %#x\n", __FUNCTION__, *paddr));
1672	}
1673	}
1674	break;
1675	}
1676	}
1677
1678	/* map the interrupt */
1679	uint32_t iPin = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_INTERRUPT_PIN, 1);
1680	if (iPin != 0)
1681	{
1682	uint8_t uBridgeDevFn = uDevFn;
1683	iPin--;
1684
1685	/* We need to go up to the host bus to see which irq this device will assert there. */
1686	while (cBridgeDepth != 0)
1687	{
1688	/* Get the pin the device would assert on the bridge. */
1689	iPin = ((uBridgeDevFn >> 3) + iPin) & 3;
1690	uBridgeDevFn = paBridgePositions[cBridgeDepth];
1691	cBridgeDepth--;
1692	}
1693
1694	int iIrq = aPciIrqs[ich9pciSlotGetPirq(uBus, uDevFn, iPin)];
1695	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_INTERRUPT_LINE, iIrq, 1);
1696	}
1697	}
1698
1699	static DECLCALLBACK(int) ich9pciFakePCIBIOS(PPDMDEVINS pDevIns)
1700	{
1701	unsigned i;
1702	uint8_t elcr[2] = {0, 0};
1703	PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
1704	PVM pVM = PDMDevHlpGetVM(pDevIns);
1705	Assert(pVM);
1706
1707	/*
1708	* Set the start addresses.
1709	*/
1710	pGlobals->uPciBiosIo = 0xd000;
1711	pGlobals->uPciBiosMmio = UINT32_C(0xf0000000);
1712	pGlobals->uBus = 0;
1713
1714	/*
1715	* Init the devices.
1716	*/
1717	for (i = 0; i < 256; i++)
1718	{
1719	uint8_t aBridgePositions[256];
1720
1721	memset(aBridgePositions, 0, sizeof(aBridgePositions));
1722	Log2(("PCI: Initializing device %d (%#x)\n",
1723	i, 0x80000000 \| (i << 8)));
1724	ich9pciBiosInitDevice(pGlobals, 0, i, 0, aBridgePositions);
1725	}
1726
1727	return VINF_SUCCESS;
1728	}
1729
1730	static DECLCALLBACK(uint32_t) ich9pciConfigReadDev(PCIDevice *aDev, uint32_t u32Address, unsigned len)
1731	{
1732	if ((u32Address + len) > 256 && (u32Address + len) < 4096)
1733	{
1734	AssertMsgReturn(false, ("Read from extended registers falled back to generic code\n"), 0);
1735	}
1736
1737	if ( PCIIsMsiCapable(aDev)
1738	&& (u32Address >= aDev->Int.s.u8MsiCapOffset)
1739	&& (u32Address < aDev->Int.s.u8MsiCapOffset + aDev->Int.s.u8MsiCapSize)
1740	)
1741	{
1742	return MsiPciConfigRead(aDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pDevIns), aDev, u32Address, len);
1743	}
1744
1745	if ( PCIIsMsixCapable(aDev)
1746	&& (u32Address >= aDev->Int.s.u8MsixCapOffset)
1747	&& (u32Address < aDev->Int.s.u8MsixCapOffset + aDev->Int.s.u8MsixCapSize)
1748	)
1749	{
1750	return MsixPciConfigRead(aDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pDevIns), aDev, u32Address, len);
1751	}
1752
1753	AssertMsgReturn(u32Address + len <= 256, ("Read after end of PCI config space\n"),
1754	0);
1755	switch (len)
1756	{
1757	case 1:
1758	return PCIDevGetByte(aDev, u32Address);
1759	case 2:
1760	return PCIDevGetWord(aDev, u32Address);
1761	case 4:
1762	return PCIDevGetDWord(aDev, u32Address);
1763	default:
1764	Assert(false);
1765	return 0;
1766	}
1767	}
1768
1769	DECLINLINE(void) ich9pciWriteBarByte(PCIDevice *aDev, int iRegion, int iOffset, uint8_t u8Val)
1770	{
1771	PCIIORegion * pRegion = &aDev->Int.s.aIORegions[iRegion];
1772
1773	int iRegionSize = pRegion->size;
1774
1775	Log3(("ich9pciWriteBarByte: region=%d off=%d val=%x size=%d\n",
1776	iRegion, iOffset, u8Val, iRegionSize));
1777
1778	/* Region doesn't exist */
1779	if (iRegionSize == 0)
1780	return;
1781
1782	uint32_t uAddr = ich9pciGetRegionReg(iRegion) + iOffset;
1783	/* Region size must be power of two */
1784	Assert((iRegionSize & (iRegionSize - 1)) == 0);
1785	uint8_t uMask = (((uint32_t)iRegionSize - 1) >> (iOffset*8) ) & 0xff;
1786
1787	if (iOffset == 0)
1788	{
1789	uMask \|= (pRegion->type & PCI_ADDRESS_SPACE_IO) ?
1790	(1 << 2) - 1 /* 2 lowest bits for IO region */ :
1791	(1 << 4) - 1 /* 4 lowest bits for memory region, also ROM enable bit for ROM region */;
1792
1793	}
1794
1795	uint8_t u8Old = PCIDevGetByte(aDev, uAddr) & uMask;
1796	u8Val = (u8Old & uMask) \| (u8Val & ~uMask);
1797
1798	Log3(("ich9pciWriteBarByte: was %x writing %x\n", u8Old, u8Val));
1799
1800	PCIDevSetByte(aDev, uAddr, u8Val);
1801	}
1802	/**
1803	* See paragraph 7.5 of PCI Express specification (p. 349) for definition of
1804	* registers and their writability policy.
1805	*/
1806	static DECLCALLBACK(void) ich9pciConfigWriteDev(PCIDevice *aDev, uint32_t u32Address,
1807	uint32_t val, unsigned len)
1808	{
1809	Assert(len <= 4);
1810
1811	if ((u32Address + len) > 256 && (u32Address + len) < 4096)
1812	{
1813	AssertMsgReturnVoid(false, ("Write to extended registers falled back to generic code\n"));
1814	}
1815
1816	AssertMsgReturnVoid(u32Address + len <= 256, ("Write after end of PCI config space\n"));
1817
1818	if ( PCIIsMsiCapable(aDev)
1819	&& (u32Address >= aDev->Int.s.u8MsiCapOffset)
1820	&& (u32Address < aDev->Int.s.u8MsiCapOffset + aDev->Int.s.u8MsiCapSize)
1821	)
1822	{
1823	MsiPciConfigWrite(aDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pDevIns),
1824	aDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pPciHlp),
1825	aDev, u32Address, val, len);
1826	return;
1827	}
1828
1829	if ( PCIIsMsixCapable(aDev)
1830	&& (u32Address >= aDev->Int.s.u8MsixCapOffset)
1831	&& (u32Address < aDev->Int.s.u8MsixCapOffset + aDev->Int.s.u8MsixCapSize)
1832	)
1833	{
1834	MsixPciConfigWrite(aDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pDevIns),
1835	aDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pPciHlp),
1836	aDev, u32Address, val, len);
1837	return;
1838	}
1839
1840	uint32_t addr = u32Address;
1841	bool fUpdateMappings = false;
1842	bool fP2PBridge = false;
1843	for (uint32_t i = 0; i < len; i++)
1844	{
1845	bool fWritable = false;
1846	bool fRom = false;
1847	switch (PCIDevGetHeaderType(aDev))
1848	{
1849	case 0x00: /* normal device */
1850	case 0x80: /* multi-function device */
1851	switch (addr)
1852	{
1853	/* Read-only registers */
1854	case VBOX_PCI_VENDOR_ID: case VBOX_PCI_VENDOR_ID+1:
1855	case VBOX_PCI_DEVICE_ID: case VBOX_PCI_DEVICE_ID+1:
1856	case VBOX_PCI_REVISION_ID:
1857	case VBOX_PCI_CLASS_PROG:
1858	case VBOX_PCI_CLASS_SUB:
1859	case VBOX_PCI_CLASS_BASE:
1860	case VBOX_PCI_HEADER_TYPE:
1861	case VBOX_PCI_SUBSYSTEM_VENDOR_ID: case VBOX_PCI_SUBSYSTEM_VENDOR_ID+1:
1862	case VBOX_PCI_SUBSYSTEM_ID: case VBOX_PCI_SUBSYSTEM_ID+1:
1863	case VBOX_PCI_ROM_ADDRESS: case VBOX_PCI_ROM_ADDRESS+1: case VBOX_PCI_ROM_ADDRESS+2: case VBOX_PCI_ROM_ADDRESS+3:
1864	case VBOX_PCI_CAPABILITY_LIST:
1865	case VBOX_PCI_INTERRUPT_PIN:
1866	fWritable = false;
1867	break;
1868	/* Others can be written */
1869	default:
1870	fWritable = true;
1871	break;
1872	}
1873	break;
1874	case 0x01: /* PCI-PCI bridge */
1875	fP2PBridge = true;
1876	switch (addr)
1877	{
1878	/* Read-only registers */
1879	case VBOX_PCI_VENDOR_ID: case VBOX_PCI_VENDOR_ID+1:
1880	case VBOX_PCI_DEVICE_ID: case VBOX_PCI_DEVICE_ID+1:
1881	case VBOX_PCI_REVISION_ID:
1882	case VBOX_PCI_CLASS_PROG:
1883	case VBOX_PCI_CLASS_SUB:
1884	case VBOX_PCI_CLASS_BASE:
1885	case VBOX_PCI_HEADER_TYPE:
1886	case VBOX_PCI_ROM_ADDRESS_BR: case VBOX_PCI_ROM_ADDRESS_BR+1: case VBOX_PCI_ROM_ADDRESS_BR+2: case VBOX_PCI_ROM_ADDRESS_BR+3:
1887	case VBOX_PCI_INTERRUPT_PIN:
1888	fWritable = false;
1889	break;
1890	default:
1891	fWritable = true;
1892	break;
1893	}
1894	break;
1895	default:
1896	AssertMsgFailed(("Unknown header type %x\n", PCIDevGetHeaderType(aDev)));
1897	fWritable = false;
1898	break;
1899	}
1900
1901	uint8_t u8Val = (uint8_t)val;
1902	switch (addr)
1903	{
1904	case VBOX_PCI_COMMAND: /* Command register, bits 0-7. */
1905	fUpdateMappings = true;
1906	PCIDevSetByte(aDev, addr, u8Val);
1907	break;
1908	case VBOX_PCI_COMMAND+1: /* Command register, bits 8-15. */
1909	/* don't change reserved bits (11-15) */
1910	u8Val &= UINT32_C(~0xf8);
1911	fUpdateMappings = true;
1912	PCIDevSetByte(aDev, addr, u8Val);
1913	break;
1914	case VBOX_PCI_STATUS: /* Status register, bits 0-7. */
1915	/* don't change read-only bits => actually all lower bits are read-only */
1916	u8Val &= UINT32_C(~0xff);
1917	/* status register, low part: clear bits by writing a '1' to the corresponding bit */
1918	aDev->config[addr] &= ~u8Val;
1919	break;
1920	case VBOX_PCI_STATUS+1: /* Status register, bits 8-15. */
1921	/* don't change read-only bits */
1922	u8Val &= UINT32_C(~0x06);
1923	/* status register, high part: clear bits by writing a '1' to the corresponding bit */
1924	aDev->config[addr] &= ~u8Val;
1925	break;
1926	case VBOX_PCI_ROM_ADDRESS: case VBOX_PCI_ROM_ADDRESS +1: case VBOX_PCI_ROM_ADDRESS +2: case VBOX_PCI_ROM_ADDRESS +3:
1927	fRom = true;
1928	case VBOX_PCI_BASE_ADDRESS_0: case VBOX_PCI_BASE_ADDRESS_0+1: case VBOX_PCI_BASE_ADDRESS_0+2: case VBOX_PCI_BASE_ADDRESS_0+3:
1929	case VBOX_PCI_BASE_ADDRESS_1: case VBOX_PCI_BASE_ADDRESS_1+1: case VBOX_PCI_BASE_ADDRESS_1+2: case VBOX_PCI_BASE_ADDRESS_1+3:
1930	case VBOX_PCI_BASE_ADDRESS_2: case VBOX_PCI_BASE_ADDRESS_2+1: case VBOX_PCI_BASE_ADDRESS_2+2: case VBOX_PCI_BASE_ADDRESS_2+3:
1931	case VBOX_PCI_BASE_ADDRESS_3: case VBOX_PCI_BASE_ADDRESS_3+1: case VBOX_PCI_BASE_ADDRESS_3+2: case VBOX_PCI_BASE_ADDRESS_3+3:
1932	case VBOX_PCI_BASE_ADDRESS_4: case VBOX_PCI_BASE_ADDRESS_4+1: case VBOX_PCI_BASE_ADDRESS_4+2: case VBOX_PCI_BASE_ADDRESS_4+3:
1933	case VBOX_PCI_BASE_ADDRESS_5: case VBOX_PCI_BASE_ADDRESS_5+1: case VBOX_PCI_BASE_ADDRESS_5+2: case VBOX_PCI_BASE_ADDRESS_5+3:
1934	{
1935	/* We check that, as same PCI register numbers as BARs may mean different registers for bridges */
1936	if (fP2PBridge)
1937	goto default_case;
1938	else
1939	{
1940	int iRegion = fRom ? VBOX_PCI_ROM_SLOT : (addr - VBOX_PCI_BASE_ADDRESS_0) >> 2;
1941	int iOffset = addr & 0x3;
1942	ich9pciWriteBarByte(aDev, iRegion, iOffset, u8Val);
1943	fUpdateMappings = true;
1944	}
1945	break;
1946	}
1947	default:
1948	default_case:
1949	if (fWritable)
1950	PCIDevSetByte(aDev, addr, u8Val);
1951	}
1952	addr++;
1953	val >>= 8;
1954	}
1955
1956	if (fUpdateMappings)
1957	/* if the command/base address register is modified, we must modify the mappings */
1958	ich9pciUpdateMappings(aDev);
1959	}
1960
1961	/* Slot/functions assignment per table at p. 12 of ICH9 family spec update */
1962	static const struct {
1963	const char* pszName;
1964	int32_t iSlot;
1965	int32_t iFunction;
1966	} PciSlotAssignments[] = {
1967	/* The only override that have to be here, as host controller is added in the way invisible to bus slot assignment management,
1968	maybe to be changed in the future. */
1969	{
1970	"i82801", 30, 0 /* Host Controller */
1971	},
1972	};
1973
1974	static bool assignPosition(PPCIBUS pBus, PPCIDEVICE pPciDev, const char pszName, int iDevFn, PciAddress aPosition)
1975	{
1976	aPosition->iBus = 0;
1977	aPosition->iDeviceFunc = iDevFn;
1978	aPosition->iRegister = 0; /* N/A */
1979
1980	/* Hardcoded slots/functions, per chipset spec */
1981	for (size_t i = 0; i < RT_ELEMENTS(PciSlotAssignments); i++)
1982	{
1983	if (!strcmp(pszName, PciSlotAssignments[i].pszName))
1984	{
1985	PCISetRequestedDevfunc(pPciDev);
1986	aPosition->iDeviceFunc =
1987	(PciSlotAssignments[i].iSlot << 3) + PciSlotAssignments[i].iFunction;
1988	return true;
1989	}
1990	}
1991
1992	/* Explicit slot request */
1993	if (iDevFn >=0 && iDevFn < (int)RT_ELEMENTS(pBus->apDevices))
1994	return true;
1995
1996	int iStartPos = 0;
1997
1998	/* Otherwise when assigning a slot, we need to make sure all its functions are available */
1999	for (int iPos = iStartPos; iPos < (int)RT_ELEMENTS(pBus->apDevices); iPos += 8)
2000	{
2001	if ( !pBus->apDevices[iPos]
2002	&& !pBus->apDevices[iPos + 1]
2003	&& !pBus->apDevices[iPos + 2]
2004	&& !pBus->apDevices[iPos + 3]
2005	&& !pBus->apDevices[iPos + 4]
2006	&& !pBus->apDevices[iPos + 5]
2007	&& !pBus->apDevices[iPos + 6]
2008	&& !pBus->apDevices[iPos + 7])
2009	{
2010	PCIClearRequestedDevfunc(pPciDev);
2011	aPosition->iDeviceFunc = iPos;
2012	return true;
2013	}
2014	}
2015
2016	return false;
2017	}
2018
2019	static bool hasHardAssignedDevsInSlot(PPCIBUS pBus, int iSlot)
2020	{
2021	PCIDevice** aSlot = &pBus->apDevices[iSlot << 3];
2022
2023	return (aSlot[0] && PCIIsRequestedDevfunc(aSlot[0]))
2024	\|\| (aSlot[1] && PCIIsRequestedDevfunc(aSlot[1]))
2025	\|\| (aSlot[2] && PCIIsRequestedDevfunc(aSlot[2]))
2026	\|\| (aSlot[3] && PCIIsRequestedDevfunc(aSlot[3]))
2027	\|\| (aSlot[4] && PCIIsRequestedDevfunc(aSlot[4]))
2028	\|\| (aSlot[5] && PCIIsRequestedDevfunc(aSlot[5]))
2029	\|\| (aSlot[6] && PCIIsRequestedDevfunc(aSlot[6]))
2030	\|\| (aSlot[7] && PCIIsRequestedDevfunc(aSlot[7]))
2031	;
2032	}
2033
2034	static int ich9pciRegisterInternal(PPCIBUS pBus, int iDev, PPCIDEVICE pPciDev, const char *pszName)
2035	{
2036	PciAddress aPosition = {0, 0, 0};
2037
2038	/*
2039	* Find device position
2040	*/
2041	if (!assignPosition(pBus, pPciDev, pszName, iDev, &aPosition))
2042	{
2043	AssertMsgFailed(("Couldn't asssign position!\n"));
2044	return VERR_PDM_TOO_PCI_MANY_DEVICES;
2045	}
2046
2047	AssertMsgReturn(aPosition.iBus == 0,
2048	("Assigning behind the bridge not implemented yet\n"),
2049	VERR_PDM_TOO_PCI_MANY_DEVICES);
2050
2051
2052	iDev = aPosition.iDeviceFunc;
2053	/*
2054	* Check if we can really take this slot, possibly by relocating
2055	* its current habitant, if it wasn't hard assigned too.
2056	*/
2057	if (PCIIsRequestedDevfunc(pPciDev) &&
2058	pBus->apDevices[iDev] &&
2059	PCIIsRequestedDevfunc(pBus->apDevices[iDev]))
2060	{
2061	AssertReleaseMsgFailed(("Configuration error:'%s' and '%s' are both configured as device %d\n",
2062	pszName, pBus->apDevices[iDev]->name, iDev));
2063	return VERR_INTERNAL_ERROR;
2064	}
2065
2066	if (pBus->apDevices[iDev])
2067	{
2068	/* if we got here, we shall (and usually can) relocate the device */
2069	bool assigned = assignPosition(pBus, pBus->apDevices[iDev], pBus->apDevices[iDev]->name, -1, &aPosition);
2070	AssertMsgReturn(aPosition.iBus == 0,
2071	("Assigning behind the bridge not implemented yet\n"),
2072	VERR_PDM_TOO_PCI_MANY_DEVICES);
2073	int iRelDev = aPosition.iDeviceFunc;
2074	if (!assigned \|\| iRelDev == iDev)
2075	{
2076	AssertMsgFailed(("Couldn't find free spot!\n"));
2077	return VERR_PDM_TOO_PCI_MANY_DEVICES;
2078	}
2079	/* Copy device function by function to its new position */
2080	for (int i = 0; i < 8; i++)
2081	{
2082	if (!pBus->apDevices[iDev + i])
2083	continue;
2084	Log(("PCI: relocating '%s' from slot %#x to %#x\n", pBus->apDevices[iDev + i]->name, iDev + i, iRelDev + i));
2085	pBus->apDevices[iRelDev + i] = pBus->apDevices[iDev + i];
2086	pBus->apDevices[iRelDev + i]->devfn = iRelDev + i;
2087	pBus->apDevices[iDev + i] = NULL;
2088	}
2089	}
2090
2091	/*
2092	* Fill in device information.
2093	*/
2094	pPciDev->devfn = iDev;
2095	pPciDev->name = pszName;
2096	pPciDev->Int.s.pBusR3 = pBus;
2097	pPciDev->Int.s.pBusR0 = MMHyperR3ToR0(PDMDevHlpGetVM(pBus->CTX_SUFF(pDevIns)), pBus);
2098	pPciDev->Int.s.pBusRC = MMHyperR3ToRC(PDMDevHlpGetVM(pBus->CTX_SUFF(pDevIns)), pBus);
2099	pPciDev->Int.s.pfnConfigRead = ich9pciConfigReadDev;
2100	pPciDev->Int.s.pfnConfigWrite = ich9pciConfigWriteDev;
2101	pBus->apDevices[iDev] = pPciDev;
2102	if (PCIIsPci2PciBridge(pPciDev))
2103	{
2104	AssertMsg(pBus->cBridges < RT_ELEMENTS(pBus->apDevices), ("Number of bridges exceeds the number of possible devices on the bus\n"));
2105	AssertMsg(pPciDev->Int.s.pfnBridgeConfigRead && pPciDev->Int.s.pfnBridgeConfigWrite,
2106	("device is a bridge but does not implement read/write functions\n"));
2107	pBus->papBridgesR3[pBus->cBridges] = pPciDev;
2108	pBus->cBridges++;
2109	}
2110
2111	Log(("PCI: Registered device %d function %d (%#x) '%s'.\n",
2112	iDev >> 3, iDev & 7, 0x80000000 \| (iDev << 8), pszName));
2113
2114	return VINF_SUCCESS;
2115	}
2116
2117	static void printIndent(PCDBGFINFOHLP pHlp, int iIndent)
2118	{
2119	for (int i = 0; i < iIndent; i++)
2120	{
2121	pHlp->pfnPrintf(pHlp, " ");
2122	}
2123	}
2124
2125	static void ich9pciBusInfo(PPCIBUS pBus, PCDBGFINFOHLP pHlp, int iIndent, bool fRegisters)
2126	{
2127	for (uint32_t iDev = 0; iDev < RT_ELEMENTS(pBus->apDevices); iDev++)
2128	{
2129	PPCIDEVICE pPciDev = pBus->apDevices[iDev];
2130	if (pPciDev != NULL)
2131	{
2132	printIndent(pHlp, iIndent);
2133	pHlp->pfnPrintf(pHlp, "%02x:%02x:%02x %s: %04x-%04x%s%s",
2134	pBus->iBus, (iDev >> 3) & 0xff, iDev & 0x7,
2135	pPciDev->name,
2136	PCIDevGetVendorId(pPciDev), PCIDevGetDeviceId(pPciDev),
2137	PCIIsMsiCapable(pPciDev) ? " MSI" : "",
2138	PCIIsMsixCapable(pPciDev) ? " MSI-X" : ""
2139	);
2140	if (PCIDevGetInterruptPin(pPciDev) != 0)
2141	pHlp->pfnPrintf(pHlp, " IRQ%d", PCIDevGetInterruptLine(pPciDev));
2142
2143	pHlp->pfnPrintf(pHlp, "\n");
2144
2145	int iCmd = PCIDevGetCommand(pPciDev);
2146	if ((iCmd & (VBOX_PCI_COMMAND_IO \| VBOX_PCI_COMMAND_MEMORY)) != 0)
2147	{
2148	for (int iRegion = 0; iRegion < PCI_NUM_REGIONS; iRegion++)
2149	{
2150	PCIIORegion* pRegion = &pPciDev->Int.s.aIORegions[iRegion];
2151	int32_t iRegionSize = pRegion->size;
2152
2153	if (iRegionSize == 0)
2154	continue;
2155
2156	uint32_t u32Addr = ich9pciConfigReadDev(pPciDev, ich9pciGetRegionReg(iRegion), 4);
2157	const char * szDesc;
2158
2159	if (pRegion->type & PCI_ADDRESS_SPACE_IO)
2160	{
2161	szDesc = "IO";
2162	u32Addr &= ~0x3;
2163	}
2164	else
2165	{
2166	szDesc = "MMIO";
2167	u32Addr &= ~0xf;
2168	}
2169
2170	printIndent(pHlp, iIndent + 2);
2171	pHlp->pfnPrintf(pHlp, " %s region #%d: %x..%x\n",
2172	szDesc, iRegion, u32Addr, u32Addr+iRegionSize);
2173	}
2174	}
2175
2176	if (fRegisters)
2177	{
2178	printIndent(pHlp, iIndent + 2);
2179	pHlp->pfnPrintf(pHlp, " PCI registers:\n");
2180	for (int iReg = 0; iReg < 0x100; )
2181	{
2182	int iPerLine = 0x10;
2183	Assert (0x100 % iPerLine == 0);
2184	printIndent(pHlp, iIndent + 3);
2185
2186	while (iPerLine-- > 0)
2187	{
2188	pHlp->pfnPrintf(pHlp, "%02x ", pPciDev->config[iReg++]);
2189	}
2190	pHlp->pfnPrintf(pHlp, "\n");
2191	}
2192	}
2193	}
2194	}
2195
2196	if (pBus->cBridges > 0)
2197	{
2198	printIndent(pHlp, iIndent);
2199	pHlp->pfnPrintf(pHlp, "Registered %d bridges, subordinate buses info follows\n", pBus->cBridges);
2200	for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
2201	{
2202	PPCIBUS pBusSub = PDMINS_2_DATA(pBus->papBridgesR3[iBridge]->pDevIns, PPCIBUS);
2203	ich9pciBusInfo(pBusSub, pHlp, iIndent + 1, fRegisters);
2204	}
2205	}
2206	}
2207
2208	/**
2209	* Info handler, device version.
2210	*
2211	* @param pDevIns Device instance which registered the info.
2212	* @param pHlp Callback functions for doing output.
2213	* @param pszArgs Argument string. Optional and specific to the handler.
2214	*/
2215	static DECLCALLBACK(void) ich9pciInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
2216	{
2217	PPCIBUS pBus = DEVINS_2_PCIBUS(pDevIns);
2218
2219	if (pszArgs == NULL \|\| !strcmp(pszArgs, "basic"))
2220	{
2221	ich9pciBusInfo(pBus, pHlp, 0, false);
2222	}
2223	else if (!strcmp(pszArgs, "verbose"))
2224	{
2225	ich9pciBusInfo(pBus, pHlp, 0, true);
2226	}
2227	else
2228	{
2229	pHlp->pfnPrintf(pHlp, "Invalid argument. Recognized arguments are 'basic', 'verbose'.\n");
2230	}
2231	}
2232
2233
2234	static DECLCALLBACK(int) ich9pciConstruct(PPDMDEVINS pDevIns,
2235	int iInstance,
2236	PCFGMNODE pCfg)
2237	{
2238	int rc;
2239	Assert(iInstance == 0);
2240
2241	/*
2242	* Validate and read configuration.
2243	*/
2244	if (!CFGMR3AreValuesValid(pCfg,
2245	"IOAPIC\0"
2246	"GCEnabled\0"
2247	"R0Enabled\0"
2248	"McfgBase\0"
2249	"McfgLength\0"
2250	))
2251	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
2252
2253	/* query whether we got an IOAPIC */
2254	bool fUseIoApic;
2255	rc = CFGMR3QueryBoolDef(pCfg, "IOAPIC", &fUseIoApic, false);
2256	if (RT_FAILURE(rc))
2257	return PDMDEV_SET_ERROR(pDevIns, rc,
2258	N_("Configuration error: Failed to query boolean value \"IOAPIC\""));
2259
2260	/* check if RC code is enabled. */
2261	bool fGCEnabled;
2262	rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
2263	if (RT_FAILURE(rc))
2264	return PDMDEV_SET_ERROR(pDevIns, rc,
2265	N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
2266
2267	/* check if R0 code is enabled. */
2268	bool fR0Enabled;
2269	rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
2270	if (RT_FAILURE(rc))
2271	return PDMDEV_SET_ERROR(pDevIns, rc,
2272	N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
2273
2274	Log(("PCI: fUseIoApic=%RTbool fGCEnabled=%RTbool fR0Enabled=%RTbool\n", fUseIoApic, fGCEnabled, fR0Enabled));
2275
2276	/*
2277	* Init data.
2278	*/
2279	PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
2280	PPCIBUS pBus = &pGlobals->aPciBus;
2281	/* Zero out everything */
2282	memset(pGlobals, 0, sizeof(*pGlobals));
2283	/* And fill values */
2284	if (!fUseIoApic)
2285	return PDMDEV_SET_ERROR(pDevIns, rc,
2286	N_("Must use IO-APIC with ICH9 chipset"));
2287	rc = CFGMR3QueryU64Def(pCfg, "McfgBase", &pGlobals->u64PciConfigMMioAddress, 0);
2288	if (RT_FAILURE(rc))
2289	return PDMDEV_SET_ERROR(pDevIns, rc,
2290	N_("Configuration error: Failed to read \"McfgBase\""));
2291	rc = CFGMR3QueryU64Def(pCfg, "McfgLength", &pGlobals->u64PciConfigMMioLength, 0);
2292	if (RT_FAILURE(rc))
2293	return PDMDEV_SET_ERROR(pDevIns, rc,
2294	N_("Configuration error: Failed to read \"McfgLength\""));
2295
2296	pGlobals->pDevInsR3 = pDevIns;
2297	pGlobals->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2298	pGlobals->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2299
2300	pGlobals->aPciBus.pDevInsR3 = pDevIns;
2301	pGlobals->aPciBus.pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2302	pGlobals->aPciBus.pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2303	pGlobals->aPciBus.papBridgesR3 = (PPCIDEVICE )PDMDevHlpMMHeapAllocZ(pDevIns, sizeof(PPCIDEVICE) RT_ELEMENTS(pGlobals->aPciBus.apDevices));
2304
2305	/*
2306	* Register bus
2307	*/
2308	PDMPCIBUSREG PciBusReg;
2309	PciBusReg.u32Version = PDM_PCIBUSREG_VERSION;
2310	PciBusReg.pfnRegisterR3 = ich9pciRegister;
2311	PciBusReg.pfnRegisterMsiR3 = ich9pciRegisterMsi;
2312	PciBusReg.pfnIORegionRegisterR3 = ich9pciIORegionRegister;
2313	PciBusReg.pfnSetConfigCallbacksR3 = ich9pciSetConfigCallbacks;
2314	PciBusReg.pfnSetIrqR3 = ich9pciSetIrq;
2315	PciBusReg.pfnSaveExecR3 = ich9pciGenericSaveExec;
2316	PciBusReg.pfnLoadExecR3 = ich9pciGenericLoadExec;
2317	PciBusReg.pfnFakePCIBIOSR3 = ich9pciFakePCIBIOS;
2318	PciBusReg.pszSetIrqRC = fGCEnabled ? "ich9pciSetIrq" : NULL;
2319	PciBusReg.pszSetIrqR0 = fR0Enabled ? "ich9pciSetIrq" : NULL;
2320	rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBus->pPciHlpR3);
2321	if (RT_FAILURE(rc))
2322	return PDMDEV_SET_ERROR(pDevIns, rc,
2323	N_("Failed to register ourselves as a PCI Bus"));
2324	if (pBus->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
2325	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
2326	N_("PCI helper version mismatch; got %#x expected %#x"),
2327	pBus->pPciHlpR3->u32Version, PDM_PCIHLPR3_VERSION);
2328
2329	pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
2330	pBus->pPciHlpR0 = pBus->pPciHlpR3->pfnGetR0Helpers(pDevIns);
2331
2332	/*
2333	* Fill in PCI configs and add them to the bus.
2334	*/
2335
2336	/**
2337	* We emulate 82801IB ICH9 IO chip used in Q35,
2338	* see http://ark.intel.com/Product.aspx?id=31892
2339	*
2340	* Stepping S-Spec Top Marking
2341	*
2342	* A2 SLA9M NH82801IB
2343	*/
2344	/* Host bridge device */
2345	/* @todo: move to separate driver? */
2346	PCIDevSetVendorId( &pBus->aPciDev, 0x8086); /* Intel */
2347	PCIDevSetDeviceId( &pBus->aPciDev, 0x244e); /* Desktop */
2348	PCIDevSetRevisionId(&pBus->aPciDev, 0x92); /* rev. A2 */
2349	PCIDevSetClassBase( &pBus->aPciDev, 0x06); /* bridge */
2350	PCIDevSetClassSub( &pBus->aPciDev, 0x04); /* Host/PCI bridge */
2351	PCIDevSetClassProg( &pBus->aPciDev, 0x01); /* Supports subtractive decoding. */
2352	PCIDevSetHeaderType(&pBus->aPciDev, 0x01); /* bridge */
2353	PCIDevSetWord(&pBus->aPciDev, VBOX_PCI_SEC_STATUS, 0x0280); /* secondary status */
2354	PCIDevSetDWord(&pBus->aPciDev, 0x4c, 0x00001200); /* Bridge policy configuration */
2355	PCIDevSetStatus (&pBus->aPciDev, VBOX_PCI_STATUS_CAP_LIST);
2356	PCIDevSetCapabilityList(&pBus->aPciDev, 0x50);
2357	/* capability */
2358	PCIDevSetWord(&pBus->aPciDev, 0x50, VBOX_PCI_CAP_ID_SSVID);
2359	PCIDevSetDWord(&pBus->aPciDev, 0x54, 0x00000000); /* Subsystem vendor ids */
2360
2361	pBus->aPciDev.pDevIns = pDevIns;
2362	/* We register Host<->PCI controller on the bus */
2363	ich9pciRegisterInternal(pBus, -1, &pBus->aPciDev, "i82801");
2364
2365	/*
2366	* Register I/O ports and save state.
2367	*/
2368	rc = PDMDevHlpIOPortRegister(pDevIns, 0x0cf8, 1, NULL, ich9pciIOPortAddressWrite, ich9pciIOPortAddressRead, NULL, NULL, "ICH9 (PCI)");
2369	if (RT_FAILURE(rc))
2370	return rc;
2371	rc = PDMDevHlpIOPortRegister(pDevIns, 0x0cfc, 4, NULL, ich9pciIOPortDataWrite, ich9pciIOPortDataRead, NULL, NULL, "ICH9 (PCI)");
2372	if (RT_FAILURE(rc))
2373	return rc;
2374	if (fGCEnabled)
2375	{
2376	rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x0cf8, 1, NIL_RTGCPTR, "ich9pciIOPortAddressWrite", "ich9pciIOPortAddressRead", NULL, NULL, "ICH9 (PCI)");
2377	if (RT_FAILURE(rc))
2378	return rc;
2379	rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x0cfc, 4, NIL_RTGCPTR, "ich9pciIOPortDataWrite", "ich9pciIOPortDataRead", NULL, NULL, "ICH9 (PCI)");
2380	if (RT_FAILURE(rc))
2381	return rc;
2382	}
2383	if (fR0Enabled)
2384	{
2385	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x0cf8, 1, NIL_RTR0PTR, "ich9pciIOPortAddressWrite", "ich9pciIOPortAddressRead", NULL, NULL, "ICH9 (PCI)");
2386	if (RT_FAILURE(rc))
2387	return rc;
2388	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x0cfc, 4, NIL_RTR0PTR, "ich9pciIOPortDataWrite", "ich9pciIOPortDataRead", NULL, NULL, "ICH9 (PCI)");
2389	if (RT_FAILURE(rc))
2390	return rc;
2391	}
2392
2393	if (pGlobals->u64PciConfigMMioAddress != 0)
2394	{
2395	rc = PDMDevHlpMMIORegister(pDevIns,
2396	pGlobals->u64PciConfigMMioAddress,
2397	pGlobals->u64PciConfigMMioLength,
2398	0,
2399	ich9pciMcfgMMIOWrite,
2400	ich9pciMcfgMMIORead,
2401	NULL /* fill */,
2402	"MCFG ranges");
2403	if (RT_FAILURE(rc))
2404	{
2405	AssertMsgRC(rc, ("Cannot register MCFG MMIO: %Rrc\n", rc));
2406	return rc;
2407	}
2408
2409	if (fGCEnabled)
2410	{
2411
2412	rc = PDMDevHlpMMIORegisterRC(pDevIns,
2413	pGlobals->u64PciConfigMMioAddress,
2414	pGlobals->u64PciConfigMMioLength,
2415	0,
2416	"ich9pciMcfgMMIOWrite",
2417	"ich9pciMcfgMMIORead",
2418	NULL /* fill */);
2419	if (RT_FAILURE(rc))
2420	{
2421	AssertMsgRC(rc, ("Cannot register MCFG MMIO (GC): %Rrc\n", rc));
2422	return rc;
2423	}
2424	}
2425
2426
2427	if (fR0Enabled)
2428	{
2429
2430	rc = PDMDevHlpMMIORegisterR0(pDevIns,
2431	pGlobals->u64PciConfigMMioAddress,
2432	pGlobals->u64PciConfigMMioLength,
2433	0,
2434	"ich9pciMcfgMMIOWrite",
2435	"ich9pciMcfgMMIORead",
2436	NULL /* fill */);
2437	if (RT_FAILURE(rc))
2438	{
2439	AssertMsgRC(rc, ("Cannot register MCFG MMIO (R0): %Rrc\n", rc));
2440	return rc;
2441	}
2442	}
2443	}
2444
2445	rc = PDMDevHlpSSMRegisterEx(pDevIns, VBOX_ICH9PCI_SAVED_STATE_VERSION_CURRENT,
2446	sizeof(pBus) + 16128, "pgm",
2447	NULL, NULL, NULL,
2448	NULL, ich9pciR3SaveExec, NULL,
2449	NULL, ich9pciR3LoadExec, NULL);
2450	if (RT_FAILURE(rc))
2451	return rc;
2452
2453
2454	/** @todo: other chipset devices shall be registered too */
2455	/** @todo: what to with bridges? */
2456
2457	PDMDevHlpDBGFInfoRegister(pDevIns, "pci", "Display PCI bus status. (no arguments)", ich9pciInfo);
2458
2459	return VINF_SUCCESS;
2460	}
2461
2462	static void ich9pciResetDevice(PPCIDEVICE pDev)
2463	{
2464	PCIDevSetCommand(pDev,
2465	PCIDevGetCommand(pDev)
2466	&
2467	~(VBOX_PCI_COMMAND_IO \|
2468	VBOX_PCI_COMMAND_MEMORY \|
2469	VBOX_PCI_COMMAND_MASTER));
2470
2471	/* Bridge device reset handlers processed later */
2472	if (!PCIIsPci2PciBridge(pDev))
2473	{
2474	PCIDevSetByte(pDev, VBOX_PCI_CACHE_LINE_SIZE, 0x0);
2475	PCIDevSetInterruptLine(pDev, 0x0);
2476	}
2477	/* Clear regions too ? */
2478	}
2479
2480
2481	/**
2482	* @copydoc FNPDMDEVRESET
2483	*/
2484	static DECLCALLBACK(void) ich9pciReset(PPDMDEVINS pDevIns)
2485	{
2486	PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
2487	PPCIBUS pBus = &pGlobals->aPciBus;
2488
2489	/* PCI-specific reset for each device. */
2490	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
2491	{
2492	if (pBus->apDevices[i])
2493	ich9pciResetDevice(pBus->apDevices[i]);
2494	}
2495
2496	for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
2497	{
2498	if (pBus->papBridgesR3[iBridge])
2499	ich9pcibridgeReset(pBus->papBridgesR3[iBridge]->pDevIns);
2500	}
2501
2502	ich9pciFakePCIBIOS(pDevIns);
2503	}
2504
2505	static void ich9pciRelocateDevice(PPCIDEVICE pDev, RTGCINTPTR offDelta)
2506	{
2507	if (pDev)
2508	{
2509	pDev->Int.s.pBusRC += offDelta;
2510	if (pDev->Int.s.pMsixPageRC)
2511	pDev->Int.s.pMsixPageRC += offDelta;
2512	}
2513	}
2514
2515	/**
2516	* @copydoc FNPDMDEVRELOCATE
2517	*/
2518	static DECLCALLBACK(void) ich9pciRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
2519	{
2520	PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
2521	PPCIBUS pBus = &pGlobals->aPciBus;
2522	pGlobals->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2523
2524	pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
2525	pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2526
2527	/* Relocate RC pointers for the attached pci devices. */
2528	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
2529	ich9pciRelocateDevice(pBus->apDevices[i], offDelta);
2530
2531	}
2532
2533	/**
2534	* @interface_method_impl{PDMDEVREG,pfnConstruct}
2535	*/
2536	static DECLCALLBACK(int) ich9pcibridgeConstruct(PPDMDEVINS pDevIns,
2537	int iInstance,
2538	PCFGMNODE pCfg)
2539	{
2540	int rc;
2541
2542	/*
2543	* Validate and read configuration.
2544	*/
2545	if (!CFGMR3AreValuesValid(pCfg, "GCEnabled\0" "R0Enabled\0"))
2546	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
2547
2548	/* check if RC code is enabled. */
2549	bool fGCEnabled;
2550	rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
2551	if (RT_FAILURE(rc))
2552	return PDMDEV_SET_ERROR(pDevIns, rc,
2553	N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
2554
2555	/* check if R0 code is enabled. */
2556	bool fR0Enabled;
2557	rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
2558	if (RT_FAILURE(rc))
2559	return PDMDEV_SET_ERROR(pDevIns, rc,
2560	N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
2561	Log(("PCI: fGCEnabled=%RTbool fR0Enabled=%RTbool\n", fGCEnabled, fR0Enabled));
2562
2563	/*
2564	* Init data and register the PCI bus.
2565	*/
2566	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
2567	pBus->pDevInsR3 = pDevIns;
2568	pBus->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2569	pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2570	pBus->papBridgesR3 = (PPCIDEVICE )PDMDevHlpMMHeapAllocZ(pDevIns, sizeof(PPCIDEVICE) RT_ELEMENTS(pBus->apDevices));
2571
2572	PDMPCIBUSREG PciBusReg;
2573	PciBusReg.u32Version = PDM_PCIBUSREG_VERSION;
2574	PciBusReg.pfnRegisterR3 = ich9pcibridgeRegister;
2575	PciBusReg.pfnRegisterMsiR3 = ich9pciRegisterMsi;
2576	PciBusReg.pfnIORegionRegisterR3 = ich9pciIORegionRegister;
2577	PciBusReg.pfnSetConfigCallbacksR3 = ich9pciSetConfigCallbacks;
2578	PciBusReg.pfnSetIrqR3 = ich9pcibridgeSetIrq;
2579	PciBusReg.pfnSaveExecR3 = ich9pciGenericSaveExec;
2580	PciBusReg.pfnLoadExecR3 = ich9pciGenericLoadExec;
2581	PciBusReg.pfnFakePCIBIOSR3 = NULL; /* Only needed for the first bus. */
2582	PciBusReg.pszSetIrqRC = fGCEnabled ? "ich9pcibridgeSetIrq" : NULL;
2583	PciBusReg.pszSetIrqR0 = fR0Enabled ? "ich9pcibridgeSetIrq" : NULL;
2584	rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBus->pPciHlpR3);
2585	if (RT_FAILURE(rc))
2586	return PDMDEV_SET_ERROR(pDevIns, rc,
2587	N_("Failed to register ourselves as a PCI Bus"));
2588	if (pBus->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
2589	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
2590	N_("PCI helper version mismatch; got %#x expected %#x"),
2591	pBus->pPciHlpR3->u32Version, PDM_PCIHLPR3_VERSION);
2592
2593	pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
2594	pBus->pPciHlpR0 = pBus->pPciHlpR3->pfnGetR0Helpers(pDevIns);
2595
2596	/*
2597	* Fill in PCI configs and add them to the bus.
2598	*/
2599	PCIDevSetVendorId( &pBus->aPciDev, 0x8086); /* Intel */
2600	PCIDevSetDeviceId( &pBus->aPciDev, 0x2448); /* 82801 Mobile PCI bridge. */
2601	PCIDevSetRevisionId(&pBus->aPciDev, 0xf2);
2602	PCIDevSetClassSub( &pBus->aPciDev, 0x04); /* pci2pci */
2603	PCIDevSetClassBase( &pBus->aPciDev, 0x06); /* PCI_bridge */
2604	PCIDevSetClassProg( &pBus->aPciDev, 0x01); /* Supports subtractive decoding. */
2605	PCIDevSetHeaderType(&pBus->aPciDev, 0x01); /* Single function device which adheres to the PCI-to-PCI bridge spec. */
2606	PCIDevSetCommand( &pBus->aPciDev, 0x00);
2607	PCIDevSetStatus( &pBus->aPciDev, 0x20); /* 66MHz Capable. */
2608	PCIDevSetInterruptLine(&pBus->aPciDev, 0x00); /* This device does not assert interrupts. */
2609
2610	/*
2611	* This device does not generate interrupts. Interrupt delivery from
2612	* devices attached to the bus is unaffected.
2613	*/
2614	PCIDevSetInterruptPin (&pBus->aPciDev, 0x00);
2615
2616	pBus->aPciDev.pDevIns = pDevIns;
2617
2618	/* Bridge-specific data */
2619	PCISetPci2PciBridge(&pBus->aPciDev);
2620	pBus->aPciDev.Int.s.pfnBridgeConfigRead = ich9pcibridgeConfigRead;
2621	pBus->aPciDev.Int.s.pfnBridgeConfigWrite = ich9pcibridgeConfigWrite;
2622
2623	/*
2624	* Register this PCI bridge. The called function will take care on which bus we will get registered.
2625	*/
2626	rc = PDMDevHlpPCIRegister (pDevIns, &pBus->aPciDev);
2627	if (RT_FAILURE(rc))
2628	return rc;
2629
2630	/*
2631	* The iBus property doesn't really represent the bus number
2632	* because the guest and the BIOS can choose different bus numbers
2633	* for them.
2634	* The bus number is mainly for the setIrq function to indicate
2635	* when the host bus is reached which will have iBus = 0.
2636	* That's why the + 1.
2637	*/
2638	pBus->iBus = iInstance + 1;
2639
2640	/*
2641	* Register SSM handlers. We use the same saved state version as for the host bridge
2642	* to make changes easier.
2643	*/
2644	rc = PDMDevHlpSSMRegisterEx(pDevIns, VBOX_ICH9PCI_SAVED_STATE_VERSION_CURRENT,
2645	sizeof(pBus) + 16128,
2646	"pgm" /* before */,
2647	NULL, NULL, NULL,
2648	NULL, ich9pcibridgeR3SaveExec, NULL,
2649	NULL, ich9pcibridgeR3LoadExec, NULL);
2650	if (RT_FAILURE(rc))
2651	return rc;
2652
2653
2654	return VINF_SUCCESS;
2655	}
2656
2657	/**
2658	* @copydoc FNPDMDEVRESET
2659	*/
2660	static void ich9pcibridgeReset(PPDMDEVINS pDevIns)
2661	{
2662	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
2663
2664	/* Reset config space to default values. */
2665	PCIDevSetByte(&pBus->aPciDev, VBOX_PCI_PRIMARY_BUS, 0);
2666	PCIDevSetByte(&pBus->aPciDev, VBOX_PCI_SECONDARY_BUS, 0);
2667	PCIDevSetByte(&pBus->aPciDev, VBOX_PCI_SUBORDINATE_BUS, 0);
2668
2669	/* PCI-specific reset for each device. */
2670	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
2671	{
2672	if (pBus->apDevices[i])
2673	ich9pciResetDevice(pBus->apDevices[i]);
2674	}
2675	}
2676
2677
2678	/**
2679	* @copydoc FNPDMDEVRELOCATE
2680	*/
2681	static DECLCALLBACK(void) ich9pcibridgeRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
2682	{
2683	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
2684	pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2685
2686	/* Relocate RC pointers for the attached pci devices. */
2687	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
2688	ich9pciRelocateDevice(pBus->apDevices[i], offDelta);
2689	}
2690
2691	/**
2692	* The PCI bus device registration structure.
2693	*/
2694	const PDMDEVREG g_DevicePciIch9 =
2695	{
2696	/* u32Version */
2697	PDM_DEVREG_VERSION,
2698	/* szName */
2699	"ich9pci",
2700	/* szRCMod */
2701	"VBoxDDGC.gc",
2702	/* szR0Mod */
2703	"VBoxDDR0.r0",
2704	/* pszDescription */
2705	"ICH9 PCI bridge",
2706	/* fFlags */
2707	PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
2708	/* fClass */
2709	PDM_DEVREG_CLASS_BUS_PCI \| PDM_DEVREG_CLASS_BUS_ISA,
2710	/* cMaxInstances */
2711	1,
2712	/* cbInstance */
2713	sizeof(PCIGLOBALS),
2714	/* pfnConstruct */
2715	ich9pciConstruct,
2716	/* pfnDestruct */
2717	NULL,
2718	/* pfnRelocate */
2719	ich9pciRelocate,
2720	/* pfnIOCtl */
2721	NULL,
2722	/* pfnPowerOn */
2723	NULL,
2724	/* pfnReset */
2725	ich9pciReset,
2726	/* pfnSuspend */
2727	NULL,
2728	/* pfnResume */
2729	NULL,
2730	/* pfnAttach */
2731	NULL,
2732	/* pfnDetach */
2733	NULL,
2734	/* pfnQueryInterface */
2735	NULL,
2736	/* pfnInitComplete */
2737	NULL,
2738	/* pfnPowerOff */
2739	NULL,
2740	/* pfnSoftReset */
2741	NULL,
2742	/* u32VersionEnd */
2743	PDM_DEVREG_VERSION
2744	};
2745
2746	/**
2747	* The device registration structure
2748	* for the PCI-to-PCI bridge.
2749	*/
2750	const PDMDEVREG g_DevicePciIch9Bridge =
2751	{
2752	/* u32Version */
2753	PDM_DEVREG_VERSION,
2754	/* szName */
2755	"ich9pcibridge",
2756	/* szRCMod */
2757	"VBoxDDGC.gc",
2758	/* szR0Mod */
2759	"VBoxDDR0.r0",
2760	/* pszDescription */
2761	"ICH9 PCI to PCI bridge",
2762	/* fFlags */
2763	PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
2764	/* fClass */
2765	PDM_DEVREG_CLASS_BUS_PCI,
2766	/* cMaxInstances */
2767	~0,
2768	/* cbInstance */
2769	sizeof(PCIBUS),
2770	/* pfnConstruct */
2771	ich9pcibridgeConstruct,
2772	/* pfnDestruct */
2773	NULL,
2774	/* pfnRelocate */
2775	ich9pcibridgeRelocate,
2776	/* pfnIOCtl */
2777	NULL,
2778	/* pfnPowerOn */
2779	NULL,
2780	/* pfnReset */
2781	NULL, /* Must be NULL, to make sure only bus driver handles reset */
2782	/* pfnSuspend */
2783	NULL,
2784	/* pfnResume */
2785	NULL,
2786	/* pfnAttach */
2787	NULL,
2788	/* pfnDetach */
2789	NULL,
2790	/* pfnQueryInterface */
2791	NULL,
2792	/* pfnInitComplete */
2793	NULL,
2794	/* pfnPowerOff */
2795	NULL,
2796	/* pfnSoftReset */
2797	NULL,
2798	/* u32VersionEnd */
2799	PDM_DEVREG_VERSION
2800	};
2801
2802	#endif /* IN_RING3 */
2803	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */

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source: vbox/trunk/src/VBox/Devices/Bus/DevPciIch9.cpp@ 34836

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