DevPciIch9.cpp@ 35753

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1	/* $Id: DevPciIch9.cpp 35753 2011-01-28 10:58:06Z vboxsync $ */
2	/** @file
3	* DevPCI - ICH9 southbridge PCI bus emulation Device.
4	*/
5
6	/*
7	* Copyright (C) 2010 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/*******************************************************************************
19	* Header Files *
20	*******************************************************************************/
21	#define LOG_GROUP LOG_GROUP_DEV_PCI
22	/* Hack to get PCIDEVICEINT declare at the right point - include "PCIInternal.h". */
23	#define PCI_INCLUDE_PRIVATE
24	#include <VBox/pci.h>
25	#include <VBox/msi.h>
26	#include <VBox/vmm/pdmdev.h>
27	#include <iprt/asm.h>
28	#include <iprt/assert.h>
29	#include <iprt/string.h>
30	#ifdef IN_RING3
31	#include <iprt/alloc.h>
32	#endif
33
34	#include "VBoxDD.h"
35
36	#include "MsiCommon.h"
37
38	/**
39	* PCI Bus instance.
40	*/
41	typedef struct PCIBus
42	{
43	/** Bus number. */
44	int32_t iBus;
45	/** Number of bridges attached to the bus. */
46	uint32_t cBridges;
47
48	/** Array of PCI devices. We assume 32 slots, each with 8 functions. */
49	R3PTRTYPE(PPCIDEVICE) apDevices[256];
50	/** Array of bridges attached to the bus. */
51	R3PTRTYPE(PPCIDEVICE *) papBridgesR3;
52
53	/** R3 pointer to the device instance. */
54	PPDMDEVINSR3 pDevInsR3;
55	/** Pointer to the PCI R3 helpers. */
56	PCPDMPCIHLPR3 pPciHlpR3;
57
58	/** R0 pointer to the device instance. */
59	PPDMDEVINSR0 pDevInsR0;
60	/** Pointer to the PCI R0 helpers. */
61	PCPDMPCIHLPR0 pPciHlpR0;
62
63	/** RC pointer to the device instance. */
64	PPDMDEVINSRC pDevInsRC;
65	/** Pointer to the PCI RC helpers. */
66	PCPDMPCIHLPRC pPciHlpRC;
67
68	/** The PCI device for the PCI bridge. */
69	PCIDEVICE aPciDev;
70
71	} PCIBUS, *PPCIBUS;
72
73
74	/** @def PCI_APIC_IRQ_PINS
75	* Number of pins for interrupts if the APIC is used.
76	*/
77	#define PCI_APIC_IRQ_PINS 8
78
79	/**
80	* PCI Globals - This is the host-to-pci bridge and the root bus.
81	*/
82	typedef struct
83	{
84	/** R3 pointer to the device instance. */
85	PPDMDEVINSR3 pDevInsR3;
86	/** R0 pointer to the device instance. */
87	PPDMDEVINSR0 pDevInsR0;
88	/** RC pointer to the device instance. */
89	PPDMDEVINSRC pDevInsRC;
90
91	#if HC_ARCH_BITS == 64
92	uint32_t Alignment0;
93	#endif
94
95	/** PCI bus which is attached to the host-to-PCI bridge. */
96	PCIBUS aPciBus;
97
98
99	/** I/O APIC irq levels */
100	volatile uint32_t uaPciApicIrqLevels[PCI_APIC_IRQ_PINS];
101
102	#if 1 /* Will be moved into the BIOS soon. */
103	/** The next I/O port address which the PCI BIOS will use. */
104	uint32_t uPciBiosIo;
105	/** The next MMIO address which the PCI BIOS will use. */
106	uint32_t uPciBiosMmio;
107	/** Actual bus number. */
108	uint8_t uBus;
109	#endif
110	/* Physical address of PCI config space MMIO region */
111	uint64_t u64PciConfigMMioAddress;
112	/* Length of PCI config space MMIO region */
113	uint64_t u64PciConfigMMioLength;
114
115
116	/** Config register. */
117	uint32_t uConfigReg;
118	} PCIGLOBALS, *PPCIGLOBALS;
119
120
121	typedef struct {
122	uint8_t iBus;
123	uint8_t iDeviceFunc;
124	uint16_t iRegister;
125	} PciAddress;
126
127	/*******************************************************************************
128	* Defined Constants And Macros *
129	*******************************************************************************/
130
131	/** @def VBOX_ICH9PCI_SAVED_STATE_VERSION
132	* Saved state version of the ICH9 PCI bus device.
133	*/
134	#define VBOX_ICH9PCI_SAVED_STATE_VERSION_NOMSI 1
135	#define VBOX_ICH9PCI_SAVED_STATE_VERSION_MSI 2
136	#define VBOX_ICH9PCI_SAVED_STATE_VERSION_CURRENT VBOX_ICH9PCI_SAVED_STATE_VERSION_MSI
137
138	/** Converts a bus instance pointer to a device instance pointer. */
139	#define PCIBUS_2_DEVINS(pPciBus) ((pPciBus)->CTX_SUFF(pDevIns))
140	/** Converts a device instance pointer to a PCIGLOBALS pointer. */
141	#define DEVINS_2_PCIGLOBALS(pDevIns) ((PPCIGLOBALS)(PDMINS_2_DATA(pDevIns, PPCIGLOBALS)))
142	/** Converts a device instance pointer to a PCIBUS pointer. */
143	#define DEVINS_2_PCIBUS(pDevIns) ((PPCIBUS)(&PDMINS_2_DATA(pDevIns, PPCIGLOBALS)->aPciBus))
144	/** Converts a pointer to a PCI root bus instance to a PCIGLOBALS pointer.
145	*/
146	#define PCIROOTBUS_2_PCIGLOBALS(pPciBus) ( (PPCIGLOBALS)((uintptr_t)(pPciBus) - RT_OFFSETOF(PCIGLOBALS, aPciBus)) )
147
148
149	/** @def PCI_LOCK
150	* Acquires the PDM lock. This is a NOP if locking is disabled. */
151	/** @def PCI_UNLOCK
152	* Releases the PDM lock. This is a NOP if locking is disabled. */
153	#define PCI_LOCK(pDevIns, rc) \
154	do { \
155	int rc2 = DEVINS_2_PCIBUS(pDevIns)->CTX_SUFF(pPciHlp)->pfnLock((pDevIns), rc); \
156	if (rc2 != VINF_SUCCESS) \
157	return rc2; \
158	} while (0)
159	#define PCI_UNLOCK(pDevIns) \
160	DEVINS_2_PCIBUS(pDevIns)->CTX_SUFF(pPciHlp)->pfnUnlock(pDevIns)
161
162	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
163
164	RT_C_DECLS_BEGIN
165
166	PDMBOTHCBDECL(void) ich9pciSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel);
167	PDMBOTHCBDECL(void) ich9pcibridgeSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel);
168	PDMBOTHCBDECL(int) ich9pciIOPortAddressWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
169	PDMBOTHCBDECL(int) ich9pciIOPortAddressRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb);
170	PDMBOTHCBDECL(int) ich9pciIOPortDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
171	PDMBOTHCBDECL(int) ich9pciIOPortDataRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb);
172	PDMBOTHCBDECL(int) ich9pciMcfgMMIOWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb);
173	PDMBOTHCBDECL(int) ich9pciMcfgMMIORead (PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb);
174
175	RT_C_DECLS_END
176
177	/* Prototypes */
178	static void ich9pciSetIrqInternal(PPCIGLOBALS pGlobals, uint8_t uDevFn, PPCIDEVICE pPciDev, int iIrq, int iLevel);
179	#ifdef IN_RING3
180	static void ich9pcibridgeReset(PPDMDEVINS pDevIns);
181	static int ich9pciRegisterInternal(PPCIBUS pBus, int iDev, PPCIDEVICE pPciDev, const char *pszName);
182	static void ich9pciUpdateMappings(PCIDevice *pDev);
183	static DECLCALLBACK(uint32_t) ich9pciConfigReadDev(PCIDevice *aDev, uint32_t u32Address, unsigned len);
184	DECLINLINE(PPCIDEVICE) ich9pciFindBridge(PPCIBUS pBus, uint8_t iBus);
185	static void ich9pciBiosInitDevice(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint8_t cBridgeDepth, uint8_t *paBridgePositions);
186	#endif
187
188	// See 7.2.2. PCI Express Enhanced Configuration Mechanism for details of address
189	// mapping, we take n=6 approach
190	DECLINLINE(void) ich9pciPhysToPciAddr(PPCIGLOBALS pGlobals, RTGCPHYS GCPhysAddr, PciAddress* pPciAddr)
191	{
192	pPciAddr->iBus = (GCPhysAddr >> 20) & ((1<<6) - 1);
193	pPciAddr->iDeviceFunc = (GCPhysAddr >> 12) & ((1<<(5+3)) - 1); // 5 bits - device, 3 bits - function
194	pPciAddr->iRegister = (GCPhysAddr >> 0) & ((1<<(6+4+2)) - 1); // 6 bits - register, 4 bits - extended register, 2 bits -Byte Enable
195	}
196
197	DECLINLINE(void) ich9pciStateToPciAddr(PPCIGLOBALS pGlobals, RTGCPHYS addr, PciAddress* pPciAddr)
198	{
199	pPciAddr->iBus = (pGlobals->uConfigReg >> 16) & 0xff;
200	pPciAddr->iDeviceFunc = (pGlobals->uConfigReg >> 8) & 0xff;
201	pPciAddr->iRegister = (pGlobals->uConfigReg & 0xfc) \| (addr & 3);
202	}
203
204	PDMBOTHCBDECL(void) ich9pciSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel)
205	{
206	ich9pciSetIrqInternal(PDMINS_2_DATA(pDevIns, PPCIGLOBALS), pPciDev->devfn, pPciDev, iIrq, iLevel);
207	}
208
209	PDMBOTHCBDECL(void) ich9pcibridgeSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel)
210	{
211	/*
212	* The PCI-to-PCI bridge specification defines how the interrupt pins
213	* are routed from the secondary to the primary bus (see chapter 9).
214	* iIrq gives the interrupt pin the pci device asserted.
215	* We change iIrq here according to the spec and call the SetIrq function
216	* of our parent passing the device which asserted the interrupt instead of the device of the bridge.
217	*/
218	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
219	PPCIDEVICE pPciDevBus = pPciDev;
220	int iIrqPinBridge = iIrq;
221	uint8_t uDevFnBridge = 0;
222
223	/* Walk the chain until we reach the host bus. */
224	do
225	{
226	uDevFnBridge = pBus->aPciDev.devfn;
227	iIrqPinBridge = ((pPciDevBus->devfn >> 3) + iIrqPinBridge) & 3;
228
229	/* Get the parent. */
230	pBus = pBus->aPciDev.Int.s.CTX_SUFF(pBus);
231	pPciDevBus = &pBus->aPciDev;
232	} while (pBus->iBus != 0);
233
234	AssertMsgReturnVoid(pBus->iBus == 0, ("This is not the host pci bus iBus=%d\n", pBus->iBus));
235	ich9pciSetIrqInternal(PCIROOTBUS_2_PCIGLOBALS(pBus), uDevFnBridge, pPciDev, iIrqPinBridge, iLevel);
236	}
237
238	/**
239	* Port I/O Handler for PCI address OUT operations.
240	*
241	* @returns VBox status code.
242	*
243	* @param pDevIns The device instance.
244	* @param pvUser User argument - ignored.
245	* @param uPort Port number used for the OUT operation.
246	* @param u32 The value to output.
247	* @param cb The value size in bytes.
248	*/
249	PDMBOTHCBDECL(int) ich9pciIOPortAddressWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
250	{
251	Log(("ich9pciIOPortAddressWrite: Port=%#x u32=%#x cb=%d\n", Port, u32, cb));
252	NOREF(pvUser);
253	if (cb == 4)
254	{
255	PPCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
256
257	PCI_LOCK(pDevIns, VINF_IOM_HC_IOPORT_WRITE);
258	pThis->uConfigReg = u32 & ~3; /* Bits 0-1 are reserved and we silently clear them */
259	PCI_UNLOCK(pDevIns);
260	}
261
262	return VINF_SUCCESS;
263	}
264
265	/**
266	* Port I/O Handler for PCI address IN operations.
267	*
268	* @returns VBox status code.
269	*
270	* @param pDevIns The device instance.
271	* @param pvUser User argument - ignored.
272	* @param uPort Port number used for the IN operation.
273	* @param pu32 Where to store the result.
274	* @param cb Number of bytes read.
275	*/
276	PDMBOTHCBDECL(int) ich9pciIOPortAddressRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
277	{
278	NOREF(pvUser);
279	if (cb == 4)
280	{
281	PPCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
282	PCI_LOCK(pDevIns, VINF_IOM_HC_IOPORT_READ);
283	*pu32 = pThis->uConfigReg;
284	PCI_UNLOCK(pDevIns);
285	Log(("pciIOPortAddressRead: Port=%#x cb=%d -> %#x\n", Port, cb, *pu32));
286	return VINF_SUCCESS;
287	}
288
289	Log(("ich9pciIOPortAddressRead: Port=%#x cb=%d VERR_IOM_IOPORT_UNUSED\n", Port, cb));
290
291	return VERR_IOM_IOPORT_UNUSED;
292	}
293
294	static int ich9pciDataWriteAddr(PPCIGLOBALS pGlobals, PciAddress* pAddr,
295	uint32_t val, int cb, int rcReschedule)
296	{
297	int rc = VINF_SUCCESS;
298
299	if (pAddr->iRegister > 0xff)
300	{
301	LogRel(("PCI: attempt to write extended register: %x (%d) <- val\n", pAddr->iRegister, cb, val));
302	goto out;
303	}
304
305	if (pAddr->iBus != 0)
306	{
307	if (pGlobals->aPciBus.cBridges)
308	{
309	#ifdef IN_RING3 /** @todo do lookup in R0/RC too! */
310	PPCIDEVICE pBridgeDevice = ich9pciFindBridge(&pGlobals->aPciBus, pAddr->iBus);
311	if (pBridgeDevice)
312	{
313	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigWrite);
314	pBridgeDevice->Int.s.pfnBridgeConfigWrite(pBridgeDevice->pDevIns, pAddr->iBus, pAddr->iDeviceFunc, pAddr->iRegister, val, cb);
315	}
316	else
317	{
318	// do nothing, bridge not found
319	}
320	#else
321	rc = rcReschedule;
322	goto out;
323	#endif
324	}
325	}
326	else
327	{
328	if (pGlobals->aPciBus.apDevices[pAddr->iDeviceFunc])
329	{
330	#ifdef IN_RING3
331	R3PTRTYPE(PCIDevice *) aDev = pGlobals->aPciBus.apDevices[pAddr->iDeviceFunc];
332	Log(("ich9pciConfigWrite: %s: addr=%02x val=%08x len=%d\n", aDev->name, pAddr->iRegister, val, cb));
333	aDev->Int.s.pfnConfigWrite(aDev, pAddr->iRegister, val, cb);
334	#else
335	rc = rcReschedule;
336	goto out;
337	#endif
338	}
339	}
340
341	out:
342	Log2(("ich9pciDataWriteAddr: %02x:%02x:%02x reg %x(%d) %x %Rrc\n",
343	pAddr->iBus, pAddr->iDeviceFunc >> 3, pAddr->iDeviceFunc & 0x7, pAddr->iRegister,
344	cb, val, rc));
345
346	return rc;
347	}
348
349	static int ich9pciDataWrite(PPCIGLOBALS pGlobals, uint32_t addr, uint32_t val, int len)
350	{
351	PciAddress aPciAddr;
352
353	LogFlow(("ich9pciDataWrite: config=%08x val=%08x len=%d\n", pGlobals->uConfigReg, val, len));
354
355	if (!(pGlobals->uConfigReg & (1 << 31)))
356	return VINF_SUCCESS;
357
358	if ((pGlobals->uConfigReg & 0x3) != 0)
359	return VINF_SUCCESS;
360
361	/* Compute destination device */
362	ich9pciStateToPciAddr(pGlobals, addr, &aPciAddr);
363
364	return ich9pciDataWriteAddr(pGlobals, &aPciAddr, val, len, VINF_IOM_HC_IOPORT_WRITE);
365	}
366
367	static void ich9pciNoMem(void* ptr, int cb)
368	{
369	for (int i = 0; i < cb; i++)
370	((uint8_t*)ptr)[i] = 0xff;
371	}
372
373	/**
374	* Port I/O Handler for PCI data OUT operations.
375	*
376	* @returns VBox status code.
377	*
378	* @param pDevIns The device instance.
379	* @param pvUser User argument - ignored.
380	* @param uPort Port number used for the OUT operation.
381	* @param u32 The value to output.
382	* @param cb The value size in bytes.
383	*/
384	PDMBOTHCBDECL(int) ich9pciIOPortDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
385	{
386	Log(("pciIOPortDataWrite: Port=%#x u32=%#x cb=%d\n", Port, u32, cb));
387	NOREF(pvUser);
388	int rc = VINF_SUCCESS;
389	if (!(Port % cb))
390	{
391	PCI_LOCK(pDevIns, VINF_IOM_HC_IOPORT_WRITE);
392	rc = ich9pciDataWrite(PDMINS_2_DATA(pDevIns, PPCIGLOBALS), Port, u32, cb);
393	PCI_UNLOCK(pDevIns);
394	}
395	else
396	AssertMsgFailed(("Unaligned write to port %#x u32=%#x cb=%d\n", Port, u32, cb));
397	return rc;
398	}
399
400	static int ich9pciDataReadAddr(PPCIGLOBALS pGlobals, PciAddress* pPciAddr, int cb,
401	uint32_t *pu32, int rcReschedule)
402	{
403	int rc = VINF_SUCCESS;
404
405	if (pPciAddr->iRegister > 0xff)
406	{
407	LogRel(("PCI: attempt to read extended register: %x\n", pPciAddr->iRegister));
408	ich9pciNoMem(pu32, cb);
409	goto out;
410	}
411
412
413	if (pPciAddr->iBus != 0)
414	{
415	if (pGlobals->aPciBus.cBridges)
416	{
417	#ifdef IN_RING3 /** @todo do lookup in R0/RC too! */
418	PPCIDEVICE pBridgeDevice = ich9pciFindBridge(&pGlobals->aPciBus, pPciAddr->iBus);
419	if (pBridgeDevice)
420	{
421	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigRead);
422	*pu32 = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->pDevIns, pPciAddr->iBus, pPciAddr->iDeviceFunc, pPciAddr->iRegister, cb);
423	}
424	else
425	ich9pciNoMem(pu32, cb);
426	#else
427	rc = rcReschedule;
428	goto out;
429	#endif
430	} else
431	ich9pciNoMem(pu32, cb);
432	}
433	else
434	{
435	if (pGlobals->aPciBus.apDevices[pPciAddr->iDeviceFunc])
436	{
437	#ifdef IN_RING3
438	R3PTRTYPE(PCIDevice *) aDev = pGlobals->aPciBus.apDevices[pPciAddr->iDeviceFunc];
439	*pu32 = aDev->Int.s.pfnConfigRead(aDev, pPciAddr->iRegister, cb);
440	Log(("ich9pciDataReadAddr: %s: addr=%02x val=%08x len=%d\n", aDev->name, pPciAddr->iRegister, *pu32, cb));
441	#else
442	rc = rcReschedule;
443	goto out;
444	#endif
445	}
446	else
447	ich9pciNoMem(pu32, cb);
448	}
449
450	out:
451	Log2(("ich9pciDataReadAddr: %02x:%02x:%02x reg %x(%d) gave %x %Rrc\n",
452	pPciAddr->iBus, pPciAddr->iDeviceFunc >> 3, pPciAddr->iDeviceFunc & 0x7, pPciAddr->iRegister,
453	cb, *pu32, rc));
454
455	return rc;
456	}
457
458	static int ich9pciDataRead(PPCIGLOBALS pGlobals, uint32_t addr, int cb, uint32_t *pu32)
459	{
460	PciAddress aPciAddr;
461
462	LogFlow(("ich9pciDataRead: config=%x cb=%d\n", pGlobals->uConfigReg, cb));
463
464	*pu32 = 0xffffffff;
465
466	if (!(pGlobals->uConfigReg & (1 << 31)))
467	return VINF_SUCCESS;
468
469	if ((pGlobals->uConfigReg & 0x3) != 0)
470	return VINF_SUCCESS;
471
472	/* Compute destination device */
473	ich9pciStateToPciAddr(pGlobals, addr, &aPciAddr);
474
475	return ich9pciDataReadAddr(pGlobals, &aPciAddr, cb, pu32, VINF_IOM_HC_IOPORT_READ);
476	}
477
478	/**
479	* Port I/O Handler for PCI data IN operations.
480	*
481	* @returns VBox status code.
482	*
483	* @param pDevIns The device instance.
484	* @param pvUser User argument - ignored.
485	* @param uPort Port number used for the IN operation.
486	* @param pu32 Where to store the result.
487	* @param cb Number of bytes read.
488	*/
489	PDMBOTHCBDECL(int) ich9pciIOPortDataRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
490	{
491	NOREF(pvUser);
492	if (!(Port % cb))
493	{
494	PCI_LOCK(pDevIns, VINF_IOM_HC_IOPORT_READ);
495	int rc = ich9pciDataRead(PDMINS_2_DATA(pDevIns, PPCIGLOBALS), Port, cb, pu32);
496	PCI_UNLOCK(pDevIns);
497	Log(("pciIOPortDataRead: Port=%#x cb=%#x -> %#x (%Rrc)\n", Port, cb, *pu32, rc));
498	return rc;
499	}
500	AssertMsgFailed(("Unaligned read from port %#x cb=%d\n", Port, cb));
501	return VERR_IOM_IOPORT_UNUSED;
502	}
503
504	/* Compute mapping of PCI slot and IRQ number to APIC interrupt line */
505	DECLINLINE(int) ich9pciSlot2ApicIrq(uint8_t uSlot, int irq_num)
506	{
507	return (irq_num + uSlot) & 7;
508	}
509
510	/* return the global irq number corresponding to a given device irq
511	pin. We could also use the bus number to have a more precise
512	mapping. This is the implementation note described in the PCI spec chapter 2.2.6 */
513	DECLINLINE(int) ich9pciSlotGetPirq(uint8_t uBus, uint8_t uDevFn, int iIrqNum)
514	{
515	int iSlotAddend = (uDevFn >> 3) - 1;
516	return (iIrqNum + iSlotAddend) & 3;
517	}
518
519	/* irqs corresponding to PCI irqs A-D, must match pci_irq_list in rombios.c */
520	static const uint8_t aPciIrqs[4] = { 11, 10, 9, 5 };
521
522	/* Add one more level up request on APIC input line */
523	DECLINLINE(void) ich9pciApicLevelUp(PPCIGLOBALS pGlobals, int irq_num)
524	{
525	ASMAtomicIncU32(&pGlobals->uaPciApicIrqLevels[irq_num]);
526	}
527
528	/* Remove one level up request on APIC input line */
529	DECLINLINE(void) ich9pciApicLevelDown(PPCIGLOBALS pGlobals, int irq_num)
530	{
531	ASMAtomicDecU32(&pGlobals->uaPciApicIrqLevels[irq_num]);
532	}
533
534	static void ich9pciApicSetIrq(PPCIBUS pBus, uint8_t uDevFn, PCIDevice *pPciDev, int irq_num1, int iLevel, int iForcedIrq)
535	{
536	/* This is only allowed to be called with a pointer to the root bus. */
537	AssertMsg(pBus->iBus == 0, ("iBus=%u\n", pBus->iBus));
538
539	if (iForcedIrq == -1)
540	{
541	int apic_irq, apic_level;
542	PPCIGLOBALS pGlobals = PCIROOTBUS_2_PCIGLOBALS(pBus);
543	int irq_num = ich9pciSlot2ApicIrq(uDevFn >> 3, irq_num1);
544
545	if ((iLevel & PDM_IRQ_LEVEL_HIGH) == PDM_IRQ_LEVEL_HIGH)
546	ich9pciApicLevelUp(pGlobals, irq_num);
547	else if ((iLevel & PDM_IRQ_LEVEL_HIGH) == PDM_IRQ_LEVEL_LOW)
548	ich9pciApicLevelDown(pGlobals, irq_num);
549
550	apic_irq = irq_num + 0x10;
551	apic_level = pGlobals->uaPciApicIrqLevels[irq_num] != 0;
552	Log3(("ich9pciApicSetIrq: %s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d\n",
553	R3STRING(pPciDev->name), irq_num1, iLevel, apic_irq, apic_level, irq_num));
554	pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), apic_irq, apic_level);
555
556	if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP)
557	{
558	/**
559	* we raised it few lines above, as PDM_IRQ_LEVEL_FLIP_FLOP has
560	* PDM_IRQ_LEVEL_HIGH bit set
561	*/
562	ich9pciApicLevelDown(pGlobals, irq_num);
563	pPciDev->Int.s.uIrqPinState = PDM_IRQ_LEVEL_LOW;
564	apic_level = pGlobals->uaPciApicIrqLevels[irq_num] != 0;
565	Log3(("ich9pciApicSetIrq: %s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d (flop)\n",
566	R3STRING(pPciDev->name), irq_num1, iLevel, apic_irq, apic_level, irq_num));
567	pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), apic_irq, apic_level);
568	}
569	} else {
570	Log3(("ich9pciApicSetIrq: (forced) %s: irq_num1=%d level=%d acpi_irq=%d\n",
571	R3STRING(pPciDev->name), irq_num1, iLevel, iForcedIrq));
572	pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), iForcedIrq, iLevel);
573	}
574	}
575
576	static void ich9pciSetIrqInternal(PPCIGLOBALS pGlobals, uint8_t uDevFn, PPCIDEVICE pPciDev, int iIrq, int iLevel)
577	{
578
579	if (PCIDevIsIntxDisabled(pPciDev))
580	{
581	if (MsiIsEnabled(pPciDev))
582	{
583	PPDMDEVINS pDevIns = pGlobals->aPciBus.CTX_SUFF(pDevIns);
584	MsiNotify(pDevIns, pGlobals->aPciBus.CTX_SUFF(pPciHlp), pPciDev, iIrq, iLevel);
585	}
586
587	if (MsixIsEnabled(pPciDev))
588	{
589	PPDMDEVINS pDevIns = pGlobals->aPciBus.CTX_SUFF(pDevIns);
590	MsixNotify(pDevIns, pGlobals->aPciBus.CTX_SUFF(pPciHlp), pPciDev, iIrq, iLevel);
591	}
592	return;
593	}
594
595	PPCIBUS pBus = &pGlobals->aPciBus;
596	const bool fIsAcpiDevice = PCIDevGetDeviceId(pPciDev) == 0x7113;
597
598	/* Check if the state changed. */
599	if (pPciDev->Int.s.uIrqPinState != iLevel)
600	{
601	pPciDev->Int.s.uIrqPinState = (iLevel & PDM_IRQ_LEVEL_HIGH);
602
603	/* Send interrupt to I/O APIC only now. */
604	if (fIsAcpiDevice)
605	/*
606	* ACPI needs special treatment since SCI is hardwired and
607	* should not be affected by PCI IRQ routing tables at the
608	* same time SCI IRQ is shared in PCI sense hence this
609	* kludge (i.e. we fetch the hardwired value from ACPIs
610	* PCI device configuration space).
611	*/
612	ich9pciApicSetIrq(pBus, uDevFn, pPciDev, -1, iLevel, PCIDevGetInterruptLine(pPciDev));
613	else
614	ich9pciApicSetIrq(pBus, uDevFn, pPciDev, iIrq, iLevel, -1);
615	}
616	}
617
618	PDMBOTHCBDECL(int) ich9pciMcfgMMIOWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb)
619	{
620	PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
621	PciAddress aDest;
622	uint32_t u32 = 0;
623
624	Log2(("ich9pciMcfgMMIOWrite: %RGp(%d) \n", GCPhysAddr, cb));
625
626	PCI_LOCK(pDevIns, VINF_IOM_HC_MMIO_WRITE);
627
628	ich9pciPhysToPciAddr(pGlobals, GCPhysAddr, &aDest);
629
630	switch (cb)
631	{
632	case 1:
633	u32 = (uint8_t)pv;
634	break;
635	case 2:
636	u32 = (uint16_t)pv;
637	break;
638	case 4:
639	u32 = (uint32_t)pv;
640	break;
641	default:
642	Assert(false);
643	break;
644	}
645	int rc = ich9pciDataWriteAddr(pGlobals, &aDest, u32, cb, VINF_IOM_HC_MMIO_WRITE);
646	PCI_UNLOCK(pDevIns);
647
648	return rc;
649	}
650
651	PDMBOTHCBDECL(int) ich9pciMcfgMMIORead (PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb)
652	{
653	PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
654	PciAddress aDest;
655	uint32_t rv;
656
657	LogFlow(("ich9pciMcfgMMIORead: %RGp(%d) \n", GCPhysAddr, cb));
658
659	PCI_LOCK(pDevIns, VINF_IOM_HC_MMIO_READ);
660
661	ich9pciPhysToPciAddr(pGlobals, GCPhysAddr, &aDest);
662
663	int rc = ich9pciDataReadAddr(pGlobals, &aDest, cb, &rv, VINF_IOM_HC_MMIO_READ);
664
665	if (RT_SUCCESS(rc))
666	{
667	switch (cb)
668	{
669	case 1:
670	(uint8_t)pv = (uint8_t)rv;
671	break;
672	case 2:
673	(uint16_t)pv = (uint16_t)rv;
674	break;
675	case 4:
676	(uint32_t)pv = (uint32_t)rv;
677	break;
678	default:
679	Assert(false);
680	break;
681	}
682	}
683	PCI_UNLOCK(pDevIns);
684
685	return rc;
686	}
687
688	#ifdef IN_RING3
689
690	DECLINLINE(PPCIDEVICE) ich9pciFindBridge(PPCIBUS pBus, uint8_t iBus)
691	{
692	/* Search for a fitting bridge. */
693	for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
694	{
695	/*
696	* Examine secondary and subordinate bus number.
697	* If the target bus is in the range we pass the request on to the bridge.
698	*/
699	PPCIDEVICE pBridgeTemp = pBus->papBridgesR3[iBridge];
700	AssertMsg(pBridgeTemp && PCIIsPci2PciBridge(pBridgeTemp),
701	("Device is not a PCI bridge but on the list of PCI bridges\n"));
702
703	if ( iBus >= PCIDevGetByte(pBridgeTemp, VBOX_PCI_SECONDARY_BUS)
704	&& iBus <= PCIDevGetByte(pBridgeTemp, VBOX_PCI_SUBORDINATE_BUS))
705	return pBridgeTemp;
706	}
707
708	/* Nothing found. */
709	return NULL;
710	}
711
712	DECLINLINE(uint32_t) ich9pciGetRegionReg(int iRegion)
713	{
714	return (iRegion == VBOX_PCI_ROM_SLOT) ?
715	VBOX_PCI_ROM_ADDRESS : (VBOX_PCI_BASE_ADDRESS_0 + iRegion * 4);
716	}
717
718	#define INVALID_PCI_ADDRESS ~0U
719
720	static int ich9pciUnmapRegion(PPCIDEVICE pDev, int iRegion)
721	{
722	PCIIORegion* pRegion = &pDev->Int.s.aIORegions[iRegion];
723	int rc = VINF_SUCCESS;
724	PPCIBUS pBus = pDev->Int.s.CTX_SUFF(pBus);
725
726	Assert (pRegion->size != 0);
727
728	if (pRegion->addr != INVALID_PCI_ADDRESS)
729	{
730	if (pRegion->type & PCI_ADDRESS_SPACE_IO)
731	{
732	/* Port IO */
733	rc = PDMDevHlpIOPortDeregister(pDev->pDevIns, pRegion->addr, pRegion->size);
734	AssertRC(rc);
735	}
736	else
737	{
738	RTGCPHYS GCPhysBase = pRegion->addr;
739	if (pBus->pPciHlpR3->pfnIsMMIO2Base(pBus->pDevInsR3, pDev->pDevIns, GCPhysBase))
740	{
741	/* unmap it. */
742	rc = pRegion->map_func(pDev, iRegion, NIL_RTGCPHYS, pRegion->size, (PCIADDRESSSPACE)(pRegion->type));
743	AssertRC(rc);
744	rc = PDMDevHlpMMIO2Unmap(pDev->pDevIns, iRegion, GCPhysBase);
745	}
746	else
747	rc = PDMDevHlpMMIODeregister(pDev->pDevIns, GCPhysBase, pRegion->size);
748	}
749
750	pRegion->addr = INVALID_PCI_ADDRESS;
751	}
752
753	return rc;
754	}
755
756	static void ich9pciUpdateMappings(PCIDevice* pDev)
757	{
758	PPCIBUS pBus = pDev->Int.s.CTX_SUFF(pBus);
759	uint32_t uLast, uNew;
760
761	int iCmd = PCIDevGetCommand(pDev);
762	for (int iRegion = 0; iRegion < PCI_NUM_REGIONS; iRegion++)
763	{
764	PCIIORegion* pRegion = &pDev->Int.s.aIORegions[iRegion];
765	uint32_t uConfigReg = ich9pciGetRegionReg(iRegion);
766	int32_t iRegionSize = pRegion->size;
767	int rc;
768
769	if (iRegionSize == 0)
770	continue;
771
772	AssertMsg((pRegion->type & PCI_ADDRESS_SPACE_BAR64) == 0, ("64-bit BARs not yet implemented\n"));
773
774	if (pRegion->type & PCI_ADDRESS_SPACE_IO)
775	{
776	/* port IO region */
777	if (iCmd & PCI_COMMAND_IOACCESS)
778	{
779	/* IO access allowed */
780	uNew = ich9pciConfigReadDev(pDev, uConfigReg, 4);
781	uNew &= ~(iRegionSize - 1);
782	uLast = uNew + iRegionSize - 1;
783	/* only 64K ioports on PC */
784	if (uLast <= uNew \|\| uNew == 0 \|\| uLast >= 0x10000)
785	uNew = INVALID_PCI_ADDRESS;
786	} else
787	uNew = INVALID_PCI_ADDRESS;
788	}
789	else
790	{
791	/* MMIO region */
792	if (iCmd & PCI_COMMAND_MEMACCESS)
793	{
794	uNew = ich9pciConfigReadDev(pDev, uConfigReg, 4);
795	/* the ROM slot has a specific enable bit */
796	if (iRegion == PCI_ROM_SLOT && !(uNew & 1))
797	uNew = INVALID_PCI_ADDRESS;
798	else
799	{
800	uNew &= ~(iRegionSize - 1);
801	uLast = uNew + iRegionSize - 1;
802	/* NOTE: we do not support wrapping */
803	/* XXX: as we cannot support really dynamic
804	mappings, we handle specific values as invalid
805	mappings. */
806	if (uLast <= uNew \|\| uNew == 0 \|\| uLast == INVALID_PCI_ADDRESS)
807	uNew = INVALID_PCI_ADDRESS;
808	}
809	} else
810	uNew = INVALID_PCI_ADDRESS;
811	}
812	/* now do the real mapping */
813	if (uNew != pRegion->addr)
814	{
815	if (pRegion->addr != INVALID_PCI_ADDRESS)
816	ich9pciUnmapRegion(pDev, iRegion);
817
818	pRegion->addr = uNew;
819	if (pRegion->addr != INVALID_PCI_ADDRESS)
820	{
821	/* finally, map the region */
822	rc = pRegion->map_func(pDev, iRegion,
823	pRegion->addr, pRegion->size,
824	(PCIADDRESSSPACE)(pRegion->type));
825	AssertRC(rc);
826	}
827	}
828	}
829	}
830
831	static DECLCALLBACK(int) ich9pciRegister(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, const char *pszName, int iDev)
832	{
833	PPCIBUS pBus = DEVINS_2_PCIBUS(pDevIns);
834
835	/*
836	* Check input.
837	*/
838	if ( !pszName
839	\|\| !pPciDev
840	\|\| iDev >= (int)RT_ELEMENTS(pBus->apDevices)
841	)
842	{
843	AssertMsgFailed(("Invalid argument! pszName=%s pPciDev=%p iDev=%d\n", pszName, pPciDev, iDev));
844	return VERR_INVALID_PARAMETER;
845	}
846
847	/*
848	* Register the device.
849	*/
850	return ich9pciRegisterInternal(pBus, iDev, pPciDev, pszName);
851	}
852
853
854	static DECLCALLBACK(int) ich9pciRegisterMsi(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PPDMMSIREG pMsiReg)
855	{
856	int rc;
857
858	rc = MsiInit(pPciDev, pMsiReg);
859	if (rc != VINF_SUCCESS)
860	return rc;
861
862	rc = MsixInit(pPciDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pPciHlp), pPciDev, pMsiReg);
863	if (rc != VINF_SUCCESS)
864	return rc;
865
866	return rc;
867	}
868
869
870	static DECLCALLBACK(int) ich9pcibridgeRegister(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, const char *pszName, int iDev)
871	{
872
873	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
874
875	/*
876	* Check input.
877	*/
878	if ( !pszName
879	\|\| !pPciDev
880	\|\| iDev >= (int)RT_ELEMENTS(pBus->apDevices))
881	{
882	AssertMsgFailed(("Invalid argument! pszName=%s pPciDev=%p iDev=%d\n", pszName, pPciDev, iDev));
883	return VERR_INVALID_PARAMETER;
884	}
885
886	/*
887	* Register the device.
888	*/
889	return ich9pciRegisterInternal(pBus, iDev, pPciDev, pszName);
890	}
891
892	static DECLCALLBACK(int) ich9pciIORegionRegister(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iRegion, uint32_t cbRegion, PCIADDRESSSPACE enmType, PFNPCIIOREGIONMAP pfnCallback)
893	{
894	/*
895	* Validate.
896	*/
897	AssertMsgReturn( enmType == PCI_ADDRESS_SPACE_MEM
898	\|\| enmType == PCI_ADDRESS_SPACE_IO
899	\|\| enmType == PCI_ADDRESS_SPACE_MEM_PREFETCH,
900	("Invalid enmType=%#x? Or was this a bitmask after all...\n", enmType),
901	VERR_INVALID_PARAMETER);
902	AssertMsgReturn((unsigned)iRegion < PCI_NUM_REGIONS,
903	("Invalid iRegion=%d PCI_NUM_REGIONS=%d\n", iRegion, PCI_NUM_REGIONS),
904	VERR_INVALID_PARAMETER);
905	int iLastSet = ASMBitLastSetU32(cbRegion);
906	AssertMsgReturn( iLastSet != 0
907	&& RT_BIT_32(iLastSet - 1) == cbRegion,
908	("Invalid cbRegion=%#x iLastSet=%#x (not a power of 2 or 0)\n", cbRegion, iLastSet),
909	VERR_INVALID_PARAMETER);
910
911	/*
912	* Register the I/O region.
913	*/
914	PPCIIOREGION pRegion = &pPciDev->Int.s.aIORegions[iRegion];
915	pRegion->addr = INVALID_PCI_ADDRESS;
916	pRegion->size = cbRegion;
917	pRegion->type = enmType;
918	pRegion->map_func = pfnCallback;
919
920	/* Set type in the config space. */
921	uint32_t u32Address = ich9pciGetRegionReg(iRegion);
922	uint32_t u32Value = (enmType == PCI_ADDRESS_SPACE_MEM_PREFETCH ? (1 << 3) : 0)
923	\| (enmType == PCI_ADDRESS_SPACE_IO ? 1 : 0);
924	PCIDevSetDWord(pPciDev, u32Address, u32Value);
925
926	return VINF_SUCCESS;
927	}
928
929	static DECLCALLBACK(void) ich9pciSetConfigCallbacks(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PFNPCICONFIGREAD pfnRead, PPFNPCICONFIGREAD ppfnReadOld,
930	PFNPCICONFIGWRITE pfnWrite, PPFNPCICONFIGWRITE ppfnWriteOld)
931	{
932	if (ppfnReadOld)
933	*ppfnReadOld = pPciDev->Int.s.pfnConfigRead;
934	pPciDev->Int.s.pfnConfigRead = pfnRead;
935
936	if (ppfnWriteOld)
937	*ppfnWriteOld = pPciDev->Int.s.pfnConfigWrite;
938	pPciDev->Int.s.pfnConfigWrite = pfnWrite;
939	}
940
941	/**
942	* Saves a state of the PCI device.
943	*
944	* @returns VBox status code.
945	* @param pDevIns Device instance of the PCI Bus.
946	* @param pPciDev Pointer to PCI device.
947	* @param pSSM The handle to save the state to.
948	*/
949	static DECLCALLBACK(int) ich9pciGenericSaveExec(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PSSMHANDLE pSSM)
950	{
951	Assert(!PCIIsPassthrough(pPciDev));
952	return SSMR3PutMem(pSSM, &pPciDev->config[0], sizeof(pPciDev->config));
953	}
954
955	static int ich9pciR3CommonSaveExec(PPCIBUS pBus, PSSMHANDLE pSSM)
956	{
957	/*
958	* Iterate thru all the devices.
959	*/
960	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
961	{
962	PPCIDEVICE pDev = pBus->apDevices[i];
963	if (pDev)
964	{
965	/* Device position */
966	SSMR3PutU32(pSSM, i);
967	/* PCI config registers */
968	SSMR3PutMem(pSSM, pDev->config, sizeof(pDev->config));
969
970	/* Device flags */
971	int rc = SSMR3PutU32(pSSM, pDev->Int.s.uFlags);
972	if (RT_FAILURE(rc))
973	return rc;
974
975	/* IRQ pin state */
976	rc = SSMR3PutS32(pSSM, pDev->Int.s.uIrqPinState);
977	if (RT_FAILURE(rc))
978	return rc;
979
980	/* MSI info */
981	rc = SSMR3PutU8(pSSM, pDev->Int.s.u8MsiCapOffset);
982	if (RT_FAILURE(rc))
983	return rc;
984	rc = SSMR3PutU8(pSSM, pDev->Int.s.u8MsiCapSize);
985	if (RT_FAILURE(rc))
986	return rc;
987
988	/* MSI-X info */
989	rc = SSMR3PutU8(pSSM, pDev->Int.s.u8MsixCapOffset);
990	if (RT_FAILURE(rc))
991	return rc;
992	rc = SSMR3PutU8(pSSM, pDev->Int.s.u8MsixCapSize);
993	if (RT_FAILURE(rc))
994	return rc;
995	/* Save MSI-X page state */
996	if (pDev->Int.s.u8MsixCapOffset != 0)
997	{
998	Assert(pDev->Int.s.pMsixPageR3 != NULL);
999	SSMR3PutMem(pSSM, pDev->Int.s.pMsixPageR3, 0x1000);
1000	if (RT_FAILURE(rc))
1001	return rc;
1002	}
1003	}
1004	}
1005	return SSMR3PutU32(pSSM, UINT32_MAX); /* terminator */
1006	}
1007
1008	static DECLCALLBACK(int) ich9pciR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
1009	{
1010	PPCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
1011
1012	/*
1013	* Bus state data.
1014	*/
1015	SSMR3PutU32(pSSM, pThis->uConfigReg);
1016
1017	/*
1018	* Save IRQ states.
1019	*/
1020	for (int i = 0; i < PCI_APIC_IRQ_PINS; i++)
1021	SSMR3PutU32(pSSM, pThis->uaPciApicIrqLevels[i]);
1022
1023	SSMR3PutU32(pSSM, ~0); /* separator */
1024
1025	return ich9pciR3CommonSaveExec(&pThis->aPciBus, pSSM);
1026	}
1027
1028
1029	static DECLCALLBACK(int) ich9pcibridgeR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
1030	{
1031	PPCIBUS pThis = PDMINS_2_DATA(pDevIns, PPCIBUS);
1032	return ich9pciR3CommonSaveExec(pThis, pSSM);
1033	}
1034
1035
1036	static void ich9pcibridgeConfigWrite(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice, uint32_t u32Address, uint32_t u32Value, unsigned cb)
1037	{
1038	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
1039
1040	LogFlowFunc((": pDevIns=%p iBus=%d iDevice=%d u32Address=%u u32Value=%u cb=%d\n", pDevIns, iBus, iDevice, u32Address, u32Value, cb));
1041
1042	/* If the current bus is not the target bus search for the bus which contains the device. */
1043	if (iBus != PCIDevGetByte(&pBus->aPciDev, VBOX_PCI_SECONDARY_BUS))
1044	{
1045	PPCIDEVICE pBridgeDevice = ich9pciFindBridge(pBus, iBus);
1046	if (pBridgeDevice)
1047	{
1048	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigWrite);
1049	pBridgeDevice->Int.s.pfnBridgeConfigWrite(pBridgeDevice->pDevIns, iBus, iDevice, u32Address, u32Value, cb);
1050	}
1051	}
1052	else
1053	{
1054	/* This is the target bus, pass the write to the device. */
1055	PPCIDEVICE pPciDev = pBus->apDevices[iDevice];
1056	if (pPciDev)
1057	{
1058	Log(("%s: %s: addr=%02x val=%08x len=%d\n", __FUNCTION__, pPciDev->name, u32Address, u32Value, cb));
1059	pPciDev->Int.s.pfnConfigWrite(pPciDev, u32Address, u32Value, cb);
1060	}
1061	}
1062	}
1063
1064	static uint32_t ich9pcibridgeConfigRead(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice, uint32_t u32Address, unsigned cb)
1065	{
1066	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
1067	uint32_t u32Value;
1068
1069	LogFlowFunc((": pDevIns=%p iBus=%d iDevice=%d u32Address=%u cb=%d\n", pDevIns, iBus, iDevice, u32Address, cb));
1070
1071	/* If the current bus is not the target bus search for the bus which contains the device. */
1072	if (iBus != PCIDevGetByte(&pBus->aPciDev, VBOX_PCI_SECONDARY_BUS))
1073	{
1074	PPCIDEVICE pBridgeDevice = ich9pciFindBridge(pBus, iBus);
1075	if (pBridgeDevice)
1076	{
1077	AssertPtr( pBridgeDevice->Int.s.pfnBridgeConfigRead);
1078	u32Value = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->pDevIns, iBus, iDevice, u32Address, cb);
1079	}
1080	else
1081	ich9pciNoMem(&u32Value, 4);
1082	}
1083	else
1084	{
1085	/* This is the target bus, pass the read to the device. */
1086	PPCIDEVICE pPciDev = pBus->apDevices[iDevice];
1087	if (pPciDev)
1088	{
1089	u32Value = pPciDev->Int.s.pfnConfigRead(pPciDev, u32Address, cb);
1090	Log(("%s: %s: u32Address=%02x u32Value=%08x cb=%d\n", __FUNCTION__, pPciDev->name, u32Address, u32Value, cb));
1091	}
1092	else
1093	ich9pciNoMem(&u32Value, 4);
1094	}
1095
1096	return u32Value;
1097	}
1098
1099
1100	/**
1101	* Common routine for restoring the config registers of a PCI device.
1102	*
1103	* @param pDev The PCI device.
1104	* @param pbSrcConfig The configuration register values to be loaded.
1105	* @param fIsBridge Whether this is a bridge device or not.
1106	*/
1107	static void pciR3CommonRestoreConfig(PPCIDEVICE pDev, uint8_t const *pbSrcConfig, bool fIsBridge)
1108	{
1109	/*
1110	* This table defines the fields for normal devices and bridge devices, and
1111	* the order in which they need to be restored.
1112	*/
1113	static const struct PciField
1114	{
1115	uint8_t off;
1116	uint8_t cb;
1117	uint8_t fWritable;
1118	uint8_t fBridge;
1119	const char *pszName;
1120	} s_aFields[] =
1121	{
1122	/* off,cb,fW,fB, pszName */
1123	{ VBOX_PCI_VENDOR_ID, 2, 0, 3, "VENDOR_ID" },
1124	{ VBOX_PCI_DEVICE_ID, 2, 0, 3, "DEVICE_ID" },
1125	{ VBOX_PCI_STATUS, 2, 1, 3, "STATUS" },
1126	{ VBOX_PCI_REVISION_ID, 1, 0, 3, "REVISION_ID" },
1127	{ VBOX_PCI_CLASS_PROG, 1, 0, 3, "CLASS_PROG" },
1128	{ VBOX_PCI_CLASS_SUB, 1, 0, 3, "CLASS_SUB" },
1129	{ VBOX_PCI_CLASS_BASE, 1, 0, 3, "CLASS_BASE" },
1130	{ VBOX_PCI_CACHE_LINE_SIZE, 1, 1, 3, "CACHE_LINE_SIZE" },
1131	{ VBOX_PCI_LATENCY_TIMER, 1, 1, 3, "LATENCY_TIMER" },
1132	{ VBOX_PCI_HEADER_TYPE, 1, 0, 3, "HEADER_TYPE" },
1133	{ VBOX_PCI_BIST, 1, 1, 3, "BIST" },
1134	{ VBOX_PCI_BASE_ADDRESS_0, 4, 1, 3, "BASE_ADDRESS_0" },
1135	{ VBOX_PCI_BASE_ADDRESS_1, 4, 1, 3, "BASE_ADDRESS_1" },
1136	{ VBOX_PCI_BASE_ADDRESS_2, 4, 1, 1, "BASE_ADDRESS_2" },
1137	{ VBOX_PCI_PRIMARY_BUS, 1, 1, 2, "PRIMARY_BUS" }, // fWritable = ??
1138	{ VBOX_PCI_SECONDARY_BUS, 1, 1, 2, "SECONDARY_BUS" }, // fWritable = ??
1139	{ VBOX_PCI_SUBORDINATE_BUS, 1, 1, 2, "SUBORDINATE_BUS" }, // fWritable = ??
1140	{ VBOX_PCI_SEC_LATENCY_TIMER, 1, 1, 2, "SEC_LATENCY_TIMER" }, // fWritable = ??
1141	{ VBOX_PCI_BASE_ADDRESS_3, 4, 1, 1, "BASE_ADDRESS_3" },
1142	{ VBOX_PCI_IO_BASE, 1, 1, 2, "IO_BASE" }, // fWritable = ??
1143	{ VBOX_PCI_IO_LIMIT, 1, 1, 2, "IO_LIMIT" }, // fWritable = ??
1144	{ VBOX_PCI_SEC_STATUS, 2, 1, 2, "SEC_STATUS" }, // fWritable = ??
1145	{ VBOX_PCI_BASE_ADDRESS_4, 4, 1, 1, "BASE_ADDRESS_4" },
1146	{ VBOX_PCI_MEMORY_BASE, 2, 1, 2, "MEMORY_BASE" }, // fWritable = ??
1147	{ VBOX_PCI_MEMORY_LIMIT, 2, 1, 2, "MEMORY_LIMIT" }, // fWritable = ??
1148	{ VBOX_PCI_BASE_ADDRESS_5, 4, 1, 1, "BASE_ADDRESS_5" },
1149	{ VBOX_PCI_PREF_MEMORY_BASE, 2, 1, 2, "PREF_MEMORY_BASE" }, // fWritable = ??
1150	{ VBOX_PCI_PREF_MEMORY_LIMIT, 2, 1, 2, "PREF_MEMORY_LIMIT" }, // fWritable = ??
1151	{ VBOX_PCI_CARDBUS_CIS, 4, 1, 1, "CARDBUS_CIS" }, // fWritable = ??
1152	{ VBOX_PCI_PREF_BASE_UPPER32, 4, 1, 2, "PREF_BASE_UPPER32" }, // fWritable = ??
1153	{ VBOX_PCI_SUBSYSTEM_VENDOR_ID, 2, 0, 1, "SUBSYSTEM_VENDOR_ID" },// fWritable = !?
1154	{ VBOX_PCI_PREF_LIMIT_UPPER32, 4, 1, 2, "PREF_LIMIT_UPPER32" },// fWritable = ??
1155	{ VBOX_PCI_SUBSYSTEM_ID, 2, 0, 1, "SUBSYSTEM_ID" }, // fWritable = !?
1156	{ VBOX_PCI_ROM_ADDRESS, 4, 1, 1, "ROM_ADDRESS" }, // fWritable = ?!
1157	{ VBOX_PCI_IO_BASE_UPPER16, 2, 1, 2, "IO_BASE_UPPER16" }, // fWritable = ?!
1158	{ VBOX_PCI_IO_LIMIT_UPPER16, 2, 1, 2, "IO_LIMIT_UPPER16" }, // fWritable = ?!
1159	{ VBOX_PCI_CAPABILITY_LIST, 4, 0, 3, "CAPABILITY_LIST" }, // fWritable = !? cb=!?
1160	{ VBOX_PCI_RESERVED_38, 4, 1, 1, "RESERVED_38" }, // ???
1161	{ VBOX_PCI_ROM_ADDRESS_BR, 4, 1, 2, "ROM_ADDRESS_BR" }, // fWritable = !? cb=!? fBridge=!?
1162	{ VBOX_PCI_INTERRUPT_LINE, 1, 1, 3, "INTERRUPT_LINE" }, // fBridge=??
1163	{ VBOX_PCI_INTERRUPT_PIN, 1, 0, 3, "INTERRUPT_PIN" }, // fBridge=??
1164	{ VBOX_PCI_MIN_GNT, 1, 0, 1, "MIN_GNT" },
1165	{ VBOX_PCI_BRIDGE_CONTROL, 2, 1, 2, "BRIDGE_CONTROL" }, // fWritable = !?
1166	{ VBOX_PCI_MAX_LAT, 1, 0, 1, "MAX_LAT" },
1167	/* The COMMAND register must come last as it requires the ADDRESS
1168	registers to be restored before we pretent to change it from 0 to
1169	whatever value the guest assigned it. */
1170	{ VBOX_PCI_COMMAND, 2, 1, 3, "COMMAND" },
1171	};
1172
1173	#ifdef RT_STRICT
1174	/* Check that we've got full register coverage. */
1175	uint32_t bmDevice[0x40 / 32];
1176	uint32_t bmBridge[0x40 / 32];
1177	RT_ZERO(bmDevice);
1178	RT_ZERO(bmBridge);
1179	for (uint32_t i = 0; i < RT_ELEMENTS(s_aFields); i++)
1180	{
1181	uint8_t off = s_aFields[i].off;
1182	uint8_t cb = s_aFields[i].cb;
1183	uint8_t f = s_aFields[i].fBridge;
1184	while (cb-- > 0)
1185	{
1186	if (f & 1) AssertMsg(!ASMBitTest(bmDevice, off), ("%#x\n", off));
1187	if (f & 2) AssertMsg(!ASMBitTest(bmBridge, off), ("%#x\n", off));
1188	if (f & 1) ASMBitSet(bmDevice, off);
1189	if (f & 2) ASMBitSet(bmBridge, off);
1190	off++;
1191	}
1192	}
1193	for (uint32_t off = 0; off < 0x40; off++)
1194	{
1195	AssertMsg(ASMBitTest(bmDevice, off), ("%#x\n", off));
1196	AssertMsg(ASMBitTest(bmBridge, off), ("%#x\n", off));
1197	}
1198	#endif
1199
1200	/*
1201	* Loop thru the fields covering the 64 bytes of standard registers.
1202	*/
1203	uint8_t const fBridge = fIsBridge ? 2 : 1;
1204	Assert(!PCIIsPassthrough(pDev));
1205	uint8_t *pbDstConfig = &pDev->config[0];
1206
1207	for (uint32_t i = 0; i < RT_ELEMENTS(s_aFields); i++)
1208	if (s_aFields[i].fBridge & fBridge)
1209	{
1210	uint8_t const off = s_aFields[i].off;
1211	uint8_t const cb = s_aFields[i].cb;
1212	uint32_t u32Src;
1213	uint32_t u32Dst;
1214	switch (cb)
1215	{
1216	case 1:
1217	u32Src = pbSrcConfig[off];
1218	u32Dst = pbDstConfig[off];
1219	break;
1220	case 2:
1221	u32Src = (uint16_t const )&pbSrcConfig[off];
1222	u32Dst = (uint16_t const )&pbDstConfig[off];
1223	break;
1224	case 4:
1225	u32Src = (uint32_t const )&pbSrcConfig[off];
1226	u32Dst = (uint32_t const )&pbDstConfig[off];
1227	break;
1228	default:
1229	AssertFailed();
1230	continue;
1231	}
1232
1233	if ( u32Src != u32Dst
1234	\|\| off == VBOX_PCI_COMMAND)
1235	{
1236	if (u32Src != u32Dst)
1237	{
1238	if (!s_aFields[i].fWritable)
1239	LogRel(("PCI: %8s/%u: %2u-bit field %s: %x -> %x - !READ ONLY!\n",
1240	pDev->name, pDev->pDevIns->iInstance, cb*8, s_aFields[i].pszName, u32Dst, u32Src));
1241	else
1242	LogRel(("PCI: %8s/%u: %2u-bit field %s: %x -> %x\n",
1243	pDev->name, pDev->pDevIns->iInstance, cb*8, s_aFields[i].pszName, u32Dst, u32Src));
1244	}
1245	if (off == VBOX_PCI_COMMAND)
1246	PCIDevSetCommand(pDev, 0); /* For remapping, see ich9pciR3CommonLoadExec. */
1247	pDev->Int.s.pfnConfigWrite(pDev, off, u32Src, cb);
1248	}
1249	}
1250
1251	/*
1252	* The device dependent registers.
1253	*
1254	* We will not use ConfigWrite here as we have no clue about the size
1255	* of the registers, so the device is responsible for correctly
1256	* restoring functionality governed by these registers.
1257	*/
1258	for (uint32_t off = 0x40; off < sizeof(pDev->config); off++)
1259	if (pbDstConfig[off] != pbSrcConfig[off])
1260	{
1261	LogRel(("PCI: %8s/%u: register %02x: %02x -> %02x\n",
1262	pDev->name, pDev->pDevIns->iInstance, off, pbDstConfig[off], pbSrcConfig[off])); /** @todo make this Log() later. */
1263	pbDstConfig[off] = pbSrcConfig[off];
1264	}
1265	}
1266
1267	/**
1268	* Common worker for ich9pciR3LoadExec and ich9pcibridgeR3LoadExec.
1269	*
1270	* @returns VBox status code.
1271	* @param pBus The bus which data is being loaded.
1272	* @param pSSM The saved state handle.
1273	* @param uVersion The data version.
1274	* @param uPass The pass.
1275	*/
1276	static DECLCALLBACK(int) ich9pciR3CommonLoadExec(PPCIBUS pBus, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1277	{
1278	uint32_t u32;
1279	uint32_t i;
1280	int rc;
1281
1282	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
1283
1284	/*
1285	* Iterate thru all the devices and write 0 to the COMMAND register so
1286	* that all the memory is unmapped before we start restoring the saved
1287	* mapping locations.
1288	*
1289	* The register value is restored afterwards so we can do proper
1290	* LogRels in pciR3CommonRestoreConfig.
1291	*/
1292	for (i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
1293	{
1294	PPCIDEVICE pDev = pBus->apDevices[i];
1295	if (pDev)
1296	{
1297	uint16_t u16 = PCIDevGetCommand(pDev);
1298	pDev->Int.s.pfnConfigWrite(pDev, VBOX_PCI_COMMAND, 0, 2);
1299	PCIDevSetCommand(pDev, u16);
1300	Assert(PCIDevGetCommand(pDev) == u16);
1301	}
1302	}
1303
1304	void* pvMsixPage = RTMemTmpAllocZ(0x1000);
1305	/*
1306	* Iterate all the devices.
1307	*/
1308	for (i = 0;; i++)
1309	{
1310	PPCIDEVICE pDev;
1311	PCIDEVICE DevTmp;
1312
1313	/* index / terminator */
1314	rc = SSMR3GetU32(pSSM, &u32);
1315	if (RT_FAILURE(rc))
1316	return rc;
1317	if (u32 == (uint32_t)~0)
1318	break;
1319	if ( u32 >= RT_ELEMENTS(pBus->apDevices)
1320	\|\| u32 < i)
1321	{
1322	AssertMsgFailed(("u32=%#x i=%#x\n", u32, i));
1323	goto out;
1324	}
1325
1326	/* skip forward to the device checking that no new devices are present. */
1327	for (; i < u32; i++)
1328	{
1329	pDev = pBus->apDevices[i];
1330	if (pDev)
1331	{
1332	LogRel(("New device in slot %#x, %s (vendor=%#06x device=%#06x)\n", i, pDev->name,
1333	PCIDevGetVendorId(pDev), PCIDevGetDeviceId(pDev)));
1334	if (SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT)
1335	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("New device in slot %#x, %s (vendor=%#06x device=%#06x)"),
1336	i, pDev->name, PCIDevGetVendorId(pDev), PCIDevGetDeviceId(pDev));
1337	}
1338	}
1339
1340	/* get the data */
1341	DevTmp.Int.s.uFlags = 0;
1342	DevTmp.Int.s.u8MsiCapOffset = 0;
1343	DevTmp.Int.s.u8MsiCapSize = 0;
1344	DevTmp.Int.s.u8MsixCapOffset = 0;
1345	DevTmp.Int.s.u8MsixCapSize = 0;
1346	DevTmp.Int.s.uIrqPinState = ~0; /* Invalid value in case we have an older saved state to force a state change in pciSetIrq. */
1347	SSMR3GetMem(pSSM, DevTmp.config, sizeof(DevTmp.config));
1348
1349	rc = SSMR3GetU32(pSSM, &DevTmp.Int.s.uFlags);
1350	if (RT_FAILURE(rc))
1351	goto out;
1352
1353	rc = SSMR3GetS32(pSSM, &DevTmp.Int.s.uIrqPinState);
1354	if (RT_FAILURE(rc))
1355	goto out;
1356
1357	rc = SSMR3GetU8(pSSM, &DevTmp.Int.s.u8MsiCapOffset);
1358	if (RT_FAILURE(rc))
1359	goto out;
1360
1361	rc = SSMR3GetU8(pSSM, &DevTmp.Int.s.u8MsiCapSize);
1362	if (RT_FAILURE(rc))
1363	goto out;
1364
1365	rc = SSMR3GetU8(pSSM, &DevTmp.Int.s.u8MsixCapOffset);
1366	if (RT_FAILURE(rc))
1367	goto out;
1368
1369	rc = SSMR3GetU8(pSSM, &DevTmp.Int.s.u8MsixCapSize);
1370	if (RT_FAILURE(rc))
1371	goto out;
1372
1373	/* Load MSI-X page state */
1374	if (DevTmp.Int.s.u8MsixCapOffset != 0)
1375	{
1376	Assert(pvMsixPage != NULL);
1377	SSMR3GetMem(pSSM, pvMsixPage, 0x1000);
1378	if (RT_FAILURE(rc))
1379	goto out;
1380	}
1381
1382	/* check that it's still around. */
1383	pDev = pBus->apDevices[i];
1384	if (!pDev)
1385	{
1386	LogRel(("Device in slot %#x has been removed! vendor=%#06x device=%#06x\n", i,
1387	PCIDevGetVendorId(&DevTmp), PCIDevGetDeviceId(&DevTmp)));
1388	if (SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT)
1389	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Device in slot %#x has been removed! vendor=%#06x device=%#06x"),
1390	i, PCIDevGetVendorId(&DevTmp), PCIDevGetDeviceId(&DevTmp));
1391	continue;
1392	}
1393
1394	/* match the vendor id assuming that this will never be changed. */
1395	if ( PCIDevGetVendorId(&DevTmp) != PCIDevGetVendorId(pDev))
1396	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Device in slot %#x (%s) vendor id mismatch! saved=%.4Rhxs current=%.4Rhxs"),
1397	i, pDev->name, PCIDevGetVendorId(&DevTmp), PCIDevGetVendorId(pDev));
1398
1399	/* commit the loaded device config. */
1400	Assert(!PCIIsPassthrough(pDev));
1401	pciR3CommonRestoreConfig(pDev, &DevTmp.config[0], false ); /** @todo fix bridge fun! */
1402
1403	pDev->Int.s.uIrqPinState = DevTmp.Int.s.uIrqPinState;
1404	pDev->Int.s.u8MsiCapOffset = DevTmp.Int.s.u8MsiCapOffset;
1405	pDev->Int.s.u8MsiCapSize = DevTmp.Int.s.u8MsiCapSize;
1406	pDev->Int.s.u8MsixCapOffset = DevTmp.Int.s.u8MsixCapOffset;
1407	pDev->Int.s.u8MsixCapSize = DevTmp.Int.s.u8MsixCapSize;
1408	if (DevTmp.Int.s.u8MsixCapSize != 0)
1409	{
1410	Assert(pDev->Int.s.pMsixPageR3 != NULL);
1411	memcpy(pDev->Int.s.pMsixPageR3, pvMsixPage, 0x1000);
1412	}
1413	}
1414
1415	out:
1416	if (pvMsixPage)
1417	RTMemTmpFree(pvMsixPage);
1418
1419	return rc;
1420	}
1421
1422	/**
1423	* Loads a saved PCI device state.
1424	*
1425	* @returns VBox status code.
1426	* @param pDevIns Device instance of the PCI Bus.
1427	* @param pPciDev Pointer to PCI device.
1428	* @param pSSM The handle to the saved state.
1429	*/
1430	static DECLCALLBACK(int) ich9pciGenericLoadExec(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PSSMHANDLE pSSM)
1431	{
1432	Assert(!PCIIsPassthrough(pPciDev));
1433	return SSMR3GetMem(pSSM, &pPciDev->config[0], sizeof(pPciDev->config));
1434	}
1435
1436	static DECLCALLBACK(int) ich9pciR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1437	{
1438	PPCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
1439	PPCIBUS pBus = &pThis->aPciBus;
1440	uint32_t u32;
1441	int rc;
1442
1443	/* We ignore this version as there's no saved state with it anyway */
1444	if (uVersion == VBOX_ICH9PCI_SAVED_STATE_VERSION_NOMSI)
1445	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1446	if (uVersion > VBOX_ICH9PCI_SAVED_STATE_VERSION_MSI)
1447	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1448
1449	/*
1450	* Bus state data.
1451	*/
1452	SSMR3GetU32(pSSM, &pThis->uConfigReg);
1453
1454	/*
1455	* Load IRQ states.
1456	*/
1457	for (int i = 0; i < PCI_APIC_IRQ_PINS; i++)
1458	SSMR3GetU32(pSSM, (uint32_t*)&pThis->uaPciApicIrqLevels[i]);
1459
1460	/* separator */
1461	rc = SSMR3GetU32(pSSM, &u32);
1462	if (RT_FAILURE(rc))
1463	return rc;
1464	if (u32 != (uint32_t)~0)
1465	AssertMsgFailedReturn(("u32=%#x\n", u32), rc);
1466
1467	return ich9pciR3CommonLoadExec(pBus, pSSM, uVersion, uPass);
1468	}
1469
1470	static DECLCALLBACK(int) ich9pcibridgeR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1471	{
1472	PPCIBUS pThis = PDMINS_2_DATA(pDevIns, PPCIBUS);
1473	if (uVersion > VBOX_ICH9PCI_SAVED_STATE_VERSION_MSI)
1474	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1475	return ich9pciR3CommonLoadExec(pThis, pSSM, uVersion, uPass);
1476	}
1477
1478	static uint32_t ich9pciConfigRead(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t len)
1479	{
1480	/* Will only work in LSB case */
1481	uint32_t u32Val;
1482	PciAddress aPciAddr;
1483
1484	aPciAddr.iBus = uBus;
1485	aPciAddr.iDeviceFunc = uDevFn;
1486	aPciAddr.iRegister = addr;
1487
1488	/* cannot be rescheduled, as already in R3 */
1489	int rc = ich9pciDataReadAddr(pGlobals, &aPciAddr, len, &u32Val, VERR_INTERNAL_ERROR);
1490	AssertRC(rc);
1491	return u32Val;
1492	}
1493
1494	static void ich9pciConfigWrite(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t val, uint32_t len)
1495	{
1496	PciAddress aPciAddr;
1497
1498	aPciAddr.iBus = uBus;
1499	aPciAddr.iDeviceFunc = uDevFn;
1500	aPciAddr.iRegister = addr;
1501
1502	/* cannot be rescheduled, as already in R3 */
1503	int rc = ich9pciDataWriteAddr(pGlobals, &aPciAddr, val, len, VERR_INTERNAL_ERROR);
1504	AssertRC(rc);
1505	}
1506
1507	static void ich9pciSetRegionAddress(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, int iRegion, uint32_t addr)
1508	{
1509	uint32_t uReg = ich9pciGetRegionReg(iRegion);
1510
1511	/* Read memory type first. */
1512	uint8_t uResourceType = ich9pciConfigRead(pGlobals, uBus, uDevFn, uReg, 1);
1513	/* Read command register. */
1514	uint16_t uCmd = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_COMMAND, 2);
1515
1516	if ( iRegion == PCI_ROM_SLOT )
1517	uCmd \|= PCI_COMMAND_MEMACCESS;
1518	else if ((uResourceType & PCI_ADDRESS_SPACE_IO) == PCI_ADDRESS_SPACE_IO)
1519	uCmd \|= PCI_COMMAND_IOACCESS; /* Enable I/O space access. */
1520	else /* The region is MMIO. */
1521	uCmd \|= PCI_COMMAND_MEMACCESS; /* Enable MMIO access. */
1522
1523	/* Write address of the device. */
1524	ich9pciConfigWrite(pGlobals, uBus, uDevFn, uReg, addr, 4);
1525
1526	/* enable memory mappings */
1527	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_COMMAND, uCmd, 2);
1528	}
1529
1530
1531	static void ich9pciBiosInitBridge(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint8_t cBridgeDepth, uint8_t *paBridgePositions)
1532	{
1533	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_SECONDARY_BUS, pGlobals->uBus, 1);
1534	/* Temporary until we know how many other bridges are behind this one. */
1535	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_SUBORDINATE_BUS, 0xff, 1);
1536
1537	/* Add position of this bridge into the array. */
1538	paBridgePositions[cBridgeDepth+1] = (uDevFn >> 3);
1539
1540	/*
1541	* The I/O range for the bridge must be aligned to a 4KB boundary.
1542	* This does not change anything really as the access to the device is not going
1543	* through the bridge but we want to be compliant to the spec.
1544	*/
1545	if ((pGlobals->uPciBiosIo % 4096) != 0)
1546	{
1547	pGlobals->uPciBiosIo = RT_ALIGN_32(pGlobals->uPciBiosIo, 4*1024);
1548	Log(("%s: Aligned I/O start address. New address %#x\n", __FUNCTION__, pGlobals->uPciBiosIo));
1549	}
1550	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_IO_BASE, (pGlobals->uPciBiosIo >> 8) & 0xf0, 1);
1551
1552	/* The MMIO range for the bridge must be aligned to a 1MB boundary. */
1553	if ((pGlobals->uPciBiosMmio % (1024 * 1024)) != 0)
1554	{
1555	pGlobals->uPciBiosMmio = RT_ALIGN_32(pGlobals->uPciBiosMmio, 1024*1024);
1556	Log(("%s: Aligned MMIO start address. New address %#x\n", __FUNCTION__, pGlobals->uPciBiosMmio));
1557	}
1558	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_MEMORY_BASE, (pGlobals->uPciBiosMmio >> 16) & UINT32_C(0xffff0), 2);
1559
1560	/* Save values to compare later to. */
1561	uint32_t u32IoAddressBase = pGlobals->uPciBiosIo;
1562	uint32_t u32MMIOAddressBase = pGlobals->uPciBiosMmio;
1563
1564	/* Init devices behind the bridge and possibly other bridges as well. */
1565	for (int iDev = 0; iDev <= 255; iDev++)
1566	ich9pciBiosInitDevice(pGlobals, uBus + 1, iDev, cBridgeDepth + 1, paBridgePositions);
1567
1568	/* The number of bridges behind the this one is now available. */
1569	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_SUBORDINATE_BUS, pGlobals->uBus, 1);
1570
1571	/*
1572	* Set I/O limit register. If there is no device with I/O space behind the bridge
1573	* we set a lower value than in the base register.
1574	* The result with a real bridge is that no I/O transactions are passed to the secondary
1575	* interface. Again this doesn't really matter here but we want to be compliant to the spec.
1576	*/
1577	if ((u32IoAddressBase != pGlobals->uPciBiosIo) && ((pGlobals->uPciBiosIo % 4096) != 0))
1578	{
1579	/* The upper boundary must be one byte less than a 4KB boundary. */
1580	pGlobals->uPciBiosIo = RT_ALIGN_32(pGlobals->uPciBiosIo, 4*1024);
1581	}
1582
1583	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_IO_LIMIT, ((pGlobals->uPciBiosIo >> 8) & 0xf0) - 1, 1);
1584
1585	/* Same with the MMIO limit register but with 1MB boundary here. */
1586	if ((u32MMIOAddressBase != pGlobals->uPciBiosMmio) && ((pGlobals->uPciBiosMmio % (1024 * 1024)) != 0))
1587	{
1588	/* The upper boundary must be one byte less than a 1MB boundary. */
1589	pGlobals->uPciBiosMmio = RT_ALIGN_32(pGlobals->uPciBiosMmio, 1024*1024);
1590	}
1591	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_MEMORY_LIMIT, ((pGlobals->uPciBiosMmio >> 16) & UINT32_C(0xfff0)) - 1, 2);
1592
1593	/*
1594	* Set the prefetch base and limit registers. We currently have no device with a prefetchable region
1595	* which may be behind a bridge. That's why it is unconditionally disabled here atm by writing a higher value into
1596	* the base register than in the limit register.
1597	*/
1598	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_MEMORY_BASE, 0xfff0, 2);
1599	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_MEMORY_LIMIT, 0x0, 2);
1600	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_BASE_UPPER32, 0x00, 4);
1601	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_LIMIT_UPPER32, 0x00, 4);
1602	}
1603
1604	static void ich9pciBiosInitDevice(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint8_t cBridgeDepth, uint8_t *paBridgePositions)
1605	{
1606	uint32_t *paddr;
1607	uint16_t uDevClass, uVendor, uDevice;
1608	uint8_t uCmd;
1609
1610	uDevClass = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_CLASS_DEVICE, 2);
1611	uVendor = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_VENDOR_ID, 2);
1612	uDevice = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_DEVICE_ID, 2);
1613
1614	/* If device is present */
1615	if (uVendor == 0xffff)
1616	return;
1617
1618	switch (uDevClass)
1619	{
1620	case 0x0101:
1621	/* IDE controller */
1622	ich9pciConfigWrite(pGlobals, uBus, uDevFn, 0x40, 0x8000, 2); /* enable IDE0 */
1623	ich9pciConfigWrite(pGlobals, uBus, uDevFn, 0x42, 0x8000, 2); /* enable IDE1 */
1624	goto default_map;
1625	break;
1626	case 0x0300:
1627	/* VGA controller */
1628	if (uVendor != 0x80ee)
1629	goto default_map;
1630	/* VGA: map frame buffer to default Bochs VBE address */
1631	ich9pciSetRegionAddress(pGlobals, uBus, uDevFn, 0, 0xE0000000);
1632	/*
1633	* Legacy VGA I/O ports are implicitly decoded by a VGA class device. But
1634	* only the framebuffer (i.e., a memory region) is explicitly registered via
1635	* ich9pciSetRegionAddress, so I/O decoding must be enabled manually.
1636	*/
1637	uCmd = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_COMMAND, 1);
1638	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_COMMAND,
1639	/* Enable I/O space access. */
1640	uCmd \| PCI_COMMAND_IOACCESS,
1641	1);
1642	break;
1643	case 0x0604:
1644	/* PCI-to-PCI bridge. */
1645	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_PRIMARY_BUS, uBus, 1);
1646
1647	AssertMsg(pGlobals->uBus < 255, ("Too many bridges on the bus\n"));
1648	pGlobals->uBus++;
1649	ich9pciBiosInitBridge(pGlobals, uBus, uDevFn, cBridgeDepth, paBridgePositions);
1650	break;
1651	default:
1652	default_map:
1653	{
1654	/* default memory mappings */
1655	/*
1656	* We ignore ROM region here.
1657	*/
1658	for (int iRegion = 0; iRegion < (PCI_NUM_REGIONS-1); iRegion++)
1659	{
1660	uint32_t u32Address = ich9pciGetRegionReg(iRegion);
1661
1662	/* Calculate size - we write all 1s into the BAR, and then evaluate which bits
1663	are cleared. . */
1664	uint8_t u8ResourceType = ich9pciConfigRead(pGlobals, uBus, uDevFn, u32Address, 1);
1665	ich9pciConfigWrite(pGlobals, uBus, uDevFn, u32Address, UINT32_C(0xffffffff), 4);
1666	uint32_t u32Size = ich9pciConfigRead(pGlobals, uBus, uDevFn, u32Address, 4);
1667	/* Clear resource information depending on resource type. */
1668	if ((u8ResourceType & PCI_COMMAND_IOACCESS) == PCI_COMMAND_IOACCESS) /* I/O */
1669	u32Size &= ~(0x01);
1670	else /* MMIO */
1671	u32Size &= ~(0x0f);
1672
1673	bool fIsPio = ((u8ResourceType & PCI_COMMAND_IOACCESS) == PCI_COMMAND_IOACCESS);
1674	/*
1675	* Invert all bits and add 1 to get size of the region.
1676	* (From PCI implementation note)
1677	*/
1678	if (fIsPio && (u32Size & UINT32_C(0xffff0000)) == 0)
1679	u32Size = (~(u32Size \| UINT32_C(0xffff0000))) + 1;
1680	else
1681	u32Size = (~u32Size) + 1;
1682
1683	Log(("%s: Size of region %u for device %d on bus %d is %u\n", __FUNCTION__, iRegion, uDevFn, uBus, u32Size));
1684
1685	if (u32Size)
1686	{
1687	paddr = fIsPio ? &pGlobals->uPciBiosIo : &pGlobals->uPciBiosMmio;
1688	paddr = (paddr + u32Size - 1) & ~(u32Size - 1);
1689	Log(("%s: Start address of %s region %u is %#x\n", __FUNCTION__, (fIsPio ? "I/O" : "MMIO"), iRegion, *paddr));
1690	ich9pciSetRegionAddress(pGlobals, uBus, uDevFn, iRegion, *paddr);
1691	*paddr += u32Size;
1692	Log(("%s: New address is %#x\n", __FUNCTION__, *paddr));
1693	}
1694	}
1695	break;
1696	}
1697	}
1698
1699	/* map the interrupt */
1700	uint32_t iPin = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_INTERRUPT_PIN, 1);
1701	if (iPin != 0)
1702	{
1703	uint8_t uBridgeDevFn = uDevFn;
1704	iPin--;
1705
1706	/* We need to go up to the host bus to see which irq this device will assert there. */
1707	while (cBridgeDepth != 0)
1708	{
1709	/* Get the pin the device would assert on the bridge. */
1710	iPin = ((uBridgeDevFn >> 3) + iPin) & 3;
1711	uBridgeDevFn = paBridgePositions[cBridgeDepth];
1712	cBridgeDepth--;
1713	}
1714
1715	int iIrq = aPciIrqs[ich9pciSlotGetPirq(uBus, uDevFn, iPin)];
1716	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_INTERRUPT_LINE, iIrq, 1);
1717	}
1718	}
1719
1720	static DECLCALLBACK(int) ich9pciFakePCIBIOS(PPDMDEVINS pDevIns)
1721	{
1722	unsigned i;
1723	uint8_t elcr[2] = {0, 0};
1724	PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
1725	PVM pVM = PDMDevHlpGetVM(pDevIns);
1726	Assert(pVM);
1727
1728	/*
1729	* Set the start addresses.
1730	*/
1731	pGlobals->uPciBiosIo = 0xd000;
1732	pGlobals->uPciBiosMmio = UINT32_C(0xf0000000);
1733	pGlobals->uBus = 0;
1734
1735	/*
1736	* Init the devices.
1737	*/
1738	for (i = 0; i < 256; i++)
1739	{
1740	uint8_t aBridgePositions[256];
1741
1742	memset(aBridgePositions, 0, sizeof(aBridgePositions));
1743	Log2(("PCI: Initializing device %d (%#x)\n",
1744	i, 0x80000000 \| (i << 8)));
1745	ich9pciBiosInitDevice(pGlobals, 0, i, 0, aBridgePositions);
1746	}
1747
1748	return VINF_SUCCESS;
1749	}
1750
1751	static DECLCALLBACK(uint32_t) ich9pciConfigReadDev(PCIDevice *aDev, uint32_t u32Address, unsigned len)
1752	{
1753	if ((u32Address + len) > 256 && (u32Address + len) < 4096)
1754	{
1755	AssertMsgReturn(false, ("Read from extended registers falled back to generic code\n"), 0);
1756	}
1757
1758	AssertMsgReturn(u32Address + len <= 256, ("Read after end of PCI config space\n"),
1759	0);
1760	if ( PCIIsMsiCapable(aDev)
1761	&& (u32Address >= aDev->Int.s.u8MsiCapOffset)
1762	&& (u32Address < aDev->Int.s.u8MsiCapOffset + aDev->Int.s.u8MsiCapSize)
1763	)
1764	{
1765	return MsiPciConfigRead(aDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pDevIns), aDev, u32Address, len);
1766	}
1767
1768	if ( PCIIsMsixCapable(aDev)
1769	&& (u32Address >= aDev->Int.s.u8MsixCapOffset)
1770	&& (u32Address < aDev->Int.s.u8MsixCapOffset + aDev->Int.s.u8MsixCapSize)
1771	)
1772	{
1773	return MsixPciConfigRead(aDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pDevIns), aDev, u32Address, len);
1774	}
1775
1776	AssertMsgReturn(u32Address + len <= 256, ("Read after end of PCI config space\n"),
1777	0);
1778	switch (len)
1779	{
1780	case 1:
1781	return PCIDevGetByte(aDev, u32Address);
1782	case 2:
1783	return PCIDevGetWord(aDev, u32Address);
1784	case 4:
1785	return PCIDevGetDWord(aDev, u32Address);
1786	default:
1787	Assert(false);
1788	return 0;
1789	}
1790	}
1791
1792	DECLINLINE(void) ich9pciWriteBarByte(PCIDevice *aDev, int iRegion, int iOffset, uint8_t u8Val)
1793	{
1794	PCIIORegion * pRegion = &aDev->Int.s.aIORegions[iRegion];
1795
1796	int iRegionSize = pRegion->size;
1797
1798	Log3(("ich9pciWriteBarByte: region=%d off=%d val=%x size=%d\n",
1799	iRegion, iOffset, u8Val, iRegionSize));
1800
1801	/* Region doesn't exist */
1802	if (iRegionSize == 0)
1803	return;
1804
1805	uint32_t uAddr = ich9pciGetRegionReg(iRegion) + iOffset;
1806	/* Region size must be power of two */
1807	Assert((iRegionSize & (iRegionSize - 1)) == 0);
1808	uint8_t uMask = (((uint32_t)iRegionSize - 1) >> (iOffset*8) ) & 0xff;
1809
1810	if (iOffset == 0)
1811	{
1812	uMask \|= (pRegion->type & PCI_ADDRESS_SPACE_IO) ?
1813	(1 << 2) - 1 /* 2 lowest bits for IO region */ :
1814	(1 << 4) - 1 /* 4 lowest bits for memory region, also ROM enable bit for ROM region */;
1815
1816	}
1817
1818	uint8_t u8Old = PCIDevGetByte(aDev, uAddr) & uMask;
1819	u8Val = (u8Old & uMask) \| (u8Val & ~uMask);
1820
1821	Log3(("ich9pciWriteBarByte: was %x writing %x\n", u8Old, u8Val));
1822
1823	PCIDevSetByte(aDev, uAddr, u8Val);
1824	}
1825	/**
1826	* See paragraph 7.5 of PCI Express specification (p. 349) for definition of
1827	* registers and their writability policy.
1828	*/
1829	static DECLCALLBACK(void) ich9pciConfigWriteDev(PCIDevice *aDev, uint32_t u32Address,
1830	uint32_t val, unsigned len)
1831	{
1832	Assert(len <= 4);
1833
1834	if ((u32Address + len) > 256 && (u32Address + len) < 4096)
1835	{
1836	AssertMsgReturnVoid(false, ("Write to extended registers falled back to generic code\n"));
1837	}
1838
1839	AssertMsgReturnVoid(u32Address + len <= 256, ("Write after end of PCI config space\n"));
1840
1841	if ( PCIIsMsiCapable(aDev)
1842	&& (u32Address >= aDev->Int.s.u8MsiCapOffset)
1843	&& (u32Address < aDev->Int.s.u8MsiCapOffset + aDev->Int.s.u8MsiCapSize)
1844	)
1845	{
1846	MsiPciConfigWrite(aDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pDevIns),
1847	aDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pPciHlp),
1848	aDev, u32Address, val, len);
1849	return;
1850	}
1851
1852	if ( PCIIsMsixCapable(aDev)
1853	&& (u32Address >= aDev->Int.s.u8MsixCapOffset)
1854	&& (u32Address < aDev->Int.s.u8MsixCapOffset + aDev->Int.s.u8MsixCapSize)
1855	)
1856	{
1857	MsixPciConfigWrite(aDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pDevIns),
1858	aDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pPciHlp),
1859	aDev, u32Address, val, len);
1860	return;
1861	}
1862
1863	uint32_t addr = u32Address;
1864	bool fUpdateMappings = false;
1865	bool fP2PBridge = false;
1866	for (uint32_t i = 0; i < len; i++)
1867	{
1868	bool fWritable = false;
1869	bool fRom = false;
1870	switch (PCIDevGetHeaderType(aDev))
1871	{
1872	case 0x00: /* normal device */
1873	case 0x80: /* multi-function device */
1874	switch (addr)
1875	{
1876	/* Read-only registers */
1877	case VBOX_PCI_VENDOR_ID: case VBOX_PCI_VENDOR_ID+1:
1878	case VBOX_PCI_DEVICE_ID: case VBOX_PCI_DEVICE_ID+1:
1879	case VBOX_PCI_REVISION_ID:
1880	case VBOX_PCI_CLASS_PROG:
1881	case VBOX_PCI_CLASS_SUB:
1882	case VBOX_PCI_CLASS_BASE:
1883	case VBOX_PCI_HEADER_TYPE:
1884	case VBOX_PCI_SUBSYSTEM_VENDOR_ID: case VBOX_PCI_SUBSYSTEM_VENDOR_ID+1:
1885	case VBOX_PCI_SUBSYSTEM_ID: case VBOX_PCI_SUBSYSTEM_ID+1:
1886	case VBOX_PCI_ROM_ADDRESS: case VBOX_PCI_ROM_ADDRESS+1: case VBOX_PCI_ROM_ADDRESS+2: case VBOX_PCI_ROM_ADDRESS+3:
1887	case VBOX_PCI_CAPABILITY_LIST:
1888	case VBOX_PCI_INTERRUPT_PIN:
1889	fWritable = false;
1890	break;
1891	/* Others can be written */
1892	default:
1893	fWritable = true;
1894	break;
1895	}
1896	break;
1897	case 0x01: /* PCI-PCI bridge */
1898	fP2PBridge = true;
1899	switch (addr)
1900	{
1901	/* Read-only registers */
1902	case VBOX_PCI_VENDOR_ID: case VBOX_PCI_VENDOR_ID+1:
1903	case VBOX_PCI_DEVICE_ID: case VBOX_PCI_DEVICE_ID+1:
1904	case VBOX_PCI_REVISION_ID:
1905	case VBOX_PCI_CLASS_PROG:
1906	case VBOX_PCI_CLASS_SUB:
1907	case VBOX_PCI_CLASS_BASE:
1908	case VBOX_PCI_HEADER_TYPE:
1909	case VBOX_PCI_ROM_ADDRESS_BR: case VBOX_PCI_ROM_ADDRESS_BR+1: case VBOX_PCI_ROM_ADDRESS_BR+2: case VBOX_PCI_ROM_ADDRESS_BR+3:
1910	case VBOX_PCI_INTERRUPT_PIN:
1911	fWritable = false;
1912	break;
1913	default:
1914	fWritable = true;
1915	break;
1916	}
1917	break;
1918	default:
1919	AssertMsgFailed(("Unknown header type %x\n", PCIDevGetHeaderType(aDev)));
1920	fWritable = false;
1921	break;
1922	}
1923
1924	uint8_t u8Val = (uint8_t)val;
1925	switch (addr)
1926	{
1927	case VBOX_PCI_COMMAND: /* Command register, bits 0-7. */
1928	fUpdateMappings = true;
1929	PCIDevSetByte(aDev, addr, u8Val);
1930	break;
1931	case VBOX_PCI_COMMAND+1: /* Command register, bits 8-15. */
1932	/* don't change reserved bits (11-15) */
1933	u8Val &= UINT32_C(~0xf8);
1934	fUpdateMappings = true;
1935	PCIDevSetByte(aDev, addr, u8Val);
1936	break;
1937	case VBOX_PCI_STATUS: /* Status register, bits 0-7. */
1938	/* don't change read-only bits => actually all lower bits are read-only */
1939	u8Val &= UINT32_C(~0xff);
1940	/* status register, low part: clear bits by writing a '1' to the corresponding bit */
1941	aDev->config[addr] &= ~u8Val;
1942	break;
1943	case VBOX_PCI_STATUS+1: /* Status register, bits 8-15. */
1944	/* don't change read-only bits */
1945	u8Val &= UINT32_C(~0x06);
1946	/* status register, high part: clear bits by writing a '1' to the corresponding bit */
1947	aDev->config[addr] &= ~u8Val;
1948	break;
1949	case VBOX_PCI_ROM_ADDRESS: case VBOX_PCI_ROM_ADDRESS +1: case VBOX_PCI_ROM_ADDRESS +2: case VBOX_PCI_ROM_ADDRESS +3:
1950	fRom = true;
1951	case VBOX_PCI_BASE_ADDRESS_0: case VBOX_PCI_BASE_ADDRESS_0+1: case VBOX_PCI_BASE_ADDRESS_0+2: case VBOX_PCI_BASE_ADDRESS_0+3:
1952	case VBOX_PCI_BASE_ADDRESS_1: case VBOX_PCI_BASE_ADDRESS_1+1: case VBOX_PCI_BASE_ADDRESS_1+2: case VBOX_PCI_BASE_ADDRESS_1+3:
1953	case VBOX_PCI_BASE_ADDRESS_2: case VBOX_PCI_BASE_ADDRESS_2+1: case VBOX_PCI_BASE_ADDRESS_2+2: case VBOX_PCI_BASE_ADDRESS_2+3:
1954	case VBOX_PCI_BASE_ADDRESS_3: case VBOX_PCI_BASE_ADDRESS_3+1: case VBOX_PCI_BASE_ADDRESS_3+2: case VBOX_PCI_BASE_ADDRESS_3+3:
1955	case VBOX_PCI_BASE_ADDRESS_4: case VBOX_PCI_BASE_ADDRESS_4+1: case VBOX_PCI_BASE_ADDRESS_4+2: case VBOX_PCI_BASE_ADDRESS_4+3:
1956	case VBOX_PCI_BASE_ADDRESS_5: case VBOX_PCI_BASE_ADDRESS_5+1: case VBOX_PCI_BASE_ADDRESS_5+2: case VBOX_PCI_BASE_ADDRESS_5+3:
1957	{
1958	/* We check that, as same PCI register numbers as BARs may mean different registers for bridges */
1959	if (fP2PBridge)
1960	goto default_case;
1961	else
1962	{
1963	int iRegion = fRom ? VBOX_PCI_ROM_SLOT : (addr - VBOX_PCI_BASE_ADDRESS_0) >> 2;
1964	int iOffset = addr & 0x3;
1965	ich9pciWriteBarByte(aDev, iRegion, iOffset, u8Val);
1966	fUpdateMappings = true;
1967	}
1968	break;
1969	}
1970	default:
1971	default_case:
1972	if (fWritable)
1973	PCIDevSetByte(aDev, addr, u8Val);
1974	}
1975	addr++;
1976	val >>= 8;
1977	}
1978
1979	if (fUpdateMappings)
1980	/* if the command/base address register is modified, we must modify the mappings */
1981	ich9pciUpdateMappings(aDev);
1982	}
1983
1984	/* Slot/functions assignment per table at p. 12 of ICH9 family spec update */
1985	static const struct {
1986	const char* pszName;
1987	int32_t iSlot;
1988	int32_t iFunction;
1989	} PciSlotAssignments[] = {
1990	/* The only override that have to be here, as host controller is added in the way invisible to bus slot assignment management,
1991	maybe to be changed in the future. */
1992	{
1993	"i82801", 30, 0 /* Host Controller */
1994	},
1995	};
1996
1997	static bool assignPosition(PPCIBUS pBus, PPCIDEVICE pPciDev, const char pszName, int iDevFn, PciAddress aPosition)
1998	{
1999	aPosition->iBus = 0;
2000	aPosition->iDeviceFunc = iDevFn;
2001	aPosition->iRegister = 0; /* N/A */
2002
2003	/* Hardcoded slots/functions, per chipset spec */
2004	for (size_t i = 0; i < RT_ELEMENTS(PciSlotAssignments); i++)
2005	{
2006	if (!strcmp(pszName, PciSlotAssignments[i].pszName))
2007	{
2008	PCISetRequestedDevfunc(pPciDev);
2009	aPosition->iDeviceFunc =
2010	(PciSlotAssignments[i].iSlot << 3) + PciSlotAssignments[i].iFunction;
2011	return true;
2012	}
2013	}
2014
2015	/* Explicit slot request */
2016	if (iDevFn >=0 && iDevFn < (int)RT_ELEMENTS(pBus->apDevices))
2017	return true;
2018
2019	int iStartPos = 0;
2020
2021	/* Otherwise when assigning a slot, we need to make sure all its functions are available */
2022	for (int iPos = iStartPos; iPos < (int)RT_ELEMENTS(pBus->apDevices); iPos += 8)
2023	{
2024	if ( !pBus->apDevices[iPos]
2025	&& !pBus->apDevices[iPos + 1]
2026	&& !pBus->apDevices[iPos + 2]
2027	&& !pBus->apDevices[iPos + 3]
2028	&& !pBus->apDevices[iPos + 4]
2029	&& !pBus->apDevices[iPos + 5]
2030	&& !pBus->apDevices[iPos + 6]
2031	&& !pBus->apDevices[iPos + 7])
2032	{
2033	PCIClearRequestedDevfunc(pPciDev);
2034	aPosition->iDeviceFunc = iPos;
2035	return true;
2036	}
2037	}
2038
2039	return false;
2040	}
2041
2042	static bool hasHardAssignedDevsInSlot(PPCIBUS pBus, int iSlot)
2043	{
2044	PCIDevice** aSlot = &pBus->apDevices[iSlot << 3];
2045
2046	return (aSlot[0] && PCIIsRequestedDevfunc(aSlot[0]))
2047	\|\| (aSlot[1] && PCIIsRequestedDevfunc(aSlot[1]))
2048	\|\| (aSlot[2] && PCIIsRequestedDevfunc(aSlot[2]))
2049	\|\| (aSlot[3] && PCIIsRequestedDevfunc(aSlot[3]))
2050	\|\| (aSlot[4] && PCIIsRequestedDevfunc(aSlot[4]))
2051	\|\| (aSlot[5] && PCIIsRequestedDevfunc(aSlot[5]))
2052	\|\| (aSlot[6] && PCIIsRequestedDevfunc(aSlot[6]))
2053	\|\| (aSlot[7] && PCIIsRequestedDevfunc(aSlot[7]))
2054	;
2055	}
2056
2057	static int ich9pciRegisterInternal(PPCIBUS pBus, int iDev, PPCIDEVICE pPciDev, const char *pszName)
2058	{
2059	PciAddress aPosition = {0, 0, 0};
2060
2061	/*
2062	* Find device position
2063	*/
2064	if (!assignPosition(pBus, pPciDev, pszName, iDev, &aPosition))
2065	{
2066	AssertMsgFailed(("Couldn't asssign position!\n"));
2067	return VERR_PDM_TOO_PCI_MANY_DEVICES;
2068	}
2069
2070	AssertMsgReturn(aPosition.iBus == 0,
2071	("Assigning behind the bridge not implemented yet\n"),
2072	VERR_PDM_TOO_PCI_MANY_DEVICES);
2073
2074
2075	iDev = aPosition.iDeviceFunc;
2076	/*
2077	* Check if we can really take this slot, possibly by relocating
2078	* its current habitant, if it wasn't hard assigned too.
2079	*/
2080	if (PCIIsRequestedDevfunc(pPciDev) &&
2081	pBus->apDevices[iDev] &&
2082	PCIIsRequestedDevfunc(pBus->apDevices[iDev]))
2083	{
2084	AssertReleaseMsgFailed(("Configuration error:'%s' and '%s' are both configured as device %d\n",
2085	pszName, pBus->apDevices[iDev]->name, iDev));
2086	return VERR_INTERNAL_ERROR;
2087	}
2088
2089	if (pBus->apDevices[iDev])
2090	{
2091	/* if we got here, we shall (and usually can) relocate the device */
2092	bool assigned = assignPosition(pBus, pBus->apDevices[iDev], pBus->apDevices[iDev]->name, -1, &aPosition);
2093	AssertMsgReturn(aPosition.iBus == 0,
2094	("Assigning behind the bridge not implemented yet\n"),
2095	VERR_PDM_TOO_PCI_MANY_DEVICES);
2096	int iRelDev = aPosition.iDeviceFunc;
2097	if (!assigned \|\| iRelDev == iDev)
2098	{
2099	AssertMsgFailed(("Couldn't find free spot!\n"));
2100	return VERR_PDM_TOO_PCI_MANY_DEVICES;
2101	}
2102	/* Copy device function by function to its new position */
2103	for (int i = 0; i < 8; i++)
2104	{
2105	if (!pBus->apDevices[iDev + i])
2106	continue;
2107	Log(("PCI: relocating '%s' from slot %#x to %#x\n", pBus->apDevices[iDev + i]->name, iDev + i, iRelDev + i));
2108	pBus->apDevices[iRelDev + i] = pBus->apDevices[iDev + i];
2109	pBus->apDevices[iRelDev + i]->devfn = iRelDev + i;
2110	pBus->apDevices[iDev + i] = NULL;
2111	}
2112	}
2113
2114	/*
2115	* Fill in device information.
2116	*/
2117	pPciDev->devfn = iDev;
2118	pPciDev->name = pszName;
2119	pPciDev->Int.s.pBusR3 = pBus;
2120	pPciDev->Int.s.pBusR0 = MMHyperR3ToR0(PDMDevHlpGetVM(pBus->CTX_SUFF(pDevIns)), pBus);
2121	pPciDev->Int.s.pBusRC = MMHyperR3ToRC(PDMDevHlpGetVM(pBus->CTX_SUFF(pDevIns)), pBus);
2122	pPciDev->Int.s.pfnConfigRead = ich9pciConfigReadDev;
2123	pPciDev->Int.s.pfnConfigWrite = ich9pciConfigWriteDev;
2124	pBus->apDevices[iDev] = pPciDev;
2125	if (PCIIsPci2PciBridge(pPciDev))
2126	{
2127	AssertMsg(pBus->cBridges < RT_ELEMENTS(pBus->apDevices), ("Number of bridges exceeds the number of possible devices on the bus\n"));
2128	AssertMsg(pPciDev->Int.s.pfnBridgeConfigRead && pPciDev->Int.s.pfnBridgeConfigWrite,
2129	("device is a bridge but does not implement read/write functions\n"));
2130	pBus->papBridgesR3[pBus->cBridges] = pPciDev;
2131	pBus->cBridges++;
2132	}
2133
2134	Log(("PCI: Registered device %d function %d (%#x) '%s'.\n",
2135	iDev >> 3, iDev & 7, 0x80000000 \| (iDev << 8), pszName));
2136
2137	return VINF_SUCCESS;
2138	}
2139
2140	static void printIndent(PCDBGFINFOHLP pHlp, int iIndent)
2141	{
2142	for (int i = 0; i < iIndent; i++)
2143	{
2144	pHlp->pfnPrintf(pHlp, " ");
2145	}
2146	}
2147
2148	static void ich9pciBusInfo(PPCIBUS pBus, PCDBGFINFOHLP pHlp, int iIndent, bool fRegisters)
2149	{
2150	for (uint32_t iDev = 0; iDev < RT_ELEMENTS(pBus->apDevices); iDev++)
2151	{
2152	PPCIDEVICE pPciDev = pBus->apDevices[iDev];
2153	if (pPciDev != NULL)
2154	{
2155	if (PCIIsPassthrough(pPciDev))
2156	{
2157	printIndent(pHlp, iIndent);
2158	/**
2159	* For passthrough devices MSI/MSI-X mostly reflects the way interrupts delivered to the guest,
2160	* as host driver handles real devices interrupts.
2161	*/
2162	pHlp->pfnPrintf(pHlp, "%02x:%02x:%02x %s: %s%s - PASSTHROUGH\n",
2163	pBus->iBus, (iDev >> 3) & 0xff, iDev & 0x7,
2164	pPciDev->name,
2165	PCIIsMsiCapable(pPciDev) ? " MSI" : "",
2166	PCIIsMsixCapable(pPciDev) ? " MSI-X" : ""
2167	);
2168	continue;
2169	}
2170	printIndent(pHlp, iIndent);
2171	pHlp->pfnPrintf(pHlp, "%02x:%02x:%02x %s: %04x-%04x%s%s",
2172	pBus->iBus, (iDev >> 3) & 0xff, iDev & 0x7,
2173	pPciDev->name,
2174	PCIDevGetVendorId(pPciDev), PCIDevGetDeviceId(pPciDev),
2175	PCIIsMsiCapable(pPciDev) ? " MSI" : "",
2176	PCIIsMsixCapable(pPciDev) ? " MSI-X" : ""
2177	);
2178	if (PCIDevGetInterruptPin(pPciDev) != 0)
2179	pHlp->pfnPrintf(pHlp, " IRQ%d", PCIDevGetInterruptLine(pPciDev));
2180
2181	pHlp->pfnPrintf(pHlp, "\n");
2182
2183	int iCmd = PCIDevGetCommand(pPciDev);
2184	if ((iCmd & (VBOX_PCI_COMMAND_IO \| VBOX_PCI_COMMAND_MEMORY)) != 0)
2185	{
2186	for (int iRegion = 0; iRegion < PCI_NUM_REGIONS; iRegion++)
2187	{
2188	PCIIORegion* pRegion = &pPciDev->Int.s.aIORegions[iRegion];
2189	int32_t iRegionSize = pRegion->size;
2190
2191	if (iRegionSize == 0)
2192	continue;
2193
2194	uint32_t u32Addr = ich9pciConfigReadDev(pPciDev, ich9pciGetRegionReg(iRegion), 4);
2195	const char * szDesc;
2196
2197	if (pRegion->type & PCI_ADDRESS_SPACE_IO)
2198	{
2199	szDesc = "IO";
2200	u32Addr &= ~0x3;
2201	}
2202	else
2203	{
2204	szDesc = "MMIO";
2205	u32Addr &= ~0xf;
2206	}
2207
2208	printIndent(pHlp, iIndent + 2);
2209	pHlp->pfnPrintf(pHlp, " %s region #%d: %x..%x\n",
2210	szDesc, iRegion, u32Addr, u32Addr+iRegionSize);
2211	}
2212	}
2213
2214	if (fRegisters)
2215	{
2216	printIndent(pHlp, iIndent + 2);
2217	pHlp->pfnPrintf(pHlp, " PCI registers:\n");
2218	for (int iReg = 0; iReg < 0x100; )
2219	{
2220	int iPerLine = 0x10;
2221	Assert (0x100 % iPerLine == 0);
2222	printIndent(pHlp, iIndent + 3);
2223
2224	while (iPerLine-- > 0)
2225	{
2226	pHlp->pfnPrintf(pHlp, "%02x ", pPciDev->config[iReg++]);
2227	}
2228	pHlp->pfnPrintf(pHlp, "\n");
2229	}
2230	}
2231	}
2232	}
2233
2234	if (pBus->cBridges > 0)
2235	{
2236	printIndent(pHlp, iIndent);
2237	pHlp->pfnPrintf(pHlp, "Registered %d bridges, subordinate buses info follows\n", pBus->cBridges);
2238	for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
2239	{
2240	PPCIBUS pBusSub = PDMINS_2_DATA(pBus->papBridgesR3[iBridge]->pDevIns, PPCIBUS);
2241	ich9pciBusInfo(pBusSub, pHlp, iIndent + 1, fRegisters);
2242	}
2243	}
2244	}
2245
2246	/**
2247	* Info handler, device version.
2248	*
2249	* @param pDevIns Device instance which registered the info.
2250	* @param pHlp Callback functions for doing output.
2251	* @param pszArgs Argument string. Optional and specific to the handler.
2252	*/
2253	static DECLCALLBACK(void) ich9pciInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
2254	{
2255	PPCIBUS pBus = DEVINS_2_PCIBUS(pDevIns);
2256
2257	if (pszArgs == NULL \|\| !strcmp(pszArgs, "basic"))
2258	{
2259	ich9pciBusInfo(pBus, pHlp, 0, false);
2260	}
2261	else if (!strcmp(pszArgs, "verbose"))
2262	{
2263	ich9pciBusInfo(pBus, pHlp, 0, true);
2264	}
2265	else
2266	{
2267	pHlp->pfnPrintf(pHlp, "Invalid argument. Recognized arguments are 'basic', 'verbose'.\n");
2268	}
2269	}
2270
2271
2272	static DECLCALLBACK(int) ich9pciConstruct(PPDMDEVINS pDevIns,
2273	int iInstance,
2274	PCFGMNODE pCfg)
2275	{
2276	Assert(iInstance == 0);
2277	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
2278
2279	/*
2280	* Validate and read configuration.
2281	*/
2282	if (!CFGMR3AreValuesValid(pCfg,
2283	"IOAPIC\0"
2284	"GCEnabled\0"
2285	"R0Enabled\0"
2286	"McfgBase\0"
2287	"McfgLength\0"
2288	))
2289	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
2290
2291	/* query whether we got an IOAPIC */
2292	bool fUseIoApic;
2293	int rc = CFGMR3QueryBoolDef(pCfg, "IOAPIC", &fUseIoApic, false);
2294	if (RT_FAILURE(rc))
2295	return PDMDEV_SET_ERROR(pDevIns, rc,
2296	N_("Configuration error: Failed to query boolean value \"IOAPIC\""));
2297
2298	/* check if RC code is enabled. */
2299	bool fGCEnabled;
2300	rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
2301	if (RT_FAILURE(rc))
2302	return PDMDEV_SET_ERROR(pDevIns, rc,
2303	N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
2304
2305	/* check if R0 code is enabled. */
2306	bool fR0Enabled;
2307	rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
2308	if (RT_FAILURE(rc))
2309	return PDMDEV_SET_ERROR(pDevIns, rc,
2310	N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
2311
2312	Log(("PCI: fUseIoApic=%RTbool fGCEnabled=%RTbool fR0Enabled=%RTbool\n", fUseIoApic, fGCEnabled, fR0Enabled));
2313
2314	/*
2315	* Init data.
2316	*/
2317	PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
2318	PPCIBUS pBus = &pGlobals->aPciBus;
2319	/* Zero out everything */
2320	memset(pGlobals, 0, sizeof(*pGlobals));
2321	/* And fill values */
2322	if (!fUseIoApic)
2323	return PDMDEV_SET_ERROR(pDevIns, rc,
2324	N_("Must use IO-APIC with ICH9 chipset"));
2325	rc = CFGMR3QueryU64Def(pCfg, "McfgBase", &pGlobals->u64PciConfigMMioAddress, 0);
2326	if (RT_FAILURE(rc))
2327	return PDMDEV_SET_ERROR(pDevIns, rc,
2328	N_("Configuration error: Failed to read \"McfgBase\""));
2329	rc = CFGMR3QueryU64Def(pCfg, "McfgLength", &pGlobals->u64PciConfigMMioLength, 0);
2330	if (RT_FAILURE(rc))
2331	return PDMDEV_SET_ERROR(pDevIns, rc,
2332	N_("Configuration error: Failed to read \"McfgLength\""));
2333
2334	pGlobals->pDevInsR3 = pDevIns;
2335	pGlobals->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2336	pGlobals->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2337
2338	pGlobals->aPciBus.pDevInsR3 = pDevIns;
2339	pGlobals->aPciBus.pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2340	pGlobals->aPciBus.pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2341	pGlobals->aPciBus.papBridgesR3 = (PPCIDEVICE )PDMDevHlpMMHeapAllocZ(pDevIns, sizeof(PPCIDEVICE) RT_ELEMENTS(pGlobals->aPciBus.apDevices));
2342
2343	/*
2344	* Register bus
2345	*/
2346	PDMPCIBUSREG PciBusReg;
2347	PciBusReg.u32Version = PDM_PCIBUSREG_VERSION;
2348	PciBusReg.pfnRegisterR3 = ich9pciRegister;
2349	PciBusReg.pfnRegisterMsiR3 = ich9pciRegisterMsi;
2350	PciBusReg.pfnIORegionRegisterR3 = ich9pciIORegionRegister;
2351	PciBusReg.pfnSetConfigCallbacksR3 = ich9pciSetConfigCallbacks;
2352	PciBusReg.pfnSetIrqR3 = ich9pciSetIrq;
2353	PciBusReg.pfnSaveExecR3 = ich9pciGenericSaveExec;
2354	PciBusReg.pfnLoadExecR3 = ich9pciGenericLoadExec;
2355	PciBusReg.pfnFakePCIBIOSR3 = ich9pciFakePCIBIOS;
2356	PciBusReg.pszSetIrqRC = fGCEnabled ? "ich9pciSetIrq" : NULL;
2357	PciBusReg.pszSetIrqR0 = fR0Enabled ? "ich9pciSetIrq" : NULL;
2358	rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBus->pPciHlpR3);
2359	if (RT_FAILURE(rc))
2360	return PDMDEV_SET_ERROR(pDevIns, rc,
2361	N_("Failed to register ourselves as a PCI Bus"));
2362	if (pBus->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
2363	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
2364	N_("PCI helper version mismatch; got %#x expected %#x"),
2365	pBus->pPciHlpR3->u32Version, PDM_PCIHLPR3_VERSION);
2366
2367	pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
2368	pBus->pPciHlpR0 = pBus->pPciHlpR3->pfnGetR0Helpers(pDevIns);
2369
2370	/*
2371	* Fill in PCI configs and add them to the bus.
2372	*/
2373
2374	/**
2375	* We emulate 82801IB ICH9 IO chip used in Q35,
2376	* see http://ark.intel.com/Product.aspx?id=31892
2377	*
2378	* Stepping S-Spec Top Marking
2379	*
2380	* A2 SLA9M NH82801IB
2381	*/
2382	/* Host bridge device */
2383	/* @todo: move to separate driver? */
2384	PCIDevSetVendorId( &pBus->aPciDev, 0x8086); /* Intel */
2385	PCIDevSetDeviceId( &pBus->aPciDev, 0x244e); /* Desktop */
2386	PCIDevSetRevisionId(&pBus->aPciDev, 0x92); /* rev. A2 */
2387	PCIDevSetClassBase( &pBus->aPciDev, 0x06); /* bridge */
2388	PCIDevSetClassSub( &pBus->aPciDev, 0x04); /* Host/PCI bridge */
2389	PCIDevSetClassProg( &pBus->aPciDev, 0x01); /* Supports subtractive decoding. */
2390	PCIDevSetHeaderType(&pBus->aPciDev, 0x01); /* bridge */
2391	PCIDevSetWord(&pBus->aPciDev, VBOX_PCI_SEC_STATUS, 0x0280); /* secondary status */
2392	PCIDevSetDWord(&pBus->aPciDev, 0x4c, 0x00001200); /* Bridge policy configuration */
2393	PCIDevSetStatus (&pBus->aPciDev, VBOX_PCI_STATUS_CAP_LIST);
2394	PCIDevSetCapabilityList(&pBus->aPciDev, 0x50);
2395	/* capability */
2396	PCIDevSetWord(&pBus->aPciDev, 0x50, VBOX_PCI_CAP_ID_SSVID);
2397	PCIDevSetDWord(&pBus->aPciDev, 0x54, 0x00000000); /* Subsystem vendor ids */
2398
2399	pBus->aPciDev.pDevIns = pDevIns;
2400	/* We register Host<->PCI controller on the bus */
2401	ich9pciRegisterInternal(pBus, -1, &pBus->aPciDev, "i82801");
2402
2403	/*
2404	* Register I/O ports and save state.
2405	*/
2406	rc = PDMDevHlpIOPortRegister(pDevIns, 0x0cf8, 1, NULL, ich9pciIOPortAddressWrite, ich9pciIOPortAddressRead, NULL, NULL, "ICH9 (PCI)");
2407	if (RT_FAILURE(rc))
2408	return rc;
2409	rc = PDMDevHlpIOPortRegister(pDevIns, 0x0cfc, 4, NULL, ich9pciIOPortDataWrite, ich9pciIOPortDataRead, NULL, NULL, "ICH9 (PCI)");
2410	if (RT_FAILURE(rc))
2411	return rc;
2412	if (fGCEnabled)
2413	{
2414	rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x0cf8, 1, NIL_RTGCPTR, "ich9pciIOPortAddressWrite", "ich9pciIOPortAddressRead", NULL, NULL, "ICH9 (PCI)");
2415	if (RT_FAILURE(rc))
2416	return rc;
2417	rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x0cfc, 4, NIL_RTGCPTR, "ich9pciIOPortDataWrite", "ich9pciIOPortDataRead", NULL, NULL, "ICH9 (PCI)");
2418	if (RT_FAILURE(rc))
2419	return rc;
2420	}
2421	if (fR0Enabled)
2422	{
2423	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x0cf8, 1, NIL_RTR0PTR, "ich9pciIOPortAddressWrite", "ich9pciIOPortAddressRead", NULL, NULL, "ICH9 (PCI)");
2424	if (RT_FAILURE(rc))
2425	return rc;
2426	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x0cfc, 4, NIL_RTR0PTR, "ich9pciIOPortDataWrite", "ich9pciIOPortDataRead", NULL, NULL, "ICH9 (PCI)");
2427	if (RT_FAILURE(rc))
2428	return rc;
2429	}
2430
2431	if (pGlobals->u64PciConfigMMioAddress != 0)
2432	{
2433	rc = PDMDevHlpMMIORegister(pDevIns,
2434	pGlobals->u64PciConfigMMioAddress,
2435	pGlobals->u64PciConfigMMioLength,
2436	0,
2437	ich9pciMcfgMMIOWrite,
2438	ich9pciMcfgMMIORead,
2439	NULL /* fill */,
2440	"MCFG ranges");
2441	if (RT_FAILURE(rc))
2442	{
2443	AssertMsgRC(rc, ("Cannot register MCFG MMIO: %Rrc\n", rc));
2444	return rc;
2445	}
2446
2447	if (fGCEnabled)
2448	{
2449
2450	rc = PDMDevHlpMMIORegisterRC(pDevIns,
2451	pGlobals->u64PciConfigMMioAddress,
2452	pGlobals->u64PciConfigMMioLength,
2453	0,
2454	"ich9pciMcfgMMIOWrite",
2455	"ich9pciMcfgMMIORead",
2456	NULL /* fill */);
2457	if (RT_FAILURE(rc))
2458	{
2459	AssertMsgRC(rc, ("Cannot register MCFG MMIO (GC): %Rrc\n", rc));
2460	return rc;
2461	}
2462	}
2463
2464
2465	if (fR0Enabled)
2466	{
2467
2468	rc = PDMDevHlpMMIORegisterR0(pDevIns,
2469	pGlobals->u64PciConfigMMioAddress,
2470	pGlobals->u64PciConfigMMioLength,
2471	0,
2472	"ich9pciMcfgMMIOWrite",
2473	"ich9pciMcfgMMIORead",
2474	NULL /* fill */);
2475	if (RT_FAILURE(rc))
2476	{
2477	AssertMsgRC(rc, ("Cannot register MCFG MMIO (R0): %Rrc\n", rc));
2478	return rc;
2479	}
2480	}
2481	}
2482
2483	rc = PDMDevHlpSSMRegisterEx(pDevIns, VBOX_ICH9PCI_SAVED_STATE_VERSION_CURRENT,
2484	sizeof(pBus) + 16128, "pgm",
2485	NULL, NULL, NULL,
2486	NULL, ich9pciR3SaveExec, NULL,
2487	NULL, ich9pciR3LoadExec, NULL);
2488	if (RT_FAILURE(rc))
2489	return rc;
2490
2491
2492	/** @todo: other chipset devices shall be registered too */
2493	/** @todo: what to with bridges? */
2494
2495	PDMDevHlpDBGFInfoRegister(pDevIns, "pci", "Display PCI bus status. (no arguments)", ich9pciInfo);
2496
2497	return VINF_SUCCESS;
2498	}
2499
2500	static void ich9pciResetDevice(PPCIDEVICE pDev)
2501	{
2502	PPCIBUS pBus = pDev->Int.s.CTX_SUFF(pBus);
2503	int rc;
2504
2505	/* Clear regions */
2506	for (int iRegion = 0; iRegion < PCI_NUM_REGIONS; iRegion++)
2507	{
2508	PCIIORegion* pRegion = &pDev->Int.s.aIORegions[iRegion];
2509	if (pRegion->size == 0)
2510	continue;
2511
2512	ich9pciUnmapRegion(pDev, iRegion);
2513	}
2514
2515	PCIDevSetCommand(pDev,
2516	PCIDevGetCommand(pDev)
2517	&
2518	~(VBOX_PCI_COMMAND_IO \|
2519	VBOX_PCI_COMMAND_MEMORY \|
2520	VBOX_PCI_COMMAND_MASTER));
2521
2522	/* Bridge device reset handlers processed later */
2523	if (!PCIIsPci2PciBridge(pDev))
2524	{
2525	PCIDevSetByte(pDev, VBOX_PCI_CACHE_LINE_SIZE, 0x0);
2526	PCIDevSetInterruptLine(pDev, 0x0);
2527	}
2528	}
2529
2530
2531	/**
2532	* @copydoc FNPDMDEVRESET
2533	*/
2534	static DECLCALLBACK(void) ich9pciReset(PPDMDEVINS pDevIns)
2535	{
2536	PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
2537	PPCIBUS pBus = &pGlobals->aPciBus;
2538
2539	/* PCI-specific reset for each device. */
2540	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
2541	{
2542	if (pBus->apDevices[i])
2543	ich9pciResetDevice(pBus->apDevices[i]);
2544	}
2545
2546	for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
2547	{
2548	if (pBus->papBridgesR3[iBridge])
2549	ich9pcibridgeReset(pBus->papBridgesR3[iBridge]->pDevIns);
2550	}
2551
2552	ich9pciFakePCIBIOS(pDevIns);
2553	}
2554
2555	static void ich9pciRelocateDevice(PPCIDEVICE pDev, RTGCINTPTR offDelta)
2556	{
2557	if (pDev)
2558	{
2559	pDev->Int.s.pBusRC += offDelta;
2560	if (pDev->Int.s.pMsixPageRC)
2561	pDev->Int.s.pMsixPageRC += offDelta;
2562	}
2563	}
2564
2565	/**
2566	* @copydoc FNPDMDEVRELOCATE
2567	*/
2568	static DECLCALLBACK(void) ich9pciRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
2569	{
2570	PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
2571	PPCIBUS pBus = &pGlobals->aPciBus;
2572	pGlobals->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2573
2574	pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
2575	pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2576
2577	/* Relocate RC pointers for the attached pci devices. */
2578	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
2579	ich9pciRelocateDevice(pBus->apDevices[i], offDelta);
2580
2581	}
2582
2583	/**
2584	* @interface_method_impl{PDMDEVREG,pfnConstruct}
2585	*/
2586	static DECLCALLBACK(int) ich9pcibridgeConstruct(PPDMDEVINS pDevIns,
2587	int iInstance,
2588	PCFGMNODE pCfg)
2589	{
2590	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
2591
2592	/*
2593	* Validate and read configuration.
2594	*/
2595	if (!CFGMR3AreValuesValid(pCfg, "GCEnabled\0" "R0Enabled\0"))
2596	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
2597
2598	/* check if RC code is enabled. */
2599	bool fGCEnabled;
2600	int rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
2601	if (RT_FAILURE(rc))
2602	return PDMDEV_SET_ERROR(pDevIns, rc,
2603	N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
2604
2605	/* check if R0 code is enabled. */
2606	bool fR0Enabled;
2607	rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
2608	if (RT_FAILURE(rc))
2609	return PDMDEV_SET_ERROR(pDevIns, rc,
2610	N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
2611	Log(("PCI: fGCEnabled=%RTbool fR0Enabled=%RTbool\n", fGCEnabled, fR0Enabled));
2612
2613	/*
2614	* Init data and register the PCI bus.
2615	*/
2616	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
2617	pBus->pDevInsR3 = pDevIns;
2618	pBus->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2619	pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2620	pBus->papBridgesR3 = (PPCIDEVICE )PDMDevHlpMMHeapAllocZ(pDevIns, sizeof(PPCIDEVICE) RT_ELEMENTS(pBus->apDevices));
2621
2622	PDMPCIBUSREG PciBusReg;
2623	PciBusReg.u32Version = PDM_PCIBUSREG_VERSION;
2624	PciBusReg.pfnRegisterR3 = ich9pcibridgeRegister;
2625	PciBusReg.pfnRegisterMsiR3 = ich9pciRegisterMsi;
2626	PciBusReg.pfnIORegionRegisterR3 = ich9pciIORegionRegister;
2627	PciBusReg.pfnSetConfigCallbacksR3 = ich9pciSetConfigCallbacks;
2628	PciBusReg.pfnSetIrqR3 = ich9pcibridgeSetIrq;
2629	PciBusReg.pfnSaveExecR3 = ich9pciGenericSaveExec;
2630	PciBusReg.pfnLoadExecR3 = ich9pciGenericLoadExec;
2631	PciBusReg.pfnFakePCIBIOSR3 = NULL; /* Only needed for the first bus. */
2632	PciBusReg.pszSetIrqRC = fGCEnabled ? "ich9pcibridgeSetIrq" : NULL;
2633	PciBusReg.pszSetIrqR0 = fR0Enabled ? "ich9pcibridgeSetIrq" : NULL;
2634	rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBus->pPciHlpR3);
2635	if (RT_FAILURE(rc))
2636	return PDMDEV_SET_ERROR(pDevIns, rc,
2637	N_("Failed to register ourselves as a PCI Bus"));
2638	if (pBus->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
2639	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
2640	N_("PCI helper version mismatch; got %#x expected %#x"),
2641	pBus->pPciHlpR3->u32Version, PDM_PCIHLPR3_VERSION);
2642
2643	pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
2644	pBus->pPciHlpR0 = pBus->pPciHlpR3->pfnGetR0Helpers(pDevIns);
2645
2646	/*
2647	* Fill in PCI configs and add them to the bus.
2648	*/
2649	PCIDevSetVendorId( &pBus->aPciDev, 0x8086); /* Intel */
2650	PCIDevSetDeviceId( &pBus->aPciDev, 0x2448); /* 82801 Mobile PCI bridge. */
2651	PCIDevSetRevisionId(&pBus->aPciDev, 0xf2);
2652	PCIDevSetClassSub( &pBus->aPciDev, 0x04); /* pci2pci */
2653	PCIDevSetClassBase( &pBus->aPciDev, 0x06); /* PCI_bridge */
2654	PCIDevSetClassProg( &pBus->aPciDev, 0x01); /* Supports subtractive decoding. */
2655	PCIDevSetHeaderType(&pBus->aPciDev, 0x01); /* Single function device which adheres to the PCI-to-PCI bridge spec. */
2656	PCIDevSetCommand( &pBus->aPciDev, 0x00);
2657	PCIDevSetStatus( &pBus->aPciDev, 0x20); /* 66MHz Capable. */
2658	PCIDevSetInterruptLine(&pBus->aPciDev, 0x00); /* This device does not assert interrupts. */
2659
2660	/*
2661	* This device does not generate interrupts. Interrupt delivery from
2662	* devices attached to the bus is unaffected.
2663	*/
2664	PCIDevSetInterruptPin (&pBus->aPciDev, 0x00);
2665
2666	pBus->aPciDev.pDevIns = pDevIns;
2667
2668	/* Bridge-specific data */
2669	PCISetPci2PciBridge(&pBus->aPciDev);
2670	pBus->aPciDev.Int.s.pfnBridgeConfigRead = ich9pcibridgeConfigRead;
2671	pBus->aPciDev.Int.s.pfnBridgeConfigWrite = ich9pcibridgeConfigWrite;
2672
2673	/*
2674	* Register this PCI bridge. The called function will take care on which bus we will get registered.
2675	*/
2676	rc = PDMDevHlpPCIRegister (pDevIns, &pBus->aPciDev);
2677	if (RT_FAILURE(rc))
2678	return rc;
2679
2680	/*
2681	* The iBus property doesn't really represent the bus number
2682	* because the guest and the BIOS can choose different bus numbers
2683	* for them.
2684	* The bus number is mainly for the setIrq function to indicate
2685	* when the host bus is reached which will have iBus = 0.
2686	* That's why the + 1.
2687	*/
2688	pBus->iBus = iInstance + 1;
2689
2690	/*
2691	* Register SSM handlers. We use the same saved state version as for the host bridge
2692	* to make changes easier.
2693	*/
2694	rc = PDMDevHlpSSMRegisterEx(pDevIns, VBOX_ICH9PCI_SAVED_STATE_VERSION_CURRENT,
2695	sizeof(pBus) + 16128,
2696	"pgm" /* before */,
2697	NULL, NULL, NULL,
2698	NULL, ich9pcibridgeR3SaveExec, NULL,
2699	NULL, ich9pcibridgeR3LoadExec, NULL);
2700	if (RT_FAILURE(rc))
2701	return rc;
2702
2703
2704	return VINF_SUCCESS;
2705	}
2706
2707	/**
2708	* @copydoc FNPDMDEVRESET
2709	*/
2710	static void ich9pcibridgeReset(PPDMDEVINS pDevIns)
2711	{
2712	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
2713
2714	/* Reset config space to default values. */
2715	PCIDevSetByte(&pBus->aPciDev, VBOX_PCI_PRIMARY_BUS, 0);
2716	PCIDevSetByte(&pBus->aPciDev, VBOX_PCI_SECONDARY_BUS, 0);
2717	PCIDevSetByte(&pBus->aPciDev, VBOX_PCI_SUBORDINATE_BUS, 0);
2718
2719	/* PCI-specific reset for each device. */
2720	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
2721	{
2722	if (pBus->apDevices[i])
2723	ich9pciResetDevice(pBus->apDevices[i]);
2724	}
2725	}
2726
2727
2728	/**
2729	* @copydoc FNPDMDEVRELOCATE
2730	*/
2731	static DECLCALLBACK(void) ich9pcibridgeRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
2732	{
2733	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
2734	pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2735
2736	/* Relocate RC pointers for the attached pci devices. */
2737	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
2738	ich9pciRelocateDevice(pBus->apDevices[i], offDelta);
2739	}
2740
2741	/**
2742	* The PCI bus device registration structure.
2743	*/
2744	const PDMDEVREG g_DevicePciIch9 =
2745	{
2746	/* u32Version */
2747	PDM_DEVREG_VERSION,
2748	/* szName */
2749	"ich9pci",
2750	/* szRCMod */
2751	"VBoxDDGC.gc",
2752	/* szR0Mod */
2753	"VBoxDDR0.r0",
2754	/* pszDescription */
2755	"ICH9 PCI bridge",
2756	/* fFlags */
2757	PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
2758	/* fClass */
2759	PDM_DEVREG_CLASS_BUS_PCI \| PDM_DEVREG_CLASS_BUS_ISA,
2760	/* cMaxInstances */
2761	1,
2762	/* cbInstance */
2763	sizeof(PCIGLOBALS),
2764	/* pfnConstruct */
2765	ich9pciConstruct,
2766	/* pfnDestruct */
2767	NULL,
2768	/* pfnRelocate */
2769	ich9pciRelocate,
2770	/* pfnIOCtl */
2771	NULL,
2772	/* pfnPowerOn */
2773	NULL,
2774	/* pfnReset */
2775	ich9pciReset,
2776	/* pfnSuspend */
2777	NULL,
2778	/* pfnResume */
2779	NULL,
2780	/* pfnAttach */
2781	NULL,
2782	/* pfnDetach */
2783	NULL,
2784	/* pfnQueryInterface */
2785	NULL,
2786	/* pfnInitComplete */
2787	NULL,
2788	/* pfnPowerOff */
2789	NULL,
2790	/* pfnSoftReset */
2791	NULL,
2792	/* u32VersionEnd */
2793	PDM_DEVREG_VERSION
2794	};
2795
2796	/**
2797	* The device registration structure
2798	* for the PCI-to-PCI bridge.
2799	*/
2800	const PDMDEVREG g_DevicePciIch9Bridge =
2801	{
2802	/* u32Version */
2803	PDM_DEVREG_VERSION,
2804	/* szName */
2805	"ich9pcibridge",
2806	/* szRCMod */
2807	"VBoxDDGC.gc",
2808	/* szR0Mod */
2809	"VBoxDDR0.r0",
2810	/* pszDescription */
2811	"ICH9 PCI to PCI bridge",
2812	/* fFlags */
2813	PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
2814	/* fClass */
2815	PDM_DEVREG_CLASS_BUS_PCI,
2816	/* cMaxInstances */
2817	~0,
2818	/* cbInstance */
2819	sizeof(PCIBUS),
2820	/* pfnConstruct */
2821	ich9pcibridgeConstruct,
2822	/* pfnDestruct */
2823	NULL,
2824	/* pfnRelocate */
2825	ich9pcibridgeRelocate,
2826	/* pfnIOCtl */
2827	NULL,
2828	/* pfnPowerOn */
2829	NULL,
2830	/* pfnReset */
2831	NULL, /* Must be NULL, to make sure only bus driver handles reset */
2832	/* pfnSuspend */
2833	NULL,
2834	/* pfnResume */
2835	NULL,
2836	/* pfnAttach */
2837	NULL,
2838	/* pfnDetach */
2839	NULL,
2840	/* pfnQueryInterface */
2841	NULL,
2842	/* pfnInitComplete */
2843	NULL,
2844	/* pfnPowerOff */
2845	NULL,
2846	/* pfnSoftReset */
2847	NULL,
2848	/* u32VersionEnd */
2849	PDM_DEVREG_VERSION
2850	};
2851
2852	#endif /* IN_RING3 */
2853	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */

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source: vbox/trunk/src/VBox/Devices/Bus/DevPciIch9.cpp@ 35753

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