VirtualBox

source: vbox/trunk/src/VBox/Devices/Bus/DevPciIch9.cpp@ 36092

Last change on this file since 36092 was 36092, checked in by vboxsync, 14 years ago

PCI: simplified BIOS init, fixed routing for nontrivial topologies

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1/* $Id: DevPciIch9.cpp 36092 2011-02-26 21:07:51Z vboxsync $ */
2/** @file
3 * DevPCI - ICH9 southbridge PCI bus emulation Device.
4 */
5
6/*
7 * Copyright (C) 2010 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/*******************************************************************************
19 * Header Files *
20 *******************************************************************************/
21#define LOG_GROUP LOG_GROUP_DEV_PCI
22/* Hack to get PCIDEVICEINT declare at the right point - include "PCIInternal.h". */
23#define PCI_INCLUDE_PRIVATE
24#include <VBox/pci.h>
25#include <VBox/msi.h>
26#include <VBox/vmm/pdmdev.h>
27#include <iprt/asm.h>
28#include <iprt/assert.h>
29#include <iprt/string.h>
30#ifdef IN_RING3
31#include <iprt/alloc.h>
32#endif
33
34#include "VBoxDD.h"
35
36#include "MsiCommon.h"
37
38/**
39 * PCI Bus instance.
40 */
41typedef struct PCIBus
42{
43 /** Bus number. */
44 int32_t iBus;
45 /** Number of bridges attached to the bus. */
46 uint32_t cBridges;
47
48 /** Array of PCI devices. We assume 32 slots, each with 8 functions. */
49 R3PTRTYPE(PPCIDEVICE) apDevices[256];
50 /** Array of bridges attached to the bus. */
51 R3PTRTYPE(PPCIDEVICE *) papBridgesR3;
52
53 /** R3 pointer to the device instance. */
54 PPDMDEVINSR3 pDevInsR3;
55 /** Pointer to the PCI R3 helpers. */
56 PCPDMPCIHLPR3 pPciHlpR3;
57
58 /** R0 pointer to the device instance. */
59 PPDMDEVINSR0 pDevInsR0;
60 /** Pointer to the PCI R0 helpers. */
61 PCPDMPCIHLPR0 pPciHlpR0;
62
63 /** RC pointer to the device instance. */
64 PPDMDEVINSRC pDevInsRC;
65 /** Pointer to the PCI RC helpers. */
66 PCPDMPCIHLPRC pPciHlpRC;
67
68 /** The PCI device for the PCI bridge. */
69 PCIDEVICE aPciDev;
70
71} PCIBUS, *PPCIBUS;
72
73
74/** @def PCI_APIC_IRQ_PINS
75 * Number of pins for interrupts if the APIC is used.
76 */
77#define PCI_APIC_IRQ_PINS 8
78
79/**
80 * PCI Globals - This is the host-to-pci bridge and the root bus.
81 */
82typedef struct
83{
84 /** R3 pointer to the device instance. */
85 PPDMDEVINSR3 pDevInsR3;
86 /** R0 pointer to the device instance. */
87 PPDMDEVINSR0 pDevInsR0;
88 /** RC pointer to the device instance. */
89 PPDMDEVINSRC pDevInsRC;
90
91#if HC_ARCH_BITS == 64
92 uint32_t Alignment0;
93#endif
94
95 /** PCI bus which is attached to the host-to-PCI bridge. */
96 PCIBUS aPciBus;
97
98 /** I/O APIC irq levels */
99 volatile uint32_t uaPciApicIrqLevels[PCI_APIC_IRQ_PINS];
100
101#if 1 /* Will be moved into the BIOS soon. */
102 /** The next I/O port address which the PCI BIOS will use. */
103 uint32_t uPciBiosIo;
104 /** The next MMIO address which the PCI BIOS will use. */
105 uint32_t uPciBiosMmio;
106 /** Actual bus number. */
107 uint8_t uBus;
108#endif
109 /* Physical address of PCI config space MMIO region */
110 uint64_t u64PciConfigMMioAddress;
111 /* Length of PCI config space MMIO region */
112 uint64_t u64PciConfigMMioLength;
113
114
115 /** Config register. */
116 uint32_t uConfigReg;
117} PCIGLOBALS, *PPCIGLOBALS;
118
119
120typedef struct {
121 uint8_t iBus;
122 uint8_t iDeviceFunc;
123 uint16_t iRegister;
124} PciAddress;
125
126/*******************************************************************************
127 * Defined Constants And Macros *
128 *******************************************************************************/
129
130/** @def VBOX_ICH9PCI_SAVED_STATE_VERSION
131 * Saved state version of the ICH9 PCI bus device.
132 */
133#define VBOX_ICH9PCI_SAVED_STATE_VERSION_NOMSI 1
134#define VBOX_ICH9PCI_SAVED_STATE_VERSION_MSI 2
135#define VBOX_ICH9PCI_SAVED_STATE_VERSION_CURRENT VBOX_ICH9PCI_SAVED_STATE_VERSION_MSI
136
137/** Converts a bus instance pointer to a device instance pointer. */
138#define PCIBUS_2_DEVINS(pPciBus) ((pPciBus)->CTX_SUFF(pDevIns))
139/** Converts a device instance pointer to a PCIGLOBALS pointer. */
140#define DEVINS_2_PCIGLOBALS(pDevIns) ((PPCIGLOBALS)(PDMINS_2_DATA(pDevIns, PPCIGLOBALS)))
141/** Converts a device instance pointer to a PCIBUS pointer. */
142#define DEVINS_2_PCIBUS(pDevIns) ((PPCIBUS)(&PDMINS_2_DATA(pDevIns, PPCIGLOBALS)->aPciBus))
143/** Converts a pointer to a PCI root bus instance to a PCIGLOBALS pointer.
144 */
145#define PCIROOTBUS_2_PCIGLOBALS(pPciBus) ( (PPCIGLOBALS)((uintptr_t)(pPciBus) - RT_OFFSETOF(PCIGLOBALS, aPciBus)) )
146
147
148/** @def PCI_LOCK
149 * Acquires the PDM lock. This is a NOP if locking is disabled. */
150/** @def PCI_UNLOCK
151 * Releases the PDM lock. This is a NOP if locking is disabled. */
152#define PCI_LOCK(pDevIns, rc) \
153 do { \
154 int rc2 = DEVINS_2_PCIBUS(pDevIns)->CTX_SUFF(pPciHlp)->pfnLock((pDevIns), rc); \
155 if (rc2 != VINF_SUCCESS) \
156 return rc2; \
157 } while (0)
158#define PCI_UNLOCK(pDevIns) \
159 DEVINS_2_PCIBUS(pDevIns)->CTX_SUFF(pPciHlp)->pfnUnlock(pDevIns)
160
161#ifndef VBOX_DEVICE_STRUCT_TESTCASE
162
163RT_C_DECLS_BEGIN
164
165PDMBOTHCBDECL(void) ich9pciSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel);
166PDMBOTHCBDECL(void) ich9pcibridgeSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel);
167PDMBOTHCBDECL(int) ich9pciIOPortAddressWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
168PDMBOTHCBDECL(int) ich9pciIOPortAddressRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb);
169PDMBOTHCBDECL(int) ich9pciIOPortDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
170PDMBOTHCBDECL(int) ich9pciIOPortDataRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb);
171PDMBOTHCBDECL(int) ich9pciMcfgMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb);
172PDMBOTHCBDECL(int) ich9pciMcfgMMIORead (PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb);
173
174RT_C_DECLS_END
175
176/* Prototypes */
177static void ich9pciSetIrqInternal(PPCIGLOBALS pGlobals, uint8_t uDevFn, PPCIDEVICE pPciDev, int iIrq, int iLevel);
178#ifdef IN_RING3
179static void ich9pcibridgeReset(PPDMDEVINS pDevIns);
180static int ich9pciRegisterInternal(PPCIBUS pBus, int iDev, PPCIDEVICE pPciDev, const char *pszName);
181static void ich9pciUpdateMappings(PCIDevice *pDev);
182static DECLCALLBACK(uint32_t) ich9pciConfigReadDev(PCIDevice *aDev, uint32_t u32Address, unsigned len);
183DECLINLINE(PPCIDEVICE) ich9pciFindBridge(PPCIBUS pBus, uint8_t iBus);
184static void ich9pciBiosInitDevice(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn);
185#endif
186
187// See 7.2.2. PCI Express Enhanced Configuration Mechanism for details of address
188// mapping, we take n=6 approach
189DECLINLINE(void) ich9pciPhysToPciAddr(PPCIGLOBALS pGlobals, RTGCPHYS GCPhysAddr, PciAddress* pPciAddr)
190{
191 pPciAddr->iBus = (GCPhysAddr >> 20) & ((1<<6) - 1);
192 pPciAddr->iDeviceFunc = (GCPhysAddr >> 12) & ((1<<(5+3)) - 1); // 5 bits - device, 3 bits - function
193 pPciAddr->iRegister = (GCPhysAddr >> 0) & ((1<<(6+4+2)) - 1); // 6 bits - register, 4 bits - extended register, 2 bits -Byte Enable
194}
195
196DECLINLINE(void) ich9pciStateToPciAddr(PPCIGLOBALS pGlobals, RTGCPHYS addr, PciAddress* pPciAddr)
197{
198 pPciAddr->iBus = (pGlobals->uConfigReg >> 16) & 0xff;
199 pPciAddr->iDeviceFunc = (pGlobals->uConfigReg >> 8) & 0xff;
200 pPciAddr->iRegister = (pGlobals->uConfigReg & 0xfc) | (addr & 3);
201}
202
203PDMBOTHCBDECL(void) ich9pciSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel)
204{
205 ich9pciSetIrqInternal(PDMINS_2_DATA(pDevIns, PPCIGLOBALS), pPciDev->devfn, pPciDev, iIrq, iLevel);
206}
207
208PDMBOTHCBDECL(void) ich9pcibridgeSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel)
209{
210 /*
211 * The PCI-to-PCI bridge specification defines how the interrupt pins
212 * are routed from the secondary to the primary bus (see chapter 9).
213 * iIrq gives the interrupt pin the pci device asserted.
214 * We change iIrq here according to the spec and call the SetIrq function
215 * of our parent passing the device which asserted the interrupt instead of the device of the bridge.
216 */
217 PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
218 PPCIDEVICE pPciDevBus = pPciDev;
219 int iIrqPinBridge = iIrq;
220 uint8_t uDevFnBridge = 0;
221
222 /* Walk the chain until we reach the host bus. */
223 do
224 {
225 uDevFnBridge = pBus->aPciDev.devfn;
226 iIrqPinBridge = ((pPciDevBus->devfn >> 3) + iIrqPinBridge) & 3;
227
228 /* Get the parent. */
229 pBus = pBus->aPciDev.Int.s.CTX_SUFF(pBus);
230 pPciDevBus = &pBus->aPciDev;
231 } while (pBus->iBus != 0);
232
233 AssertMsgReturnVoid(pBus->iBus == 0, ("This is not the host pci bus iBus=%d\n", pBus->iBus));
234 ich9pciSetIrqInternal(PCIROOTBUS_2_PCIGLOBALS(pBus), uDevFnBridge, pPciDev, iIrqPinBridge, iLevel);
235}
236
237/**
238 * Port I/O Handler for PCI address OUT operations.
239 *
240 * @returns VBox status code.
241 *
242 * @param pDevIns The device instance.
243 * @param pvUser User argument - ignored.
244 * @param uPort Port number used for the OUT operation.
245 * @param u32 The value to output.
246 * @param cb The value size in bytes.
247 */
248PDMBOTHCBDECL(int) ich9pciIOPortAddressWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
249{
250 Log(("ich9pciIOPortAddressWrite: Port=%#x u32=%#x cb=%d\n", Port, u32, cb));
251 NOREF(pvUser);
252 if (cb == 4)
253 {
254 PPCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
255
256 PCI_LOCK(pDevIns, VINF_IOM_HC_IOPORT_WRITE);
257 pThis->uConfigReg = u32 & ~3; /* Bits 0-1 are reserved and we silently clear them */
258 PCI_UNLOCK(pDevIns);
259 }
260
261 return VINF_SUCCESS;
262}
263
264/**
265 * Port I/O Handler for PCI address IN operations.
266 *
267 * @returns VBox status code.
268 *
269 * @param pDevIns The device instance.
270 * @param pvUser User argument - ignored.
271 * @param uPort Port number used for the IN operation.
272 * @param pu32 Where to store the result.
273 * @param cb Number of bytes read.
274 */
275PDMBOTHCBDECL(int) ich9pciIOPortAddressRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
276{
277 NOREF(pvUser);
278 if (cb == 4)
279 {
280 PPCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
281 PCI_LOCK(pDevIns, VINF_IOM_HC_IOPORT_READ);
282 *pu32 = pThis->uConfigReg;
283 PCI_UNLOCK(pDevIns);
284 Log(("pciIOPortAddressRead: Port=%#x cb=%d -> %#x\n", Port, cb, *pu32));
285 return VINF_SUCCESS;
286 }
287
288 Log(("ich9pciIOPortAddressRead: Port=%#x cb=%d VERR_IOM_IOPORT_UNUSED\n", Port, cb));
289
290 return VERR_IOM_IOPORT_UNUSED;
291}
292
293static int ich9pciDataWriteAddr(PPCIGLOBALS pGlobals, PciAddress* pAddr,
294 uint32_t val, int cb, int rcReschedule)
295{
296 int rc = VINF_SUCCESS;
297
298 if (pAddr->iRegister > 0xff)
299 {
300 LogRel(("PCI: attempt to write extended register: %x (%d) <- val\n", pAddr->iRegister, cb, val));
301 goto out;
302 }
303
304 if (pAddr->iBus != 0)
305 {
306 if (pGlobals->aPciBus.cBridges)
307 {
308#ifdef IN_RING3 /** @todo do lookup in R0/RC too! */
309 PPCIDEVICE pBridgeDevice = ich9pciFindBridge(&pGlobals->aPciBus, pAddr->iBus);
310 if (pBridgeDevice)
311 {
312 AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigWrite);
313 pBridgeDevice->Int.s.pfnBridgeConfigWrite(pBridgeDevice->pDevIns, pAddr->iBus, pAddr->iDeviceFunc, pAddr->iRegister, val, cb);
314 }
315 else
316 {
317 // do nothing, bridge not found
318 }
319#else
320 rc = rcReschedule;
321 goto out;
322#endif
323 }
324 }
325 else
326 {
327 if (pGlobals->aPciBus.apDevices[pAddr->iDeviceFunc])
328 {
329#ifdef IN_RING3
330 R3PTRTYPE(PCIDevice *) aDev = pGlobals->aPciBus.apDevices[pAddr->iDeviceFunc];
331 Log(("ich9pciConfigWrite: %s: addr=%02x val=%08x len=%d\n", aDev->name, pAddr->iRegister, val, cb));
332 aDev->Int.s.pfnConfigWrite(aDev, pAddr->iRegister, val, cb);
333#else
334 rc = rcReschedule;
335 goto out;
336#endif
337 }
338 }
339
340 out:
341 Log2(("ich9pciDataWriteAddr: %02x:%02x:%02x reg %x(%d) %x %Rrc\n",
342 pAddr->iBus, pAddr->iDeviceFunc >> 3, pAddr->iDeviceFunc & 0x7, pAddr->iRegister,
343 cb, val, rc));
344
345 return rc;
346}
347
348static int ich9pciDataWrite(PPCIGLOBALS pGlobals, uint32_t addr, uint32_t val, int len)
349{
350 PciAddress aPciAddr;
351
352 LogFlow(("ich9pciDataWrite: config=%08x val=%08x len=%d\n", pGlobals->uConfigReg, val, len));
353
354 if (!(pGlobals->uConfigReg & (1 << 31)))
355 return VINF_SUCCESS;
356
357 if ((pGlobals->uConfigReg & 0x3) != 0)
358 return VINF_SUCCESS;
359
360 /* Compute destination device */
361 ich9pciStateToPciAddr(pGlobals, addr, &aPciAddr);
362
363 return ich9pciDataWriteAddr(pGlobals, &aPciAddr, val, len, VINF_IOM_HC_IOPORT_WRITE);
364}
365
366static void ich9pciNoMem(void* ptr, int cb)
367{
368 for (int i = 0; i < cb; i++)
369 ((uint8_t*)ptr)[i] = 0xff;
370}
371
372/**
373 * Port I/O Handler for PCI data OUT operations.
374 *
375 * @returns VBox status code.
376 *
377 * @param pDevIns The device instance.
378 * @param pvUser User argument - ignored.
379 * @param uPort Port number used for the OUT operation.
380 * @param u32 The value to output.
381 * @param cb The value size in bytes.
382 */
383PDMBOTHCBDECL(int) ich9pciIOPortDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
384{
385 Log(("pciIOPortDataWrite: Port=%#x u32=%#x cb=%d\n", Port, u32, cb));
386 NOREF(pvUser);
387 int rc = VINF_SUCCESS;
388 if (!(Port % cb))
389 {
390 PCI_LOCK(pDevIns, VINF_IOM_HC_IOPORT_WRITE);
391 rc = ich9pciDataWrite(PDMINS_2_DATA(pDevIns, PPCIGLOBALS), Port, u32, cb);
392 PCI_UNLOCK(pDevIns);
393 }
394 else
395 AssertMsgFailed(("Unaligned write to port %#x u32=%#x cb=%d\n", Port, u32, cb));
396 return rc;
397}
398
399static int ich9pciDataReadAddr(PPCIGLOBALS pGlobals, PciAddress* pPciAddr, int cb,
400 uint32_t *pu32, int rcReschedule)
401{
402 int rc = VINF_SUCCESS;
403
404 if (pPciAddr->iRegister > 0xff)
405 {
406 LogRel(("PCI: attempt to read extended register: %x\n", pPciAddr->iRegister));
407 ich9pciNoMem(pu32, cb);
408 goto out;
409 }
410
411
412 if (pPciAddr->iBus != 0)
413 {
414 if (pGlobals->aPciBus.cBridges)
415 {
416#ifdef IN_RING3 /** @todo do lookup in R0/RC too! */
417 PPCIDEVICE pBridgeDevice = ich9pciFindBridge(&pGlobals->aPciBus, pPciAddr->iBus);
418 if (pBridgeDevice)
419 {
420 AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigRead);
421 *pu32 = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->pDevIns, pPciAddr->iBus, pPciAddr->iDeviceFunc, pPciAddr->iRegister, cb);
422 }
423 else
424 ich9pciNoMem(pu32, cb);
425#else
426 rc = rcReschedule;
427 goto out;
428#endif
429 } else
430 ich9pciNoMem(pu32, cb);
431 }
432 else
433 {
434 if (pGlobals->aPciBus.apDevices[pPciAddr->iDeviceFunc])
435 {
436#ifdef IN_RING3
437 R3PTRTYPE(PCIDevice *) aDev = pGlobals->aPciBus.apDevices[pPciAddr->iDeviceFunc];
438 *pu32 = aDev->Int.s.pfnConfigRead(aDev, pPciAddr->iRegister, cb);
439 Log(("ich9pciDataReadAddr: %s: addr=%02x val=%08x len=%d\n", aDev->name, pPciAddr->iRegister, *pu32, cb));
440#else
441 rc = rcReschedule;
442 goto out;
443#endif
444 }
445 else
446 ich9pciNoMem(pu32, cb);
447 }
448
449 out:
450 Log2(("ich9pciDataReadAddr: %02x:%02x:%02x reg %x(%d) gave %x %Rrc\n",
451 pPciAddr->iBus, pPciAddr->iDeviceFunc >> 3, pPciAddr->iDeviceFunc & 0x7, pPciAddr->iRegister,
452 cb, *pu32, rc));
453
454 return rc;
455}
456
457static int ich9pciDataRead(PPCIGLOBALS pGlobals, uint32_t addr, int cb, uint32_t *pu32)
458{
459 PciAddress aPciAddr;
460
461 LogFlow(("ich9pciDataRead: config=%x cb=%d\n", pGlobals->uConfigReg, cb));
462
463 *pu32 = 0xffffffff;
464
465 if (!(pGlobals->uConfigReg & (1 << 31)))
466 return VINF_SUCCESS;
467
468 if ((pGlobals->uConfigReg & 0x3) != 0)
469 return VINF_SUCCESS;
470
471 /* Compute destination device */
472 ich9pciStateToPciAddr(pGlobals, addr, &aPciAddr);
473
474 return ich9pciDataReadAddr(pGlobals, &aPciAddr, cb, pu32, VINF_IOM_HC_IOPORT_READ);
475}
476
477/**
478 * Port I/O Handler for PCI data IN operations.
479 *
480 * @returns VBox status code.
481 *
482 * @param pDevIns The device instance.
483 * @param pvUser User argument - ignored.
484 * @param uPort Port number used for the IN operation.
485 * @param pu32 Where to store the result.
486 * @param cb Number of bytes read.
487 */
488PDMBOTHCBDECL(int) ich9pciIOPortDataRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
489{
490 NOREF(pvUser);
491 if (!(Port % cb))
492 {
493 PCI_LOCK(pDevIns, VINF_IOM_HC_IOPORT_READ);
494 int rc = ich9pciDataRead(PDMINS_2_DATA(pDevIns, PPCIGLOBALS), Port, cb, pu32);
495 PCI_UNLOCK(pDevIns);
496 Log(("pciIOPortDataRead: Port=%#x cb=%#x -> %#x (%Rrc)\n", Port, cb, *pu32, rc));
497 return rc;
498 }
499 AssertMsgFailed(("Unaligned read from port %#x cb=%d\n", Port, cb));
500 return VERR_IOM_IOPORT_UNUSED;
501}
502
503/* Compute mapping of PCI slot and IRQ number to APIC interrupt line */
504DECLINLINE(int) ich9pciSlot2ApicIrq(uint8_t uSlot, int irq_num)
505{
506 return (irq_num + uSlot) & 7;
507}
508
509/* return the global irq number corresponding to a given device irq
510 pin. We could also use the bus number to have a more precise
511 mapping. This is the implementation note described in the PCI spec chapter 2.2.6 */
512DECLINLINE(int) ich9pciSlotGetPirq(uint8_t uBus, uint8_t uDevFn, int iIrqNum)
513{
514 int iSlotAddend = (uDevFn >> 3) - 1;
515 return (iIrqNum + iSlotAddend) & 3;
516}
517
518/* irqs corresponding to PCI irqs A-D, must match pci_irq_list in rombios.c */
519static const uint8_t aPciIrqs[4] = { 11, 10, 9, 5 };
520
521/* Add one more level up request on APIC input line */
522DECLINLINE(void) ich9pciApicLevelUp(PPCIGLOBALS pGlobals, int irq_num)
523{
524 ASMAtomicIncU32(&pGlobals->uaPciApicIrqLevels[irq_num]);
525}
526
527/* Remove one level up request on APIC input line */
528DECLINLINE(void) ich9pciApicLevelDown(PPCIGLOBALS pGlobals, int irq_num)
529{
530 ASMAtomicDecU32(&pGlobals->uaPciApicIrqLevels[irq_num]);
531}
532
533static void ich9pciApicSetIrq(PPCIBUS pBus, uint8_t uDevFn, PCIDevice *pPciDev, int irq_num1, int iLevel, int iForcedIrq)
534{
535 /* This is only allowed to be called with a pointer to the root bus. */
536 AssertMsg(pBus->iBus == 0, ("iBus=%u\n", pBus->iBus));
537
538 if (iForcedIrq == -1)
539 {
540 int apic_irq, apic_level;
541 PPCIGLOBALS pGlobals = PCIROOTBUS_2_PCIGLOBALS(pBus);
542 int irq_num = ich9pciSlot2ApicIrq(uDevFn >> 3, irq_num1);
543
544 if ((iLevel & PDM_IRQ_LEVEL_HIGH) == PDM_IRQ_LEVEL_HIGH)
545 ich9pciApicLevelUp(pGlobals, irq_num);
546 else if ((iLevel & PDM_IRQ_LEVEL_HIGH) == PDM_IRQ_LEVEL_LOW)
547 ich9pciApicLevelDown(pGlobals, irq_num);
548
549 apic_irq = irq_num + 0x10;
550 apic_level = pGlobals->uaPciApicIrqLevels[irq_num] != 0;
551 Log3(("ich9pciApicSetIrq: %s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d\n",
552 R3STRING(pPciDev->name), irq_num1, iLevel, apic_irq, apic_level, irq_num));
553 pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), apic_irq, apic_level);
554
555 if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP)
556 {
557 /**
558 * we raised it few lines above, as PDM_IRQ_LEVEL_FLIP_FLOP has
559 * PDM_IRQ_LEVEL_HIGH bit set
560 */
561 ich9pciApicLevelDown(pGlobals, irq_num);
562 pPciDev->Int.s.uIrqPinState = PDM_IRQ_LEVEL_LOW;
563 apic_level = pGlobals->uaPciApicIrqLevels[irq_num] != 0;
564 Log3(("ich9pciApicSetIrq: %s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d (flop)\n",
565 R3STRING(pPciDev->name), irq_num1, iLevel, apic_irq, apic_level, irq_num));
566 pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), apic_irq, apic_level);
567 }
568 } else {
569 Log3(("ich9pciApicSetIrq: (forced) %s: irq_num1=%d level=%d acpi_irq=%d\n",
570 R3STRING(pPciDev->name), irq_num1, iLevel, iForcedIrq));
571 pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), iForcedIrq, iLevel);
572 }
573}
574
575static void ich9pciSetIrqInternal(PPCIGLOBALS pGlobals, uint8_t uDevFn, PPCIDEVICE pPciDev, int iIrq, int iLevel)
576{
577
578 if (PCIDevIsIntxDisabled(pPciDev))
579 {
580 if (MsiIsEnabled(pPciDev))
581 {
582 PPDMDEVINS pDevIns = pGlobals->aPciBus.CTX_SUFF(pDevIns);
583 MsiNotify(pDevIns, pGlobals->aPciBus.CTX_SUFF(pPciHlp), pPciDev, iIrq, iLevel);
584 }
585
586 if (MsixIsEnabled(pPciDev))
587 {
588 PPDMDEVINS pDevIns = pGlobals->aPciBus.CTX_SUFF(pDevIns);
589 MsixNotify(pDevIns, pGlobals->aPciBus.CTX_SUFF(pPciHlp), pPciDev, iIrq, iLevel);
590 }
591 return;
592 }
593
594 PPCIBUS pBus = &pGlobals->aPciBus;
595 const bool fIsAcpiDevice = PCIDevGetDeviceId(pPciDev) == 0x7113;
596
597 /* Check if the state changed. */
598 if (pPciDev->Int.s.uIrqPinState != iLevel)
599 {
600 pPciDev->Int.s.uIrqPinState = (iLevel & PDM_IRQ_LEVEL_HIGH);
601
602 /* Send interrupt to I/O APIC only now. */
603 if (fIsAcpiDevice)
604 /*
605 * ACPI needs special treatment since SCI is hardwired and
606 * should not be affected by PCI IRQ routing tables at the
607 * same time SCI IRQ is shared in PCI sense hence this
608 * kludge (i.e. we fetch the hardwired value from ACPIs
609 * PCI device configuration space).
610 */
611 ich9pciApicSetIrq(pBus, uDevFn, pPciDev, -1, iLevel, PCIDevGetInterruptLine(pPciDev));
612 else
613 ich9pciApicSetIrq(pBus, uDevFn, pPciDev, iIrq, iLevel, -1);
614 }
615}
616
617PDMBOTHCBDECL(int) ich9pciMcfgMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
618{
619 PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
620 PciAddress aDest;
621 uint32_t u32 = 0;
622
623 Log2(("ich9pciMcfgMMIOWrite: %RGp(%d) \n", GCPhysAddr, cb));
624
625 PCI_LOCK(pDevIns, VINF_IOM_HC_MMIO_WRITE);
626
627 ich9pciPhysToPciAddr(pGlobals, GCPhysAddr, &aDest);
628
629 switch (cb)
630 {
631 case 1:
632 u32 = *(uint8_t*)pv;
633 break;
634 case 2:
635 u32 = *(uint16_t*)pv;
636 break;
637 case 4:
638 u32 = *(uint32_t*)pv;
639 break;
640 default:
641 Assert(false);
642 break;
643 }
644 int rc = ich9pciDataWriteAddr(pGlobals, &aDest, u32, cb, VINF_IOM_HC_MMIO_WRITE);
645 PCI_UNLOCK(pDevIns);
646
647 return rc;
648}
649
650PDMBOTHCBDECL(int) ich9pciMcfgMMIORead (PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
651{
652 PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
653 PciAddress aDest;
654 uint32_t rv;
655
656 LogFlow(("ich9pciMcfgMMIORead: %RGp(%d) \n", GCPhysAddr, cb));
657
658 PCI_LOCK(pDevIns, VINF_IOM_HC_MMIO_READ);
659
660 ich9pciPhysToPciAddr(pGlobals, GCPhysAddr, &aDest);
661
662 int rc = ich9pciDataReadAddr(pGlobals, &aDest, cb, &rv, VINF_IOM_HC_MMIO_READ);
663
664 if (RT_SUCCESS(rc))
665 {
666 switch (cb)
667 {
668 case 1:
669 *(uint8_t*)pv = (uint8_t)rv;
670 break;
671 case 2:
672 *(uint16_t*)pv = (uint16_t)rv;
673 break;
674 case 4:
675 *(uint32_t*)pv = (uint32_t)rv;
676 break;
677 default:
678 Assert(false);
679 break;
680 }
681 }
682 PCI_UNLOCK(pDevIns);
683
684 return rc;
685}
686
687#ifdef IN_RING3
688
689DECLINLINE(PPCIDEVICE) ich9pciFindBridge(PPCIBUS pBus, uint8_t iBus)
690{
691 /* Search for a fitting bridge. */
692 for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
693 {
694 /*
695 * Examine secondary and subordinate bus number.
696 * If the target bus is in the range we pass the request on to the bridge.
697 */
698 PPCIDEVICE pBridge = pBus->papBridgesR3[iBridge];
699 AssertMsg(pBridge && pciDevIsPci2PciBridge(pBridge),
700 ("Device is not a PCI bridge but on the list of PCI bridges\n"));
701 uint32_t uSecondary = PCIDevGetByte(pBridge, VBOX_PCI_SECONDARY_BUS);
702 uint32_t uSubordinate = PCIDevGetByte(pBridge, VBOX_PCI_SUBORDINATE_BUS);
703 Log2(("ich9pciFindBridge on bus %p, bridge %d: %d in %d..%d\n", pBus, iBridge, iBus, uSecondary, uSubordinate));
704 if (iBus >= uSecondary && iBus <= uSubordinate)
705 return pBridge;
706 }
707
708 /* Nothing found. */
709 return NULL;
710}
711
712DECLINLINE(uint32_t) ich9pciGetRegionReg(int iRegion)
713{
714 return (iRegion == VBOX_PCI_ROM_SLOT) ?
715 VBOX_PCI_ROM_ADDRESS : (VBOX_PCI_BASE_ADDRESS_0 + iRegion * 4);
716}
717
718#define INVALID_PCI_ADDRESS ~0U
719
720static int ich9pciUnmapRegion(PPCIDEVICE pDev, int iRegion)
721{
722 PCIIORegion* pRegion = &pDev->Int.s.aIORegions[iRegion];
723 int rc = VINF_SUCCESS;
724 PPCIBUS pBus = pDev->Int.s.CTX_SUFF(pBus);
725
726 Assert (pRegion->size != 0);
727
728 if (pRegion->addr != INVALID_PCI_ADDRESS)
729 {
730 if (pRegion->type & PCI_ADDRESS_SPACE_IO)
731 {
732 /* Port IO */
733 rc = PDMDevHlpIOPortDeregister(pDev->pDevIns, pRegion->addr, pRegion->size);
734 AssertRC(rc);
735 }
736 else
737 {
738 RTGCPHYS GCPhysBase = pRegion->addr;
739 if (pBus->pPciHlpR3->pfnIsMMIO2Base(pBus->pDevInsR3, pDev->pDevIns, GCPhysBase))
740 {
741 /* unmap it. */
742 rc = pRegion->map_func(pDev, iRegion, NIL_RTGCPHYS, pRegion->size, (PCIADDRESSSPACE)(pRegion->type));
743 AssertRC(rc);
744 rc = PDMDevHlpMMIO2Unmap(pDev->pDevIns, iRegion, GCPhysBase);
745 }
746 else
747 rc = PDMDevHlpMMIODeregister(pDev->pDevIns, GCPhysBase, pRegion->size);
748 }
749
750 pRegion->addr = INVALID_PCI_ADDRESS;
751 }
752
753 return rc;
754}
755
756static void ich9pciUpdateMappings(PCIDevice* pDev)
757{
758 PPCIBUS pBus = pDev->Int.s.CTX_SUFF(pBus);
759 uint32_t uLast, uNew;
760
761 int iCmd = PCIDevGetCommand(pDev);
762 for (int iRegion = 0; iRegion < PCI_NUM_REGIONS; iRegion++)
763 {
764 PCIIORegion* pRegion = &pDev->Int.s.aIORegions[iRegion];
765 uint32_t uConfigReg = ich9pciGetRegionReg(iRegion);
766 int32_t iRegionSize = pRegion->size;
767 int rc;
768
769 if (iRegionSize == 0)
770 continue;
771
772 AssertMsg((pRegion->type & PCI_ADDRESS_SPACE_BAR64) == 0, ("64-bit BARs not yet implemented\n"));
773
774 if (pRegion->type & PCI_ADDRESS_SPACE_IO)
775 {
776 /* port IO region */
777 if (iCmd & PCI_COMMAND_IOACCESS)
778 {
779 /* IO access allowed */
780 uNew = ich9pciConfigReadDev(pDev, uConfigReg, 4);
781 uNew &= ~(iRegionSize - 1);
782 uLast = uNew + iRegionSize - 1;
783 /* only 64K ioports on PC */
784 if (uLast <= uNew || uNew == 0 || uLast >= 0x10000)
785 uNew = INVALID_PCI_ADDRESS;
786 } else
787 uNew = INVALID_PCI_ADDRESS;
788 }
789 else
790 {
791 /* MMIO region */
792 if (iCmd & PCI_COMMAND_MEMACCESS)
793 {
794 uNew = ich9pciConfigReadDev(pDev, uConfigReg, 4);
795 /* the ROM slot has a specific enable bit */
796 if (iRegion == PCI_ROM_SLOT && !(uNew & 1))
797 uNew = INVALID_PCI_ADDRESS;
798 else
799 {
800 uNew &= ~(iRegionSize - 1);
801 uLast = uNew + iRegionSize - 1;
802 /* NOTE: we do not support wrapping */
803 /* XXX: as we cannot support really dynamic
804 mappings, we handle specific values as invalid
805 mappings. */
806 if (uLast <= uNew || uNew == 0 || uLast == INVALID_PCI_ADDRESS)
807 uNew = INVALID_PCI_ADDRESS;
808 }
809 } else
810 uNew = INVALID_PCI_ADDRESS;
811 }
812 /* now do the real mapping */
813 if (uNew != pRegion->addr)
814 {
815 if (pRegion->addr != INVALID_PCI_ADDRESS)
816 ich9pciUnmapRegion(pDev, iRegion);
817
818 pRegion->addr = uNew;
819 if (pRegion->addr != INVALID_PCI_ADDRESS)
820 {
821 /* finally, map the region */
822 rc = pRegion->map_func(pDev, iRegion,
823 pRegion->addr, pRegion->size,
824 (PCIADDRESSSPACE)(pRegion->type));
825 AssertRC(rc);
826 }
827 }
828 }
829}
830
831static DECLCALLBACK(int) ich9pciRegister(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, const char *pszName, int iDev)
832{
833 PPCIBUS pBus = DEVINS_2_PCIBUS(pDevIns);
834
835 /*
836 * Check input.
837 */
838 if ( !pszName
839 || !pPciDev
840 || iDev >= (int)RT_ELEMENTS(pBus->apDevices)
841 )
842 {
843 AssertMsgFailed(("Invalid argument! pszName=%s pPciDev=%p iDev=%d\n", pszName, pPciDev, iDev));
844 return VERR_INVALID_PARAMETER;
845 }
846
847 /*
848 * Register the device.
849 */
850 return ich9pciRegisterInternal(pBus, iDev, pPciDev, pszName);
851}
852
853
854static DECLCALLBACK(int) ich9pciRegisterMsi(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PPDMMSIREG pMsiReg)
855{
856 int rc;
857
858 rc = MsiInit(pPciDev, pMsiReg);
859 if (rc != VINF_SUCCESS)
860 return rc;
861
862 rc = MsixInit(pPciDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pPciHlp), pPciDev, pMsiReg);
863 if (rc != VINF_SUCCESS)
864 return rc;
865
866 return rc;
867}
868
869
870static DECLCALLBACK(int) ich9pcibridgeRegister(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, const char *pszName, int iDev)
871{
872
873 PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
874
875 /*
876 * Check input.
877 */
878 if ( !pszName
879 || !pPciDev
880 || iDev >= (int)RT_ELEMENTS(pBus->apDevices))
881 {
882 AssertMsgFailed(("Invalid argument! pszName=%s pPciDev=%p iDev=%d\n", pszName, pPciDev, iDev));
883 return VERR_INVALID_PARAMETER;
884 }
885
886 /*
887 * Register the device.
888 */
889 return ich9pciRegisterInternal(pBus, iDev, pPciDev, pszName);
890}
891
892static DECLCALLBACK(int) ich9pciIORegionRegister(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iRegion, uint32_t cbRegion, PCIADDRESSSPACE enmType, PFNPCIIOREGIONMAP pfnCallback)
893{
894 /*
895 * Validate.
896 */
897 AssertMsgReturn( enmType == PCI_ADDRESS_SPACE_MEM
898 || enmType == PCI_ADDRESS_SPACE_IO
899 || enmType == PCI_ADDRESS_SPACE_MEM_PREFETCH,
900 ("Invalid enmType=%#x? Or was this a bitmask after all...\n", enmType),
901 VERR_INVALID_PARAMETER);
902 AssertMsgReturn((unsigned)iRegion < PCI_NUM_REGIONS,
903 ("Invalid iRegion=%d PCI_NUM_REGIONS=%d\n", iRegion, PCI_NUM_REGIONS),
904 VERR_INVALID_PARAMETER);
905 int iLastSet = ASMBitLastSetU32(cbRegion);
906 AssertMsgReturn( iLastSet != 0
907 && RT_BIT_32(iLastSet - 1) == cbRegion,
908 ("Invalid cbRegion=%#x iLastSet=%#x (not a power of 2 or 0)\n", cbRegion, iLastSet),
909 VERR_INVALID_PARAMETER);
910
911 /*
912 * Register the I/O region.
913 */
914 PPCIIOREGION pRegion = &pPciDev->Int.s.aIORegions[iRegion];
915 pRegion->addr = INVALID_PCI_ADDRESS;
916 pRegion->size = cbRegion;
917 pRegion->type = enmType;
918 pRegion->map_func = pfnCallback;
919
920 /* Set type in the config space. */
921 uint32_t u32Address = ich9pciGetRegionReg(iRegion);
922 uint32_t u32Value = (enmType == PCI_ADDRESS_SPACE_MEM_PREFETCH ? (1 << 3) : 0)
923 | (enmType == PCI_ADDRESS_SPACE_IO ? 1 : 0);
924 PCIDevSetDWord(pPciDev, u32Address, u32Value);
925
926 return VINF_SUCCESS;
927}
928
929static DECLCALLBACK(void) ich9pciSetConfigCallbacks(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PFNPCICONFIGREAD pfnRead, PPFNPCICONFIGREAD ppfnReadOld,
930 PFNPCICONFIGWRITE pfnWrite, PPFNPCICONFIGWRITE ppfnWriteOld)
931{
932 if (ppfnReadOld)
933 *ppfnReadOld = pPciDev->Int.s.pfnConfigRead;
934 pPciDev->Int.s.pfnConfigRead = pfnRead;
935
936 if (ppfnWriteOld)
937 *ppfnWriteOld = pPciDev->Int.s.pfnConfigWrite;
938 pPciDev->Int.s.pfnConfigWrite = pfnWrite;
939}
940
941/**
942 * Saves a state of the PCI device.
943 *
944 * @returns VBox status code.
945 * @param pDevIns Device instance of the PCI Bus.
946 * @param pPciDev Pointer to PCI device.
947 * @param pSSM The handle to save the state to.
948 */
949static DECLCALLBACK(int) ich9pciGenericSaveExec(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PSSMHANDLE pSSM)
950{
951 Assert(!pciDevIsPassthrough(pPciDev));
952 return SSMR3PutMem(pSSM, &pPciDev->config[0], sizeof(pPciDev->config));
953}
954
955static int ich9pciR3CommonSaveExec(PPCIBUS pBus, PSSMHANDLE pSSM)
956{
957 /*
958 * Iterate thru all the devices.
959 */
960 for (uint32_t i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
961 {
962 PPCIDEVICE pDev = pBus->apDevices[i];
963 if (pDev)
964 {
965 /* Device position */
966 SSMR3PutU32(pSSM, i);
967 /* PCI config registers */
968 SSMR3PutMem(pSSM, pDev->config, sizeof(pDev->config));
969
970 /* Device flags */
971 int rc = SSMR3PutU32(pSSM, pDev->Int.s.fFlags);
972 if (RT_FAILURE(rc))
973 return rc;
974
975 /* IRQ pin state */
976 rc = SSMR3PutS32(pSSM, pDev->Int.s.uIrqPinState);
977 if (RT_FAILURE(rc))
978 return rc;
979
980 /* MSI info */
981 rc = SSMR3PutU8(pSSM, pDev->Int.s.u8MsiCapOffset);
982 if (RT_FAILURE(rc))
983 return rc;
984 rc = SSMR3PutU8(pSSM, pDev->Int.s.u8MsiCapSize);
985 if (RT_FAILURE(rc))
986 return rc;
987
988 /* MSI-X info */
989 rc = SSMR3PutU8(pSSM, pDev->Int.s.u8MsixCapOffset);
990 if (RT_FAILURE(rc))
991 return rc;
992 rc = SSMR3PutU8(pSSM, pDev->Int.s.u8MsixCapSize);
993 if (RT_FAILURE(rc))
994 return rc;
995 /* Save MSI-X page state */
996 if (pDev->Int.s.u8MsixCapOffset != 0)
997 {
998 Assert(pDev->Int.s.pMsixPageR3 != NULL);
999 SSMR3PutMem(pSSM, pDev->Int.s.pMsixPageR3, 0x1000);
1000 if (RT_FAILURE(rc))
1001 return rc;
1002 }
1003 }
1004 }
1005 return SSMR3PutU32(pSSM, UINT32_MAX); /* terminator */
1006}
1007
1008static DECLCALLBACK(int) ich9pciR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
1009{
1010 PPCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
1011
1012 /*
1013 * Bus state data.
1014 */
1015 SSMR3PutU32(pSSM, pThis->uConfigReg);
1016
1017 /*
1018 * Save IRQ states.
1019 */
1020 for (int i = 0; i < PCI_APIC_IRQ_PINS; i++)
1021 SSMR3PutU32(pSSM, pThis->uaPciApicIrqLevels[i]);
1022
1023 SSMR3PutU32(pSSM, ~0); /* separator */
1024
1025 return ich9pciR3CommonSaveExec(&pThis->aPciBus, pSSM);
1026}
1027
1028
1029static DECLCALLBACK(int) ich9pcibridgeR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
1030{
1031 PPCIBUS pThis = PDMINS_2_DATA(pDevIns, PPCIBUS);
1032 return ich9pciR3CommonSaveExec(pThis, pSSM);
1033}
1034
1035
1036static void ich9pcibridgeConfigWrite(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice, uint32_t u32Address, uint32_t u32Value, unsigned cb)
1037{
1038 PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
1039
1040 LogFlowFunc((": pDevIns=%p iBus=%d iDevice=%d u32Address=%u u32Value=%u cb=%d\n", pDevIns, iBus, iDevice, u32Address, u32Value, cb));
1041
1042 /* If the current bus is not the target bus search for the bus which contains the device. */
1043 if (iBus != PCIDevGetByte(&pBus->aPciDev, VBOX_PCI_SECONDARY_BUS))
1044 {
1045 PPCIDEVICE pBridgeDevice = ich9pciFindBridge(pBus, iBus);
1046 if (pBridgeDevice)
1047 {
1048 AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigWrite);
1049 pBridgeDevice->Int.s.pfnBridgeConfigWrite(pBridgeDevice->pDevIns, iBus, iDevice, u32Address, u32Value, cb);
1050 }
1051 }
1052 else
1053 {
1054 /* This is the target bus, pass the write to the device. */
1055 PPCIDEVICE pPciDev = pBus->apDevices[iDevice];
1056 if (pPciDev)
1057 {
1058 Log(("%s: %s: addr=%02x val=%08x len=%d\n", __FUNCTION__, pPciDev->name, u32Address, u32Value, cb));
1059 pPciDev->Int.s.pfnConfigWrite(pPciDev, u32Address, u32Value, cb);
1060 }
1061 }
1062}
1063
1064static uint32_t ich9pcibridgeConfigRead(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice, uint32_t u32Address, unsigned cb)
1065{
1066 PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
1067 uint32_t u32Value;
1068
1069 LogFlowFunc((": pDevIns=%p iBus=%d iDevice=%d u32Address=%u cb=%d\n", pDevIns, iBus, iDevice, u32Address, cb));
1070
1071 /* If the current bus is not the target bus search for the bus which contains the device. */
1072 if (iBus != PCIDevGetByte(&pBus->aPciDev, VBOX_PCI_SECONDARY_BUS))
1073 {
1074 PPCIDEVICE pBridgeDevice = ich9pciFindBridge(pBus, iBus);
1075 if (pBridgeDevice)
1076 {
1077 AssertPtr( pBridgeDevice->Int.s.pfnBridgeConfigRead);
1078 u32Value = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->pDevIns, iBus, iDevice, u32Address, cb);
1079 }
1080 else
1081 ich9pciNoMem(&u32Value, 4);
1082 }
1083 else
1084 {
1085 /* This is the target bus, pass the read to the device. */
1086 PPCIDEVICE pPciDev = pBus->apDevices[iDevice];
1087 if (pPciDev)
1088 {
1089 u32Value = pPciDev->Int.s.pfnConfigRead(pPciDev, u32Address, cb);
1090 Log(("%s: %s: u32Address=%02x u32Value=%08x cb=%d\n", __FUNCTION__, pPciDev->name, u32Address, u32Value, cb));
1091 }
1092 else
1093 ich9pciNoMem(&u32Value, 4);
1094 }
1095
1096 return u32Value;
1097}
1098
1099
1100/**
1101 * Common routine for restoring the config registers of a PCI device.
1102 *
1103 * @param pDev The PCI device.
1104 * @param pbSrcConfig The configuration register values to be loaded.
1105 * @param fIsBridge Whether this is a bridge device or not.
1106 */
1107static void pciR3CommonRestoreConfig(PPCIDEVICE pDev, uint8_t const *pbSrcConfig, bool fIsBridge)
1108{
1109 /*
1110 * This table defines the fields for normal devices and bridge devices, and
1111 * the order in which they need to be restored.
1112 */
1113 static const struct PciField
1114 {
1115 uint8_t off;
1116 uint8_t cb;
1117 uint8_t fWritable;
1118 uint8_t fBridge;
1119 const char *pszName;
1120 } s_aFields[] =
1121 {
1122 /* off,cb,fW,fB, pszName */
1123 { VBOX_PCI_VENDOR_ID, 2, 0, 3, "VENDOR_ID" },
1124 { VBOX_PCI_DEVICE_ID, 2, 0, 3, "DEVICE_ID" },
1125 { VBOX_PCI_STATUS, 2, 1, 3, "STATUS" },
1126 { VBOX_PCI_REVISION_ID, 1, 0, 3, "REVISION_ID" },
1127 { VBOX_PCI_CLASS_PROG, 1, 0, 3, "CLASS_PROG" },
1128 { VBOX_PCI_CLASS_SUB, 1, 0, 3, "CLASS_SUB" },
1129 { VBOX_PCI_CLASS_BASE, 1, 0, 3, "CLASS_BASE" },
1130 { VBOX_PCI_CACHE_LINE_SIZE, 1, 1, 3, "CACHE_LINE_SIZE" },
1131 { VBOX_PCI_LATENCY_TIMER, 1, 1, 3, "LATENCY_TIMER" },
1132 { VBOX_PCI_HEADER_TYPE, 1, 0, 3, "HEADER_TYPE" },
1133 { VBOX_PCI_BIST, 1, 1, 3, "BIST" },
1134 { VBOX_PCI_BASE_ADDRESS_0, 4, 1, 3, "BASE_ADDRESS_0" },
1135 { VBOX_PCI_BASE_ADDRESS_1, 4, 1, 3, "BASE_ADDRESS_1" },
1136 { VBOX_PCI_BASE_ADDRESS_2, 4, 1, 1, "BASE_ADDRESS_2" },
1137 { VBOX_PCI_PRIMARY_BUS, 1, 1, 2, "PRIMARY_BUS" }, // fWritable = ??
1138 { VBOX_PCI_SECONDARY_BUS, 1, 1, 2, "SECONDARY_BUS" }, // fWritable = ??
1139 { VBOX_PCI_SUBORDINATE_BUS, 1, 1, 2, "SUBORDINATE_BUS" }, // fWritable = ??
1140 { VBOX_PCI_SEC_LATENCY_TIMER, 1, 1, 2, "SEC_LATENCY_TIMER" }, // fWritable = ??
1141 { VBOX_PCI_BASE_ADDRESS_3, 4, 1, 1, "BASE_ADDRESS_3" },
1142 { VBOX_PCI_IO_BASE, 1, 1, 2, "IO_BASE" }, // fWritable = ??
1143 { VBOX_PCI_IO_LIMIT, 1, 1, 2, "IO_LIMIT" }, // fWritable = ??
1144 { VBOX_PCI_SEC_STATUS, 2, 1, 2, "SEC_STATUS" }, // fWritable = ??
1145 { VBOX_PCI_BASE_ADDRESS_4, 4, 1, 1, "BASE_ADDRESS_4" },
1146 { VBOX_PCI_MEMORY_BASE, 2, 1, 2, "MEMORY_BASE" }, // fWritable = ??
1147 { VBOX_PCI_MEMORY_LIMIT, 2, 1, 2, "MEMORY_LIMIT" }, // fWritable = ??
1148 { VBOX_PCI_BASE_ADDRESS_5, 4, 1, 1, "BASE_ADDRESS_5" },
1149 { VBOX_PCI_PREF_MEMORY_BASE, 2, 1, 2, "PREF_MEMORY_BASE" }, // fWritable = ??
1150 { VBOX_PCI_PREF_MEMORY_LIMIT, 2, 1, 2, "PREF_MEMORY_LIMIT" }, // fWritable = ??
1151 { VBOX_PCI_CARDBUS_CIS, 4, 1, 1, "CARDBUS_CIS" }, // fWritable = ??
1152 { VBOX_PCI_PREF_BASE_UPPER32, 4, 1, 2, "PREF_BASE_UPPER32" }, // fWritable = ??
1153 { VBOX_PCI_SUBSYSTEM_VENDOR_ID, 2, 0, 1, "SUBSYSTEM_VENDOR_ID" },// fWritable = !?
1154 { VBOX_PCI_PREF_LIMIT_UPPER32, 4, 1, 2, "PREF_LIMIT_UPPER32" },// fWritable = ??
1155 { VBOX_PCI_SUBSYSTEM_ID, 2, 0, 1, "SUBSYSTEM_ID" }, // fWritable = !?
1156 { VBOX_PCI_ROM_ADDRESS, 4, 1, 1, "ROM_ADDRESS" }, // fWritable = ?!
1157 { VBOX_PCI_IO_BASE_UPPER16, 2, 1, 2, "IO_BASE_UPPER16" }, // fWritable = ?!
1158 { VBOX_PCI_IO_LIMIT_UPPER16, 2, 1, 2, "IO_LIMIT_UPPER16" }, // fWritable = ?!
1159 { VBOX_PCI_CAPABILITY_LIST, 4, 0, 3, "CAPABILITY_LIST" }, // fWritable = !? cb=!?
1160 { VBOX_PCI_RESERVED_38, 4, 1, 1, "RESERVED_38" }, // ???
1161 { VBOX_PCI_ROM_ADDRESS_BR, 4, 1, 2, "ROM_ADDRESS_BR" }, // fWritable = !? cb=!? fBridge=!?
1162 { VBOX_PCI_INTERRUPT_LINE, 1, 1, 3, "INTERRUPT_LINE" }, // fBridge=??
1163 { VBOX_PCI_INTERRUPT_PIN, 1, 0, 3, "INTERRUPT_PIN" }, // fBridge=??
1164 { VBOX_PCI_MIN_GNT, 1, 0, 1, "MIN_GNT" },
1165 { VBOX_PCI_BRIDGE_CONTROL, 2, 1, 2, "BRIDGE_CONTROL" }, // fWritable = !?
1166 { VBOX_PCI_MAX_LAT, 1, 0, 1, "MAX_LAT" },
1167 /* The COMMAND register must come last as it requires the *ADDRESS*
1168 registers to be restored before we pretent to change it from 0 to
1169 whatever value the guest assigned it. */
1170 { VBOX_PCI_COMMAND, 2, 1, 3, "COMMAND" },
1171 };
1172
1173#ifdef RT_STRICT
1174 /* Check that we've got full register coverage. */
1175 uint32_t bmDevice[0x40 / 32];
1176 uint32_t bmBridge[0x40 / 32];
1177 RT_ZERO(bmDevice);
1178 RT_ZERO(bmBridge);
1179 for (uint32_t i = 0; i < RT_ELEMENTS(s_aFields); i++)
1180 {
1181 uint8_t off = s_aFields[i].off;
1182 uint8_t cb = s_aFields[i].cb;
1183 uint8_t f = s_aFields[i].fBridge;
1184 while (cb-- > 0)
1185 {
1186 if (f & 1) AssertMsg(!ASMBitTest(bmDevice, off), ("%#x\n", off));
1187 if (f & 2) AssertMsg(!ASMBitTest(bmBridge, off), ("%#x\n", off));
1188 if (f & 1) ASMBitSet(bmDevice, off);
1189 if (f & 2) ASMBitSet(bmBridge, off);
1190 off++;
1191 }
1192 }
1193 for (uint32_t off = 0; off < 0x40; off++)
1194 {
1195 AssertMsg(ASMBitTest(bmDevice, off), ("%#x\n", off));
1196 AssertMsg(ASMBitTest(bmBridge, off), ("%#x\n", off));
1197 }
1198#endif
1199
1200 /*
1201 * Loop thru the fields covering the 64 bytes of standard registers.
1202 */
1203 uint8_t const fBridge = fIsBridge ? 2 : 1;
1204 Assert(!pciDevIsPassthrough(pDev));
1205 uint8_t *pbDstConfig = &pDev->config[0];
1206
1207 for (uint32_t i = 0; i < RT_ELEMENTS(s_aFields); i++)
1208 if (s_aFields[i].fBridge & fBridge)
1209 {
1210 uint8_t const off = s_aFields[i].off;
1211 uint8_t const cb = s_aFields[i].cb;
1212 uint32_t u32Src;
1213 uint32_t u32Dst;
1214 switch (cb)
1215 {
1216 case 1:
1217 u32Src = pbSrcConfig[off];
1218 u32Dst = pbDstConfig[off];
1219 break;
1220 case 2:
1221 u32Src = *(uint16_t const *)&pbSrcConfig[off];
1222 u32Dst = *(uint16_t const *)&pbDstConfig[off];
1223 break;
1224 case 4:
1225 u32Src = *(uint32_t const *)&pbSrcConfig[off];
1226 u32Dst = *(uint32_t const *)&pbDstConfig[off];
1227 break;
1228 default:
1229 AssertFailed();
1230 continue;
1231 }
1232
1233 if ( u32Src != u32Dst
1234 || off == VBOX_PCI_COMMAND)
1235 {
1236 if (u32Src != u32Dst)
1237 {
1238 if (!s_aFields[i].fWritable)
1239 LogRel(("PCI: %8s/%u: %2u-bit field %s: %x -> %x - !READ ONLY!\n",
1240 pDev->name, pDev->pDevIns->iInstance, cb*8, s_aFields[i].pszName, u32Dst, u32Src));
1241 else
1242 LogRel(("PCI: %8s/%u: %2u-bit field %s: %x -> %x\n",
1243 pDev->name, pDev->pDevIns->iInstance, cb*8, s_aFields[i].pszName, u32Dst, u32Src));
1244 }
1245 if (off == VBOX_PCI_COMMAND)
1246 PCIDevSetCommand(pDev, 0); /* For remapping, see ich9pciR3CommonLoadExec. */
1247 pDev->Int.s.pfnConfigWrite(pDev, off, u32Src, cb);
1248 }
1249 }
1250
1251 /*
1252 * The device dependent registers.
1253 *
1254 * We will not use ConfigWrite here as we have no clue about the size
1255 * of the registers, so the device is responsible for correctly
1256 * restoring functionality governed by these registers.
1257 */
1258 for (uint32_t off = 0x40; off < sizeof(pDev->config); off++)
1259 if (pbDstConfig[off] != pbSrcConfig[off])
1260 {
1261 LogRel(("PCI: %8s/%u: register %02x: %02x -> %02x\n",
1262 pDev->name, pDev->pDevIns->iInstance, off, pbDstConfig[off], pbSrcConfig[off])); /** @todo make this Log() later. */
1263 pbDstConfig[off] = pbSrcConfig[off];
1264 }
1265}
1266
1267/**
1268 * Common worker for ich9pciR3LoadExec and ich9pcibridgeR3LoadExec.
1269 *
1270 * @returns VBox status code.
1271 * @param pBus The bus which data is being loaded.
1272 * @param pSSM The saved state handle.
1273 * @param uVersion The data version.
1274 * @param uPass The pass.
1275 */
1276static DECLCALLBACK(int) ich9pciR3CommonLoadExec(PPCIBUS pBus, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1277{
1278 uint32_t u32;
1279 uint32_t i;
1280 int rc;
1281
1282 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
1283
1284 /*
1285 * Iterate thru all the devices and write 0 to the COMMAND register so
1286 * that all the memory is unmapped before we start restoring the saved
1287 * mapping locations.
1288 *
1289 * The register value is restored afterwards so we can do proper
1290 * LogRels in pciR3CommonRestoreConfig.
1291 */
1292 for (i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
1293 {
1294 PPCIDEVICE pDev = pBus->apDevices[i];
1295 if (pDev)
1296 {
1297 uint16_t u16 = PCIDevGetCommand(pDev);
1298 pDev->Int.s.pfnConfigWrite(pDev, VBOX_PCI_COMMAND, 0, 2);
1299 PCIDevSetCommand(pDev, u16);
1300 Assert(PCIDevGetCommand(pDev) == u16);
1301 }
1302 }
1303
1304 void* pvMsixPage = RTMemTmpAllocZ(0x1000);
1305 /*
1306 * Iterate all the devices.
1307 */
1308 for (i = 0;; i++)
1309 {
1310 PPCIDEVICE pDev;
1311 PCIDEVICE DevTmp;
1312
1313 /* index / terminator */
1314 rc = SSMR3GetU32(pSSM, &u32);
1315 if (RT_FAILURE(rc))
1316 return rc;
1317 if (u32 == (uint32_t)~0)
1318 break;
1319 if ( u32 >= RT_ELEMENTS(pBus->apDevices)
1320 || u32 < i)
1321 {
1322 AssertMsgFailed(("u32=%#x i=%#x\n", u32, i));
1323 goto out;
1324 }
1325
1326 /* skip forward to the device checking that no new devices are present. */
1327 for (; i < u32; i++)
1328 {
1329 pDev = pBus->apDevices[i];
1330 if (pDev)
1331 {
1332 LogRel(("New device in slot %#x, %s (vendor=%#06x device=%#06x)\n", i, pDev->name,
1333 PCIDevGetVendorId(pDev), PCIDevGetDeviceId(pDev)));
1334 if (SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT)
1335 return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("New device in slot %#x, %s (vendor=%#06x device=%#06x)"),
1336 i, pDev->name, PCIDevGetVendorId(pDev), PCIDevGetDeviceId(pDev));
1337 }
1338 }
1339
1340 /* get the data */
1341 DevTmp.Int.s.fFlags = 0;
1342 DevTmp.Int.s.u8MsiCapOffset = 0;
1343 DevTmp.Int.s.u8MsiCapSize = 0;
1344 DevTmp.Int.s.u8MsixCapOffset = 0;
1345 DevTmp.Int.s.u8MsixCapSize = 0;
1346 DevTmp.Int.s.uIrqPinState = ~0; /* Invalid value in case we have an older saved state to force a state change in pciSetIrq. */
1347 SSMR3GetMem(pSSM, DevTmp.config, sizeof(DevTmp.config));
1348
1349 rc = SSMR3GetU32(pSSM, &DevTmp.Int.s.fFlags);
1350 if (RT_FAILURE(rc))
1351 goto out;
1352
1353 rc = SSMR3GetS32(pSSM, &DevTmp.Int.s.uIrqPinState);
1354 if (RT_FAILURE(rc))
1355 goto out;
1356
1357 rc = SSMR3GetU8(pSSM, &DevTmp.Int.s.u8MsiCapOffset);
1358 if (RT_FAILURE(rc))
1359 goto out;
1360
1361 rc = SSMR3GetU8(pSSM, &DevTmp.Int.s.u8MsiCapSize);
1362 if (RT_FAILURE(rc))
1363 goto out;
1364
1365 rc = SSMR3GetU8(pSSM, &DevTmp.Int.s.u8MsixCapOffset);
1366 if (RT_FAILURE(rc))
1367 goto out;
1368
1369 rc = SSMR3GetU8(pSSM, &DevTmp.Int.s.u8MsixCapSize);
1370 if (RT_FAILURE(rc))
1371 goto out;
1372
1373 /* Load MSI-X page state */
1374 if (DevTmp.Int.s.u8MsixCapOffset != 0)
1375 {
1376 Assert(pvMsixPage != NULL);
1377 SSMR3GetMem(pSSM, pvMsixPage, 0x1000);
1378 if (RT_FAILURE(rc))
1379 goto out;
1380 }
1381
1382 /* check that it's still around. */
1383 pDev = pBus->apDevices[i];
1384 if (!pDev)
1385 {
1386 LogRel(("Device in slot %#x has been removed! vendor=%#06x device=%#06x\n", i,
1387 PCIDevGetVendorId(&DevTmp), PCIDevGetDeviceId(&DevTmp)));
1388 if (SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT)
1389 return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Device in slot %#x has been removed! vendor=%#06x device=%#06x"),
1390 i, PCIDevGetVendorId(&DevTmp), PCIDevGetDeviceId(&DevTmp));
1391 continue;
1392 }
1393
1394 /* match the vendor id assuming that this will never be changed. */
1395 if ( PCIDevGetVendorId(&DevTmp) != PCIDevGetVendorId(pDev))
1396 return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Device in slot %#x (%s) vendor id mismatch! saved=%.4Rhxs current=%.4Rhxs"),
1397 i, pDev->name, PCIDevGetVendorId(&DevTmp), PCIDevGetVendorId(pDev));
1398
1399 /* commit the loaded device config. */
1400 Assert(!pciDevIsPassthrough(pDev));
1401 pciR3CommonRestoreConfig(pDev, &DevTmp.config[0], false ); /** @todo fix bridge fun! */
1402
1403 pDev->Int.s.uIrqPinState = DevTmp.Int.s.uIrqPinState;
1404 pDev->Int.s.u8MsiCapOffset = DevTmp.Int.s.u8MsiCapOffset;
1405 pDev->Int.s.u8MsiCapSize = DevTmp.Int.s.u8MsiCapSize;
1406 pDev->Int.s.u8MsixCapOffset = DevTmp.Int.s.u8MsixCapOffset;
1407 pDev->Int.s.u8MsixCapSize = DevTmp.Int.s.u8MsixCapSize;
1408 if (DevTmp.Int.s.u8MsixCapSize != 0)
1409 {
1410 Assert(pDev->Int.s.pMsixPageR3 != NULL);
1411 memcpy(pDev->Int.s.pMsixPageR3, pvMsixPage, 0x1000);
1412 }
1413 }
1414
1415 out:
1416 if (pvMsixPage)
1417 RTMemTmpFree(pvMsixPage);
1418
1419 return rc;
1420}
1421
1422/**
1423 * Loads a saved PCI device state.
1424 *
1425 * @returns VBox status code.
1426 * @param pDevIns Device instance of the PCI Bus.
1427 * @param pPciDev Pointer to PCI device.
1428 * @param pSSM The handle to the saved state.
1429 */
1430static DECLCALLBACK(int) ich9pciGenericLoadExec(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PSSMHANDLE pSSM)
1431{
1432 Assert(!pciDevIsPassthrough(pPciDev));
1433 return SSMR3GetMem(pSSM, &pPciDev->config[0], sizeof(pPciDev->config));
1434}
1435
1436static DECLCALLBACK(int) ich9pciR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1437{
1438 PPCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
1439 PPCIBUS pBus = &pThis->aPciBus;
1440 uint32_t u32;
1441 int rc;
1442
1443 /* We ignore this version as there's no saved state with it anyway */
1444 if (uVersion == VBOX_ICH9PCI_SAVED_STATE_VERSION_NOMSI)
1445 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1446 if (uVersion > VBOX_ICH9PCI_SAVED_STATE_VERSION_MSI)
1447 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1448
1449 /*
1450 * Bus state data.
1451 */
1452 SSMR3GetU32(pSSM, &pThis->uConfigReg);
1453
1454 /*
1455 * Load IRQ states.
1456 */
1457 for (int i = 0; i < PCI_APIC_IRQ_PINS; i++)
1458 SSMR3GetU32(pSSM, (uint32_t*)&pThis->uaPciApicIrqLevels[i]);
1459
1460 /* separator */
1461 rc = SSMR3GetU32(pSSM, &u32);
1462 if (RT_FAILURE(rc))
1463 return rc;
1464 if (u32 != (uint32_t)~0)
1465 AssertMsgFailedReturn(("u32=%#x\n", u32), rc);
1466
1467 return ich9pciR3CommonLoadExec(pBus, pSSM, uVersion, uPass);
1468}
1469
1470static DECLCALLBACK(int) ich9pcibridgeR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1471{
1472 PPCIBUS pThis = PDMINS_2_DATA(pDevIns, PPCIBUS);
1473 if (uVersion > VBOX_ICH9PCI_SAVED_STATE_VERSION_MSI)
1474 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1475 return ich9pciR3CommonLoadExec(pThis, pSSM, uVersion, uPass);
1476}
1477
1478static uint32_t ich9pciConfigRead(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t len)
1479{
1480 /* Will only work in LSB case */
1481 uint32_t u32Val;
1482 PciAddress aPciAddr;
1483
1484 aPciAddr.iBus = uBus;
1485 aPciAddr.iDeviceFunc = uDevFn;
1486 aPciAddr.iRegister = addr;
1487
1488 /* cannot be rescheduled, as already in R3 */
1489 int rc = ich9pciDataReadAddr(pGlobals, &aPciAddr, len, &u32Val, VERR_INTERNAL_ERROR);
1490 AssertRC(rc);
1491 return u32Val;
1492}
1493
1494static void ich9pciConfigWrite(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t val, uint32_t len)
1495{
1496 PciAddress aPciAddr;
1497
1498 aPciAddr.iBus = uBus;
1499 aPciAddr.iDeviceFunc = uDevFn;
1500 aPciAddr.iRegister = addr;
1501
1502 /* cannot be rescheduled, as already in R3 */
1503 int rc = ich9pciDataWriteAddr(pGlobals, &aPciAddr, val, len, VERR_INTERNAL_ERROR);
1504 AssertRC(rc);
1505}
1506
1507static void ich9pciSetRegionAddress(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, int iRegion, uint32_t addr)
1508{
1509 uint32_t uReg = ich9pciGetRegionReg(iRegion);
1510
1511 /* Read memory type first. */
1512 uint8_t uResourceType = ich9pciConfigRead(pGlobals, uBus, uDevFn, uReg, 1);
1513 /* Read command register. */
1514 uint16_t uCmd = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_COMMAND, 2);
1515
1516 if ( iRegion == PCI_ROM_SLOT )
1517 uCmd |= PCI_COMMAND_MEMACCESS;
1518 else if ((uResourceType & PCI_ADDRESS_SPACE_IO) == PCI_ADDRESS_SPACE_IO)
1519 uCmd |= PCI_COMMAND_IOACCESS; /* Enable I/O space access. */
1520 else /* The region is MMIO. */
1521 uCmd |= PCI_COMMAND_MEMACCESS; /* Enable MMIO access. */
1522
1523 /* Write address of the device. */
1524 ich9pciConfigWrite(pGlobals, uBus, uDevFn, uReg, addr, 4);
1525
1526 /* enable memory mappings */
1527 ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_COMMAND, uCmd, 2);
1528}
1529
1530
1531static void ich9pciBiosInitBridge(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn)
1532{
1533 Log(("BIOS init device: %0x2::%02x.%d\n", uBus, uDevFn >> 3, uDevFn & 7));
1534
1535 /*
1536 * The I/O range for the bridge must be aligned to a 4KB boundary.
1537 * This does not change anything really as the access to the device is not going
1538 * through the bridge but we want to be compliant to the spec.
1539 */
1540 if ((pGlobals->uPciBiosIo % 4096) != 0)
1541 {
1542 pGlobals->uPciBiosIo = RT_ALIGN_32(pGlobals->uPciBiosIo, 4*1024);
1543 Log(("%s: Aligned I/O start address. New address %#x\n", __FUNCTION__, pGlobals->uPciBiosIo));
1544 }
1545 ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_IO_BASE, (pGlobals->uPciBiosIo >> 8) & 0xf0, 1);
1546
1547 /* The MMIO range for the bridge must be aligned to a 1MB boundary. */
1548 if ((pGlobals->uPciBiosMmio % (1024 * 1024)) != 0)
1549 {
1550 pGlobals->uPciBiosMmio = RT_ALIGN_32(pGlobals->uPciBiosMmio, 1024*1024);
1551 Log(("%s: Aligned MMIO start address. New address %#x\n", __FUNCTION__, pGlobals->uPciBiosMmio));
1552 }
1553 ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_MEMORY_BASE, (pGlobals->uPciBiosMmio >> 16) & UINT32_C(0xffff0), 2);
1554
1555 /* Save values to compare later to. */
1556 uint32_t u32IoAddressBase = pGlobals->uPciBiosIo;
1557 uint32_t u32MMIOAddressBase = pGlobals->uPciBiosMmio;
1558
1559 /* Init devices behind the bridge and possibly other bridges as well. */
1560 for (int iDev = 0; iDev <= 255; iDev++)
1561 ich9pciBiosInitDevice(pGlobals, uBus + 1, iDev);
1562
1563 /*
1564 * Set I/O limit register. If there is no device with I/O space behind the bridge
1565 * we set a lower value than in the base register.
1566 * The result with a real bridge is that no I/O transactions are passed to the secondary
1567 * interface. Again this doesn't really matter here but we want to be compliant to the spec.
1568 */
1569 if ((u32IoAddressBase != pGlobals->uPciBiosIo) && ((pGlobals->uPciBiosIo % 4096) != 0))
1570 {
1571 /* The upper boundary must be one byte less than a 4KB boundary. */
1572 pGlobals->uPciBiosIo = RT_ALIGN_32(pGlobals->uPciBiosIo, 4*1024);
1573 }
1574
1575 ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_IO_LIMIT, ((pGlobals->uPciBiosIo >> 8) & 0xf0) - 1, 1);
1576
1577 /* Same with the MMIO limit register but with 1MB boundary here. */
1578 if ((u32MMIOAddressBase != pGlobals->uPciBiosMmio) && ((pGlobals->uPciBiosMmio % (1024 * 1024)) != 0))
1579 {
1580 /* The upper boundary must be one byte less than a 1MB boundary. */
1581 pGlobals->uPciBiosMmio = RT_ALIGN_32(pGlobals->uPciBiosMmio, 1024*1024);
1582 }
1583 ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_MEMORY_LIMIT, ((pGlobals->uPciBiosMmio >> 16) & UINT32_C(0xfff0)) - 1, 2);
1584
1585 /*
1586 * Set the prefetch base and limit registers. We currently have no device with a prefetchable region
1587 * which may be behind a bridge. That's why it is unconditionally disabled here atm by writing a higher value into
1588 * the base register than in the limit register.
1589 */
1590 ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_MEMORY_BASE, 0xfff0, 2);
1591 ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_MEMORY_LIMIT, 0x0, 2);
1592 ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_BASE_UPPER32, 0x00, 4);
1593 ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_LIMIT_UPPER32, 0x00, 4);
1594}
1595
1596static void ich9pciBiosInitDevice(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn)
1597{
1598 uint32_t *paddr;
1599 uint16_t uDevClass, uVendor, uDevice;
1600 uint8_t uCmd;
1601
1602 uDevClass = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_CLASS_DEVICE, 2);
1603 uVendor = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_VENDOR_ID, 2);
1604 uDevice = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_DEVICE_ID, 2);
1605
1606 /* If device is present */
1607 if (uVendor == 0xffff)
1608 return;
1609
1610 switch (uDevClass)
1611 {
1612 case 0x0101:
1613 /* IDE controller */
1614 ich9pciConfigWrite(pGlobals, uBus, uDevFn, 0x40, 0x8000, 2); /* enable IDE0 */
1615 ich9pciConfigWrite(pGlobals, uBus, uDevFn, 0x42, 0x8000, 2); /* enable IDE1 */
1616 goto default_map;
1617 break;
1618 case 0x0300:
1619 /* VGA controller */
1620 if (uVendor != 0x80ee)
1621 goto default_map;
1622 /* VGA: map frame buffer to default Bochs VBE address */
1623 ich9pciSetRegionAddress(pGlobals, uBus, uDevFn, 0, 0xE0000000);
1624 /*
1625 * Legacy VGA I/O ports are implicitly decoded by a VGA class device. But
1626 * only the framebuffer (i.e., a memory region) is explicitly registered via
1627 * ich9pciSetRegionAddress, so I/O decoding must be enabled manually.
1628 */
1629 uCmd = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_COMMAND, 1);
1630 ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_COMMAND,
1631 /* Enable I/O space access. */
1632 uCmd | PCI_COMMAND_IOACCESS,
1633 1);
1634 break;
1635 case 0x0604:
1636 /* PCI-to-PCI bridge. */
1637 AssertMsg(pGlobals->uBus < 255, ("Too many bridges on the bus\n"));
1638 ich9pciBiosInitBridge(pGlobals, uBus, uDevFn);
1639 break;
1640 default:
1641 default_map:
1642 {
1643 /* default memory mappings */
1644 /*
1645 * We ignore ROM region here.
1646 */
1647 for (int iRegion = 0; iRegion < (PCI_NUM_REGIONS-1); iRegion++)
1648 {
1649 uint32_t u32Address = ich9pciGetRegionReg(iRegion);
1650
1651 /* Calculate size - we write all 1s into the BAR, and then evaluate which bits
1652 are cleared. . */
1653 uint8_t u8ResourceType = ich9pciConfigRead(pGlobals, uBus, uDevFn, u32Address, 1);
1654 ich9pciConfigWrite(pGlobals, uBus, uDevFn, u32Address, UINT32_C(0xffffffff), 4);
1655 uint32_t u32Size = ich9pciConfigRead(pGlobals, uBus, uDevFn, u32Address, 4);
1656 /* Clear resource information depending on resource type. */
1657 if ((u8ResourceType & PCI_COMMAND_IOACCESS) == PCI_COMMAND_IOACCESS) /* I/O */
1658 u32Size &= ~(0x01);
1659 else /* MMIO */
1660 u32Size &= ~(0x0f);
1661
1662 bool fIsPio = ((u8ResourceType & PCI_COMMAND_IOACCESS) == PCI_COMMAND_IOACCESS);
1663 /*
1664 * Invert all bits and add 1 to get size of the region.
1665 * (From PCI implementation note)
1666 */
1667 if (fIsPio && (u32Size & UINT32_C(0xffff0000)) == 0)
1668 u32Size = (~(u32Size | UINT32_C(0xffff0000))) + 1;
1669 else
1670 u32Size = (~u32Size) + 1;
1671
1672 Log(("%s: Size of region %u for device %d on bus %d is %u\n", __FUNCTION__, iRegion, uDevFn, uBus, u32Size));
1673
1674 if (u32Size)
1675 {
1676 paddr = fIsPio ? &pGlobals->uPciBiosIo : &pGlobals->uPciBiosMmio;
1677 *paddr = (*paddr + u32Size - 1) & ~(u32Size - 1);
1678 Log(("%s: Start address of %s region %u is %#x\n", __FUNCTION__, (fIsPio ? "I/O" : "MMIO"), iRegion, *paddr));
1679 ich9pciSetRegionAddress(pGlobals, uBus, uDevFn, iRegion, *paddr);
1680 *paddr += u32Size;
1681 Log(("%s: New address is %#x\n", __FUNCTION__, *paddr));
1682 }
1683 }
1684 break;
1685 }
1686 }
1687
1688 /* map the interrupt */
1689 uint32_t iPin = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_INTERRUPT_PIN, 1);
1690 if (iPin != 0)
1691 {
1692 iPin--;
1693
1694 if (uBus != 0)
1695 {
1696 /* Find bus this device attached to. */
1697 PPCIBUS pBus = &pGlobals->aPciBus;
1698 while (1)
1699 {
1700 PPCIDEVICE pBridge = ich9pciFindBridge(pBus, uBus);
1701 if (!pBridge)
1702 {
1703 Assert(false);
1704 break;
1705 }
1706 if (uBus == PCIDevGetByte(pBridge, VBOX_PCI_SECONDARY_BUS))
1707 {
1708 /* OK, found bus this device attached to. */
1709 break;
1710 }
1711 pBus = PDMINS_2_DATA(pBridge->pDevIns, PPCIBUS);
1712 }
1713
1714 /* We need to go up to the host bus to see which irq pin this
1715 * device will use there. See logic in ich9pcibridgeSetIrq().
1716 */
1717 while (pBus->iBus != 0)
1718 {
1719 /* Get the pin the device would assert on the bridge. */
1720 iPin = ((pBus->aPciDev.devfn >> 3) + iPin) & 3;
1721 pBus = pBus->aPciDev.Int.s.pBusR3;
1722 };
1723 }
1724
1725 int iIrq = aPciIrqs[ich9pciSlotGetPirq(uBus, uDevFn, iPin)];
1726 Log(("Using pin %d and IRQ %d for device %02x:%02x.%d\n",
1727 iPin, iIrq, uBus, uDevFn>>3, uDevFn&7));
1728 ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_INTERRUPT_LINE, iIrq, 1);
1729 }
1730}
1731
1732/* Initializes bridges registers used for routing. */
1733static void ich9pciInitBridgeTopology(PPCIGLOBALS pGlobals, PPCIBUS pBus)
1734{
1735 PPCIDEVICE pBridgeDev = &pBus->aPciDev;
1736 PCIDevSetByte(pBridgeDev, VBOX_PCI_PRIMARY_BUS, pGlobals->uBus);
1737
1738 /* For simplicity, let's start numbering PCI bridges from 0,
1739 * not 1, so don't increment count on Host->PCI bridge.
1740 */
1741 if (strcmp(pBridgeDev->name, "i82801") != 0)
1742 pGlobals->uBus++;
1743
1744 PCIDevSetByte(pBridgeDev, VBOX_PCI_SECONDARY_BUS, pGlobals->uBus);
1745 for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
1746 {
1747 PPCIDEVICE pBridge = pBus->papBridgesR3[iBridge];
1748 AssertMsg(pBridge && pciDevIsPci2PciBridge(pBridge),
1749 ("Device is not a PCI bridge but on the list of PCI bridges\n"));
1750 PPCIBUS pChildBus = PDMINS_2_DATA(pBridge->pDevIns, PPCIBUS);
1751 ich9pciInitBridgeTopology(pGlobals, pChildBus);
1752 }
1753 PCIDevSetByte(pBridgeDev, VBOX_PCI_SUBORDINATE_BUS, pGlobals->uBus);
1754 Log2(("ich9pciInitBridgeTopology: for bus %p: primary=%d secondary=%d subordinate=%d\n",
1755 pBus,
1756 PCIDevGetByte(pBridgeDev, VBOX_PCI_PRIMARY_BUS),
1757 PCIDevGetByte(pBridgeDev, VBOX_PCI_SECONDARY_BUS),
1758 PCIDevGetByte(pBridgeDev, VBOX_PCI_SUBORDINATE_BUS)
1759 ));
1760}
1761
1762
1763static DECLCALLBACK(int) ich9pciFakePCIBIOS(PPDMDEVINS pDevIns)
1764{
1765 unsigned i;
1766 uint8_t elcr[2] = {0, 0};
1767 PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
1768 PVM pVM = PDMDevHlpGetVM(pDevIns);
1769 Assert(pVM);
1770
1771 /*
1772 * Set the start addresses.
1773 */
1774 pGlobals->uPciBiosIo = 0xd000;
1775 pGlobals->uPciBiosMmio = UINT32_C(0xf0000000);
1776 pGlobals->uBus = 0;
1777
1778 /**
1779 * Assign bridge topology, for further routing to work.
1780 */
1781 PPCIBUS pBus = &pGlobals->aPciBus;
1782 ich9pciInitBridgeTopology(pGlobals, pBus);
1783
1784 /**
1785 * Init the devices.
1786 */
1787 for (i = 0; i < 256; i++)
1788 {
1789 ich9pciBiosInitDevice(pGlobals, 0, i);
1790 }
1791
1792 return VINF_SUCCESS;
1793}
1794
1795static DECLCALLBACK(uint32_t) ich9pciConfigReadDev(PCIDevice *aDev, uint32_t u32Address, unsigned len)
1796{
1797 if ((u32Address + len) > 256 && (u32Address + len) < 4096)
1798 {
1799 AssertMsgReturn(false, ("Read from extended registers falled back to generic code\n"), 0);
1800 }
1801
1802 AssertMsgReturn(u32Address + len <= 256, ("Read after end of PCI config space\n"),
1803 0);
1804 if ( pciDevIsMsiCapable(aDev)
1805 && (u32Address >= aDev->Int.s.u8MsiCapOffset)
1806 && (u32Address < aDev->Int.s.u8MsiCapOffset + aDev->Int.s.u8MsiCapSize)
1807 )
1808 {
1809 return MsiPciConfigRead(aDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pDevIns), aDev, u32Address, len);
1810 }
1811
1812 if ( pciDevIsMsixCapable(aDev)
1813 && (u32Address >= aDev->Int.s.u8MsixCapOffset)
1814 && (u32Address < aDev->Int.s.u8MsixCapOffset + aDev->Int.s.u8MsixCapSize)
1815 )
1816 {
1817 return MsixPciConfigRead(aDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pDevIns), aDev, u32Address, len);
1818 }
1819
1820 AssertMsgReturn(u32Address + len <= 256, ("Read after end of PCI config space\n"),
1821 0);
1822 switch (len)
1823 {
1824 case 1:
1825 return PCIDevGetByte(aDev, u32Address);
1826 case 2:
1827 return PCIDevGetWord(aDev, u32Address);
1828 case 4:
1829 return PCIDevGetDWord(aDev, u32Address);
1830 default:
1831 Assert(false);
1832 return 0;
1833 }
1834}
1835
1836DECLINLINE(void) ich9pciWriteBarByte(PCIDevice *aDev, int iRegion, int iOffset, uint8_t u8Val)
1837{
1838 PCIIORegion * pRegion = &aDev->Int.s.aIORegions[iRegion];
1839
1840 int iRegionSize = pRegion->size;
1841
1842 Log3(("ich9pciWriteBarByte: region=%d off=%d val=%x size=%d\n",
1843 iRegion, iOffset, u8Val, iRegionSize));
1844
1845 /* Region doesn't exist */
1846 if (iRegionSize == 0)
1847 return;
1848
1849 uint32_t uAddr = ich9pciGetRegionReg(iRegion) + iOffset;
1850 /* Region size must be power of two */
1851 Assert((iRegionSize & (iRegionSize - 1)) == 0);
1852 uint8_t uMask = (((uint32_t)iRegionSize - 1) >> (iOffset*8) ) & 0xff;
1853
1854 if (iOffset == 0)
1855 {
1856 uMask |= (pRegion->type & PCI_ADDRESS_SPACE_IO) ?
1857 (1 << 2) - 1 /* 2 lowest bits for IO region */ :
1858 (1 << 4) - 1 /* 4 lowest bits for memory region, also ROM enable bit for ROM region */;
1859
1860 }
1861
1862 uint8_t u8Old = PCIDevGetByte(aDev, uAddr) & uMask;
1863 u8Val = (u8Old & uMask) | (u8Val & ~uMask);
1864
1865 Log3(("ich9pciWriteBarByte: was %x writing %x\n", u8Old, u8Val));
1866
1867 PCIDevSetByte(aDev, uAddr, u8Val);
1868}
1869/**
1870 * See paragraph 7.5 of PCI Express specification (p. 349) for definition of
1871 * registers and their writability policy.
1872 */
1873static DECLCALLBACK(void) ich9pciConfigWriteDev(PCIDevice *aDev, uint32_t u32Address,
1874 uint32_t val, unsigned len)
1875{
1876 Assert(len <= 4);
1877
1878 if ((u32Address + len) > 256 && (u32Address + len) < 4096)
1879 {
1880 AssertMsgReturnVoid(false, ("Write to extended registers falled back to generic code\n"));
1881 }
1882
1883 AssertMsgReturnVoid(u32Address + len <= 256, ("Write after end of PCI config space\n"));
1884
1885 if ( pciDevIsMsiCapable(aDev)
1886 && (u32Address >= aDev->Int.s.u8MsiCapOffset)
1887 && (u32Address < aDev->Int.s.u8MsiCapOffset + aDev->Int.s.u8MsiCapSize)
1888 )
1889 {
1890 MsiPciConfigWrite(aDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pDevIns),
1891 aDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pPciHlp),
1892 aDev, u32Address, val, len);
1893 return;
1894 }
1895
1896 if ( pciDevIsMsixCapable(aDev)
1897 && (u32Address >= aDev->Int.s.u8MsixCapOffset)
1898 && (u32Address < aDev->Int.s.u8MsixCapOffset + aDev->Int.s.u8MsixCapSize)
1899 )
1900 {
1901 MsixPciConfigWrite(aDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pDevIns),
1902 aDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pPciHlp),
1903 aDev, u32Address, val, len);
1904 return;
1905 }
1906
1907 uint32_t addr = u32Address;
1908 bool fUpdateMappings = false;
1909 bool fP2PBridge = false;
1910 for (uint32_t i = 0; i < len; i++)
1911 {
1912 bool fWritable = false;
1913 bool fRom = false;
1914 switch (PCIDevGetHeaderType(aDev))
1915 {
1916 case 0x00: /* normal device */
1917 case 0x80: /* multi-function device */
1918 switch (addr)
1919 {
1920 /* Read-only registers */
1921 case VBOX_PCI_VENDOR_ID: case VBOX_PCI_VENDOR_ID+1:
1922 case VBOX_PCI_DEVICE_ID: case VBOX_PCI_DEVICE_ID+1:
1923 case VBOX_PCI_REVISION_ID:
1924 case VBOX_PCI_CLASS_PROG:
1925 case VBOX_PCI_CLASS_SUB:
1926 case VBOX_PCI_CLASS_BASE:
1927 case VBOX_PCI_HEADER_TYPE:
1928 case VBOX_PCI_SUBSYSTEM_VENDOR_ID: case VBOX_PCI_SUBSYSTEM_VENDOR_ID+1:
1929 case VBOX_PCI_SUBSYSTEM_ID: case VBOX_PCI_SUBSYSTEM_ID+1:
1930 case VBOX_PCI_ROM_ADDRESS: case VBOX_PCI_ROM_ADDRESS+1: case VBOX_PCI_ROM_ADDRESS+2: case VBOX_PCI_ROM_ADDRESS+3:
1931 case VBOX_PCI_CAPABILITY_LIST:
1932 case VBOX_PCI_INTERRUPT_PIN:
1933 fWritable = false;
1934 break;
1935 /* Others can be written */
1936 default:
1937 fWritable = true;
1938 break;
1939 }
1940 break;
1941 case 0x01: /* PCI-PCI bridge */
1942 fP2PBridge = true;
1943 switch (addr)
1944 {
1945 /* Read-only registers */
1946 case VBOX_PCI_VENDOR_ID: case VBOX_PCI_VENDOR_ID+1:
1947 case VBOX_PCI_DEVICE_ID: case VBOX_PCI_DEVICE_ID+1:
1948 case VBOX_PCI_REVISION_ID:
1949 case VBOX_PCI_CLASS_PROG:
1950 case VBOX_PCI_CLASS_SUB:
1951 case VBOX_PCI_CLASS_BASE:
1952 case VBOX_PCI_HEADER_TYPE:
1953 case VBOX_PCI_ROM_ADDRESS_BR: case VBOX_PCI_ROM_ADDRESS_BR+1: case VBOX_PCI_ROM_ADDRESS_BR+2: case VBOX_PCI_ROM_ADDRESS_BR+3:
1954 case VBOX_PCI_INTERRUPT_PIN:
1955 fWritable = false;
1956 break;
1957 default:
1958 fWritable = true;
1959 break;
1960 }
1961 break;
1962 default:
1963 AssertMsgFailed(("Unknown header type %x\n", PCIDevGetHeaderType(aDev)));
1964 fWritable = false;
1965 break;
1966 }
1967
1968 uint8_t u8Val = (uint8_t)val;
1969 switch (addr)
1970 {
1971 case VBOX_PCI_COMMAND: /* Command register, bits 0-7. */
1972 fUpdateMappings = true;
1973 PCIDevSetByte(aDev, addr, u8Val);
1974 break;
1975 case VBOX_PCI_COMMAND+1: /* Command register, bits 8-15. */
1976 /* don't change reserved bits (11-15) */
1977 u8Val &= UINT32_C(~0xf8);
1978 fUpdateMappings = true;
1979 PCIDevSetByte(aDev, addr, u8Val);
1980 break;
1981 case VBOX_PCI_STATUS: /* Status register, bits 0-7. */
1982 /* don't change read-only bits => actually all lower bits are read-only */
1983 u8Val &= UINT32_C(~0xff);
1984 /* status register, low part: clear bits by writing a '1' to the corresponding bit */
1985 aDev->config[addr] &= ~u8Val;
1986 break;
1987 case VBOX_PCI_STATUS+1: /* Status register, bits 8-15. */
1988 /* don't change read-only bits */
1989 u8Val &= UINT32_C(~0x06);
1990 /* status register, high part: clear bits by writing a '1' to the corresponding bit */
1991 aDev->config[addr] &= ~u8Val;
1992 break;
1993 case VBOX_PCI_ROM_ADDRESS: case VBOX_PCI_ROM_ADDRESS +1: case VBOX_PCI_ROM_ADDRESS +2: case VBOX_PCI_ROM_ADDRESS +3:
1994 fRom = true;
1995 case VBOX_PCI_BASE_ADDRESS_0: case VBOX_PCI_BASE_ADDRESS_0+1: case VBOX_PCI_BASE_ADDRESS_0+2: case VBOX_PCI_BASE_ADDRESS_0+3:
1996 case VBOX_PCI_BASE_ADDRESS_1: case VBOX_PCI_BASE_ADDRESS_1+1: case VBOX_PCI_BASE_ADDRESS_1+2: case VBOX_PCI_BASE_ADDRESS_1+3:
1997 case VBOX_PCI_BASE_ADDRESS_2: case VBOX_PCI_BASE_ADDRESS_2+1: case VBOX_PCI_BASE_ADDRESS_2+2: case VBOX_PCI_BASE_ADDRESS_2+3:
1998 case VBOX_PCI_BASE_ADDRESS_3: case VBOX_PCI_BASE_ADDRESS_3+1: case VBOX_PCI_BASE_ADDRESS_3+2: case VBOX_PCI_BASE_ADDRESS_3+3:
1999 case VBOX_PCI_BASE_ADDRESS_4: case VBOX_PCI_BASE_ADDRESS_4+1: case VBOX_PCI_BASE_ADDRESS_4+2: case VBOX_PCI_BASE_ADDRESS_4+3:
2000 case VBOX_PCI_BASE_ADDRESS_5: case VBOX_PCI_BASE_ADDRESS_5+1: case VBOX_PCI_BASE_ADDRESS_5+2: case VBOX_PCI_BASE_ADDRESS_5+3:
2001 {
2002 /* We check that, as same PCI register numbers as BARs may mean different registers for bridges */
2003 if (fP2PBridge)
2004 goto default_case;
2005 else
2006 {
2007 int iRegion = fRom ? VBOX_PCI_ROM_SLOT : (addr - VBOX_PCI_BASE_ADDRESS_0) >> 2;
2008 int iOffset = addr & 0x3;
2009 ich9pciWriteBarByte(aDev, iRegion, iOffset, u8Val);
2010 fUpdateMappings = true;
2011 }
2012 break;
2013 }
2014 default:
2015 default_case:
2016 if (fWritable)
2017 PCIDevSetByte(aDev, addr, u8Val);
2018 }
2019 addr++;
2020 val >>= 8;
2021 }
2022
2023 if (fUpdateMappings)
2024 /* if the command/base address register is modified, we must modify the mappings */
2025 ich9pciUpdateMappings(aDev);
2026}
2027
2028/* Slot/functions assignment per table at p. 12 of ICH9 family spec update */
2029static const struct {
2030 const char* pszName;
2031 int32_t iSlot;
2032 int32_t iFunction;
2033} PciSlotAssignments[] = {
2034 /* The only override that have to be here, as host controller is added in the way invisible to bus slot assignment management,
2035 maybe to be changed in the future. */
2036 {
2037 "i82801", 30, 0 /* Host Controller */
2038 },
2039};
2040
2041static bool assignPosition(PPCIBUS pBus, PPCIDEVICE pPciDev, const char *pszName, int iDevFn, PciAddress* aPosition)
2042{
2043 aPosition->iBus = 0;
2044 aPosition->iDeviceFunc = iDevFn;
2045 aPosition->iRegister = 0; /* N/A */
2046
2047 /* Hardcoded slots/functions, per chipset spec */
2048 for (size_t i = 0; i < RT_ELEMENTS(PciSlotAssignments); i++)
2049 {
2050 if (!strcmp(pszName, PciSlotAssignments[i].pszName))
2051 {
2052 pciDevSetRequestedDevfunc(pPciDev);
2053 aPosition->iDeviceFunc =
2054 (PciSlotAssignments[i].iSlot << 3) + PciSlotAssignments[i].iFunction;
2055 return true;
2056 }
2057 }
2058
2059 /* Explicit slot request */
2060 if (iDevFn >=0 && iDevFn < (int)RT_ELEMENTS(pBus->apDevices))
2061 return true;
2062
2063 int iStartPos = 0;
2064
2065 /* Otherwise when assigning a slot, we need to make sure all its functions are available */
2066 for (int iPos = iStartPos; iPos < (int)RT_ELEMENTS(pBus->apDevices); iPos += 8)
2067 {
2068 if ( !pBus->apDevices[iPos]
2069 && !pBus->apDevices[iPos + 1]
2070 && !pBus->apDevices[iPos + 2]
2071 && !pBus->apDevices[iPos + 3]
2072 && !pBus->apDevices[iPos + 4]
2073 && !pBus->apDevices[iPos + 5]
2074 && !pBus->apDevices[iPos + 6]
2075 && !pBus->apDevices[iPos + 7])
2076 {
2077 pciDevClearRequestedDevfunc(pPciDev);
2078 aPosition->iDeviceFunc = iPos;
2079 return true;
2080 }
2081 }
2082
2083 return false;
2084}
2085
2086static bool hasHardAssignedDevsInSlot(PPCIBUS pBus, int iSlot)
2087{
2088 PCIDevice** aSlot = &pBus->apDevices[iSlot << 3];
2089
2090 return (aSlot[0] && pciDevIsRequestedDevfunc(aSlot[0]))
2091 || (aSlot[1] && pciDevIsRequestedDevfunc(aSlot[1]))
2092 || (aSlot[2] && pciDevIsRequestedDevfunc(aSlot[2]))
2093 || (aSlot[3] && pciDevIsRequestedDevfunc(aSlot[3]))
2094 || (aSlot[4] && pciDevIsRequestedDevfunc(aSlot[4]))
2095 || (aSlot[5] && pciDevIsRequestedDevfunc(aSlot[5]))
2096 || (aSlot[6] && pciDevIsRequestedDevfunc(aSlot[6]))
2097 || (aSlot[7] && pciDevIsRequestedDevfunc(aSlot[7]))
2098 ;
2099}
2100
2101static int ich9pciRegisterInternal(PPCIBUS pBus, int iDev, PPCIDEVICE pPciDev, const char *pszName)
2102{
2103 PciAddress aPosition = {0, 0, 0};
2104
2105 /*
2106 * Find device position
2107 */
2108 if (!assignPosition(pBus, pPciDev, pszName, iDev, &aPosition))
2109 {
2110 AssertMsgFailed(("Couldn't asssign position!\n"));
2111 return VERR_PDM_TOO_PCI_MANY_DEVICES;
2112 }
2113
2114 AssertMsgReturn(aPosition.iBus == 0,
2115 ("Assigning behind the bridge not implemented yet\n"),
2116 VERR_PDM_TOO_PCI_MANY_DEVICES);
2117
2118
2119 iDev = aPosition.iDeviceFunc;
2120 /*
2121 * Check if we can really take this slot, possibly by relocating
2122 * its current habitant, if it wasn't hard assigned too.
2123 */
2124 if (pciDevIsRequestedDevfunc(pPciDev) &&
2125 pBus->apDevices[iDev] &&
2126 pciDevIsRequestedDevfunc(pBus->apDevices[iDev]))
2127 {
2128 AssertReleaseMsgFailed(("Configuration error:'%s' and '%s' are both configured as device %d\n",
2129 pszName, pBus->apDevices[iDev]->name, iDev));
2130 return VERR_INTERNAL_ERROR;
2131 }
2132
2133 if (pBus->apDevices[iDev])
2134 {
2135 /* if we got here, we shall (and usually can) relocate the device */
2136 bool assigned = assignPosition(pBus, pBus->apDevices[iDev], pBus->apDevices[iDev]->name, -1, &aPosition);
2137 AssertMsgReturn(aPosition.iBus == 0,
2138 ("Assigning behind the bridge not implemented yet\n"),
2139 VERR_PDM_TOO_PCI_MANY_DEVICES);
2140 int iRelDev = aPosition.iDeviceFunc;
2141 if (!assigned || iRelDev == iDev)
2142 {
2143 AssertMsgFailed(("Couldn't find free spot!\n"));
2144 return VERR_PDM_TOO_PCI_MANY_DEVICES;
2145 }
2146 /* Copy device function by function to its new position */
2147 for (int i = 0; i < 8; i++)
2148 {
2149 if (!pBus->apDevices[iDev + i])
2150 continue;
2151 Log(("PCI: relocating '%s' from slot %#x to %#x\n", pBus->apDevices[iDev + i]->name, iDev + i, iRelDev + i));
2152 pBus->apDevices[iRelDev + i] = pBus->apDevices[iDev + i];
2153 pBus->apDevices[iRelDev + i]->devfn = iRelDev + i;
2154 pBus->apDevices[iDev + i] = NULL;
2155 }
2156 }
2157
2158 /*
2159 * Fill in device information.
2160 */
2161 pPciDev->devfn = iDev;
2162 pPciDev->name = pszName;
2163 pPciDev->Int.s.pBusR3 = pBus;
2164 pPciDev->Int.s.pBusR0 = MMHyperR3ToR0(PDMDevHlpGetVM(pBus->CTX_SUFF(pDevIns)), pBus);
2165 pPciDev->Int.s.pBusRC = MMHyperR3ToRC(PDMDevHlpGetVM(pBus->CTX_SUFF(pDevIns)), pBus);
2166 pPciDev->Int.s.pfnConfigRead = ich9pciConfigReadDev;
2167 pPciDev->Int.s.pfnConfigWrite = ich9pciConfigWriteDev;
2168 pBus->apDevices[iDev] = pPciDev;
2169 if (pciDevIsPci2PciBridge(pPciDev))
2170 {
2171 AssertMsg(pBus->cBridges < RT_ELEMENTS(pBus->apDevices), ("Number of bridges exceeds the number of possible devices on the bus\n"));
2172 AssertMsg(pPciDev->Int.s.pfnBridgeConfigRead && pPciDev->Int.s.pfnBridgeConfigWrite,
2173 ("device is a bridge but does not implement read/write functions\n"));
2174 Log2(("Setting bridge %d on bus %p\n", pBus->cBridges, pBus));
2175 pBus->papBridgesR3[pBus->cBridges] = pPciDev;
2176 pBus->cBridges++;
2177 }
2178
2179 Log(("PCI: Registered device %d function %d on bus %d (%#x) '%s'.\n",
2180 iDev >> 3, iDev & 7, pBus->iBus, 0x80000000 | (iDev << 8), pszName));
2181
2182 return VINF_SUCCESS;
2183}
2184
2185static void printIndent(PCDBGFINFOHLP pHlp, int iIndent)
2186{
2187 for (int i = 0; i < iIndent; i++)
2188 {
2189 pHlp->pfnPrintf(pHlp, " ");
2190 }
2191}
2192static uint32_t ich9pciGetCfg(PCIDevice* aDev, int32_t iRegister, int cb)
2193{
2194 return aDev->Int.s.pfnConfigRead(aDev, iRegister, cb);
2195}
2196
2197static uint8_t ich9pciGetByte(PCIDevice* aDev, int32_t iRegister)
2198{
2199 return (uint8_t)ich9pciGetCfg(aDev, iRegister, 1);
2200}
2201
2202static uint16_t ich9pciGetWord(PCIDevice* aDev, int32_t iRegister)
2203{
2204 return (uint16_t)ich9pciGetCfg(aDev, iRegister, 2);
2205}
2206
2207static uint32_t ich9pciGetDWord(PCIDevice* aDev, int32_t iRegister)
2208{
2209 return (uint32_t)ich9pciGetCfg(aDev, iRegister, 4);
2210}
2211
2212static void ich9pciBusInfo(PPCIBUS pBus, PCDBGFINFOHLP pHlp, int iIndent, bool fRegisters)
2213{
2214 for (uint32_t iDev = 0; iDev < RT_ELEMENTS(pBus->apDevices); iDev++)
2215 {
2216 PPCIDEVICE pPciDev = pBus->apDevices[iDev];
2217 if (pPciDev != NULL)
2218 {
2219 printIndent(pHlp, iIndent);
2220
2221 /**
2222 * For passthrough devices MSI/MSI-X mostly reflects the way interrupts delivered to the guest,
2223 * as host driver handles real devices interrupts.
2224 */
2225 pHlp->pfnPrintf(pHlp, "%02x:%02x:%02x %s%s: %04x-%04x%s%s",
2226 pBus->iBus, (iDev >> 3) & 0xff, iDev & 0x7,
2227 pPciDev->name,
2228 pciDevIsPassthrough(pPciDev) ? " (PASSTHROUGH)" : "",
2229 ich9pciGetWord(pPciDev, VBOX_PCI_VENDOR_ID), ich9pciGetWord(pPciDev, VBOX_PCI_DEVICE_ID),
2230 pciDevIsMsiCapable(pPciDev) ? " MSI" : "",
2231 pciDevIsMsixCapable(pPciDev) ? " MSI-X" : ""
2232 );
2233 if (!pciDevIsPassthrough(pPciDev) && PCIDevGetInterruptPin(pPciDev) != 0)
2234 pHlp->pfnPrintf(pHlp, " IRQ%d", PCIDevGetInterruptLine(pPciDev));
2235
2236 pHlp->pfnPrintf(pHlp, "\n");
2237
2238 int iCmd = ich9pciGetWord(pPciDev, VBOX_PCI_COMMAND);
2239 if ((iCmd & (VBOX_PCI_COMMAND_IO | VBOX_PCI_COMMAND_MEMORY)) != 0)
2240 {
2241 for (int iRegion = 0; iRegion < PCI_NUM_REGIONS; iRegion++)
2242 {
2243 PCIIORegion* pRegion = &pPciDev->Int.s.aIORegions[iRegion];
2244 int32_t iRegionSize = pRegion->size;
2245
2246 if (iRegionSize == 0)
2247 continue;
2248
2249 uint32_t u32Addr = ich9pciGetDWord(pPciDev, ich9pciGetRegionReg(iRegion));
2250 const char * szDesc;
2251
2252 if (pRegion->type & PCI_ADDRESS_SPACE_IO)
2253 {
2254 szDesc = "IO";
2255 u32Addr &= ~0x3;
2256 }
2257 else
2258 {
2259 szDesc = "MMIO";
2260 u32Addr &= ~0xf;
2261 }
2262
2263 printIndent(pHlp, iIndent + 2);
2264 pHlp->pfnPrintf(pHlp, " %s region #%d: %x..%x\n",
2265 szDesc, iRegion, u32Addr, u32Addr+iRegionSize);
2266 }
2267 }
2268
2269 if (fRegisters)
2270 {
2271 printIndent(pHlp, iIndent + 2);
2272 pHlp->pfnPrintf(pHlp, " PCI registers:\n");
2273 for (int iReg = 0; iReg < 0x100; )
2274 {
2275 int iPerLine = 0x10;
2276 Assert (0x100 % iPerLine == 0);
2277 printIndent(pHlp, iIndent + 3);
2278
2279 while (iPerLine-- > 0)
2280 {
2281 pHlp->pfnPrintf(pHlp, "%02x ", ich9pciGetByte(pPciDev, iReg++));
2282 }
2283 pHlp->pfnPrintf(pHlp, "\n");
2284 }
2285 }
2286 }
2287 }
2288
2289 if (pBus->cBridges > 0)
2290 {
2291 printIndent(pHlp, iIndent);
2292 pHlp->pfnPrintf(pHlp, "Registered %d bridges, subordinate buses info follows\n", pBus->cBridges);
2293 for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
2294 {
2295 PPCIBUS pBusSub = PDMINS_2_DATA(pBus->papBridgesR3[iBridge]->pDevIns, PPCIBUS);
2296 ich9pciBusInfo(pBusSub, pHlp, iIndent + 1, fRegisters);
2297 }
2298 }
2299}
2300
2301/**
2302 * Info handler, device version.
2303 *
2304 * @param pDevIns Device instance which registered the info.
2305 * @param pHlp Callback functions for doing output.
2306 * @param pszArgs Argument string. Optional and specific to the handler.
2307 */
2308static DECLCALLBACK(void) ich9pciInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
2309{
2310 PPCIBUS pBus = DEVINS_2_PCIBUS(pDevIns);
2311
2312 if (pszArgs == NULL || !strcmp(pszArgs, "basic"))
2313 {
2314 ich9pciBusInfo(pBus, pHlp, 0, false);
2315 }
2316 else if (!strcmp(pszArgs, "verbose"))
2317 {
2318 ich9pciBusInfo(pBus, pHlp, 0, true);
2319 }
2320 else
2321 {
2322 pHlp->pfnPrintf(pHlp, "Invalid argument. Recognized arguments are 'basic', 'verbose'.\n");
2323 }
2324}
2325
2326
2327static DECLCALLBACK(int) ich9pciConstruct(PPDMDEVINS pDevIns,
2328 int iInstance,
2329 PCFGMNODE pCfg)
2330{
2331 Assert(iInstance == 0);
2332 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
2333
2334 /*
2335 * Validate and read configuration.
2336 */
2337 if (!CFGMR3AreValuesValid(pCfg,
2338 "IOAPIC\0"
2339 "GCEnabled\0"
2340 "R0Enabled\0"
2341 "McfgBase\0"
2342 "McfgLength\0"
2343 ))
2344 return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
2345
2346 /* query whether we got an IOAPIC */
2347 bool fUseIoApic;
2348 int rc = CFGMR3QueryBoolDef(pCfg, "IOAPIC", &fUseIoApic, false);
2349 if (RT_FAILURE(rc))
2350 return PDMDEV_SET_ERROR(pDevIns, rc,
2351 N_("Configuration error: Failed to query boolean value \"IOAPIC\""));
2352
2353 /* check if RC code is enabled. */
2354 bool fGCEnabled;
2355 rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
2356 if (RT_FAILURE(rc))
2357 return PDMDEV_SET_ERROR(pDevIns, rc,
2358 N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
2359
2360 /* check if R0 code is enabled. */
2361 bool fR0Enabled;
2362 rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
2363 if (RT_FAILURE(rc))
2364 return PDMDEV_SET_ERROR(pDevIns, rc,
2365 N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
2366
2367 Log(("PCI: fUseIoApic=%RTbool fGCEnabled=%RTbool fR0Enabled=%RTbool\n", fUseIoApic, fGCEnabled, fR0Enabled));
2368
2369 /*
2370 * Init data.
2371 */
2372 PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
2373 PPCIBUS pBus = &pGlobals->aPciBus;
2374 /* Zero out everything */
2375 memset(pGlobals, 0, sizeof(*pGlobals));
2376 /* And fill values */
2377 if (!fUseIoApic)
2378 return PDMDEV_SET_ERROR(pDevIns, rc,
2379 N_("Must use IO-APIC with ICH9 chipset"));
2380 rc = CFGMR3QueryU64Def(pCfg, "McfgBase", &pGlobals->u64PciConfigMMioAddress, 0);
2381 if (RT_FAILURE(rc))
2382 return PDMDEV_SET_ERROR(pDevIns, rc,
2383 N_("Configuration error: Failed to read \"McfgBase\""));
2384 rc = CFGMR3QueryU64Def(pCfg, "McfgLength", &pGlobals->u64PciConfigMMioLength, 0);
2385 if (RT_FAILURE(rc))
2386 return PDMDEV_SET_ERROR(pDevIns, rc,
2387 N_("Configuration error: Failed to read \"McfgLength\""));
2388
2389 pGlobals->pDevInsR3 = pDevIns;
2390 pGlobals->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2391 pGlobals->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2392
2393 pGlobals->aPciBus.pDevInsR3 = pDevIns;
2394 pGlobals->aPciBus.pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2395 pGlobals->aPciBus.pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2396 pGlobals->aPciBus.papBridgesR3 = (PPCIDEVICE *)PDMDevHlpMMHeapAllocZ(pDevIns, sizeof(PPCIDEVICE) * RT_ELEMENTS(pGlobals->aPciBus.apDevices));
2397
2398 /*
2399 * Register bus
2400 */
2401 PDMPCIBUSREG PciBusReg;
2402 PciBusReg.u32Version = PDM_PCIBUSREG_VERSION;
2403 PciBusReg.pfnRegisterR3 = ich9pciRegister;
2404 PciBusReg.pfnRegisterMsiR3 = ich9pciRegisterMsi;
2405 PciBusReg.pfnIORegionRegisterR3 = ich9pciIORegionRegister;
2406 PciBusReg.pfnSetConfigCallbacksR3 = ich9pciSetConfigCallbacks;
2407 PciBusReg.pfnSetIrqR3 = ich9pciSetIrq;
2408 PciBusReg.pfnSaveExecR3 = ich9pciGenericSaveExec;
2409 PciBusReg.pfnLoadExecR3 = ich9pciGenericLoadExec;
2410 PciBusReg.pfnFakePCIBIOSR3 = ich9pciFakePCIBIOS;
2411 PciBusReg.pszSetIrqRC = fGCEnabled ? "ich9pciSetIrq" : NULL;
2412 PciBusReg.pszSetIrqR0 = fR0Enabled ? "ich9pciSetIrq" : NULL;
2413 rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBus->pPciHlpR3);
2414 if (RT_FAILURE(rc))
2415 return PDMDEV_SET_ERROR(pDevIns, rc,
2416 N_("Failed to register ourselves as a PCI Bus"));
2417 if (pBus->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
2418 return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
2419 N_("PCI helper version mismatch; got %#x expected %#x"),
2420 pBus->pPciHlpR3->u32Version, PDM_PCIHLPR3_VERSION);
2421
2422 pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
2423 pBus->pPciHlpR0 = pBus->pPciHlpR3->pfnGetR0Helpers(pDevIns);
2424
2425 /*
2426 * Fill in PCI configs and add them to the bus.
2427 */
2428
2429 /**
2430 * We emulate 82801IB ICH9 IO chip used in Q35,
2431 * see http://ark.intel.com/Product.aspx?id=31892
2432 *
2433 * Stepping S-Spec Top Marking
2434 *
2435 * A2 SLA9M NH82801IB
2436 */
2437 /* Host bridge device */
2438 /* @todo: move to separate driver? */
2439 PCIDevSetVendorId( &pBus->aPciDev, 0x8086); /* Intel */
2440 PCIDevSetDeviceId( &pBus->aPciDev, 0x244e); /* Desktop */
2441 PCIDevSetRevisionId(&pBus->aPciDev, 0x92); /* rev. A2 */
2442 PCIDevSetClassBase( &pBus->aPciDev, 0x06); /* bridge */
2443 PCIDevSetClassSub( &pBus->aPciDev, 0x04); /* Host/PCI bridge */
2444 PCIDevSetClassProg( &pBus->aPciDev, 0x01); /* Supports subtractive decoding. */
2445 PCIDevSetHeaderType(&pBus->aPciDev, 0x01); /* bridge */
2446 PCIDevSetWord(&pBus->aPciDev, VBOX_PCI_SEC_STATUS, 0x0280); /* secondary status */
2447 PCIDevSetDWord(&pBus->aPciDev, 0x4c, 0x00001200); /* Bridge policy configuration */
2448 PCIDevSetStatus (&pBus->aPciDev, VBOX_PCI_STATUS_CAP_LIST);
2449 PCIDevSetCapabilityList(&pBus->aPciDev, 0x50);
2450 /* capability */
2451 PCIDevSetWord(&pBus->aPciDev, 0x50, VBOX_PCI_CAP_ID_SSVID);
2452 PCIDevSetDWord(&pBus->aPciDev, 0x54, 0x00000000); /* Subsystem vendor ids */
2453
2454 pBus->aPciDev.pDevIns = pDevIns;
2455 /* We register Host<->PCI controller on the bus */
2456 ich9pciRegisterInternal(pBus, -1, &pBus->aPciDev, "i82801");
2457
2458 /*
2459 * Register I/O ports and save state.
2460 */
2461 rc = PDMDevHlpIOPortRegister(pDevIns, 0x0cf8, 1, NULL, ich9pciIOPortAddressWrite, ich9pciIOPortAddressRead, NULL, NULL, "ICH9 (PCI)");
2462 if (RT_FAILURE(rc))
2463 return rc;
2464 rc = PDMDevHlpIOPortRegister(pDevIns, 0x0cfc, 4, NULL, ich9pciIOPortDataWrite, ich9pciIOPortDataRead, NULL, NULL, "ICH9 (PCI)");
2465 if (RT_FAILURE(rc))
2466 return rc;
2467 if (fGCEnabled)
2468 {
2469 rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x0cf8, 1, NIL_RTGCPTR, "ich9pciIOPortAddressWrite", "ich9pciIOPortAddressRead", NULL, NULL, "ICH9 (PCI)");
2470 if (RT_FAILURE(rc))
2471 return rc;
2472 rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x0cfc, 4, NIL_RTGCPTR, "ich9pciIOPortDataWrite", "ich9pciIOPortDataRead", NULL, NULL, "ICH9 (PCI)");
2473 if (RT_FAILURE(rc))
2474 return rc;
2475 }
2476 if (fR0Enabled)
2477 {
2478 rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x0cf8, 1, NIL_RTR0PTR, "ich9pciIOPortAddressWrite", "ich9pciIOPortAddressRead", NULL, NULL, "ICH9 (PCI)");
2479 if (RT_FAILURE(rc))
2480 return rc;
2481 rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x0cfc, 4, NIL_RTR0PTR, "ich9pciIOPortDataWrite", "ich9pciIOPortDataRead", NULL, NULL, "ICH9 (PCI)");
2482 if (RT_FAILURE(rc))
2483 return rc;
2484 }
2485
2486 if (pGlobals->u64PciConfigMMioAddress != 0)
2487 {
2488 rc = PDMDevHlpMMIORegister(pDevIns,
2489 pGlobals->u64PciConfigMMioAddress,
2490 pGlobals->u64PciConfigMMioLength,
2491 0,
2492 ich9pciMcfgMMIOWrite,
2493 ich9pciMcfgMMIORead,
2494 NULL /* fill */,
2495 "MCFG ranges");
2496 if (RT_FAILURE(rc))
2497 {
2498 AssertMsgRC(rc, ("Cannot register MCFG MMIO: %Rrc\n", rc));
2499 return rc;
2500 }
2501
2502 if (fGCEnabled)
2503 {
2504
2505 rc = PDMDevHlpMMIORegisterRC(pDevIns,
2506 pGlobals->u64PciConfigMMioAddress,
2507 pGlobals->u64PciConfigMMioLength,
2508 0,
2509 "ich9pciMcfgMMIOWrite",
2510 "ich9pciMcfgMMIORead",
2511 NULL /* fill */);
2512 if (RT_FAILURE(rc))
2513 {
2514 AssertMsgRC(rc, ("Cannot register MCFG MMIO (GC): %Rrc\n", rc));
2515 return rc;
2516 }
2517 }
2518
2519
2520 if (fR0Enabled)
2521 {
2522
2523 rc = PDMDevHlpMMIORegisterR0(pDevIns,
2524 pGlobals->u64PciConfigMMioAddress,
2525 pGlobals->u64PciConfigMMioLength,
2526 0,
2527 "ich9pciMcfgMMIOWrite",
2528 "ich9pciMcfgMMIORead",
2529 NULL /* fill */);
2530 if (RT_FAILURE(rc))
2531 {
2532 AssertMsgRC(rc, ("Cannot register MCFG MMIO (R0): %Rrc\n", rc));
2533 return rc;
2534 }
2535 }
2536 }
2537
2538 rc = PDMDevHlpSSMRegisterEx(pDevIns, VBOX_ICH9PCI_SAVED_STATE_VERSION_CURRENT,
2539 sizeof(*pBus) + 16*128, "pgm",
2540 NULL, NULL, NULL,
2541 NULL, ich9pciR3SaveExec, NULL,
2542 NULL, ich9pciR3LoadExec, NULL);
2543 if (RT_FAILURE(rc))
2544 return rc;
2545
2546
2547 /** @todo: other chipset devices shall be registered too */
2548 /** @todo: what to with bridges? */
2549
2550 PDMDevHlpDBGFInfoRegister(pDevIns, "pci", "Display PCI bus status. (no arguments)", ich9pciInfo);
2551
2552 return VINF_SUCCESS;
2553}
2554
2555static void ich9pciResetDevice(PPCIDEVICE pDev)
2556{
2557 PPCIBUS pBus = pDev->Int.s.CTX_SUFF(pBus);
2558 int rc;
2559
2560 /* Clear regions */
2561 for (int iRegion = 0; iRegion < PCI_NUM_REGIONS; iRegion++)
2562 {
2563 PCIIORegion* pRegion = &pDev->Int.s.aIORegions[iRegion];
2564 if (pRegion->size == 0)
2565 continue;
2566
2567 ich9pciUnmapRegion(pDev, iRegion);
2568 }
2569
2570 PCIDevSetCommand(pDev,
2571 PCIDevGetCommand(pDev)
2572 &
2573 ~(VBOX_PCI_COMMAND_IO |
2574 VBOX_PCI_COMMAND_MEMORY |
2575 VBOX_PCI_COMMAND_MASTER));
2576
2577 /* Bridge device reset handlers processed later */
2578 if (!pciDevIsPci2PciBridge(pDev))
2579 {
2580 PCIDevSetByte(pDev, VBOX_PCI_CACHE_LINE_SIZE, 0x0);
2581 PCIDevSetInterruptLine(pDev, 0x0);
2582 }
2583}
2584
2585
2586/**
2587 * @copydoc FNPDMDEVRESET
2588 */
2589static DECLCALLBACK(void) ich9pciReset(PPDMDEVINS pDevIns)
2590{
2591 PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
2592 PPCIBUS pBus = &pGlobals->aPciBus;
2593
2594 /* PCI-specific reset for each device. */
2595 for (uint32_t i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
2596 {
2597 if (pBus->apDevices[i])
2598 ich9pciResetDevice(pBus->apDevices[i]);
2599 }
2600
2601 for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
2602 {
2603 if (pBus->papBridgesR3[iBridge])
2604 ich9pcibridgeReset(pBus->papBridgesR3[iBridge]->pDevIns);
2605 }
2606
2607 ich9pciFakePCIBIOS(pDevIns);
2608}
2609
2610static void ich9pciRelocateDevice(PPCIDEVICE pDev, RTGCINTPTR offDelta)
2611{
2612 if (pDev)
2613 {
2614 pDev->Int.s.pBusRC += offDelta;
2615 if (pDev->Int.s.pMsixPageRC)
2616 pDev->Int.s.pMsixPageRC += offDelta;
2617 }
2618}
2619
2620/**
2621 * @copydoc FNPDMDEVRELOCATE
2622 */
2623static DECLCALLBACK(void) ich9pciRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
2624{
2625 PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
2626 PPCIBUS pBus = &pGlobals->aPciBus;
2627 pGlobals->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2628
2629 pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
2630 pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2631
2632 /* Relocate RC pointers for the attached pci devices. */
2633 for (uint32_t i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
2634 ich9pciRelocateDevice(pBus->apDevices[i], offDelta);
2635
2636}
2637
2638/**
2639 * @interface_method_impl{PDMDEVREG,pfnConstruct}
2640 */
2641static DECLCALLBACK(int) ich9pcibridgeConstruct(PPDMDEVINS pDevIns,
2642 int iInstance,
2643 PCFGMNODE pCfg)
2644{
2645 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
2646
2647 /*
2648 * Validate and read configuration.
2649 */
2650 if (!CFGMR3AreValuesValid(pCfg, "GCEnabled\0" "R0Enabled\0"))
2651 return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
2652
2653 /* check if RC code is enabled. */
2654 bool fGCEnabled;
2655 int rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
2656 if (RT_FAILURE(rc))
2657 return PDMDEV_SET_ERROR(pDevIns, rc,
2658 N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
2659
2660 /* check if R0 code is enabled. */
2661 bool fR0Enabled;
2662 rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
2663 if (RT_FAILURE(rc))
2664 return PDMDEV_SET_ERROR(pDevIns, rc,
2665 N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
2666 Log(("PCI: fGCEnabled=%RTbool fR0Enabled=%RTbool\n", fGCEnabled, fR0Enabled));
2667
2668 /*
2669 * Init data and register the PCI bus.
2670 */
2671 PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
2672 pBus->pDevInsR3 = pDevIns;
2673 pBus->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2674 pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2675 pBus->papBridgesR3 = (PPCIDEVICE *)PDMDevHlpMMHeapAllocZ(pDevIns, sizeof(PPCIDEVICE) * RT_ELEMENTS(pBus->apDevices));
2676
2677 PDMPCIBUSREG PciBusReg;
2678 PciBusReg.u32Version = PDM_PCIBUSREG_VERSION;
2679 PciBusReg.pfnRegisterR3 = ich9pcibridgeRegister;
2680 PciBusReg.pfnRegisterMsiR3 = ich9pciRegisterMsi;
2681 PciBusReg.pfnIORegionRegisterR3 = ich9pciIORegionRegister;
2682 PciBusReg.pfnSetConfigCallbacksR3 = ich9pciSetConfigCallbacks;
2683 PciBusReg.pfnSetIrqR3 = ich9pcibridgeSetIrq;
2684 PciBusReg.pfnSaveExecR3 = ich9pciGenericSaveExec;
2685 PciBusReg.pfnLoadExecR3 = ich9pciGenericLoadExec;
2686 PciBusReg.pfnFakePCIBIOSR3 = NULL; /* Only needed for the first bus. */
2687 PciBusReg.pszSetIrqRC = fGCEnabled ? "ich9pcibridgeSetIrq" : NULL;
2688 PciBusReg.pszSetIrqR0 = fR0Enabled ? "ich9pcibridgeSetIrq" : NULL;
2689 rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBus->pPciHlpR3);
2690 if (RT_FAILURE(rc))
2691 return PDMDEV_SET_ERROR(pDevIns, rc,
2692 N_("Failed to register ourselves as a PCI Bus"));
2693 if (pBus->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
2694 return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
2695 N_("PCI helper version mismatch; got %#x expected %#x"),
2696 pBus->pPciHlpR3->u32Version, PDM_PCIHLPR3_VERSION);
2697
2698 pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
2699 pBus->pPciHlpR0 = pBus->pPciHlpR3->pfnGetR0Helpers(pDevIns);
2700
2701 /*
2702 * Fill in PCI configs and add them to the bus.
2703 */
2704 PCIDevSetVendorId( &pBus->aPciDev, 0x8086); /* Intel */
2705 PCIDevSetDeviceId( &pBus->aPciDev, 0x2448); /* 82801 Mobile PCI bridge. */
2706 PCIDevSetRevisionId(&pBus->aPciDev, 0xf2);
2707 PCIDevSetClassSub( &pBus->aPciDev, 0x04); /* pci2pci */
2708 PCIDevSetClassBase( &pBus->aPciDev, 0x06); /* PCI_bridge */
2709 PCIDevSetClassProg( &pBus->aPciDev, 0x01); /* Supports subtractive decoding. */
2710 PCIDevSetHeaderType(&pBus->aPciDev, 0x01); /* Single function device which adheres to the PCI-to-PCI bridge spec. */
2711 PCIDevSetCommand( &pBus->aPciDev, 0x00);
2712 PCIDevSetStatus( &pBus->aPciDev, 0x20); /* 66MHz Capable. */
2713 PCIDevSetInterruptLine(&pBus->aPciDev, 0x00); /* This device does not assert interrupts. */
2714
2715 /*
2716 * This device does not generate interrupts. Interrupt delivery from
2717 * devices attached to the bus is unaffected.
2718 */
2719 PCIDevSetInterruptPin (&pBus->aPciDev, 0x00);
2720
2721 pBus->aPciDev.pDevIns = pDevIns;
2722
2723 /* Bridge-specific data */
2724 pciDevSetPci2PciBridge(&pBus->aPciDev);
2725 pBus->aPciDev.Int.s.pfnBridgeConfigRead = ich9pcibridgeConfigRead;
2726 pBus->aPciDev.Int.s.pfnBridgeConfigWrite = ich9pcibridgeConfigWrite;
2727
2728 /*
2729 * Register this PCI bridge. The called function will take care on which bus we will get registered.
2730 */
2731 rc = PDMDevHlpPCIRegister (pDevIns, &pBus->aPciDev);
2732 if (RT_FAILURE(rc))
2733 return rc;
2734
2735 /*
2736 * The iBus property doesn't really represent the bus number
2737 * because the guest and the BIOS can choose different bus numbers
2738 * for them.
2739 * The bus number is mainly for the setIrq function to indicate
2740 * when the host bus is reached which will have iBus = 0.
2741 * That's why the + 1.
2742 */
2743 pBus->iBus = iInstance + 1;
2744
2745 /*
2746 * Register SSM handlers. We use the same saved state version as for the host bridge
2747 * to make changes easier.
2748 */
2749 rc = PDMDevHlpSSMRegisterEx(pDevIns, VBOX_ICH9PCI_SAVED_STATE_VERSION_CURRENT,
2750 sizeof(*pBus) + 16*128,
2751 "pgm" /* before */,
2752 NULL, NULL, NULL,
2753 NULL, ich9pcibridgeR3SaveExec, NULL,
2754 NULL, ich9pcibridgeR3LoadExec, NULL);
2755 if (RT_FAILURE(rc))
2756 return rc;
2757
2758
2759 return VINF_SUCCESS;
2760}
2761
2762/**
2763 * @copydoc FNPDMDEVRESET
2764 */
2765static void ich9pcibridgeReset(PPDMDEVINS pDevIns)
2766{
2767 PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
2768
2769 /* Reset config space to default values. */
2770 PCIDevSetByte(&pBus->aPciDev, VBOX_PCI_PRIMARY_BUS, 0);
2771 PCIDevSetByte(&pBus->aPciDev, VBOX_PCI_SECONDARY_BUS, 0);
2772 PCIDevSetByte(&pBus->aPciDev, VBOX_PCI_SUBORDINATE_BUS, 0);
2773
2774 /* PCI-specific reset for each device. */
2775 for (uint32_t i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
2776 {
2777 if (pBus->apDevices[i])
2778 ich9pciResetDevice(pBus->apDevices[i]);
2779 }
2780}
2781
2782
2783/**
2784 * @copydoc FNPDMDEVRELOCATE
2785 */
2786static DECLCALLBACK(void) ich9pcibridgeRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
2787{
2788 PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
2789 pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2790
2791 /* Relocate RC pointers for the attached pci devices. */
2792 for (uint32_t i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
2793 ich9pciRelocateDevice(pBus->apDevices[i], offDelta);
2794}
2795
2796/**
2797 * The PCI bus device registration structure.
2798 */
2799const PDMDEVREG g_DevicePciIch9 =
2800{
2801 /* u32Version */
2802 PDM_DEVREG_VERSION,
2803 /* szName */
2804 "ich9pci",
2805 /* szRCMod */
2806 "VBoxDDGC.gc",
2807 /* szR0Mod */
2808 "VBoxDDR0.r0",
2809 /* pszDescription */
2810 "ICH9 PCI bridge",
2811 /* fFlags */
2812 PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0,
2813 /* fClass */
2814 PDM_DEVREG_CLASS_BUS_PCI | PDM_DEVREG_CLASS_BUS_ISA,
2815 /* cMaxInstances */
2816 1,
2817 /* cbInstance */
2818 sizeof(PCIGLOBALS),
2819 /* pfnConstruct */
2820 ich9pciConstruct,
2821 /* pfnDestruct */
2822 NULL,
2823 /* pfnRelocate */
2824 ich9pciRelocate,
2825 /* pfnIOCtl */
2826 NULL,
2827 /* pfnPowerOn */
2828 NULL,
2829 /* pfnReset */
2830 ich9pciReset,
2831 /* pfnSuspend */
2832 NULL,
2833 /* pfnResume */
2834 NULL,
2835 /* pfnAttach */
2836 NULL,
2837 /* pfnDetach */
2838 NULL,
2839 /* pfnQueryInterface */
2840 NULL,
2841 /* pfnInitComplete */
2842 NULL,
2843 /* pfnPowerOff */
2844 NULL,
2845 /* pfnSoftReset */
2846 NULL,
2847 /* u32VersionEnd */
2848 PDM_DEVREG_VERSION
2849};
2850
2851/**
2852 * The device registration structure
2853 * for the PCI-to-PCI bridge.
2854 */
2855const PDMDEVREG g_DevicePciIch9Bridge =
2856{
2857 /* u32Version */
2858 PDM_DEVREG_VERSION,
2859 /* szName */
2860 "ich9pcibridge",
2861 /* szRCMod */
2862 "VBoxDDGC.gc",
2863 /* szR0Mod */
2864 "VBoxDDR0.r0",
2865 /* pszDescription */
2866 "ICH9 PCI to PCI bridge",
2867 /* fFlags */
2868 PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0,
2869 /* fClass */
2870 PDM_DEVREG_CLASS_BUS_PCI,
2871 /* cMaxInstances */
2872 ~0,
2873 /* cbInstance */
2874 sizeof(PCIBUS),
2875 /* pfnConstruct */
2876 ich9pcibridgeConstruct,
2877 /* pfnDestruct */
2878 NULL,
2879 /* pfnRelocate */
2880 ich9pcibridgeRelocate,
2881 /* pfnIOCtl */
2882 NULL,
2883 /* pfnPowerOn */
2884 NULL,
2885 /* pfnReset */
2886 NULL, /* Must be NULL, to make sure only bus driver handles reset */
2887 /* pfnSuspend */
2888 NULL,
2889 /* pfnResume */
2890 NULL,
2891 /* pfnAttach */
2892 NULL,
2893 /* pfnDetach */
2894 NULL,
2895 /* pfnQueryInterface */
2896 NULL,
2897 /* pfnInitComplete */
2898 NULL,
2899 /* pfnPowerOff */
2900 NULL,
2901 /* pfnSoftReset */
2902 NULL,
2903 /* u32VersionEnd */
2904 PDM_DEVREG_VERSION
2905};
2906
2907#endif /* IN_RING3 */
2908#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
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