DevPciIch9.cpp@ 38751

Last change on this file since 38751 was 37636, checked in by vboxsync, 13 years ago
Changed FNIOMMMIOWRITE to take a const buffer pointer.
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 107.1 KB

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1	/* $Id: DevPciIch9.cpp 37636 2011-06-24 14:59:59Z vboxsync $ */
2	/** @file
3	* DevPCI - ICH9 southbridge PCI bus emulation device.
4	*/
5
6	/*
7	* Copyright (C) 2010-2011 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/*******************************************************************************
19	* Header Files *
20	*******************************************************************************/
21	#define LOG_GROUP LOG_GROUP_DEV_PCI
22	/* Hack to get PCIDEVICEINT declare at the right point - include "PCIInternal.h". */
23	#define PCI_INCLUDE_PRIVATE
24	#define PCIBus ICH9PCIBus
25	#include <VBox/pci.h>
26	#include <VBox/msi.h>
27	#include <VBox/vmm/pdmdev.h>
28	#include <iprt/asm.h>
29	#include <iprt/assert.h>
30	#include <iprt/string.h>
31	#ifdef IN_RING3
32	#include <iprt/alloc.h>
33	#endif
34
35	#include "VBoxDD.h"
36
37	#include "MsiCommon.h"
38
39
40	/*******************************************************************************
41	* Structures and Typedefs *
42	*******************************************************************************/
43	/**
44	* PCI Bus instance.
45	*/
46	typedef struct ICH9PCIBus
47	{
48	/** Bus number. */
49	int32_t iBus;
50	/** Number of bridges attached to the bus. */
51	uint32_t cBridges;
52
53	/** Array of PCI devices. We assume 32 slots, each with 8 functions. */
54	R3PTRTYPE(PPCIDEVICE) apDevices[256];
55	/** Array of bridges attached to the bus. */
56	R3PTRTYPE(PPCIDEVICE *) papBridgesR3;
57
58	/** R3 pointer to the device instance. */
59	PPDMDEVINSR3 pDevInsR3;
60	/** Pointer to the PCI R3 helpers. */
61	PCPDMPCIHLPR3 pPciHlpR3;
62
63	/** R0 pointer to the device instance. */
64	PPDMDEVINSR0 pDevInsR0;
65	/** Pointer to the PCI R0 helpers. */
66	PCPDMPCIHLPR0 pPciHlpR0;
67
68	/** RC pointer to the device instance. */
69	PPDMDEVINSRC pDevInsRC;
70	/** Pointer to the PCI RC helpers. */
71	PCPDMPCIHLPRC pPciHlpRC;
72
73	/** The PCI device for the PCI bridge. */
74	PCIDEVICE aPciDev;
75
76	} ICH9PCIBUS, *PICH9PCIBUS;
77
78
79	/** @def PCI_APIC_IRQ_PINS
80	* Number of pins for interrupts if the APIC is used.
81	*/
82	#define PCI_APIC_IRQ_PINS 8
83
84	/**
85	* PCI Globals - This is the host-to-pci bridge and the root bus.
86	*/
87	typedef struct
88	{
89	/** R3 pointer to the device instance. */
90	PPDMDEVINSR3 pDevInsR3;
91	/** R0 pointer to the device instance. */
92	PPDMDEVINSR0 pDevInsR0;
93	/** RC pointer to the device instance. */
94	PPDMDEVINSRC pDevInsRC;
95
96	#if HC_ARCH_BITS == 64
97	uint32_t Alignment0;
98	#endif
99
100	/** Config register. */
101	uint32_t uConfigReg;
102
103	/** I/O APIC irq levels */
104	volatile uint32_t uaPciApicIrqLevels[PCI_APIC_IRQ_PINS];
105
106	#if 1 /* Will be moved into the BIOS soon. */
107	/** The next I/O port address which the PCI BIOS will use. */
108	uint32_t uPciBiosIo;
109	/** The next MMIO address which the PCI BIOS will use. */
110	uint32_t uPciBiosMmio;
111	/** Actual bus number. */
112	uint8_t uBus;
113	#endif
114	/* Physical address of PCI config space MMIO region */
115	uint64_t u64PciConfigMMioAddress;
116	/* Length of PCI config space MMIO region */
117	uint64_t u64PciConfigMMioLength;
118
119	/** PCI bus which is attached to the host-to-PCI bridge. */
120	ICH9PCIBUS aPciBus;
121	} ICH9PCIGLOBALS, *PICH9PCIGLOBALS;
122
123
124	typedef struct
125	{
126	uint8_t iBus;
127	uint8_t iDeviceFunc;
128	uint16_t iRegister;
129	} PciAddress;
130
131	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
132
133	/*******************************************************************************
134	* Defined Constants And Macros *
135	*******************************************************************************/
136
137	/** @def VBOX_ICH9PCI_SAVED_STATE_VERSION
138	* Saved state version of the ICH9 PCI bus device.
139	*/
140	#define VBOX_ICH9PCI_SAVED_STATE_VERSION_NOMSI 1
141	#define VBOX_ICH9PCI_SAVED_STATE_VERSION_MSI 2
142	#define VBOX_ICH9PCI_SAVED_STATE_VERSION_CURRENT VBOX_ICH9PCI_SAVED_STATE_VERSION_MSI
143
144	/** Converts a bus instance pointer to a device instance pointer. */
145	#define PCIBUS_2_DEVINS(pPciBus) ((pPciBus)->CTX_SUFF(pDevIns))
146	/** Converts a device instance pointer to a ICH9PCIGLOBALS pointer. */
147	#define DEVINS_2_PCIGLOBALS(pDevIns) ((PICH9PCIGLOBALS)(PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS)))
148	/** Converts a device instance pointer to a PCIBUS pointer. */
149	#define DEVINS_2_PCIBUS(pDevIns) ((PICH9PCIBUS)(&PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS)->aPciBus))
150	/** Converts a pointer to a PCI root bus instance to a PCIGLOBALS pointer. */
151	#define PCIROOTBUS_2_PCIGLOBALS(pPciBus) ( (PICH9PCIGLOBALS)((uintptr_t)(pPciBus) - RT_OFFSETOF(ICH9PCIGLOBALS, aPciBus)) )
152
153	/** @def PCI_LOCK
154	* Acquires the PDM lock. This is a NOP if locking is disabled. */
155	/** @def PCI_UNLOCK
156	* Releases the PDM lock. This is a NOP if locking is disabled. */
157	#define PCI_LOCK(pDevIns, rc) \
158	do { \
159	int rc2 = DEVINS_2_PCIBUS(pDevIns)->CTX_SUFF(pPciHlp)->pfnLock((pDevIns), rc); \
160	if (rc2 != VINF_SUCCESS) \
161	return rc2; \
162	} while (0)
163	#define PCI_UNLOCK(pDevIns) \
164	DEVINS_2_PCIBUS(pDevIns)->CTX_SUFF(pPciHlp)->pfnUnlock(pDevIns)
165
166	/* Prototypes */
167	static void ich9pciSetIrqInternal(PICH9PCIGLOBALS pGlobals, uint8_t uDevFn, PPCIDEVICE pPciDev, int iIrq, int iLevel);
168	#ifdef IN_RING3
169	static void ich9pcibridgeReset(PPDMDEVINS pDevIns);
170	static int ich9pciRegisterInternal(PICH9PCIBUS pBus, int iDev, PPCIDEVICE pPciDev, const char *pszName);
171	static void ich9pciUpdateMappings(PCIDevice *pDev);
172	static DECLCALLBACK(uint32_t) ich9pciConfigReadDev(PCIDevice *aDev, uint32_t u32Address, unsigned len);
173	DECLINLINE(PPCIDEVICE) ich9pciFindBridge(PICH9PCIBUS pBus, uint8_t iBus);
174	static void ich9pciBiosInitDevice(PICH9PCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn);
175	#endif
176
177	// See 7.2.2. PCI Express Enhanced Configuration Mechanism for details of address
178	// mapping, we take n=6 approach
179	DECLINLINE(void) ich9pciPhysToPciAddr(PICH9PCIGLOBALS pGlobals, RTGCPHYS GCPhysAddr, PciAddress* pPciAddr)
180	{
181	pPciAddr->iBus = (GCPhysAddr >> 20) & ((1<<6) - 1);
182	pPciAddr->iDeviceFunc = (GCPhysAddr >> 12) & ((1<<(5+3)) - 1); // 5 bits - device, 3 bits - function
183	pPciAddr->iRegister = (GCPhysAddr >> 0) & ((1<<(6+4+2)) - 1); // 6 bits - register, 4 bits - extended register, 2 bits -Byte Enable
184	}
185
186	DECLINLINE(void) ich9pciStateToPciAddr(PICH9PCIGLOBALS pGlobals, RTGCPHYS addr, PciAddress* pPciAddr)
187	{
188	pPciAddr->iBus = (pGlobals->uConfigReg >> 16) & 0xff;
189	pPciAddr->iDeviceFunc = (pGlobals->uConfigReg >> 8) & 0xff;
190	pPciAddr->iRegister = (pGlobals->uConfigReg & 0xfc) \| (addr & 3);
191	}
192
193	PDMBOTHCBDECL(void) ich9pciSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel)
194	{
195	ich9pciSetIrqInternal(PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS), pPciDev->devfn, pPciDev, iIrq, iLevel);
196	}
197
198	PDMBOTHCBDECL(void) ich9pcibridgeSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel)
199	{
200	/*
201	* The PCI-to-PCI bridge specification defines how the interrupt pins
202	* are routed from the secondary to the primary bus (see chapter 9).
203	* iIrq gives the interrupt pin the pci device asserted.
204	* We change iIrq here according to the spec and call the SetIrq function
205	* of our parent passing the device which asserted the interrupt instead of the device of the bridge.
206	*/
207	PICH9PCIBUS pBus = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
208	PPCIDEVICE pPciDevBus = pPciDev;
209	int iIrqPinBridge = iIrq;
210	uint8_t uDevFnBridge = 0;
211
212	/* Walk the chain until we reach the host bus. */
213	do
214	{
215	uDevFnBridge = pBus->aPciDev.devfn;
216	iIrqPinBridge = ((pPciDevBus->devfn >> 3) + iIrqPinBridge) & 3;
217
218	/* Get the parent. */
219	pBus = pBus->aPciDev.Int.s.CTX_SUFF(pBus);
220	pPciDevBus = &pBus->aPciDev;
221	} while (pBus->iBus != 0);
222
223	AssertMsgReturnVoid(pBus->iBus == 0, ("This is not the host pci bus iBus=%d\n", pBus->iBus));
224	ich9pciSetIrqInternal(PCIROOTBUS_2_PCIGLOBALS(pBus), uDevFnBridge, pPciDev, iIrqPinBridge, iLevel);
225	}
226
227	/**
228	* Port I/O Handler for PCI address OUT operations.
229	*
230	* @returns VBox status code.
231	*
232	* @param pDevIns The device instance.
233	* @param pvUser User argument - ignored.
234	* @param uPort Port number used for the OUT operation.
235	* @param u32 The value to output.
236	* @param cb The value size in bytes.
237	*/
238	PDMBOTHCBDECL(int) ich9pciIOPortAddressWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
239	{
240	LogFlow(("ich9pciIOPortAddressWrite: Port=%#x u32=%#x cb=%d\n", Port, u32, cb));
241	NOREF(pvUser);
242	if (cb == 4)
243	{
244	PICH9PCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
245
246	PCI_LOCK(pDevIns, VINF_IOM_HC_IOPORT_WRITE);
247	pThis->uConfigReg = u32 & ~3; /* Bits 0-1 are reserved and we silently clear them */
248	PCI_UNLOCK(pDevIns);
249	}
250
251	return VINF_SUCCESS;
252	}
253
254	/**
255	* Port I/O Handler for PCI address IN operations.
256	*
257	* @returns VBox status code.
258	*
259	* @param pDevIns The device instance.
260	* @param pvUser User argument - ignored.
261	* @param uPort Port number used for the IN operation.
262	* @param pu32 Where to store the result.
263	* @param cb Number of bytes read.
264	*/
265	PDMBOTHCBDECL(int) ich9pciIOPortAddressRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
266	{
267	NOREF(pvUser);
268	if (cb == 4)
269	{
270	PICH9PCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
271	PCI_LOCK(pDevIns, VINF_IOM_HC_IOPORT_READ);
272	*pu32 = pThis->uConfigReg;
273	PCI_UNLOCK(pDevIns);
274	LogFlow(("ich9pciIOPortAddressRead: Port=%#x cb=%d -> %#x\n", Port, cb, *pu32));
275	return VINF_SUCCESS;
276	}
277
278	Log(("ich9pciIOPortAddressRead: Port=%#x cb=%d VERR_IOM_IOPORT_UNUSED\n", Port, cb));
279
280	return VERR_IOM_IOPORT_UNUSED;
281	}
282
283	static int ich9pciDataWriteAddr(PICH9PCIGLOBALS pGlobals, PciAddress* pAddr,
284	uint32_t val, int cb, int rcReschedule)
285	{
286	int rc = VINF_SUCCESS;
287
288	if (pAddr->iBus != 0)
289	{
290	if (pGlobals->aPciBus.cBridges)
291	{
292	#ifdef IN_RING3 /** @todo do lookup in R0/RC too! */
293	PPCIDEVICE pBridgeDevice = ich9pciFindBridge(&pGlobals->aPciBus, pAddr->iBus);
294	if (pBridgeDevice)
295	{
296	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigWrite);
297	pBridgeDevice->Int.s.pfnBridgeConfigWrite(pBridgeDevice->pDevIns, pAddr->iBus, pAddr->iDeviceFunc, pAddr->iRegister, val, cb);
298	}
299	else
300	{
301	// do nothing, bridge not found
302	}
303	#else
304	rc = rcReschedule;
305	goto out;
306	#endif
307	}
308	}
309	else
310	{
311	if (pGlobals->aPciBus.apDevices[pAddr->iDeviceFunc])
312	{
313	#ifdef IN_RING3
314	R3PTRTYPE(PCIDevice *) aDev = pGlobals->aPciBus.apDevices[pAddr->iDeviceFunc];
315	aDev->Int.s.pfnConfigWrite(aDev, pAddr->iRegister, val, cb);
316	#else
317	rc = rcReschedule;
318	goto out;
319	#endif
320	}
321	}
322
323	out:
324	Log2(("ich9pciDataWriteAddr: %02x:%02x:%02x reg %x(%d) %x %Rrc\n",
325	pAddr->iBus, pAddr->iDeviceFunc >> 3, pAddr->iDeviceFunc & 0x7, pAddr->iRegister,
326	cb, val, rc));
327
328	return rc;
329	}
330
331	static int ich9pciDataWrite(PICH9PCIGLOBALS pGlobals, uint32_t addr, uint32_t val, int len)
332	{
333	PciAddress aPciAddr;
334
335	LogFlow(("ich9pciDataWrite: config=%08x val=%08x len=%d\n", pGlobals->uConfigReg, val, len));
336
337	if (!(pGlobals->uConfigReg & (1 << 31)))
338	return VINF_SUCCESS;
339
340	if ((pGlobals->uConfigReg & 0x3) != 0)
341	return VINF_SUCCESS;
342
343	/* Compute destination device */
344	ich9pciStateToPciAddr(pGlobals, addr, &aPciAddr);
345
346	return ich9pciDataWriteAddr(pGlobals, &aPciAddr, val, len, VINF_IOM_HC_IOPORT_WRITE);
347	}
348
349	static void ich9pciNoMem(void* ptr, int cb)
350	{
351	for (int i = 0; i < cb; i++)
352	((uint8_t*)ptr)[i] = 0xff;
353	}
354
355	/**
356	* Port I/O Handler for PCI data OUT operations.
357	*
358	* @returns VBox status code.
359	*
360	* @param pDevIns The device instance.
361	* @param pvUser User argument - ignored.
362	* @param uPort Port number used for the OUT operation.
363	* @param u32 The value to output.
364	* @param cb The value size in bytes.
365	*/
366	PDMBOTHCBDECL(int) ich9pciIOPortDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
367	{
368	LogFlow(("ich9pciIOPortDataWrite: Port=%#x u32=%#x cb=%d\n", Port, u32, cb));
369	NOREF(pvUser);
370	int rc = VINF_SUCCESS;
371	if (!(Port % cb))
372	{
373	PCI_LOCK(pDevIns, VINF_IOM_HC_IOPORT_WRITE);
374	rc = ich9pciDataWrite(PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS), Port, u32, cb);
375	PCI_UNLOCK(pDevIns);
376	}
377	else
378	AssertMsgFailed(("Unaligned write to port %#x u32=%#x cb=%d\n", Port, u32, cb));
379	return rc;
380	}
381
382	static int ich9pciDataReadAddr(PICH9PCIGLOBALS pGlobals, PciAddress* pPciAddr, int cb,
383	uint32_t *pu32, int rcReschedule)
384	{
385	int rc = VINF_SUCCESS;
386
387	if (pPciAddr->iBus != 0)
388	{
389	if (pGlobals->aPciBus.cBridges)
390	{
391	#ifdef IN_RING3 /** @todo do lookup in R0/RC too! */
392	PPCIDEVICE pBridgeDevice = ich9pciFindBridge(&pGlobals->aPciBus, pPciAddr->iBus);
393	if (pBridgeDevice)
394	{
395	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigRead);
396	*pu32 = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->pDevIns, pPciAddr->iBus, pPciAddr->iDeviceFunc, pPciAddr->iRegister, cb);
397	}
398	else
399	ich9pciNoMem(pu32, cb);
400	#else
401	rc = rcReschedule;
402	goto out;
403	#endif
404	} else
405	ich9pciNoMem(pu32, cb);
406	}
407	else
408	{
409	if (pGlobals->aPciBus.apDevices[pPciAddr->iDeviceFunc])
410	{
411	#ifdef IN_RING3
412	R3PTRTYPE(PCIDevice *) aDev = pGlobals->aPciBus.apDevices[pPciAddr->iDeviceFunc];
413	*pu32 = aDev->Int.s.pfnConfigRead(aDev, pPciAddr->iRegister, cb);
414	#else
415	rc = rcReschedule;
416	goto out;
417	#endif
418	}
419	else
420	ich9pciNoMem(pu32, cb);
421	}
422
423	out:
424	Log3(("ich9pciDataReadAddr: %02x:%02x:%02x reg %x(%d) gave %x %Rrc\n",
425	pPciAddr->iBus, pPciAddr->iDeviceFunc >> 3, pPciAddr->iDeviceFunc & 0x7, pPciAddr->iRegister,
426	cb, *pu32, rc));
427
428	return rc;
429	}
430
431	static int ich9pciDataRead(PICH9PCIGLOBALS pGlobals, uint32_t addr, int cb, uint32_t *pu32)
432	{
433	PciAddress aPciAddr;
434
435	LogFlow(("ich9pciDataRead: config=%x cb=%d\n", pGlobals->uConfigReg, cb));
436
437	*pu32 = 0xffffffff;
438
439	if (!(pGlobals->uConfigReg & (1 << 31)))
440	return VINF_SUCCESS;
441
442	if ((pGlobals->uConfigReg & 0x3) != 0)
443	return VINF_SUCCESS;
444
445	/* Compute destination device */
446	ich9pciStateToPciAddr(pGlobals, addr, &aPciAddr);
447
448	return ich9pciDataReadAddr(pGlobals, &aPciAddr, cb, pu32, VINF_IOM_HC_IOPORT_READ);
449	}
450
451	/**
452	* Port I/O Handler for PCI data IN operations.
453	*
454	* @returns VBox status code.
455	*
456	* @param pDevIns The device instance.
457	* @param pvUser User argument - ignored.
458	* @param uPort Port number used for the IN operation.
459	* @param pu32 Where to store the result.
460	* @param cb Number of bytes read.
461	*/
462	PDMBOTHCBDECL(int) ich9pciIOPortDataRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
463	{
464	NOREF(pvUser);
465	if (!(Port % cb))
466	{
467	PCI_LOCK(pDevIns, VINF_IOM_HC_IOPORT_READ);
468	int rc = ich9pciDataRead(PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS), Port, cb, pu32);
469	PCI_UNLOCK(pDevIns);
470	LogFlow(("ich9pciIOPortDataRead: Port=%#x cb=%#x -> %#x (%Rrc)\n", Port, cb, *pu32, rc));
471	return rc;
472	}
473	AssertMsgFailed(("Unaligned read from port %#x cb=%d\n", Port, cb));
474	return VERR_IOM_IOPORT_UNUSED;
475	}
476
477	/* Compute mapping of PCI slot and IRQ number to APIC interrupt line */
478	DECLINLINE(int) ich9pciSlot2ApicIrq(uint8_t uSlot, int irq_num)
479	{
480	return (irq_num + uSlot) & 7;
481	}
482
483	/* return the global irq number corresponding to a given device irq
484	pin. We could also use the bus number to have a more precise
485	mapping. This is the implementation note described in the PCI spec chapter 2.2.6 */
486	DECLINLINE(int) ich9pciSlotGetPirq(uint8_t uBus, uint8_t uDevFn, int iIrqNum)
487	{
488	int iSlotAddend = (uDevFn >> 3) - 1;
489	return (iIrqNum + iSlotAddend) & 3;
490	}
491
492	/* irqs corresponding to PCI irqs A-D, must match pci_irq_list in rombios.c */
493	static const uint8_t aPciIrqs[4] = { 11, 10, 9, 5 };
494
495	/* Add one more level up request on APIC input line */
496	DECLINLINE(void) ich9pciApicLevelUp(PICH9PCIGLOBALS pGlobals, int irq_num)
497	{
498	ASMAtomicIncU32(&pGlobals->uaPciApicIrqLevels[irq_num]);
499	}
500
501	/* Remove one level up request on APIC input line */
502	DECLINLINE(void) ich9pciApicLevelDown(PICH9PCIGLOBALS pGlobals, int irq_num)
503	{
504	ASMAtomicDecU32(&pGlobals->uaPciApicIrqLevels[irq_num]);
505	}
506
507	static void ich9pciApicSetIrq(PICH9PCIBUS pBus, uint8_t uDevFn, PCIDevice *pPciDev, int irq_num1, int iLevel, int iForcedIrq)
508	{
509	/* This is only allowed to be called with a pointer to the root bus. */
510	AssertMsg(pBus->iBus == 0, ("iBus=%u\n", pBus->iBus));
511
512	if (iForcedIrq == -1)
513	{
514	int apic_irq, apic_level;
515	PICH9PCIGLOBALS pGlobals = PCIROOTBUS_2_PCIGLOBALS(pBus);
516	int irq_num = ich9pciSlot2ApicIrq(uDevFn >> 3, irq_num1);
517
518	if ((iLevel & PDM_IRQ_LEVEL_HIGH) == PDM_IRQ_LEVEL_HIGH)
519	ich9pciApicLevelUp(pGlobals, irq_num);
520	else if ((iLevel & PDM_IRQ_LEVEL_HIGH) == PDM_IRQ_LEVEL_LOW)
521	ich9pciApicLevelDown(pGlobals, irq_num);
522
523	apic_irq = irq_num + 0x10;
524	apic_level = pGlobals->uaPciApicIrqLevels[irq_num] != 0;
525	Log3(("ich9pciApicSetIrq: %s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d\n",
526	R3STRING(pPciDev->name), irq_num1, iLevel, apic_irq, apic_level, irq_num));
527	pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), apic_irq, apic_level);
528
529	if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP)
530	{
531	/*
532	* we raised it few lines above, as PDM_IRQ_LEVEL_FLIP_FLOP has
533	* PDM_IRQ_LEVEL_HIGH bit set
534	*/
535	ich9pciApicLevelDown(pGlobals, irq_num);
536	pPciDev->Int.s.uIrqPinState = PDM_IRQ_LEVEL_LOW;
537	apic_level = pGlobals->uaPciApicIrqLevels[irq_num] != 0;
538	Log3(("ich9pciApicSetIrq: %s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d (flop)\n",
539	R3STRING(pPciDev->name), irq_num1, iLevel, apic_irq, apic_level, irq_num));
540	pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), apic_irq, apic_level);
541	}
542	} else {
543	Log3(("ich9pciApicSetIrq: (forced) %s: irq_num1=%d level=%d acpi_irq=%d\n",
544	R3STRING(pPciDev->name), irq_num1, iLevel, iForcedIrq));
545	pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), iForcedIrq, iLevel);
546	}
547	}
548
549	static void ich9pciSetIrqInternal(PICH9PCIGLOBALS pGlobals, uint8_t uDevFn, PPCIDEVICE pPciDev, int iIrq, int iLevel)
550	{
551
552	if (PCIDevIsIntxDisabled(pPciDev))
553	{
554	if (MsiIsEnabled(pPciDev))
555	{
556	PPDMDEVINS pDevIns = pGlobals->aPciBus.CTX_SUFF(pDevIns);
557	MsiNotify(pDevIns, pGlobals->aPciBus.CTX_SUFF(pPciHlp), pPciDev, iIrq, iLevel);
558	}
559
560	if (MsixIsEnabled(pPciDev))
561	{
562	PPDMDEVINS pDevIns = pGlobals->aPciBus.CTX_SUFF(pDevIns);
563	MsixNotify(pDevIns, pGlobals->aPciBus.CTX_SUFF(pPciHlp), pPciDev, iIrq, iLevel);
564	}
565	return;
566	}
567
568	PICH9PCIBUS pBus = &pGlobals->aPciBus;
569	const bool fIsAcpiDevice = PCIDevGetDeviceId(pPciDev) == 0x7113;
570
571	/* Check if the state changed. */
572	if (pPciDev->Int.s.uIrqPinState != iLevel)
573	{
574	pPciDev->Int.s.uIrqPinState = (iLevel & PDM_IRQ_LEVEL_HIGH);
575
576	/* Send interrupt to I/O APIC only now. */
577	if (fIsAcpiDevice)
578	/*
579	* ACPI needs special treatment since SCI is hardwired and
580	* should not be affected by PCI IRQ routing tables at the
581	* same time SCI IRQ is shared in PCI sense hence this
582	* kludge (i.e. we fetch the hardwired value from ACPIs
583	* PCI device configuration space).
584	*/
585	ich9pciApicSetIrq(pBus, uDevFn, pPciDev, -1, iLevel, PCIDevGetInterruptLine(pPciDev));
586	else
587	ich9pciApicSetIrq(pBus, uDevFn, pPciDev, iIrq, iLevel, -1);
588	}
589	}
590
591	PDMBOTHCBDECL(int) ich9pciMcfgMMIOWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void const pv, unsigned cb)
592	{
593	PICH9PCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
594	PciAddress aDest;
595	uint32_t u32 = 0;
596
597	Log2(("ich9pciMcfgMMIOWrite: %RGp(%d) \n", GCPhysAddr, cb));
598
599	PCI_LOCK(pDevIns, VINF_IOM_HC_MMIO_WRITE);
600
601	ich9pciPhysToPciAddr(pGlobals, GCPhysAddr, &aDest);
602
603	switch (cb)
604	{
605	case 1:
606	u32 = (uint8_t)pv;
607	break;
608	case 2:
609	u32 = (uint16_t)pv;
610	break;
611	case 4:
612	u32 = (uint32_t)pv;
613	break;
614	default:
615	Assert(false);
616	break;
617	}
618	int rc = ich9pciDataWriteAddr(pGlobals, &aDest, u32, cb, VINF_IOM_HC_MMIO_WRITE);
619	PCI_UNLOCK(pDevIns);
620
621	return rc;
622	}
623
624	PDMBOTHCBDECL(int) ich9pciMcfgMMIORead (PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb)
625	{
626	PICH9PCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
627	PciAddress aDest;
628	uint32_t rv;
629
630	LogFlow(("ich9pciMcfgMMIORead: %RGp(%d) \n", GCPhysAddr, cb));
631
632	PCI_LOCK(pDevIns, VINF_IOM_HC_MMIO_READ);
633
634	ich9pciPhysToPciAddr(pGlobals, GCPhysAddr, &aDest);
635
636	int rc = ich9pciDataReadAddr(pGlobals, &aDest, cb, &rv, VINF_IOM_HC_MMIO_READ);
637
638	if (RT_SUCCESS(rc))
639	{
640	switch (cb)
641	{
642	case 1:
643	(uint8_t)pv = (uint8_t)rv;
644	break;
645	case 2:
646	(uint16_t)pv = (uint16_t)rv;
647	break;
648	case 4:
649	(uint32_t)pv = (uint32_t)rv;
650	break;
651	default:
652	Assert(false);
653	break;
654	}
655	}
656	PCI_UNLOCK(pDevIns);
657
658	return rc;
659	}
660
661	#ifdef IN_RING3
662
663	DECLINLINE(PPCIDEVICE) ich9pciFindBridge(PICH9PCIBUS pBus, uint8_t iBus)
664	{
665	/* Search for a fitting bridge. */
666	for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
667	{
668	/*
669	* Examine secondary and subordinate bus number.
670	* If the target bus is in the range we pass the request on to the bridge.
671	*/
672	PPCIDEVICE pBridge = pBus->papBridgesR3[iBridge];
673	AssertMsg(pBridge && pciDevIsPci2PciBridge(pBridge),
674	("Device is not a PCI bridge but on the list of PCI bridges\n"));
675	uint32_t uSecondary = PCIDevGetByte(pBridge, VBOX_PCI_SECONDARY_BUS);
676	uint32_t uSubordinate = PCIDevGetByte(pBridge, VBOX_PCI_SUBORDINATE_BUS);
677	Log3(("ich9pciFindBridge on bus %p, bridge %d: %d in %d..%d\n", pBus, iBridge, iBus, uSecondary, uSubordinate));
678	if (iBus >= uSecondary && iBus <= uSubordinate)
679	return pBridge;
680	}
681
682	/* Nothing found. */
683	return NULL;
684	}
685
686	static uint32_t ich9pciGetCfg(PCIDevice* aDev, int32_t iRegister, int cb)
687	{
688	return aDev->Int.s.pfnConfigRead(aDev, iRegister, cb);
689	}
690
691	static uint8_t ich9pciGetByte(PCIDevice* aDev, int32_t iRegister)
692	{
693	return (uint8_t)ich9pciGetCfg(aDev, iRegister, 1);
694	}
695
696	static uint16_t ich9pciGetWord(PCIDevice* aDev, int32_t iRegister)
697	{
698	return (uint16_t)ich9pciGetCfg(aDev, iRegister, 2);
699	}
700
701	static uint32_t ich9pciGetDWord(PCIDevice* aDev, int32_t iRegister)
702	{
703	return (uint32_t)ich9pciGetCfg(aDev, iRegister, 4);
704	}
705
706	DECLINLINE(uint32_t) ich9pciGetRegionReg(int iRegion)
707	{
708	return (iRegion == VBOX_PCI_ROM_SLOT) ?
709	VBOX_PCI_ROM_ADDRESS : (VBOX_PCI_BASE_ADDRESS_0 + iRegion * 4);
710	}
711
712	#define INVALID_PCI_ADDRESS ~0U
713
714	static int ich9pciUnmapRegion(PPCIDEVICE pDev, int iRegion)
715	{
716	PCIIORegion* pRegion = &pDev->Int.s.aIORegions[iRegion];
717	int rc = VINF_SUCCESS;
718	PICH9PCIBUS pBus = pDev->Int.s.CTX_SUFF(pBus);
719
720	Assert (pRegion->size != 0);
721
722	if (pRegion->addr != INVALID_PCI_ADDRESS)
723	{
724	if (pRegion->type & PCI_ADDRESS_SPACE_IO)
725	{
726	/* Port IO */
727	rc = PDMDevHlpIOPortDeregister(pDev->pDevIns, pRegion->addr, pRegion->size);
728	AssertRC(rc);
729	}
730	else
731	{
732	RTGCPHYS GCPhysBase = pRegion->addr;
733	if (pBus->pPciHlpR3->pfnIsMMIO2Base(pBus->pDevInsR3, pDev->pDevIns, GCPhysBase))
734	{
735	/* unmap it. */
736	rc = pRegion->map_func(pDev, iRegion, NIL_RTGCPHYS, pRegion->size, (PCIADDRESSSPACE)(pRegion->type));
737	AssertRC(rc);
738	rc = PDMDevHlpMMIO2Unmap(pDev->pDevIns, iRegion, GCPhysBase);
739	}
740	else
741	rc = PDMDevHlpMMIODeregister(pDev->pDevIns, GCPhysBase, pRegion->size);
742	}
743
744	pRegion->addr = INVALID_PCI_ADDRESS;
745	}
746
747	return rc;
748	}
749
750	static void ich9pciUpdateMappings(PCIDevice* pDev)
751	{
752	PICH9PCIBUS pBus = pDev->Int.s.CTX_SUFF(pBus);
753	uint64_t uLast, uNew;
754
755	int iCmd = ich9pciGetWord(pDev, VBOX_PCI_COMMAND);
756	for (int iRegion = 0; iRegion < PCI_NUM_REGIONS; iRegion++)
757	{
758	PCIIORegion* pRegion = &pDev->Int.s.aIORegions[iRegion];
759	uint32_t uConfigReg = ich9pciGetRegionReg(iRegion);
760	int64_t iRegionSize = pRegion->size;
761	int rc;
762
763	if (iRegionSize == 0)
764	continue;
765
766	bool f64Bit = (pRegion->type & PCI_ADDRESS_SPACE_BAR64) != 0;
767
768	if (pRegion->type & PCI_ADDRESS_SPACE_IO)
769	{
770	/* port IO region */
771	if (iCmd & PCI_COMMAND_IOACCESS)
772	{
773	/* IO access allowed */
774	uNew = ich9pciGetDWord(pDev, uConfigReg);
775	uNew &= ~(iRegionSize - 1);
776	uLast = uNew + iRegionSize - 1;
777	/* only 64K ioports on PC */
778	if (uLast <= uNew \|\| uNew == 0 \|\| uLast >= 0x10000)
779	uNew = INVALID_PCI_ADDRESS;
780	} else
781	uNew = INVALID_PCI_ADDRESS;
782	}
783	else
784	{
785	/* MMIO region */
786	if (iCmd & PCI_COMMAND_MEMACCESS)
787	{
788	uNew = ich9pciGetDWord(pDev, uConfigReg);
789
790	if (f64Bit)
791	{
792	uNew \|= ((uint64_t)ich9pciGetDWord(pDev, uConfigReg+4)) << 32;
793	if (uNew > UINT64_C(0x0000010000000000))
794	{
795	/* Workaround for REM being unhapping with mapping very lange 64-bit addresses */
796	Log(("Ignoring too 64-bit BAR: %llx\n", uNew));
797	uNew = INVALID_PCI_ADDRESS;
798	}
799	}
800
801	/* the ROM slot has a specific enable bit */
802	if (iRegion == PCI_ROM_SLOT && !(uNew & 1))
803	uNew = INVALID_PCI_ADDRESS;
804	else
805	{
806	uNew &= ~(iRegionSize - 1);
807	uLast = uNew + iRegionSize - 1;
808	/* NOTE: we do not support wrapping */
809	/* XXX: as we cannot support really dynamic
810	mappings, we handle specific values as invalid
811	mappings. */
812	if (uLast <= uNew \|\| uNew == 0 \|\| uLast == INVALID_PCI_ADDRESS)
813	uNew = INVALID_PCI_ADDRESS;
814	}
815	} else
816	uNew = INVALID_PCI_ADDRESS;
817	}
818	/* now do the real mapping */
819	if (uNew != pRegion->addr)
820	{
821	if (pRegion->addr != INVALID_PCI_ADDRESS)
822	ich9pciUnmapRegion(pDev, iRegion);
823
824	pRegion->addr = uNew;
825	if (pRegion->addr != INVALID_PCI_ADDRESS)
826	{
827
828	/* finally, map the region */
829	rc = pRegion->map_func(pDev, iRegion,
830	pRegion->addr, pRegion->size,
831	(PCIADDRESSSPACE)(pRegion->type));
832	AssertRC(rc);
833	}
834	}
835	}
836	}
837
838	static DECLCALLBACK(int) ich9pciRegister(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, const char *pszName, int iDev)
839	{
840	PICH9PCIBUS pBus = DEVINS_2_PCIBUS(pDevIns);
841
842	/*
843	* Check input.
844	*/
845	if ( !pszName
846	\|\| !pPciDev
847	\|\| iDev >= (int)RT_ELEMENTS(pBus->apDevices)
848	)
849	{
850	AssertMsgFailed(("Invalid argument! pszName=%s pPciDev=%p iDev=%d\n", pszName, pPciDev, iDev));
851	return VERR_INVALID_PARAMETER;
852	}
853
854	/*
855	* Register the device.
856	*/
857	return ich9pciRegisterInternal(pBus, iDev, pPciDev, pszName);
858	}
859
860
861	static DECLCALLBACK(int) ich9pciRegisterMsi(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PPDMMSIREG pMsiReg)
862	{
863	int rc;
864
865	rc = MsiInit(pPciDev, pMsiReg);
866	if (RT_FAILURE(rc))
867	return rc;
868
869	rc = MsixInit(pPciDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pPciHlp), pPciDev, pMsiReg);
870	if (RT_FAILURE(rc))
871	return rc;
872
873	return VINF_SUCCESS;
874	}
875
876
877	static DECLCALLBACK(int) ich9pcibridgeRegister(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, const char *pszName, int iDev)
878	{
879
880	PICH9PCIBUS pBus = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
881
882	/*
883	* Check input.
884	*/
885	if ( !pszName
886	\|\| !pPciDev
887	\|\| iDev >= (int)RT_ELEMENTS(pBus->apDevices))
888	{
889	AssertMsgFailed(("Invalid argument! pszName=%s pPciDev=%p iDev=%d\n", pszName, pPciDev, iDev));
890	return VERR_INVALID_PARAMETER;
891	}
892
893	/*
894	* Register the device.
895	*/
896	return ich9pciRegisterInternal(pBus, iDev, pPciDev, pszName);
897	}
898
899	static DECLCALLBACK(int) ich9pciIORegionRegister(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iRegion, uint32_t cbRegion, PCIADDRESSSPACE enmType, PFNPCIIOREGIONMAP pfnCallback)
900	{
901	/*
902	* Validate.
903	*/
904	AssertMsgReturn( enmType == (PCI_ADDRESS_SPACE_MEM \| PCI_ADDRESS_SPACE_BAR32)
905	\|\| enmType == (PCI_ADDRESS_SPACE_MEM_PREFETCH \| PCI_ADDRESS_SPACE_BAR32)
906	\|\| enmType == (PCI_ADDRESS_SPACE_MEM \| PCI_ADDRESS_SPACE_BAR64)
907	\|\| enmType == (PCI_ADDRESS_SPACE_MEM_PREFETCH \| PCI_ADDRESS_SPACE_BAR64)
908	\|\| enmType == PCI_ADDRESS_SPACE_IO
909	,
910	("Invalid enmType=%#x? Or was this a bitmask after all...\n", enmType),
911	VERR_INVALID_PARAMETER);
912	AssertMsgReturn((unsigned)iRegion < PCI_NUM_REGIONS,
913	("Invalid iRegion=%d PCI_NUM_REGIONS=%d\n", iRegion, PCI_NUM_REGIONS),
914	VERR_INVALID_PARAMETER);
915	int iLastSet = ASMBitLastSetU32(cbRegion);
916	AssertMsgReturn( iLastSet != 0
917	&& RT_BIT_32(iLastSet - 1) == cbRegion,
918	("Invalid cbRegion=%#x iLastSet=%#x (not a power of 2 or 0)\n", cbRegion, iLastSet),
919	VERR_INVALID_PARAMETER);
920
921	Log(("ich9pciIORegionRegister: %s region %d size %d type %x\n",
922	pPciDev->name, iRegion, cbRegion, enmType));
923
924	/* Make sure that we haven't marked this region as continuation of 64-bit region. */
925	Assert(pPciDev->Int.s.aIORegions[iRegion].type != 0xff);
926
927	/*
928	* Register the I/O region.
929	*/
930	PPCIIOREGION pRegion = &pPciDev->Int.s.aIORegions[iRegion];
931	pRegion->addr = INVALID_PCI_ADDRESS;
932	pRegion->size = cbRegion;
933	pRegion->type = enmType;
934	pRegion->map_func = pfnCallback;
935
936	if ((enmType & PCI_ADDRESS_SPACE_BAR64) != 0)
937	{
938	AssertMsgReturn(iRegion < 4,
939	("Region %d cannot be 64-bit\n", iRegion),
940	VERR_INVALID_PARAMETER);
941	/* Mark next region as continuation of this one. */
942	pPciDev->Int.s.aIORegions[iRegion+1].type = 0xff;
943	}
944
945	/* Set type in the PCI config space. */
946	uint32_t u32Value = ((uint32_t)enmType) & (PCI_ADDRESS_SPACE_IO \| PCI_ADDRESS_SPACE_BAR64 \| PCI_ADDRESS_SPACE_MEM_PREFETCH);
947	PCIDevSetDWord(pPciDev, ich9pciGetRegionReg(iRegion), u32Value);
948
949	return VINF_SUCCESS;
950	}
951
952	static DECLCALLBACK(void) ich9pciSetConfigCallbacks(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PFNPCICONFIGREAD pfnRead, PPFNPCICONFIGREAD ppfnReadOld,
953	PFNPCICONFIGWRITE pfnWrite, PPFNPCICONFIGWRITE ppfnWriteOld)
954	{
955	if (ppfnReadOld)
956	*ppfnReadOld = pPciDev->Int.s.pfnConfigRead;
957	pPciDev->Int.s.pfnConfigRead = pfnRead;
958
959	if (ppfnWriteOld)
960	*ppfnWriteOld = pPciDev->Int.s.pfnConfigWrite;
961	pPciDev->Int.s.pfnConfigWrite = pfnWrite;
962	}
963
964	/**
965	* Saves a state of the PCI device.
966	*
967	* @returns VBox status code.
968	* @param pDevIns Device instance of the PCI Bus.
969	* @param pPciDev Pointer to PCI device.
970	* @param pSSM The handle to save the state to.
971	*/
972	static DECLCALLBACK(int) ich9pciGenericSaveExec(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PSSMHANDLE pSSM)
973	{
974	Assert(!pciDevIsPassthrough(pPciDev));
975	return SSMR3PutMem(pSSM, &pPciDev->config[0], sizeof(pPciDev->config));
976	}
977
978	static int ich9pciR3CommonSaveExec(PICH9PCIBUS pBus, PSSMHANDLE pSSM)
979	{
980	/*
981	* Iterate thru all the devices.
982	*/
983	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
984	{
985	PPCIDEVICE pDev = pBus->apDevices[i];
986	if (pDev)
987	{
988	/* Device position */
989	SSMR3PutU32(pSSM, i);
990	/* PCI config registers */
991	SSMR3PutMem(pSSM, pDev->config, sizeof(pDev->config));
992
993	/* Device flags */
994	int rc = SSMR3PutU32(pSSM, pDev->Int.s.fFlags);
995	if (RT_FAILURE(rc))
996	return rc;
997
998	/* IRQ pin state */
999	rc = SSMR3PutS32(pSSM, pDev->Int.s.uIrqPinState);
1000	if (RT_FAILURE(rc))
1001	return rc;
1002
1003	/* MSI info */
1004	rc = SSMR3PutU8(pSSM, pDev->Int.s.u8MsiCapOffset);
1005	if (RT_FAILURE(rc))
1006	return rc;
1007	rc = SSMR3PutU8(pSSM, pDev->Int.s.u8MsiCapSize);
1008	if (RT_FAILURE(rc))
1009	return rc;
1010
1011	/* MSI-X info */
1012	rc = SSMR3PutU8(pSSM, pDev->Int.s.u8MsixCapOffset);
1013	if (RT_FAILURE(rc))
1014	return rc;
1015	rc = SSMR3PutU8(pSSM, pDev->Int.s.u8MsixCapSize);
1016	if (RT_FAILURE(rc))
1017	return rc;
1018	/* Save MSI-X page state */
1019	if (pDev->Int.s.u8MsixCapOffset != 0)
1020	{
1021	Assert(pDev->Int.s.pMsixPageR3 != NULL);
1022	SSMR3PutMem(pSSM, pDev->Int.s.pMsixPageR3, 0x1000);
1023	if (RT_FAILURE(rc))
1024	return rc;
1025	}
1026	}
1027	}
1028	return SSMR3PutU32(pSSM, UINT32_MAX); /* terminator */
1029	}
1030
1031	static DECLCALLBACK(int) ich9pciR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
1032	{
1033	PICH9PCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
1034
1035	/*
1036	* Bus state data.
1037	*/
1038	SSMR3PutU32(pSSM, pThis->uConfigReg);
1039
1040	/*
1041	* Save IRQ states.
1042	*/
1043	for (int i = 0; i < PCI_APIC_IRQ_PINS; i++)
1044	SSMR3PutU32(pSSM, pThis->uaPciApicIrqLevels[i]);
1045
1046	SSMR3PutU32(pSSM, ~0); /* separator */
1047
1048	return ich9pciR3CommonSaveExec(&pThis->aPciBus, pSSM);
1049	}
1050
1051
1052	static DECLCALLBACK(int) ich9pcibridgeR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
1053	{
1054	PICH9PCIBUS pThis = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
1055	return ich9pciR3CommonSaveExec(pThis, pSSM);
1056	}
1057
1058
1059	static void ich9pcibridgeConfigWrite(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice, uint32_t u32Address, uint32_t u32Value, unsigned cb)
1060	{
1061	PICH9PCIBUS pBus = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
1062
1063	LogFlowFunc((": pDevIns=%p iBus=%d iDevice=%d u32Address=%u u32Value=%u cb=%d\n", pDevIns, iBus, iDevice, u32Address, u32Value, cb));
1064
1065	/* If the current bus is not the target bus search for the bus which contains the device. */
1066	if (iBus != PCIDevGetByte(&pBus->aPciDev, VBOX_PCI_SECONDARY_BUS))
1067	{
1068	PPCIDEVICE pBridgeDevice = ich9pciFindBridge(pBus, iBus);
1069	if (pBridgeDevice)
1070	{
1071	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigWrite);
1072	pBridgeDevice->Int.s.pfnBridgeConfigWrite(pBridgeDevice->pDevIns, iBus, iDevice, u32Address, u32Value, cb);
1073	}
1074	}
1075	else
1076	{
1077	/* This is the target bus, pass the write to the device. */
1078	PPCIDEVICE pPciDev = pBus->apDevices[iDevice];
1079	if (pPciDev)
1080	{
1081	Log(("%s: %s: addr=%02x val=%08x len=%d\n", __FUNCTION__, pPciDev->name, u32Address, u32Value, cb));
1082	pPciDev->Int.s.pfnConfigWrite(pPciDev, u32Address, u32Value, cb);
1083	}
1084	}
1085	}
1086
1087	static uint32_t ich9pcibridgeConfigRead(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice, uint32_t u32Address, unsigned cb)
1088	{
1089	PICH9PCIBUS pBus = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
1090	uint32_t u32Value;
1091
1092	LogFlowFunc((": pDevIns=%p iBus=%d iDevice=%d u32Address=%u cb=%d\n", pDevIns, iBus, iDevice, u32Address, cb));
1093
1094	/* If the current bus is not the target bus search for the bus which contains the device. */
1095	if (iBus != PCIDevGetByte(&pBus->aPciDev, VBOX_PCI_SECONDARY_BUS))
1096	{
1097	PPCIDEVICE pBridgeDevice = ich9pciFindBridge(pBus, iBus);
1098	if (pBridgeDevice)
1099	{
1100	AssertPtr( pBridgeDevice->Int.s.pfnBridgeConfigRead);
1101	u32Value = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->pDevIns, iBus, iDevice, u32Address, cb);
1102	}
1103	else
1104	ich9pciNoMem(&u32Value, 4);
1105	}
1106	else
1107	{
1108	/* This is the target bus, pass the read to the device. */
1109	PPCIDEVICE pPciDev = pBus->apDevices[iDevice];
1110	if (pPciDev)
1111	{
1112	u32Value = pPciDev->Int.s.pfnConfigRead(pPciDev, u32Address, cb);
1113	Log(("%s: %s: u32Address=%02x u32Value=%08x cb=%d\n", __FUNCTION__, pPciDev->name, u32Address, u32Value, cb));
1114	}
1115	else
1116	ich9pciNoMem(&u32Value, 4);
1117	}
1118
1119	return u32Value;
1120	}
1121
1122
1123	/**
1124	* Common routine for restoring the config registers of a PCI device.
1125	*
1126	* @param pDev The PCI device.
1127	* @param pbSrcConfig The configuration register values to be loaded.
1128	* @param fIsBridge Whether this is a bridge device or not.
1129	*/
1130	static void pciR3CommonRestoreConfig(PPCIDEVICE pDev, uint8_t const *pbSrcConfig, bool fIsBridge)
1131	{
1132	/*
1133	* This table defines the fields for normal devices and bridge devices, and
1134	* the order in which they need to be restored.
1135	*/
1136	static const struct PciField
1137	{
1138	uint8_t off;
1139	uint8_t cb;
1140	uint8_t fWritable;
1141	uint8_t fBridge;
1142	const char *pszName;
1143	} s_aFields[] =
1144	{
1145	/* off,cb,fW,fB, pszName */
1146	{ VBOX_PCI_VENDOR_ID, 2, 0, 3, "VENDOR_ID" },
1147	{ VBOX_PCI_DEVICE_ID, 2, 0, 3, "DEVICE_ID" },
1148	{ VBOX_PCI_STATUS, 2, 1, 3, "STATUS" },
1149	{ VBOX_PCI_REVISION_ID, 1, 0, 3, "REVISION_ID" },
1150	{ VBOX_PCI_CLASS_PROG, 1, 0, 3, "CLASS_PROG" },
1151	{ VBOX_PCI_CLASS_SUB, 1, 0, 3, "CLASS_SUB" },
1152	{ VBOX_PCI_CLASS_BASE, 1, 0, 3, "CLASS_BASE" },
1153	{ VBOX_PCI_CACHE_LINE_SIZE, 1, 1, 3, "CACHE_LINE_SIZE" },
1154	{ VBOX_PCI_LATENCY_TIMER, 1, 1, 3, "LATENCY_TIMER" },
1155	{ VBOX_PCI_HEADER_TYPE, 1, 0, 3, "HEADER_TYPE" },
1156	{ VBOX_PCI_BIST, 1, 1, 3, "BIST" },
1157	{ VBOX_PCI_BASE_ADDRESS_0, 4, 1, 3, "BASE_ADDRESS_0" },
1158	{ VBOX_PCI_BASE_ADDRESS_1, 4, 1, 3, "BASE_ADDRESS_1" },
1159	{ VBOX_PCI_BASE_ADDRESS_2, 4, 1, 1, "BASE_ADDRESS_2" },
1160	{ VBOX_PCI_PRIMARY_BUS, 1, 1, 2, "PRIMARY_BUS" }, // fWritable = ??
1161	{ VBOX_PCI_SECONDARY_BUS, 1, 1, 2, "SECONDARY_BUS" }, // fWritable = ??
1162	{ VBOX_PCI_SUBORDINATE_BUS, 1, 1, 2, "SUBORDINATE_BUS" }, // fWritable = ??
1163	{ VBOX_PCI_SEC_LATENCY_TIMER, 1, 1, 2, "SEC_LATENCY_TIMER" }, // fWritable = ??
1164	{ VBOX_PCI_BASE_ADDRESS_3, 4, 1, 1, "BASE_ADDRESS_3" },
1165	{ VBOX_PCI_IO_BASE, 1, 1, 2, "IO_BASE" }, // fWritable = ??
1166	{ VBOX_PCI_IO_LIMIT, 1, 1, 2, "IO_LIMIT" }, // fWritable = ??
1167	{ VBOX_PCI_SEC_STATUS, 2, 1, 2, "SEC_STATUS" }, // fWritable = ??
1168	{ VBOX_PCI_BASE_ADDRESS_4, 4, 1, 1, "BASE_ADDRESS_4" },
1169	{ VBOX_PCI_MEMORY_BASE, 2, 1, 2, "MEMORY_BASE" }, // fWritable = ??
1170	{ VBOX_PCI_MEMORY_LIMIT, 2, 1, 2, "MEMORY_LIMIT" }, // fWritable = ??
1171	{ VBOX_PCI_BASE_ADDRESS_5, 4, 1, 1, "BASE_ADDRESS_5" },
1172	{ VBOX_PCI_PREF_MEMORY_BASE, 2, 1, 2, "PREF_MEMORY_BASE" }, // fWritable = ??
1173	{ VBOX_PCI_PREF_MEMORY_LIMIT, 2, 1, 2, "PREF_MEMORY_LIMIT" }, // fWritable = ??
1174	{ VBOX_PCI_CARDBUS_CIS, 4, 1, 1, "CARDBUS_CIS" }, // fWritable = ??
1175	{ VBOX_PCI_PREF_BASE_UPPER32, 4, 1, 2, "PREF_BASE_UPPER32" }, // fWritable = ??
1176	{ VBOX_PCI_SUBSYSTEM_VENDOR_ID, 2, 0, 1, "SUBSYSTEM_VENDOR_ID" },// fWritable = !?
1177	{ VBOX_PCI_PREF_LIMIT_UPPER32, 4, 1, 2, "PREF_LIMIT_UPPER32" },// fWritable = ??
1178	{ VBOX_PCI_SUBSYSTEM_ID, 2, 0, 1, "SUBSYSTEM_ID" }, // fWritable = !?
1179	{ VBOX_PCI_ROM_ADDRESS, 4, 1, 1, "ROM_ADDRESS" }, // fWritable = ?!
1180	{ VBOX_PCI_IO_BASE_UPPER16, 2, 1, 2, "IO_BASE_UPPER16" }, // fWritable = ?!
1181	{ VBOX_PCI_IO_LIMIT_UPPER16, 2, 1, 2, "IO_LIMIT_UPPER16" }, // fWritable = ?!
1182	{ VBOX_PCI_CAPABILITY_LIST, 4, 0, 3, "CAPABILITY_LIST" }, // fWritable = !? cb=!?
1183	{ VBOX_PCI_RESERVED_38, 4, 1, 1, "RESERVED_38" }, // ???
1184	{ VBOX_PCI_ROM_ADDRESS_BR, 4, 1, 2, "ROM_ADDRESS_BR" }, // fWritable = !? cb=!? fBridge=!?
1185	{ VBOX_PCI_INTERRUPT_LINE, 1, 1, 3, "INTERRUPT_LINE" }, // fBridge=??
1186	{ VBOX_PCI_INTERRUPT_PIN, 1, 0, 3, "INTERRUPT_PIN" }, // fBridge=??
1187	{ VBOX_PCI_MIN_GNT, 1, 0, 1, "MIN_GNT" },
1188	{ VBOX_PCI_BRIDGE_CONTROL, 2, 1, 2, "BRIDGE_CONTROL" }, // fWritable = !?
1189	{ VBOX_PCI_MAX_LAT, 1, 0, 1, "MAX_LAT" },
1190	/* The COMMAND register must come last as it requires the ADDRESS
1191	registers to be restored before we pretent to change it from 0 to
1192	whatever value the guest assigned it. */
1193	{ VBOX_PCI_COMMAND, 2, 1, 3, "COMMAND" },
1194	};
1195
1196	#ifdef RT_STRICT
1197	/* Check that we've got full register coverage. */
1198	uint32_t bmDevice[0x40 / 32];
1199	uint32_t bmBridge[0x40 / 32];
1200	RT_ZERO(bmDevice);
1201	RT_ZERO(bmBridge);
1202	for (uint32_t i = 0; i < RT_ELEMENTS(s_aFields); i++)
1203	{
1204	uint8_t off = s_aFields[i].off;
1205	uint8_t cb = s_aFields[i].cb;
1206	uint8_t f = s_aFields[i].fBridge;
1207	while (cb-- > 0)
1208	{
1209	if (f & 1) AssertMsg(!ASMBitTest(bmDevice, off), ("%#x\n", off));
1210	if (f & 2) AssertMsg(!ASMBitTest(bmBridge, off), ("%#x\n", off));
1211	if (f & 1) ASMBitSet(bmDevice, off);
1212	if (f & 2) ASMBitSet(bmBridge, off);
1213	off++;
1214	}
1215	}
1216	for (uint32_t off = 0; off < 0x40; off++)
1217	{
1218	AssertMsg(ASMBitTest(bmDevice, off), ("%#x\n", off));
1219	AssertMsg(ASMBitTest(bmBridge, off), ("%#x\n", off));
1220	}
1221	#endif
1222
1223	/*
1224	* Loop thru the fields covering the 64 bytes of standard registers.
1225	*/
1226	uint8_t const fBridge = fIsBridge ? 2 : 1;
1227	Assert(!pciDevIsPassthrough(pDev));
1228	uint8_t *pbDstConfig = &pDev->config[0];
1229
1230	for (uint32_t i = 0; i < RT_ELEMENTS(s_aFields); i++)
1231	if (s_aFields[i].fBridge & fBridge)
1232	{
1233	uint8_t const off = s_aFields[i].off;
1234	uint8_t const cb = s_aFields[i].cb;
1235	uint32_t u32Src;
1236	uint32_t u32Dst;
1237	switch (cb)
1238	{
1239	case 1:
1240	u32Src = pbSrcConfig[off];
1241	u32Dst = pbDstConfig[off];
1242	break;
1243	case 2:
1244	u32Src = (uint16_t const )&pbSrcConfig[off];
1245	u32Dst = (uint16_t const )&pbDstConfig[off];
1246	break;
1247	case 4:
1248	u32Src = (uint32_t const )&pbSrcConfig[off];
1249	u32Dst = (uint32_t const )&pbDstConfig[off];
1250	break;
1251	default:
1252	AssertFailed();
1253	continue;
1254	}
1255
1256	if ( u32Src != u32Dst
1257	\|\| off == VBOX_PCI_COMMAND)
1258	{
1259	if (u32Src != u32Dst)
1260	{
1261	if (!s_aFields[i].fWritable)
1262	LogRel(("PCI: %8s/%u: %2u-bit field %s: %x -> %x - !READ ONLY!\n",
1263	pDev->name, pDev->pDevIns->iInstance, cb*8, s_aFields[i].pszName, u32Dst, u32Src));
1264	else
1265	LogRel(("PCI: %8s/%u: %2u-bit field %s: %x -> %x\n",
1266	pDev->name, pDev->pDevIns->iInstance, cb*8, s_aFields[i].pszName, u32Dst, u32Src));
1267	}
1268	if (off == VBOX_PCI_COMMAND)
1269	PCIDevSetCommand(pDev, 0); /* For remapping, see ich9pciR3CommonLoadExec. */
1270	pDev->Int.s.pfnConfigWrite(pDev, off, u32Src, cb);
1271	}
1272	}
1273
1274	/*
1275	* The device dependent registers.
1276	*
1277	* We will not use ConfigWrite here as we have no clue about the size
1278	* of the registers, so the device is responsible for correctly
1279	* restoring functionality governed by these registers.
1280	*/
1281	for (uint32_t off = 0x40; off < sizeof(pDev->config); off++)
1282	if (pbDstConfig[off] != pbSrcConfig[off])
1283	{
1284	LogRel(("PCI: %8s/%u: register %02x: %02x -> %02x\n",
1285	pDev->name, pDev->pDevIns->iInstance, off, pbDstConfig[off], pbSrcConfig[off])); /** @todo make this Log() later. */
1286	pbDstConfig[off] = pbSrcConfig[off];
1287	}
1288	}
1289
1290	/**
1291	* Common worker for ich9pciR3LoadExec and ich9pcibridgeR3LoadExec.
1292	*
1293	* @returns VBox status code.
1294	* @param pBus The bus which data is being loaded.
1295	* @param pSSM The saved state handle.
1296	* @param uVersion The data version.
1297	* @param uPass The pass.
1298	*/
1299	static DECLCALLBACK(int) ich9pciR3CommonLoadExec(PICH9PCIBUS pBus, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1300	{
1301	uint32_t u32;
1302	uint32_t i;
1303	int rc;
1304
1305	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
1306
1307	/*
1308	* Iterate thru all the devices and write 0 to the COMMAND register so
1309	* that all the memory is unmapped before we start restoring the saved
1310	* mapping locations.
1311	*
1312	* The register value is restored afterwards so we can do proper
1313	* LogRels in pciR3CommonRestoreConfig.
1314	*/
1315	for (i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
1316	{
1317	PPCIDEVICE pDev = pBus->apDevices[i];
1318	if (pDev)
1319	{
1320	uint16_t u16 = PCIDevGetCommand(pDev);
1321	pDev->Int.s.pfnConfigWrite(pDev, VBOX_PCI_COMMAND, 0, 2);
1322	PCIDevSetCommand(pDev, u16);
1323	Assert(PCIDevGetCommand(pDev) == u16);
1324	}
1325	}
1326
1327	void* pvMsixPage = RTMemTmpAllocZ(0x1000);
1328	/*
1329	* Iterate all the devices.
1330	*/
1331	for (i = 0;; i++)
1332	{
1333	PPCIDEVICE pDev;
1334	PCIDEVICE DevTmp;
1335
1336	/* index / terminator */
1337	rc = SSMR3GetU32(pSSM, &u32);
1338	if (RT_FAILURE(rc))
1339	return rc;
1340	if (u32 == (uint32_t)~0)
1341	break;
1342	if ( u32 >= RT_ELEMENTS(pBus->apDevices)
1343	\|\| u32 < i)
1344	{
1345	AssertMsgFailed(("u32=%#x i=%#x\n", u32, i));
1346	goto out;
1347	}
1348
1349	/* skip forward to the device checking that no new devices are present. */
1350	for (; i < u32; i++)
1351	{
1352	pDev = pBus->apDevices[i];
1353	if (pDev)
1354	{
1355	LogRel(("New device in slot %#x, %s (vendor=%#06x device=%#06x)\n", i, pDev->name,
1356	PCIDevGetVendorId(pDev), PCIDevGetDeviceId(pDev)));
1357	if (SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT)
1358	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("New device in slot %#x, %s (vendor=%#06x device=%#06x)"),
1359	i, pDev->name, PCIDevGetVendorId(pDev), PCIDevGetDeviceId(pDev));
1360	}
1361	}
1362
1363	/* get the data */
1364	DevTmp.Int.s.fFlags = 0;
1365	DevTmp.Int.s.u8MsiCapOffset = 0;
1366	DevTmp.Int.s.u8MsiCapSize = 0;
1367	DevTmp.Int.s.u8MsixCapOffset = 0;
1368	DevTmp.Int.s.u8MsixCapSize = 0;
1369	DevTmp.Int.s.uIrqPinState = ~0; /* Invalid value in case we have an older saved state to force a state change in pciSetIrq. */
1370	SSMR3GetMem(pSSM, DevTmp.config, sizeof(DevTmp.config));
1371
1372	rc = SSMR3GetU32(pSSM, &DevTmp.Int.s.fFlags);
1373	if (RT_FAILURE(rc))
1374	goto out;
1375
1376	rc = SSMR3GetS32(pSSM, &DevTmp.Int.s.uIrqPinState);
1377	if (RT_FAILURE(rc))
1378	goto out;
1379
1380	rc = SSMR3GetU8(pSSM, &DevTmp.Int.s.u8MsiCapOffset);
1381	if (RT_FAILURE(rc))
1382	goto out;
1383
1384	rc = SSMR3GetU8(pSSM, &DevTmp.Int.s.u8MsiCapSize);
1385	if (RT_FAILURE(rc))
1386	goto out;
1387
1388	rc = SSMR3GetU8(pSSM, &DevTmp.Int.s.u8MsixCapOffset);
1389	if (RT_FAILURE(rc))
1390	goto out;
1391
1392	rc = SSMR3GetU8(pSSM, &DevTmp.Int.s.u8MsixCapSize);
1393	if (RT_FAILURE(rc))
1394	goto out;
1395
1396	/* Load MSI-X page state */
1397	if (DevTmp.Int.s.u8MsixCapOffset != 0)
1398	{
1399	Assert(pvMsixPage != NULL);
1400	SSMR3GetMem(pSSM, pvMsixPage, 0x1000);
1401	if (RT_FAILURE(rc))
1402	goto out;
1403	}
1404
1405	/* check that it's still around. */
1406	pDev = pBus->apDevices[i];
1407	if (!pDev)
1408	{
1409	LogRel(("Device in slot %#x has been removed! vendor=%#06x device=%#06x\n", i,
1410	PCIDevGetVendorId(&DevTmp), PCIDevGetDeviceId(&DevTmp)));
1411	if (SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT)
1412	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Device in slot %#x has been removed! vendor=%#06x device=%#06x"),
1413	i, PCIDevGetVendorId(&DevTmp), PCIDevGetDeviceId(&DevTmp));
1414	continue;
1415	}
1416
1417	/* match the vendor id assuming that this will never be changed. */
1418	if ( PCIDevGetVendorId(&DevTmp) != PCIDevGetVendorId(pDev))
1419	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Device in slot %#x (%s) vendor id mismatch! saved=%.4Rhxs current=%.4Rhxs"),
1420	i, pDev->name, PCIDevGetVendorId(&DevTmp), PCIDevGetVendorId(pDev));
1421
1422	/* commit the loaded device config. */
1423	Assert(!pciDevIsPassthrough(pDev));
1424	pciR3CommonRestoreConfig(pDev, &DevTmp.config[0], false ); /** @todo fix bridge fun! */
1425
1426	pDev->Int.s.uIrqPinState = DevTmp.Int.s.uIrqPinState;
1427	pDev->Int.s.u8MsiCapOffset = DevTmp.Int.s.u8MsiCapOffset;
1428	pDev->Int.s.u8MsiCapSize = DevTmp.Int.s.u8MsiCapSize;
1429	pDev->Int.s.u8MsixCapOffset = DevTmp.Int.s.u8MsixCapOffset;
1430	pDev->Int.s.u8MsixCapSize = DevTmp.Int.s.u8MsixCapSize;
1431	if (DevTmp.Int.s.u8MsixCapSize != 0)
1432	{
1433	Assert(pDev->Int.s.pMsixPageR3 != NULL);
1434	memcpy(pDev->Int.s.pMsixPageR3, pvMsixPage, 0x1000);
1435	}
1436	}
1437
1438	out:
1439	if (pvMsixPage)
1440	RTMemTmpFree(pvMsixPage);
1441
1442	return rc;
1443	}
1444
1445	/**
1446	* Loads a saved PCI device state.
1447	*
1448	* @returns VBox status code.
1449	* @param pDevIns Device instance of the PCI Bus.
1450	* @param pPciDev Pointer to PCI device.
1451	* @param pSSM The handle to the saved state.
1452	*/
1453	static DECLCALLBACK(int) ich9pciGenericLoadExec(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PSSMHANDLE pSSM)
1454	{
1455	Assert(!pciDevIsPassthrough(pPciDev));
1456	return SSMR3GetMem(pSSM, &pPciDev->config[0], sizeof(pPciDev->config));
1457	}
1458
1459	static DECLCALLBACK(int) ich9pciR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1460	{
1461	PICH9PCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
1462	PICH9PCIBUS pBus = &pThis->aPciBus;
1463	uint32_t u32;
1464	int rc;
1465
1466	/* We ignore this version as there's no saved state with it anyway */
1467	if (uVersion == VBOX_ICH9PCI_SAVED_STATE_VERSION_NOMSI)
1468	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1469	if (uVersion > VBOX_ICH9PCI_SAVED_STATE_VERSION_MSI)
1470	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1471
1472	/*
1473	* Bus state data.
1474	*/
1475	SSMR3GetU32(pSSM, &pThis->uConfigReg);
1476
1477	/*
1478	* Load IRQ states.
1479	*/
1480	for (int i = 0; i < PCI_APIC_IRQ_PINS; i++)
1481	SSMR3GetU32(pSSM, (uint32_t*)&pThis->uaPciApicIrqLevels[i]);
1482
1483	/* separator */
1484	rc = SSMR3GetU32(pSSM, &u32);
1485	if (RT_FAILURE(rc))
1486	return rc;
1487	if (u32 != (uint32_t)~0)
1488	AssertMsgFailedReturn(("u32=%#x\n", u32), rc);
1489
1490	return ich9pciR3CommonLoadExec(pBus, pSSM, uVersion, uPass);
1491	}
1492
1493	static DECLCALLBACK(int) ich9pcibridgeR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1494	{
1495	PICH9PCIBUS pThis = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
1496	if (uVersion > VBOX_ICH9PCI_SAVED_STATE_VERSION_MSI)
1497	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1498	return ich9pciR3CommonLoadExec(pThis, pSSM, uVersion, uPass);
1499	}
1500
1501	static uint32_t ich9pciConfigRead(PICH9PCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t len)
1502	{
1503	/* Will only work in LSB case */
1504	uint32_t u32Val;
1505	PciAddress aPciAddr;
1506
1507	aPciAddr.iBus = uBus;
1508	aPciAddr.iDeviceFunc = uDevFn;
1509	aPciAddr.iRegister = addr;
1510
1511	/* cannot be rescheduled, as already in R3 */
1512	int rc = ich9pciDataReadAddr(pGlobals, &aPciAddr, len, &u32Val, VERR_INTERNAL_ERROR);
1513	AssertRC(rc);
1514	return u32Val;
1515	}
1516
1517	static void ich9pciConfigWrite(PICH9PCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t val, uint32_t len)
1518	{
1519	PciAddress aPciAddr;
1520
1521	aPciAddr.iBus = uBus;
1522	aPciAddr.iDeviceFunc = uDevFn;
1523	aPciAddr.iRegister = addr;
1524
1525	/* cannot be rescheduled, as already in R3 */
1526	int rc = ich9pciDataWriteAddr(pGlobals, &aPciAddr, val, len, VERR_INTERNAL_ERROR);
1527	AssertRC(rc);
1528	}
1529
1530	static void ich9pciSetRegionAddress(PICH9PCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, int iRegion, uint64_t addr)
1531	{
1532	uint32_t uReg = ich9pciGetRegionReg(iRegion);
1533
1534	/* Read memory type first. */
1535	uint8_t uResourceType = ich9pciConfigRead(pGlobals, uBus, uDevFn, uReg, 1);
1536	/* Read command register. */
1537	uint16_t uCmd = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_COMMAND, 2);
1538
1539	Log(("Set region address: %02x:%02x.%d region %d address=%lld\n",
1540	uBus, uDevFn>>3, uDevFn&7, addr));
1541
1542	if ( iRegion == PCI_ROM_SLOT )
1543	uCmd \|= PCI_COMMAND_MEMACCESS;
1544	else if ((uResourceType & PCI_ADDRESS_SPACE_IO) == PCI_ADDRESS_SPACE_IO)
1545	uCmd \|= PCI_COMMAND_IOACCESS; /* Enable I/O space access. */
1546	else /* The region is MMIO. */
1547	uCmd \|= PCI_COMMAND_MEMACCESS; /* Enable MMIO access. */
1548
1549	bool f64Bit = (uResourceType & PCI_ADDRESS_SPACE_BAR64) != 0;
1550
1551	/* Write address of the device. */
1552	ich9pciConfigWrite(pGlobals, uBus, uDevFn, uReg, (uint32_t)addr, 4);
1553	if (f64Bit)
1554	ich9pciConfigWrite(pGlobals, uBus, uDevFn, uReg + 4, (uint32_t)(addr >> 32), 4);
1555
1556	/* enable memory mappings */
1557	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_COMMAND, uCmd, 2);
1558	}
1559
1560
1561	static void ich9pciBiosInitBridge(PICH9PCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn)
1562	{
1563	Log(("BIOS init bridge: %02x::%02x.%d\n", uBus, uDevFn >> 3, uDevFn & 7));
1564
1565	/*
1566	* The I/O range for the bridge must be aligned to a 4KB boundary.
1567	* This does not change anything really as the access to the device is not going
1568	* through the bridge but we want to be compliant to the spec.
1569	*/
1570	if ((pGlobals->uPciBiosIo % 4096) != 0)
1571	{
1572	pGlobals->uPciBiosIo = RT_ALIGN_32(pGlobals->uPciBiosIo, 4*1024);
1573	Log(("%s: Aligned I/O start address. New address %#x\n", __FUNCTION__, pGlobals->uPciBiosIo));
1574	}
1575	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_IO_BASE, (pGlobals->uPciBiosIo >> 8) & 0xf0, 1);
1576
1577	/* The MMIO range for the bridge must be aligned to a 1MB boundary. */
1578	if ((pGlobals->uPciBiosMmio % (1024 * 1024)) != 0)
1579	{
1580	pGlobals->uPciBiosMmio = RT_ALIGN_32(pGlobals->uPciBiosMmio, 1024*1024);
1581	Log(("%s: Aligned MMIO start address. New address %#x\n", __FUNCTION__, pGlobals->uPciBiosMmio));
1582	}
1583	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_MEMORY_BASE, (pGlobals->uPciBiosMmio >> 16) & UINT32_C(0xffff0), 2);
1584
1585	/* Save values to compare later to. */
1586	uint32_t u32IoAddressBase = pGlobals->uPciBiosIo;
1587	uint32_t u32MMIOAddressBase = pGlobals->uPciBiosMmio;
1588	uint8_t uBridgeBus = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_SECONDARY_BUS, 1);
1589
1590	/* Init devices behind the bridge and possibly other bridges as well. */
1591	for (int iDev = 0; iDev <= 255; iDev++)
1592	ich9pciBiosInitDevice(pGlobals, uBridgeBus, iDev);
1593
1594	/*
1595	* Set I/O limit register. If there is no device with I/O space behind the bridge
1596	* we set a lower value than in the base register.
1597	* The result with a real bridge is that no I/O transactions are passed to the secondary
1598	* interface. Again this doesn't really matter here but we want to be compliant to the spec.
1599	*/
1600	if ((u32IoAddressBase != pGlobals->uPciBiosIo) && ((pGlobals->uPciBiosIo % 4096) != 0))
1601	{
1602	/* The upper boundary must be one byte less than a 4KB boundary. */
1603	pGlobals->uPciBiosIo = RT_ALIGN_32(pGlobals->uPciBiosIo, 4*1024);
1604	}
1605
1606	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_IO_LIMIT, ((pGlobals->uPciBiosIo >> 8) & 0xf0) - 1, 1);
1607
1608	/* Same with the MMIO limit register but with 1MB boundary here. */
1609	if ((u32MMIOAddressBase != pGlobals->uPciBiosMmio) && ((pGlobals->uPciBiosMmio % (1024 * 1024)) != 0))
1610	{
1611	/* The upper boundary must be one byte less than a 1MB boundary. */
1612	pGlobals->uPciBiosMmio = RT_ALIGN_32(pGlobals->uPciBiosMmio, 1024*1024);
1613	}
1614	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_MEMORY_LIMIT, ((pGlobals->uPciBiosMmio >> 16) & UINT32_C(0xfff0)) - 1, 2);
1615
1616	/*
1617	* Set the prefetch base and limit registers. We currently have no device with a prefetchable region
1618	* which may be behind a bridge. That's why it is unconditionally disabled here atm by writing a higher value into
1619	* the base register than in the limit register.
1620	*/
1621	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_MEMORY_BASE, 0xfff0, 2);
1622	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_MEMORY_LIMIT, 0x0, 2);
1623	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_BASE_UPPER32, 0x00, 4);
1624	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_LIMIT_UPPER32, 0x00, 4);
1625	}
1626
1627	static void ich9pciBiosInitDevice(PICH9PCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn)
1628	{
1629	uint16_t uDevClass, uVendor, uDevice;
1630	uint8_t uCmd;
1631
1632	uDevClass = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_CLASS_DEVICE, 2);
1633	uVendor = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_VENDOR_ID, 2);
1634	uDevice = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_DEVICE_ID, 2);
1635
1636	/* If device is present */
1637	if (uVendor == 0xffff)
1638	return;
1639
1640	Log(("BIOS init device: %02x:%02x.%d\n", uBus, uDevFn >> 3, uDevFn & 7));
1641
1642	switch (uDevClass)
1643	{
1644	case 0x0101:
1645	/* IDE controller */
1646	ich9pciConfigWrite(pGlobals, uBus, uDevFn, 0x40, 0x8000, 2); /* enable IDE0 */
1647	ich9pciConfigWrite(pGlobals, uBus, uDevFn, 0x42, 0x8000, 2); /* enable IDE1 */
1648	goto default_map;
1649	break;
1650	case 0x0300:
1651	/* VGA controller */
1652	if (uVendor != 0x80ee)
1653	goto default_map;
1654	/* VGA: map frame buffer to default Bochs VBE address */
1655	ich9pciSetRegionAddress(pGlobals, uBus, uDevFn, 0, 0xE0000000);
1656	/*
1657	* Legacy VGA I/O ports are implicitly decoded by a VGA class device. But
1658	* only the framebuffer (i.e., a memory region) is explicitly registered via
1659	* ich9pciSetRegionAddress, so I/O decoding must be enabled manually.
1660	*/
1661	uCmd = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_COMMAND, 1);
1662	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_COMMAND,
1663	/* Enable I/O space access. */
1664	uCmd \| PCI_COMMAND_IOACCESS,
1665	1);
1666	break;
1667	case 0x0604:
1668	/* PCI-to-PCI bridge. */
1669	AssertMsg(pGlobals->uBus < 255, ("Too many bridges on the bus\n"));
1670	ich9pciBiosInitBridge(pGlobals, uBus, uDevFn);
1671	break;
1672	default:
1673	default_map:
1674	{
1675	/* default memory mappings */
1676	/*
1677	* We ignore ROM region here.
1678	*/
1679	for (int iRegion = 0; iRegion < (PCI_NUM_REGIONS-1); iRegion++)
1680	{
1681	uint32_t u32Address = ich9pciGetRegionReg(iRegion);
1682
1683	/* Calculate size - we write all 1s into the BAR, and then evaluate which bits
1684	are cleared. . */
1685	uint8_t u8ResourceType = ich9pciConfigRead(pGlobals, uBus, uDevFn, u32Address, 1);
1686
1687	bool f64bit = (u8ResourceType & PCI_ADDRESS_SPACE_BAR64) != 0;
1688	bool fIsPio = ((u8ResourceType & PCI_COMMAND_IOACCESS) == PCI_COMMAND_IOACCESS);
1689	uint64_t cbRegSize64 = 0;
1690
1691	if (f64bit)
1692	{
1693	ich9pciConfigWrite(pGlobals, uBus, uDevFn, u32Address, UINT32_C(0xffffffff), 4);
1694	ich9pciConfigWrite(pGlobals, uBus, uDevFn, u32Address+4, UINT32_C(0xffffffff), 4);
1695	cbRegSize64 = ich9pciConfigRead(pGlobals, uBus, uDevFn, u32Address, 4);
1696	cbRegSize64 \|= ((uint64_t)ich9pciConfigRead(pGlobals, uBus, uDevFn, u32Address+4, 4) << 32);
1697	cbRegSize64 &= ~UINT64_C(0x0f);
1698	cbRegSize64 = (~cbRegSize64) + 1;
1699
1700	/* No 64-bit PIO regions possible. */
1701	Assert((u8ResourceType & PCI_COMMAND_IOACCESS) == 0);
1702	}
1703	else
1704	{
1705	uint32_t cbRegSize32;
1706	ich9pciConfigWrite(pGlobals, uBus, uDevFn, u32Address, UINT32_C(0xffffffff), 4);
1707	cbRegSize32 = ich9pciConfigRead(pGlobals, uBus, uDevFn, u32Address, 4);
1708
1709	/* Clear resource information depending on resource type. */
1710	if (fIsPio) /* PIO */
1711	cbRegSize32 &= ~UINT32_C(0x01);
1712	else /* MMIO */
1713	cbRegSize32 &= ~UINT32_C(0x0f);
1714
1715	/*
1716	* Invert all bits and add 1 to get size of the region.
1717	* (From PCI implementation note)
1718	*/
1719	if (fIsPio && (cbRegSize32 & UINT32_C(0xffff0000)) == 0)
1720	cbRegSize32 = (~(cbRegSize32 \| UINT32_C(0xffff0000))) + 1;
1721	else
1722	cbRegSize32 = (~cbRegSize32) + 1;
1723
1724	cbRegSize64 = cbRegSize32;
1725	}
1726	Assert(cbRegSize64 == (uint32_t)cbRegSize64);
1727	Log2(("%s: Size of region %u for device %d on bus %d is %lld\n", __FUNCTION__, iRegion, uDevFn, uBus, cbRegSize64));
1728
1729	if (cbRegSize64)
1730	{
1731	uint32_t cbRegSize32 = (uint32_t)cbRegSize64;
1732	uint32_t* paddr = fIsPio ? &pGlobals->uPciBiosIo : &pGlobals->uPciBiosMmio;
1733	paddr = (paddr + cbRegSize32 - 1) & ~(cbRegSize32 - 1);
1734	Log(("%s: Start address of %s region %u is %#x\n", __FUNCTION__, (fIsPio ? "I/O" : "MMIO"), iRegion, *paddr));
1735	ich9pciSetRegionAddress(pGlobals, uBus, uDevFn, iRegion, *paddr);
1736	*paddr += cbRegSize32;
1737	Log2(("%s: New address is %#x\n", __FUNCTION__, *paddr));
1738
1739	if (f64bit)
1740	iRegion++; /* skip next region */
1741	}
1742	}
1743	break;
1744	}
1745	}
1746
1747	/* map the interrupt */
1748	uint32_t iPin = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_INTERRUPT_PIN, 1);
1749	if (iPin != 0)
1750	{
1751	iPin--;
1752
1753	if (uBus != 0)
1754	{
1755	/* Find bus this device attached to. */
1756	PICH9PCIBUS pBus = &pGlobals->aPciBus;
1757	while (1)
1758	{
1759	PPCIDEVICE pBridge = ich9pciFindBridge(pBus, uBus);
1760	if (!pBridge)
1761	{
1762	Assert(false);
1763	break;
1764	}
1765	if (uBus == PCIDevGetByte(pBridge, VBOX_PCI_SECONDARY_BUS))
1766	{
1767	/* OK, found bus this device attached to. */
1768	break;
1769	}
1770	pBus = PDMINS_2_DATA(pBridge->pDevIns, PICH9PCIBUS);
1771	}
1772
1773	/* We need to go up to the host bus to see which irq pin this
1774	* device will use there. See logic in ich9pcibridgeSetIrq().
1775	*/
1776	while (pBus->iBus != 0)
1777	{
1778	/* Get the pin the device would assert on the bridge. */
1779	iPin = ((pBus->aPciDev.devfn >> 3) + iPin) & 3;
1780	pBus = pBus->aPciDev.Int.s.pBusR3;
1781	};
1782	}
1783
1784	int iIrq = aPciIrqs[ich9pciSlotGetPirq(uBus, uDevFn, iPin)];
1785	Log(("Using pin %d and IRQ %d for device %02x:%02x.%d\n",
1786	iPin, iIrq, uBus, uDevFn>>3, uDevFn&7));
1787	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_INTERRUPT_LINE, iIrq, 1);
1788	}
1789	}
1790
1791	/* Initializes bridges registers used for routing. */
1792	static void ich9pciInitBridgeTopology(PICH9PCIGLOBALS pGlobals, PICH9PCIBUS pBus)
1793	{
1794	PPCIDEVICE pBridgeDev = &pBus->aPciDev;
1795
1796	/* Set only if we are not on the root bus, it has no primary bus attached. */
1797	if (pGlobals->uBus != 0)
1798	{
1799	PCIDevSetByte(pBridgeDev, VBOX_PCI_PRIMARY_BUS, pGlobals->uBus);
1800	PCIDevSetByte(pBridgeDev, VBOX_PCI_SECONDARY_BUS, pGlobals->uBus);
1801	}
1802
1803	pGlobals->uBus++;
1804	for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
1805	{
1806	PPCIDEVICE pBridge = pBus->papBridgesR3[iBridge];
1807	AssertMsg(pBridge && pciDevIsPci2PciBridge(pBridge),
1808	("Device is not a PCI bridge but on the list of PCI bridges\n"));
1809	PICH9PCIBUS pChildBus = PDMINS_2_DATA(pBridge->pDevIns, PICH9PCIBUS);
1810	ich9pciInitBridgeTopology(pGlobals, pChildBus);
1811	}
1812	PCIDevSetByte(pBridgeDev, VBOX_PCI_SUBORDINATE_BUS, pGlobals->uBus);
1813	Log2(("ich9pciInitBridgeTopology: for bus %p: primary=%d secondary=%d subordinate=%d\n",
1814	pBus,
1815	PCIDevGetByte(pBridgeDev, VBOX_PCI_PRIMARY_BUS),
1816	PCIDevGetByte(pBridgeDev, VBOX_PCI_SECONDARY_BUS),
1817	PCIDevGetByte(pBridgeDev, VBOX_PCI_SUBORDINATE_BUS)
1818	));
1819	}
1820
1821
1822	static DECLCALLBACK(int) ich9pciFakePCIBIOS(PPDMDEVINS pDevIns)
1823	{
1824	unsigned i;
1825	uint8_t elcr[2] = {0, 0};
1826	PICH9PCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
1827	PVM pVM = PDMDevHlpGetVM(pDevIns);
1828	Assert(pVM);
1829
1830	/*
1831	* Set the start addresses.
1832	*/
1833	pGlobals->uPciBiosIo = 0xd000;
1834	pGlobals->uPciBiosMmio = UINT32_C(0xf0000000);
1835	pGlobals->uBus = 0;
1836
1837	/*
1838	* Assign bridge topology, for further routing to work.
1839	*/
1840	PICH9PCIBUS pBus = &pGlobals->aPciBus;
1841	ich9pciInitBridgeTopology(pGlobals, pBus);
1842
1843	/*
1844	* Init the devices.
1845	*/
1846	for (i = 0; i < 256; i++)
1847	{
1848	ich9pciBiosInitDevice(pGlobals, 0, i);
1849	}
1850
1851	return VINF_SUCCESS;
1852	}
1853
1854	static DECLCALLBACK(uint32_t) ich9pciConfigReadDev(PCIDevice *aDev, uint32_t u32Address, unsigned len)
1855	{
1856	if ((u32Address + len) > 256 && (u32Address + len) < 4096)
1857	{
1858	LogRel(("Read from extended register %d fallen back to generic code\n",
1859	u32Address));
1860	return 0;
1861	}
1862
1863	AssertMsgReturn(u32Address + len <= 256, ("Read after the end of PCI config space\n"),
1864	0);
1865	if ( pciDevIsMsiCapable(aDev)
1866	&& (u32Address >= aDev->Int.s.u8MsiCapOffset)
1867	&& (u32Address < aDev->Int.s.u8MsiCapOffset + aDev->Int.s.u8MsiCapSize)
1868	)
1869	{
1870	return MsiPciConfigRead(aDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pDevIns), aDev, u32Address, len);
1871	}
1872
1873	if ( pciDevIsMsixCapable(aDev)
1874	&& (u32Address >= aDev->Int.s.u8MsixCapOffset)
1875	&& (u32Address < aDev->Int.s.u8MsixCapOffset + aDev->Int.s.u8MsixCapSize)
1876	)
1877	{
1878	return MsixPciConfigRead(aDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pDevIns), aDev, u32Address, len);
1879	}
1880
1881	AssertMsgReturn(u32Address + len <= 256, ("Read after end of PCI config space\n"),
1882	0);
1883	switch (len)
1884	{
1885	case 1:
1886	return PCIDevGetByte(aDev, u32Address);
1887	case 2:
1888	return PCIDevGetWord(aDev, u32Address);
1889	case 4:
1890	return PCIDevGetDWord(aDev, u32Address);
1891	default:
1892	Assert(false);
1893	return 0;
1894	}
1895	}
1896
1897	DECLINLINE(void) ich9pciWriteBarByte(PCIDevice *aDev, int iRegion, int iOffset, uint8_t u8Val)
1898	{
1899	PCIIORegion * pRegion = &aDev->Int.s.aIORegions[iRegion];
1900	int64_t iRegionSize = pRegion->size;
1901
1902	Log3(("ich9pciWriteBarByte: region=%d off=%d val=%x size=%d\n",
1903	iRegion, iOffset, u8Val, iRegionSize));
1904
1905	if (iOffset > 3)
1906	Assert((aDev->Int.s.aIORegions[iRegion].type & PCI_ADDRESS_SPACE_BAR64) != 0);
1907
1908	/* Check if we're writing to upper part of 64-bit BAR. */
1909	if (aDev->Int.s.aIORegions[iRegion].type == 0xff)
1910	{
1911	ich9pciWriteBarByte(aDev, iRegion-1, iOffset+4, u8Val);
1912	return;
1913	}
1914
1915	/* Region doesn't exist */
1916	if (iRegionSize == 0)
1917	return;
1918
1919	uint32_t uAddr = ich9pciGetRegionReg(iRegion) + iOffset;
1920	/* Region size must be power of two */
1921	Assert((iRegionSize & (iRegionSize - 1)) == 0);
1922	uint8_t uMask = ((iRegionSize - 1) >> (iOffset*8) ) & 0xff;
1923
1924	if (iOffset == 0)
1925	{
1926	uMask \|= (pRegion->type & PCI_ADDRESS_SPACE_IO) ?
1927	(1 << 2) - 1 /* 2 lowest bits for IO region */ :
1928	(1 << 4) - 1 /* 4 lowest bits for memory region, also ROM enable bit for ROM region */;
1929
1930	}
1931
1932	uint8_t u8Old = PCIDevGetByte(aDev, uAddr) & uMask;
1933	u8Val = (u8Old & uMask) \| (u8Val & ~uMask);
1934
1935	Log3(("ich9pciWriteBarByte: was %x writing %x\n", u8Old, u8Val));
1936
1937	PCIDevSetByte(aDev, uAddr, u8Val);
1938	}
1939
1940	/**
1941	* See paragraph 7.5 of PCI Express specification (p. 349) for definition of
1942	* registers and their writability policy.
1943	*/
1944	static DECLCALLBACK(void) ich9pciConfigWriteDev(PCIDevice *aDev, uint32_t u32Address,
1945	uint32_t val, unsigned len)
1946	{
1947	Assert(len <= 4);
1948
1949	if ((u32Address + len) > 256 && (u32Address + len) < 4096)
1950	{
1951	LogRel(("Write to extended register %d fallen back to generic code\n",
1952	u32Address));
1953	return;
1954	}
1955
1956	AssertMsgReturnVoid(u32Address + len <= 256, ("Write after end of PCI config space\n"));
1957
1958	if ( pciDevIsMsiCapable(aDev)
1959	&& (u32Address >= aDev->Int.s.u8MsiCapOffset)
1960	&& (u32Address < aDev->Int.s.u8MsiCapOffset + aDev->Int.s.u8MsiCapSize)
1961	)
1962	{
1963	MsiPciConfigWrite(aDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pDevIns),
1964	aDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pPciHlp),
1965	aDev, u32Address, val, len);
1966	return;
1967	}
1968
1969	if ( pciDevIsMsixCapable(aDev)
1970	&& (u32Address >= aDev->Int.s.u8MsixCapOffset)
1971	&& (u32Address < aDev->Int.s.u8MsixCapOffset + aDev->Int.s.u8MsixCapSize)
1972	)
1973	{
1974	MsixPciConfigWrite(aDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pDevIns),
1975	aDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pPciHlp),
1976	aDev, u32Address, val, len);
1977	return;
1978	}
1979
1980	uint32_t addr = u32Address;
1981	bool fUpdateMappings = false;
1982	bool fP2PBridge = false;
1983	bool fPassthrough = pciDevIsPassthrough(aDev);
1984	uint8_t u8HeaderType = ich9pciGetByte(aDev, VBOX_PCI_HEADER_TYPE);
1985
1986	for (uint32_t i = 0; i < len; i++)
1987	{
1988	bool fWritable = false;
1989	bool fRom = false;
1990	switch (u8HeaderType)
1991	{
1992	case 0x00: /* normal device */
1993	case 0x80: /* multi-function device */
1994	switch (addr)
1995	{
1996	/* Read-only registers */
1997	case VBOX_PCI_VENDOR_ID: case VBOX_PCI_VENDOR_ID+1:
1998	case VBOX_PCI_DEVICE_ID: case VBOX_PCI_DEVICE_ID+1:
1999	case VBOX_PCI_REVISION_ID:
2000	case VBOX_PCI_CLASS_PROG:
2001	case VBOX_PCI_CLASS_SUB:
2002	case VBOX_PCI_CLASS_BASE:
2003	case VBOX_PCI_HEADER_TYPE:
2004	case VBOX_PCI_SUBSYSTEM_VENDOR_ID: case VBOX_PCI_SUBSYSTEM_VENDOR_ID+1:
2005	case VBOX_PCI_SUBSYSTEM_ID: case VBOX_PCI_SUBSYSTEM_ID+1:
2006	case VBOX_PCI_ROM_ADDRESS: case VBOX_PCI_ROM_ADDRESS+1: case VBOX_PCI_ROM_ADDRESS+2: case VBOX_PCI_ROM_ADDRESS+3:
2007	case VBOX_PCI_CAPABILITY_LIST:
2008	case VBOX_PCI_INTERRUPT_PIN:
2009	fWritable = false;
2010	break;
2011	/* Others can be written */
2012	default:
2013	fWritable = true;
2014	break;
2015	}
2016	break;
2017	case 0x01: /* PCI-PCI bridge */
2018	fP2PBridge = true;
2019	switch (addr)
2020	{
2021	/* Read-only registers */
2022	case VBOX_PCI_VENDOR_ID: case VBOX_PCI_VENDOR_ID+1:
2023	case VBOX_PCI_DEVICE_ID: case VBOX_PCI_DEVICE_ID+1:
2024	case VBOX_PCI_REVISION_ID:
2025	case VBOX_PCI_CLASS_PROG:
2026	case VBOX_PCI_CLASS_SUB:
2027	case VBOX_PCI_CLASS_BASE:
2028	case VBOX_PCI_HEADER_TYPE:
2029	case VBOX_PCI_ROM_ADDRESS_BR: case VBOX_PCI_ROM_ADDRESS_BR+1: case VBOX_PCI_ROM_ADDRESS_BR+2: case VBOX_PCI_ROM_ADDRESS_BR+3:
2030	case VBOX_PCI_INTERRUPT_PIN:
2031	fWritable = false;
2032	break;
2033	default:
2034	fWritable = true;
2035	break;
2036	}
2037	break;
2038	default:
2039	AssertMsgFailed(("Unknown header type %x\n", PCIDevGetHeaderType(aDev)));
2040	fWritable = false;
2041	break;
2042	}
2043
2044	uint8_t u8Val = (uint8_t)val;
2045	switch (addr)
2046	{
2047	case VBOX_PCI_COMMAND: /* Command register, bits 0-7. */
2048	fUpdateMappings = true;
2049	goto default_case;
2050	case VBOX_PCI_COMMAND+1: /* Command register, bits 8-15. */
2051	/* don't change reserved bits (11-15) */
2052	u8Val &= UINT32_C(~0xf8);
2053	fUpdateMappings = true;
2054	goto default_case;
2055	case VBOX_PCI_STATUS: /* Status register, bits 0-7. */
2056	/* don't change read-only bits => actually all lower bits are read-only */
2057	u8Val &= UINT32_C(~0xff);
2058	/* status register, low part: clear bits by writing a '1' to the corresponding bit */
2059	aDev->config[addr] &= ~u8Val;
2060	break;
2061	case VBOX_PCI_STATUS+1: /* Status register, bits 8-15. */
2062	/* don't change read-only bits */
2063	u8Val &= UINT32_C(~0x06);
2064	/* status register, high part: clear bits by writing a '1' to the corresponding bit */
2065	aDev->config[addr] &= ~u8Val;
2066	break;
2067	case VBOX_PCI_ROM_ADDRESS: case VBOX_PCI_ROM_ADDRESS +1: case VBOX_PCI_ROM_ADDRESS +2: case VBOX_PCI_ROM_ADDRESS +3:
2068	fRom = true;
2069	case VBOX_PCI_BASE_ADDRESS_0: case VBOX_PCI_BASE_ADDRESS_0+1: case VBOX_PCI_BASE_ADDRESS_0+2: case VBOX_PCI_BASE_ADDRESS_0+3:
2070	case VBOX_PCI_BASE_ADDRESS_1: case VBOX_PCI_BASE_ADDRESS_1+1: case VBOX_PCI_BASE_ADDRESS_1+2: case VBOX_PCI_BASE_ADDRESS_1+3:
2071	case VBOX_PCI_BASE_ADDRESS_2: case VBOX_PCI_BASE_ADDRESS_2+1: case VBOX_PCI_BASE_ADDRESS_2+2: case VBOX_PCI_BASE_ADDRESS_2+3:
2072	case VBOX_PCI_BASE_ADDRESS_3: case VBOX_PCI_BASE_ADDRESS_3+1: case VBOX_PCI_BASE_ADDRESS_3+2: case VBOX_PCI_BASE_ADDRESS_3+3:
2073	case VBOX_PCI_BASE_ADDRESS_4: case VBOX_PCI_BASE_ADDRESS_4+1: case VBOX_PCI_BASE_ADDRESS_4+2: case VBOX_PCI_BASE_ADDRESS_4+3:
2074	case VBOX_PCI_BASE_ADDRESS_5: case VBOX_PCI_BASE_ADDRESS_5+1: case VBOX_PCI_BASE_ADDRESS_5+2: case VBOX_PCI_BASE_ADDRESS_5+3:
2075	{
2076	/* We check that, as same PCI register numbers as BARs may mean different registers for bridges */
2077	if (fP2PBridge)
2078	goto default_case;
2079	else
2080	{
2081	int iRegion = fRom ? VBOX_PCI_ROM_SLOT : (addr - VBOX_PCI_BASE_ADDRESS_0) >> 2;
2082	int iOffset = addr & 0x3;
2083	ich9pciWriteBarByte(aDev, iRegion, iOffset, u8Val);
2084	fUpdateMappings = true;
2085	}
2086	break;
2087	}
2088	default:
2089	default_case:
2090	if (fWritable)
2091	PCIDevSetByte(aDev, addr, u8Val);
2092	}
2093	addr++;
2094	val >>= 8;
2095	}
2096
2097	if (fUpdateMappings)
2098	/* if the command/base address register is modified, we must modify the mappings */
2099	ich9pciUpdateMappings(aDev);
2100	}
2101
2102	static bool assignPosition(PICH9PCIBUS pBus, PPCIDEVICE pPciDev, const char pszName, int iDevFn, PciAddress aPosition)
2103	{
2104	aPosition->iBus = 0;
2105	aPosition->iDeviceFunc = iDevFn;
2106	aPosition->iRegister = 0; /* N/A */
2107
2108	/* Explicit slot request */
2109	if (iDevFn >=0 && iDevFn < (int)RT_ELEMENTS(pBus->apDevices))
2110	return true;
2111
2112	int iStartPos = 0;
2113
2114	/* Otherwise when assigning a slot, we need to make sure all its functions are available */
2115	for (int iPos = iStartPos; iPos < (int)RT_ELEMENTS(pBus->apDevices); iPos += 8)
2116	{
2117	if ( !pBus->apDevices[iPos]
2118	&& !pBus->apDevices[iPos + 1]
2119	&& !pBus->apDevices[iPos + 2]
2120	&& !pBus->apDevices[iPos + 3]
2121	&& !pBus->apDevices[iPos + 4]
2122	&& !pBus->apDevices[iPos + 5]
2123	&& !pBus->apDevices[iPos + 6]
2124	&& !pBus->apDevices[iPos + 7])
2125	{
2126	pciDevClearRequestedDevfunc(pPciDev);
2127	aPosition->iDeviceFunc = iPos;
2128	return true;
2129	}
2130	}
2131
2132	return false;
2133	}
2134
2135	static bool hasHardAssignedDevsInSlot(PICH9PCIBUS pBus, int iSlot)
2136	{
2137	PCIDevice** aSlot = &pBus->apDevices[iSlot << 3];
2138
2139	return (aSlot[0] && pciDevIsRequestedDevfunc(aSlot[0]))
2140	\|\| (aSlot[1] && pciDevIsRequestedDevfunc(aSlot[1]))
2141	\|\| (aSlot[2] && pciDevIsRequestedDevfunc(aSlot[2]))
2142	\|\| (aSlot[3] && pciDevIsRequestedDevfunc(aSlot[3]))
2143	\|\| (aSlot[4] && pciDevIsRequestedDevfunc(aSlot[4]))
2144	\|\| (aSlot[5] && pciDevIsRequestedDevfunc(aSlot[5]))
2145	\|\| (aSlot[6] && pciDevIsRequestedDevfunc(aSlot[6]))
2146	\|\| (aSlot[7] && pciDevIsRequestedDevfunc(aSlot[7]))
2147	;
2148	}
2149
2150	static int ich9pciRegisterInternal(PICH9PCIBUS pBus, int iDev, PPCIDEVICE pPciDev, const char *pszName)
2151	{
2152	PciAddress aPosition = {0, 0, 0};
2153
2154	/*
2155	* Find device position
2156	*/
2157	if (!assignPosition(pBus, pPciDev, pszName, iDev, &aPosition))
2158	{
2159	AssertMsgFailed(("Couldn't asssign position!\n"));
2160	return VERR_PDM_TOO_PCI_MANY_DEVICES;
2161	}
2162
2163	AssertMsgReturn(aPosition.iBus == 0,
2164	("Assigning behind the bridge not implemented yet\n"),
2165	VERR_PDM_TOO_PCI_MANY_DEVICES);
2166
2167
2168	iDev = aPosition.iDeviceFunc;
2169	/*
2170	* Check if we can really take this slot, possibly by relocating
2171	* its current habitant, if it wasn't hard assigned too.
2172	*/
2173	if (pciDevIsRequestedDevfunc(pPciDev) &&
2174	pBus->apDevices[iDev] &&
2175	pciDevIsRequestedDevfunc(pBus->apDevices[iDev]))
2176	{
2177	AssertReleaseMsgFailed(("Configuration error:'%s' and '%s' are both configured as device %d\n",
2178	pszName, pBus->apDevices[iDev]->name, iDev));
2179	return VERR_INTERNAL_ERROR;
2180	}
2181
2182	if (pBus->apDevices[iDev])
2183	{
2184	/* if we got here, we shall (and usually can) relocate the device */
2185	bool assigned = assignPosition(pBus, pBus->apDevices[iDev], pBus->apDevices[iDev]->name, -1, &aPosition);
2186	AssertMsgReturn(aPosition.iBus == 0,
2187	("Assigning behind the bridge not implemented yet\n"),
2188	VERR_PDM_TOO_PCI_MANY_DEVICES);
2189	int iRelDev = aPosition.iDeviceFunc;
2190	if (!assigned \|\| iRelDev == iDev)
2191	{
2192	AssertMsgFailed(("Couldn't find free spot!\n"));
2193	return VERR_PDM_TOO_PCI_MANY_DEVICES;
2194	}
2195	/* Copy device function by function to its new position */
2196	for (int i = 0; i < 8; i++)
2197	{
2198	if (!pBus->apDevices[iDev + i])
2199	continue;
2200	Log(("PCI: relocating '%s' from slot %#x to %#x\n", pBus->apDevices[iDev + i]->name, iDev + i, iRelDev + i));
2201	pBus->apDevices[iRelDev + i] = pBus->apDevices[iDev + i];
2202	pBus->apDevices[iRelDev + i]->devfn = iRelDev + i;
2203	pBus->apDevices[iDev + i] = NULL;
2204	}
2205	}
2206
2207	/*
2208	* Fill in device information.
2209	*/
2210	pPciDev->devfn = iDev;
2211	pPciDev->name = pszName;
2212	pPciDev->Int.s.pBusR3 = pBus;
2213	pPciDev->Int.s.pBusR0 = MMHyperR3ToR0(PDMDevHlpGetVM(pBus->CTX_SUFF(pDevIns)), pBus);
2214	pPciDev->Int.s.pBusRC = MMHyperR3ToRC(PDMDevHlpGetVM(pBus->CTX_SUFF(pDevIns)), pBus);
2215	pPciDev->Int.s.pfnConfigRead = ich9pciConfigReadDev;
2216	pPciDev->Int.s.pfnConfigWrite = ich9pciConfigWriteDev;
2217	pBus->apDevices[iDev] = pPciDev;
2218	if (pciDevIsPci2PciBridge(pPciDev))
2219	{
2220	AssertMsg(pBus->cBridges < RT_ELEMENTS(pBus->apDevices), ("Number of bridges exceeds the number of possible devices on the bus\n"));
2221	AssertMsg(pPciDev->Int.s.pfnBridgeConfigRead && pPciDev->Int.s.pfnBridgeConfigWrite,
2222	("device is a bridge but does not implement read/write functions\n"));
2223	Log2(("Setting bridge %d on bus %p\n", pBus->cBridges, pBus));
2224	pBus->papBridgesR3[pBus->cBridges] = pPciDev;
2225	pBus->cBridges++;
2226	}
2227
2228	Log(("PCI: Registered device %d function %d on bus %d (%#x) '%s'.\n",
2229	iDev >> 3, iDev & 7, pBus->iBus, 0x80000000 \| (iDev << 8), pszName));
2230
2231	return VINF_SUCCESS;
2232	}
2233
2234	static void printIndent(PCDBGFINFOHLP pHlp, int iIndent)
2235	{
2236	for (int i = 0; i < iIndent; i++)
2237	{
2238	pHlp->pfnPrintf(pHlp, " ");
2239	}
2240	}
2241
2242	static void ich9pciBusInfo(PICH9PCIBUS pBus, PCDBGFINFOHLP pHlp, int iIndent, bool fRegisters)
2243	{
2244	for (uint32_t iDev = 0; iDev < RT_ELEMENTS(pBus->apDevices); iDev++)
2245	{
2246	PPCIDEVICE pPciDev = pBus->apDevices[iDev];
2247	if (pPciDev != NULL)
2248	{
2249	printIndent(pHlp, iIndent);
2250
2251	/*
2252	* For passthrough devices MSI/MSI-X mostly reflects the way interrupts delivered to the guest,
2253	* as host driver handles real devices interrupts.
2254	*/
2255	pHlp->pfnPrintf(pHlp, "%02x:%02x:%02x %s%s: %04x-%04x%s%s",
2256	pBus->iBus, (iDev >> 3) & 0xff, iDev & 0x7,
2257	pPciDev->name,
2258	pciDevIsPassthrough(pPciDev) ? " (PASSTHROUGH)" : "",
2259	ich9pciGetWord(pPciDev, VBOX_PCI_VENDOR_ID), ich9pciGetWord(pPciDev, VBOX_PCI_DEVICE_ID),
2260	pciDevIsMsiCapable(pPciDev) ? " MSI" : "",
2261	pciDevIsMsixCapable(pPciDev) ? " MSI-X" : ""
2262	);
2263	if (ich9pciGetByte(pPciDev, VBOX_PCI_INTERRUPT_PIN) != 0)
2264	pHlp->pfnPrintf(pHlp, " IRQ%d", ich9pciGetByte(pPciDev, VBOX_PCI_INTERRUPT_LINE));
2265
2266	pHlp->pfnPrintf(pHlp, "\n");
2267
2268	int iCmd = ich9pciGetWord(pPciDev, VBOX_PCI_COMMAND);
2269	if ((iCmd & (VBOX_PCI_COMMAND_IO \| VBOX_PCI_COMMAND_MEMORY)) != 0)
2270	{
2271	for (int iRegion = 0; iRegion < PCI_NUM_REGIONS; iRegion++)
2272	{
2273	PCIIORegion* pRegion = &pPciDev->Int.s.aIORegions[iRegion];
2274	int32_t iRegionSize = pRegion->size;
2275
2276	if (iRegionSize == 0)
2277	continue;
2278
2279	uint32_t u32Addr = ich9pciGetDWord(pPciDev, ich9pciGetRegionReg(iRegion));
2280	const char * pszDesc;
2281	char szDescBuf[128];
2282
2283	bool f64Bit = (pRegion->type & PCI_ADDRESS_SPACE_BAR64);
2284	if (pRegion->type & PCI_ADDRESS_SPACE_IO)
2285	{
2286	pszDesc = "IO";
2287	u32Addr &= ~0x3;
2288	}
2289	else
2290	{
2291	RTStrPrintf(szDescBuf, sizeof(szDescBuf), "MMIO%s%s",
2292	f64Bit ? "64" : "32",
2293	(pRegion->type & PCI_ADDRESS_SPACE_MEM_PREFETCH) ? " PREFETCH" : "");
2294	pszDesc = szDescBuf;
2295	u32Addr &= ~0xf;
2296	}
2297
2298	printIndent(pHlp, iIndent + 2);
2299	pHlp->pfnPrintf(pHlp, " %s region #%d: %x..%x\n",
2300	pszDesc, iRegion, u32Addr, u32Addr+iRegionSize);
2301	if (f64Bit)
2302	iRegion++;
2303	}
2304	}
2305
2306	if (fRegisters)
2307	{
2308	printIndent(pHlp, iIndent + 2);
2309	pHlp->pfnPrintf(pHlp, " PCI registers:\n");
2310	for (int iReg = 0; iReg < 0x100; )
2311	{
2312	int iPerLine = 0x10;
2313	Assert (0x100 % iPerLine == 0);
2314	printIndent(pHlp, iIndent + 3);
2315
2316	while (iPerLine-- > 0)
2317	{
2318	pHlp->pfnPrintf(pHlp, "%02x ", ich9pciGetByte(pPciDev, iReg++));
2319	}
2320	pHlp->pfnPrintf(pHlp, "\n");
2321	}
2322	}
2323	}
2324	}
2325
2326	if (pBus->cBridges > 0)
2327	{
2328	printIndent(pHlp, iIndent);
2329	pHlp->pfnPrintf(pHlp, "Registered %d bridges, subordinate buses info follows\n", pBus->cBridges);
2330	for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
2331	{
2332	PICH9PCIBUS pBusSub = PDMINS_2_DATA(pBus->papBridgesR3[iBridge]->pDevIns, PICH9PCIBUS);
2333	ich9pciBusInfo(pBusSub, pHlp, iIndent + 1, fRegisters);
2334	}
2335	}
2336	}
2337
2338	/**
2339	* Info handler, device version.
2340	*
2341	* @param pDevIns Device instance which registered the info.
2342	* @param pHlp Callback functions for doing output.
2343	* @param pszArgs Argument string. Optional and specific to the handler.
2344	*/
2345	static DECLCALLBACK(void) ich9pciInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
2346	{
2347	PICH9PCIBUS pBus = DEVINS_2_PCIBUS(pDevIns);
2348
2349	if (pszArgs == NULL \|\| !strcmp(pszArgs, "basic"))
2350	{
2351	ich9pciBusInfo(pBus, pHlp, 0, false);
2352	}
2353	else if (!strcmp(pszArgs, "verbose"))
2354	{
2355	ich9pciBusInfo(pBus, pHlp, 0, true);
2356	}
2357	else
2358	{
2359	pHlp->pfnPrintf(pHlp, "Invalid argument. Recognized arguments are 'basic', 'verbose'.\n");
2360	}
2361	}
2362
2363
2364	static DECLCALLBACK(int) ich9pciConstruct(PPDMDEVINS pDevIns,
2365	int iInstance,
2366	PCFGMNODE pCfg)
2367	{
2368	Assert(iInstance == 0);
2369	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
2370
2371	/*
2372	* Validate and read configuration.
2373	*/
2374	if (!CFGMR3AreValuesValid(pCfg,
2375	"IOAPIC\0"
2376	"GCEnabled\0"
2377	"R0Enabled\0"
2378	"McfgBase\0"
2379	"McfgLength\0"
2380	))
2381	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
2382
2383	/* query whether we got an IOAPIC */
2384	bool fUseIoApic;
2385	int rc = CFGMR3QueryBoolDef(pCfg, "IOAPIC", &fUseIoApic, false);
2386	if (RT_FAILURE(rc))
2387	return PDMDEV_SET_ERROR(pDevIns, rc,
2388	N_("Configuration error: Failed to query boolean value \"IOAPIC\""));
2389
2390	/* check if RC code is enabled. */
2391	bool fGCEnabled;
2392	rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
2393	if (RT_FAILURE(rc))
2394	return PDMDEV_SET_ERROR(pDevIns, rc,
2395	N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
2396	/* check if R0 code is enabled. */
2397	bool fR0Enabled;
2398	rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
2399	if (RT_FAILURE(rc))
2400	return PDMDEV_SET_ERROR(pDevIns, rc,
2401	N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
2402
2403	Log(("PCI: fUseIoApic=%RTbool fGCEnabled=%RTbool fR0Enabled=%RTbool\n", fUseIoApic, fGCEnabled, fR0Enabled));
2404
2405	/*
2406	* Init data.
2407	*/
2408	PICH9PCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
2409	PICH9PCIBUS pBus = &pGlobals->aPciBus;
2410	/* Zero out everything */
2411	memset(pGlobals, 0, sizeof(*pGlobals));
2412	/* And fill values */
2413	if (!fUseIoApic)
2414	return PDMDEV_SET_ERROR(pDevIns, rc,
2415	N_("Must use IO-APIC with ICH9 chipset"));
2416	rc = CFGMR3QueryU64Def(pCfg, "McfgBase", &pGlobals->u64PciConfigMMioAddress, 0);
2417	if (RT_FAILURE(rc))
2418	return PDMDEV_SET_ERROR(pDevIns, rc,
2419	N_("Configuration error: Failed to read \"McfgBase\""));
2420	rc = CFGMR3QueryU64Def(pCfg, "McfgLength", &pGlobals->u64PciConfigMMioLength, 0);
2421	if (RT_FAILURE(rc))
2422	return PDMDEV_SET_ERROR(pDevIns, rc,
2423	N_("Configuration error: Failed to read \"McfgLength\""));
2424
2425	pGlobals->pDevInsR3 = pDevIns;
2426	pGlobals->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2427	pGlobals->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2428
2429	pGlobals->aPciBus.pDevInsR3 = pDevIns;
2430	pGlobals->aPciBus.pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2431	pGlobals->aPciBus.pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2432	pGlobals->aPciBus.papBridgesR3 = (PPCIDEVICE )PDMDevHlpMMHeapAllocZ(pDevIns, sizeof(PPCIDEVICE) RT_ELEMENTS(pGlobals->aPciBus.apDevices));
2433
2434	/*
2435	* Register bus
2436	*/
2437	PDMPCIBUSREG PciBusReg;
2438	PciBusReg.u32Version = PDM_PCIBUSREG_VERSION;
2439	PciBusReg.pfnRegisterR3 = ich9pciRegister;
2440	PciBusReg.pfnRegisterMsiR3 = ich9pciRegisterMsi;
2441	PciBusReg.pfnIORegionRegisterR3 = ich9pciIORegionRegister;
2442	PciBusReg.pfnSetConfigCallbacksR3 = ich9pciSetConfigCallbacks;
2443	PciBusReg.pfnSetIrqR3 = ich9pciSetIrq;
2444	PciBusReg.pfnSaveExecR3 = ich9pciGenericSaveExec;
2445	PciBusReg.pfnLoadExecR3 = ich9pciGenericLoadExec;
2446	PciBusReg.pfnFakePCIBIOSR3 = ich9pciFakePCIBIOS;
2447	PciBusReg.pszSetIrqRC = fGCEnabled ? "ich9pciSetIrq" : NULL;
2448	PciBusReg.pszSetIrqR0 = fR0Enabled ? "ich9pciSetIrq" : NULL;
2449	rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBus->pPciHlpR3);
2450	if (RT_FAILURE(rc))
2451	return PDMDEV_SET_ERROR(pDevIns, rc,
2452	N_("Failed to register ourselves as a PCI Bus"));
2453	if (pBus->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
2454	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
2455	N_("PCI helper version mismatch; got %#x expected %#x"),
2456	pBus->pPciHlpR3->u32Version, PDM_PCIHLPR3_VERSION);
2457
2458	pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
2459	pBus->pPciHlpR0 = pBus->pPciHlpR3->pfnGetR0Helpers(pDevIns);
2460
2461	/*
2462	* Fill in PCI configs and add them to the bus.
2463	*/
2464	/** @todo: Disabled for now because this causes error messages with Linux guests.
2465	* The guest loads the x38_edac device which tries to map a memory region
2466	* using an address given at place 0x48 - 0x4f in the PCi config space.
2467	* This fails. because we don't register such a region.
2468	*/
2469	#if 0
2470	/* Host bridge device */
2471	PCIDevSetVendorId( &pBus->aPciDev, 0x8086); /* Intel */
2472	PCIDevSetDeviceId( &pBus->aPciDev, 0x29e0); /* Desktop */
2473	PCIDevSetRevisionId(&pBus->aPciDev, 0x01); /* rev. 01 */
2474	PCIDevSetClassBase( &pBus->aPciDev, 0x06); /* bridge */
2475	PCIDevSetClassSub( &pBus->aPciDev, 0x00); /* Host/PCI bridge */
2476	PCIDevSetClassProg( &pBus->aPciDev, 0x00); /* Host/PCI bridge */
2477	PCIDevSetHeaderType(&pBus->aPciDev, 0x00); /* bridge */
2478	PCIDevSetWord(&pBus->aPciDev, VBOX_PCI_SEC_STATUS, 0x0280); /* secondary status */
2479
2480	pBus->aPciDev.pDevIns = pDevIns;
2481	/* We register Host<->PCI controller on the bus */
2482	ich9pciRegisterInternal(pBus, 0, &pBus->aPciDev, "dram");
2483	#endif
2484
2485	/*
2486	* Register I/O ports and save state.
2487	*/
2488	rc = PDMDevHlpIOPortRegister(pDevIns, 0x0cf8, 1, NULL, ich9pciIOPortAddressWrite, ich9pciIOPortAddressRead, NULL, NULL, "ICH9 (PCI)");
2489	if (RT_FAILURE(rc))
2490	return rc;
2491	rc = PDMDevHlpIOPortRegister(pDevIns, 0x0cfc, 4, NULL, ich9pciIOPortDataWrite, ich9pciIOPortDataRead, NULL, NULL, "ICH9 (PCI)");
2492	if (RT_FAILURE(rc))
2493	return rc;
2494	if (fGCEnabled)
2495	{
2496	rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x0cf8, 1, NIL_RTGCPTR, "ich9pciIOPortAddressWrite", "ich9pciIOPortAddressRead", NULL, NULL, "ICH9 (PCI)");
2497	if (RT_FAILURE(rc))
2498	return rc;
2499	rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x0cfc, 4, NIL_RTGCPTR, "ich9pciIOPortDataWrite", "ich9pciIOPortDataRead", NULL, NULL, "ICH9 (PCI)");
2500	if (RT_FAILURE(rc))
2501	return rc;
2502	}
2503	if (fR0Enabled)
2504	{
2505	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x0cf8, 1, NIL_RTR0PTR, "ich9pciIOPortAddressWrite", "ich9pciIOPortAddressRead", NULL, NULL, "ICH9 (PCI)");
2506	if (RT_FAILURE(rc))
2507	return rc;
2508	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x0cfc, 4, NIL_RTR0PTR, "ich9pciIOPortDataWrite", "ich9pciIOPortDataRead", NULL, NULL, "ICH9 (PCI)");
2509	if (RT_FAILURE(rc))
2510	return rc;
2511	}
2512
2513	if (pGlobals->u64PciConfigMMioAddress != 0)
2514	{
2515	rc = PDMDevHlpMMIORegister(pDevIns,
2516	pGlobals->u64PciConfigMMioAddress,
2517	pGlobals->u64PciConfigMMioLength,
2518	0,
2519	ich9pciMcfgMMIOWrite,
2520	ich9pciMcfgMMIORead,
2521	NULL /* fill */,
2522	"MCFG ranges");
2523	if (RT_FAILURE(rc))
2524	{
2525	AssertMsgRC(rc, ("Cannot register MCFG MMIO: %Rrc\n", rc));
2526	return rc;
2527	}
2528
2529	if (fGCEnabled)
2530	{
2531
2532	rc = PDMDevHlpMMIORegisterRC(pDevIns,
2533	pGlobals->u64PciConfigMMioAddress,
2534	pGlobals->u64PciConfigMMioLength,
2535	0,
2536	"ich9pciMcfgMMIOWrite",
2537	"ich9pciMcfgMMIORead",
2538	NULL /* fill */);
2539	if (RT_FAILURE(rc))
2540	{
2541	AssertMsgRC(rc, ("Cannot register MCFG MMIO (GC): %Rrc\n", rc));
2542	return rc;
2543	}
2544	}
2545
2546
2547	if (fR0Enabled)
2548	{
2549
2550	rc = PDMDevHlpMMIORegisterR0(pDevIns,
2551	pGlobals->u64PciConfigMMioAddress,
2552	pGlobals->u64PciConfigMMioLength,
2553	0,
2554	"ich9pciMcfgMMIOWrite",
2555	"ich9pciMcfgMMIORead",
2556	NULL /* fill */);
2557	if (RT_FAILURE(rc))
2558	{
2559	AssertMsgRC(rc, ("Cannot register MCFG MMIO (R0): %Rrc\n", rc));
2560	return rc;
2561	}
2562	}
2563	}
2564
2565	rc = PDMDevHlpSSMRegisterEx(pDevIns, VBOX_ICH9PCI_SAVED_STATE_VERSION_CURRENT,
2566	sizeof(pBus) + 16128, "pgm",
2567	NULL, NULL, NULL,
2568	NULL, ich9pciR3SaveExec, NULL,
2569	NULL, ich9pciR3LoadExec, NULL);
2570	if (RT_FAILURE(rc))
2571	return rc;
2572
2573
2574	/** @todo: other chipset devices shall be registered too */
2575
2576	PDMDevHlpDBGFInfoRegister(pDevIns, "pci", "Display PCI bus status. (no arguments)", ich9pciInfo);
2577
2578	return VINF_SUCCESS;
2579	}
2580
2581	static void ich9pciResetDevice(PPCIDEVICE pDev)
2582	{
2583	PICH9PCIBUS pBus = pDev->Int.s.CTX_SUFF(pBus);
2584	int rc;
2585
2586	/* Clear regions */
2587	for (int iRegion = 0; iRegion < PCI_NUM_REGIONS; iRegion++)
2588	{
2589	PCIIORegion* pRegion = &pDev->Int.s.aIORegions[iRegion];
2590	if (pRegion->size == 0)
2591	continue;
2592
2593	ich9pciUnmapRegion(pDev, iRegion);
2594	}
2595
2596	if (pciDevIsPassthrough(pDev))
2597	{
2598	// no reset handler - we can do what we need in PDM reset handler
2599	// @todo: is it correct?
2600	}
2601	else
2602	{
2603	PCIDevSetCommand(pDev,
2604	PCIDevGetCommand(pDev)
2605	&
2606	~(VBOX_PCI_COMMAND_IO \|
2607	VBOX_PCI_COMMAND_MEMORY \|
2608	VBOX_PCI_COMMAND_MASTER));
2609
2610	/* Bridge device reset handlers processed later */
2611	if (!pciDevIsPci2PciBridge(pDev))
2612	{
2613	PCIDevSetByte(pDev, VBOX_PCI_CACHE_LINE_SIZE, 0x0);
2614	PCIDevSetInterruptLine(pDev, 0x0);
2615	}
2616	}
2617	}
2618
2619
2620	/**
2621	* @copydoc FNPDMDEVRESET
2622	*/
2623	static DECLCALLBACK(void) ich9pciReset(PPDMDEVINS pDevIns)
2624	{
2625	PICH9PCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
2626	PICH9PCIBUS pBus = &pGlobals->aPciBus;
2627
2628	/* PCI-specific reset for each device. */
2629	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
2630	{
2631	if (pBus->apDevices[i])
2632	ich9pciResetDevice(pBus->apDevices[i]);
2633	}
2634
2635	for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
2636	{
2637	if (pBus->papBridgesR3[iBridge])
2638	ich9pcibridgeReset(pBus->papBridgesR3[iBridge]->pDevIns);
2639	}
2640
2641	ich9pciFakePCIBIOS(pDevIns);
2642	}
2643
2644	static void ich9pciRelocateDevice(PPCIDEVICE pDev, RTGCINTPTR offDelta)
2645	{
2646	if (pDev)
2647	{
2648	pDev->Int.s.pBusRC += offDelta;
2649	if (pDev->Int.s.pMsixPageRC)
2650	pDev->Int.s.pMsixPageRC += offDelta;
2651	}
2652	}
2653
2654	/**
2655	* @copydoc FNPDMDEVRELOCATE
2656	*/
2657	static DECLCALLBACK(void) ich9pciRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
2658	{
2659	PICH9PCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
2660	PICH9PCIBUS pBus = &pGlobals->aPciBus;
2661	pGlobals->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2662
2663	pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
2664	pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2665
2666	/* Relocate RC pointers for the attached pci devices. */
2667	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
2668	ich9pciRelocateDevice(pBus->apDevices[i], offDelta);
2669
2670	}
2671
2672	/**
2673	* @interface_method_impl{PDMDEVREG,pfnConstruct}
2674	*/
2675	static DECLCALLBACK(int) ich9pcibridgeConstruct(PPDMDEVINS pDevIns,
2676	int iInstance,
2677	PCFGMNODE pCfg)
2678	{
2679	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
2680
2681	/*
2682	* Validate and read configuration.
2683	*/
2684	if (!CFGMR3AreValuesValid(pCfg, "GCEnabled\0" "R0Enabled\0"))
2685	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
2686
2687	/* check if RC code is enabled. */
2688	bool fGCEnabled;
2689	int rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
2690	if (RT_FAILURE(rc))
2691	return PDMDEV_SET_ERROR(pDevIns, rc,
2692	N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
2693
2694	/* check if R0 code is enabled. */
2695	bool fR0Enabled;
2696	rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
2697	if (RT_FAILURE(rc))
2698	return PDMDEV_SET_ERROR(pDevIns, rc,
2699	N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
2700	Log(("PCI: fGCEnabled=%RTbool fR0Enabled=%RTbool\n", fGCEnabled, fR0Enabled));
2701
2702	/*
2703	* Init data and register the PCI bus.
2704	*/
2705	PICH9PCIBUS pBus = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
2706	pBus->pDevInsR3 = pDevIns;
2707	pBus->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2708	pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2709	pBus->papBridgesR3 = (PPCIDEVICE )PDMDevHlpMMHeapAllocZ(pDevIns, sizeof(PPCIDEVICE) RT_ELEMENTS(pBus->apDevices));
2710
2711	PDMPCIBUSREG PciBusReg;
2712	PciBusReg.u32Version = PDM_PCIBUSREG_VERSION;
2713	PciBusReg.pfnRegisterR3 = ich9pcibridgeRegister;
2714	PciBusReg.pfnRegisterMsiR3 = ich9pciRegisterMsi;
2715	PciBusReg.pfnIORegionRegisterR3 = ich9pciIORegionRegister;
2716	PciBusReg.pfnSetConfigCallbacksR3 = ich9pciSetConfigCallbacks;
2717	PciBusReg.pfnSetIrqR3 = ich9pcibridgeSetIrq;
2718	PciBusReg.pfnSaveExecR3 = ich9pciGenericSaveExec;
2719	PciBusReg.pfnLoadExecR3 = ich9pciGenericLoadExec;
2720	PciBusReg.pfnFakePCIBIOSR3 = NULL; /* Only needed for the first bus. */
2721	PciBusReg.pszSetIrqRC = fGCEnabled ? "ich9pcibridgeSetIrq" : NULL;
2722	PciBusReg.pszSetIrqR0 = fR0Enabled ? "ich9pcibridgeSetIrq" : NULL;
2723	rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBus->pPciHlpR3);
2724	if (RT_FAILURE(rc))
2725	return PDMDEV_SET_ERROR(pDevIns, rc,
2726	N_("Failed to register ourselves as a PCI Bus"));
2727	if (pBus->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
2728	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
2729	N_("PCI helper version mismatch; got %#x expected %#x"),
2730	pBus->pPciHlpR3->u32Version, PDM_PCIHLPR3_VERSION);
2731
2732	pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
2733	pBus->pPciHlpR0 = pBus->pPciHlpR3->pfnGetR0Helpers(pDevIns);
2734
2735	/*
2736	* Fill in PCI configs and add them to the bus.
2737	*/
2738	PCIDevSetVendorId( &pBus->aPciDev, 0x8086); /* Intel */
2739	PCIDevSetDeviceId( &pBus->aPciDev, 0x2448); /* 82801 Mobile PCI bridge. */
2740	PCIDevSetRevisionId(&pBus->aPciDev, 0xf2);
2741	PCIDevSetClassSub( &pBus->aPciDev, 0x04); /* pci2pci */
2742	PCIDevSetClassBase( &pBus->aPciDev, 0x06); /* PCI_bridge */
2743	PCIDevSetClassProg( &pBus->aPciDev, 0x01); /* Supports subtractive decoding. */
2744	PCIDevSetHeaderType(&pBus->aPciDev, 0x01); /* Single function device which adheres to the PCI-to-PCI bridge spec. */
2745	PCIDevSetCommand( &pBus->aPciDev, 0x00);
2746	PCIDevSetStatus( &pBus->aPciDev, 0x20); /* 66MHz Capable. */
2747	PCIDevSetInterruptLine(&pBus->aPciDev, 0x00); /* This device does not assert interrupts. */
2748
2749	/*
2750	* This device does not generate interrupts. Interrupt delivery from
2751	* devices attached to the bus is unaffected.
2752	*/
2753	PCIDevSetInterruptPin (&pBus->aPciDev, 0x00);
2754
2755	pBus->aPciDev.pDevIns = pDevIns;
2756
2757	/* Bridge-specific data */
2758	pciDevSetPci2PciBridge(&pBus->aPciDev);
2759	pBus->aPciDev.Int.s.pfnBridgeConfigRead = ich9pcibridgeConfigRead;
2760	pBus->aPciDev.Int.s.pfnBridgeConfigWrite = ich9pcibridgeConfigWrite;
2761
2762	/*
2763	* Register this PCI bridge. The called function will take care on which bus we will get registered.
2764	*/
2765	rc = PDMDevHlpPCIRegister (pDevIns, &pBus->aPciDev);
2766	if (RT_FAILURE(rc))
2767	return rc;
2768
2769	/*
2770	* The iBus property doesn't really represent the bus number
2771	* because the guest and the BIOS can choose different bus numbers
2772	* for them.
2773	* The bus number is mainly for the setIrq function to indicate
2774	* when the host bus is reached which will have iBus = 0.
2775	* That's why the + 1.
2776	*/
2777	pBus->iBus = iInstance + 1;
2778
2779	/*
2780	* Register SSM handlers. We use the same saved state version as for the host bridge
2781	* to make changes easier.
2782	*/
2783	rc = PDMDevHlpSSMRegisterEx(pDevIns, VBOX_ICH9PCI_SAVED_STATE_VERSION_CURRENT,
2784	sizeof(pBus) + 16128,
2785	"pgm" /* before */,
2786	NULL, NULL, NULL,
2787	NULL, ich9pcibridgeR3SaveExec, NULL,
2788	NULL, ich9pcibridgeR3LoadExec, NULL);
2789	if (RT_FAILURE(rc))
2790	return rc;
2791
2792
2793	return VINF_SUCCESS;
2794	}
2795
2796	/**
2797	* @copydoc FNPDMDEVRESET
2798	*/
2799	static void ich9pcibridgeReset(PPDMDEVINS pDevIns)
2800	{
2801	PICH9PCIBUS pBus = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
2802
2803	/* Reset config space to default values. */
2804	PCIDevSetByte(&pBus->aPciDev, VBOX_PCI_PRIMARY_BUS, 0);
2805	PCIDevSetByte(&pBus->aPciDev, VBOX_PCI_SECONDARY_BUS, 0);
2806	PCIDevSetByte(&pBus->aPciDev, VBOX_PCI_SUBORDINATE_BUS, 0);
2807
2808	/* PCI-specific reset for each device. */
2809	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
2810	{
2811	if (pBus->apDevices[i])
2812	ich9pciResetDevice(pBus->apDevices[i]);
2813	}
2814	}
2815
2816
2817	/**
2818	* @copydoc FNPDMDEVRELOCATE
2819	*/
2820	static DECLCALLBACK(void) ich9pcibridgeRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
2821	{
2822	PICH9PCIBUS pBus = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
2823	pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2824
2825	/* Relocate RC pointers for the attached pci devices. */
2826	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
2827	ich9pciRelocateDevice(pBus->apDevices[i], offDelta);
2828	}
2829
2830	/**
2831	* The PCI bus device registration structure.
2832	*/
2833	const PDMDEVREG g_DevicePciIch9 =
2834	{
2835	/* u32Version */
2836	PDM_DEVREG_VERSION,
2837	/* szName */
2838	"ich9pci",
2839	/* szRCMod */
2840	"VBoxDDGC.gc",
2841	/* szR0Mod */
2842	"VBoxDDR0.r0",
2843	/* pszDescription */
2844	"ICH9 PCI bridge",
2845	/* fFlags */
2846	PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
2847	/* fClass */
2848	PDM_DEVREG_CLASS_BUS_PCI \| PDM_DEVREG_CLASS_BUS_ISA,
2849	/* cMaxInstances */
2850	1,
2851	/* cbInstance */
2852	sizeof(ICH9PCIGLOBALS),
2853	/* pfnConstruct */
2854	ich9pciConstruct,
2855	/* pfnDestruct */
2856	NULL,
2857	/* pfnRelocate */
2858	ich9pciRelocate,
2859	/* pfnIOCtl */
2860	NULL,
2861	/* pfnPowerOn */
2862	NULL,
2863	/* pfnReset */
2864	ich9pciReset,
2865	/* pfnSuspend */
2866	NULL,
2867	/* pfnResume */
2868	NULL,
2869	/* pfnAttach */
2870	NULL,
2871	/* pfnDetach */
2872	NULL,
2873	/* pfnQueryInterface */
2874	NULL,
2875	/* pfnInitComplete */
2876	NULL,
2877	/* pfnPowerOff */
2878	NULL,
2879	/* pfnSoftReset */
2880	NULL,
2881	/* u32VersionEnd */
2882	PDM_DEVREG_VERSION
2883	};
2884
2885	/**
2886	* The device registration structure
2887	* for the PCI-to-PCI bridge.
2888	*/
2889	const PDMDEVREG g_DevicePciIch9Bridge =
2890	{
2891	/* u32Version */
2892	PDM_DEVREG_VERSION,
2893	/* szName */
2894	"ich9pcibridge",
2895	/* szRCMod */
2896	"VBoxDDGC.gc",
2897	/* szR0Mod */
2898	"VBoxDDR0.r0",
2899	/* pszDescription */
2900	"ICH9 PCI to PCI bridge",
2901	/* fFlags */
2902	PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
2903	/* fClass */
2904	PDM_DEVREG_CLASS_BUS_PCI,
2905	/* cMaxInstances */
2906	~0,
2907	/* cbInstance */
2908	sizeof(ICH9PCIBUS),
2909	/* pfnConstruct */
2910	ich9pcibridgeConstruct,
2911	/* pfnDestruct */
2912	NULL,
2913	/* pfnRelocate */
2914	ich9pcibridgeRelocate,
2915	/* pfnIOCtl */
2916	NULL,
2917	/* pfnPowerOn */
2918	NULL,
2919	/* pfnReset */
2920	NULL, /* Must be NULL, to make sure only bus driver handles reset */
2921	/* pfnSuspend */
2922	NULL,
2923	/* pfnResume */
2924	NULL,
2925	/* pfnAttach */
2926	NULL,
2927	/* pfnDetach */
2928	NULL,
2929	/* pfnQueryInterface */
2930	NULL,
2931	/* pfnInitComplete */
2932	NULL,
2933	/* pfnPowerOff */
2934	NULL,
2935	/* pfnSoftReset */
2936	NULL,
2937	/* u32VersionEnd */
2938	PDM_DEVREG_VERSION
2939	};
2940
2941	#endif /* IN_RING3 */
2942	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */

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source: vbox/trunk/src/VBox/Devices/Bus/DevPciIch9.cpp@ 38751

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