DevPciIch9.cpp@ 41697

Last change on this file since 41697 was 41697, checked in by vboxsync, 12 years ago
Debugger: Added "info pci" command PCI devices; added showing bus master status. Fixed some variables in the ICH9 implementation.
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 107.5 KB

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1	/* $Id: DevPciIch9.cpp 41697 2012-06-14 09:44:06Z vboxsync $ */
2	/** @file
3	* DevPCI - ICH9 southbridge PCI bus emulation device.
4	*/
5
6	/*
7	* Copyright (C) 2010-2011 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/*******************************************************************************
19	* Header Files *
20	*******************************************************************************/
21	#define LOG_GROUP LOG_GROUP_DEV_PCI
22	/* Hack to get PCIDEVICEINT declare at the right point - include "PCIInternal.h". */
23	#define PCI_INCLUDE_PRIVATE
24	#define PCIBus ICH9PCIBus
25	#include <VBox/pci.h>
26	#include <VBox/msi.h>
27	#include <VBox/vmm/pdmdev.h>
28	#include <iprt/asm.h>
29	#include <iprt/assert.h>
30	#include <iprt/string.h>
31	#ifdef IN_RING3
32	#include <iprt/alloc.h>
33	#endif
34
35	#include "VBoxDD.h"
36
37	#include "MsiCommon.h"
38
39
40	/*******************************************************************************
41	* Structures and Typedefs *
42	*******************************************************************************/
43	/**
44	* PCI Bus instance.
45	*/
46	typedef struct ICH9PCIBus
47	{
48	/** Bus number. */
49	int32_t iBus;
50	/** Number of bridges attached to the bus. */
51	uint32_t cBridges;
52
53	/** Array of PCI devices. We assume 32 slots, each with 8 functions. */
54	R3PTRTYPE(PPCIDEVICE) apDevices[256];
55	/** Array of bridges attached to the bus. */
56	R3PTRTYPE(PPCIDEVICE *) papBridgesR3;
57
58	/** R3 pointer to the device instance. */
59	PPDMDEVINSR3 pDevInsR3;
60	/** Pointer to the PCI R3 helpers. */
61	PCPDMPCIHLPR3 pPciHlpR3;
62
63	/** R0 pointer to the device instance. */
64	PPDMDEVINSR0 pDevInsR0;
65	/** Pointer to the PCI R0 helpers. */
66	PCPDMPCIHLPR0 pPciHlpR0;
67
68	/** RC pointer to the device instance. */
69	PPDMDEVINSRC pDevInsRC;
70	/** Pointer to the PCI RC helpers. */
71	PCPDMPCIHLPRC pPciHlpRC;
72
73	/** The PCI device for the PCI bridge. */
74	PCIDEVICE aPciDev;
75
76	} ICH9PCIBUS, *PICH9PCIBUS;
77
78
79	/** @def PCI_APIC_IRQ_PINS
80	* Number of pins for interrupts if the APIC is used.
81	*/
82	#define PCI_APIC_IRQ_PINS 8
83
84	/**
85	* PCI Globals - This is the host-to-pci bridge and the root bus.
86	*/
87	typedef struct
88	{
89	/** R3 pointer to the device instance. */
90	PPDMDEVINSR3 pDevInsR3;
91	/** R0 pointer to the device instance. */
92	PPDMDEVINSR0 pDevInsR0;
93	/** RC pointer to the device instance. */
94	PPDMDEVINSRC pDevInsRC;
95
96	#if HC_ARCH_BITS == 64
97	uint32_t Alignment0;
98	#endif
99
100	/** Config register. */
101	uint32_t uConfigReg;
102
103	/** I/O APIC irq levels */
104	volatile uint32_t uaPciApicIrqLevels[PCI_APIC_IRQ_PINS];
105
106	#if 1 /* Will be moved into the BIOS soon. */
107	/** The next I/O port address which the PCI BIOS will use. */
108	uint32_t uPciBiosIo;
109	/** The next MMIO address which the PCI BIOS will use. */
110	uint32_t uPciBiosMmio;
111	/** Actual bus number. */
112	uint8_t uBus;
113	#endif
114	/** Physical address of PCI config space MMIO region. */
115	uint64_t u64PciConfigMMioAddress;
116	/** Length of PCI config space MMIO region. */
117	uint64_t u64PciConfigMMioLength;
118
119	/** PCI bus which is attached to the host-to-PCI bridge. */
120	ICH9PCIBUS aPciBus;
121	} ICH9PCIGLOBALS, *PICH9PCIGLOBALS;
122
123
124	typedef struct
125	{
126	uint8_t iBus;
127	uint8_t iDeviceFunc;
128	uint16_t iRegister;
129	} PciAddress;
130
131	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
132
133	/*******************************************************************************
134	* Defined Constants And Macros *
135	*******************************************************************************/
136
137	/** @def VBOX_ICH9PCI_SAVED_STATE_VERSION
138	* Saved state version of the ICH9 PCI bus device.
139	*/
140	#define VBOX_ICH9PCI_SAVED_STATE_VERSION_NOMSI 1
141	#define VBOX_ICH9PCI_SAVED_STATE_VERSION_MSI 2
142	#define VBOX_ICH9PCI_SAVED_STATE_VERSION_CURRENT VBOX_ICH9PCI_SAVED_STATE_VERSION_MSI
143
144	/** Converts a bus instance pointer to a device instance pointer. */
145	#define PCIBUS_2_DEVINS(pPciBus) ((pPciBus)->CTX_SUFF(pDevIns))
146	/** Converts a device instance pointer to a ICH9PCIGLOBALS pointer. */
147	#define DEVINS_2_PCIGLOBALS(pDevIns) ((PICH9PCIGLOBALS)(PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS)))
148	/** Converts a device instance pointer to a PCIBUS pointer. */
149	#define DEVINS_2_PCIBUS(pDevIns) ((PICH9PCIBUS)(&PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS)->aPciBus))
150	/** Converts a pointer to a PCI root bus instance to a PCIGLOBALS pointer. */
151	#define PCIROOTBUS_2_PCIGLOBALS(pPciBus) ( (PICH9PCIGLOBALS)((uintptr_t)(pPciBus) - RT_OFFSETOF(ICH9PCIGLOBALS, aPciBus)) )
152
153	/** @def PCI_LOCK
154	* Acquires the PDM lock. This is a NOP if locking is disabled. */
155	/** @def PCI_UNLOCK
156	* Releases the PDM lock. This is a NOP if locking is disabled. */
157	#define PCI_LOCK(pDevIns, rc) \
158	do { \
159	int rc2 = DEVINS_2_PCIBUS(pDevIns)->CTX_SUFF(pPciHlp)->pfnLock((pDevIns), rc); \
160	if (rc2 != VINF_SUCCESS) \
161	return rc2; \
162	} while (0)
163	#define PCI_UNLOCK(pDevIns) \
164	DEVINS_2_PCIBUS(pDevIns)->CTX_SUFF(pPciHlp)->pfnUnlock(pDevIns)
165
166	/* Prototypes */
167	static void ich9pciSetIrqInternal(PICH9PCIGLOBALS pGlobals, uint8_t uDevFn, PPCIDEVICE pPciDev,
168	int iIrq, int iLevel, uint32_t uTagSrc);
169	#ifdef IN_RING3
170	static void ich9pcibridgeReset(PPDMDEVINS pDevIns);
171	static int ich9pciRegisterInternal(PICH9PCIBUS pBus, int iDev, PPCIDEVICE pPciDev, const char *pszName);
172	static void ich9pciUpdateMappings(PCIDevice *pDev);
173	static DECLCALLBACK(uint32_t) ich9pciConfigReadDev(PCIDevice *aDev, uint32_t u32Address, unsigned len);
174	DECLINLINE(PPCIDEVICE) ich9pciFindBridge(PICH9PCIBUS pBus, uint8_t iBus);
175	static void ich9pciBiosInitDevice(PICH9PCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn);
176	#endif
177
178	// See 7.2.2. PCI Express Enhanced Configuration Mechanism for details of address
179	// mapping, we take n=6 approach
180	DECLINLINE(void) ich9pciPhysToPciAddr(PICH9PCIGLOBALS pGlobals, RTGCPHYS GCPhysAddr, PciAddress* pPciAddr)
181	{
182	NOREF(pGlobals);
183	pPciAddr->iBus = (GCPhysAddr >> 20) & ((1<<6) - 1);
184	pPciAddr->iDeviceFunc = (GCPhysAddr >> 12) & ((1<<(5+3)) - 1); // 5 bits - device, 3 bits - function
185	pPciAddr->iRegister = (GCPhysAddr >> 0) & ((1<<(6+4+2)) - 1); // 6 bits - register, 4 bits - extended register, 2 bits -Byte Enable
186	}
187
188	DECLINLINE(void) ich9pciStateToPciAddr(PICH9PCIGLOBALS pGlobals, RTGCPHYS addr, PciAddress* pPciAddr)
189	{
190	pPciAddr->iBus = (pGlobals->uConfigReg >> 16) & 0xff;
191	pPciAddr->iDeviceFunc = (pGlobals->uConfigReg >> 8) & 0xff;
192	pPciAddr->iRegister = (pGlobals->uConfigReg & 0xfc) \| (addr & 3);
193	}
194
195	PDMBOTHCBDECL(void) ich9pciSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel, uint32_t uTagSrc)
196	{
197	ich9pciSetIrqInternal(PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS), pPciDev->devfn, pPciDev, iIrq, iLevel, uTagSrc);
198	}
199
200	PDMBOTHCBDECL(void) ich9pcibridgeSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel, uint32_t uTagSrc)
201	{
202	/*
203	* The PCI-to-PCI bridge specification defines how the interrupt pins
204	* are routed from the secondary to the primary bus (see chapter 9).
205	* iIrq gives the interrupt pin the pci device asserted.
206	* We change iIrq here according to the spec and call the SetIrq function
207	* of our parent passing the device which asserted the interrupt instead of the device of the bridge.
208	*/
209	PICH9PCIBUS pBus = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
210	PPCIDEVICE pPciDevBus = pPciDev;
211	int iIrqPinBridge = iIrq;
212	uint8_t uDevFnBridge = 0;
213
214	/* Walk the chain until we reach the host bus. */
215	do
216	{
217	uDevFnBridge = pBus->aPciDev.devfn;
218	iIrqPinBridge = ((pPciDevBus->devfn >> 3) + iIrqPinBridge) & 3;
219
220	/* Get the parent. */
221	pBus = pBus->aPciDev.Int.s.CTX_SUFF(pBus);
222	pPciDevBus = &pBus->aPciDev;
223	} while (pBus->iBus != 0);
224
225	AssertMsgReturnVoid(pBus->iBus == 0, ("This is not the host pci bus iBus=%d\n", pBus->iBus));
226	ich9pciSetIrqInternal(PCIROOTBUS_2_PCIGLOBALS(pBus), uDevFnBridge, pPciDev, iIrqPinBridge, iLevel, uTagSrc);
227	}
228
229	/**
230	* Port I/O Handler for PCI address OUT operations.
231	*
232	* @returns VBox status code.
233	*
234	* @param pDevIns The device instance.
235	* @param pvUser User argument - ignored.
236	* @param uPort Port number used for the OUT operation.
237	* @param u32 The value to output.
238	* @param cb The value size in bytes.
239	*/
240	PDMBOTHCBDECL(int) ich9pciIOPortAddressWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
241	{
242	LogFlow(("ich9pciIOPortAddressWrite: Port=%#x u32=%#x cb=%d\n", Port, u32, cb));
243	NOREF(pvUser);
244	if (cb == 4)
245	{
246	PICH9PCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
247
248	PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_WRITE);
249	pThis->uConfigReg = u32 & ~3; /* Bits 0-1 are reserved and we silently clear them */
250	PCI_UNLOCK(pDevIns);
251	}
252
253	return VINF_SUCCESS;
254	}
255
256	/**
257	* Port I/O Handler for PCI address IN operations.
258	*
259	* @returns VBox status code.
260	*
261	* @param pDevIns The device instance.
262	* @param pvUser User argument - ignored.
263	* @param uPort Port number used for the IN operation.
264	* @param pu32 Where to store the result.
265	* @param cb Number of bytes read.
266	*/
267	PDMBOTHCBDECL(int) ich9pciIOPortAddressRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
268	{
269	NOREF(pvUser);
270	if (cb == 4)
271	{
272	PICH9PCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
273	PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_READ);
274	*pu32 = pThis->uConfigReg;
275	PCI_UNLOCK(pDevIns);
276	LogFlow(("ich9pciIOPortAddressRead: Port=%#x cb=%d -> %#x\n", Port, cb, *pu32));
277	return VINF_SUCCESS;
278	}
279
280	Log(("ich9pciIOPortAddressRead: Port=%#x cb=%d VERR_IOM_IOPORT_UNUSED\n", Port, cb));
281
282	return VERR_IOM_IOPORT_UNUSED;
283	}
284
285	static int ich9pciDataWriteAddr(PICH9PCIGLOBALS pGlobals, PciAddress* pAddr,
286	uint32_t val, int cb, int rcReschedule)
287	{
288	int rc = VINF_SUCCESS;
289
290	if (pAddr->iBus != 0)
291	{
292	if (pGlobals->aPciBus.cBridges)
293	{
294	#ifdef IN_RING3 /** @todo do lookup in R0/RC too! */
295	PPCIDEVICE pBridgeDevice = ich9pciFindBridge(&pGlobals->aPciBus, pAddr->iBus);
296	if (pBridgeDevice)
297	{
298	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigWrite);
299	pBridgeDevice->Int.s.pfnBridgeConfigWrite(pBridgeDevice->pDevIns, pAddr->iBus, pAddr->iDeviceFunc,
300	pAddr->iRegister, val, cb);
301	}
302	else
303	{
304	// do nothing, bridge not found
305	}
306	NOREF(rcReschedule);
307	#else
308	rc = rcReschedule;
309	#endif
310	}
311	}
312	else
313	{
314	if (pGlobals->aPciBus.apDevices[pAddr->iDeviceFunc])
315	{
316	#ifdef IN_RING3
317	R3PTRTYPE(PCIDevice *) aDev = pGlobals->aPciBus.apDevices[pAddr->iDeviceFunc];
318	aDev->Int.s.pfnConfigWrite(aDev, pAddr->iRegister, val, cb);
319	#else
320	rc = rcReschedule;
321	#endif
322	}
323	}
324
325	Log2(("ich9pciDataWriteAddr: %02x:%02x:%02x reg %x(%d) %x %Rrc\n",
326	pAddr->iBus, pAddr->iDeviceFunc >> 3, pAddr->iDeviceFunc & 0x7, pAddr->iRegister,
327	cb, val, rc));
328
329	return rc;
330	}
331
332	static int ich9pciDataWrite(PICH9PCIGLOBALS pGlobals, uint32_t addr, uint32_t val, int len)
333	{
334	PciAddress aPciAddr;
335
336	LogFlow(("ich9pciDataWrite: config=%08x val=%08x len=%d\n", pGlobals->uConfigReg, val, len));
337
338	if (!(pGlobals->uConfigReg & (1 << 31)))
339	return VINF_SUCCESS;
340
341	if ((pGlobals->uConfigReg & 0x3) != 0)
342	return VINF_SUCCESS;
343
344	/* Compute destination device */
345	ich9pciStateToPciAddr(pGlobals, addr, &aPciAddr);
346
347	return ich9pciDataWriteAddr(pGlobals, &aPciAddr, val, len, VINF_IOM_R3_IOPORT_WRITE);
348	}
349
350	static void ich9pciNoMem(void* ptr, int cb)
351	{
352	for (int i = 0; i < cb; i++)
353	((uint8_t*)ptr)[i] = 0xff;
354	}
355
356	/**
357	* Port I/O Handler for PCI data OUT operations.
358	*
359	* @returns VBox status code.
360	*
361	* @param pDevIns The device instance.
362	* @param pvUser User argument - ignored.
363	* @param uPort Port number used for the OUT operation.
364	* @param u32 The value to output.
365	* @param cb The value size in bytes.
366	*/
367	PDMBOTHCBDECL(int) ich9pciIOPortDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
368	{
369	LogFlow(("ich9pciIOPortDataWrite: Port=%#x u32=%#x cb=%d\n", Port, u32, cb));
370	NOREF(pvUser);
371	int rc = VINF_SUCCESS;
372	if (!(Port % cb))
373	{
374	PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_WRITE);
375	rc = ich9pciDataWrite(PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS), Port, u32, cb);
376	PCI_UNLOCK(pDevIns);
377	}
378	else
379	AssertMsgFailed(("Unaligned write to port %#x u32=%#x cb=%d\n", Port, u32, cb));
380	return rc;
381	}
382
383	static int ich9pciDataReadAddr(PICH9PCIGLOBALS pGlobals, PciAddress* pPciAddr, int cb,
384	uint32_t *pu32, int rcReschedule)
385	{
386	int rc = VINF_SUCCESS;
387
388	if (pPciAddr->iBus != 0)
389	{
390	if (pGlobals->aPciBus.cBridges)
391	{
392	#ifdef IN_RING3 /** @todo do lookup in R0/RC too! */
393	PPCIDEVICE pBridgeDevice = ich9pciFindBridge(&pGlobals->aPciBus, pPciAddr->iBus);
394	if (pBridgeDevice)
395	{
396	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigRead);
397	*pu32 = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->pDevIns, pPciAddr->iBus, pPciAddr->iDeviceFunc, pPciAddr->iRegister, cb);
398	}
399	else
400	ich9pciNoMem(pu32, cb);
401	NOREF(rcReschedule);
402	#else
403	rc = rcReschedule;
404	#endif
405	} else
406	ich9pciNoMem(pu32, cb);
407	}
408	else
409	{
410	if (pGlobals->aPciBus.apDevices[pPciAddr->iDeviceFunc])
411	{
412	#ifdef IN_RING3
413	R3PTRTYPE(PCIDevice *) aDev = pGlobals->aPciBus.apDevices[pPciAddr->iDeviceFunc];
414	*pu32 = aDev->Int.s.pfnConfigRead(aDev, pPciAddr->iRegister, cb);
415	#else
416	rc = rcReschedule;
417	#endif
418	}
419	else
420	ich9pciNoMem(pu32, cb);
421	}
422
423	Log3(("ich9pciDataReadAddr: %02x:%02x:%02x reg %x(%d) gave %x %Rrc\n",
424	pPciAddr->iBus, pPciAddr->iDeviceFunc >> 3, pPciAddr->iDeviceFunc & 0x7, pPciAddr->iRegister,
425	cb, *pu32, rc));
426
427	return rc;
428	}
429
430	static int ich9pciDataRead(PICH9PCIGLOBALS pGlobals, uint32_t addr, int cb, uint32_t *pu32)
431	{
432	PciAddress aPciAddr;
433
434	LogFlow(("ich9pciDataRead: config=%x cb=%d\n", pGlobals->uConfigReg, cb));
435
436	*pu32 = 0xffffffff;
437
438	if (!(pGlobals->uConfigReg & (1 << 31)))
439	return VINF_SUCCESS;
440
441	if ((pGlobals->uConfigReg & 0x3) != 0)
442	return VINF_SUCCESS;
443
444	/* Compute destination device */
445	ich9pciStateToPciAddr(pGlobals, addr, &aPciAddr);
446
447	return ich9pciDataReadAddr(pGlobals, &aPciAddr, cb, pu32, VINF_IOM_R3_IOPORT_READ);
448	}
449
450	/**
451	* Port I/O Handler for PCI data IN operations.
452	*
453	* @returns VBox status code.
454	*
455	* @param pDevIns The device instance.
456	* @param pvUser User argument - ignored.
457	* @param uPort Port number used for the IN operation.
458	* @param pu32 Where to store the result.
459	* @param cb Number of bytes read.
460	*/
461	PDMBOTHCBDECL(int) ich9pciIOPortDataRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
462	{
463	NOREF(pvUser);
464	if (!(Port % cb))
465	{
466	PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_READ);
467	int rc = ich9pciDataRead(PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS), Port, cb, pu32);
468	PCI_UNLOCK(pDevIns);
469	LogFlow(("ich9pciIOPortDataRead: Port=%#x cb=%#x -> %#x (%Rrc)\n", Port, cb, *pu32, rc));
470	return rc;
471	}
472	AssertMsgFailed(("Unaligned read from port %#x cb=%d\n", Port, cb));
473	return VERR_IOM_IOPORT_UNUSED;
474	}
475
476	/* Compute mapping of PCI slot and IRQ number to APIC interrupt line */
477	DECLINLINE(int) ich9pciSlot2ApicIrq(uint8_t uSlot, int irq_num)
478	{
479	return (irq_num + uSlot) & 7;
480	}
481
482	/* return the global irq number corresponding to a given device irq
483	pin. We could also use the bus number to have a more precise
484	mapping. This is the implementation note described in the PCI spec chapter 2.2.6 */
485	DECLINLINE(int) ich9pciSlotGetPirq(uint8_t uBus, uint8_t uDevFn, int iIrqNum)
486	{
487	NOREF(uBus);
488	int iSlotAddend = (uDevFn >> 3) - 1;
489	return (iIrqNum + iSlotAddend) & 3;
490	}
491
492	/* irqs corresponding to PCI irqs A-D, must match pci_irq_list in rombios.c */
493	static const uint8_t aPciIrqs[4] = { 11, 10, 9, 5 };
494
495	/* Add one more level up request on APIC input line */
496	DECLINLINE(void) ich9pciApicLevelUp(PICH9PCIGLOBALS pGlobals, int irq_num)
497	{
498	ASMAtomicIncU32(&pGlobals->uaPciApicIrqLevels[irq_num]);
499	}
500
501	/* Remove one level up request on APIC input line */
502	DECLINLINE(void) ich9pciApicLevelDown(PICH9PCIGLOBALS pGlobals, int irq_num)
503	{
504	ASMAtomicDecU32(&pGlobals->uaPciApicIrqLevels[irq_num]);
505	}
506
507	static void ich9pciApicSetIrq(PICH9PCIBUS pBus, uint8_t uDevFn, PCIDevice *pPciDev, int irq_num1, int iLevel,
508	uint32_t uTagSrc, int iForcedIrq)
509	{
510	/* This is only allowed to be called with a pointer to the root bus. */
511	AssertMsg(pBus->iBus == 0, ("iBus=%u\n", pBus->iBus));
512
513	if (iForcedIrq == -1)
514	{
515	int apic_irq, apic_level;
516	PICH9PCIGLOBALS pGlobals = PCIROOTBUS_2_PCIGLOBALS(pBus);
517	int irq_num = ich9pciSlot2ApicIrq(uDevFn >> 3, irq_num1);
518
519	if ((iLevel & PDM_IRQ_LEVEL_HIGH) == PDM_IRQ_LEVEL_HIGH)
520	ich9pciApicLevelUp(pGlobals, irq_num);
521	else if ((iLevel & PDM_IRQ_LEVEL_HIGH) == PDM_IRQ_LEVEL_LOW)
522	ich9pciApicLevelDown(pGlobals, irq_num);
523
524	apic_irq = irq_num + 0x10;
525	apic_level = pGlobals->uaPciApicIrqLevels[irq_num] != 0;
526	Log3(("ich9pciApicSetIrq: %s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d uTagSrc=%#x\n",
527	R3STRING(pPciDev->name), irq_num1, iLevel, apic_irq, apic_level, irq_num, uTagSrc));
528	pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), apic_irq, apic_level, uTagSrc);
529
530	if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP)
531	{
532	/*
533	* we raised it few lines above, as PDM_IRQ_LEVEL_FLIP_FLOP has
534	* PDM_IRQ_LEVEL_HIGH bit set
535	*/
536	ich9pciApicLevelDown(pGlobals, irq_num);
537	pPciDev->Int.s.uIrqPinState = PDM_IRQ_LEVEL_LOW;
538	apic_level = pGlobals->uaPciApicIrqLevels[irq_num] != 0;
539	Log3(("ich9pciApicSetIrq: %s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d uTagSrc=%#x (flop)\n",
540	R3STRING(pPciDev->name), irq_num1, iLevel, apic_irq, apic_level, irq_num, uTagSrc));
541	pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), apic_irq, apic_level, uTagSrc);
542	}
543	} else {
544	Log3(("ich9pciApicSetIrq: (forced) %s: irq_num1=%d level=%d acpi_irq=%d uTagSrc=%#x\n",
545	R3STRING(pPciDev->name), irq_num1, iLevel, iForcedIrq, uTagSrc));
546	pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), iForcedIrq, iLevel, uTagSrc);
547	}
548	}
549
550	static void ich9pciSetIrqInternal(PICH9PCIGLOBALS pGlobals, uint8_t uDevFn, PPCIDEVICE pPciDev,
551	int iIrq, int iLevel, uint32_t uTagSrc)
552	{
553
554	if (PCIDevIsIntxDisabled(pPciDev))
555	{
556	if (MsiIsEnabled(pPciDev))
557	{
558	PPDMDEVINS pDevIns = pGlobals->aPciBus.CTX_SUFF(pDevIns);
559	MsiNotify(pDevIns, pGlobals->aPciBus.CTX_SUFF(pPciHlp), pPciDev, iIrq, iLevel, uTagSrc);
560	}
561
562	if (MsixIsEnabled(pPciDev))
563	{
564	PPDMDEVINS pDevIns = pGlobals->aPciBus.CTX_SUFF(pDevIns);
565	MsixNotify(pDevIns, pGlobals->aPciBus.CTX_SUFF(pPciHlp), pPciDev, iIrq, iLevel, uTagSrc);
566	}
567	return;
568	}
569
570	PICH9PCIBUS pBus = &pGlobals->aPciBus;
571	const bool fIsAcpiDevice = PCIDevGetDeviceId(pPciDev) == 0x7113;
572
573	/* Check if the state changed. */
574	if (pPciDev->Int.s.uIrqPinState != iLevel)
575	{
576	pPciDev->Int.s.uIrqPinState = (iLevel & PDM_IRQ_LEVEL_HIGH);
577
578	/* Send interrupt to I/O APIC only now. */
579	if (fIsAcpiDevice)
580	/*
581	* ACPI needs special treatment since SCI is hardwired and
582	* should not be affected by PCI IRQ routing tables at the
583	* same time SCI IRQ is shared in PCI sense hence this
584	* kludge (i.e. we fetch the hardwired value from ACPIs
585	* PCI device configuration space).
586	*/
587	ich9pciApicSetIrq(pBus, uDevFn, pPciDev, -1, iLevel, uTagSrc, PCIDevGetInterruptLine(pPciDev));
588	else
589	ich9pciApicSetIrq(pBus, uDevFn, pPciDev, iIrq, iLevel, uTagSrc, -1);
590	}
591	}
592
593	PDMBOTHCBDECL(int) ich9pciMcfgMMIOWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void const pv, unsigned cb)
594	{
595	PICH9PCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
596	PciAddress aDest;
597	uint32_t u32 = 0;
598	NOREF(pvUser);
599
600	Log2(("ich9pciMcfgMMIOWrite: %RGp(%d) \n", GCPhysAddr, cb));
601
602	PCI_LOCK(pDevIns, VINF_IOM_R3_MMIO_WRITE);
603
604	ich9pciPhysToPciAddr(pGlobals, GCPhysAddr, &aDest);
605
606	switch (cb)
607	{
608	case 1:
609	u32 = (uint8_t)pv;
610	break;
611	case 2:
612	u32 = (uint16_t)pv;
613	break;
614	case 4:
615	u32 = (uint32_t)pv;
616	break;
617	default:
618	Assert(false);
619	break;
620	}
621	int rc = ich9pciDataWriteAddr(pGlobals, &aDest, u32, cb, VINF_IOM_R3_MMIO_WRITE);
622	PCI_UNLOCK(pDevIns);
623
624	return rc;
625	}
626
627	PDMBOTHCBDECL(int) ich9pciMcfgMMIORead (PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb)
628	{
629	PICH9PCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
630	PciAddress aDest;
631	uint32_t rv;
632	NOREF(pvUser);
633
634	LogFlow(("ich9pciMcfgMMIORead: %RGp(%d) \n", GCPhysAddr, cb));
635
636	PCI_LOCK(pDevIns, VINF_IOM_R3_MMIO_READ);
637
638	ich9pciPhysToPciAddr(pGlobals, GCPhysAddr, &aDest);
639
640	int rc = ich9pciDataReadAddr(pGlobals, &aDest, cb, &rv, VINF_IOM_R3_MMIO_READ);
641
642	if (RT_SUCCESS(rc))
643	{
644	switch (cb)
645	{
646	case 1:
647	(uint8_t)pv = (uint8_t)rv;
648	break;
649	case 2:
650	(uint16_t)pv = (uint16_t)rv;
651	break;
652	case 4:
653	(uint32_t)pv = (uint32_t)rv;
654	break;
655	default:
656	Assert(false);
657	break;
658	}
659	}
660	PCI_UNLOCK(pDevIns);
661
662	return rc;
663	}
664
665	#ifdef IN_RING3
666
667	DECLINLINE(PPCIDEVICE) ich9pciFindBridge(PICH9PCIBUS pBus, uint8_t iBus)
668	{
669	/* Search for a fitting bridge. */
670	for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
671	{
672	/*
673	* Examine secondary and subordinate bus number.
674	* If the target bus is in the range we pass the request on to the bridge.
675	*/
676	PPCIDEVICE pBridge = pBus->papBridgesR3[iBridge];
677	AssertMsg(pBridge && pciDevIsPci2PciBridge(pBridge),
678	("Device is not a PCI bridge but on the list of PCI bridges\n"));
679	uint32_t uSecondary = PCIDevGetByte(pBridge, VBOX_PCI_SECONDARY_BUS);
680	uint32_t uSubordinate = PCIDevGetByte(pBridge, VBOX_PCI_SUBORDINATE_BUS);
681	Log3(("ich9pciFindBridge on bus %p, bridge %d: %d in %d..%d\n", pBus, iBridge, iBus, uSecondary, uSubordinate));
682	if (iBus >= uSecondary && iBus <= uSubordinate)
683	return pBridge;
684	}
685
686	/* Nothing found. */
687	return NULL;
688	}
689
690	static uint32_t ich9pciGetCfg(PCIDevice* aDev, int32_t iRegister, int cb)
691	{
692	return aDev->Int.s.pfnConfigRead(aDev, iRegister, cb);
693	}
694
695	static uint8_t ich9pciGetByte(PCIDevice* aDev, int32_t iRegister)
696	{
697	return (uint8_t)ich9pciGetCfg(aDev, iRegister, 1);
698	}
699
700	static uint16_t ich9pciGetWord(PCIDevice* aDev, int32_t iRegister)
701	{
702	return (uint16_t)ich9pciGetCfg(aDev, iRegister, 2);
703	}
704
705	static uint32_t ich9pciGetDWord(PCIDevice* aDev, int32_t iRegister)
706	{
707	return (uint32_t)ich9pciGetCfg(aDev, iRegister, 4);
708	}
709
710	DECLINLINE(uint32_t) ich9pciGetRegionReg(int iRegion)
711	{
712	return (iRegion == VBOX_PCI_ROM_SLOT) ?
713	VBOX_PCI_ROM_ADDRESS : (VBOX_PCI_BASE_ADDRESS_0 + iRegion * 4);
714	}
715
716	#define INVALID_PCI_ADDRESS ~0U
717
718	static int ich9pciUnmapRegion(PPCIDEVICE pDev, int iRegion)
719	{
720	PCIIORegion* pRegion = &pDev->Int.s.aIORegions[iRegion];
721	int rc = VINF_SUCCESS;
722	PICH9PCIBUS pBus = pDev->Int.s.CTX_SUFF(pBus);
723
724	Assert (pRegion->size != 0);
725
726	if (pRegion->addr != INVALID_PCI_ADDRESS)
727	{
728	if (pRegion->type & PCI_ADDRESS_SPACE_IO)
729	{
730	/* Port IO */
731	rc = PDMDevHlpIOPortDeregister(pDev->pDevIns, pRegion->addr, pRegion->size);
732	AssertRC(rc);
733	}
734	else
735	{
736	RTGCPHYS GCPhysBase = pRegion->addr;
737	if (pBus->pPciHlpR3->pfnIsMMIO2Base(pBus->pDevInsR3, pDev->pDevIns, GCPhysBase))
738	{
739	/* unmap it. */
740	rc = pRegion->map_func(pDev, iRegion, NIL_RTGCPHYS, pRegion->size, (PCIADDRESSSPACE)(pRegion->type));
741	AssertRC(rc);
742	rc = PDMDevHlpMMIO2Unmap(pDev->pDevIns, iRegion, GCPhysBase);
743	}
744	else
745	rc = PDMDevHlpMMIODeregister(pDev->pDevIns, GCPhysBase, pRegion->size);
746	}
747
748	pRegion->addr = INVALID_PCI_ADDRESS;
749	}
750
751	return rc;
752	}
753
754	static void ich9pciUpdateMappings(PCIDevice* pDev)
755	{
756	uint64_t uLast, uNew;
757
758	int iCmd = ich9pciGetWord(pDev, VBOX_PCI_COMMAND);
759	for (int iRegion = 0; iRegion < PCI_NUM_REGIONS; iRegion++)
760	{
761	PCIIORegion* pRegion = &pDev->Int.s.aIORegions[iRegion];
762	uint32_t uConfigReg = ich9pciGetRegionReg(iRegion);
763	int64_t iRegionSize = pRegion->size;
764	int rc;
765
766	if (iRegionSize == 0)
767	continue;
768
769	bool f64Bit = (pRegion->type & PCI_ADDRESS_SPACE_BAR64) != 0;
770
771	if (pRegion->type & PCI_ADDRESS_SPACE_IO)
772	{
773	/* port IO region */
774	if (iCmd & PCI_COMMAND_IOACCESS)
775	{
776	/* IO access allowed */
777	uNew = ich9pciGetDWord(pDev, uConfigReg);
778	uNew &= ~(iRegionSize - 1);
779	uLast = uNew + iRegionSize - 1;
780	/* only 64K ioports on PC */
781	if (uLast <= uNew \|\| uNew == 0 \|\| uLast >= 0x10000)
782	uNew = INVALID_PCI_ADDRESS;
783	} else
784	uNew = INVALID_PCI_ADDRESS;
785	}
786	else
787	{
788	/* MMIO region */
789	if (iCmd & PCI_COMMAND_MEMACCESS)
790	{
791	uNew = ich9pciGetDWord(pDev, uConfigReg);
792
793	if (f64Bit)
794	{
795	uNew \|= ((uint64_t)ich9pciGetDWord(pDev, uConfigReg+4)) << 32;
796	if (uNew > UINT64_C(0x0000010000000000))
797	{
798	/* Workaround for REM being unhapping with mapping very lange 64-bit addresses */
799	Log(("Ignoring too 64-bit BAR: %llx\n", uNew));
800	uNew = INVALID_PCI_ADDRESS;
801	}
802	}
803
804	/* the ROM slot has a specific enable bit */
805	if (iRegion == PCI_ROM_SLOT && !(uNew & 1))
806	uNew = INVALID_PCI_ADDRESS;
807	else
808	{
809	uNew &= ~(iRegionSize - 1);
810	uLast = uNew + iRegionSize - 1;
811	/* NOTE: we do not support wrapping */
812	/* XXX: as we cannot support really dynamic
813	mappings, we handle specific values as invalid
814	mappings. */
815	if (uLast <= uNew \|\| uNew == 0 \|\| uLast == INVALID_PCI_ADDRESS)
816	uNew = INVALID_PCI_ADDRESS;
817	}
818	} else
819	uNew = INVALID_PCI_ADDRESS;
820	}
821	/* now do the real mapping */
822	if (uNew != pRegion->addr)
823	{
824	if (pRegion->addr != INVALID_PCI_ADDRESS)
825	ich9pciUnmapRegion(pDev, iRegion);
826
827	pRegion->addr = uNew;
828	if (pRegion->addr != INVALID_PCI_ADDRESS)
829	{
830
831	/* finally, map the region */
832	rc = pRegion->map_func(pDev, iRegion,
833	pRegion->addr, pRegion->size,
834	(PCIADDRESSSPACE)(pRegion->type));
835	AssertRC(rc);
836	}
837	}
838	}
839	}
840
841	static DECLCALLBACK(int) ich9pciRegister(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, const char *pszName, int iDev)
842	{
843	PICH9PCIBUS pBus = DEVINS_2_PCIBUS(pDevIns);
844
845	/*
846	* Check input.
847	*/
848	if ( !pszName
849	\|\| !pPciDev
850	\|\| iDev >= (int)RT_ELEMENTS(pBus->apDevices)
851	)
852	{
853	AssertMsgFailed(("Invalid argument! pszName=%s pPciDev=%p iDev=%d\n", pszName, pPciDev, iDev));
854	return VERR_INVALID_PARAMETER;
855	}
856
857	/*
858	* Register the device.
859	*/
860	return ich9pciRegisterInternal(pBus, iDev, pPciDev, pszName);
861	}
862
863
864	static DECLCALLBACK(int) ich9pciRegisterMsi(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PPDMMSIREG pMsiReg)
865	{
866	NOREF(pDevIns);
867	int rc;
868
869	rc = MsiInit(pPciDev, pMsiReg);
870	if (RT_FAILURE(rc))
871	return rc;
872
873	rc = MsixInit(pPciDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pPciHlp), pPciDev, pMsiReg);
874	if (RT_FAILURE(rc))
875	return rc;
876
877	return VINF_SUCCESS;
878	}
879
880
881	static DECLCALLBACK(int) ich9pcibridgeRegister(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, const char *pszName, int iDev)
882	{
883
884	PICH9PCIBUS pBus = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
885
886	/*
887	* Check input.
888	*/
889	if ( !pszName
890	\|\| !pPciDev
891	\|\| iDev >= (int)RT_ELEMENTS(pBus->apDevices))
892	{
893	AssertMsgFailed(("Invalid argument! pszName=%s pPciDev=%p iDev=%d\n", pszName, pPciDev, iDev));
894	return VERR_INVALID_PARAMETER;
895	}
896
897	/*
898	* Register the device.
899	*/
900	return ich9pciRegisterInternal(pBus, iDev, pPciDev, pszName);
901	}
902
903	static DECLCALLBACK(int) ich9pciIORegionRegister(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iRegion, uint32_t cbRegion, PCIADDRESSSPACE enmType, PFNPCIIOREGIONMAP pfnCallback)
904	{
905	NOREF(pDevIns);
906
907	/*
908	* Validate.
909	*/
910	AssertMsgReturn( enmType == (PCI_ADDRESS_SPACE_MEM \| PCI_ADDRESS_SPACE_BAR32)
911	\|\| enmType == (PCI_ADDRESS_SPACE_MEM_PREFETCH \| PCI_ADDRESS_SPACE_BAR32)
912	\|\| enmType == (PCI_ADDRESS_SPACE_MEM \| PCI_ADDRESS_SPACE_BAR64)
913	\|\| enmType == (PCI_ADDRESS_SPACE_MEM_PREFETCH \| PCI_ADDRESS_SPACE_BAR64)
914	\|\| enmType == PCI_ADDRESS_SPACE_IO
915	,
916	("Invalid enmType=%#x? Or was this a bitmask after all...\n", enmType),
917	VERR_INVALID_PARAMETER);
918	AssertMsgReturn((unsigned)iRegion < PCI_NUM_REGIONS,
919	("Invalid iRegion=%d PCI_NUM_REGIONS=%d\n", iRegion, PCI_NUM_REGIONS),
920	VERR_INVALID_PARAMETER);
921	int iLastSet = ASMBitLastSetU32(cbRegion);
922	AssertMsgReturn( iLastSet != 0
923	&& RT_BIT_32(iLastSet - 1) == cbRegion,
924	("Invalid cbRegion=%#x iLastSet=%#x (not a power of 2 or 0)\n", cbRegion, iLastSet),
925	VERR_INVALID_PARAMETER);
926
927	Log(("ich9pciIORegionRegister: %s region %d size %d type %x\n",
928	pPciDev->name, iRegion, cbRegion, enmType));
929
930	/* Make sure that we haven't marked this region as continuation of 64-bit region. */
931	Assert(pPciDev->Int.s.aIORegions[iRegion].type != 0xff);
932
933	/*
934	* Register the I/O region.
935	*/
936	PPCIIOREGION pRegion = &pPciDev->Int.s.aIORegions[iRegion];
937	pRegion->addr = INVALID_PCI_ADDRESS;
938	pRegion->size = cbRegion;
939	pRegion->type = enmType;
940	pRegion->map_func = pfnCallback;
941
942	if ((enmType & PCI_ADDRESS_SPACE_BAR64) != 0)
943	{
944	AssertMsgReturn(iRegion < 4,
945	("Region %d cannot be 64-bit\n", iRegion),
946	VERR_INVALID_PARAMETER);
947	/* Mark next region as continuation of this one. */
948	pPciDev->Int.s.aIORegions[iRegion+1].type = 0xff;
949	}
950
951	/* Set type in the PCI config space. */
952	uint32_t u32Value = ((uint32_t)enmType) & (PCI_ADDRESS_SPACE_IO \| PCI_ADDRESS_SPACE_BAR64 \| PCI_ADDRESS_SPACE_MEM_PREFETCH);
953	PCIDevSetDWord(pPciDev, ich9pciGetRegionReg(iRegion), u32Value);
954
955	return VINF_SUCCESS;
956	}
957
958	static DECLCALLBACK(void) ich9pciSetConfigCallbacks(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PFNPCICONFIGREAD pfnRead, PPFNPCICONFIGREAD ppfnReadOld,
959	PFNPCICONFIGWRITE pfnWrite, PPFNPCICONFIGWRITE ppfnWriteOld)
960	{
961	NOREF(pDevIns);
962
963	if (ppfnReadOld)
964	*ppfnReadOld = pPciDev->Int.s.pfnConfigRead;
965	pPciDev->Int.s.pfnConfigRead = pfnRead;
966
967	if (ppfnWriteOld)
968	*ppfnWriteOld = pPciDev->Int.s.pfnConfigWrite;
969	pPciDev->Int.s.pfnConfigWrite = pfnWrite;
970	}
971
972	/**
973	* Saves a state of the PCI device.
974	*
975	* @returns VBox status code.
976	* @param pDevIns Device instance of the PCI Bus.
977	* @param pPciDev Pointer to PCI device.
978	* @param pSSM The handle to save the state to.
979	*/
980	static DECLCALLBACK(int) ich9pciGenericSaveExec(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PSSMHANDLE pSSM)
981	{
982	NOREF(pDevIns);
983	Assert(!pciDevIsPassthrough(pPciDev));
984	return SSMR3PutMem(pSSM, &pPciDev->config[0], sizeof(pPciDev->config));
985	}
986
987	static int ich9pciR3CommonSaveExec(PICH9PCIBUS pBus, PSSMHANDLE pSSM)
988	{
989	/*
990	* Iterate thru all the devices.
991	*/
992	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
993	{
994	PPCIDEVICE pDev = pBus->apDevices[i];
995	if (pDev)
996	{
997	/* Device position */
998	SSMR3PutU32(pSSM, i);
999	/* PCI config registers */
1000	SSMR3PutMem(pSSM, pDev->config, sizeof(pDev->config));
1001
1002	/* Device flags */
1003	int rc = SSMR3PutU32(pSSM, pDev->Int.s.fFlags);
1004	if (RT_FAILURE(rc))
1005	return rc;
1006
1007	/* IRQ pin state */
1008	rc = SSMR3PutS32(pSSM, pDev->Int.s.uIrqPinState);
1009	if (RT_FAILURE(rc))
1010	return rc;
1011
1012	/* MSI info */
1013	rc = SSMR3PutU8(pSSM, pDev->Int.s.u8MsiCapOffset);
1014	if (RT_FAILURE(rc))
1015	return rc;
1016	rc = SSMR3PutU8(pSSM, pDev->Int.s.u8MsiCapSize);
1017	if (RT_FAILURE(rc))
1018	return rc;
1019
1020	/* MSI-X info */
1021	rc = SSMR3PutU8(pSSM, pDev->Int.s.u8MsixCapOffset);
1022	if (RT_FAILURE(rc))
1023	return rc;
1024	rc = SSMR3PutU8(pSSM, pDev->Int.s.u8MsixCapSize);
1025	if (RT_FAILURE(rc))
1026	return rc;
1027	/* Save MSI-X page state */
1028	if (pDev->Int.s.u8MsixCapOffset != 0)
1029	{
1030	Assert(pDev->Int.s.pMsixPageR3 != NULL);
1031	SSMR3PutMem(pSSM, pDev->Int.s.pMsixPageR3, 0x1000);
1032	if (RT_FAILURE(rc))
1033	return rc;
1034	}
1035	}
1036	}
1037	return SSMR3PutU32(pSSM, UINT32_MAX); /* terminator */
1038	}
1039
1040	static DECLCALLBACK(int) ich9pciR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
1041	{
1042	PICH9PCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
1043
1044	/*
1045	* Bus state data.
1046	*/
1047	SSMR3PutU32(pSSM, pThis->uConfigReg);
1048
1049	/*
1050	* Save IRQ states.
1051	*/
1052	for (int i = 0; i < PCI_APIC_IRQ_PINS; i++)
1053	SSMR3PutU32(pSSM, pThis->uaPciApicIrqLevels[i]);
1054
1055	SSMR3PutU32(pSSM, ~0); /* separator */
1056
1057	return ich9pciR3CommonSaveExec(&pThis->aPciBus, pSSM);
1058	}
1059
1060
1061	static DECLCALLBACK(int) ich9pcibridgeR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
1062	{
1063	PICH9PCIBUS pThis = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
1064	return ich9pciR3CommonSaveExec(pThis, pSSM);
1065	}
1066
1067
1068	static void ich9pcibridgeConfigWrite(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice, uint32_t u32Address, uint32_t u32Value, unsigned cb)
1069	{
1070	PICH9PCIBUS pBus = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
1071
1072	LogFlowFunc((": pDevIns=%p iBus=%d iDevice=%d u32Address=%u u32Value=%u cb=%d\n", pDevIns, iBus, iDevice, u32Address, u32Value, cb));
1073
1074	/* If the current bus is not the target bus search for the bus which contains the device. */
1075	if (iBus != PCIDevGetByte(&pBus->aPciDev, VBOX_PCI_SECONDARY_BUS))
1076	{
1077	PPCIDEVICE pBridgeDevice = ich9pciFindBridge(pBus, iBus);
1078	if (pBridgeDevice)
1079	{
1080	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigWrite);
1081	pBridgeDevice->Int.s.pfnBridgeConfigWrite(pBridgeDevice->pDevIns, iBus, iDevice, u32Address, u32Value, cb);
1082	}
1083	}
1084	else
1085	{
1086	/* This is the target bus, pass the write to the device. */
1087	PPCIDEVICE pPciDev = pBus->apDevices[iDevice];
1088	if (pPciDev)
1089	{
1090	Log(("%s: %s: addr=%02x val=%08x len=%d\n", __FUNCTION__, pPciDev->name, u32Address, u32Value, cb));
1091	pPciDev->Int.s.pfnConfigWrite(pPciDev, u32Address, u32Value, cb);
1092	}
1093	}
1094	}
1095
1096	static uint32_t ich9pcibridgeConfigRead(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice, uint32_t u32Address, unsigned cb)
1097	{
1098	PICH9PCIBUS pBus = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
1099	uint32_t u32Value;
1100
1101	LogFlowFunc((": pDevIns=%p iBus=%d iDevice=%d u32Address=%u cb=%d\n", pDevIns, iBus, iDevice, u32Address, cb));
1102
1103	/* If the current bus is not the target bus search for the bus which contains the device. */
1104	if (iBus != PCIDevGetByte(&pBus->aPciDev, VBOX_PCI_SECONDARY_BUS))
1105	{
1106	PPCIDEVICE pBridgeDevice = ich9pciFindBridge(pBus, iBus);
1107	if (pBridgeDevice)
1108	{
1109	AssertPtr( pBridgeDevice->Int.s.pfnBridgeConfigRead);
1110	u32Value = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->pDevIns, iBus, iDevice, u32Address, cb);
1111	}
1112	else
1113	ich9pciNoMem(&u32Value, 4);
1114	}
1115	else
1116	{
1117	/* This is the target bus, pass the read to the device. */
1118	PPCIDEVICE pPciDev = pBus->apDevices[iDevice];
1119	if (pPciDev)
1120	{
1121	u32Value = pPciDev->Int.s.pfnConfigRead(pPciDev, u32Address, cb);
1122	Log(("%s: %s: u32Address=%02x u32Value=%08x cb=%d\n", __FUNCTION__, pPciDev->name, u32Address, u32Value, cb));
1123	}
1124	else
1125	ich9pciNoMem(&u32Value, 4);
1126	}
1127
1128	return u32Value;
1129	}
1130
1131
1132	/**
1133	* Common routine for restoring the config registers of a PCI device.
1134	*
1135	* @param pDev The PCI device.
1136	* @param pbSrcConfig The configuration register values to be loaded.
1137	* @param fIsBridge Whether this is a bridge device or not.
1138	*/
1139	static void pciR3CommonRestoreConfig(PPCIDEVICE pDev, uint8_t const *pbSrcConfig, bool fIsBridge)
1140	{
1141	/*
1142	* This table defines the fields for normal devices and bridge devices, and
1143	* the order in which they need to be restored.
1144	*/
1145	static const struct PciField
1146	{
1147	uint8_t off;
1148	uint8_t cb;
1149	uint8_t fWritable;
1150	uint8_t fBridge;
1151	const char *pszName;
1152	} s_aFields[] =
1153	{
1154	/* off,cb,fW,fB, pszName */
1155	{ VBOX_PCI_VENDOR_ID, 2, 0, 3, "VENDOR_ID" },
1156	{ VBOX_PCI_DEVICE_ID, 2, 0, 3, "DEVICE_ID" },
1157	{ VBOX_PCI_STATUS, 2, 1, 3, "STATUS" },
1158	{ VBOX_PCI_REVISION_ID, 1, 0, 3, "REVISION_ID" },
1159	{ VBOX_PCI_CLASS_PROG, 1, 0, 3, "CLASS_PROG" },
1160	{ VBOX_PCI_CLASS_SUB, 1, 0, 3, "CLASS_SUB" },
1161	{ VBOX_PCI_CLASS_BASE, 1, 0, 3, "CLASS_BASE" },
1162	{ VBOX_PCI_CACHE_LINE_SIZE, 1, 1, 3, "CACHE_LINE_SIZE" },
1163	{ VBOX_PCI_LATENCY_TIMER, 1, 1, 3, "LATENCY_TIMER" },
1164	{ VBOX_PCI_HEADER_TYPE, 1, 0, 3, "HEADER_TYPE" },
1165	{ VBOX_PCI_BIST, 1, 1, 3, "BIST" },
1166	{ VBOX_PCI_BASE_ADDRESS_0, 4, 1, 3, "BASE_ADDRESS_0" },
1167	{ VBOX_PCI_BASE_ADDRESS_1, 4, 1, 3, "BASE_ADDRESS_1" },
1168	{ VBOX_PCI_BASE_ADDRESS_2, 4, 1, 1, "BASE_ADDRESS_2" },
1169	{ VBOX_PCI_PRIMARY_BUS, 1, 1, 2, "PRIMARY_BUS" }, // fWritable = ??
1170	{ VBOX_PCI_SECONDARY_BUS, 1, 1, 2, "SECONDARY_BUS" }, // fWritable = ??
1171	{ VBOX_PCI_SUBORDINATE_BUS, 1, 1, 2, "SUBORDINATE_BUS" }, // fWritable = ??
1172	{ VBOX_PCI_SEC_LATENCY_TIMER, 1, 1, 2, "SEC_LATENCY_TIMER" }, // fWritable = ??
1173	{ VBOX_PCI_BASE_ADDRESS_3, 4, 1, 1, "BASE_ADDRESS_3" },
1174	{ VBOX_PCI_IO_BASE, 1, 1, 2, "IO_BASE" }, // fWritable = ??
1175	{ VBOX_PCI_IO_LIMIT, 1, 1, 2, "IO_LIMIT" }, // fWritable = ??
1176	{ VBOX_PCI_SEC_STATUS, 2, 1, 2, "SEC_STATUS" }, // fWritable = ??
1177	{ VBOX_PCI_BASE_ADDRESS_4, 4, 1, 1, "BASE_ADDRESS_4" },
1178	{ VBOX_PCI_MEMORY_BASE, 2, 1, 2, "MEMORY_BASE" }, // fWritable = ??
1179	{ VBOX_PCI_MEMORY_LIMIT, 2, 1, 2, "MEMORY_LIMIT" }, // fWritable = ??
1180	{ VBOX_PCI_BASE_ADDRESS_5, 4, 1, 1, "BASE_ADDRESS_5" },
1181	{ VBOX_PCI_PREF_MEMORY_BASE, 2, 1, 2, "PREF_MEMORY_BASE" }, // fWritable = ??
1182	{ VBOX_PCI_PREF_MEMORY_LIMIT, 2, 1, 2, "PREF_MEMORY_LIMIT" }, // fWritable = ??
1183	{ VBOX_PCI_CARDBUS_CIS, 4, 1, 1, "CARDBUS_CIS" }, // fWritable = ??
1184	{ VBOX_PCI_PREF_BASE_UPPER32, 4, 1, 2, "PREF_BASE_UPPER32" }, // fWritable = ??
1185	{ VBOX_PCI_SUBSYSTEM_VENDOR_ID, 2, 0, 1, "SUBSYSTEM_VENDOR_ID" },// fWritable = !?
1186	{ VBOX_PCI_PREF_LIMIT_UPPER32, 4, 1, 2, "PREF_LIMIT_UPPER32" },// fWritable = ??
1187	{ VBOX_PCI_SUBSYSTEM_ID, 2, 0, 1, "SUBSYSTEM_ID" }, // fWritable = !?
1188	{ VBOX_PCI_ROM_ADDRESS, 4, 1, 1, "ROM_ADDRESS" }, // fWritable = ?!
1189	{ VBOX_PCI_IO_BASE_UPPER16, 2, 1, 2, "IO_BASE_UPPER16" }, // fWritable = ?!
1190	{ VBOX_PCI_IO_LIMIT_UPPER16, 2, 1, 2, "IO_LIMIT_UPPER16" }, // fWritable = ?!
1191	{ VBOX_PCI_CAPABILITY_LIST, 4, 0, 3, "CAPABILITY_LIST" }, // fWritable = !? cb=!?
1192	{ VBOX_PCI_RESERVED_38, 4, 1, 1, "RESERVED_38" }, // ???
1193	{ VBOX_PCI_ROM_ADDRESS_BR, 4, 1, 2, "ROM_ADDRESS_BR" }, // fWritable = !? cb=!? fBridge=!?
1194	{ VBOX_PCI_INTERRUPT_LINE, 1, 1, 3, "INTERRUPT_LINE" }, // fBridge=??
1195	{ VBOX_PCI_INTERRUPT_PIN, 1, 0, 3, "INTERRUPT_PIN" }, // fBridge=??
1196	{ VBOX_PCI_MIN_GNT, 1, 0, 1, "MIN_GNT" },
1197	{ VBOX_PCI_BRIDGE_CONTROL, 2, 1, 2, "BRIDGE_CONTROL" }, // fWritable = !?
1198	{ VBOX_PCI_MAX_LAT, 1, 0, 1, "MAX_LAT" },
1199	/* The COMMAND register must come last as it requires the ADDRESS
1200	registers to be restored before we pretent to change it from 0 to
1201	whatever value the guest assigned it. */
1202	{ VBOX_PCI_COMMAND, 2, 1, 3, "COMMAND" },
1203	};
1204
1205	#ifdef RT_STRICT
1206	/* Check that we've got full register coverage. */
1207	uint32_t bmDevice[0x40 / 32];
1208	uint32_t bmBridge[0x40 / 32];
1209	RT_ZERO(bmDevice);
1210	RT_ZERO(bmBridge);
1211	for (uint32_t i = 0; i < RT_ELEMENTS(s_aFields); i++)
1212	{
1213	uint8_t off = s_aFields[i].off;
1214	uint8_t cb = s_aFields[i].cb;
1215	uint8_t f = s_aFields[i].fBridge;
1216	while (cb-- > 0)
1217	{
1218	if (f & 1) AssertMsg(!ASMBitTest(bmDevice, off), ("%#x\n", off));
1219	if (f & 2) AssertMsg(!ASMBitTest(bmBridge, off), ("%#x\n", off));
1220	if (f & 1) ASMBitSet(bmDevice, off);
1221	if (f & 2) ASMBitSet(bmBridge, off);
1222	off++;
1223	}
1224	}
1225	for (uint32_t off = 0; off < 0x40; off++)
1226	{
1227	AssertMsg(ASMBitTest(bmDevice, off), ("%#x\n", off));
1228	AssertMsg(ASMBitTest(bmBridge, off), ("%#x\n", off));
1229	}
1230	#endif
1231
1232	/*
1233	* Loop thru the fields covering the 64 bytes of standard registers.
1234	*/
1235	uint8_t const fBridge = fIsBridge ? 2 : 1;
1236	Assert(!pciDevIsPassthrough(pDev));
1237	uint8_t *pbDstConfig = &pDev->config[0];
1238
1239	for (uint32_t i = 0; i < RT_ELEMENTS(s_aFields); i++)
1240	if (s_aFields[i].fBridge & fBridge)
1241	{
1242	uint8_t const off = s_aFields[i].off;
1243	uint8_t const cb = s_aFields[i].cb;
1244	uint32_t u32Src;
1245	uint32_t u32Dst;
1246	switch (cb)
1247	{
1248	case 1:
1249	u32Src = pbSrcConfig[off];
1250	u32Dst = pbDstConfig[off];
1251	break;
1252	case 2:
1253	u32Src = (uint16_t const )&pbSrcConfig[off];
1254	u32Dst = (uint16_t const )&pbDstConfig[off];
1255	break;
1256	case 4:
1257	u32Src = (uint32_t const )&pbSrcConfig[off];
1258	u32Dst = (uint32_t const )&pbDstConfig[off];
1259	break;
1260	default:
1261	AssertFailed();
1262	continue;
1263	}
1264
1265	if ( u32Src != u32Dst
1266	\|\| off == VBOX_PCI_COMMAND)
1267	{
1268	if (u32Src != u32Dst)
1269	{
1270	if (!s_aFields[i].fWritable)
1271	LogRel(("PCI: %8s/%u: %2u-bit field %s: %x -> %x - !READ ONLY!\n",
1272	pDev->name, pDev->pDevIns->iInstance, cb*8, s_aFields[i].pszName, u32Dst, u32Src));
1273	else
1274	LogRel(("PCI: %8s/%u: %2u-bit field %s: %x -> %x\n",
1275	pDev->name, pDev->pDevIns->iInstance, cb*8, s_aFields[i].pszName, u32Dst, u32Src));
1276	}
1277	if (off == VBOX_PCI_COMMAND)
1278	PCIDevSetCommand(pDev, 0); /* For remapping, see ich9pciR3CommonLoadExec. */
1279	pDev->Int.s.pfnConfigWrite(pDev, off, u32Src, cb);
1280	}
1281	}
1282
1283	/*
1284	* The device dependent registers.
1285	*
1286	* We will not use ConfigWrite here as we have no clue about the size
1287	* of the registers, so the device is responsible for correctly
1288	* restoring functionality governed by these registers.
1289	*/
1290	for (uint32_t off = 0x40; off < sizeof(pDev->config); off++)
1291	if (pbDstConfig[off] != pbSrcConfig[off])
1292	{
1293	LogRel(("PCI: %8s/%u: register %02x: %02x -> %02x\n",
1294	pDev->name, pDev->pDevIns->iInstance, off, pbDstConfig[off], pbSrcConfig[off])); /** @todo make this Log() later. */
1295	pbDstConfig[off] = pbSrcConfig[off];
1296	}
1297	}
1298
1299	/**
1300	* Common worker for ich9pciR3LoadExec and ich9pcibridgeR3LoadExec.
1301	*
1302	* @returns VBox status code.
1303	* @param pBus The bus which data is being loaded.
1304	* @param pSSM The saved state handle.
1305	* @param uVersion The data version.
1306	* @param uPass The pass.
1307	*/
1308	static DECLCALLBACK(int) ich9pciR3CommonLoadExec(PICH9PCIBUS pBus, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1309	{
1310	uint32_t u32;
1311	uint32_t i;
1312	int rc;
1313
1314	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
1315	if (uVersion != VBOX_ICH9PCI_SAVED_STATE_VERSION_CURRENT)
1316	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1317
1318	/*
1319	* Iterate thru all the devices and write 0 to the COMMAND register so
1320	* that all the memory is unmapped before we start restoring the saved
1321	* mapping locations.
1322	*
1323	* The register value is restored afterwards so we can do proper
1324	* LogRels in pciR3CommonRestoreConfig.
1325	*/
1326	for (i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
1327	{
1328	PPCIDEVICE pDev = pBus->apDevices[i];
1329	if (pDev)
1330	{
1331	uint16_t u16 = PCIDevGetCommand(pDev);
1332	pDev->Int.s.pfnConfigWrite(pDev, VBOX_PCI_COMMAND, 0, 2);
1333	PCIDevSetCommand(pDev, u16);
1334	Assert(PCIDevGetCommand(pDev) == u16);
1335	}
1336	}
1337
1338	void *pvMsixPage = RTMemTmpAllocZ(0x1000);
1339	AssertReturn(pvMsixPage, VERR_NO_TMP_MEMORY);
1340
1341	/*
1342	* Iterate all the devices.
1343	*/
1344	for (i = 0;; i++)
1345	{
1346	PPCIDEVICE pDev;
1347	PCIDEVICE DevTmp;
1348
1349	/* index / terminator */
1350	rc = SSMR3GetU32(pSSM, &u32);
1351	if (RT_FAILURE(rc))
1352	break;
1353	if (u32 == (uint32_t)~0)
1354	break;
1355	AssertMsgBreak(u32 < RT_ELEMENTS(pBus->apDevices) && u32 >= i, ("u32=%#x i=%#x\n", u32, i));
1356
1357	/* skip forward to the device checking that no new devices are present. */
1358	for (; i < u32; i++)
1359	{
1360	pDev = pBus->apDevices[i];
1361	if (pDev)
1362	{
1363	LogRel(("New device in slot %#x, %s (vendor=%#06x device=%#06x)\n", i, pDev->name,
1364	PCIDevGetVendorId(pDev), PCIDevGetDeviceId(pDev)));
1365	if (SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT)
1366	{
1367	rc = SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("New device in slot %#x, %s (vendor=%#06x device=%#06x)"),
1368	i, pDev->name, PCIDevGetVendorId(pDev), PCIDevGetDeviceId(pDev));
1369	break;
1370	}
1371	}
1372	}
1373	if (RT_FAILURE(rc))
1374	break;
1375
1376	/* get the data */
1377	DevTmp.Int.s.fFlags = 0;
1378	DevTmp.Int.s.u8MsiCapOffset = 0;
1379	DevTmp.Int.s.u8MsiCapSize = 0;
1380	DevTmp.Int.s.u8MsixCapOffset = 0;
1381	DevTmp.Int.s.u8MsixCapSize = 0;
1382	DevTmp.Int.s.uIrqPinState = ~0; /* Invalid value in case we have an older saved state to force a state change in pciSetIrq. */
1383	SSMR3GetMem(pSSM, DevTmp.config, sizeof(DevTmp.config));
1384
1385	SSMR3GetU32(pSSM, &DevTmp.Int.s.fFlags);
1386	SSMR3GetS32(pSSM, &DevTmp.Int.s.uIrqPinState);
1387	SSMR3GetU8(pSSM, &DevTmp.Int.s.u8MsiCapOffset);
1388	SSMR3GetU8(pSSM, &DevTmp.Int.s.u8MsiCapSize);
1389	SSMR3GetU8(pSSM, &DevTmp.Int.s.u8MsixCapOffset);
1390	rc = SSMR3GetU8(pSSM, &DevTmp.Int.s.u8MsixCapSize);
1391	if (RT_FAILURE(rc))
1392	break;
1393
1394	/* Load MSI-X page state */
1395	if (DevTmp.Int.s.u8MsixCapOffset != 0)
1396	{
1397	Assert(pvMsixPage != NULL);
1398	rc = SSMR3GetMem(pSSM, pvMsixPage, 0x1000);
1399	if (RT_FAILURE(rc))
1400	break;
1401	}
1402
1403	/* check that it's still around. */
1404	pDev = pBus->apDevices[i];
1405	if (!pDev)
1406	{
1407	LogRel(("Device in slot %#x has been removed! vendor=%#06x device=%#06x\n", i,
1408	PCIDevGetVendorId(&DevTmp), PCIDevGetDeviceId(&DevTmp)));
1409	if (SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT)
1410	{
1411	rc = SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Device in slot %#x has been removed! vendor=%#06x device=%#06x"),
1412	i, PCIDevGetVendorId(&DevTmp), PCIDevGetDeviceId(&DevTmp));
1413	break;
1414	}
1415	continue;
1416	}
1417
1418	/* match the vendor id assuming that this will never be changed. */
1419	if (PCIDevGetVendorId(&DevTmp) != PCIDevGetVendorId(pDev))
1420	{
1421	rc = SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Device in slot %#x (%s) vendor id mismatch! saved=%.4Rhxs current=%.4Rhxs"),
1422	i, pDev->name, PCIDevGetVendorId(&DevTmp), PCIDevGetVendorId(pDev));
1423	break;
1424	}
1425
1426	/* commit the loaded device config. */
1427	Assert(!pciDevIsPassthrough(pDev));
1428	pciR3CommonRestoreConfig(pDev, &DevTmp.config[0], false ); /** @todo fix bridge fun! */
1429
1430	pDev->Int.s.uIrqPinState = DevTmp.Int.s.uIrqPinState;
1431	pDev->Int.s.u8MsiCapOffset = DevTmp.Int.s.u8MsiCapOffset;
1432	pDev->Int.s.u8MsiCapSize = DevTmp.Int.s.u8MsiCapSize;
1433	pDev->Int.s.u8MsixCapOffset = DevTmp.Int.s.u8MsixCapOffset;
1434	pDev->Int.s.u8MsixCapSize = DevTmp.Int.s.u8MsixCapSize;
1435	if (DevTmp.Int.s.u8MsixCapSize != 0)
1436	{
1437	Assert(pDev->Int.s.pMsixPageR3 != NULL);
1438	memcpy(pDev->Int.s.pMsixPageR3, pvMsixPage, 0x1000);
1439	}
1440	}
1441
1442	RTMemTmpFree(pvMsixPage);
1443
1444	return rc;
1445	}
1446
1447	/**
1448	* Loads a saved PCI device state.
1449	*
1450	* @returns VBox status code.
1451	* @param pDevIns Device instance of the PCI Bus.
1452	* @param pPciDev Pointer to PCI device.
1453	* @param pSSM The handle to the saved state.
1454	*/
1455	static DECLCALLBACK(int) ich9pciGenericLoadExec(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PSSMHANDLE pSSM)
1456	{
1457	NOREF(pDevIns);
1458	Assert(!pciDevIsPassthrough(pPciDev));
1459	return SSMR3GetMem(pSSM, &pPciDev->config[0], sizeof(pPciDev->config));
1460	}
1461
1462	static DECLCALLBACK(int) ich9pciR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1463	{
1464	PICH9PCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
1465	PICH9PCIBUS pBus = &pThis->aPciBus;
1466	uint32_t u32;
1467	int rc;
1468
1469	/* We ignore this version as there's no saved state with it anyway */
1470	if (uVersion == VBOX_ICH9PCI_SAVED_STATE_VERSION_NOMSI)
1471	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1472	if (uVersion > VBOX_ICH9PCI_SAVED_STATE_VERSION_MSI)
1473	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1474
1475	/*
1476	* Bus state data.
1477	*/
1478	SSMR3GetU32(pSSM, &pThis->uConfigReg);
1479
1480	/*
1481	* Load IRQ states.
1482	*/
1483	for (int i = 0; i < PCI_APIC_IRQ_PINS; i++)
1484	SSMR3GetU32(pSSM, (uint32_t*)&pThis->uaPciApicIrqLevels[i]);
1485
1486	/* separator */
1487	rc = SSMR3GetU32(pSSM, &u32);
1488	if (RT_FAILURE(rc))
1489	return rc;
1490	if (u32 != (uint32_t)~0)
1491	AssertMsgFailedReturn(("u32=%#x\n", u32), rc);
1492
1493	return ich9pciR3CommonLoadExec(pBus, pSSM, uVersion, uPass);
1494	}
1495
1496	static DECLCALLBACK(int) ich9pcibridgeR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1497	{
1498	PICH9PCIBUS pThis = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
1499	if (uVersion > VBOX_ICH9PCI_SAVED_STATE_VERSION_MSI)
1500	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1501	return ich9pciR3CommonLoadExec(pThis, pSSM, uVersion, uPass);
1502	}
1503
1504	static uint32_t ich9pciConfigRead(PICH9PCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t len)
1505	{
1506	/* Will only work in LSB case */
1507	uint32_t u32Val;
1508	PciAddress aPciAddr;
1509
1510	aPciAddr.iBus = uBus;
1511	aPciAddr.iDeviceFunc = uDevFn;
1512	aPciAddr.iRegister = addr;
1513
1514	/* cannot be rescheduled, as already in R3 */
1515	int rc = ich9pciDataReadAddr(pGlobals, &aPciAddr, len, &u32Val, VERR_INTERNAL_ERROR);
1516	AssertRC(rc);
1517	return u32Val;
1518	}
1519
1520	static void ich9pciConfigWrite(PICH9PCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t val, uint32_t len)
1521	{
1522	PciAddress aPciAddr;
1523
1524	aPciAddr.iBus = uBus;
1525	aPciAddr.iDeviceFunc = uDevFn;
1526	aPciAddr.iRegister = addr;
1527
1528	/* cannot be rescheduled, as already in R3 */
1529	int rc = ich9pciDataWriteAddr(pGlobals, &aPciAddr, val, len, VERR_INTERNAL_ERROR);
1530	AssertRC(rc);
1531	}
1532
1533	static void ich9pciSetRegionAddress(PICH9PCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, int iRegion, uint64_t addr)
1534	{
1535	uint32_t uReg = ich9pciGetRegionReg(iRegion);
1536
1537	/* Read memory type first. */
1538	uint8_t uResourceType = ich9pciConfigRead(pGlobals, uBus, uDevFn, uReg, 1);
1539	/* Read command register. */
1540	uint16_t uCmd = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_COMMAND, 2);
1541
1542	Log(("Set region address: %02x:%02x.%d region %d address=%lld\n",
1543	uBus, uDevFn>>3, uDevFn&7, addr));
1544
1545	if ( iRegion == PCI_ROM_SLOT )
1546	uCmd \|= PCI_COMMAND_MEMACCESS;
1547	else if ((uResourceType & PCI_ADDRESS_SPACE_IO) == PCI_ADDRESS_SPACE_IO)
1548	uCmd \|= PCI_COMMAND_IOACCESS; /* Enable I/O space access. */
1549	else /* The region is MMIO. */
1550	uCmd \|= PCI_COMMAND_MEMACCESS; /* Enable MMIO access. */
1551
1552	bool f64Bit = (uResourceType & PCI_ADDRESS_SPACE_BAR64) != 0;
1553
1554	/* Write address of the device. */
1555	ich9pciConfigWrite(pGlobals, uBus, uDevFn, uReg, (uint32_t)addr, 4);
1556	if (f64Bit)
1557	ich9pciConfigWrite(pGlobals, uBus, uDevFn, uReg + 4, (uint32_t)(addr >> 32), 4);
1558
1559	/* enable memory mappings */
1560	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_COMMAND, uCmd, 2);
1561	}
1562
1563
1564	static void ich9pciBiosInitBridge(PICH9PCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn)
1565	{
1566	Log(("BIOS init bridge: %02x::%02x.%d\n", uBus, uDevFn >> 3, uDevFn & 7));
1567
1568	/*
1569	* The I/O range for the bridge must be aligned to a 4KB boundary.
1570	* This does not change anything really as the access to the device is not going
1571	* through the bridge but we want to be compliant to the spec.
1572	*/
1573	if ((pGlobals->uPciBiosIo % 4096) != 0)
1574	{
1575	pGlobals->uPciBiosIo = RT_ALIGN_32(pGlobals->uPciBiosIo, 4*1024);
1576	Log(("%s: Aligned I/O start address. New address %#x\n", __FUNCTION__, pGlobals->uPciBiosIo));
1577	}
1578	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_IO_BASE, (pGlobals->uPciBiosIo >> 8) & 0xf0, 1);
1579
1580	/* The MMIO range for the bridge must be aligned to a 1MB boundary. */
1581	if ((pGlobals->uPciBiosMmio % (1024 * 1024)) != 0)
1582	{
1583	pGlobals->uPciBiosMmio = RT_ALIGN_32(pGlobals->uPciBiosMmio, 1024*1024);
1584	Log(("%s: Aligned MMIO start address. New address %#x\n", __FUNCTION__, pGlobals->uPciBiosMmio));
1585	}
1586	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_MEMORY_BASE, (pGlobals->uPciBiosMmio >> 16) & UINT32_C(0xffff0), 2);
1587
1588	/* Save values to compare later to. */
1589	uint32_t u32IoAddressBase = pGlobals->uPciBiosIo;
1590	uint32_t u32MMIOAddressBase = pGlobals->uPciBiosMmio;
1591	uint8_t uBridgeBus = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_SECONDARY_BUS, 1);
1592
1593	/* Init devices behind the bridge and possibly other bridges as well. */
1594	for (int iDev = 0; iDev <= 255; iDev++)
1595	ich9pciBiosInitDevice(pGlobals, uBridgeBus, iDev);
1596
1597	/*
1598	* Set I/O limit register. If there is no device with I/O space behind the bridge
1599	* we set a lower value than in the base register.
1600	* The result with a real bridge is that no I/O transactions are passed to the secondary
1601	* interface. Again this doesn't really matter here but we want to be compliant to the spec.
1602	*/
1603	if ((u32IoAddressBase != pGlobals->uPciBiosIo) && ((pGlobals->uPciBiosIo % 4096) != 0))
1604	{
1605	/* The upper boundary must be one byte less than a 4KB boundary. */
1606	pGlobals->uPciBiosIo = RT_ALIGN_32(pGlobals->uPciBiosIo, 4*1024);
1607	}
1608
1609	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_IO_LIMIT, ((pGlobals->uPciBiosIo >> 8) & 0xf0) - 1, 1);
1610
1611	/* Same with the MMIO limit register but with 1MB boundary here. */
1612	if ((u32MMIOAddressBase != pGlobals->uPciBiosMmio) && ((pGlobals->uPciBiosMmio % (1024 * 1024)) != 0))
1613	{
1614	/* The upper boundary must be one byte less than a 1MB boundary. */
1615	pGlobals->uPciBiosMmio = RT_ALIGN_32(pGlobals->uPciBiosMmio, 1024*1024);
1616	}
1617	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_MEMORY_LIMIT, ((pGlobals->uPciBiosMmio >> 16) & UINT32_C(0xfff0)) - 1, 2);
1618
1619	/*
1620	* Set the prefetch base and limit registers. We currently have no device with a prefetchable region
1621	* which may be behind a bridge. That's why it is unconditionally disabled here atm by writing a higher value into
1622	* the base register than in the limit register.
1623	*/
1624	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_MEMORY_BASE, 0xfff0, 2);
1625	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_MEMORY_LIMIT, 0x0, 2);
1626	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_BASE_UPPER32, 0x00, 4);
1627	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_LIMIT_UPPER32, 0x00, 4);
1628	}
1629
1630	static void ich9pciBiosInitDevice(PICH9PCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn)
1631	{
1632	uint16_t uDevClass, uVendor, uDevice;
1633	uint8_t uCmd;
1634
1635	uDevClass = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_CLASS_DEVICE, 2);
1636	uVendor = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_VENDOR_ID, 2);
1637	uDevice = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_DEVICE_ID, 2);
1638
1639	/* If device is present */
1640	if (uVendor == 0xffff)
1641	return;
1642
1643	Log(("BIOS init device: %02x:%02x.%d\n", uBus, uDevFn >> 3, uDevFn & 7));
1644
1645	switch (uDevClass)
1646	{
1647	case 0x0101:
1648	/* IDE controller */
1649	ich9pciConfigWrite(pGlobals, uBus, uDevFn, 0x40, 0x8000, 2); /* enable IDE0 */
1650	ich9pciConfigWrite(pGlobals, uBus, uDevFn, 0x42, 0x8000, 2); /* enable IDE1 */
1651	goto default_map;
1652	break;
1653	case 0x0300:
1654	/* VGA controller */
1655	if (uVendor != 0x80ee)
1656	goto default_map;
1657	/* VGA: map frame buffer to default Bochs VBE address */
1658	ich9pciSetRegionAddress(pGlobals, uBus, uDevFn, 0, 0xE0000000);
1659	/*
1660	* Legacy VGA I/O ports are implicitly decoded by a VGA class device. But
1661	* only the framebuffer (i.e., a memory region) is explicitly registered via
1662	* ich9pciSetRegionAddress, so I/O decoding must be enabled manually.
1663	*/
1664	uCmd = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_COMMAND, 1);
1665	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_COMMAND,
1666	/* Enable I/O space access. */
1667	uCmd \| PCI_COMMAND_IOACCESS,
1668	1);
1669	break;
1670	case 0x0604:
1671	/* PCI-to-PCI bridge. */
1672	AssertMsg(pGlobals->uBus < 255, ("Too many bridges on the bus\n"));
1673	ich9pciBiosInitBridge(pGlobals, uBus, uDevFn);
1674	break;
1675	default:
1676	default_map:
1677	{
1678	/* default memory mappings */
1679	/*
1680	* We ignore ROM region here.
1681	*/
1682	for (int iRegion = 0; iRegion < (PCI_NUM_REGIONS-1); iRegion++)
1683	{
1684	uint32_t u32Address = ich9pciGetRegionReg(iRegion);
1685
1686	/* Calculate size - we write all 1s into the BAR, and then evaluate which bits
1687	are cleared. . */
1688	uint8_t u8ResourceType = ich9pciConfigRead(pGlobals, uBus, uDevFn, u32Address, 1);
1689
1690	bool f64bit = (u8ResourceType & PCI_ADDRESS_SPACE_BAR64) != 0;
1691	bool fIsPio = ((u8ResourceType & PCI_COMMAND_IOACCESS) == PCI_COMMAND_IOACCESS);
1692	uint64_t cbRegSize64 = 0;
1693
1694	if (f64bit)
1695	{
1696	ich9pciConfigWrite(pGlobals, uBus, uDevFn, u32Address, UINT32_C(0xffffffff), 4);
1697	ich9pciConfigWrite(pGlobals, uBus, uDevFn, u32Address+4, UINT32_C(0xffffffff), 4);
1698	cbRegSize64 = ich9pciConfigRead(pGlobals, uBus, uDevFn, u32Address, 4);
1699	cbRegSize64 \|= ((uint64_t)ich9pciConfigRead(pGlobals, uBus, uDevFn, u32Address+4, 4) << 32);
1700	cbRegSize64 &= ~UINT64_C(0x0f);
1701	cbRegSize64 = (~cbRegSize64) + 1;
1702
1703	/* No 64-bit PIO regions possible. */
1704	Assert((u8ResourceType & PCI_COMMAND_IOACCESS) == 0);
1705	}
1706	else
1707	{
1708	uint32_t cbRegSize32;
1709	ich9pciConfigWrite(pGlobals, uBus, uDevFn, u32Address, UINT32_C(0xffffffff), 4);
1710	cbRegSize32 = ich9pciConfigRead(pGlobals, uBus, uDevFn, u32Address, 4);
1711
1712	/* Clear resource information depending on resource type. */
1713	if (fIsPio) /* PIO */
1714	cbRegSize32 &= ~UINT32_C(0x01);
1715	else /* MMIO */
1716	cbRegSize32 &= ~UINT32_C(0x0f);
1717
1718	/*
1719	* Invert all bits and add 1 to get size of the region.
1720	* (From PCI implementation note)
1721	*/
1722	if (fIsPio && (cbRegSize32 & UINT32_C(0xffff0000)) == 0)
1723	cbRegSize32 = (~(cbRegSize32 \| UINT32_C(0xffff0000))) + 1;
1724	else
1725	cbRegSize32 = (~cbRegSize32) + 1;
1726
1727	cbRegSize64 = cbRegSize32;
1728	}
1729	Assert(cbRegSize64 == (uint32_t)cbRegSize64);
1730	Log2(("%s: Size of region %u for device %d on bus %d is %lld\n", __FUNCTION__, iRegion, uDevFn, uBus, cbRegSize64));
1731
1732	if (cbRegSize64)
1733	{
1734	uint32_t cbRegSize32 = (uint32_t)cbRegSize64;
1735	uint32_t* paddr = fIsPio ? &pGlobals->uPciBiosIo : &pGlobals->uPciBiosMmio;
1736	paddr = (paddr + cbRegSize32 - 1) & ~(cbRegSize32 - 1);
1737	Log(("%s: Start address of %s region %u is %#x\n", __FUNCTION__, (fIsPio ? "I/O" : "MMIO"), iRegion, *paddr));
1738	ich9pciSetRegionAddress(pGlobals, uBus, uDevFn, iRegion, *paddr);
1739	*paddr += cbRegSize32;
1740	Log2(("%s: New address is %#x\n", __FUNCTION__, *paddr));
1741
1742	if (f64bit)
1743	iRegion++; /* skip next region */
1744	}
1745	}
1746	break;
1747	}
1748	}
1749
1750	/* map the interrupt */
1751	uint32_t iPin = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_INTERRUPT_PIN, 1);
1752	if (iPin != 0)
1753	{
1754	iPin--;
1755
1756	if (uBus != 0)
1757	{
1758	/* Find bus this device attached to. */
1759	PICH9PCIBUS pBus = &pGlobals->aPciBus;
1760	while (1)
1761	{
1762	PPCIDEVICE pBridge = ich9pciFindBridge(pBus, uBus);
1763	if (!pBridge)
1764	{
1765	Assert(false);
1766	break;
1767	}
1768	if (uBus == PCIDevGetByte(pBridge, VBOX_PCI_SECONDARY_BUS))
1769	{
1770	/* OK, found bus this device attached to. */
1771	break;
1772	}
1773	pBus = PDMINS_2_DATA(pBridge->pDevIns, PICH9PCIBUS);
1774	}
1775
1776	/* We need to go up to the host bus to see which irq pin this
1777	* device will use there. See logic in ich9pcibridgeSetIrq().
1778	*/
1779	while (pBus->iBus != 0)
1780	{
1781	/* Get the pin the device would assert on the bridge. */
1782	iPin = ((pBus->aPciDev.devfn >> 3) + iPin) & 3;
1783	pBus = pBus->aPciDev.Int.s.pBusR3;
1784	};
1785	}
1786
1787	int iIrq = aPciIrqs[ich9pciSlotGetPirq(uBus, uDevFn, iPin)];
1788	Log(("Using pin %d and IRQ %d for device %02x:%02x.%d\n",
1789	iPin, iIrq, uBus, uDevFn>>3, uDevFn&7));
1790	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_INTERRUPT_LINE, iIrq, 1);
1791	}
1792	}
1793
1794	/* Initializes bridges registers used for routing. */
1795	static void ich9pciInitBridgeTopology(PICH9PCIGLOBALS pGlobals, PICH9PCIBUS pBus)
1796	{
1797	PPCIDEVICE pBridgeDev = &pBus->aPciDev;
1798
1799	/* Set only if we are not on the root bus, it has no primary bus attached. */
1800	if (pGlobals->uBus != 0)
1801	{
1802	PCIDevSetByte(pBridgeDev, VBOX_PCI_PRIMARY_BUS, pGlobals->uBus);
1803	PCIDevSetByte(pBridgeDev, VBOX_PCI_SECONDARY_BUS, pGlobals->uBus);
1804	}
1805
1806	pGlobals->uBus++;
1807	for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
1808	{
1809	PPCIDEVICE pBridge = pBus->papBridgesR3[iBridge];
1810	AssertMsg(pBridge && pciDevIsPci2PciBridge(pBridge),
1811	("Device is not a PCI bridge but on the list of PCI bridges\n"));
1812	PICH9PCIBUS pChildBus = PDMINS_2_DATA(pBridge->pDevIns, PICH9PCIBUS);
1813	ich9pciInitBridgeTopology(pGlobals, pChildBus);
1814	}
1815	PCIDevSetByte(pBridgeDev, VBOX_PCI_SUBORDINATE_BUS, pGlobals->uBus);
1816	Log2(("ich9pciInitBridgeTopology: for bus %p: primary=%d secondary=%d subordinate=%d\n",
1817	pBus,
1818	PCIDevGetByte(pBridgeDev, VBOX_PCI_PRIMARY_BUS),
1819	PCIDevGetByte(pBridgeDev, VBOX_PCI_SECONDARY_BUS),
1820	PCIDevGetByte(pBridgeDev, VBOX_PCI_SUBORDINATE_BUS)
1821	));
1822	}
1823
1824
1825	static DECLCALLBACK(int) ich9pciFakePCIBIOS(PPDMDEVINS pDevIns)
1826	{
1827	PICH9PCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
1828	PVM pVM = PDMDevHlpGetVM(pDevIns);
1829	Assert(pVM);
1830
1831	/*
1832	* Set the start addresses.
1833	*/
1834	pGlobals->uPciBiosIo = 0xd000;
1835	pGlobals->uPciBiosMmio = UINT32_C(0xf0000000);
1836	pGlobals->uBus = 0;
1837
1838	/*
1839	* Assign bridge topology, for further routing to work.
1840	*/
1841	PICH9PCIBUS pBus = &pGlobals->aPciBus;
1842	ich9pciInitBridgeTopology(pGlobals, pBus);
1843
1844	/*
1845	* Init the devices.
1846	*/
1847	for (int i = 0; i < 256; i++)
1848	{
1849	ich9pciBiosInitDevice(pGlobals, 0, i);
1850	}
1851
1852	return VINF_SUCCESS;
1853	}
1854
1855	static DECLCALLBACK(uint32_t) ich9pciConfigReadDev(PCIDevice *aDev, uint32_t u32Address, unsigned len)
1856	{
1857	if ((u32Address + len) > 256 && (u32Address + len) < 4096)
1858	{
1859	LogRel(("Read from extended register %d fallen back to generic code\n",
1860	u32Address));
1861	return 0;
1862	}
1863
1864	AssertMsgReturn(u32Address + len <= 256, ("Read after the end of PCI config space\n"),
1865	0);
1866	if ( pciDevIsMsiCapable(aDev)
1867	&& (u32Address >= aDev->Int.s.u8MsiCapOffset)
1868	&& (u32Address < (unsigned)(aDev->Int.s.u8MsiCapOffset + aDev->Int.s.u8MsiCapSize))
1869	)
1870	{
1871	return MsiPciConfigRead(aDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pDevIns), aDev, u32Address, len);
1872	}
1873
1874	if ( pciDevIsMsixCapable(aDev)
1875	&& (u32Address >= aDev->Int.s.u8MsixCapOffset)
1876	&& (u32Address < (unsigned)(aDev->Int.s.u8MsixCapOffset + aDev->Int.s.u8MsixCapSize))
1877	)
1878	{
1879	return MsixPciConfigRead(aDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pDevIns), aDev, u32Address, len);
1880	}
1881
1882	AssertMsgReturn(u32Address + len <= 256, ("Read after end of PCI config space\n"),
1883	0);
1884	switch (len)
1885	{
1886	case 1:
1887	return PCIDevGetByte(aDev, u32Address);
1888	case 2:
1889	return PCIDevGetWord(aDev, u32Address);
1890	case 4:
1891	return PCIDevGetDWord(aDev, u32Address);
1892	default:
1893	Assert(false);
1894	return 0;
1895	}
1896	}
1897
1898	DECLINLINE(void) ich9pciWriteBarByte(PCIDevice *aDev, int iRegion, int iOffset, uint8_t u8Val)
1899	{
1900	PCIIORegion * pRegion = &aDev->Int.s.aIORegions[iRegion];
1901	int64_t iRegionSize = pRegion->size;
1902
1903	Log3(("ich9pciWriteBarByte: region=%d off=%d val=%x size=%d\n",
1904	iRegion, iOffset, u8Val, iRegionSize));
1905
1906	if (iOffset > 3)
1907	Assert((aDev->Int.s.aIORegions[iRegion].type & PCI_ADDRESS_SPACE_BAR64) != 0);
1908
1909	/* Check if we're writing to upper part of 64-bit BAR. */
1910	if (aDev->Int.s.aIORegions[iRegion].type == 0xff)
1911	{
1912	ich9pciWriteBarByte(aDev, iRegion-1, iOffset+4, u8Val);
1913	return;
1914	}
1915
1916	/* Region doesn't exist */
1917	if (iRegionSize == 0)
1918	return;
1919
1920	uint32_t uAddr = ich9pciGetRegionReg(iRegion) + iOffset;
1921	/* Region size must be power of two */
1922	Assert((iRegionSize & (iRegionSize - 1)) == 0);
1923	uint8_t uMask = ((iRegionSize - 1) >> (iOffset*8) ) & 0xff;
1924
1925	if (iOffset == 0)
1926	{
1927	uMask \|= (pRegion->type & PCI_ADDRESS_SPACE_IO) ?
1928	(1 << 2) - 1 /* 2 lowest bits for IO region */ :
1929	(1 << 4) - 1 /* 4 lowest bits for memory region, also ROM enable bit for ROM region */;
1930
1931	}
1932
1933	uint8_t u8Old = PCIDevGetByte(aDev, uAddr) & uMask;
1934	u8Val = (u8Old & uMask) \| (u8Val & ~uMask);
1935
1936	Log3(("ich9pciWriteBarByte: was %x writing %x\n", u8Old, u8Val));
1937
1938	PCIDevSetByte(aDev, uAddr, u8Val);
1939	}
1940
1941	/**
1942	* See paragraph 7.5 of PCI Express specification (p. 349) for definition of
1943	* registers and their writability policy.
1944	*/
1945	static DECLCALLBACK(void) ich9pciConfigWriteDev(PCIDevice *aDev, uint32_t u32Address,
1946	uint32_t val, unsigned len)
1947	{
1948	Assert(len <= 4);
1949
1950	if ((u32Address + len) > 256 && (u32Address + len) < 4096)
1951	{
1952	LogRel(("Write to extended register %d fallen back to generic code\n",
1953	u32Address));
1954	return;
1955	}
1956
1957	AssertMsgReturnVoid(u32Address + len <= 256, ("Write after end of PCI config space\n"));
1958
1959	if ( pciDevIsMsiCapable(aDev)
1960	&& (u32Address >= aDev->Int.s.u8MsiCapOffset)
1961	&& (u32Address < (unsigned)(aDev->Int.s.u8MsiCapOffset + aDev->Int.s.u8MsiCapSize))
1962	)
1963	{
1964	MsiPciConfigWrite(aDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pDevIns),
1965	aDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pPciHlp),
1966	aDev, u32Address, val, len);
1967	return;
1968	}
1969
1970	if ( pciDevIsMsixCapable(aDev)
1971	&& (u32Address >= aDev->Int.s.u8MsixCapOffset)
1972	&& (u32Address < (unsigned)(aDev->Int.s.u8MsixCapOffset + aDev->Int.s.u8MsixCapSize))
1973	)
1974	{
1975	MsixPciConfigWrite(aDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pDevIns),
1976	aDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pPciHlp),
1977	aDev, u32Address, val, len);
1978	return;
1979	}
1980
1981	uint32_t addr = u32Address;
1982	bool fUpdateMappings = false;
1983	bool fP2PBridge = false;
1984	/bool fPassthrough = pciDevIsPassthrough(aDev);/
1985	uint8_t u8HeaderType = ich9pciGetByte(aDev, VBOX_PCI_HEADER_TYPE);
1986
1987	for (uint32_t i = 0; i < len; i++)
1988	{
1989	bool fWritable = false;
1990	bool fRom = false;
1991	switch (u8HeaderType)
1992	{
1993	case 0x00: /* normal device */
1994	case 0x80: /* multi-function device */
1995	switch (addr)
1996	{
1997	/* Read-only registers */
1998	case VBOX_PCI_VENDOR_ID: case VBOX_PCI_VENDOR_ID+1:
1999	case VBOX_PCI_DEVICE_ID: case VBOX_PCI_DEVICE_ID+1:
2000	case VBOX_PCI_REVISION_ID:
2001	case VBOX_PCI_CLASS_PROG:
2002	case VBOX_PCI_CLASS_SUB:
2003	case VBOX_PCI_CLASS_BASE:
2004	case VBOX_PCI_HEADER_TYPE:
2005	case VBOX_PCI_SUBSYSTEM_VENDOR_ID: case VBOX_PCI_SUBSYSTEM_VENDOR_ID+1:
2006	case VBOX_PCI_SUBSYSTEM_ID: case VBOX_PCI_SUBSYSTEM_ID+1:
2007	case VBOX_PCI_ROM_ADDRESS: case VBOX_PCI_ROM_ADDRESS+1: case VBOX_PCI_ROM_ADDRESS+2: case VBOX_PCI_ROM_ADDRESS+3:
2008	case VBOX_PCI_CAPABILITY_LIST:
2009	case VBOX_PCI_INTERRUPT_PIN:
2010	fWritable = false;
2011	break;
2012	/* Others can be written */
2013	default:
2014	fWritable = true;
2015	break;
2016	}
2017	break;
2018	case 0x01: /* PCI-PCI bridge */
2019	fP2PBridge = true;
2020	switch (addr)
2021	{
2022	/* Read-only registers */
2023	case VBOX_PCI_VENDOR_ID: case VBOX_PCI_VENDOR_ID+1:
2024	case VBOX_PCI_DEVICE_ID: case VBOX_PCI_DEVICE_ID+1:
2025	case VBOX_PCI_REVISION_ID:
2026	case VBOX_PCI_CLASS_PROG:
2027	case VBOX_PCI_CLASS_SUB:
2028	case VBOX_PCI_CLASS_BASE:
2029	case VBOX_PCI_HEADER_TYPE:
2030	case VBOX_PCI_ROM_ADDRESS_BR: case VBOX_PCI_ROM_ADDRESS_BR+1: case VBOX_PCI_ROM_ADDRESS_BR+2: case VBOX_PCI_ROM_ADDRESS_BR+3:
2031	case VBOX_PCI_INTERRUPT_PIN:
2032	fWritable = false;
2033	break;
2034	default:
2035	fWritable = true;
2036	break;
2037	}
2038	break;
2039	default:
2040	AssertMsgFailed(("Unknown header type %x\n", PCIDevGetHeaderType(aDev)));
2041	fWritable = false;
2042	break;
2043	}
2044
2045	uint8_t u8Val = (uint8_t)val;
2046	switch (addr)
2047	{
2048	case VBOX_PCI_COMMAND: /* Command register, bits 0-7. */
2049	fUpdateMappings = true;
2050	goto default_case;
2051	case VBOX_PCI_COMMAND+1: /* Command register, bits 8-15. */
2052	/* don't change reserved bits (11-15) */
2053	u8Val &= UINT32_C(~0xf8);
2054	fUpdateMappings = true;
2055	goto default_case;
2056	case VBOX_PCI_STATUS: /* Status register, bits 0-7. */
2057	/* don't change read-only bits => actually all lower bits are read-only */
2058	u8Val &= UINT32_C(~0xff);
2059	/* status register, low part: clear bits by writing a '1' to the corresponding bit */
2060	aDev->config[addr] &= ~u8Val;
2061	break;
2062	case VBOX_PCI_STATUS+1: /* Status register, bits 8-15. */
2063	/* don't change read-only bits */
2064	u8Val &= UINT32_C(~0x06);
2065	/* status register, high part: clear bits by writing a '1' to the corresponding bit */
2066	aDev->config[addr] &= ~u8Val;
2067	break;
2068	case VBOX_PCI_ROM_ADDRESS: case VBOX_PCI_ROM_ADDRESS +1: case VBOX_PCI_ROM_ADDRESS +2: case VBOX_PCI_ROM_ADDRESS +3:
2069	fRom = true;
2070	case VBOX_PCI_BASE_ADDRESS_0: case VBOX_PCI_BASE_ADDRESS_0+1: case VBOX_PCI_BASE_ADDRESS_0+2: case VBOX_PCI_BASE_ADDRESS_0+3:
2071	case VBOX_PCI_BASE_ADDRESS_1: case VBOX_PCI_BASE_ADDRESS_1+1: case VBOX_PCI_BASE_ADDRESS_1+2: case VBOX_PCI_BASE_ADDRESS_1+3:
2072	case VBOX_PCI_BASE_ADDRESS_2: case VBOX_PCI_BASE_ADDRESS_2+1: case VBOX_PCI_BASE_ADDRESS_2+2: case VBOX_PCI_BASE_ADDRESS_2+3:
2073	case VBOX_PCI_BASE_ADDRESS_3: case VBOX_PCI_BASE_ADDRESS_3+1: case VBOX_PCI_BASE_ADDRESS_3+2: case VBOX_PCI_BASE_ADDRESS_3+3:
2074	case VBOX_PCI_BASE_ADDRESS_4: case VBOX_PCI_BASE_ADDRESS_4+1: case VBOX_PCI_BASE_ADDRESS_4+2: case VBOX_PCI_BASE_ADDRESS_4+3:
2075	case VBOX_PCI_BASE_ADDRESS_5: case VBOX_PCI_BASE_ADDRESS_5+1: case VBOX_PCI_BASE_ADDRESS_5+2: case VBOX_PCI_BASE_ADDRESS_5+3:
2076	{
2077	/* We check that, as same PCI register numbers as BARs may mean different registers for bridges */
2078	if (fP2PBridge)
2079	goto default_case;
2080	else
2081	{
2082	int iRegion = fRom ? VBOX_PCI_ROM_SLOT : (addr - VBOX_PCI_BASE_ADDRESS_0) >> 2;
2083	int iOffset = addr & 0x3;
2084	ich9pciWriteBarByte(aDev, iRegion, iOffset, u8Val);
2085	fUpdateMappings = true;
2086	}
2087	break;
2088	}
2089	default:
2090	default_case:
2091	if (fWritable)
2092	PCIDevSetByte(aDev, addr, u8Val);
2093	}
2094	addr++;
2095	val >>= 8;
2096	}
2097
2098	if (fUpdateMappings)
2099	/* if the command/base address register is modified, we must modify the mappings */
2100	ich9pciUpdateMappings(aDev);
2101	}
2102
2103	static bool assignPosition(PICH9PCIBUS pBus, PPCIDEVICE pPciDev, const char pszName, int iDevFn, PciAddress aPosition)
2104	{
2105	NOREF(pszName);
2106	aPosition->iBus = 0;
2107	aPosition->iDeviceFunc = iDevFn;
2108	aPosition->iRegister = 0; /* N/A */
2109
2110	/* Explicit slot request */
2111	if (iDevFn >= 0 && iDevFn < (int)RT_ELEMENTS(pBus->apDevices))
2112	return true;
2113
2114	int iStartPos = 0;
2115
2116	/* Otherwise when assigning a slot, we need to make sure all its functions are available */
2117	for (int iPos = iStartPos; iPos < (int)RT_ELEMENTS(pBus->apDevices); iPos += 8)
2118	{
2119	if ( !pBus->apDevices[iPos]
2120	&& !pBus->apDevices[iPos + 1]
2121	&& !pBus->apDevices[iPos + 2]
2122	&& !pBus->apDevices[iPos + 3]
2123	&& !pBus->apDevices[iPos + 4]
2124	&& !pBus->apDevices[iPos + 5]
2125	&& !pBus->apDevices[iPos + 6]
2126	&& !pBus->apDevices[iPos + 7])
2127	{
2128	pciDevClearRequestedDevfunc(pPciDev);
2129	aPosition->iDeviceFunc = iPos;
2130	return true;
2131	}
2132	}
2133
2134	return false;
2135	}
2136
2137	#ifdef SOME_UNUSED_FUNCTION
2138	static bool hasHardAssignedDevsInSlot(PICH9PCIBUS pBus, int iSlot)
2139	{
2140	PCIDevice** aSlot = &pBus->apDevices[iSlot << 3];
2141
2142	return (aSlot[0] && pciDevIsRequestedDevfunc(aSlot[0]))
2143	\|\| (aSlot[1] && pciDevIsRequestedDevfunc(aSlot[1]))
2144	\|\| (aSlot[2] && pciDevIsRequestedDevfunc(aSlot[2]))
2145	\|\| (aSlot[3] && pciDevIsRequestedDevfunc(aSlot[3]))
2146	\|\| (aSlot[4] && pciDevIsRequestedDevfunc(aSlot[4]))
2147	\|\| (aSlot[5] && pciDevIsRequestedDevfunc(aSlot[5]))
2148	\|\| (aSlot[6] && pciDevIsRequestedDevfunc(aSlot[6]))
2149	\|\| (aSlot[7] && pciDevIsRequestedDevfunc(aSlot[7]))
2150	;
2151	}
2152	#endif
2153
2154	static int ich9pciRegisterInternal(PICH9PCIBUS pBus, int iDev, PPCIDEVICE pPciDev, const char *pszName)
2155	{
2156	PciAddress aPosition = {0, 0, 0};
2157
2158	/*
2159	* Find device position
2160	*/
2161	if (!assignPosition(pBus, pPciDev, pszName, iDev, &aPosition))
2162	{
2163	AssertMsgFailed(("Couldn't asssign position!\n"));
2164	return VERR_PDM_TOO_PCI_MANY_DEVICES;
2165	}
2166
2167	AssertMsgReturn(aPosition.iBus == 0,
2168	("Assigning behind the bridge not implemented yet\n"),
2169	VERR_PDM_TOO_PCI_MANY_DEVICES);
2170
2171
2172	iDev = aPosition.iDeviceFunc;
2173	/*
2174	* Check if we can really take this slot, possibly by relocating
2175	* its current habitant, if it wasn't hard assigned too.
2176	*/
2177	if (pciDevIsRequestedDevfunc(pPciDev) &&
2178	pBus->apDevices[iDev] &&
2179	pciDevIsRequestedDevfunc(pBus->apDevices[iDev]))
2180	{
2181	AssertReleaseMsgFailed(("Configuration error:'%s' and '%s' are both configured as device %d\n",
2182	pszName, pBus->apDevices[iDev]->name, iDev));
2183	return VERR_INTERNAL_ERROR;
2184	}
2185
2186	if (pBus->apDevices[iDev])
2187	{
2188	/* if we got here, we shall (and usually can) relocate the device */
2189	bool assigned = assignPosition(pBus, pBus->apDevices[iDev], pBus->apDevices[iDev]->name, -1, &aPosition);
2190	AssertMsgReturn(aPosition.iBus == 0,
2191	("Assigning behind the bridge not implemented yet\n"),
2192	VERR_PDM_TOO_PCI_MANY_DEVICES);
2193	int iRelDev = aPosition.iDeviceFunc;
2194	if (!assigned \|\| iRelDev == iDev)
2195	{
2196	AssertMsgFailed(("Couldn't find free spot!\n"));
2197	return VERR_PDM_TOO_PCI_MANY_DEVICES;
2198	}
2199	/* Copy device function by function to its new position */
2200	for (int i = 0; i < 8; i++)
2201	{
2202	if (!pBus->apDevices[iDev + i])
2203	continue;
2204	Log(("PCI: relocating '%s' from slot %#x to %#x\n", pBus->apDevices[iDev + i]->name, iDev + i, iRelDev + i));
2205	pBus->apDevices[iRelDev + i] = pBus->apDevices[iDev + i];
2206	pBus->apDevices[iRelDev + i]->devfn = iRelDev + i;
2207	pBus->apDevices[iDev + i] = NULL;
2208	}
2209	}
2210
2211	/*
2212	* Fill in device information.
2213	*/
2214	pPciDev->devfn = iDev;
2215	pPciDev->name = pszName;
2216	pPciDev->Int.s.pBusR3 = pBus;
2217	pPciDev->Int.s.pBusR0 = MMHyperR3ToR0(PDMDevHlpGetVM(pBus->CTX_SUFF(pDevIns)), pBus);
2218	pPciDev->Int.s.pBusRC = MMHyperR3ToRC(PDMDevHlpGetVM(pBus->CTX_SUFF(pDevIns)), pBus);
2219	pPciDev->Int.s.pfnConfigRead = ich9pciConfigReadDev;
2220	pPciDev->Int.s.pfnConfigWrite = ich9pciConfigWriteDev;
2221	pBus->apDevices[iDev] = pPciDev;
2222	if (pciDevIsPci2PciBridge(pPciDev))
2223	{
2224	AssertMsg(pBus->cBridges < RT_ELEMENTS(pBus->apDevices), ("Number of bridges exceeds the number of possible devices on the bus\n"));
2225	AssertMsg(pPciDev->Int.s.pfnBridgeConfigRead && pPciDev->Int.s.pfnBridgeConfigWrite,
2226	("device is a bridge but does not implement read/write functions\n"));
2227	Log2(("Setting bridge %d on bus %p\n", pBus->cBridges, pBus));
2228	pBus->papBridgesR3[pBus->cBridges] = pPciDev;
2229	pBus->cBridges++;
2230	}
2231
2232	Log(("PCI: Registered device %d function %d on bus %d (%#x) '%s'.\n",
2233	iDev >> 3, iDev & 7, pBus->iBus, 0x80000000 \| (iDev << 8), pszName));
2234
2235	return VINF_SUCCESS;
2236	}
2237
2238	static void printIndent(PCDBGFINFOHLP pHlp, int iIndent)
2239	{
2240	for (int i = 0; i < iIndent; i++)
2241	{
2242	pHlp->pfnPrintf(pHlp, " ");
2243	}
2244	}
2245
2246	static void ich9pciBusInfo(PICH9PCIBUS pBus, PCDBGFINFOHLP pHlp, int iIndent, bool fRegisters)
2247	{
2248	for (uint32_t iDev = 0; iDev < RT_ELEMENTS(pBus->apDevices); iDev++)
2249	{
2250	PPCIDEVICE pPciDev = pBus->apDevices[iDev];
2251	if (pPciDev != NULL)
2252	{
2253	printIndent(pHlp, iIndent);
2254
2255	/*
2256	* For passthrough devices MSI/MSI-X mostly reflects the way interrupts delivered to the guest,
2257	* as host driver handles real devices interrupts.
2258	*/
2259	pHlp->pfnPrintf(pHlp, "%02x:%02x:%02x %s%s: %04x-%04x%s%s",
2260	pBus->iBus, (iDev >> 3) & 0xff, iDev & 0x7,
2261	pPciDev->name,
2262	pciDevIsPassthrough(pPciDev) ? " (PASSTHROUGH)" : "",
2263	ich9pciGetWord(pPciDev, VBOX_PCI_VENDOR_ID), ich9pciGetWord(pPciDev, VBOX_PCI_DEVICE_ID),
2264	pciDevIsMsiCapable(pPciDev) ? " MSI" : "",
2265	pciDevIsMsixCapable(pPciDev) ? " MSI-X" : ""
2266	);
2267	if (ich9pciGetByte(pPciDev, VBOX_PCI_INTERRUPT_PIN) != 0)
2268	pHlp->pfnPrintf(pHlp, " IRQ%d", ich9pciGetByte(pPciDev, VBOX_PCI_INTERRUPT_LINE));
2269
2270	pHlp->pfnPrintf(pHlp, "\n");
2271
2272	uint16_t iCmd = ich9pciGetWord(pPciDev, VBOX_PCI_COMMAND);
2273	if ((iCmd & (VBOX_PCI_COMMAND_IO \| VBOX_PCI_COMMAND_MEMORY)) != 0)
2274	{
2275	for (int iRegion = 0; iRegion < PCI_NUM_REGIONS; iRegion++)
2276	{
2277	PCIIORegion* pRegion = &pPciDev->Int.s.aIORegions[iRegion];
2278	uint64_t iRegionSize = pRegion->size;
2279
2280	if (iRegionSize == 0)
2281	continue;
2282
2283	uint32_t u32Addr = ich9pciGetDWord(pPciDev, ich9pciGetRegionReg(iRegion));
2284	const char * pszDesc;
2285	char szDescBuf[128];
2286
2287	bool f64Bit = !!(pRegion->type & PCI_ADDRESS_SPACE_BAR64);
2288	if (pRegion->type & PCI_ADDRESS_SPACE_IO)
2289	{
2290	pszDesc = "IO";
2291	u32Addr &= ~0x3;
2292	}
2293	else
2294	{
2295	RTStrPrintf(szDescBuf, sizeof(szDescBuf), "MMIO%s%s",
2296	f64Bit ? "64" : "32",
2297	(pRegion->type & PCI_ADDRESS_SPACE_MEM_PREFETCH) ? " PREFETCH" : "");
2298	pszDesc = szDescBuf;
2299	u32Addr &= ~0xf;
2300	}
2301
2302	printIndent(pHlp, iIndent + 2);
2303	pHlp->pfnPrintf(pHlp, "%s region #%d: %x..%x\n",
2304	pszDesc, iRegion, u32Addr, u32Addr+iRegionSize);
2305	if (f64Bit)
2306	iRegion++;
2307	}
2308	}
2309
2310	printIndent(pHlp, iIndent + 2);
2311	uint16_t iStatus = ich9pciGetWord(pPciDev, VBOX_PCI_STATUS);
2312	pHlp->pfnPrintf(pHlp, "Command: %.Rhxs, Status: %.Rhxs\n",
2313	sizeof(uint16_t), &iCmd, sizeof(uint16_t), &iStatus);
2314	printIndent(pHlp, iIndent + 2);
2315	pHlp->pfnPrintf(pHlp, "Bus master: %s\n",
2316	iCmd & VBOX_PCI_COMMAND_MASTER ? "Yes" : "No");
2317
2318	if (fRegisters)
2319	{
2320	printIndent(pHlp, iIndent + 2);
2321	pHlp->pfnPrintf(pHlp, "PCI registers:\n");
2322	for (int iReg = 0; iReg < 0x100; )
2323	{
2324	int iPerLine = 0x10;
2325	Assert (0x100 % iPerLine == 0);
2326	printIndent(pHlp, iIndent + 3);
2327
2328	while (iPerLine-- > 0)
2329	{
2330	pHlp->pfnPrintf(pHlp, "%02x ", ich9pciGetByte(pPciDev, iReg++));
2331	}
2332	pHlp->pfnPrintf(pHlp, "\n");
2333	}
2334	}
2335	}
2336	}
2337
2338	if (pBus->cBridges > 0)
2339	{
2340	printIndent(pHlp, iIndent);
2341	pHlp->pfnPrintf(pHlp, "Registered %d bridges, subordinate buses info follows\n", pBus->cBridges);
2342	for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
2343	{
2344	PICH9PCIBUS pBusSub = PDMINS_2_DATA(pBus->papBridgesR3[iBridge]->pDevIns, PICH9PCIBUS);
2345	ich9pciBusInfo(pBusSub, pHlp, iIndent + 1, fRegisters);
2346	}
2347	}
2348	}
2349
2350	/**
2351	* Info handler, device version.
2352	*
2353	* @param pDevIns Device instance which registered the info.
2354	* @param pHlp Callback functions for doing output.
2355	* @param pszArgs Argument string. Optional and specific to the handler.
2356	*/
2357	static DECLCALLBACK(void) ich9pciInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
2358	{
2359	PICH9PCIBUS pBus = DEVINS_2_PCIBUS(pDevIns);
2360
2361	if (pszArgs == NULL \|\| !strcmp(pszArgs, "basic"))
2362	{
2363	ich9pciBusInfo(pBus, pHlp, 0, false);
2364	}
2365	else if (!strcmp(pszArgs, "verbose"))
2366	{
2367	ich9pciBusInfo(pBus, pHlp, 0, true);
2368	}
2369	else
2370	{
2371	pHlp->pfnPrintf(pHlp, "Invalid argument. Recognized arguments are 'basic', 'verbose'.\n");
2372	}
2373	}
2374
2375
2376	static DECLCALLBACK(int) ich9pciConstruct(PPDMDEVINS pDevIns,
2377	int iInstance,
2378	PCFGMNODE pCfg)
2379	{
2380	Assert(iInstance == 0);
2381	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
2382
2383	/*
2384	* Validate and read configuration.
2385	*/
2386	if (!CFGMR3AreValuesValid(pCfg,
2387	"IOAPIC\0"
2388	"GCEnabled\0"
2389	"R0Enabled\0"
2390	"McfgBase\0"
2391	"McfgLength\0"
2392	))
2393	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
2394
2395	/* query whether we got an IOAPIC */
2396	bool fUseIoApic;
2397	int rc = CFGMR3QueryBoolDef(pCfg, "IOAPIC", &fUseIoApic, false);
2398	if (RT_FAILURE(rc))
2399	return PDMDEV_SET_ERROR(pDevIns, rc,
2400	N_("Configuration error: Failed to query boolean value \"IOAPIC\""));
2401
2402	/* check if RC code is enabled. */
2403	bool fGCEnabled;
2404	rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
2405	if (RT_FAILURE(rc))
2406	return PDMDEV_SET_ERROR(pDevIns, rc,
2407	N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
2408	/* check if R0 code is enabled. */
2409	bool fR0Enabled;
2410	rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
2411	if (RT_FAILURE(rc))
2412	return PDMDEV_SET_ERROR(pDevIns, rc,
2413	N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
2414
2415	Log(("PCI: fUseIoApic=%RTbool fGCEnabled=%RTbool fR0Enabled=%RTbool\n", fUseIoApic, fGCEnabled, fR0Enabled));
2416
2417	/*
2418	* Init data.
2419	*/
2420	PICH9PCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
2421	PICH9PCIBUS pBus = &pGlobals->aPciBus;
2422	/* Zero out everything */
2423	memset(pGlobals, 0, sizeof(*pGlobals));
2424	/* And fill values */
2425	if (!fUseIoApic)
2426	return PDMDEV_SET_ERROR(pDevIns, rc,
2427	N_("Must use IO-APIC with ICH9 chipset"));
2428	rc = CFGMR3QueryU64Def(pCfg, "McfgBase", &pGlobals->u64PciConfigMMioAddress, 0);
2429	if (RT_FAILURE(rc))
2430	return PDMDEV_SET_ERROR(pDevIns, rc,
2431	N_("Configuration error: Failed to read \"McfgBase\""));
2432	rc = CFGMR3QueryU64Def(pCfg, "McfgLength", &pGlobals->u64PciConfigMMioLength, 0);
2433	if (RT_FAILURE(rc))
2434	return PDMDEV_SET_ERROR(pDevIns, rc,
2435	N_("Configuration error: Failed to read \"McfgLength\""));
2436
2437	pGlobals->pDevInsR3 = pDevIns;
2438	pGlobals->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2439	pGlobals->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2440
2441	pGlobals->aPciBus.pDevInsR3 = pDevIns;
2442	pGlobals->aPciBus.pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2443	pGlobals->aPciBus.pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2444	pGlobals->aPciBus.papBridgesR3 = (PPCIDEVICE )PDMDevHlpMMHeapAllocZ(pDevIns, sizeof(PPCIDEVICE) RT_ELEMENTS(pGlobals->aPciBus.apDevices));
2445
2446	/*
2447	* Register bus
2448	*/
2449	PDMPCIBUSREG PciBusReg;
2450	PciBusReg.u32Version = PDM_PCIBUSREG_VERSION;
2451	PciBusReg.pfnRegisterR3 = ich9pciRegister;
2452	PciBusReg.pfnRegisterMsiR3 = ich9pciRegisterMsi;
2453	PciBusReg.pfnIORegionRegisterR3 = ich9pciIORegionRegister;
2454	PciBusReg.pfnSetConfigCallbacksR3 = ich9pciSetConfigCallbacks;
2455	PciBusReg.pfnSetIrqR3 = ich9pciSetIrq;
2456	PciBusReg.pfnSaveExecR3 = ich9pciGenericSaveExec;
2457	PciBusReg.pfnLoadExecR3 = ich9pciGenericLoadExec;
2458	PciBusReg.pfnFakePCIBIOSR3 = ich9pciFakePCIBIOS;
2459	PciBusReg.pszSetIrqRC = fGCEnabled ? "ich9pciSetIrq" : NULL;
2460	PciBusReg.pszSetIrqR0 = fR0Enabled ? "ich9pciSetIrq" : NULL;
2461	rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBus->pPciHlpR3);
2462	if (RT_FAILURE(rc))
2463	return PDMDEV_SET_ERROR(pDevIns, rc,
2464	N_("Failed to register ourselves as a PCI Bus"));
2465	if (pBus->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
2466	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
2467	N_("PCI helper version mismatch; got %#x expected %#x"),
2468	pBus->pPciHlpR3->u32Version, PDM_PCIHLPR3_VERSION);
2469
2470	pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
2471	pBus->pPciHlpR0 = pBus->pPciHlpR3->pfnGetR0Helpers(pDevIns);
2472
2473	/*
2474	* Fill in PCI configs and add them to the bus.
2475	*/
2476	/** @todo: Disabled for now because this causes error messages with Linux guests.
2477	* The guest loads the x38_edac device which tries to map a memory region
2478	* using an address given at place 0x48 - 0x4f in the PCi config space.
2479	* This fails. because we don't register such a region.
2480	*/
2481	#if 0
2482	/* Host bridge device */
2483	PCIDevSetVendorId( &pBus->aPciDev, 0x8086); /* Intel */
2484	PCIDevSetDeviceId( &pBus->aPciDev, 0x29e0); /* Desktop */
2485	PCIDevSetRevisionId(&pBus->aPciDev, 0x01); /* rev. 01 */
2486	PCIDevSetClassBase( &pBus->aPciDev, 0x06); /* bridge */
2487	PCIDevSetClassSub( &pBus->aPciDev, 0x00); /* Host/PCI bridge */
2488	PCIDevSetClassProg( &pBus->aPciDev, 0x00); /* Host/PCI bridge */
2489	PCIDevSetHeaderType(&pBus->aPciDev, 0x00); /* bridge */
2490	PCIDevSetWord(&pBus->aPciDev, VBOX_PCI_SEC_STATUS, 0x0280); /* secondary status */
2491
2492	pBus->aPciDev.pDevIns = pDevIns;
2493	/* We register Host<->PCI controller on the bus */
2494	ich9pciRegisterInternal(pBus, 0, &pBus->aPciDev, "dram");
2495	#endif
2496
2497	/*
2498	* Register I/O ports and save state.
2499	*/
2500	rc = PDMDevHlpIOPortRegister(pDevIns, 0x0cf8, 1, NULL, ich9pciIOPortAddressWrite, ich9pciIOPortAddressRead, NULL, NULL, "ICH9 (PCI)");
2501	if (RT_FAILURE(rc))
2502	return rc;
2503	rc = PDMDevHlpIOPortRegister(pDevIns, 0x0cfc, 4, NULL, ich9pciIOPortDataWrite, ich9pciIOPortDataRead, NULL, NULL, "ICH9 (PCI)");
2504	if (RT_FAILURE(rc))
2505	return rc;
2506	if (fGCEnabled)
2507	{
2508	rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x0cf8, 1, NIL_RTGCPTR, "ich9pciIOPortAddressWrite", "ich9pciIOPortAddressRead", NULL, NULL, "ICH9 (PCI)");
2509	if (RT_FAILURE(rc))
2510	return rc;
2511	rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x0cfc, 4, NIL_RTGCPTR, "ich9pciIOPortDataWrite", "ich9pciIOPortDataRead", NULL, NULL, "ICH9 (PCI)");
2512	if (RT_FAILURE(rc))
2513	return rc;
2514	}
2515	if (fR0Enabled)
2516	{
2517	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x0cf8, 1, NIL_RTR0PTR, "ich9pciIOPortAddressWrite", "ich9pciIOPortAddressRead", NULL, NULL, "ICH9 (PCI)");
2518	if (RT_FAILURE(rc))
2519	return rc;
2520	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x0cfc, 4, NIL_RTR0PTR, "ich9pciIOPortDataWrite", "ich9pciIOPortDataRead", NULL, NULL, "ICH9 (PCI)");
2521	if (RT_FAILURE(rc))
2522	return rc;
2523	}
2524
2525	if (pGlobals->u64PciConfigMMioAddress != 0)
2526	{
2527	rc = PDMDevHlpMMIORegister(pDevIns, pGlobals->u64PciConfigMMioAddress, pGlobals->u64PciConfigMMioLength, NULL /pvUser/,
2528	IOMMMIO_FLAGS_READ_PASSTHRU \| IOMMMIO_FLAGS_WRITE_PASSTHRU,
2529	ich9pciMcfgMMIOWrite, ich9pciMcfgMMIORead, "MCFG ranges");
2530	AssertMsgRCReturn(rc, ("rc=%Rrc %#llx/%#llx\n", rc, pGlobals->u64PciConfigMMioAddress, pGlobals->u64PciConfigMMioLength), rc);
2531
2532	if (fGCEnabled)
2533	{
2534	rc = PDMDevHlpMMIORegisterRC(pDevIns, pGlobals->u64PciConfigMMioAddress, pGlobals->u64PciConfigMMioLength,
2535	NIL_RTRCPTR /pvUser/, "ich9pciMcfgMMIOWrite", "ich9pciMcfgMMIORead");
2536	AssertRCReturn(rc, rc);
2537	}
2538
2539
2540	if (fR0Enabled)
2541	{
2542	rc = PDMDevHlpMMIORegisterR0(pDevIns, pGlobals->u64PciConfigMMioAddress, pGlobals->u64PciConfigMMioLength,
2543	NIL_RTR0PTR /pvUser/, "ich9pciMcfgMMIOWrite", "ich9pciMcfgMMIORead");
2544	AssertRCReturn(rc, rc);
2545	}
2546	}
2547
2548	rc = PDMDevHlpSSMRegisterEx(pDevIns, VBOX_ICH9PCI_SAVED_STATE_VERSION_CURRENT,
2549	sizeof(pBus) + 16128, "pgm",
2550	NULL, NULL, NULL,
2551	NULL, ich9pciR3SaveExec, NULL,
2552	NULL, ich9pciR3LoadExec, NULL);
2553	if (RT_FAILURE(rc))
2554	return rc;
2555
2556
2557	/** @todo: other chipset devices shall be registered too */
2558
2559	PDMDevHlpDBGFInfoRegister(pDevIns, "pci", "Display PCI bus status. Recognizes 'basic' or 'verbose' "
2560	"as arguments, defaults to 'basic'.", ich9pciInfo);
2561
2562	return VINF_SUCCESS;
2563	}
2564
2565	static void ich9pciResetDevice(PPCIDEVICE pDev)
2566	{
2567	/* Clear regions */
2568	for (int iRegion = 0; iRegion < PCI_NUM_REGIONS; iRegion++)
2569	{
2570	PCIIORegion* pRegion = &pDev->Int.s.aIORegions[iRegion];
2571	if (pRegion->size == 0)
2572	continue;
2573
2574	ich9pciUnmapRegion(pDev, iRegion);
2575	}
2576
2577	if (pciDevIsPassthrough(pDev))
2578	{
2579	// no reset handler - we can do what we need in PDM reset handler
2580	// @todo: is it correct?
2581	}
2582	else
2583	{
2584	PCIDevSetCommand(pDev,
2585	PCIDevGetCommand(pDev)
2586	&
2587	~(VBOX_PCI_COMMAND_IO \|
2588	VBOX_PCI_COMMAND_MEMORY \|
2589	VBOX_PCI_COMMAND_MASTER));
2590
2591	/* Bridge device reset handlers processed later */
2592	if (!pciDevIsPci2PciBridge(pDev))
2593	{
2594	PCIDevSetByte(pDev, VBOX_PCI_CACHE_LINE_SIZE, 0x0);
2595	PCIDevSetInterruptLine(pDev, 0x0);
2596	}
2597	}
2598	}
2599
2600
2601	/**
2602	* @copydoc FNPDMDEVRESET
2603	*/
2604	static DECLCALLBACK(void) ich9pciReset(PPDMDEVINS pDevIns)
2605	{
2606	PICH9PCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
2607	PICH9PCIBUS pBus = &pGlobals->aPciBus;
2608
2609	/* PCI-specific reset for each device. */
2610	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
2611	{
2612	if (pBus->apDevices[i])
2613	ich9pciResetDevice(pBus->apDevices[i]);
2614	}
2615
2616	for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
2617	{
2618	if (pBus->papBridgesR3[iBridge])
2619	ich9pcibridgeReset(pBus->papBridgesR3[iBridge]->pDevIns);
2620	}
2621
2622	ich9pciFakePCIBIOS(pDevIns);
2623	}
2624
2625	static void ich9pciRelocateDevice(PPCIDEVICE pDev, RTGCINTPTR offDelta)
2626	{
2627	if (pDev)
2628	{
2629	pDev->Int.s.pBusRC += offDelta;
2630	if (pDev->Int.s.pMsixPageRC)
2631	pDev->Int.s.pMsixPageRC += offDelta;
2632	}
2633	}
2634
2635	/**
2636	* @copydoc FNPDMDEVRELOCATE
2637	*/
2638	static DECLCALLBACK(void) ich9pciRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
2639	{
2640	PICH9PCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
2641	PICH9PCIBUS pBus = &pGlobals->aPciBus;
2642	pGlobals->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2643
2644	pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
2645	pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2646
2647	/* Relocate RC pointers for the attached pci devices. */
2648	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
2649	ich9pciRelocateDevice(pBus->apDevices[i], offDelta);
2650
2651	}
2652
2653	/**
2654	* @interface_method_impl{PDMDEVREG,pfnConstruct}
2655	*/
2656	static DECLCALLBACK(int) ich9pcibridgeConstruct(PPDMDEVINS pDevIns,
2657	int iInstance,
2658	PCFGMNODE pCfg)
2659	{
2660	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
2661
2662	/*
2663	* Validate and read configuration.
2664	*/
2665	if (!CFGMR3AreValuesValid(pCfg, "GCEnabled\0" "R0Enabled\0"))
2666	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
2667
2668	/* check if RC code is enabled. */
2669	bool fGCEnabled;
2670	int rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
2671	if (RT_FAILURE(rc))
2672	return PDMDEV_SET_ERROR(pDevIns, rc,
2673	N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
2674
2675	/* check if R0 code is enabled. */
2676	bool fR0Enabled;
2677	rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
2678	if (RT_FAILURE(rc))
2679	return PDMDEV_SET_ERROR(pDevIns, rc,
2680	N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
2681	Log(("PCI: fGCEnabled=%RTbool fR0Enabled=%RTbool\n", fGCEnabled, fR0Enabled));
2682
2683	/*
2684	* Init data and register the PCI bus.
2685	*/
2686	PICH9PCIBUS pBus = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
2687	pBus->pDevInsR3 = pDevIns;
2688	pBus->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2689	pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2690	pBus->papBridgesR3 = (PPCIDEVICE )PDMDevHlpMMHeapAllocZ(pDevIns, sizeof(PPCIDEVICE) RT_ELEMENTS(pBus->apDevices));
2691
2692	PDMPCIBUSREG PciBusReg;
2693	PciBusReg.u32Version = PDM_PCIBUSREG_VERSION;
2694	PciBusReg.pfnRegisterR3 = ich9pcibridgeRegister;
2695	PciBusReg.pfnRegisterMsiR3 = ich9pciRegisterMsi;
2696	PciBusReg.pfnIORegionRegisterR3 = ich9pciIORegionRegister;
2697	PciBusReg.pfnSetConfigCallbacksR3 = ich9pciSetConfigCallbacks;
2698	PciBusReg.pfnSetIrqR3 = ich9pcibridgeSetIrq;
2699	PciBusReg.pfnSaveExecR3 = ich9pciGenericSaveExec;
2700	PciBusReg.pfnLoadExecR3 = ich9pciGenericLoadExec;
2701	PciBusReg.pfnFakePCIBIOSR3 = NULL; /* Only needed for the first bus. */
2702	PciBusReg.pszSetIrqRC = fGCEnabled ? "ich9pcibridgeSetIrq" : NULL;
2703	PciBusReg.pszSetIrqR0 = fR0Enabled ? "ich9pcibridgeSetIrq" : NULL;
2704	rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBus->pPciHlpR3);
2705	if (RT_FAILURE(rc))
2706	return PDMDEV_SET_ERROR(pDevIns, rc,
2707	N_("Failed to register ourselves as a PCI Bus"));
2708	if (pBus->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
2709	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
2710	N_("PCI helper version mismatch; got %#x expected %#x"),
2711	pBus->pPciHlpR3->u32Version, PDM_PCIHLPR3_VERSION);
2712
2713	pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
2714	pBus->pPciHlpR0 = pBus->pPciHlpR3->pfnGetR0Helpers(pDevIns);
2715
2716	/* Disable default device locking. */
2717	rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
2718	AssertRCReturn(rc, rc);
2719
2720	/*
2721	* Fill in PCI configs and add them to the bus.
2722	*/
2723	PCIDevSetVendorId( &pBus->aPciDev, 0x8086); /* Intel */
2724	PCIDevSetDeviceId( &pBus->aPciDev, 0x2448); /* 82801 Mobile PCI bridge. */
2725	PCIDevSetRevisionId(&pBus->aPciDev, 0xf2);
2726	PCIDevSetClassSub( &pBus->aPciDev, 0x04); /* pci2pci */
2727	PCIDevSetClassBase( &pBus->aPciDev, 0x06); /* PCI_bridge */
2728	PCIDevSetClassProg( &pBus->aPciDev, 0x01); /* Supports subtractive decoding. */
2729	PCIDevSetHeaderType(&pBus->aPciDev, 0x01); /* Single function device which adheres to the PCI-to-PCI bridge spec. */
2730	PCIDevSetCommand( &pBus->aPciDev, 0x00);
2731	PCIDevSetStatus( &pBus->aPciDev, 0x20); /* 66MHz Capable. */
2732	PCIDevSetInterruptLine(&pBus->aPciDev, 0x00); /* This device does not assert interrupts. */
2733
2734	/*
2735	* This device does not generate interrupts. Interrupt delivery from
2736	* devices attached to the bus is unaffected.
2737	*/
2738	PCIDevSetInterruptPin (&pBus->aPciDev, 0x00);
2739
2740	pBus->aPciDev.pDevIns = pDevIns;
2741
2742	/* Bridge-specific data */
2743	pciDevSetPci2PciBridge(&pBus->aPciDev);
2744	pBus->aPciDev.Int.s.pfnBridgeConfigRead = ich9pcibridgeConfigRead;
2745	pBus->aPciDev.Int.s.pfnBridgeConfigWrite = ich9pcibridgeConfigWrite;
2746
2747	/*
2748	* Register this PCI bridge. The called function will take care on which bus we will get registered.
2749	*/
2750	rc = PDMDevHlpPCIRegister (pDevIns, &pBus->aPciDev);
2751	if (RT_FAILURE(rc))
2752	return rc;
2753
2754	/*
2755	* The iBus property doesn't really represent the bus number
2756	* because the guest and the BIOS can choose different bus numbers
2757	* for them.
2758	* The bus number is mainly for the setIrq function to indicate
2759	* when the host bus is reached which will have iBus = 0.
2760	* That's why the + 1.
2761	*/
2762	pBus->iBus = iInstance + 1;
2763
2764	/*
2765	* Register SSM handlers. We use the same saved state version as for the host bridge
2766	* to make changes easier.
2767	*/
2768	rc = PDMDevHlpSSMRegisterEx(pDevIns, VBOX_ICH9PCI_SAVED_STATE_VERSION_CURRENT,
2769	sizeof(pBus) + 16128,
2770	"pgm" /* before */,
2771	NULL, NULL, NULL,
2772	NULL, ich9pcibridgeR3SaveExec, NULL,
2773	NULL, ich9pcibridgeR3LoadExec, NULL);
2774	if (RT_FAILURE(rc))
2775	return rc;
2776
2777
2778	return VINF_SUCCESS;
2779	}
2780
2781	/**
2782	* @copydoc FNPDMDEVRESET
2783	*/
2784	static void ich9pcibridgeReset(PPDMDEVINS pDevIns)
2785	{
2786	PICH9PCIBUS pBus = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
2787
2788	/* Reset config space to default values. */
2789	PCIDevSetByte(&pBus->aPciDev, VBOX_PCI_PRIMARY_BUS, 0);
2790	PCIDevSetByte(&pBus->aPciDev, VBOX_PCI_SECONDARY_BUS, 0);
2791	PCIDevSetByte(&pBus->aPciDev, VBOX_PCI_SUBORDINATE_BUS, 0);
2792
2793	/* PCI-specific reset for each device. */
2794	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
2795	{
2796	if (pBus->apDevices[i])
2797	ich9pciResetDevice(pBus->apDevices[i]);
2798	}
2799	}
2800
2801
2802	/**
2803	* @copydoc FNPDMDEVRELOCATE
2804	*/
2805	static DECLCALLBACK(void) ich9pcibridgeRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
2806	{
2807	PICH9PCIBUS pBus = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
2808	pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2809
2810	/* Relocate RC pointers for the attached pci devices. */
2811	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
2812	ich9pciRelocateDevice(pBus->apDevices[i], offDelta);
2813	}
2814
2815	/**
2816	* The PCI bus device registration structure.
2817	*/
2818	const PDMDEVREG g_DevicePciIch9 =
2819	{
2820	/* u32Version */
2821	PDM_DEVREG_VERSION,
2822	/* szName */
2823	"ich9pci",
2824	/* szRCMod */
2825	"VBoxDDGC.gc",
2826	/* szR0Mod */
2827	"VBoxDDR0.r0",
2828	/* pszDescription */
2829	"ICH9 PCI bridge",
2830	/* fFlags */
2831	PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
2832	/* fClass */
2833	PDM_DEVREG_CLASS_BUS_PCI \| PDM_DEVREG_CLASS_BUS_ISA,
2834	/* cMaxInstances */
2835	1,
2836	/* cbInstance */
2837	sizeof(ICH9PCIGLOBALS),
2838	/* pfnConstruct */
2839	ich9pciConstruct,
2840	/* pfnDestruct */
2841	NULL,
2842	/* pfnRelocate */
2843	ich9pciRelocate,
2844	/* pfnIOCtl */
2845	NULL,
2846	/* pfnPowerOn */
2847	NULL,
2848	/* pfnReset */
2849	ich9pciReset,
2850	/* pfnSuspend */
2851	NULL,
2852	/* pfnResume */
2853	NULL,
2854	/* pfnAttach */
2855	NULL,
2856	/* pfnDetach */
2857	NULL,
2858	/* pfnQueryInterface */
2859	NULL,
2860	/* pfnInitComplete */
2861	NULL,
2862	/* pfnPowerOff */
2863	NULL,
2864	/* pfnSoftReset */
2865	NULL,
2866	/* u32VersionEnd */
2867	PDM_DEVREG_VERSION
2868	};
2869
2870	/**
2871	* The device registration structure
2872	* for the PCI-to-PCI bridge.
2873	*/
2874	const PDMDEVREG g_DevicePciIch9Bridge =
2875	{
2876	/* u32Version */
2877	PDM_DEVREG_VERSION,
2878	/* szName */
2879	"ich9pcibridge",
2880	/* szRCMod */
2881	"VBoxDDGC.gc",
2882	/* szR0Mod */
2883	"VBoxDDR0.r0",
2884	/* pszDescription */
2885	"ICH9 PCI to PCI bridge",
2886	/* fFlags */
2887	PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
2888	/* fClass */
2889	PDM_DEVREG_CLASS_BUS_PCI,
2890	/* cMaxInstances */
2891	~0U,
2892	/* cbInstance */
2893	sizeof(ICH9PCIBUS),
2894	/* pfnConstruct */
2895	ich9pcibridgeConstruct,
2896	/* pfnDestruct */
2897	NULL,
2898	/* pfnRelocate */
2899	ich9pcibridgeRelocate,
2900	/* pfnIOCtl */
2901	NULL,
2902	/* pfnPowerOn */
2903	NULL,
2904	/* pfnReset */
2905	NULL, /* Must be NULL, to make sure only bus driver handles reset */
2906	/* pfnSuspend */
2907	NULL,
2908	/* pfnResume */
2909	NULL,
2910	/* pfnAttach */
2911	NULL,
2912	/* pfnDetach */
2913	NULL,
2914	/* pfnQueryInterface */
2915	NULL,
2916	/* pfnInitComplete */
2917	NULL,
2918	/* pfnPowerOff */
2919	NULL,
2920	/* pfnSoftReset */
2921	NULL,
2922	/* u32VersionEnd */
2923	PDM_DEVREG_VERSION
2924	};
2925
2926	#endif /* IN_RING3 */
2927	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */

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source: vbox/trunk/src/VBox/Devices/Bus/DevPciIch9.cpp@ 41697

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