DevPciIch9.cpp@ 57526

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1	/* $Id: DevPciIch9.cpp 57393 2015-08-17 15:02:05Z vboxsync $ */
2	/** @file
3	* DevPCI - ICH9 southbridge PCI bus emulation device.
4	*
5	* @note bird: I've cleaned up DevPCI.cpp to some extend, this file has not
6	* be cleaned up and because of pending code merge.
7	*/
8
9	/*
10	* Copyright (C) 2010-2015 Oracle Corporation
11	*
12	* This file is part of VirtualBox Open Source Edition (OSE), as
13	* available from http://www.virtualbox.org. This file is free software;
14	* you can redistribute it and/or modify it under the terms of the GNU
15	* General Public License (GPL) as published by the Free Software
16	* Foundation, in version 2 as it comes in the "COPYING" file of the
17	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
18	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
19	*/
20
21
22	/*********************************************************************************************************************************
23	* Header Files *
24	*********************************************************************************************************************************/
25	#define LOG_GROUP LOG_GROUP_DEV_PCI
26	/* Hack to get PCIDEVICEINT declared at the right point - include "PCIInternal.h". */
27	#define PCI_INCLUDE_PRIVATE
28	#define PCIBus ICH9PCIBus
29	#include <VBox/pci.h>
30	#include <VBox/msi.h>
31	#include <VBox/vmm/pdmdev.h>
32	#include <iprt/asm.h>
33	#include <iprt/assert.h>
34	#include <iprt/string.h>
35	#ifdef IN_RING3
36	#include <iprt/alloc.h>
37	#endif
38
39	#include "VBoxDD.h"
40	#include "MsiCommon.h"
41
42
43	/*********************************************************************************************************************************
44	* Structures and Typedefs *
45	*********************************************************************************************************************************/
46	/**
47	* PCI Bus instance.
48	*/
49	typedef struct ICH9PCIBus
50	{
51	/** Bus number. */
52	int32_t iBus;
53	/** Number of bridges attached to the bus. */
54	uint32_t cBridges;
55
56	/** Array of PCI devices. We assume 32 slots, each with 8 functions. */
57	R3PTRTYPE(PPCIDEVICE) apDevices[256];
58	/** Array of bridges attached to the bus. */
59	R3PTRTYPE(PPCIDEVICE *) papBridgesR3;
60
61	/** R3 pointer to the device instance. */
62	PPDMDEVINSR3 pDevInsR3;
63	/** Pointer to the PCI R3 helpers. */
64	PCPDMPCIHLPR3 pPciHlpR3;
65
66	/** R0 pointer to the device instance. */
67	PPDMDEVINSR0 pDevInsR0;
68	/** Pointer to the PCI R0 helpers. */
69	PCPDMPCIHLPR0 pPciHlpR0;
70
71	/** RC pointer to the device instance. */
72	PPDMDEVINSRC pDevInsRC;
73	/** Pointer to the PCI RC helpers. */
74	PCPDMPCIHLPRC pPciHlpRC;
75
76	/** The PCI device for the PCI bridge. */
77	PCIDEVICE aPciDev;
78
79	} ICH9PCIBUS, *PICH9PCIBUS;
80
81
82	/** @def PCI_APIC_IRQ_PINS
83	* Number of pins for interrupts if the APIC is used.
84	*/
85	#define PCI_APIC_IRQ_PINS 8
86
87	/**
88	* PCI Globals - This is the host-to-pci bridge and the root bus.
89	*/
90	typedef struct
91	{
92	/** R3 pointer to the device instance. */
93	PPDMDEVINSR3 pDevInsR3;
94	/** R0 pointer to the device instance. */
95	PPDMDEVINSR0 pDevInsR0;
96	/** RC pointer to the device instance. */
97	PPDMDEVINSRC pDevInsRC;
98
99	#if HC_ARCH_BITS == 64
100	uint32_t Alignment0;
101	#endif
102
103	/** Value latched in Configuration Address Port (0CF8h) */
104	uint32_t uConfigReg;
105
106	/** I/O APIC irq levels */
107	volatile uint32_t uaPciApicIrqLevels[PCI_APIC_IRQ_PINS];
108
109	#if 1 /* Will be moved into the BIOS soon. */
110	/** The next I/O port address which the PCI BIOS will use. */
111	uint32_t uPciBiosIo;
112	/** The next MMIO address which the PCI BIOS will use. */
113	uint32_t uPciBiosMmio;
114	/** Actual bus number. */
115	uint8_t uBus;
116	#endif
117	/** Physical address of PCI config space MMIO region. */
118	uint64_t u64PciConfigMMioAddress;
119	/** Length of PCI config space MMIO region. */
120	uint64_t u64PciConfigMMioLength;
121
122	/** PCI bus which is attached to the host-to-PCI bridge. */
123	ICH9PCIBUS aPciBus;
124	} ICH9PCIGLOBALS, *PICH9PCIGLOBALS;
125
126
127	/**
128	* PCI configuration space address.
129	*/
130	typedef struct
131	{
132	uint8_t iBus;
133	uint8_t iDeviceFunc;
134	uint16_t iRegister;
135	} PciAddress;
136
137	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
138
139
140	/*********************************************************************************************************************************
141	* Defined Constants And Macros *
142	*********************************************************************************************************************************/
143
144	/** @def VBOX_ICH9PCI_SAVED_STATE_VERSION
145	* Saved state version of the ICH9 PCI bus device.
146	*/
147	#define VBOX_ICH9PCI_SAVED_STATE_VERSION_NOMSI 1
148	#define VBOX_ICH9PCI_SAVED_STATE_VERSION_MSI 2
149	#define VBOX_ICH9PCI_SAVED_STATE_VERSION_CURRENT VBOX_ICH9PCI_SAVED_STATE_VERSION_MSI
150
151	/** Converts a bus instance pointer to a device instance pointer. */
152	#define PCIBUS_2_DEVINS(pPciBus) ((pPciBus)->CTX_SUFF(pDevIns))
153	/** Converts a device instance pointer to a ICH9PCIGLOBALS pointer. */
154	#define DEVINS_2_PCIGLOBALS(pDevIns) ((PICH9PCIGLOBALS)(PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS)))
155	/** Converts a device instance pointer to a PCIBUS pointer. */
156	#define DEVINS_2_PCIBUS(pDevIns) ((PICH9PCIBUS)(&PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS)->aPciBus))
157	/** Converts a pointer to a PCI root bus instance to a PCIGLOBALS pointer. */
158	#define PCIROOTBUS_2_PCIGLOBALS(pPciBus) ( (PICH9PCIGLOBALS)((uintptr_t)(pPciBus) - RT_OFFSETOF(ICH9PCIGLOBALS, aPciBus)) )
159
160	/** @def PCI_LOCK
161	* Acquires the PDM lock. This is a NOP if locking is disabled. */
162	/** @def PCI_UNLOCK
163	* Releases the PDM lock. This is a NOP if locking is disabled. */
164	#define PCI_LOCK(pDevIns, rc) \
165	do { \
166	int rc2 = DEVINS_2_PCIBUS(pDevIns)->CTX_SUFF(pPciHlp)->pfnLock((pDevIns), rc); \
167	if (rc2 != VINF_SUCCESS) \
168	return rc2; \
169	} while (0)
170	#define PCI_UNLOCK(pDevIns) \
171	DEVINS_2_PCIBUS(pDevIns)->CTX_SUFF(pPciHlp)->pfnUnlock(pDevIns)
172
173	/* Prototypes */
174	static void ich9pciSetIrqInternal(PICH9PCIGLOBALS pGlobals, uint8_t uDevFn, PPCIDEVICE pPciDev,
175	int iIrq, int iLevel, uint32_t uTagSrc);
176	#ifdef IN_RING3
177	static void ich9pcibridgeReset(PPDMDEVINS pDevIns);
178	static int ich9pciRegisterInternal(PICH9PCIBUS pBus, int iDev, PPCIDEVICE pPciDev, const char *pszName);
179	static void ich9pciUpdateMappings(PCIDevice *pDev);
180	static DECLCALLBACK(uint32_t) ich9pciConfigReadDev(PCIDevice *aDev, uint32_t u32Address, unsigned len);
181	DECLINLINE(PPCIDEVICE) ich9pciFindBridge(PICH9PCIBUS pBus, uint8_t iBus);
182	static void ich9pciBiosInitDevice(PICH9PCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn);
183	#endif
184
185	// See 7.2.2. PCI Express Enhanced Configuration Mechanism for details of address
186	// mapping, we take n=6 approach
187	DECLINLINE(void) ich9pciPhysToPciAddr(PICH9PCIGLOBALS pGlobals, RTGCPHYS GCPhysAddr, PciAddress* pPciAddr)
188	{
189	NOREF(pGlobals);
190	pPciAddr->iBus = (GCPhysAddr >> 20) & ((1<<6) - 1);
191	pPciAddr->iDeviceFunc = (GCPhysAddr >> 12) & ((1<<(5+3)) - 1); // 5 bits - device, 3 bits - function
192	pPciAddr->iRegister = (GCPhysAddr >> 0) & ((1<<(6+4+2)) - 1); // 6 bits - register, 4 bits - extended register, 2 bits -Byte Enable
193	}
194
195	DECLINLINE(void) ich9pciStateToPciAddr(PICH9PCIGLOBALS pGlobals, RTGCPHYS addr, PciAddress* pPciAddr)
196	{
197	pPciAddr->iBus = (pGlobals->uConfigReg >> 16) & 0xff;
198	pPciAddr->iDeviceFunc = (pGlobals->uConfigReg >> 8) & 0xff;
199	pPciAddr->iRegister = (pGlobals->uConfigReg & 0xfc) \| (addr & 3);
200	}
201
202	PDMBOTHCBDECL(void) ich9pciSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel, uint32_t uTagSrc)
203	{
204	LogFlowFunc(("invoked by %p/%d: iIrq=%d iLevel=%d uTagSrc=%#x\n", pDevIns, pDevIns->iInstance, iIrq, iLevel, uTagSrc));
205	ich9pciSetIrqInternal(PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS), pPciDev->devfn, pPciDev, iIrq, iLevel, uTagSrc);
206	}
207
208	PDMBOTHCBDECL(void) ich9pcibridgeSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel, uint32_t uTagSrc)
209	{
210	/*
211	* The PCI-to-PCI bridge specification defines how the interrupt pins
212	* are routed from the secondary to the primary bus (see chapter 9).
213	* iIrq gives the interrupt pin the pci device asserted.
214	* We change iIrq here according to the spec and call the SetIrq function
215	* of our parent passing the device which asserted the interrupt instead of the device of the bridge.
216	*/
217	PICH9PCIBUS pBus = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
218	PPCIDEVICE pPciDevBus = pPciDev;
219	int iIrqPinBridge = iIrq;
220	uint8_t uDevFnBridge = 0;
221
222	/* Walk the chain until we reach the host bus. */
223	do
224	{
225	uDevFnBridge = pBus->aPciDev.devfn;
226	iIrqPinBridge = ((pPciDevBus->devfn >> 3) + iIrqPinBridge) & 3;
227
228	/* Get the parent. */
229	pBus = pBus->aPciDev.Int.s.CTX_SUFF(pBus);
230	pPciDevBus = &pBus->aPciDev;
231	} while (pBus->iBus != 0);
232
233	AssertMsgReturnVoid(pBus->iBus == 0, ("This is not the host pci bus iBus=%d\n", pBus->iBus));
234	ich9pciSetIrqInternal(PCIROOTBUS_2_PCIGLOBALS(pBus), uDevFnBridge, pPciDev, iIrqPinBridge, iLevel, uTagSrc);
235	}
236
237
238	/**
239	* Port I/O Handler for PCI address OUT operations.
240	*
241	* Emulates writes to Configuration Address Port at 0CF8h for
242	* Configuration Mechanism #1.
243	*
244	* @returns VBox status code.
245	*
246	* @param pDevIns ICH9 device instance.
247	* @param pvUser User argument - ignored.
248	* @param uPort Port number used for the OUT operation.
249	* @param u32 The value to output.
250	* @param cb The value size in bytes.
251	*/
252	PDMBOTHCBDECL(int) ich9pciIOPortAddressWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
253	{
254	LogFlow(("ich9pciIOPortAddressWrite: Port=%#x u32=%#x cb=%d\n", Port, u32, cb));
255	NOREF(pvUser);
256	if (cb == 4)
257	{
258	PICH9PCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
259
260	/*
261	* bits [1:0] are hard-wired, read-only and must return zeroes
262	* when read.
263	*/
264	u32 &= ~3;
265
266	PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_WRITE);
267	pThis->uConfigReg = u32;
268	PCI_UNLOCK(pDevIns);
269	}
270
271	return VINF_SUCCESS;
272	}
273
274
275	/**
276	* Port I/O Handler for PCI address IN operations.
277	*
278	* Emulates reads from Configuration Address Port at 0CF8h for
279	* Configuration Mechanism #1.
280	*
281	* @returns VBox status code.
282	*
283	* @param pDevIns ICH9 device instance.
284	* @param pvUser User argument - ignored.
285	* @param uPort Port number used for the IN operation.
286	* @param pu32 Where to store the result.
287	* @param cb Number of bytes read.
288	*/
289	PDMBOTHCBDECL(int) ich9pciIOPortAddressRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
290	{
291	NOREF(pvUser);
292	if (cb == 4)
293	{
294	PICH9PCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
295
296	PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_READ);
297	*pu32 = pThis->uConfigReg;
298	PCI_UNLOCK(pDevIns);
299
300	LogFlow(("ich9pciIOPortAddressRead: Port=%#x cb=%d -> %#x\n", Port, cb, *pu32));
301	return VINF_SUCCESS;
302	}
303
304	Log(("ich9pciIOPortAddressRead: Port=%#x cb=%d VERR_IOM_IOPORT_UNUSED\n", Port, cb));
305	return VERR_IOM_IOPORT_UNUSED;
306	}
307
308
309	/*
310	* Perform configuration space write.
311	*/
312	static int ich9pciDataWriteAddr(PICH9PCIGLOBALS pGlobals, PciAddress* pAddr,
313	uint32_t val, int cb, int rcReschedule)
314	{
315	int rc = VINF_SUCCESS;
316	#ifdef IN_RING3
317	NOREF(rcReschedule);
318	#endif
319
320	if (pAddr->iBus != 0) /* forward to subordinate bus */
321	{
322	if (pGlobals->aPciBus.cBridges)
323	{
324	#ifdef IN_RING3 /** @todo do lookup in R0/RC too! */
325	PPCIDEVICE pBridgeDevice = ich9pciFindBridge(&pGlobals->aPciBus, pAddr->iBus);
326	if (pBridgeDevice)
327	{
328	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigWrite);
329	pBridgeDevice->Int.s.pfnBridgeConfigWrite(pBridgeDevice->pDevIns, pAddr->iBus, pAddr->iDeviceFunc,
330	pAddr->iRegister, val, cb);
331	}
332	#else
333	rc = rcReschedule;
334	#endif
335	}
336	}
337	else /* forward to directly connected device */
338	{
339	R3PTRTYPE(PCIDevice *) aDev = pGlobals->aPciBus.apDevices[pAddr->iDeviceFunc];
340	if (aDev)
341	{
342	#ifdef IN_RING3
343	aDev->Int.s.pfnConfigWrite(aDev, pAddr->iRegister, val, cb);
344	#else
345	rc = rcReschedule;
346	#endif
347	}
348	}
349
350	Log2(("ich9pciDataWriteAddr: %02x:%02x:%02x reg %x(%d) %x %Rrc\n",
351	pAddr->iBus, pAddr->iDeviceFunc >> 3, pAddr->iDeviceFunc & 0x7, pAddr->iRegister,
352	cb, val, rc));
353	return rc;
354	}
355
356
357	/*
358	* Decode value latched in Configuration Address Port and perform
359	* requsted write to the target configuration space register.
360	*
361	* XXX: This code should be probably moved to its only caller
362	* (ich9pciIOPortDataWrite) to avoid prolifiration of confusingly
363	* similarly named functions.
364	*/
365	static int ich9pciDataWrite(PICH9PCIGLOBALS pGlobals, uint32_t addr, uint32_t val, int len)
366	{
367	LogFlow(("ich9pciDataWrite: config=%08x val=%08x len=%d\n", pGlobals->uConfigReg, val, len));
368
369	/* Configuration space mapping enabled? */
370	if (!(pGlobals->uConfigReg & (1 << 31)))
371	return VINF_SUCCESS;
372
373	/* Decode target device and configuration space register */
374	PciAddress aPciAddr;
375	ich9pciStateToPciAddr(pGlobals, addr, &aPciAddr);
376
377	/* Perform configuration space write */
378	return ich9pciDataWriteAddr(pGlobals, &aPciAddr, val, len, VINF_IOM_R3_IOPORT_WRITE);
379	}
380
381
382	/**
383	* Port I/O Handler for PCI data OUT operations.
384	*
385	* Emulates writes to Configuration Data Port at 0CFCh for
386	* Configuration Mechanism #1.
387	*
388	* @returns VBox status code.
389	*
390	* @param pDevIns ICH9 device instance.
391	* @param pvUser User argument - ignored.
392	* @param uPort Port number used for the OUT operation.
393	* @param u32 The value to output.
394	* @param cb The value size in bytes.
395	*/
396	PDMBOTHCBDECL(int) ich9pciIOPortDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
397	{
398	LogFlow(("ich9pciIOPortDataWrite: Port=%#x u32=%#x cb=%d\n", Port, u32, cb));
399	NOREF(pvUser);
400	int rc = VINF_SUCCESS;
401	if (!(Port % cb))
402	{
403	PICH9PCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
404
405	PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_WRITE);
406	rc = ich9pciDataWrite(pThis, Port, u32, cb);
407	PCI_UNLOCK(pDevIns);
408	}
409	else
410	AssertMsgFailed(("Unaligned write to port %#x u32=%#x cb=%d\n", Port, u32, cb));
411	return rc;
412	}
413
414
415	static void ich9pciNoMem(void* ptr, int cb)
416	{
417	for (int i = 0; i < cb; i++)
418	((uint8_t*)ptr)[i] = 0xff;
419	}
420
421
422	/*
423	* Perform configuration space read.
424	*/
425	static int ich9pciDataReadAddr(PICH9PCIGLOBALS pGlobals, PciAddress* pPciAddr, int cb,
426	uint32_t *pu32, int rcReschedule)
427	{
428	int rc = VINF_SUCCESS;
429	#ifdef IN_RING3
430	NOREF(rcReschedule);
431	#endif
432
433	if (pPciAddr->iBus != 0) /* forward to subordinate bus */
434	{
435	if (pGlobals->aPciBus.cBridges)
436	{
437	#ifdef IN_RING3 /** @todo do lookup in R0/RC too! */
438	PPCIDEVICE pBridgeDevice = ich9pciFindBridge(&pGlobals->aPciBus, pPciAddr->iBus);
439	if (pBridgeDevice)
440	{
441	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigRead);
442	*pu32 = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->pDevIns, pPciAddr->iBus, pPciAddr->iDeviceFunc, pPciAddr->iRegister, cb);
443	}
444	else
445	ich9pciNoMem(pu32, cb);
446	#else
447	rc = rcReschedule;
448	#endif
449	}
450	else
451	ich9pciNoMem(pu32, cb);
452	}
453	else /* forward to directly connected device */
454	{
455	R3PTRTYPE(PCIDevice *) aDev = pGlobals->aPciBus.apDevices[pPciAddr->iDeviceFunc];
456	if (aDev)
457	{
458	#ifdef IN_RING3
459	*pu32 = aDev->Int.s.pfnConfigRead(aDev, pPciAddr->iRegister, cb);
460	#else
461	rc = rcReschedule;
462	#endif
463	}
464	else
465	ich9pciNoMem(pu32, cb);
466	}
467
468	Log3(("ich9pciDataReadAddr: %02x:%02x:%02x reg %x(%d) gave %x %Rrc\n",
469	pPciAddr->iBus, pPciAddr->iDeviceFunc >> 3, pPciAddr->iDeviceFunc & 0x7, pPciAddr->iRegister,
470	cb, *pu32, rc));
471	return rc;
472	}
473
474
475	/*
476	* Decode value latched in Configuration Address Port and perform
477	* requsted read from the target configuration space register.
478	*
479	* XXX: This code should be probably moved to its only caller
480	* (ich9pciIOPortDataRead) to avoid prolifiration of confusingly
481	* similarly named functions.
482	*/
483	static int ich9pciDataRead(PICH9PCIGLOBALS pGlobals, uint32_t addr, int cb, uint32_t *pu32)
484	{
485	LogFlow(("ich9pciDataRead: config=%x cb=%d\n", pGlobals->uConfigReg, cb));
486
487	*pu32 = 0xffffffff;
488
489	/* Configuration space mapping enabled? */
490	if (!(pGlobals->uConfigReg & (1 << 31)))
491	return VINF_SUCCESS;
492
493	/* Decode target device and configuration space register */
494	PciAddress aPciAddr;
495	ich9pciStateToPciAddr(pGlobals, addr, &aPciAddr);
496
497	/* Perform configuration space read */
498	return ich9pciDataReadAddr(pGlobals, &aPciAddr, cb, pu32, VINF_IOM_R3_IOPORT_READ);
499	}
500
501
502	/**
503	* Port I/O Handler for PCI data IN operations.
504	*
505	* Emulates reads from Configuration Data Port at 0CFCh for
506	* Configuration Mechanism #1.
507	*
508	* @returns VBox status code.
509	*
510	* @param pDevIns ICH9 device instance.
511	* @param pvUser User argument - ignored.
512	* @param uPort Port number used for the IN operation.
513	* @param pu32 Where to store the result.
514	* @param cb Number of bytes read.
515	*/
516	PDMBOTHCBDECL(int) ich9pciIOPortDataRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
517	{
518	NOREF(pvUser);
519	if (!(Port % cb))
520	{
521	PICH9PCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
522
523	PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_READ);
524	int rc = ich9pciDataRead(pThis, Port, cb, pu32);
525	PCI_UNLOCK(pDevIns);
526
527	LogFlow(("ich9pciIOPortDataRead: Port=%#x cb=%#x -> %#x (%Rrc)\n", Port, cb, *pu32, rc));
528	return rc;
529	}
530	AssertMsgFailed(("Unaligned read from port %#x cb=%d\n", Port, cb));
531	return VERR_IOM_IOPORT_UNUSED;
532	}
533
534
535	/* Compute mapping of PCI slot and IRQ number to APIC interrupt line */
536	DECLINLINE(int) ich9pciSlot2ApicIrq(uint8_t uSlot, int irq_num)
537	{
538	return (irq_num + uSlot) & 7;
539	}
540
541	/* return the global irq number corresponding to a given device irq
542	pin. We could also use the bus number to have a more precise
543	mapping. This is the implementation note described in the PCI spec chapter 2.2.6 */
544	DECLINLINE(int) ich9pciSlotGetPirq(uint8_t uBus, uint8_t uDevFn, int iIrqNum)
545	{
546	NOREF(uBus);
547	int iSlotAddend = (uDevFn >> 3) - 1;
548	return (iIrqNum + iSlotAddend) & 3;
549	}
550
551	/* irqs corresponding to PCI irqs A-D, must match pci_irq_list in rombios.c */
552	static const uint8_t aPciIrqs[4] = { 11, 10, 9, 5 };
553
554	/* Add one more level up request on APIC input line */
555	DECLINLINE(void) ich9pciApicLevelUp(PICH9PCIGLOBALS pGlobals, int irq_num)
556	{
557	ASMAtomicIncU32(&pGlobals->uaPciApicIrqLevels[irq_num]);
558	}
559
560	/* Remove one level up request on APIC input line */
561	DECLINLINE(void) ich9pciApicLevelDown(PICH9PCIGLOBALS pGlobals, int irq_num)
562	{
563	ASMAtomicDecU32(&pGlobals->uaPciApicIrqLevels[irq_num]);
564	}
565
566	static void ich9pciApicSetIrq(PICH9PCIBUS pBus, uint8_t uDevFn, PCIDevice *pPciDev, int irq_num1, int iLevel,
567	uint32_t uTagSrc, int iForcedIrq)
568	{
569	/* This is only allowed to be called with a pointer to the root bus. */
570	AssertMsg(pBus->iBus == 0, ("iBus=%u\n", pBus->iBus));
571
572	if (iForcedIrq == -1)
573	{
574	int apic_irq, apic_level;
575	PICH9PCIGLOBALS pGlobals = PCIROOTBUS_2_PCIGLOBALS(pBus);
576	int irq_num = ich9pciSlot2ApicIrq(uDevFn >> 3, irq_num1);
577
578	if ((iLevel & PDM_IRQ_LEVEL_HIGH) == PDM_IRQ_LEVEL_HIGH)
579	ich9pciApicLevelUp(pGlobals, irq_num);
580	else if ((iLevel & PDM_IRQ_LEVEL_HIGH) == PDM_IRQ_LEVEL_LOW)
581	ich9pciApicLevelDown(pGlobals, irq_num);
582
583	apic_irq = irq_num + 0x10;
584	apic_level = pGlobals->uaPciApicIrqLevels[irq_num] != 0;
585	Log3(("ich9pciApicSetIrq: %s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d uTagSrc=%#x\n",
586	R3STRING(pPciDev->name), irq_num1, iLevel, apic_irq, apic_level, irq_num, uTagSrc));
587	pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), apic_irq, apic_level, uTagSrc);
588
589	if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP)
590	{
591	/*
592	* we raised it few lines above, as PDM_IRQ_LEVEL_FLIP_FLOP has
593	* PDM_IRQ_LEVEL_HIGH bit set
594	*/
595	ich9pciApicLevelDown(pGlobals, irq_num);
596	pPciDev->Int.s.uIrqPinState = PDM_IRQ_LEVEL_LOW;
597	apic_level = pGlobals->uaPciApicIrqLevels[irq_num] != 0;
598	Log3(("ich9pciApicSetIrq: %s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d uTagSrc=%#x (flop)\n",
599	R3STRING(pPciDev->name), irq_num1, iLevel, apic_irq, apic_level, irq_num, uTagSrc));
600	pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), apic_irq, apic_level, uTagSrc);
601	}
602	} else {
603	Log3(("ich9pciApicSetIrq: (forced) %s: irq_num1=%d level=%d acpi_irq=%d uTagSrc=%#x\n",
604	R3STRING(pPciDev->name), irq_num1, iLevel, iForcedIrq, uTagSrc));
605	pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), iForcedIrq, iLevel, uTagSrc);
606	}
607	}
608
609	static void ich9pciSetIrqInternal(PICH9PCIGLOBALS pGlobals, uint8_t uDevFn, PPCIDEVICE pPciDev,
610	int iIrq, int iLevel, uint32_t uTagSrc)
611	{
612	/* If MSI or MSI-X is enabled, PCI INTx# signals are disabled regardless of the PCI command
613	* register interrupt bit state.
614	* PCI 3.0 (section 6.8) forbids MSI and MSI-X to be enabled at the same time and makes
615	* that undefined behavior. We check for MSI first, then MSI-X.
616	*/
617	if (MsiIsEnabled(pPciDev))
618	{
619	Assert(!MsixIsEnabled(pPciDev)); /* Not allowed -- see note above. */
620	LogFlowFunc(("PCI Dev %p : MSI\n", pPciDev));
621	PPDMDEVINS pDevIns = pGlobals->aPciBus.CTX_SUFF(pDevIns);
622	MsiNotify(pDevIns, pGlobals->aPciBus.CTX_SUFF(pPciHlp), pPciDev, iIrq, iLevel, uTagSrc);
623	return;
624	}
625
626	if (MsixIsEnabled(pPciDev))
627	{
628	LogFlowFunc(("PCI Dev %p : MSI-X\n", pPciDev));
629	PPDMDEVINS pDevIns = pGlobals->aPciBus.CTX_SUFF(pDevIns);
630	MsixNotify(pDevIns, pGlobals->aPciBus.CTX_SUFF(pPciHlp), pPciDev, iIrq, iLevel, uTagSrc);
631	return;
632	}
633
634	PICH9PCIBUS pBus = &pGlobals->aPciBus;
635	const bool fIsAcpiDevice = PCIDevGetDeviceId(pPciDev) == 0x7113;
636
637	LogFlowFunc(("PCI Dev %p : IRQ\n", pPciDev));
638	/* Check if the state changed. */
639	if (pPciDev->Int.s.uIrqPinState != iLevel)
640	{
641	pPciDev->Int.s.uIrqPinState = (iLevel & PDM_IRQ_LEVEL_HIGH);
642
643	/* Send interrupt to I/O APIC only now. */
644	if (fIsAcpiDevice)
645	/*
646	* ACPI needs special treatment since SCI is hardwired and
647	* should not be affected by PCI IRQ routing tables at the
648	* same time SCI IRQ is shared in PCI sense hence this
649	* kludge (i.e. we fetch the hardwired value from ACPIs
650	* PCI device configuration space).
651	*/
652	ich9pciApicSetIrq(pBus, uDevFn, pPciDev, -1, iLevel, uTagSrc, PCIDevGetInterruptLine(pPciDev));
653	else
654	ich9pciApicSetIrq(pBus, uDevFn, pPciDev, iIrq, iLevel, uTagSrc, -1);
655	}
656	}
657
658
659	/**
660	* Memory mapped I/O Handler for write operations.
661	*
662	* Emulates writes to configuration space.
663	*
664	* @returns VBox status code.
665	*
666	* @param pDevIns The device instance.
667	* @param pvUser User argument.
668	* @param GCPhysAddr Physical address (in GC) where the read starts.
669	* @param pv Where to fetch the result.
670	* @param cb Number of bytes to write.
671	* @remarks Caller enters the device critical section.
672	*/
673	PDMBOTHCBDECL(int) ich9pciMcfgMMIOWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void const pv, unsigned cb)
674	{
675	PICH9PCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
676	uint32_t u32 = 0;
677	NOREF(pvUser);
678
679	Log2(("ich9pciMcfgMMIOWrite: %RGp(%d) \n", GCPhysAddr, cb));
680
681	PCI_LOCK(pDevIns, VINF_IOM_R3_MMIO_WRITE);
682
683	/* Decode target device and configuration space register */
684	PciAddress aDest;
685	ich9pciPhysToPciAddr(pGlobals, GCPhysAddr, &aDest);
686
687	switch (cb)
688	{
689	case 1:
690	u32 = (uint8_t)pv;
691	break;
692	case 2:
693	u32 = (uint16_t)pv;
694	break;
695	case 4:
696	u32 = (uint32_t)pv;
697	break;
698	default:
699	Assert(false);
700	break;
701	}
702
703	/* Perform configuration space write */
704	int rc = ich9pciDataWriteAddr(pGlobals, &aDest, u32, cb, VINF_IOM_R3_MMIO_WRITE);
705	PCI_UNLOCK(pDevIns);
706
707	return rc;
708	}
709
710
711	/**
712	* Memory mapped I/O Handler for read operations.
713	*
714	* Emulates reads from configuration space.
715	*
716	* @returns VBox status code.
717	*
718	* @param pDevIns The device instance.
719	* @param pvUser User argument.
720	* @param GCPhysAddr Physical address (in GC) where the read starts.
721	* @param pv Where to store the result.
722	* @param cb Number of bytes read.
723	* @remarks Caller enters the device critical section.
724	*/
725	PDMBOTHCBDECL(int) ich9pciMcfgMMIORead (PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb)
726	{
727	PICH9PCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
728	uint32_t rv;
729	NOREF(pvUser);
730
731	LogFlow(("ich9pciMcfgMMIORead: %RGp(%d) \n", GCPhysAddr, cb));
732
733	PCI_LOCK(pDevIns, VINF_IOM_R3_MMIO_READ);
734
735	/* Decode target device and configuration space register */
736	PciAddress aDest;
737	ich9pciPhysToPciAddr(pGlobals, GCPhysAddr, &aDest);
738
739	/* Perform configuration space read */
740	int rc = ich9pciDataReadAddr(pGlobals, &aDest, cb, &rv, VINF_IOM_R3_MMIO_READ);
741
742	if (RT_SUCCESS(rc))
743	{
744	switch (cb)
745	{
746	case 1:
747	(uint8_t)pv = (uint8_t)rv;
748	break;
749	case 2:
750	(uint16_t)pv = (uint16_t)rv;
751	break;
752	case 4:
753	(uint32_t)pv = (uint32_t)rv;
754	break;
755	default:
756	Assert(false);
757	break;
758	}
759	}
760	PCI_UNLOCK(pDevIns);
761
762	return rc;
763	}
764
765	#ifdef IN_RING3
766
767	DECLINLINE(PPCIDEVICE) ich9pciFindBridge(PICH9PCIBUS pBus, uint8_t iBus)
768	{
769	/* Search for a fitting bridge. */
770	for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
771	{
772	/*
773	* Examine secondary and subordinate bus number.
774	* If the target bus is in the range we pass the request on to the bridge.
775	*/
776	PPCIDEVICE pBridge = pBus->papBridgesR3[iBridge];
777	AssertMsg(pBridge && pciDevIsPci2PciBridge(pBridge),
778	("Device is not a PCI bridge but on the list of PCI bridges\n"));
779	uint32_t uSecondary = PCIDevGetByte(pBridge, VBOX_PCI_SECONDARY_BUS);
780	uint32_t uSubordinate = PCIDevGetByte(pBridge, VBOX_PCI_SUBORDINATE_BUS);
781	Log3(("ich9pciFindBridge on bus %p, bridge %d: %d in %d..%d\n", pBus, iBridge, iBus, uSecondary, uSubordinate));
782	if (iBus >= uSecondary && iBus <= uSubordinate)
783	return pBridge;
784	}
785
786	/* Nothing found. */
787	return NULL;
788	}
789
790	static uint32_t ich9pciGetCfg(PCIDevice* aDev, int32_t iRegister, int cb)
791	{
792	return aDev->Int.s.pfnConfigRead(aDev, iRegister, cb);
793	}
794
795	static uint8_t ich9pciGetByte(PCIDevice* aDev, int32_t iRegister)
796	{
797	return (uint8_t)ich9pciGetCfg(aDev, iRegister, 1);
798	}
799
800	static uint16_t ich9pciGetWord(PCIDevice* aDev, int32_t iRegister)
801	{
802	return (uint16_t)ich9pciGetCfg(aDev, iRegister, 2);
803	}
804
805	static uint32_t ich9pciGetDWord(PCIDevice* aDev, int32_t iRegister)
806	{
807	return (uint32_t)ich9pciGetCfg(aDev, iRegister, 4);
808	}
809
810	DECLINLINE(uint32_t) ich9pciGetRegionReg(int iRegion)
811	{
812	return (iRegion == VBOX_PCI_ROM_SLOT) ?
813	VBOX_PCI_ROM_ADDRESS : (VBOX_PCI_BASE_ADDRESS_0 + iRegion * 4);
814	}
815
816	#define INVALID_PCI_ADDRESS ~0U
817
818	static int ich9pciUnmapRegion(PPCIDEVICE pDev, int iRegion)
819	{
820	PCIIORegion* pRegion = &pDev->Int.s.aIORegions[iRegion];
821	int rc = VINF_SUCCESS;
822	PICH9PCIBUS pBus = pDev->Int.s.CTX_SUFF(pBus);
823
824	Assert (pRegion->size != 0);
825
826	if (pRegion->addr != INVALID_PCI_ADDRESS)
827	{
828	if (pRegion->type & PCI_ADDRESS_SPACE_IO)
829	{
830	/* Port IO */
831	rc = PDMDevHlpIOPortDeregister(pDev->pDevIns, pRegion->addr, pRegion->size);
832	AssertRC(rc);
833	}
834	else
835	{
836	RTGCPHYS GCPhysBase = pRegion->addr;
837	if (pBus->pPciHlpR3->pfnIsMMIO2Base(pBus->pDevInsR3, pDev->pDevIns, GCPhysBase))
838	{
839	/* unmap it. */
840	rc = pRegion->map_func(pDev, iRegion, NIL_RTGCPHYS, pRegion->size, (PCIADDRESSSPACE)(pRegion->type));
841	AssertRC(rc);
842	rc = PDMDevHlpMMIO2Unmap(pDev->pDevIns, iRegion, GCPhysBase);
843	}
844	else
845	rc = PDMDevHlpMMIODeregister(pDev->pDevIns, GCPhysBase, pRegion->size);
846	}
847
848	pRegion->addr = INVALID_PCI_ADDRESS;
849	}
850
851	return rc;
852	}
853
854	static void ich9pciUpdateMappings(PCIDevice* pDev)
855	{
856	uint64_t uLast, uNew;
857
858	int iCmd = ich9pciGetWord(pDev, VBOX_PCI_COMMAND);
859	for (int iRegion = 0; iRegion < PCI_NUM_REGIONS; iRegion++)
860	{
861	PCIIORegion* pRegion = &pDev->Int.s.aIORegions[iRegion];
862	uint32_t uConfigReg = ich9pciGetRegionReg(iRegion);
863	int64_t iRegionSize = pRegion->size;
864	int rc;
865
866	if (iRegionSize == 0)
867	continue;
868
869	bool f64Bit = (pRegion->type & PCI_ADDRESS_SPACE_BAR64) != 0;
870
871	if (pRegion->type & PCI_ADDRESS_SPACE_IO)
872	{
873	/* port IO region */
874	if (iCmd & PCI_COMMAND_IOACCESS)
875	{
876	/* IO access allowed */
877	uNew = ich9pciGetDWord(pDev, uConfigReg);
878	uNew &= ~(iRegionSize - 1);
879	uLast = uNew + iRegionSize - 1;
880	/* only 64K ioports on PC */
881	if (uLast <= uNew \|\| uNew == 0 \|\| uLast >= 0x10000)
882	uNew = INVALID_PCI_ADDRESS;
883	} else
884	uNew = INVALID_PCI_ADDRESS;
885	}
886	else
887	{
888	/* MMIO region */
889	if (iCmd & PCI_COMMAND_MEMACCESS)
890	{
891	uNew = ich9pciGetDWord(pDev, uConfigReg);
892
893	if (f64Bit)
894	{
895	uNew \|= ((uint64_t)ich9pciGetDWord(pDev, uConfigReg+4)) << 32;
896	if (uNew > UINT64_C(0x0000010000000000))
897	{
898	/* Workaround for REM being unhapping with mapping very lange 64-bit addresses */
899	Log(("Ignoring too 64-bit BAR: %llx\n", uNew));
900	uNew = INVALID_PCI_ADDRESS;
901	}
902	}
903
904	/* the ROM slot has a specific enable bit */
905	if (iRegion == PCI_ROM_SLOT && !(uNew & 1))
906	uNew = INVALID_PCI_ADDRESS;
907	else
908	{
909	uNew &= ~(iRegionSize - 1);
910	uLast = uNew + iRegionSize - 1;
911	/* NOTE: we do not support wrapping */
912	/* XXX: as we cannot support really dynamic
913	mappings, we handle specific values as invalid
914	mappings. */
915	if (uLast <= uNew \|\| uNew == 0 \|\| uLast == INVALID_PCI_ADDRESS)
916	uNew = INVALID_PCI_ADDRESS;
917	}
918	} else
919	uNew = INVALID_PCI_ADDRESS;
920	}
921	/* now do the real mapping */
922	if (uNew != pRegion->addr)
923	{
924	if (pRegion->addr != INVALID_PCI_ADDRESS)
925	ich9pciUnmapRegion(pDev, iRegion);
926
927	pRegion->addr = uNew;
928	if (pRegion->addr != INVALID_PCI_ADDRESS)
929	{
930
931	/* finally, map the region */
932	rc = pRegion->map_func(pDev, iRegion,
933	pRegion->addr, pRegion->size,
934	(PCIADDRESSSPACE)(pRegion->type));
935	AssertRC(rc);
936	}
937	}
938	}
939	}
940
941	static DECLCALLBACK(int) ich9pciRegister(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, const char *pszName, int iDev)
942	{
943	PICH9PCIBUS pBus = DEVINS_2_PCIBUS(pDevIns);
944
945	/*
946	* Check input.
947	*/
948	if ( !pszName
949	\|\| !pPciDev
950	\|\| iDev >= (int)RT_ELEMENTS(pBus->apDevices)
951	)
952	{
953	AssertMsgFailed(("Invalid argument! pszName=%s pPciDev=%p iDev=%d\n", pszName, pPciDev, iDev));
954	return VERR_INVALID_PARAMETER;
955	}
956
957	/*
958	* Register the device.
959	*/
960	return ich9pciRegisterInternal(pBus, iDev, pPciDev, pszName);
961	}
962
963
964	static DECLCALLBACK(int) ich9pciRegisterMsi(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PPDMMSIREG pMsiReg)
965	{
966	NOREF(pDevIns);
967	int rc;
968
969	rc = MsiInit(pPciDev, pMsiReg);
970	if (RT_FAILURE(rc))
971	return rc;
972
973	rc = MsixInit(pPciDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pPciHlp), pPciDev, pMsiReg);
974	if (RT_FAILURE(rc))
975	return rc;
976
977	return VINF_SUCCESS;
978	}
979
980
981	static DECLCALLBACK(int) ich9pcibridgeRegister(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, const char *pszName, int iDev)
982	{
983
984	PICH9PCIBUS pBus = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
985
986	/*
987	* Check input.
988	*/
989	if ( !pszName
990	\|\| !pPciDev
991	\|\| iDev >= (int)RT_ELEMENTS(pBus->apDevices))
992	{
993	AssertMsgFailed(("Invalid argument! pszName=%s pPciDev=%p iDev=%d\n", pszName, pPciDev, iDev));
994	return VERR_INVALID_PARAMETER;
995	}
996
997	/*
998	* Register the device.
999	*/
1000	return ich9pciRegisterInternal(pBus, iDev, pPciDev, pszName);
1001	}
1002
1003	static DECLCALLBACK(int) ich9pciIORegionRegister(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iRegion, uint32_t cbRegion, PCIADDRESSSPACE enmType, PFNPCIIOREGIONMAP pfnCallback)
1004	{
1005	NOREF(pDevIns);
1006
1007	/*
1008	* Validate.
1009	*/
1010	AssertMsgReturn( enmType == (PCI_ADDRESS_SPACE_MEM \| PCI_ADDRESS_SPACE_BAR32)
1011	\|\| enmType == (PCI_ADDRESS_SPACE_MEM_PREFETCH \| PCI_ADDRESS_SPACE_BAR32)
1012	\|\| enmType == (PCI_ADDRESS_SPACE_MEM \| PCI_ADDRESS_SPACE_BAR64)
1013	\|\| enmType == (PCI_ADDRESS_SPACE_MEM_PREFETCH \| PCI_ADDRESS_SPACE_BAR64)
1014	\|\| enmType == PCI_ADDRESS_SPACE_IO
1015	,
1016	("Invalid enmType=%#x? Or was this a bitmask after all...\n", enmType),
1017	VERR_INVALID_PARAMETER);
1018	AssertMsgReturn((unsigned)iRegion < PCI_NUM_REGIONS,
1019	("Invalid iRegion=%d PCI_NUM_REGIONS=%d\n", iRegion, PCI_NUM_REGIONS),
1020	VERR_INVALID_PARAMETER);
1021	int iLastSet = ASMBitLastSetU32(cbRegion);
1022	AssertMsgReturn( iLastSet != 0
1023	&& RT_BIT_32(iLastSet - 1) == cbRegion,
1024	("Invalid cbRegion=%#x iLastSet=%#x (not a power of 2 or 0)\n", cbRegion, iLastSet),
1025	VERR_INVALID_PARAMETER);
1026
1027	Log(("ich9pciIORegionRegister: %s region %d size %d type %x\n",
1028	pPciDev->name, iRegion, cbRegion, enmType));
1029
1030	/* Make sure that we haven't marked this region as continuation of 64-bit region. */
1031	Assert(pPciDev->Int.s.aIORegions[iRegion].type != 0xff);
1032
1033	/*
1034	* Register the I/O region.
1035	*/
1036	PPCIIOREGION pRegion = &pPciDev->Int.s.aIORegions[iRegion];
1037	pRegion->addr = INVALID_PCI_ADDRESS;
1038	pRegion->size = cbRegion;
1039	pRegion->type = enmType;
1040	pRegion->map_func = pfnCallback;
1041
1042	if ((enmType & PCI_ADDRESS_SPACE_BAR64) != 0)
1043	{
1044	AssertMsgReturn(iRegion < 4,
1045	("Region %d cannot be 64-bit\n", iRegion),
1046	VERR_INVALID_PARAMETER);
1047	/* Mark next region as continuation of this one. */
1048	pPciDev->Int.s.aIORegions[iRegion+1].type = 0xff;
1049	}
1050
1051	/* Set type in the PCI config space. */
1052	uint32_t u32Value = ((uint32_t)enmType) & (PCI_ADDRESS_SPACE_IO \| PCI_ADDRESS_SPACE_BAR64 \| PCI_ADDRESS_SPACE_MEM_PREFETCH);
1053	PCIDevSetDWord(pPciDev, ich9pciGetRegionReg(iRegion), u32Value);
1054
1055	return VINF_SUCCESS;
1056	}
1057
1058	static DECLCALLBACK(void) ich9pciSetConfigCallbacks(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PFNPCICONFIGREAD pfnRead, PPFNPCICONFIGREAD ppfnReadOld,
1059	PFNPCICONFIGWRITE pfnWrite, PPFNPCICONFIGWRITE ppfnWriteOld)
1060	{
1061	NOREF(pDevIns);
1062
1063	if (ppfnReadOld)
1064	*ppfnReadOld = pPciDev->Int.s.pfnConfigRead;
1065	pPciDev->Int.s.pfnConfigRead = pfnRead;
1066
1067	if (ppfnWriteOld)
1068	*ppfnWriteOld = pPciDev->Int.s.pfnConfigWrite;
1069	pPciDev->Int.s.pfnConfigWrite = pfnWrite;
1070	}
1071
1072	static int ich9pciR3CommonSaveExec(PICH9PCIBUS pBus, PSSMHANDLE pSSM)
1073	{
1074	/*
1075	* Iterate thru all the devices.
1076	*/
1077	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
1078	{
1079	PPCIDEVICE pDev = pBus->apDevices[i];
1080	if (pDev)
1081	{
1082	/* Device position */
1083	SSMR3PutU32(pSSM, i);
1084	/* PCI config registers */
1085	SSMR3PutMem(pSSM, pDev->config, sizeof(pDev->config));
1086
1087	/* Device flags */
1088	int rc = SSMR3PutU32(pSSM, pDev->Int.s.fFlags);
1089	if (RT_FAILURE(rc))
1090	return rc;
1091
1092	/* IRQ pin state */
1093	rc = SSMR3PutS32(pSSM, pDev->Int.s.uIrqPinState);
1094	if (RT_FAILURE(rc))
1095	return rc;
1096
1097	/* MSI info */
1098	rc = SSMR3PutU8(pSSM, pDev->Int.s.u8MsiCapOffset);
1099	if (RT_FAILURE(rc))
1100	return rc;
1101	rc = SSMR3PutU8(pSSM, pDev->Int.s.u8MsiCapSize);
1102	if (RT_FAILURE(rc))
1103	return rc;
1104
1105	/* MSI-X info */
1106	rc = SSMR3PutU8(pSSM, pDev->Int.s.u8MsixCapOffset);
1107	if (RT_FAILURE(rc))
1108	return rc;
1109	rc = SSMR3PutU8(pSSM, pDev->Int.s.u8MsixCapSize);
1110	if (RT_FAILURE(rc))
1111	return rc;
1112	/* Save MSI-X page state */
1113	if (pDev->Int.s.u8MsixCapOffset != 0)
1114	{
1115	Assert(pDev->Int.s.pMsixPageR3 != NULL);
1116	SSMR3PutMem(pSSM, pDev->Int.s.pMsixPageR3, 0x1000);
1117	if (RT_FAILURE(rc))
1118	return rc;
1119	}
1120	}
1121	}
1122	return SSMR3PutU32(pSSM, UINT32_MAX); /* terminator */
1123	}
1124
1125	static DECLCALLBACK(int) ich9pciR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
1126	{
1127	PICH9PCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
1128
1129	/*
1130	* Bus state data.
1131	*/
1132	SSMR3PutU32(pSSM, pThis->uConfigReg);
1133
1134	/*
1135	* Save IRQ states.
1136	*/
1137	for (int i = 0; i < PCI_APIC_IRQ_PINS; i++)
1138	SSMR3PutU32(pSSM, pThis->uaPciApicIrqLevels[i]);
1139
1140	SSMR3PutU32(pSSM, ~0); /* separator */
1141
1142	return ich9pciR3CommonSaveExec(&pThis->aPciBus, pSSM);
1143	}
1144
1145
1146	static DECLCALLBACK(int) ich9pcibridgeR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
1147	{
1148	PICH9PCIBUS pThis = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
1149	return ich9pciR3CommonSaveExec(pThis, pSSM);
1150	}
1151
1152
1153	static DECLCALLBACK(void) ich9pcibridgeConfigWrite(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice, uint32_t u32Address, uint32_t u32Value, unsigned cb)
1154	{
1155	PICH9PCIBUS pBus = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
1156
1157	LogFlowFunc((": pDevIns=%p iBus=%d iDevice=%d u32Address=%u u32Value=%u cb=%d\n", pDevIns, iBus, iDevice, u32Address, u32Value, cb));
1158
1159	/* If the current bus is not the target bus search for the bus which contains the device. */
1160	if (iBus != PCIDevGetByte(&pBus->aPciDev, VBOX_PCI_SECONDARY_BUS))
1161	{
1162	PPCIDEVICE pBridgeDevice = ich9pciFindBridge(pBus, iBus);
1163	if (pBridgeDevice)
1164	{
1165	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigWrite);
1166	pBridgeDevice->Int.s.pfnBridgeConfigWrite(pBridgeDevice->pDevIns, iBus, iDevice, u32Address, u32Value, cb);
1167	}
1168	}
1169	else
1170	{
1171	/* This is the target bus, pass the write to the device. */
1172	PPCIDEVICE pPciDev = pBus->apDevices[iDevice];
1173	if (pPciDev)
1174	{
1175	Log(("%s: %s: addr=%02x val=%08x len=%d\n", __FUNCTION__, pPciDev->name, u32Address, u32Value, cb));
1176	pPciDev->Int.s.pfnConfigWrite(pPciDev, u32Address, u32Value, cb);
1177	}
1178	}
1179	}
1180
1181	static DECLCALLBACK(uint32_t) ich9pcibridgeConfigRead(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice, uint32_t u32Address, unsigned cb)
1182	{
1183	PICH9PCIBUS pBus = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
1184	uint32_t u32Value;
1185
1186	LogFlowFunc((": pDevIns=%p iBus=%d iDevice=%d u32Address=%u cb=%d\n", pDevIns, iBus, iDevice, u32Address, cb));
1187
1188	/* If the current bus is not the target bus search for the bus which contains the device. */
1189	if (iBus != PCIDevGetByte(&pBus->aPciDev, VBOX_PCI_SECONDARY_BUS))
1190	{
1191	PPCIDEVICE pBridgeDevice = ich9pciFindBridge(pBus, iBus);
1192	if (pBridgeDevice)
1193	{
1194	AssertPtr( pBridgeDevice->Int.s.pfnBridgeConfigRead);
1195	u32Value = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->pDevIns, iBus, iDevice, u32Address, cb);
1196	}
1197	else
1198	ich9pciNoMem(&u32Value, 4);
1199	}
1200	else
1201	{
1202	/* This is the target bus, pass the read to the device. */
1203	PPCIDEVICE pPciDev = pBus->apDevices[iDevice];
1204	if (pPciDev)
1205	{
1206	u32Value = pPciDev->Int.s.pfnConfigRead(pPciDev, u32Address, cb);
1207	Log(("%s: %s: u32Address=%02x u32Value=%08x cb=%d\n", __FUNCTION__, pPciDev->name, u32Address, u32Value, cb));
1208	}
1209	else
1210	ich9pciNoMem(&u32Value, 4);
1211	}
1212
1213	return u32Value;
1214	}
1215
1216
1217	/**
1218	* Common routine for restoring the config registers of a PCI device.
1219	*
1220	* @param pDev The PCI device.
1221	* @param pbSrcConfig The configuration register values to be loaded.
1222	* @param fIsBridge Whether this is a bridge device or not.
1223	*/
1224	static void pciR3CommonRestoreConfig(PPCIDEVICE pDev, uint8_t const *pbSrcConfig, bool fIsBridge)
1225	{
1226	/*
1227	* This table defines the fields for normal devices and bridge devices, and
1228	* the order in which they need to be restored.
1229	*/
1230	static const struct PciField
1231	{
1232	uint8_t off;
1233	uint8_t cb;
1234	uint8_t fWritable;
1235	uint8_t fBridge;
1236	const char *pszName;
1237	} s_aFields[] =
1238	{
1239	/* off,cb,fW,fB, pszName */
1240	{ 0x00, 2, 0, 3, "VENDOR_ID" },
1241	{ 0x02, 2, 0, 3, "DEVICE_ID" },
1242	{ 0x06, 2, 1, 3, "STATUS" },
1243	{ 0x08, 1, 0, 3, "REVISION_ID" },
1244	{ 0x09, 1, 0, 3, "CLASS_PROG" },
1245	{ 0x0a, 1, 0, 3, "CLASS_SUB" },
1246	{ 0x0b, 1, 0, 3, "CLASS_BASE" },
1247	{ 0x0c, 1, 1, 3, "CACHE_LINE_SIZE" },
1248	{ 0x0d, 1, 1, 3, "LATENCY_TIMER" },
1249	{ 0x0e, 1, 0, 3, "HEADER_TYPE" },
1250	{ 0x0f, 1, 1, 3, "BIST" },
1251	{ 0x10, 4, 1, 3, "BASE_ADDRESS_0" },
1252	{ 0x14, 4, 1, 3, "BASE_ADDRESS_1" },
1253	{ 0x18, 4, 1, 1, "BASE_ADDRESS_2" },
1254	{ 0x18, 1, 1, 2, "PRIMARY_BUS" }, // fWritable = ??
1255	{ 0x19, 1, 1, 2, "SECONDARY_BUS" }, // fWritable = ??
1256	{ 0x1a, 1, 1, 2, "SUBORDINATE_BUS" }, // fWritable = ??
1257	{ 0x1b, 1, 1, 2, "SEC_LATENCY_TIMER" }, // fWritable = ??
1258	{ 0x1c, 4, 1, 1, "BASE_ADDRESS_3" },
1259	{ 0x1c, 1, 1, 2, "IO_BASE" }, // fWritable = ??
1260	{ 0x1d, 1, 1, 2, "IO_LIMIT" }, // fWritable = ??
1261	{ 0x1e, 2, 1, 2, "SEC_STATUS" }, // fWritable = ??
1262	{ 0x20, 4, 1, 1, "BASE_ADDRESS_4" },
1263	{ 0x20, 2, 1, 2, "MEMORY_BASE" }, // fWritable = ??
1264	{ 0x22, 2, 1, 2, "MEMORY_LIMIT" }, // fWritable = ??
1265	{ 0x24, 4, 1, 1, "BASE_ADDRESS_5" },
1266	{ 0x24, 2, 1, 2, "PREF_MEMORY_BASE" }, // fWritable = ??
1267	{ 0x26, 2, 1, 2, "PREF_MEMORY_LIMIT" }, // fWritable = ??
1268	{ 0x28, 4, 1, 1, "CARDBUS_CIS" }, // fWritable = ??
1269	{ 0x28, 4, 1, 2, "PREF_BASE_UPPER32" }, // fWritable = ??
1270	{ 0x2c, 2, 0, 1, "SUBSYSTEM_VENDOR_ID" },// fWritable = !?
1271	{ 0x2c, 4, 1, 2, "PREF_LIMIT_UPPER32" },// fWritable = ??
1272	{ 0x2e, 2, 0, 1, "SUBSYSTEM_ID" }, // fWritable = !?
1273	{ 0x30, 4, 1, 1, "ROM_ADDRESS" }, // fWritable = ?!
1274	{ 0x30, 2, 1, 2, "IO_BASE_UPPER16" }, // fWritable = ?!
1275	{ 0x32, 2, 1, 2, "IO_LIMIT_UPPER16" }, // fWritable = ?!
1276	{ 0x34, 4, 0, 3, "CAPABILITY_LIST" }, // fWritable = !? cb=!?
1277	{ 0x38, 4, 1, 1, "RESERVED_38" }, // ???
1278	{ 0x38, 4, 1, 2, "ROM_ADDRESS_BR" }, // fWritable = !? cb=!? fBridge=!?
1279	{ 0x3c, 1, 1, 3, "INTERRUPT_LINE" }, // fBridge=??
1280	{ 0x3d, 1, 0, 3, "INTERRUPT_PIN" }, // fBridge=??
1281	{ 0x3e, 1, 0, 1, "MIN_GNT" },
1282	{ 0x3e, 2, 1, 2, "BRIDGE_CONTROL" }, // fWritable = !?
1283	{ 0x3f, 1, 0, 1, "MAX_LAT" },
1284	/* The COMMAND register must come last as it requires the ADDRESS
1285	registers to be restored before we pretent to change it from 0 to
1286	whatever value the guest assigned it. */
1287	{ 0x04, 2, 1, 3, "COMMAND" },
1288	};
1289
1290	#ifdef RT_STRICT
1291	/* Check that we've got full register coverage. */
1292	uint32_t bmDevice[0x40 / 32];
1293	uint32_t bmBridge[0x40 / 32];
1294	RT_ZERO(bmDevice);
1295	RT_ZERO(bmBridge);
1296	for (uint32_t i = 0; i < RT_ELEMENTS(s_aFields); i++)
1297	{
1298	uint8_t off = s_aFields[i].off;
1299	uint8_t cb = s_aFields[i].cb;
1300	uint8_t f = s_aFields[i].fBridge;
1301	while (cb-- > 0)
1302	{
1303	if (f & 1) AssertMsg(!ASMBitTest(bmDevice, off), ("%#x\n", off));
1304	if (f & 2) AssertMsg(!ASMBitTest(bmBridge, off), ("%#x\n", off));
1305	if (f & 1) ASMBitSet(bmDevice, off);
1306	if (f & 2) ASMBitSet(bmBridge, off);
1307	off++;
1308	}
1309	}
1310	for (uint32_t off = 0; off < 0x40; off++)
1311	{
1312	AssertMsg(ASMBitTest(bmDevice, off), ("%#x\n", off));
1313	AssertMsg(ASMBitTest(bmBridge, off), ("%#x\n", off));
1314	}
1315	#endif
1316
1317	/*
1318	* Loop thru the fields covering the 64 bytes of standard registers.
1319	*/
1320	uint8_t const fBridge = fIsBridge ? 2 : 1;
1321	Assert(!pciDevIsPassthrough(pDev));
1322	uint8_t *pbDstConfig = &pDev->config[0];
1323
1324	for (uint32_t i = 0; i < RT_ELEMENTS(s_aFields); i++)
1325	if (s_aFields[i].fBridge & fBridge)
1326	{
1327	uint8_t const off = s_aFields[i].off;
1328	uint8_t const cb = s_aFields[i].cb;
1329	uint32_t u32Src;
1330	uint32_t u32Dst;
1331	switch (cb)
1332	{
1333	case 1:
1334	u32Src = pbSrcConfig[off];
1335	u32Dst = pbDstConfig[off];
1336	break;
1337	case 2:
1338	u32Src = (uint16_t const )&pbSrcConfig[off];
1339	u32Dst = (uint16_t const )&pbDstConfig[off];
1340	break;
1341	case 4:
1342	u32Src = (uint32_t const )&pbSrcConfig[off];
1343	u32Dst = (uint32_t const )&pbDstConfig[off];
1344	break;
1345	default:
1346	AssertFailed();
1347	continue;
1348	}
1349
1350	if ( u32Src != u32Dst
1351	\|\| off == VBOX_PCI_COMMAND)
1352	{
1353	if (u32Src != u32Dst)
1354	{
1355	if (!s_aFields[i].fWritable)
1356	LogRel(("PCI: %8s/%u: %2u-bit field %s: %x -> %x - !READ ONLY!\n",
1357	pDev->name, pDev->pDevIns->iInstance, cb*8, s_aFields[i].pszName, u32Dst, u32Src));
1358	else
1359	LogRel(("PCI: %8s/%u: %2u-bit field %s: %x -> %x\n",
1360	pDev->name, pDev->pDevIns->iInstance, cb*8, s_aFields[i].pszName, u32Dst, u32Src));
1361	}
1362	if (off == VBOX_PCI_COMMAND)
1363	PCIDevSetCommand(pDev, 0); /* For remapping, see ich9pciR3CommonLoadExec. */
1364	pDev->Int.s.pfnConfigWrite(pDev, off, u32Src, cb);
1365	}
1366	}
1367
1368	/*
1369	* The device dependent registers.
1370	*
1371	* We will not use ConfigWrite here as we have no clue about the size
1372	* of the registers, so the device is responsible for correctly
1373	* restoring functionality governed by these registers.
1374	*/
1375	for (uint32_t off = 0x40; off < sizeof(pDev->config); off++)
1376	if (pbDstConfig[off] != pbSrcConfig[off])
1377	{
1378	LogRel(("PCI: %8s/%u: register %02x: %02x -> %02x\n",
1379	pDev->name, pDev->pDevIns->iInstance, off, pbDstConfig[off], pbSrcConfig[off])); /** @todo make this Log() later. */
1380	pbDstConfig[off] = pbSrcConfig[off];
1381	}
1382	}
1383
1384	/**
1385	* Common worker for ich9pciR3LoadExec and ich9pcibridgeR3LoadExec.
1386	*
1387	* @returns VBox status code.
1388	* @param pBus The bus which data is being loaded.
1389	* @param pSSM The saved state handle.
1390	* @param uVersion The data version.
1391	* @param uPass The pass.
1392	*/
1393	static DECLCALLBACK(int) ich9pciR3CommonLoadExec(PICH9PCIBUS pBus, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1394	{
1395	uint32_t u32;
1396	uint32_t i;
1397	int rc;
1398
1399	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
1400	if (uVersion != VBOX_ICH9PCI_SAVED_STATE_VERSION_CURRENT)
1401	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1402
1403	/*
1404	* Iterate thru all the devices and write 0 to the COMMAND register so
1405	* that all the memory is unmapped before we start restoring the saved
1406	* mapping locations.
1407	*
1408	* The register value is restored afterwards so we can do proper
1409	* LogRels in pciR3CommonRestoreConfig.
1410	*/
1411	for (i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
1412	{
1413	PPCIDEVICE pDev = pBus->apDevices[i];
1414	if (pDev)
1415	{
1416	uint16_t u16 = PCIDevGetCommand(pDev);
1417	pDev->Int.s.pfnConfigWrite(pDev, VBOX_PCI_COMMAND, 0, 2);
1418	PCIDevSetCommand(pDev, u16);
1419	Assert(PCIDevGetCommand(pDev) == u16);
1420	}
1421	}
1422
1423	void *pvMsixPage = RTMemTmpAllocZ(0x1000);
1424	AssertReturn(pvMsixPage, VERR_NO_TMP_MEMORY);
1425
1426	/*
1427	* Iterate all the devices.
1428	*/
1429	for (i = 0;; i++)
1430	{
1431	PPCIDEVICE pDev;
1432	PCIDEVICE DevTmp;
1433
1434	/* index / terminator */
1435	rc = SSMR3GetU32(pSSM, &u32);
1436	if (RT_FAILURE(rc))
1437	break;
1438	if (u32 == (uint32_t)~0)
1439	break;
1440	AssertMsgBreak(u32 < RT_ELEMENTS(pBus->apDevices) && u32 >= i, ("u32=%#x i=%#x\n", u32, i));
1441
1442	/* skip forward to the device checking that no new devices are present. */
1443	for (; i < u32; i++)
1444	{
1445	pDev = pBus->apDevices[i];
1446	if (pDev)
1447	{
1448	LogRel(("PCI: New device in slot %#x, %s (vendor=%#06x device=%#06x)\n", i, pDev->name,
1449	PCIDevGetVendorId(pDev), PCIDevGetDeviceId(pDev)));
1450	if (SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT)
1451	{
1452	rc = SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("New device in slot %#x, %s (vendor=%#06x device=%#06x)"),
1453	i, pDev->name, PCIDevGetVendorId(pDev), PCIDevGetDeviceId(pDev));
1454	break;
1455	}
1456	}
1457	}
1458	if (RT_FAILURE(rc))
1459	break;
1460
1461	/* get the data */
1462	DevTmp.Int.s.fFlags = 0;
1463	DevTmp.Int.s.u8MsiCapOffset = 0;
1464	DevTmp.Int.s.u8MsiCapSize = 0;
1465	DevTmp.Int.s.u8MsixCapOffset = 0;
1466	DevTmp.Int.s.u8MsixCapSize = 0;
1467	DevTmp.Int.s.uIrqPinState = ~0; /* Invalid value in case we have an older saved state to force a state change in pciSetIrq. */
1468	SSMR3GetMem(pSSM, DevTmp.config, sizeof(DevTmp.config));
1469
1470	SSMR3GetU32(pSSM, &DevTmp.Int.s.fFlags);
1471	SSMR3GetS32(pSSM, &DevTmp.Int.s.uIrqPinState);
1472	SSMR3GetU8(pSSM, &DevTmp.Int.s.u8MsiCapOffset);
1473	SSMR3GetU8(pSSM, &DevTmp.Int.s.u8MsiCapSize);
1474	SSMR3GetU8(pSSM, &DevTmp.Int.s.u8MsixCapOffset);
1475	rc = SSMR3GetU8(pSSM, &DevTmp.Int.s.u8MsixCapSize);
1476	if (RT_FAILURE(rc))
1477	break;
1478
1479	/* Load MSI-X page state */
1480	if (DevTmp.Int.s.u8MsixCapOffset != 0)
1481	{
1482	Assert(pvMsixPage != NULL);
1483	rc = SSMR3GetMem(pSSM, pvMsixPage, 0x1000);
1484	if (RT_FAILURE(rc))
1485	break;
1486	}
1487
1488	/* check that it's still around. */
1489	pDev = pBus->apDevices[i];
1490	if (!pDev)
1491	{
1492	LogRel(("PCI: Device in slot %#x has been removed! vendor=%#06x device=%#06x\n", i,
1493	PCIDevGetVendorId(&DevTmp), PCIDevGetDeviceId(&DevTmp)));
1494	if (SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT)
1495	{
1496	rc = SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Device in slot %#x has been removed! vendor=%#06x device=%#06x"),
1497	i, PCIDevGetVendorId(&DevTmp), PCIDevGetDeviceId(&DevTmp));
1498	break;
1499	}
1500	continue;
1501	}
1502
1503	/* match the vendor id assuming that this will never be changed. */
1504	if (PCIDevGetVendorId(&DevTmp) != PCIDevGetVendorId(pDev))
1505	{
1506	rc = SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Device in slot %#x (%s) vendor id mismatch! saved=%.4Rhxs current=%.4Rhxs"),
1507	i, pDev->name, PCIDevGetVendorId(&DevTmp), PCIDevGetVendorId(pDev));
1508	break;
1509	}
1510
1511	/* commit the loaded device config. */
1512	Assert(!pciDevIsPassthrough(pDev));
1513	pciR3CommonRestoreConfig(pDev, &DevTmp.config[0], false ); /** @todo fix bridge fun! */
1514
1515	pDev->Int.s.uIrqPinState = DevTmp.Int.s.uIrqPinState;
1516	pDev->Int.s.u8MsiCapOffset = DevTmp.Int.s.u8MsiCapOffset;
1517	pDev->Int.s.u8MsiCapSize = DevTmp.Int.s.u8MsiCapSize;
1518	pDev->Int.s.u8MsixCapOffset = DevTmp.Int.s.u8MsixCapOffset;
1519	pDev->Int.s.u8MsixCapSize = DevTmp.Int.s.u8MsixCapSize;
1520	if (DevTmp.Int.s.u8MsixCapSize != 0)
1521	{
1522	Assert(pDev->Int.s.pMsixPageR3 != NULL);
1523	memcpy(pDev->Int.s.pMsixPageR3, pvMsixPage, 0x1000);
1524	}
1525	}
1526
1527	RTMemTmpFree(pvMsixPage);
1528
1529	return rc;
1530	}
1531
1532	static DECLCALLBACK(int) ich9pciR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1533	{
1534	PICH9PCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
1535	PICH9PCIBUS pBus = &pThis->aPciBus;
1536	uint32_t u32;
1537	int rc;
1538
1539	/* We ignore this version as there's no saved state with it anyway */
1540	if (uVersion == VBOX_ICH9PCI_SAVED_STATE_VERSION_NOMSI)
1541	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1542	if (uVersion > VBOX_ICH9PCI_SAVED_STATE_VERSION_MSI)
1543	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1544
1545	/*
1546	* Bus state data.
1547	*/
1548	SSMR3GetU32(pSSM, &pThis->uConfigReg);
1549
1550	/*
1551	* Load IRQ states.
1552	*/
1553	for (int i = 0; i < PCI_APIC_IRQ_PINS; i++)
1554	SSMR3GetU32(pSSM, (uint32_t*)&pThis->uaPciApicIrqLevels[i]);
1555
1556	/* separator */
1557	rc = SSMR3GetU32(pSSM, &u32);
1558	if (RT_FAILURE(rc))
1559	return rc;
1560	if (u32 != (uint32_t)~0)
1561	AssertMsgFailedReturn(("u32=%#x\n", u32), rc);
1562
1563	return ich9pciR3CommonLoadExec(pBus, pSSM, uVersion, uPass);
1564	}
1565
1566	static DECLCALLBACK(int) ich9pcibridgeR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1567	{
1568	PICH9PCIBUS pThis = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
1569	if (uVersion > VBOX_ICH9PCI_SAVED_STATE_VERSION_MSI)
1570	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1571	return ich9pciR3CommonLoadExec(pThis, pSSM, uVersion, uPass);
1572	}
1573
1574
1575	/*
1576	* Perform imeediate read of configuration space register.
1577	* Cannot be rescheduled, as already in R3.
1578	*/
1579	static uint32_t ich9pciConfigRead(PICH9PCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t len)
1580	{
1581	PciAddress aPciAddr;
1582	aPciAddr.iBus = uBus;
1583	aPciAddr.iDeviceFunc = uDevFn;
1584	aPciAddr.iRegister = addr;
1585
1586	uint32_t u32Val;
1587	int rc = ich9pciDataReadAddr(pGlobals, &aPciAddr, len, &u32Val, VERR_INTERNAL_ERROR);
1588	AssertRC(rc);
1589
1590	return u32Val;
1591	}
1592
1593
1594	/*
1595	* Perform imeediate write to configuration space register.
1596	* Cannot be rescheduled, as already in R3.
1597	*/
1598	static void ich9pciConfigWrite(PICH9PCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t val, uint32_t len)
1599	{
1600	PciAddress aPciAddr;
1601	aPciAddr.iBus = uBus;
1602	aPciAddr.iDeviceFunc = uDevFn;
1603	aPciAddr.iRegister = addr;
1604
1605	int rc = ich9pciDataWriteAddr(pGlobals, &aPciAddr, val, len, VERR_INTERNAL_ERROR);
1606	AssertRC(rc);
1607	}
1608
1609
1610	static void ich9pciSetRegionAddress(PICH9PCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, int iRegion, uint64_t addr)
1611	{
1612	uint32_t uReg = ich9pciGetRegionReg(iRegion);
1613
1614	/* Read memory type first. */
1615	uint8_t uResourceType = ich9pciConfigRead(pGlobals, uBus, uDevFn, uReg, 1);
1616	/* Read command register. */
1617	uint16_t uCmd = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_COMMAND, 2);
1618
1619	Log(("Set region address: %02x:%02x.%d region %d address=%lld\n",
1620	uBus, uDevFn >> 3, uDevFn & 7, iRegion, addr));
1621
1622	if ( iRegion == PCI_ROM_SLOT )
1623	uCmd \|= PCI_COMMAND_MEMACCESS;
1624	else if ((uResourceType & PCI_ADDRESS_SPACE_IO) == PCI_ADDRESS_SPACE_IO)
1625	uCmd \|= PCI_COMMAND_IOACCESS; /* Enable I/O space access. */
1626	else /* The region is MMIO. */
1627	uCmd \|= PCI_COMMAND_MEMACCESS; /* Enable MMIO access. */
1628
1629	bool f64Bit = (uResourceType & PCI_ADDRESS_SPACE_BAR64) != 0;
1630
1631	/* Write address of the device. */
1632	ich9pciConfigWrite(pGlobals, uBus, uDevFn, uReg, (uint32_t)addr, 4);
1633	if (f64Bit)
1634	ich9pciConfigWrite(pGlobals, uBus, uDevFn, uReg + 4, (uint32_t)(addr >> 32), 4);
1635
1636	/* enable memory mappings */
1637	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_COMMAND, uCmd, 2);
1638	}
1639
1640
1641	static void ich9pciBiosInitBridge(PICH9PCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn)
1642	{
1643	Log(("BIOS init bridge: %02x::%02x.%d\n", uBus, uDevFn >> 3, uDevFn & 7));
1644
1645	/*
1646	* The I/O range for the bridge must be aligned to a 4KB boundary.
1647	* This does not change anything really as the access to the device is not going
1648	* through the bridge but we want to be compliant to the spec.
1649	*/
1650	if ((pGlobals->uPciBiosIo % 4096) != 0)
1651	{
1652	pGlobals->uPciBiosIo = RT_ALIGN_32(pGlobals->uPciBiosIo, 4*1024);
1653	Log(("%s: Aligned I/O start address. New address %#x\n", __FUNCTION__, pGlobals->uPciBiosIo));
1654	}
1655	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_IO_BASE, (pGlobals->uPciBiosIo >> 8) & 0xf0, 1);
1656
1657	/* The MMIO range for the bridge must be aligned to a 1MB boundary. */
1658	if ((pGlobals->uPciBiosMmio % (1024 * 1024)) != 0)
1659	{
1660	pGlobals->uPciBiosMmio = RT_ALIGN_32(pGlobals->uPciBiosMmio, 1024*1024);
1661	Log(("%s: Aligned MMIO start address. New address %#x\n", __FUNCTION__, pGlobals->uPciBiosMmio));
1662	}
1663	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_MEMORY_BASE, (pGlobals->uPciBiosMmio >> 16) & UINT32_C(0xffff0), 2);
1664
1665	/* Save values to compare later to. */
1666	uint32_t u32IoAddressBase = pGlobals->uPciBiosIo;
1667	uint32_t u32MMIOAddressBase = pGlobals->uPciBiosMmio;
1668	uint8_t uBridgeBus = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_SECONDARY_BUS, 1);
1669
1670	/* Init devices behind the bridge and possibly other bridges as well. */
1671	for (int iDev = 0; iDev <= 255; iDev++)
1672	ich9pciBiosInitDevice(pGlobals, uBridgeBus, iDev);
1673
1674	/*
1675	* Set I/O limit register. If there is no device with I/O space behind the bridge
1676	* we set a lower value than in the base register.
1677	* The result with a real bridge is that no I/O transactions are passed to the secondary
1678	* interface. Again this doesn't really matter here but we want to be compliant to the spec.
1679	*/
1680	if ((u32IoAddressBase != pGlobals->uPciBiosIo) && ((pGlobals->uPciBiosIo % 4096) != 0))
1681	{
1682	/* The upper boundary must be one byte less than a 4KB boundary. */
1683	pGlobals->uPciBiosIo = RT_ALIGN_32(pGlobals->uPciBiosIo, 4*1024);
1684	}
1685
1686	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_IO_LIMIT, ((pGlobals->uPciBiosIo >> 8) & 0xf0) - 1, 1);
1687
1688	/* Same with the MMIO limit register but with 1MB boundary here. */
1689	if ((u32MMIOAddressBase != pGlobals->uPciBiosMmio) && ((pGlobals->uPciBiosMmio % (1024 * 1024)) != 0))
1690	{
1691	/* The upper boundary must be one byte less than a 1MB boundary. */
1692	pGlobals->uPciBiosMmio = RT_ALIGN_32(pGlobals->uPciBiosMmio, 1024*1024);
1693	}
1694	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_MEMORY_LIMIT, ((pGlobals->uPciBiosMmio >> 16) & UINT32_C(0xfff0)) - 1, 2);
1695
1696	/*
1697	* Set the prefetch base and limit registers. We currently have no device with a prefetchable region
1698	* which may be behind a bridge. That's why it is unconditionally disabled here atm by writing a higher value into
1699	* the base register than in the limit register.
1700	*/
1701	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_MEMORY_BASE, 0xfff0, 2);
1702	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_MEMORY_LIMIT, 0x0, 2);
1703	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_BASE_UPPER32, 0x00, 4);
1704	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_LIMIT_UPPER32, 0x00, 4);
1705	}
1706
1707	static void ich9pciBiosInitDevice(PICH9PCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn)
1708	{
1709	uint16_t uDevClass, uVendor, uDevice;
1710	uint8_t uCmd;
1711
1712	uDevClass = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_CLASS_DEVICE, 2);
1713	uVendor = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_VENDOR_ID, 2);
1714	uDevice = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_DEVICE_ID, 2);
1715
1716	/* If device is present */
1717	if (uVendor == 0xffff)
1718	return;
1719
1720	Log(("BIOS init device: %02x:%02x.%d\n", uBus, uDevFn >> 3, uDevFn & 7));
1721
1722	switch (uDevClass)
1723	{
1724	case 0x0101:
1725	/* IDE controller */
1726	ich9pciConfigWrite(pGlobals, uBus, uDevFn, 0x40, 0x8000, 2); /* enable IDE0 */
1727	ich9pciConfigWrite(pGlobals, uBus, uDevFn, 0x42, 0x8000, 2); /* enable IDE1 */
1728	goto default_map;
1729	break;
1730	case 0x0300:
1731	/* VGA controller */
1732	if (uVendor != 0x80ee)
1733	goto default_map;
1734	/* VGA: map frame buffer to default Bochs VBE address */
1735	ich9pciSetRegionAddress(pGlobals, uBus, uDevFn, 0, 0xE0000000);
1736	/*
1737	* Legacy VGA I/O ports are implicitly decoded by a VGA class device. But
1738	* only the framebuffer (i.e., a memory region) is explicitly registered via
1739	* ich9pciSetRegionAddress, so I/O decoding must be enabled manually.
1740	*/
1741	uCmd = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_COMMAND, 1);
1742	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_COMMAND,
1743	/* Enable I/O space access. */
1744	uCmd \| PCI_COMMAND_IOACCESS,
1745	1);
1746	break;
1747	case 0x0604:
1748	/* PCI-to-PCI bridge. */
1749	AssertMsg(pGlobals->uBus < 255, ("Too many bridges on the bus\n"));
1750	ich9pciBiosInitBridge(pGlobals, uBus, uDevFn);
1751	break;
1752	default:
1753	default_map:
1754	{
1755	/* default memory mappings */
1756	/*
1757	* We ignore ROM region here.
1758	*/
1759	for (int iRegion = 0; iRegion < (PCI_NUM_REGIONS-1); iRegion++)
1760	{
1761	uint32_t u32Address = ich9pciGetRegionReg(iRegion);
1762
1763	/* Calculate size - we write all 1s into the BAR, and then evaluate which bits
1764	are cleared. . */
1765	uint8_t u8ResourceType = ich9pciConfigRead(pGlobals, uBus, uDevFn, u32Address, 1);
1766
1767	bool f64bit = (u8ResourceType & PCI_ADDRESS_SPACE_BAR64) != 0;
1768	bool fIsPio = ((u8ResourceType & PCI_COMMAND_IOACCESS) == PCI_COMMAND_IOACCESS);
1769	uint64_t cbRegSize64 = 0;
1770
1771	if (f64bit)
1772	{
1773	ich9pciConfigWrite(pGlobals, uBus, uDevFn, u32Address, UINT32_C(0xffffffff), 4);
1774	ich9pciConfigWrite(pGlobals, uBus, uDevFn, u32Address+4, UINT32_C(0xffffffff), 4);
1775	cbRegSize64 = ich9pciConfigRead(pGlobals, uBus, uDevFn, u32Address, 4);
1776	cbRegSize64 \|= ((uint64_t)ich9pciConfigRead(pGlobals, uBus, uDevFn, u32Address+4, 4) << 32);
1777	cbRegSize64 &= ~UINT64_C(0x0f);
1778	cbRegSize64 = (~cbRegSize64) + 1;
1779
1780	/* No 64-bit PIO regions possible. */
1781	#ifndef DEBUG_bird /* EFI triggers this for DevAHCI. */
1782	AssertMsg((u8ResourceType & PCI_COMMAND_IOACCESS) == 0, ("type=%#x rgn=%d\n", u8ResourceType, iRegion));
1783	#endif
1784	}
1785	else
1786	{
1787	uint32_t cbRegSize32;
1788	ich9pciConfigWrite(pGlobals, uBus, uDevFn, u32Address, UINT32_C(0xffffffff), 4);
1789	cbRegSize32 = ich9pciConfigRead(pGlobals, uBus, uDevFn, u32Address, 4);
1790
1791	/* Clear resource information depending on resource type. */
1792	if (fIsPio) /* PIO */
1793	cbRegSize32 &= ~UINT32_C(0x01);
1794	else /* MMIO */
1795	cbRegSize32 &= ~UINT32_C(0x0f);
1796
1797	/*
1798	* Invert all bits and add 1 to get size of the region.
1799	* (From PCI implementation note)
1800	*/
1801	if (fIsPio && (cbRegSize32 & UINT32_C(0xffff0000)) == 0)
1802	cbRegSize32 = (~(cbRegSize32 \| UINT32_C(0xffff0000))) + 1;
1803	else
1804	cbRegSize32 = (~cbRegSize32) + 1;
1805
1806	cbRegSize64 = cbRegSize32;
1807	}
1808	#ifndef DEBUG_bird /* EFI triggers this for DevAHCI. */
1809	Assert(cbRegSize64 == (uint32_t)cbRegSize64);
1810	#endif
1811	Log2(("%s: Size of region %u for device %d on bus %d is %lld\n", __FUNCTION__, iRegion, uDevFn, uBus, cbRegSize64));
1812
1813	if (cbRegSize64)
1814	{
1815	uint32_t cbRegSize32 = (uint32_t)cbRegSize64;
1816	uint32_t* paddr = fIsPio ? &pGlobals->uPciBiosIo : &pGlobals->uPciBiosMmio;
1817	paddr = (paddr + cbRegSize32 - 1) & ~(cbRegSize32 - 1);
1818	Log(("%s: Start address of %s region %u is %#x\n", __FUNCTION__, (fIsPio ? "I/O" : "MMIO"), iRegion, *paddr));
1819	ich9pciSetRegionAddress(pGlobals, uBus, uDevFn, iRegion, *paddr);
1820	*paddr += cbRegSize32;
1821	Log2(("%s: New address is %#x\n", __FUNCTION__, *paddr));
1822
1823	if (f64bit)
1824	iRegion++; /* skip next region */
1825	}
1826	}
1827	break;
1828	}
1829	}
1830
1831	/* map the interrupt */
1832	uint32_t iPin = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_INTERRUPT_PIN, 1);
1833	if (iPin != 0)
1834	{
1835	iPin--;
1836
1837	if (uBus != 0)
1838	{
1839	/* Find bus this device attached to. */
1840	PICH9PCIBUS pBus = &pGlobals->aPciBus;
1841	while (1)
1842	{
1843	PPCIDEVICE pBridge = ich9pciFindBridge(pBus, uBus);
1844	if (!pBridge)
1845	{
1846	Assert(false);
1847	break;
1848	}
1849	if (uBus == PCIDevGetByte(pBridge, VBOX_PCI_SECONDARY_BUS))
1850	{
1851	/* OK, found bus this device attached to. */
1852	break;
1853	}
1854	pBus = PDMINS_2_DATA(pBridge->pDevIns, PICH9PCIBUS);
1855	}
1856
1857	/* We need to go up to the host bus to see which irq pin this
1858	* device will use there. See logic in ich9pcibridgeSetIrq().
1859	*/
1860	while (pBus->iBus != 0)
1861	{
1862	/* Get the pin the device would assert on the bridge. */
1863	iPin = ((pBus->aPciDev.devfn >> 3) + iPin) & 3;
1864	pBus = pBus->aPciDev.Int.s.pBusR3;
1865	};
1866	}
1867
1868	int iIrq = aPciIrqs[ich9pciSlotGetPirq(uBus, uDevFn, iPin)];
1869	Log(("Using pin %d and IRQ %d for device %02x:%02x.%d\n",
1870	iPin, iIrq, uBus, uDevFn>>3, uDevFn&7));
1871	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_INTERRUPT_LINE, iIrq, 1);
1872	}
1873	}
1874
1875	/**
1876	* Initializes bridges registers used for routing.
1877	*
1878	* @returns nothing.
1879	* @param pGlobals Global device instance data used to generate unique bus numbers.
1880	* @param pBus The PCI bus to initialize.
1881	* @param uBusPrimary The primary bus number the bus is connected to.
1882	* @param uBusSecondary The secondary bus number, i.e. the bus number behind the bridge.
1883	*/
1884	static void ich9pciInitBridgeTopology(PICH9PCIGLOBALS pGlobals, PICH9PCIBUS pBus, unsigned uBusPrimary,
1885	unsigned uBusSecondary)
1886	{
1887	PPCIDEVICE pBridgeDev = &pBus->aPciDev;
1888
1889	/* Set only if we are not on the root bus, it has no primary bus attached. */
1890	if (uBusSecondary != 0)
1891	{
1892	PCIDevSetByte(pBridgeDev, VBOX_PCI_PRIMARY_BUS, uBusPrimary);
1893	PCIDevSetByte(pBridgeDev, VBOX_PCI_SECONDARY_BUS, uBusSecondary);
1894	}
1895
1896	for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
1897	{
1898	PPCIDEVICE pBridge = pBus->papBridgesR3[iBridge];
1899	AssertMsg(pBridge && pciDevIsPci2PciBridge(pBridge),
1900	("Device is not a PCI bridge but on the list of PCI bridges\n"));
1901	PICH9PCIBUS pChildBus = PDMINS_2_DATA(pBridge->pDevIns, PICH9PCIBUS);
1902	pGlobals->uBus++;
1903	ich9pciInitBridgeTopology(pGlobals, pChildBus, uBusSecondary, pGlobals->uBus);
1904	}
1905	PCIDevSetByte(pBridgeDev, VBOX_PCI_SUBORDINATE_BUS, pGlobals->uBus);
1906	Log2(("ich9pciInitBridgeTopology: for bus %p: primary=%d secondary=%d subordinate=%d\n",
1907	pBus,
1908	PCIDevGetByte(pBridgeDev, VBOX_PCI_PRIMARY_BUS),
1909	PCIDevGetByte(pBridgeDev, VBOX_PCI_SECONDARY_BUS),
1910	PCIDevGetByte(pBridgeDev, VBOX_PCI_SUBORDINATE_BUS)
1911	));
1912	}
1913
1914
1915	static DECLCALLBACK(int) ich9pciFakePCIBIOS(PPDMDEVINS pDevIns)
1916	{
1917	PICH9PCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
1918	PVM pVM = PDMDevHlpGetVM(pDevIns);
1919	Assert(pVM);
1920
1921	/*
1922	* Set the start addresses.
1923	*/
1924	pGlobals->uPciBiosIo = 0xd000;
1925	pGlobals->uPciBiosMmio = UINT32_C(0xf0000000);
1926	pGlobals->uBus = 0;
1927
1928	/*
1929	* Assign bridge topology, for further routing to work.
1930	*/
1931	PICH9PCIBUS pBus = &pGlobals->aPciBus;
1932	ich9pciInitBridgeTopology(pGlobals, pBus, 0, 0);
1933
1934	/*
1935	* Init the devices.
1936	*/
1937	for (int i = 0; i < 256; i++)
1938	{
1939	ich9pciBiosInitDevice(pGlobals, 0, i);
1940	}
1941
1942	return VINF_SUCCESS;
1943	}
1944
1945
1946	/*
1947	* Configuration space read callback (PCIDEVICEINT::pfnConfigRead) for
1948	* connected devices.
1949	*/
1950	static DECLCALLBACK(uint32_t) ich9pciConfigReadDev(PCIDevice *aDev, uint32_t u32Address, unsigned len)
1951	{
1952	if ((u32Address + len) > 256 && (u32Address + len) < 4096)
1953	{
1954	LogRel(("PCI: %8s/%u: Read from extended register %d fallen back to generic code\n",
1955	aDev->name, aDev->pDevIns->iInstance, u32Address));
1956	return 0;
1957	}
1958
1959	AssertMsgReturn(u32Address + len <= 256, ("Read after the end of PCI config space\n"),
1960	0);
1961	if ( pciDevIsMsiCapable(aDev)
1962	&& (u32Address >= aDev->Int.s.u8MsiCapOffset)
1963	&& (u32Address < (unsigned)(aDev->Int.s.u8MsiCapOffset + aDev->Int.s.u8MsiCapSize))
1964	)
1965	{
1966	return MsiPciConfigRead(aDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pDevIns), aDev, u32Address, len);
1967	}
1968
1969	if ( pciDevIsMsixCapable(aDev)
1970	&& (u32Address >= aDev->Int.s.u8MsixCapOffset)
1971	&& (u32Address < (unsigned)(aDev->Int.s.u8MsixCapOffset + aDev->Int.s.u8MsixCapSize))
1972	)
1973	{
1974	return MsixPciConfigRead(aDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pDevIns), aDev, u32Address, len);
1975	}
1976
1977	AssertMsgReturn(u32Address + len <= 256, ("Read after end of PCI config space\n"),
1978	0);
1979	switch (len)
1980	{
1981	case 1:
1982	return PCIDevGetByte(aDev, u32Address);
1983	case 2:
1984	return PCIDevGetWord(aDev, u32Address);
1985	case 4:
1986	return PCIDevGetDWord(aDev, u32Address);
1987	default:
1988	Assert(false);
1989	return 0;
1990	}
1991	}
1992
1993
1994	DECLINLINE(void) ich9pciWriteBarByte(PCIDevice *aDev, int iRegion, int iOffset, uint8_t u8Val)
1995	{
1996	PCIIORegion * pRegion = &aDev->Int.s.aIORegions[iRegion];
1997	int64_t iRegionSize = pRegion->size;
1998
1999	Log3(("ich9pciWriteBarByte: region=%d off=%d val=%x size=%d\n",
2000	iRegion, iOffset, u8Val, iRegionSize));
2001
2002	if (iOffset > 3)
2003	Assert((pRegion->type & PCI_ADDRESS_SPACE_BAR64) != 0);
2004
2005	/* Check if we're writing to upper part of 64-bit BAR. */
2006	if (pRegion->type == 0xff)
2007	{
2008	ich9pciWriteBarByte(aDev, iRegion-1, iOffset+4, u8Val);
2009	return;
2010	}
2011
2012	/* Region doesn't exist */
2013	if (iRegionSize == 0)
2014	return;
2015
2016	uint32_t uAddr = ich9pciGetRegionReg(iRegion) + iOffset;
2017	/* Region size must be power of two */
2018	Assert((iRegionSize & (iRegionSize - 1)) == 0);
2019	uint8_t uMask = ((iRegionSize - 1) >> (iOffset*8) ) & 0xff;
2020
2021	if (iOffset == 0)
2022	{
2023	uMask \|= (pRegion->type & PCI_ADDRESS_SPACE_IO) ?
2024	(1 << 2) - 1 /* 2 lowest bits for IO region */ :
2025	(1 << 4) - 1 /* 4 lowest bits for memory region, also ROM enable bit for ROM region */;
2026
2027	}
2028
2029	uint8_t u8Old = PCIDevGetByte(aDev, uAddr) & uMask;
2030	u8Val = (u8Old & uMask) \| (u8Val & ~uMask);
2031
2032	Log3(("ich9pciWriteBarByte: was %x writing %x\n", u8Old, u8Val));
2033
2034	PCIDevSetByte(aDev, uAddr, u8Val);
2035	}
2036
2037
2038	/**
2039	* Configuration space write callback (PCIDEVICEINT::pfnConfigWrite)
2040	* for connected devices.
2041	*
2042	* See paragraph 7.5 of PCI Express specification (p. 349) for
2043	* definition of registers and their writability policy.
2044	*/
2045	static DECLCALLBACK(void) ich9pciConfigWriteDev(PCIDevice *aDev, uint32_t u32Address,
2046	uint32_t val, unsigned len)
2047	{
2048	Assert(len <= 4);
2049
2050	if ((u32Address + len) > 256 && (u32Address + len) < 4096)
2051	{
2052	LogRel(("PCI: %8s/%u: Write to extended register %d fallen back to generic code\n",
2053	aDev->name, aDev->pDevIns->iInstance, u32Address));
2054	return;
2055	}
2056
2057	AssertMsgReturnVoid(u32Address + len <= 256, ("Write after end of PCI config space\n"));
2058
2059	if ( pciDevIsMsiCapable(aDev)
2060	&& (u32Address >= aDev->Int.s.u8MsiCapOffset)
2061	&& (u32Address < (unsigned)(aDev->Int.s.u8MsiCapOffset + aDev->Int.s.u8MsiCapSize))
2062	)
2063	{
2064	MsiPciConfigWrite(aDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pDevIns),
2065	aDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pPciHlp),
2066	aDev, u32Address, val, len);
2067	return;
2068	}
2069
2070	if ( pciDevIsMsixCapable(aDev)
2071	&& (u32Address >= aDev->Int.s.u8MsixCapOffset)
2072	&& (u32Address < (unsigned)(aDev->Int.s.u8MsixCapOffset + aDev->Int.s.u8MsixCapSize))
2073	)
2074	{
2075	MsixPciConfigWrite(aDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pDevIns),
2076	aDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pPciHlp),
2077	aDev, u32Address, val, len);
2078	return;
2079	}
2080
2081	uint32_t addr = u32Address;
2082	bool fUpdateMappings = false;
2083	bool fP2PBridge = false;
2084	/bool fPassthrough = pciDevIsPassthrough(aDev);/
2085	uint8_t u8HeaderType = ich9pciGetByte(aDev, VBOX_PCI_HEADER_TYPE);
2086
2087	for (uint32_t i = 0; i < len; i++)
2088	{
2089	bool fWritable = false;
2090	bool fRom = false;
2091	switch (u8HeaderType)
2092	{
2093	case 0x00: /* normal device */
2094	case 0x80: /* multi-function device */
2095	switch (addr)
2096	{
2097	/* Read-only registers */
2098	case VBOX_PCI_VENDOR_ID: case VBOX_PCI_VENDOR_ID+1:
2099	case VBOX_PCI_DEVICE_ID: case VBOX_PCI_DEVICE_ID+1:
2100	case VBOX_PCI_REVISION_ID:
2101	case VBOX_PCI_CLASS_PROG:
2102	case VBOX_PCI_CLASS_SUB:
2103	case VBOX_PCI_CLASS_BASE:
2104	case VBOX_PCI_HEADER_TYPE:
2105	case VBOX_PCI_SUBSYSTEM_VENDOR_ID: case VBOX_PCI_SUBSYSTEM_VENDOR_ID+1:
2106	case VBOX_PCI_SUBSYSTEM_ID: case VBOX_PCI_SUBSYSTEM_ID+1:
2107	case VBOX_PCI_ROM_ADDRESS: case VBOX_PCI_ROM_ADDRESS+1: case VBOX_PCI_ROM_ADDRESS+2: case VBOX_PCI_ROM_ADDRESS+3:
2108	case VBOX_PCI_CAPABILITY_LIST:
2109	case VBOX_PCI_INTERRUPT_PIN:
2110	fWritable = false;
2111	break;
2112	/* Others can be written */
2113	default:
2114	fWritable = true;
2115	break;
2116	}
2117	break;
2118	case 0x01: /* PCI-PCI bridge */
2119	fP2PBridge = true;
2120	switch (addr)
2121	{
2122	/* Read-only registers */
2123	case VBOX_PCI_VENDOR_ID: case VBOX_PCI_VENDOR_ID+1:
2124	case VBOX_PCI_DEVICE_ID: case VBOX_PCI_DEVICE_ID+1:
2125	case VBOX_PCI_REVISION_ID:
2126	case VBOX_PCI_CLASS_PROG:
2127	case VBOX_PCI_CLASS_SUB:
2128	case VBOX_PCI_CLASS_BASE:
2129	case VBOX_PCI_HEADER_TYPE:
2130	case VBOX_PCI_ROM_ADDRESS_BR: case VBOX_PCI_ROM_ADDRESS_BR+1: case VBOX_PCI_ROM_ADDRESS_BR+2: case VBOX_PCI_ROM_ADDRESS_BR+3:
2131	case VBOX_PCI_INTERRUPT_PIN:
2132	fWritable = false;
2133	break;
2134	default:
2135	fWritable = true;
2136	break;
2137	}
2138	break;
2139	default:
2140	AssertMsgFailed(("Unknown header type %x\n", PCIDevGetHeaderType(aDev)));
2141	fWritable = false;
2142	break;
2143	}
2144
2145	uint8_t u8Val = (uint8_t)val;
2146	switch (addr)
2147	{
2148	case VBOX_PCI_COMMAND: /* Command register, bits 0-7. */
2149	fUpdateMappings = true;
2150	goto default_case;
2151	case VBOX_PCI_COMMAND+1: /* Command register, bits 8-15. */
2152	/* don't change reserved bits (11-15) */
2153	u8Val &= UINT32_C(~0xf8);
2154	fUpdateMappings = true;
2155	goto default_case;
2156	case VBOX_PCI_STATUS: /* Status register, bits 0-7. */
2157	/* don't change read-only bits => actually all lower bits are read-only */
2158	u8Val &= UINT32_C(~0xff);
2159	/* status register, low part: clear bits by writing a '1' to the corresponding bit */
2160	aDev->config[addr] &= ~u8Val;
2161	break;
2162	case VBOX_PCI_STATUS+1: /* Status register, bits 8-15. */
2163	/* don't change read-only bits */
2164	u8Val &= UINT32_C(~0x06);
2165	/* status register, high part: clear bits by writing a '1' to the corresponding bit */
2166	aDev->config[addr] &= ~u8Val;
2167	break;
2168	case VBOX_PCI_ROM_ADDRESS: case VBOX_PCI_ROM_ADDRESS +1: case VBOX_PCI_ROM_ADDRESS +2: case VBOX_PCI_ROM_ADDRESS +3:
2169	fRom = true;
2170	case VBOX_PCI_BASE_ADDRESS_0: case VBOX_PCI_BASE_ADDRESS_0+1: case VBOX_PCI_BASE_ADDRESS_0+2: case VBOX_PCI_BASE_ADDRESS_0+3:
2171	case VBOX_PCI_BASE_ADDRESS_1: case VBOX_PCI_BASE_ADDRESS_1+1: case VBOX_PCI_BASE_ADDRESS_1+2: case VBOX_PCI_BASE_ADDRESS_1+3:
2172	case VBOX_PCI_BASE_ADDRESS_2: case VBOX_PCI_BASE_ADDRESS_2+1: case VBOX_PCI_BASE_ADDRESS_2+2: case VBOX_PCI_BASE_ADDRESS_2+3:
2173	case VBOX_PCI_BASE_ADDRESS_3: case VBOX_PCI_BASE_ADDRESS_3+1: case VBOX_PCI_BASE_ADDRESS_3+2: case VBOX_PCI_BASE_ADDRESS_3+3:
2174	case VBOX_PCI_BASE_ADDRESS_4: case VBOX_PCI_BASE_ADDRESS_4+1: case VBOX_PCI_BASE_ADDRESS_4+2: case VBOX_PCI_BASE_ADDRESS_4+3:
2175	case VBOX_PCI_BASE_ADDRESS_5: case VBOX_PCI_BASE_ADDRESS_5+1: case VBOX_PCI_BASE_ADDRESS_5+2: case VBOX_PCI_BASE_ADDRESS_5+3:
2176	{
2177	/* We check that, as same PCI register numbers as BARs may mean different registers for bridges */
2178	if (fP2PBridge)
2179	goto default_case;
2180	else
2181	{
2182	int iRegion = fRom ? VBOX_PCI_ROM_SLOT : (addr - VBOX_PCI_BASE_ADDRESS_0) >> 2;
2183	int iOffset = addr & 0x3;
2184	ich9pciWriteBarByte(aDev, iRegion, iOffset, u8Val);
2185	fUpdateMappings = true;
2186	}
2187	break;
2188	}
2189	default:
2190	default_case:
2191	if (fWritable)
2192	PCIDevSetByte(aDev, addr, u8Val);
2193	}
2194	addr++;
2195	val >>= 8;
2196	}
2197
2198	if (fUpdateMappings)
2199	/* if the command/base address register is modified, we must modify the mappings */
2200	ich9pciUpdateMappings(aDev);
2201	}
2202
2203	static bool assignPosition(PICH9PCIBUS pBus, PPCIDEVICE pPciDev, const char pszName, int iDevFn, PciAddress aPosition)
2204	{
2205	NOREF(pszName);
2206	aPosition->iBus = 0;
2207	aPosition->iDeviceFunc = iDevFn;
2208	aPosition->iRegister = 0; /* N/A */
2209
2210	/* Explicit slot request */
2211	if (iDevFn >= 0 && iDevFn < (int)RT_ELEMENTS(pBus->apDevices))
2212	return true;
2213
2214	int iStartPos = 0;
2215
2216	/* Otherwise when assigning a slot, we need to make sure all its functions are available */
2217	for (int iPos = iStartPos; iPos < (int)RT_ELEMENTS(pBus->apDevices); iPos += 8)
2218	{
2219	if ( !pBus->apDevices[iPos]
2220	&& !pBus->apDevices[iPos + 1]
2221	&& !pBus->apDevices[iPos + 2]
2222	&& !pBus->apDevices[iPos + 3]
2223	&& !pBus->apDevices[iPos + 4]
2224	&& !pBus->apDevices[iPos + 5]
2225	&& !pBus->apDevices[iPos + 6]
2226	&& !pBus->apDevices[iPos + 7])
2227	{
2228	pciDevClearRequestedDevfunc(pPciDev);
2229	aPosition->iDeviceFunc = iPos;
2230	return true;
2231	}
2232	}
2233
2234	return false;
2235	}
2236
2237	#ifdef SOME_UNUSED_FUNCTION
2238	static bool hasHardAssignedDevsInSlot(PICH9PCIBUS pBus, int iSlot)
2239	{
2240	PCIDevice** aSlot = &pBus->apDevices[iSlot << 3];
2241
2242	return (aSlot[0] && pciDevIsRequestedDevfunc(aSlot[0]))
2243	\|\| (aSlot[1] && pciDevIsRequestedDevfunc(aSlot[1]))
2244	\|\| (aSlot[2] && pciDevIsRequestedDevfunc(aSlot[2]))
2245	\|\| (aSlot[3] && pciDevIsRequestedDevfunc(aSlot[3]))
2246	\|\| (aSlot[4] && pciDevIsRequestedDevfunc(aSlot[4]))
2247	\|\| (aSlot[5] && pciDevIsRequestedDevfunc(aSlot[5]))
2248	\|\| (aSlot[6] && pciDevIsRequestedDevfunc(aSlot[6]))
2249	\|\| (aSlot[7] && pciDevIsRequestedDevfunc(aSlot[7]))
2250	;
2251	}
2252	#endif
2253
2254	static int ich9pciRegisterInternal(PICH9PCIBUS pBus, int iDev, PPCIDEVICE pPciDev, const char *pszName)
2255	{
2256	PciAddress aPosition;
2257	aPosition.iBus = 0;
2258	aPosition.iDeviceFunc = 0;
2259	aPosition.iRegister = 0;
2260
2261	/*
2262	* Find device position
2263	*/
2264	if (!assignPosition(pBus, pPciDev, pszName, iDev, &aPosition))
2265	{
2266	AssertMsgFailed(("Couldn't asssign position!\n"));
2267	return VERR_PDM_TOO_PCI_MANY_DEVICES;
2268	}
2269
2270	AssertMsgReturn(aPosition.iBus == 0,
2271	("Assigning behind the bridge not implemented yet\n"),
2272	VERR_PDM_TOO_PCI_MANY_DEVICES);
2273
2274
2275	iDev = aPosition.iDeviceFunc;
2276	/*
2277	* Check if we can really take this slot, possibly by relocating
2278	* its current habitant, if it wasn't hard assigned too.
2279	*/
2280	if (pciDevIsRequestedDevfunc(pPciDev) &&
2281	pBus->apDevices[iDev] &&
2282	pciDevIsRequestedDevfunc(pBus->apDevices[iDev]))
2283	{
2284	AssertReleaseMsgFailed(("Configuration error:'%s' and '%s' are both configured as device %d\n",
2285	pszName, pBus->apDevices[iDev]->name, iDev));
2286	return VERR_INTERNAL_ERROR;
2287	}
2288
2289	if (pBus->apDevices[iDev])
2290	{
2291	/* if we got here, we shall (and usually can) relocate the device */
2292	bool assigned = assignPosition(pBus, pBus->apDevices[iDev], pBus->apDevices[iDev]->name, -1, &aPosition);
2293	AssertMsgReturn(aPosition.iBus == 0,
2294	("Assigning behind the bridge not implemented yet\n"),
2295	VERR_PDM_TOO_PCI_MANY_DEVICES);
2296	int iRelDev = aPosition.iDeviceFunc;
2297	if (!assigned \|\| iRelDev == iDev)
2298	{
2299	AssertMsgFailed(("Couldn't find free spot!\n"));
2300	return VERR_PDM_TOO_PCI_MANY_DEVICES;
2301	}
2302	/* Copy device function by function to its new position */
2303	for (int i = 0; i < 8; i++)
2304	{
2305	if (!pBus->apDevices[iDev + i])
2306	continue;
2307	Log(("PCI: relocating '%s' from slot %#x to %#x\n", pBus->apDevices[iDev + i]->name, iDev + i, iRelDev + i));
2308	pBus->apDevices[iRelDev + i] = pBus->apDevices[iDev + i];
2309	pBus->apDevices[iRelDev + i]->devfn = iRelDev + i;
2310	pBus->apDevices[iDev + i] = NULL;
2311	}
2312	}
2313
2314	/*
2315	* Fill in device information.
2316	*/
2317	pPciDev->devfn = iDev;
2318	pPciDev->name = pszName;
2319	pPciDev->Int.s.pBusR3 = pBus;
2320	pPciDev->Int.s.pBusR0 = MMHyperR3ToR0(PDMDevHlpGetVM(pBus->CTX_SUFF(pDevIns)), pBus);
2321	pPciDev->Int.s.pBusRC = MMHyperR3ToRC(PDMDevHlpGetVM(pBus->CTX_SUFF(pDevIns)), pBus);
2322	pPciDev->Int.s.pfnConfigRead = ich9pciConfigReadDev;
2323	pPciDev->Int.s.pfnConfigWrite = ich9pciConfigWriteDev;
2324	pBus->apDevices[iDev] = pPciDev;
2325	if (pciDevIsPci2PciBridge(pPciDev))
2326	{
2327	AssertMsg(pBus->cBridges < RT_ELEMENTS(pBus->apDevices), ("Number of bridges exceeds the number of possible devices on the bus\n"));
2328	AssertMsg(pPciDev->Int.s.pfnBridgeConfigRead && pPciDev->Int.s.pfnBridgeConfigWrite,
2329	("device is a bridge but does not implement read/write functions\n"));
2330	Log2(("Setting bridge %d on bus %p\n", pBus->cBridges, pBus));
2331	pBus->papBridgesR3[pBus->cBridges] = pPciDev;
2332	pBus->cBridges++;
2333	}
2334
2335	Log(("PCI: Registered device %d function %d on bus %d (%#x) '%s'.\n",
2336	iDev >> 3, iDev & 7, pBus->iBus, 0x80000000 \| (iDev << 8), pszName));
2337
2338	return VINF_SUCCESS;
2339	}
2340
2341	static void printIndent(PCDBGFINFOHLP pHlp, int iIndent)
2342	{
2343	for (int i = 0; i < iIndent; i++)
2344	{
2345	pHlp->pfnPrintf(pHlp, " ");
2346	}
2347	}
2348
2349	static void ich9pciBusInfo(PICH9PCIBUS pBus, PCDBGFINFOHLP pHlp, int iIndent, bool fRegisters)
2350	{
2351	for (uint32_t iDev = 0; iDev < RT_ELEMENTS(pBus->apDevices); iDev++)
2352	{
2353	PPCIDEVICE pPciDev = pBus->apDevices[iDev];
2354	if (pPciDev != NULL)
2355	{
2356	printIndent(pHlp, iIndent);
2357
2358	/*
2359	* For passthrough devices MSI/MSI-X mostly reflects the way interrupts delivered to the guest,
2360	* as host driver handles real devices interrupts.
2361	*/
2362	pHlp->pfnPrintf(pHlp, "%02x:%02x:%02x %s%s: %04x-%04x",
2363	pBus->iBus, (iDev >> 3) & 0xff, iDev & 0x7,
2364	pPciDev->name,
2365	pciDevIsPassthrough(pPciDev) ? " (PASSTHROUGH)" : "",
2366	ich9pciGetWord(pPciDev, VBOX_PCI_VENDOR_ID), ich9pciGetWord(pPciDev, VBOX_PCI_DEVICE_ID)
2367	);
2368	if (ich9pciGetByte(pPciDev, VBOX_PCI_INTERRUPT_PIN) != 0)
2369	pHlp->pfnPrintf(pHlp, " IRQ%d", ich9pciGetByte(pPciDev, VBOX_PCI_INTERRUPT_LINE));
2370	pHlp->pfnPrintf(pHlp, "\n");
2371
2372	if (pciDevIsMsiCapable(pPciDev) \|\| pciDevIsMsixCapable(pPciDev))
2373	{
2374	printIndent(pHlp, iIndent + 2);
2375
2376	if (pciDevIsMsiCapable(pPciDev))
2377	pHlp->pfnPrintf(pHlp, "MSI:%s ", MsiIsEnabled(pPciDev) ? "on" : "off");
2378
2379	if (pciDevIsMsixCapable(pPciDev))
2380	pHlp->pfnPrintf(pHlp, "MSI-X:%s ", MsixIsEnabled(pPciDev) ? "on" : "off");
2381
2382	pHlp->pfnPrintf(pHlp, "\n");
2383	}
2384
2385	uint16_t iCmd = ich9pciGetWord(pPciDev, VBOX_PCI_COMMAND);
2386	if ((iCmd & (VBOX_PCI_COMMAND_IO \| VBOX_PCI_COMMAND_MEMORY)) != 0)
2387	{
2388	for (int iRegion = 0; iRegion < PCI_NUM_REGIONS; iRegion++)
2389	{
2390	PCIIORegion* pRegion = &pPciDev->Int.s.aIORegions[iRegion];
2391	uint64_t iRegionSize = pRegion->size;
2392
2393	if (iRegionSize == 0)
2394	continue;
2395
2396	uint32_t u32Addr = ich9pciGetDWord(pPciDev, ich9pciGetRegionReg(iRegion));
2397	const char * pszDesc;
2398	char szDescBuf[128];
2399
2400	bool f64Bit = !!(pRegion->type & PCI_ADDRESS_SPACE_BAR64);
2401	if (pRegion->type & PCI_ADDRESS_SPACE_IO)
2402	{
2403	pszDesc = "IO";
2404	u32Addr &= ~0x3;
2405	}
2406	else
2407	{
2408	RTStrPrintf(szDescBuf, sizeof(szDescBuf), "MMIO%s%s",
2409	f64Bit ? "64" : "32",
2410	(pRegion->type & PCI_ADDRESS_SPACE_MEM_PREFETCH) ? " PREFETCH" : "");
2411	pszDesc = szDescBuf;
2412	u32Addr &= ~0xf;
2413	}
2414
2415	printIndent(pHlp, iIndent + 2);
2416	pHlp->pfnPrintf(pHlp, "%s region #%d: %x..%x\n",
2417	pszDesc, iRegion, u32Addr, u32Addr+iRegionSize);
2418	if (f64Bit)
2419	iRegion++;
2420	}
2421	}
2422
2423	printIndent(pHlp, iIndent + 2);
2424	uint16_t iStatus = ich9pciGetWord(pPciDev, VBOX_PCI_STATUS);
2425	pHlp->pfnPrintf(pHlp, "Command: %04X, Status: %04X\n",
2426	iCmd, iStatus);
2427	printIndent(pHlp, iIndent + 2);
2428	pHlp->pfnPrintf(pHlp, "Bus master: %s\n",
2429	iCmd & VBOX_PCI_COMMAND_MASTER ? "Yes" : "No");
2430
2431	if (fRegisters)
2432	{
2433	printIndent(pHlp, iIndent + 2);
2434	pHlp->pfnPrintf(pHlp, "PCI registers:\n");
2435	for (int iReg = 0; iReg < 0x100; )
2436	{
2437	int iPerLine = 0x10;
2438	Assert (0x100 % iPerLine == 0);
2439	printIndent(pHlp, iIndent + 3);
2440
2441	while (iPerLine-- > 0)
2442	{
2443	pHlp->pfnPrintf(pHlp, "%02x ", ich9pciGetByte(pPciDev, iReg++));
2444	}
2445	pHlp->pfnPrintf(pHlp, "\n");
2446	}
2447	}
2448	}
2449	}
2450
2451	if (pBus->cBridges > 0)
2452	{
2453	printIndent(pHlp, iIndent);
2454	pHlp->pfnPrintf(pHlp, "Registered %d bridges, subordinate buses info follows\n", pBus->cBridges);
2455	for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
2456	{
2457	PICH9PCIBUS pBusSub = PDMINS_2_DATA(pBus->papBridgesR3[iBridge]->pDevIns, PICH9PCIBUS);
2458	ich9pciBusInfo(pBusSub, pHlp, iIndent + 1, fRegisters);
2459	}
2460	}
2461	}
2462
2463	/**
2464	* Info handler, device version.
2465	*
2466	* @param pDevIns Device instance which registered the info.
2467	* @param pHlp Callback functions for doing output.
2468	* @param pszArgs Argument string. Optional and specific to the handler.
2469	*/
2470	static DECLCALLBACK(void) ich9pciInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
2471	{
2472	PICH9PCIBUS pBus = DEVINS_2_PCIBUS(pDevIns);
2473
2474	if (pszArgs == NULL \|\| !strcmp(pszArgs, "basic"))
2475	{
2476	ich9pciBusInfo(pBus, pHlp, 0, false);
2477	}
2478	else if (!strcmp(pszArgs, "verbose"))
2479	{
2480	ich9pciBusInfo(pBus, pHlp, 0, true);
2481	}
2482	else
2483	{
2484	pHlp->pfnPrintf(pHlp, "Invalid argument. Recognized arguments are 'basic', 'verbose'.\n");
2485	}
2486	}
2487
2488
2489	static DECLCALLBACK(int) ich9pciConstruct(PPDMDEVINS pDevIns,
2490	int iInstance,
2491	PCFGMNODE pCfg)
2492	{
2493	Assert(iInstance == 0);
2494	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
2495
2496	/*
2497	* Validate and read configuration.
2498	*/
2499	if (!CFGMR3AreValuesValid(pCfg,
2500	"IOAPIC\0"
2501	"GCEnabled\0"
2502	"R0Enabled\0"
2503	"McfgBase\0"
2504	"McfgLength\0"
2505	))
2506	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
2507
2508	/* query whether we got an IOAPIC */
2509	bool fUseIoApic;
2510	int rc = CFGMR3QueryBoolDef(pCfg, "IOAPIC", &fUseIoApic, false);
2511	if (RT_FAILURE(rc))
2512	return PDMDEV_SET_ERROR(pDevIns, rc,
2513	N_("Configuration error: Failed to query boolean value \"IOAPIC\""));
2514
2515	/* check if RC code is enabled. */
2516	bool fGCEnabled;
2517	rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
2518	if (RT_FAILURE(rc))
2519	return PDMDEV_SET_ERROR(pDevIns, rc,
2520	N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
2521	/* check if R0 code is enabled. */
2522	bool fR0Enabled;
2523	rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
2524	if (RT_FAILURE(rc))
2525	return PDMDEV_SET_ERROR(pDevIns, rc,
2526	N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
2527
2528	Log(("PCI: fUseIoApic=%RTbool fGCEnabled=%RTbool fR0Enabled=%RTbool\n", fUseIoApic, fGCEnabled, fR0Enabled));
2529
2530	/*
2531	* Init data.
2532	*/
2533	PICH9PCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
2534	PICH9PCIBUS pBus = &pGlobals->aPciBus;
2535	/* Zero out everything */
2536	memset(pGlobals, 0, sizeof(*pGlobals));
2537	/* And fill values */
2538	if (!fUseIoApic)
2539	return PDMDEV_SET_ERROR(pDevIns, rc,
2540	N_("Must use IO-APIC with ICH9 chipset"));
2541	rc = CFGMR3QueryU64Def(pCfg, "McfgBase", &pGlobals->u64PciConfigMMioAddress, 0);
2542	if (RT_FAILURE(rc))
2543	return PDMDEV_SET_ERROR(pDevIns, rc,
2544	N_("Configuration error: Failed to read \"McfgBase\""));
2545	rc = CFGMR3QueryU64Def(pCfg, "McfgLength", &pGlobals->u64PciConfigMMioLength, 0);
2546	if (RT_FAILURE(rc))
2547	return PDMDEV_SET_ERROR(pDevIns, rc,
2548	N_("Configuration error: Failed to read \"McfgLength\""));
2549
2550	pGlobals->pDevInsR3 = pDevIns;
2551	pGlobals->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2552	pGlobals->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2553
2554	pGlobals->aPciBus.pDevInsR3 = pDevIns;
2555	pGlobals->aPciBus.pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2556	pGlobals->aPciBus.pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2557	pGlobals->aPciBus.papBridgesR3 = (PPCIDEVICE )PDMDevHlpMMHeapAllocZ(pDevIns, sizeof(PPCIDEVICE) RT_ELEMENTS(pGlobals->aPciBus.apDevices));
2558
2559	/*
2560	* Register bus
2561	*/
2562	PDMPCIBUSREG PciBusReg;
2563	PciBusReg.u32Version = PDM_PCIBUSREG_VERSION;
2564	PciBusReg.pfnRegisterR3 = ich9pciRegister;
2565	PciBusReg.pfnRegisterMsiR3 = ich9pciRegisterMsi;
2566	PciBusReg.pfnIORegionRegisterR3 = ich9pciIORegionRegister;
2567	PciBusReg.pfnSetConfigCallbacksR3 = ich9pciSetConfigCallbacks;
2568	PciBusReg.pfnSetIrqR3 = ich9pciSetIrq;
2569	PciBusReg.pfnFakePCIBIOSR3 = ich9pciFakePCIBIOS;
2570	PciBusReg.pszSetIrqRC = fGCEnabled ? "ich9pciSetIrq" : NULL;
2571	PciBusReg.pszSetIrqR0 = fR0Enabled ? "ich9pciSetIrq" : NULL;
2572	rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBus->pPciHlpR3);
2573	if (RT_FAILURE(rc))
2574	return PDMDEV_SET_ERROR(pDevIns, rc,
2575	N_("Failed to register ourselves as a PCI Bus"));
2576	if (pBus->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
2577	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
2578	N_("PCI helper version mismatch; got %#x expected %#x"),
2579	pBus->pPciHlpR3->u32Version, PDM_PCIHLPR3_VERSION);
2580
2581	pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
2582	pBus->pPciHlpR0 = pBus->pPciHlpR3->pfnGetR0Helpers(pDevIns);
2583
2584	/*
2585	* Fill in PCI configs and add them to the bus.
2586	*/
2587	/** @todo: Disabled for now because this causes error messages with Linux guests.
2588	* The guest loads the x38_edac device which tries to map a memory region
2589	* using an address given at place 0x48 - 0x4f in the PCi config space.
2590	* This fails. because we don't register such a region.
2591	*/
2592	#if 0
2593	/* Host bridge device */
2594	PCIDevSetVendorId( &pBus->aPciDev, 0x8086); /* Intel */
2595	PCIDevSetDeviceId( &pBus->aPciDev, 0x29e0); /* Desktop */
2596	PCIDevSetRevisionId(&pBus->aPciDev, 0x01); /* rev. 01 */
2597	PCIDevSetClassBase( &pBus->aPciDev, 0x06); /* bridge */
2598	PCIDevSetClassSub( &pBus->aPciDev, 0x00); /* Host/PCI bridge */
2599	PCIDevSetClassProg( &pBus->aPciDev, 0x00); /* Host/PCI bridge */
2600	PCIDevSetHeaderType(&pBus->aPciDev, 0x00); /* bridge */
2601	PCIDevSetWord(&pBus->aPciDev, VBOX_PCI_SEC_STATUS, 0x0280); /* secondary status */
2602
2603	pBus->aPciDev.pDevIns = pDevIns;
2604	/* We register Host<->PCI controller on the bus */
2605	ich9pciRegisterInternal(pBus, 0, &pBus->aPciDev, "dram");
2606	#endif
2607
2608	/*
2609	* Register I/O ports and save state.
2610	*/
2611	rc = PDMDevHlpIOPortRegister(pDevIns, 0x0cf8, 1, NULL, ich9pciIOPortAddressWrite, ich9pciIOPortAddressRead, NULL, NULL, "ICH9 (PCI)");
2612	if (RT_FAILURE(rc))
2613	return rc;
2614	rc = PDMDevHlpIOPortRegister(pDevIns, 0x0cfc, 4, NULL, ich9pciIOPortDataWrite, ich9pciIOPortDataRead, NULL, NULL, "ICH9 (PCI)");
2615	if (RT_FAILURE(rc))
2616	return rc;
2617	if (fGCEnabled)
2618	{
2619	rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x0cf8, 1, NIL_RTGCPTR, "ich9pciIOPortAddressWrite", "ich9pciIOPortAddressRead", NULL, NULL, "ICH9 (PCI)");
2620	if (RT_FAILURE(rc))
2621	return rc;
2622	rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x0cfc, 4, NIL_RTGCPTR, "ich9pciIOPortDataWrite", "ich9pciIOPortDataRead", NULL, NULL, "ICH9 (PCI)");
2623	if (RT_FAILURE(rc))
2624	return rc;
2625	}
2626	if (fR0Enabled)
2627	{
2628	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x0cf8, 1, NIL_RTR0PTR, "ich9pciIOPortAddressWrite", "ich9pciIOPortAddressRead", NULL, NULL, "ICH9 (PCI)");
2629	if (RT_FAILURE(rc))
2630	return rc;
2631	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x0cfc, 4, NIL_RTR0PTR, "ich9pciIOPortDataWrite", "ich9pciIOPortDataRead", NULL, NULL, "ICH9 (PCI)");
2632	if (RT_FAILURE(rc))
2633	return rc;
2634	}
2635
2636	if (pGlobals->u64PciConfigMMioAddress != 0)
2637	{
2638	rc = PDMDevHlpMMIORegister(pDevIns, pGlobals->u64PciConfigMMioAddress, pGlobals->u64PciConfigMMioLength, NULL /pvUser/,
2639	IOMMMIO_FLAGS_READ_PASSTHRU \| IOMMMIO_FLAGS_WRITE_PASSTHRU,
2640	ich9pciMcfgMMIOWrite, ich9pciMcfgMMIORead, "MCFG ranges");
2641	AssertMsgRCReturn(rc, ("rc=%Rrc %#llx/%#llx\n", rc, pGlobals->u64PciConfigMMioAddress, pGlobals->u64PciConfigMMioLength), rc);
2642
2643	if (fGCEnabled)
2644	{
2645	rc = PDMDevHlpMMIORegisterRC(pDevIns, pGlobals->u64PciConfigMMioAddress, pGlobals->u64PciConfigMMioLength,
2646	NIL_RTRCPTR /pvUser/, "ich9pciMcfgMMIOWrite", "ich9pciMcfgMMIORead");
2647	AssertRCReturn(rc, rc);
2648	}
2649
2650
2651	if (fR0Enabled)
2652	{
2653	rc = PDMDevHlpMMIORegisterR0(pDevIns, pGlobals->u64PciConfigMMioAddress, pGlobals->u64PciConfigMMioLength,
2654	NIL_RTR0PTR /pvUser/, "ich9pciMcfgMMIOWrite", "ich9pciMcfgMMIORead");
2655	AssertRCReturn(rc, rc);
2656	}
2657	}
2658
2659	rc = PDMDevHlpSSMRegisterEx(pDevIns, VBOX_ICH9PCI_SAVED_STATE_VERSION_CURRENT,
2660	sizeof(pBus) + 16128, "pgm",
2661	NULL, NULL, NULL,
2662	NULL, ich9pciR3SaveExec, NULL,
2663	NULL, ich9pciR3LoadExec, NULL);
2664	if (RT_FAILURE(rc))
2665	return rc;
2666
2667
2668	/** @todo: other chipset devices shall be registered too */
2669
2670	PDMDevHlpDBGFInfoRegister(pDevIns, "pci", "Display PCI bus status. Recognizes 'basic' or 'verbose' "
2671	"as arguments, defaults to 'basic'.", ich9pciInfo);
2672
2673	return VINF_SUCCESS;
2674	}
2675
2676	static void ich9pciResetDevice(PPCIDEVICE pDev)
2677	{
2678	/* Clear regions */
2679	for (int iRegion = 0; iRegion < PCI_NUM_REGIONS; iRegion++)
2680	{
2681	PCIIORegion* pRegion = &pDev->Int.s.aIORegions[iRegion];
2682	if (pRegion->size == 0)
2683	continue;
2684
2685	ich9pciUnmapRegion(pDev, iRegion);
2686	}
2687
2688	if (pciDevIsPassthrough(pDev))
2689	{
2690	// no reset handler - we can do what we need in PDM reset handler
2691	// @todo: is it correct?
2692	}
2693	else
2694	{
2695	PCIDevSetCommand(pDev,
2696	PCIDevGetCommand(pDev)
2697	&
2698	~(VBOX_PCI_COMMAND_IO \| VBOX_PCI_COMMAND_MEMORY \|
2699	VBOX_PCI_COMMAND_MASTER \| VBOX_PCI_COMMAND_SPECIAL \|
2700	VBOX_PCI_COMMAND_PARITY \| VBOX_PCI_COMMAND_SERR \|
2701	VBOX_PCI_COMMAND_FAST_BACK \| VBOX_PCI_COMMAND_INTX_DISABLE));
2702
2703	/* Bridge device reset handlers processed later */
2704	if (!pciDevIsPci2PciBridge(pDev))
2705	{
2706	PCIDevSetByte(pDev, VBOX_PCI_CACHE_LINE_SIZE, 0x0);
2707	PCIDevSetInterruptLine(pDev, 0x0);
2708	}
2709
2710	/* Reset MSI message control. */
2711	if (pciDevIsMsiCapable(pDev))
2712	{
2713	/* Extracted from MsiPciConfigWrite(). */
2714	pDev->config[pDev->Int.s.u8MsiCapOffset + VBOX_MSI_CAP_MESSAGE_CONTROL] &= 0x8e;
2715	}
2716
2717	/* Reset MSI-X message control. */
2718	if (pciDevIsMsixCapable(pDev))
2719	{
2720	/* Extracted from MsixPciConfigWrite(); no side effects. */
2721	pDev->config[pDev->Int.s.u8MsixCapOffset + VBOX_MSIX_CAP_MESSAGE_CONTROL + 1] &= 0x3f;
2722	}
2723	}
2724	}
2725
2726
2727	/**
2728	* @copydoc FNPDMDEVRESET
2729	*/
2730	static DECLCALLBACK(void) ich9pciReset(PPDMDEVINS pDevIns)
2731	{
2732	PICH9PCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
2733	PICH9PCIBUS pBus = &pGlobals->aPciBus;
2734
2735	/* PCI-specific reset for each device. */
2736	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
2737	{
2738	if (pBus->apDevices[i])
2739	ich9pciResetDevice(pBus->apDevices[i]);
2740	}
2741
2742	for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
2743	{
2744	if (pBus->papBridgesR3[iBridge])
2745	ich9pcibridgeReset(pBus->papBridgesR3[iBridge]->pDevIns);
2746	}
2747
2748	ich9pciFakePCIBIOS(pDevIns);
2749	}
2750
2751	static void ich9pciRelocateDevice(PPCIDEVICE pDev, RTGCINTPTR offDelta)
2752	{
2753	if (pDev)
2754	{
2755	pDev->Int.s.pBusRC += offDelta;
2756	if (pDev->Int.s.pMsixPageRC)
2757	pDev->Int.s.pMsixPageRC += offDelta;
2758	}
2759	}
2760
2761	/**
2762	* @copydoc FNPDMDEVRELOCATE
2763	*/
2764	static DECLCALLBACK(void) ich9pciRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
2765	{
2766	PICH9PCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
2767	PICH9PCIBUS pBus = &pGlobals->aPciBus;
2768	pGlobals->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2769
2770	pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
2771	pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2772
2773	/* Relocate RC pointers for the attached pci devices. */
2774	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
2775	ich9pciRelocateDevice(pBus->apDevices[i], offDelta);
2776
2777	}
2778
2779	/**
2780	* @interface_method_impl{PDMDEVREG,pfnConstruct}
2781	*/
2782	static DECLCALLBACK(int) ich9pcibridgeConstruct(PPDMDEVINS pDevIns,
2783	int iInstance,
2784	PCFGMNODE pCfg)
2785	{
2786	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
2787
2788	/*
2789	* Validate and read configuration.
2790	*/
2791	if (!CFGMR3AreValuesValid(pCfg, "GCEnabled\0" "R0Enabled\0"))
2792	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
2793
2794	/* check if RC code is enabled. */
2795	bool fGCEnabled;
2796	int rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
2797	if (RT_FAILURE(rc))
2798	return PDMDEV_SET_ERROR(pDevIns, rc,
2799	N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
2800
2801	/* check if R0 code is enabled. */
2802	bool fR0Enabled;
2803	rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
2804	if (RT_FAILURE(rc))
2805	return PDMDEV_SET_ERROR(pDevIns, rc,
2806	N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
2807	Log(("PCI: fGCEnabled=%RTbool fR0Enabled=%RTbool\n", fGCEnabled, fR0Enabled));
2808
2809	/*
2810	* Init data and register the PCI bus.
2811	*/
2812	PICH9PCIBUS pBus = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
2813	pBus->pDevInsR3 = pDevIns;
2814	pBus->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2815	pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2816	pBus->papBridgesR3 = (PPCIDEVICE )PDMDevHlpMMHeapAllocZ(pDevIns, sizeof(PPCIDEVICE) RT_ELEMENTS(pBus->apDevices));
2817
2818	PDMPCIBUSREG PciBusReg;
2819	PciBusReg.u32Version = PDM_PCIBUSREG_VERSION;
2820	PciBusReg.pfnRegisterR3 = ich9pcibridgeRegister;
2821	PciBusReg.pfnRegisterMsiR3 = ich9pciRegisterMsi;
2822	PciBusReg.pfnIORegionRegisterR3 = ich9pciIORegionRegister;
2823	PciBusReg.pfnSetConfigCallbacksR3 = ich9pciSetConfigCallbacks;
2824	PciBusReg.pfnSetIrqR3 = ich9pcibridgeSetIrq;
2825	PciBusReg.pfnFakePCIBIOSR3 = NULL; /* Only needed for the first bus. */
2826	PciBusReg.pszSetIrqRC = fGCEnabled ? "ich9pcibridgeSetIrq" : NULL;
2827	PciBusReg.pszSetIrqR0 = fR0Enabled ? "ich9pcibridgeSetIrq" : NULL;
2828	rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBus->pPciHlpR3);
2829	if (RT_FAILURE(rc))
2830	return PDMDEV_SET_ERROR(pDevIns, rc,
2831	N_("Failed to register ourselves as a PCI Bus"));
2832	if (pBus->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
2833	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
2834	N_("PCI helper version mismatch; got %#x expected %#x"),
2835	pBus->pPciHlpR3->u32Version, PDM_PCIHLPR3_VERSION);
2836
2837	pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
2838	pBus->pPciHlpR0 = pBus->pPciHlpR3->pfnGetR0Helpers(pDevIns);
2839
2840	/* Disable default device locking. */
2841	rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
2842	AssertRCReturn(rc, rc);
2843
2844	/*
2845	* Fill in PCI configs and add them to the bus.
2846	*/
2847	PCIDevSetVendorId( &pBus->aPciDev, 0x8086); /* Intel */
2848	PCIDevSetDeviceId( &pBus->aPciDev, 0x2448); /* 82801 Mobile PCI bridge. */
2849	PCIDevSetRevisionId(&pBus->aPciDev, 0xf2);
2850	PCIDevSetClassSub( &pBus->aPciDev, 0x04); /* pci2pci */
2851	PCIDevSetClassBase( &pBus->aPciDev, 0x06); /* PCI_bridge */
2852	PCIDevSetClassProg( &pBus->aPciDev, 0x01); /* Supports subtractive decoding. */
2853	PCIDevSetHeaderType(&pBus->aPciDev, 0x01); /* Single function device which adheres to the PCI-to-PCI bridge spec. */
2854	PCIDevSetCommand( &pBus->aPciDev, 0x00);
2855	PCIDevSetStatus( &pBus->aPciDev, 0x20); /* 66MHz Capable. */
2856	PCIDevSetInterruptLine(&pBus->aPciDev, 0x00); /* This device does not assert interrupts. */
2857
2858	/*
2859	* This device does not generate interrupts. Interrupt delivery from
2860	* devices attached to the bus is unaffected.
2861	*/
2862	PCIDevSetInterruptPin (&pBus->aPciDev, 0x00);
2863
2864	pBus->aPciDev.pDevIns = pDevIns;
2865
2866	/* Bridge-specific data */
2867	pciDevSetPci2PciBridge(&pBus->aPciDev);
2868	pBus->aPciDev.Int.s.pfnBridgeConfigRead = ich9pcibridgeConfigRead;
2869	pBus->aPciDev.Int.s.pfnBridgeConfigWrite = ich9pcibridgeConfigWrite;
2870
2871	/*
2872	* Register this PCI bridge. The called function will take care on which bus we will get registered.
2873	*/
2874	rc = PDMDevHlpPCIRegister (pDevIns, &pBus->aPciDev);
2875	if (RT_FAILURE(rc))
2876	return rc;
2877
2878	/*
2879	* The iBus property doesn't really represent the bus number
2880	* because the guest and the BIOS can choose different bus numbers
2881	* for them.
2882	* The bus number is mainly for the setIrq function to indicate
2883	* when the host bus is reached which will have iBus = 0.
2884	* That's why the + 1.
2885	*/
2886	pBus->iBus = iInstance + 1;
2887
2888	/*
2889	* Register SSM handlers. We use the same saved state version as for the host bridge
2890	* to make changes easier.
2891	*/
2892	rc = PDMDevHlpSSMRegisterEx(pDevIns, VBOX_ICH9PCI_SAVED_STATE_VERSION_CURRENT,
2893	sizeof(pBus) + 16128,
2894	"pgm" /* before */,
2895	NULL, NULL, NULL,
2896	NULL, ich9pcibridgeR3SaveExec, NULL,
2897	NULL, ich9pcibridgeR3LoadExec, NULL);
2898	if (RT_FAILURE(rc))
2899	return rc;
2900
2901
2902	return VINF_SUCCESS;
2903	}
2904
2905	/**
2906	* @copydoc FNPDMDEVRESET
2907	*/
2908	static void ich9pcibridgeReset(PPDMDEVINS pDevIns)
2909	{
2910	PICH9PCIBUS pBus = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
2911
2912	/* Reset config space to default values. */
2913	PCIDevSetByte(&pBus->aPciDev, VBOX_PCI_PRIMARY_BUS, 0);
2914	PCIDevSetByte(&pBus->aPciDev, VBOX_PCI_SECONDARY_BUS, 0);
2915	PCIDevSetByte(&pBus->aPciDev, VBOX_PCI_SUBORDINATE_BUS, 0);
2916
2917	/* PCI-specific reset for each device. */
2918	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
2919	{
2920	if (pBus->apDevices[i])
2921	ich9pciResetDevice(pBus->apDevices[i]);
2922	}
2923	}
2924
2925
2926	/**
2927	* @copydoc FNPDMDEVRELOCATE
2928	*/
2929	static DECLCALLBACK(void) ich9pcibridgeRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
2930	{
2931	PICH9PCIBUS pBus = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
2932	pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2933
2934	/* Relocate RC pointers for the attached pci devices. */
2935	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
2936	ich9pciRelocateDevice(pBus->apDevices[i], offDelta);
2937	}
2938
2939	/**
2940	* The PCI bus device registration structure.
2941	*/
2942	const PDMDEVREG g_DevicePciIch9 =
2943	{
2944	/* u32Version */
2945	PDM_DEVREG_VERSION,
2946	/* szName */
2947	"ich9pci",
2948	/* szRCMod */
2949	"VBoxDDRC.rc",
2950	/* szR0Mod */
2951	"VBoxDDR0.r0",
2952	/* pszDescription */
2953	"ICH9 PCI bridge",
2954	/* fFlags */
2955	PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
2956	/* fClass */
2957	PDM_DEVREG_CLASS_BUS_PCI \| PDM_DEVREG_CLASS_BUS_ISA,
2958	/* cMaxInstances */
2959	1,
2960	/* cbInstance */
2961	sizeof(ICH9PCIGLOBALS),
2962	/* pfnConstruct */
2963	ich9pciConstruct,
2964	/* pfnDestruct */
2965	NULL,
2966	/* pfnRelocate */
2967	ich9pciRelocate,
2968	/* pfnMemSetup */
2969	NULL,
2970	/* pfnPowerOn */
2971	NULL,
2972	/* pfnReset */
2973	ich9pciReset,
2974	/* pfnSuspend */
2975	NULL,
2976	/* pfnResume */
2977	NULL,
2978	/* pfnAttach */
2979	NULL,
2980	/* pfnDetach */
2981	NULL,
2982	/* pfnQueryInterface */
2983	NULL,
2984	/* pfnInitComplete */
2985	NULL,
2986	/* pfnPowerOff */
2987	NULL,
2988	/* pfnSoftReset */
2989	NULL,
2990	/* u32VersionEnd */
2991	PDM_DEVREG_VERSION
2992	};
2993
2994	/**
2995	* The device registration structure
2996	* for the PCI-to-PCI bridge.
2997	*/
2998	const PDMDEVREG g_DevicePciIch9Bridge =
2999	{
3000	/* u32Version */
3001	PDM_DEVREG_VERSION,
3002	/* szName */
3003	"ich9pcibridge",
3004	/* szRCMod */
3005	"VBoxDDRC.rc",
3006	/* szR0Mod */
3007	"VBoxDDR0.r0",
3008	/* pszDescription */
3009	"ICH9 PCI to PCI bridge",
3010	/* fFlags */
3011	PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
3012	/* fClass */
3013	PDM_DEVREG_CLASS_BUS_PCI,
3014	/* cMaxInstances */
3015	~0U,
3016	/* cbInstance */
3017	sizeof(ICH9PCIBUS),
3018	/* pfnConstruct */
3019	ich9pcibridgeConstruct,
3020	/* pfnDestruct */
3021	NULL,
3022	/* pfnRelocate */
3023	ich9pcibridgeRelocate,
3024	/* pfnMemSetup */
3025	NULL,
3026	/* pfnPowerOn */
3027	NULL,
3028	/* pfnReset */
3029	NULL, /* Must be NULL, to make sure only bus driver handles reset */
3030	/* pfnSuspend */
3031	NULL,
3032	/* pfnResume */
3033	NULL,
3034	/* pfnAttach */
3035	NULL,
3036	/* pfnDetach */
3037	NULL,
3038	/* pfnQueryInterface */
3039	NULL,
3040	/* pfnInitComplete */
3041	NULL,
3042	/* pfnPowerOff */
3043	NULL,
3044	/* pfnSoftReset */
3045	NULL,
3046	/* u32VersionEnd */
3047	PDM_DEVREG_VERSION
3048	};
3049
3050	#endif /* IN_RING3 */
3051	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */

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source: vbox/trunk/src/VBox/Devices/Bus/DevPciIch9.cpp@ 57526

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