DevPciIch9.cpp@ 61497

Last change on this file since 61497 was 58091, checked in by vboxsync, 9 years ago
pciraw: integrate the changes to make MSI work, and assorted fixes and cleanups
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1	/* $Id: DevPciIch9.cpp 58091 2015-10-07 13:28:38Z vboxsync $ */
2	/** @file
3	* DevPCI - ICH9 southbridge PCI bus emulation device.
4	*
5	* @note bird: I've cleaned up DevPCI.cpp to some extend, this file has not
6	* be cleaned up and because of pending code merge.
7	*/
8
9	/*
10	* Copyright (C) 2010-2015 Oracle Corporation
11	*
12	* This file is part of VirtualBox Open Source Edition (OSE), as
13	* available from http://www.virtualbox.org. This file is free software;
14	* you can redistribute it and/or modify it under the terms of the GNU
15	* General Public License (GPL) as published by the Free Software
16	* Foundation, in version 2 as it comes in the "COPYING" file of the
17	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
18	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
19	*/
20
21
22	/*********************************************************************************************************************************
23	* Header Files *
24	*********************************************************************************************************************************/
25	#define LOG_GROUP LOG_GROUP_DEV_PCI
26	/* Hack to get PCIDEVICEINT declared at the right point - include "PCIInternal.h". */
27	#define PCI_INCLUDE_PRIVATE
28	#define PCIBus ICH9PCIBus
29	#include <VBox/pci.h>
30	#include <VBox/msi.h>
31	#include <VBox/vmm/pdmdev.h>
32	#include <iprt/asm.h>
33	#include <iprt/assert.h>
34	#include <iprt/string.h>
35	#ifdef IN_RING3
36	#include <iprt/alloc.h>
37	#endif
38
39	#include "VBoxDD.h"
40	#include "MsiCommon.h"
41
42
43	/*********************************************************************************************************************************
44	* Structures and Typedefs *
45	*********************************************************************************************************************************/
46	/**
47	* PCI Bus instance.
48	*/
49	typedef struct ICH9PCIBus
50	{
51	/** Bus number. */
52	int32_t iBus;
53	/** Number of bridges attached to the bus. */
54	uint32_t cBridges;
55
56	/** Array of PCI devices. We assume 32 slots, each with 8 functions. */
57	R3PTRTYPE(PPCIDEVICE) apDevices[256];
58	/** Array of bridges attached to the bus. */
59	R3PTRTYPE(PPCIDEVICE *) papBridgesR3;
60
61	/** R3 pointer to the device instance. */
62	PPDMDEVINSR3 pDevInsR3;
63	/** Pointer to the PCI R3 helpers. */
64	PCPDMPCIHLPR3 pPciHlpR3;
65
66	/** R0 pointer to the device instance. */
67	PPDMDEVINSR0 pDevInsR0;
68	/** Pointer to the PCI R0 helpers. */
69	PCPDMPCIHLPR0 pPciHlpR0;
70
71	/** RC pointer to the device instance. */
72	PPDMDEVINSRC pDevInsRC;
73	/** Pointer to the PCI RC helpers. */
74	PCPDMPCIHLPRC pPciHlpRC;
75
76	/** The PCI device for the PCI bridge. */
77	PCIDEVICE aPciDev;
78
79	} ICH9PCIBUS, *PICH9PCIBUS;
80
81
82	/** @def PCI_APIC_IRQ_PINS
83	* Number of pins for interrupts if the APIC is used.
84	*/
85	#define PCI_APIC_IRQ_PINS 8
86
87	/**
88	* PCI Globals - This is the host-to-pci bridge and the root bus.
89	*/
90	typedef struct
91	{
92	/** R3 pointer to the device instance. */
93	PPDMDEVINSR3 pDevInsR3;
94	/** R0 pointer to the device instance. */
95	PPDMDEVINSR0 pDevInsR0;
96	/** RC pointer to the device instance. */
97	PPDMDEVINSRC pDevInsRC;
98
99	#if HC_ARCH_BITS == 64
100	uint32_t Alignment0;
101	#endif
102
103	/** Value latched in Configuration Address Port (0CF8h) */
104	uint32_t uConfigReg;
105
106	/** I/O APIC irq levels */
107	volatile uint32_t uaPciApicIrqLevels[PCI_APIC_IRQ_PINS];
108
109	#if 1 /* Will be moved into the BIOS soon. */
110	/** The next I/O port address which the PCI BIOS will use. */
111	uint32_t uPciBiosIo;
112	/** The next MMIO address which the PCI BIOS will use. */
113	uint32_t uPciBiosMmio;
114	/** Actual bus number. */
115	uint8_t uBus;
116	#endif
117	/** Physical address of PCI config space MMIO region. */
118	uint64_t u64PciConfigMMioAddress;
119	/** Length of PCI config space MMIO region. */
120	uint64_t u64PciConfigMMioLength;
121
122	/** PCI bus which is attached to the host-to-PCI bridge. */
123	ICH9PCIBUS aPciBus;
124	} ICH9PCIGLOBALS, *PICH9PCIGLOBALS;
125
126
127	/**
128	* PCI configuration space address.
129	*/
130	typedef struct
131	{
132	uint8_t iBus;
133	uint8_t iDeviceFunc;
134	uint16_t iRegister;
135	} PciAddress;
136
137	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
138
139
140	/*********************************************************************************************************************************
141	* Defined Constants And Macros *
142	*********************************************************************************************************************************/
143
144	/** @def VBOX_ICH9PCI_SAVED_STATE_VERSION
145	* Saved state version of the ICH9 PCI bus device.
146	*/
147	#define VBOX_ICH9PCI_SAVED_STATE_VERSION_NOMSI 1
148	#define VBOX_ICH9PCI_SAVED_STATE_VERSION_MSI 2
149	#define VBOX_ICH9PCI_SAVED_STATE_VERSION_CURRENT VBOX_ICH9PCI_SAVED_STATE_VERSION_MSI
150
151	/** Converts a bus instance pointer to a device instance pointer. */
152	#define PCIBUS_2_DEVINS(pPciBus) ((pPciBus)->CTX_SUFF(pDevIns))
153	/** Converts a device instance pointer to a ICH9PCIGLOBALS pointer. */
154	#define DEVINS_2_PCIGLOBALS(pDevIns) ((PICH9PCIGLOBALS)(PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS)))
155	/** Converts a device instance pointer to a PCIBUS pointer. */
156	#define DEVINS_2_PCIBUS(pDevIns) ((PICH9PCIBUS)(&PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS)->aPciBus))
157	/** Converts a pointer to a PCI root bus instance to a PCIGLOBALS pointer. */
158	#define PCIROOTBUS_2_PCIGLOBALS(pPciBus) ( (PICH9PCIGLOBALS)((uintptr_t)(pPciBus) - RT_OFFSETOF(ICH9PCIGLOBALS, aPciBus)) )
159
160	/** @def PCI_LOCK
161	* Acquires the PDM lock. This is a NOP if locking is disabled. */
162	/** @def PCI_UNLOCK
163	* Releases the PDM lock. This is a NOP if locking is disabled. */
164	#define PCI_LOCK(pDevIns, rc) \
165	do { \
166	int rc2 = DEVINS_2_PCIBUS(pDevIns)->CTX_SUFF(pPciHlp)->pfnLock((pDevIns), rc); \
167	if (rc2 != VINF_SUCCESS) \
168	return rc2; \
169	} while (0)
170	#define PCI_UNLOCK(pDevIns) \
171	DEVINS_2_PCIBUS(pDevIns)->CTX_SUFF(pPciHlp)->pfnUnlock(pDevIns)
172
173	/* Prototypes */
174	static void ich9pciSetIrqInternal(PICH9PCIGLOBALS pGlobals, uint8_t uDevFn, PPCIDEVICE pPciDev,
175	int iIrq, int iLevel, uint32_t uTagSrc);
176	#ifdef IN_RING3
177	static void ich9pcibridgeReset(PPDMDEVINS pDevIns);
178	static int ich9pciRegisterInternal(PICH9PCIBUS pBus, int iDev, PPCIDEVICE pPciDev, const char *pszName);
179	static void ich9pciUpdateMappings(PCIDevice *pDev);
180	static DECLCALLBACK(uint32_t) ich9pciConfigReadDev(PCIDevice *aDev, uint32_t u32Address, unsigned len);
181	DECLINLINE(PPCIDEVICE) ich9pciFindBridge(PICH9PCIBUS pBus, uint8_t iBus);
182	static void ich9pciBiosInitDevice(PICH9PCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn);
183	#endif
184
185	// See 7.2.2. PCI Express Enhanced Configuration Mechanism for details of address
186	// mapping, we take n=6 approach
187	DECLINLINE(void) ich9pciPhysToPciAddr(PICH9PCIGLOBALS pGlobals, RTGCPHYS GCPhysAddr, PciAddress* pPciAddr)
188	{
189	NOREF(pGlobals);
190	pPciAddr->iBus = (GCPhysAddr >> 20) & ((1<<6) - 1);
191	pPciAddr->iDeviceFunc = (GCPhysAddr >> 12) & ((1<<(5+3)) - 1); // 5 bits - device, 3 bits - function
192	pPciAddr->iRegister = (GCPhysAddr >> 0) & ((1<<(6+4+2)) - 1); // 6 bits - register, 4 bits - extended register, 2 bits -Byte Enable
193	}
194
195	DECLINLINE(void) ich9pciStateToPciAddr(PICH9PCIGLOBALS pGlobals, RTGCPHYS addr, PciAddress* pPciAddr)
196	{
197	pPciAddr->iBus = (pGlobals->uConfigReg >> 16) & 0xff;
198	pPciAddr->iDeviceFunc = (pGlobals->uConfigReg >> 8) & 0xff;
199	pPciAddr->iRegister = (pGlobals->uConfigReg & 0xfc) \| (addr & 3);
200	}
201
202	PDMBOTHCBDECL(void) ich9pciSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel, uint32_t uTagSrc)
203	{
204	LogFlowFunc(("invoked by %p/%d: iIrq=%d iLevel=%d uTagSrc=%#x\n", pDevIns, pDevIns->iInstance, iIrq, iLevel, uTagSrc));
205	ich9pciSetIrqInternal(PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS), pPciDev->devfn, pPciDev, iIrq, iLevel, uTagSrc);
206	}
207
208	PDMBOTHCBDECL(void) ich9pcibridgeSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel, uint32_t uTagSrc)
209	{
210	/*
211	* The PCI-to-PCI bridge specification defines how the interrupt pins
212	* are routed from the secondary to the primary bus (see chapter 9).
213	* iIrq gives the interrupt pin the pci device asserted.
214	* We change iIrq here according to the spec and call the SetIrq function
215	* of our parent passing the device which asserted the interrupt instead of the device of the bridge.
216	*/
217	PICH9PCIBUS pBus = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
218	PPCIDEVICE pPciDevBus = pPciDev;
219	int iIrqPinBridge = iIrq;
220	uint8_t uDevFnBridge = 0;
221
222	/* Walk the chain until we reach the host bus. */
223	do
224	{
225	uDevFnBridge = pBus->aPciDev.devfn;
226	iIrqPinBridge = ((pPciDevBus->devfn >> 3) + iIrqPinBridge) & 3;
227
228	/* Get the parent. */
229	pBus = pBus->aPciDev.Int.s.CTX_SUFF(pBus);
230	pPciDevBus = &pBus->aPciDev;
231	} while (pBus->iBus != 0);
232
233	AssertMsgReturnVoid(pBus->iBus == 0, ("This is not the host pci bus iBus=%d\n", pBus->iBus));
234	ich9pciSetIrqInternal(PCIROOTBUS_2_PCIGLOBALS(pBus), uDevFnBridge, pPciDev, iIrqPinBridge, iLevel, uTagSrc);
235	}
236
237
238	/**
239	* Port I/O Handler for PCI address OUT operations.
240	*
241	* Emulates writes to Configuration Address Port at 0CF8h for
242	* Configuration Mechanism #1.
243	*
244	* @returns VBox status code.
245	*
246	* @param pDevIns ICH9 device instance.
247	* @param pvUser User argument - ignored.
248	* @param uPort Port number used for the OUT operation.
249	* @param u32 The value to output.
250	* @param cb The value size in bytes.
251	*/
252	PDMBOTHCBDECL(int) ich9pciIOPortAddressWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
253	{
254	LogFlow(("ich9pciIOPortAddressWrite: Port=%#x u32=%#x cb=%d\n", Port, u32, cb));
255	NOREF(pvUser);
256	if (cb == 4)
257	{
258	PICH9PCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
259
260	/*
261	* bits [1:0] are hard-wired, read-only and must return zeroes
262	* when read.
263	*/
264	u32 &= ~3;
265
266	PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_WRITE);
267	pThis->uConfigReg = u32;
268	PCI_UNLOCK(pDevIns);
269	}
270
271	return VINF_SUCCESS;
272	}
273
274
275	/**
276	* Port I/O Handler for PCI address IN operations.
277	*
278	* Emulates reads from Configuration Address Port at 0CF8h for
279	* Configuration Mechanism #1.
280	*
281	* @returns VBox status code.
282	*
283	* @param pDevIns ICH9 device instance.
284	* @param pvUser User argument - ignored.
285	* @param uPort Port number used for the IN operation.
286	* @param pu32 Where to store the result.
287	* @param cb Number of bytes read.
288	*/
289	PDMBOTHCBDECL(int) ich9pciIOPortAddressRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
290	{
291	NOREF(pvUser);
292	if (cb == 4)
293	{
294	PICH9PCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
295
296	PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_READ);
297	*pu32 = pThis->uConfigReg;
298	PCI_UNLOCK(pDevIns);
299
300	LogFlow(("ich9pciIOPortAddressRead: Port=%#x cb=%d -> %#x\n", Port, cb, *pu32));
301	return VINF_SUCCESS;
302	}
303
304	Log(("ich9pciIOPortAddressRead: Port=%#x cb=%d VERR_IOM_IOPORT_UNUSED\n", Port, cb));
305	return VERR_IOM_IOPORT_UNUSED;
306	}
307
308
309	/*
310	* Perform configuration space write.
311	*/
312	static int ich9pciDataWriteAddr(PICH9PCIGLOBALS pGlobals, PciAddress* pAddr,
313	uint32_t val, int cb, int rcReschedule)
314	{
315	int rc = VINF_SUCCESS;
316	#ifdef IN_RING3
317	NOREF(rcReschedule);
318	#endif
319
320	if (pAddr->iBus != 0) /* forward to subordinate bus */
321	{
322	if (pGlobals->aPciBus.cBridges)
323	{
324	#ifdef IN_RING3 /** @todo do lookup in R0/RC too! */
325	PPCIDEVICE pBridgeDevice = ich9pciFindBridge(&pGlobals->aPciBus, pAddr->iBus);
326	if (pBridgeDevice)
327	{
328	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigWrite);
329	pBridgeDevice->Int.s.pfnBridgeConfigWrite(pBridgeDevice->pDevIns, pAddr->iBus, pAddr->iDeviceFunc,
330	pAddr->iRegister, val, cb);
331	}
332	#else
333	rc = rcReschedule;
334	#endif
335	}
336	}
337	else /* forward to directly connected device */
338	{
339	R3PTRTYPE(PCIDevice *) aDev = pGlobals->aPciBus.apDevices[pAddr->iDeviceFunc];
340	if (aDev)
341	{
342	#ifdef IN_RING3
343	aDev->Int.s.pfnConfigWrite(aDev, pAddr->iRegister, val, cb);
344	#else
345	rc = rcReschedule;
346	#endif
347	}
348	}
349
350	Log2(("ich9pciDataWriteAddr: %02x:%02x:%02x reg %x(%d) %x %Rrc\n",
351	pAddr->iBus, pAddr->iDeviceFunc >> 3, pAddr->iDeviceFunc & 0x7, pAddr->iRegister,
352	cb, val, rc));
353	return rc;
354	}
355
356
357	/*
358	* Decode value latched in Configuration Address Port and perform
359	* requsted write to the target configuration space register.
360	*
361	* XXX: This code should be probably moved to its only caller
362	* (ich9pciIOPortDataWrite) to avoid prolifiration of confusingly
363	* similarly named functions.
364	*/
365	static int ich9pciDataWrite(PICH9PCIGLOBALS pGlobals, uint32_t addr, uint32_t val, int len)
366	{
367	LogFlow(("ich9pciDataWrite: config=%08x val=%08x len=%d\n", pGlobals->uConfigReg, val, len));
368
369	/* Configuration space mapping enabled? */
370	if (!(pGlobals->uConfigReg & (1 << 31)))
371	return VINF_SUCCESS;
372
373	/* Decode target device and configuration space register */
374	PciAddress aPciAddr;
375	ich9pciStateToPciAddr(pGlobals, addr, &aPciAddr);
376
377	/* Perform configuration space write */
378	return ich9pciDataWriteAddr(pGlobals, &aPciAddr, val, len, VINF_IOM_R3_IOPORT_WRITE);
379	}
380
381
382	/**
383	* Port I/O Handler for PCI data OUT operations.
384	*
385	* Emulates writes to Configuration Data Port at 0CFCh for
386	* Configuration Mechanism #1.
387	*
388	* @returns VBox status code.
389	*
390	* @param pDevIns ICH9 device instance.
391	* @param pvUser User argument - ignored.
392	* @param uPort Port number used for the OUT operation.
393	* @param u32 The value to output.
394	* @param cb The value size in bytes.
395	*/
396	PDMBOTHCBDECL(int) ich9pciIOPortDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
397	{
398	LogFlow(("ich9pciIOPortDataWrite: Port=%#x u32=%#x cb=%d\n", Port, u32, cb));
399	NOREF(pvUser);
400	int rc = VINF_SUCCESS;
401	if (!(Port % cb))
402	{
403	PICH9PCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
404
405	PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_WRITE);
406	rc = ich9pciDataWrite(pThis, Port, u32, cb);
407	PCI_UNLOCK(pDevIns);
408	}
409	else
410	AssertMsgFailed(("Unaligned write to port %#x u32=%#x cb=%d\n", Port, u32, cb));
411	return rc;
412	}
413
414
415	static void ich9pciNoMem(void* ptr, int cb)
416	{
417	for (int i = 0; i < cb; i++)
418	((uint8_t*)ptr)[i] = 0xff;
419	}
420
421
422	/*
423	* Perform configuration space read.
424	*/
425	static int ich9pciDataReadAddr(PICH9PCIGLOBALS pGlobals, PciAddress* pPciAddr, int cb,
426	uint32_t *pu32, int rcReschedule)
427	{
428	int rc = VINF_SUCCESS;
429	#ifdef IN_RING3
430	NOREF(rcReschedule);
431	#endif
432
433	if (pPciAddr->iBus != 0) /* forward to subordinate bus */
434	{
435	if (pGlobals->aPciBus.cBridges)
436	{
437	#ifdef IN_RING3 /** @todo do lookup in R0/RC too! */
438	PPCIDEVICE pBridgeDevice = ich9pciFindBridge(&pGlobals->aPciBus, pPciAddr->iBus);
439	if (pBridgeDevice)
440	{
441	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigRead);
442	*pu32 = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->pDevIns, pPciAddr->iBus, pPciAddr->iDeviceFunc, pPciAddr->iRegister, cb);
443	}
444	else
445	ich9pciNoMem(pu32, cb);
446	#else
447	rc = rcReschedule;
448	#endif
449	}
450	else
451	ich9pciNoMem(pu32, cb);
452	}
453	else /* forward to directly connected device */
454	{
455	R3PTRTYPE(PCIDevice *) aDev = pGlobals->aPciBus.apDevices[pPciAddr->iDeviceFunc];
456	if (aDev)
457	{
458	#ifdef IN_RING3
459	*pu32 = aDev->Int.s.pfnConfigRead(aDev, pPciAddr->iRegister, cb);
460	#else
461	rc = rcReschedule;
462	#endif
463	}
464	else
465	ich9pciNoMem(pu32, cb);
466	}
467
468	Log3(("ich9pciDataReadAddr: %02x:%02x:%02x reg %x(%d) gave %x %Rrc\n",
469	pPciAddr->iBus, pPciAddr->iDeviceFunc >> 3, pPciAddr->iDeviceFunc & 0x7, pPciAddr->iRegister,
470	cb, *pu32, rc));
471	return rc;
472	}
473
474
475	/*
476	* Decode value latched in Configuration Address Port and perform
477	* requsted read from the target configuration space register.
478	*
479	* XXX: This code should be probably moved to its only caller
480	* (ich9pciIOPortDataRead) to avoid prolifiration of confusingly
481	* similarly named functions.
482	*/
483	static int ich9pciDataRead(PICH9PCIGLOBALS pGlobals, uint32_t addr, int cb, uint32_t *pu32)
484	{
485	LogFlow(("ich9pciDataRead: config=%x cb=%d\n", pGlobals->uConfigReg, cb));
486
487	*pu32 = 0xffffffff;
488
489	/* Configuration space mapping enabled? */
490	if (!(pGlobals->uConfigReg & (1 << 31)))
491	return VINF_SUCCESS;
492
493	/* Decode target device and configuration space register */
494	PciAddress aPciAddr;
495	ich9pciStateToPciAddr(pGlobals, addr, &aPciAddr);
496
497	/* Perform configuration space read */
498	return ich9pciDataReadAddr(pGlobals, &aPciAddr, cb, pu32, VINF_IOM_R3_IOPORT_READ);
499	}
500
501
502	/**
503	* Port I/O Handler for PCI data IN operations.
504	*
505	* Emulates reads from Configuration Data Port at 0CFCh for
506	* Configuration Mechanism #1.
507	*
508	* @returns VBox status code.
509	*
510	* @param pDevIns ICH9 device instance.
511	* @param pvUser User argument - ignored.
512	* @param uPort Port number used for the IN operation.
513	* @param pu32 Where to store the result.
514	* @param cb Number of bytes read.
515	*/
516	PDMBOTHCBDECL(int) ich9pciIOPortDataRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
517	{
518	NOREF(pvUser);
519	if (!(Port % cb))
520	{
521	PICH9PCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
522
523	PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_READ);
524	int rc = ich9pciDataRead(pThis, Port, cb, pu32);
525	PCI_UNLOCK(pDevIns);
526
527	LogFlow(("ich9pciIOPortDataRead: Port=%#x cb=%#x -> %#x (%Rrc)\n", Port, cb, *pu32, rc));
528	return rc;
529	}
530	AssertMsgFailed(("Unaligned read from port %#x cb=%d\n", Port, cb));
531	return VERR_IOM_IOPORT_UNUSED;
532	}
533
534
535	/* Compute mapping of PCI slot and IRQ number to APIC interrupt line */
536	DECLINLINE(int) ich9pciSlot2ApicIrq(uint8_t uSlot, int irq_num)
537	{
538	return (irq_num + uSlot) & 7;
539	}
540
541	/* return the global irq number corresponding to a given device irq
542	pin. We could also use the bus number to have a more precise
543	mapping. This is the implementation note described in the PCI spec chapter 2.2.6 */
544	DECLINLINE(int) ich9pciSlotGetPirq(uint8_t uBus, uint8_t uDevFn, int iIrqNum)
545	{
546	NOREF(uBus);
547	int iSlotAddend = (uDevFn >> 3) - 1;
548	return (iIrqNum + iSlotAddend) & 3;
549	}
550
551	/* irqs corresponding to PCI irqs A-D, must match pci_irq_list in rombios.c */
552	static const uint8_t aPciIrqs[4] = { 11, 10, 9, 5 };
553
554	/* Add one more level up request on APIC input line */
555	DECLINLINE(void) ich9pciApicLevelUp(PICH9PCIGLOBALS pGlobals, int irq_num)
556	{
557	ASMAtomicIncU32(&pGlobals->uaPciApicIrqLevels[irq_num]);
558	}
559
560	/* Remove one level up request on APIC input line */
561	DECLINLINE(void) ich9pciApicLevelDown(PICH9PCIGLOBALS pGlobals, int irq_num)
562	{
563	ASMAtomicDecU32(&pGlobals->uaPciApicIrqLevels[irq_num]);
564	}
565
566	static void ich9pciApicSetIrq(PICH9PCIBUS pBus, uint8_t uDevFn, PCIDevice *pPciDev, int irq_num1, int iLevel,
567	uint32_t uTagSrc, int iForcedIrq)
568	{
569	/* This is only allowed to be called with a pointer to the root bus. */
570	AssertMsg(pBus->iBus == 0, ("iBus=%u\n", pBus->iBus));
571
572	if (iForcedIrq == -1)
573	{
574	int apic_irq, apic_level;
575	PICH9PCIGLOBALS pGlobals = PCIROOTBUS_2_PCIGLOBALS(pBus);
576	int irq_num = ich9pciSlot2ApicIrq(uDevFn >> 3, irq_num1);
577
578	if ((iLevel & PDM_IRQ_LEVEL_HIGH) == PDM_IRQ_LEVEL_HIGH)
579	ich9pciApicLevelUp(pGlobals, irq_num);
580	else if ((iLevel & PDM_IRQ_LEVEL_HIGH) == PDM_IRQ_LEVEL_LOW)
581	ich9pciApicLevelDown(pGlobals, irq_num);
582
583	apic_irq = irq_num + 0x10;
584	apic_level = pGlobals->uaPciApicIrqLevels[irq_num] != 0;
585	Log3(("ich9pciApicSetIrq: %s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d uTagSrc=%#x\n",
586	R3STRING(pPciDev->name), irq_num1, iLevel, apic_irq, apic_level, irq_num, uTagSrc));
587	pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), apic_irq, apic_level, uTagSrc);
588
589	if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP)
590	{
591	/*
592	* we raised it few lines above, as PDM_IRQ_LEVEL_FLIP_FLOP has
593	* PDM_IRQ_LEVEL_HIGH bit set
594	*/
595	ich9pciApicLevelDown(pGlobals, irq_num);
596	pPciDev->Int.s.uIrqPinState = PDM_IRQ_LEVEL_LOW;
597	apic_level = pGlobals->uaPciApicIrqLevels[irq_num] != 0;
598	Log3(("ich9pciApicSetIrq: %s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d uTagSrc=%#x (flop)\n",
599	R3STRING(pPciDev->name), irq_num1, iLevel, apic_irq, apic_level, irq_num, uTagSrc));
600	pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), apic_irq, apic_level, uTagSrc);
601	}
602	} else {
603	Log3(("ich9pciApicSetIrq: (forced) %s: irq_num1=%d level=%d acpi_irq=%d uTagSrc=%#x\n",
604	R3STRING(pPciDev->name), irq_num1, iLevel, iForcedIrq, uTagSrc));
605	pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), iForcedIrq, iLevel, uTagSrc);
606	}
607	}
608
609	static void ich9pciSetIrqInternal(PICH9PCIGLOBALS pGlobals, uint8_t uDevFn, PPCIDEVICE pPciDev,
610	int iIrq, int iLevel, uint32_t uTagSrc)
611	{
612	/* If MSI or MSI-X is enabled, PCI INTx# signals are disabled regardless of the PCI command
613	* register interrupt bit state.
614	* PCI 3.0 (section 6.8) forbids MSI and MSI-X to be enabled at the same time and makes
615	* that undefined behavior. We check for MSI first, then MSI-X.
616	*/
617	if (MsiIsEnabled(pPciDev))
618	{
619	Assert(!MsixIsEnabled(pPciDev)); /* Not allowed -- see note above. */
620	LogFlowFunc(("PCI Dev %p : MSI\n", pPciDev));
621	PPDMDEVINS pDevIns = pGlobals->aPciBus.CTX_SUFF(pDevIns);
622	MsiNotify(pDevIns, pGlobals->aPciBus.CTX_SUFF(pPciHlp), pPciDev, iIrq, iLevel, uTagSrc);
623	return;
624	}
625
626	if (MsixIsEnabled(pPciDev))
627	{
628	LogFlowFunc(("PCI Dev %p : MSI-X\n", pPciDev));
629	PPDMDEVINS pDevIns = pGlobals->aPciBus.CTX_SUFF(pDevIns);
630	MsixNotify(pDevIns, pGlobals->aPciBus.CTX_SUFF(pPciHlp), pPciDev, iIrq, iLevel, uTagSrc);
631	return;
632	}
633
634	PICH9PCIBUS pBus = &pGlobals->aPciBus;
635	const bool fIsAcpiDevice = PCIDevGetDeviceId(pPciDev) == 0x7113;
636
637	LogFlowFunc(("PCI Dev %p : IRQ\n", pPciDev));
638	/* Check if the state changed. */
639	if (pPciDev->Int.s.uIrqPinState != iLevel)
640	{
641	pPciDev->Int.s.uIrqPinState = (iLevel & PDM_IRQ_LEVEL_HIGH);
642
643	/* Send interrupt to I/O APIC only now. */
644	if (fIsAcpiDevice)
645	/*
646	* ACPI needs special treatment since SCI is hardwired and
647	* should not be affected by PCI IRQ routing tables at the
648	* same time SCI IRQ is shared in PCI sense hence this
649	* kludge (i.e. we fetch the hardwired value from ACPIs
650	* PCI device configuration space).
651	*/
652	ich9pciApicSetIrq(pBus, uDevFn, pPciDev, -1, iLevel, uTagSrc, PCIDevGetInterruptLine(pPciDev));
653	else
654	ich9pciApicSetIrq(pBus, uDevFn, pPciDev, iIrq, iLevel, uTagSrc, -1);
655	}
656	}
657
658
659	/**
660	* Memory mapped I/O Handler for write operations.
661	*
662	* Emulates writes to configuration space.
663	*
664	* @returns VBox status code.
665	*
666	* @param pDevIns The device instance.
667	* @param pvUser User argument.
668	* @param GCPhysAddr Physical address (in GC) where the read starts.
669	* @param pv Where to fetch the result.
670	* @param cb Number of bytes to write.
671	* @remarks Caller enters the device critical section.
672	*/
673	PDMBOTHCBDECL(int) ich9pciMcfgMMIOWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void const pv, unsigned cb)
674	{
675	PICH9PCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
676	uint32_t u32 = 0;
677	NOREF(pvUser);
678
679	Log2(("ich9pciMcfgMMIOWrite: %RGp(%d) \n", GCPhysAddr, cb));
680
681	PCI_LOCK(pDevIns, VINF_IOM_R3_MMIO_WRITE);
682
683	/* Decode target device and configuration space register */
684	PciAddress aDest;
685	ich9pciPhysToPciAddr(pGlobals, GCPhysAddr, &aDest);
686
687	switch (cb)
688	{
689	case 1:
690	u32 = (uint8_t)pv;
691	break;
692	case 2:
693	u32 = (uint16_t)pv;
694	break;
695	case 4:
696	u32 = (uint32_t)pv;
697	break;
698	default:
699	Assert(false);
700	break;
701	}
702
703	/* Perform configuration space write */
704	int rc = ich9pciDataWriteAddr(pGlobals, &aDest, u32, cb, VINF_IOM_R3_MMIO_WRITE);
705	PCI_UNLOCK(pDevIns);
706
707	return rc;
708	}
709
710
711	/**
712	* Memory mapped I/O Handler for read operations.
713	*
714	* Emulates reads from configuration space.
715	*
716	* @returns VBox status code.
717	*
718	* @param pDevIns The device instance.
719	* @param pvUser User argument.
720	* @param GCPhysAddr Physical address (in GC) where the read starts.
721	* @param pv Where to store the result.
722	* @param cb Number of bytes read.
723	* @remarks Caller enters the device critical section.
724	*/
725	PDMBOTHCBDECL(int) ich9pciMcfgMMIORead (PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb)
726	{
727	PICH9PCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
728	uint32_t rv;
729	NOREF(pvUser);
730
731	LogFlow(("ich9pciMcfgMMIORead: %RGp(%d) \n", GCPhysAddr, cb));
732
733	PCI_LOCK(pDevIns, VINF_IOM_R3_MMIO_READ);
734
735	/* Decode target device and configuration space register */
736	PciAddress aDest;
737	ich9pciPhysToPciAddr(pGlobals, GCPhysAddr, &aDest);
738
739	/* Perform configuration space read */
740	int rc = ich9pciDataReadAddr(pGlobals, &aDest, cb, &rv, VINF_IOM_R3_MMIO_READ);
741
742	if (RT_SUCCESS(rc))
743	{
744	switch (cb)
745	{
746	case 1:
747	(uint8_t)pv = (uint8_t)rv;
748	break;
749	case 2:
750	(uint16_t)pv = (uint16_t)rv;
751	break;
752	case 4:
753	(uint32_t)pv = (uint32_t)rv;
754	break;
755	default:
756	Assert(false);
757	break;
758	}
759	}
760	PCI_UNLOCK(pDevIns);
761
762	return rc;
763	}
764
765	#ifdef IN_RING3
766
767	DECLINLINE(PPCIDEVICE) ich9pciFindBridge(PICH9PCIBUS pBus, uint8_t iBus)
768	{
769	/* Search for a fitting bridge. */
770	for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
771	{
772	/*
773	* Examine secondary and subordinate bus number.
774	* If the target bus is in the range we pass the request on to the bridge.
775	*/
776	PPCIDEVICE pBridge = pBus->papBridgesR3[iBridge];
777	AssertMsg(pBridge && pciDevIsPci2PciBridge(pBridge),
778	("Device is not a PCI bridge but on the list of PCI bridges\n"));
779	uint32_t uSecondary = PCIDevGetByte(pBridge, VBOX_PCI_SECONDARY_BUS);
780	uint32_t uSubordinate = PCIDevGetByte(pBridge, VBOX_PCI_SUBORDINATE_BUS);
781	Log3(("ich9pciFindBridge on bus %p, bridge %d: %d in %d..%d\n", pBus, iBridge, iBus, uSecondary, uSubordinate));
782	if (iBus >= uSecondary && iBus <= uSubordinate)
783	return pBridge;
784	}
785
786	/* Nothing found. */
787	return NULL;
788	}
789
790	static uint32_t ich9pciGetCfg(PCIDevice* aDev, int32_t iRegister, int cb)
791	{
792	return aDev->Int.s.pfnConfigRead(aDev, iRegister, cb);
793	}
794
795	static uint8_t ich9pciGetByte(PCIDevice* aDev, int32_t iRegister)
796	{
797	return (uint8_t)ich9pciGetCfg(aDev, iRegister, 1);
798	}
799
800	static uint16_t ich9pciGetWord(PCIDevice* aDev, int32_t iRegister)
801	{
802	return (uint16_t)ich9pciGetCfg(aDev, iRegister, 2);
803	}
804
805	static uint32_t ich9pciGetDWord(PCIDevice* aDev, int32_t iRegister)
806	{
807	return (uint32_t)ich9pciGetCfg(aDev, iRegister, 4);
808	}
809
810	DECLINLINE(uint32_t) ich9pciGetRegionReg(int iRegion)
811	{
812	return (iRegion == VBOX_PCI_ROM_SLOT) ?
813	VBOX_PCI_ROM_ADDRESS : (VBOX_PCI_BASE_ADDRESS_0 + iRegion * 4);
814	}
815
816	#define INVALID_PCI_ADDRESS ~0U
817
818	static int ich9pciUnmapRegion(PPCIDEVICE pDev, int iRegion)
819	{
820	PCIIORegion* pRegion = &pDev->Int.s.aIORegions[iRegion];
821	int rc = VINF_SUCCESS;
822	PICH9PCIBUS pBus = pDev->Int.s.CTX_SUFF(pBus);
823
824	Assert (pRegion->size != 0);
825
826	if (pRegion->addr != INVALID_PCI_ADDRESS)
827	{
828	if (pRegion->type & PCI_ADDRESS_SPACE_IO)
829	{
830	/* Port IO */
831	rc = PDMDevHlpIOPortDeregister(pDev->pDevIns, pRegion->addr, pRegion->size);
832	AssertRC(rc);
833	}
834	else
835	{
836	RTGCPHYS GCPhysBase = pRegion->addr;
837	if (pBus->pPciHlpR3->pfnIsMMIO2Base(pBus->pDevInsR3, pDev->pDevIns, GCPhysBase))
838	{
839	/* unmap it. */
840	rc = pRegion->map_func(pDev, iRegion, NIL_RTGCPHYS, pRegion->size, (PCIADDRESSSPACE)(pRegion->type));
841	AssertRC(rc);
842	rc = PDMDevHlpMMIO2Unmap(pDev->pDevIns, iRegion, GCPhysBase);
843	}
844	else
845	rc = PDMDevHlpMMIODeregister(pDev->pDevIns, GCPhysBase, pRegion->size);
846	}
847
848	pRegion->addr = INVALID_PCI_ADDRESS;
849	}
850
851	return rc;
852	}
853
854	static void ich9pciUpdateMappings(PCIDevice* pDev)
855	{
856	uint64_t uLast, uNew;
857
858	int iCmd = ich9pciGetWord(pDev, VBOX_PCI_COMMAND);
859	for (int iRegion = 0; iRegion < PCI_NUM_REGIONS; iRegion++)
860	{
861	PCIIORegion* pRegion = &pDev->Int.s.aIORegions[iRegion];
862	uint32_t uConfigReg = ich9pciGetRegionReg(iRegion);
863	int64_t iRegionSize = pRegion->size;
864	int rc;
865
866	if (iRegionSize == 0)
867	continue;
868
869	bool f64Bit = (pRegion->type & PCI_ADDRESS_SPACE_BAR64) != 0;
870
871	if (pRegion->type & PCI_ADDRESS_SPACE_IO)
872	{
873	/* port IO region */
874	if (iCmd & PCI_COMMAND_IOACCESS)
875	{
876	/* IO access allowed */
877	uNew = ich9pciGetDWord(pDev, uConfigReg);
878	uNew &= ~(iRegionSize - 1);
879	uLast = uNew + iRegionSize - 1;
880	/* only 64K ioports on PC */
881	if (uLast <= uNew \|\| uNew == 0 \|\| uLast >= 0x10000)
882	uNew = INVALID_PCI_ADDRESS;
883	} else
884	uNew = INVALID_PCI_ADDRESS;
885	}
886	else
887	{
888	/* MMIO region */
889	if (iCmd & PCI_COMMAND_MEMACCESS)
890	{
891	uNew = ich9pciGetDWord(pDev, uConfigReg);
892
893	if (f64Bit)
894	{
895	uNew \|= ((uint64_t)ich9pciGetDWord(pDev, uConfigReg+4)) << 32;
896	/** @todo r=klaus Is this really true? Needs to be fixed properly. */
897	if (uNew > UINT64_C(0x0000010000000000))
898	{
899	/* Workaround for REM being unhapping with mapping very long 64-bit addresses */
900	LogRel(("Ignoring too long 64-bit BAR: %llx\n", uNew));
901	uNew = INVALID_PCI_ADDRESS;
902	}
903	}
904
905	/* the ROM slot has a specific enable bit */
906	if (iRegion == PCI_ROM_SLOT && !(uNew & 1))
907	uNew = INVALID_PCI_ADDRESS;
908	else
909	{
910	uNew &= ~(iRegionSize - 1);
911	uLast = uNew + iRegionSize - 1;
912	/* NOTE: we do not support wrapping */
913	/* XXX: as we cannot support really dynamic
914	mappings, we handle specific values as invalid
915	mappings. */
916	/* Unconditionally exclude I/O-APIC/HPET/ROM. Pessimistic, but better than causing a mess. */
917	if (uLast <= uNew \|\| uNew == 0 \|\| (uNew <= UINT32_C(0xffffffff) && uLast >= UINT32_C(0xfec00000)))
918	uNew = INVALID_PCI_ADDRESS;
919	}
920	} else
921	uNew = INVALID_PCI_ADDRESS;
922	}
923	LogRel2(("PCI: config dev %u/%u BAR%i uOld=%#018llx uNew=%#018llx size=%llu\n", pDev->devfn >> 3, pDev->devfn & 7, iRegion, pRegion->addr, uNew, pRegion->size));
924	/* now do the real mapping */
925	if (uNew != pRegion->addr)
926	{
927	if (pRegion->addr != INVALID_PCI_ADDRESS)
928	ich9pciUnmapRegion(pDev, iRegion);
929
930	pRegion->addr = uNew;
931	if (pRegion->addr != INVALID_PCI_ADDRESS)
932	{
933
934	/* finally, map the region */
935	rc = pRegion->map_func(pDev, iRegion,
936	pRegion->addr, pRegion->size,
937	(PCIADDRESSSPACE)(pRegion->type));
938	AssertRC(rc);
939	}
940	}
941
942	if (f64Bit)
943	iRegion++;
944	}
945	}
946
947	static DECLCALLBACK(int) ich9pciRegister(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, const char *pszName, int iDev)
948	{
949	PICH9PCIBUS pBus = DEVINS_2_PCIBUS(pDevIns);
950
951	/*
952	* Check input.
953	*/
954	if ( !pszName
955	\|\| !pPciDev
956	\|\| iDev >= (int)RT_ELEMENTS(pBus->apDevices)
957	)
958	{
959	AssertMsgFailed(("Invalid argument! pszName=%s pPciDev=%p iDev=%d\n", pszName, pPciDev, iDev));
960	return VERR_INVALID_PARAMETER;
961	}
962
963	/*
964	* Register the device.
965	*/
966	return ich9pciRegisterInternal(pBus, iDev, pPciDev, pszName);
967	}
968
969
970	static DECLCALLBACK(int) ich9pciRegisterMsi(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PPDMMSIREG pMsiReg)
971	{
972	NOREF(pDevIns);
973	int rc;
974
975	rc = MsiInit(pPciDev, pMsiReg);
976	if (RT_FAILURE(rc))
977	return rc;
978
979	rc = MsixInit(pPciDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pPciHlp), pPciDev, pMsiReg);
980	if (RT_FAILURE(rc))
981	return rc;
982
983	return VINF_SUCCESS;
984	}
985
986
987	static DECLCALLBACK(int) ich9pcibridgeRegister(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, const char *pszName, int iDev)
988	{
989
990	PICH9PCIBUS pBus = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
991
992	/*
993	* Check input.
994	*/
995	if ( !pszName
996	\|\| !pPciDev
997	\|\| iDev >= (int)RT_ELEMENTS(pBus->apDevices))
998	{
999	AssertMsgFailed(("Invalid argument! pszName=%s pPciDev=%p iDev=%d\n", pszName, pPciDev, iDev));
1000	return VERR_INVALID_PARAMETER;
1001	}
1002
1003	/*
1004	* Register the device.
1005	*/
1006	return ich9pciRegisterInternal(pBus, iDev, pPciDev, pszName);
1007	}
1008
1009	static DECLCALLBACK(int) ich9pciIORegionRegister(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iRegion, uint32_t cbRegion, PCIADDRESSSPACE enmType, PFNPCIIOREGIONMAP pfnCallback)
1010	{
1011	NOREF(pDevIns);
1012
1013	/*
1014	* Validate.
1015	*/
1016	AssertMsgReturn( enmType == (PCI_ADDRESS_SPACE_MEM \| PCI_ADDRESS_SPACE_BAR32)
1017	\|\| enmType == (PCI_ADDRESS_SPACE_MEM_PREFETCH \| PCI_ADDRESS_SPACE_BAR32)
1018	\|\| enmType == (PCI_ADDRESS_SPACE_MEM \| PCI_ADDRESS_SPACE_BAR64)
1019	\|\| enmType == (PCI_ADDRESS_SPACE_MEM_PREFETCH \| PCI_ADDRESS_SPACE_BAR64)
1020	\|\| enmType == PCI_ADDRESS_SPACE_IO
1021	,
1022	("Invalid enmType=%#x? Or was this a bitmask after all...\n", enmType),
1023	VERR_INVALID_PARAMETER);
1024	AssertMsgReturn((unsigned)iRegion < PCI_NUM_REGIONS,
1025	("Invalid iRegion=%d PCI_NUM_REGIONS=%d\n", iRegion, PCI_NUM_REGIONS),
1026	VERR_INVALID_PARAMETER);
1027	int iLastSet = ASMBitLastSetU32(cbRegion);
1028	AssertMsgReturn( iLastSet != 0
1029	&& RT_BIT_32(iLastSet - 1) == cbRegion,
1030	("Invalid cbRegion=%#x iLastSet=%#x (not a power of 2 or 0)\n", cbRegion, iLastSet),
1031	VERR_INVALID_PARAMETER);
1032
1033	Log(("ich9pciIORegionRegister: %s region %d size %d type %x\n",
1034	pPciDev->name, iRegion, cbRegion, enmType));
1035
1036	/* Make sure that we haven't marked this region as continuation of 64-bit region. */
1037	Assert(pPciDev->Int.s.aIORegions[iRegion].type != 0xff);
1038
1039	/*
1040	* Register the I/O region.
1041	*/
1042	PPCIIOREGION pRegion = &pPciDev->Int.s.aIORegions[iRegion];
1043	pRegion->addr = INVALID_PCI_ADDRESS;
1044	pRegion->size = cbRegion;
1045	pRegion->type = enmType;
1046	pRegion->map_func = pfnCallback;
1047
1048	if ((enmType & PCI_ADDRESS_SPACE_BAR64) != 0)
1049	{
1050	AssertMsgReturn(iRegion < 4,
1051	("Region %d cannot be 64-bit\n", iRegion),
1052	VERR_INVALID_PARAMETER);
1053	/* Mark next region as continuation of this one. */
1054	pPciDev->Int.s.aIORegions[iRegion+1].type = 0xff;
1055	}
1056
1057	/* Set type in the PCI config space. */
1058	uint32_t u32Value = ((uint32_t)enmType) & (PCI_ADDRESS_SPACE_IO \| PCI_ADDRESS_SPACE_BAR64 \| PCI_ADDRESS_SPACE_MEM_PREFETCH);
1059	PCIDevSetDWord(pPciDev, ich9pciGetRegionReg(iRegion), u32Value);
1060
1061	return VINF_SUCCESS;
1062	}
1063
1064	static DECLCALLBACK(void) ich9pciSetConfigCallbacks(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PFNPCICONFIGREAD pfnRead, PPFNPCICONFIGREAD ppfnReadOld,
1065	PFNPCICONFIGWRITE pfnWrite, PPFNPCICONFIGWRITE ppfnWriteOld)
1066	{
1067	NOREF(pDevIns);
1068
1069	if (ppfnReadOld)
1070	*ppfnReadOld = pPciDev->Int.s.pfnConfigRead;
1071	pPciDev->Int.s.pfnConfigRead = pfnRead;
1072
1073	if (ppfnWriteOld)
1074	*ppfnWriteOld = pPciDev->Int.s.pfnConfigWrite;
1075	pPciDev->Int.s.pfnConfigWrite = pfnWrite;
1076	}
1077
1078	static int ich9pciR3CommonSaveExec(PICH9PCIBUS pBus, PSSMHANDLE pSSM)
1079	{
1080	/*
1081	* Iterate thru all the devices.
1082	*/
1083	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
1084	{
1085	PPCIDEVICE pDev = pBus->apDevices[i];
1086	if (pDev)
1087	{
1088	/* Device position */
1089	SSMR3PutU32(pSSM, i);
1090	/* PCI config registers */
1091	SSMR3PutMem(pSSM, pDev->config, sizeof(pDev->config));
1092
1093	/* Device flags */
1094	int rc = SSMR3PutU32(pSSM, pDev->Int.s.fFlags);
1095	if (RT_FAILURE(rc))
1096	return rc;
1097
1098	/* IRQ pin state */
1099	rc = SSMR3PutS32(pSSM, pDev->Int.s.uIrqPinState);
1100	if (RT_FAILURE(rc))
1101	return rc;
1102
1103	/* MSI info */
1104	rc = SSMR3PutU8(pSSM, pDev->Int.s.u8MsiCapOffset);
1105	if (RT_FAILURE(rc))
1106	return rc;
1107	rc = SSMR3PutU8(pSSM, pDev->Int.s.u8MsiCapSize);
1108	if (RT_FAILURE(rc))
1109	return rc;
1110
1111	/* MSI-X info */
1112	rc = SSMR3PutU8(pSSM, pDev->Int.s.u8MsixCapOffset);
1113	if (RT_FAILURE(rc))
1114	return rc;
1115	rc = SSMR3PutU8(pSSM, pDev->Int.s.u8MsixCapSize);
1116	if (RT_FAILURE(rc))
1117	return rc;
1118	/* Save MSI-X page state */
1119	if (pDev->Int.s.u8MsixCapOffset != 0)
1120	{
1121	Assert(pDev->Int.s.pMsixPageR3 != NULL);
1122	SSMR3PutMem(pSSM, pDev->Int.s.pMsixPageR3, 0x1000);
1123	if (RT_FAILURE(rc))
1124	return rc;
1125	}
1126	}
1127	}
1128	return SSMR3PutU32(pSSM, UINT32_MAX); /* terminator */
1129	}
1130
1131	static DECLCALLBACK(int) ich9pciR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
1132	{
1133	PICH9PCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
1134
1135	/*
1136	* Bus state data.
1137	*/
1138	SSMR3PutU32(pSSM, pThis->uConfigReg);
1139
1140	/*
1141	* Save IRQ states.
1142	*/
1143	for (int i = 0; i < PCI_APIC_IRQ_PINS; i++)
1144	SSMR3PutU32(pSSM, pThis->uaPciApicIrqLevels[i]);
1145
1146	SSMR3PutU32(pSSM, ~0); /* separator */
1147
1148	return ich9pciR3CommonSaveExec(&pThis->aPciBus, pSSM);
1149	}
1150
1151
1152	static DECLCALLBACK(int) ich9pcibridgeR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
1153	{
1154	PICH9PCIBUS pThis = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
1155	return ich9pciR3CommonSaveExec(pThis, pSSM);
1156	}
1157
1158
1159	static DECLCALLBACK(void) ich9pcibridgeConfigWrite(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice, uint32_t u32Address, uint32_t u32Value, unsigned cb)
1160	{
1161	PICH9PCIBUS pBus = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
1162
1163	LogFlowFunc((": pDevIns=%p iBus=%d iDevice=%d u32Address=%u u32Value=%u cb=%d\n", pDevIns, iBus, iDevice, u32Address, u32Value, cb));
1164
1165	/* If the current bus is not the target bus search for the bus which contains the device. */
1166	if (iBus != PCIDevGetByte(&pBus->aPciDev, VBOX_PCI_SECONDARY_BUS))
1167	{
1168	PPCIDEVICE pBridgeDevice = ich9pciFindBridge(pBus, iBus);
1169	if (pBridgeDevice)
1170	{
1171	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigWrite);
1172	pBridgeDevice->Int.s.pfnBridgeConfigWrite(pBridgeDevice->pDevIns, iBus, iDevice, u32Address, u32Value, cb);
1173	}
1174	}
1175	else
1176	{
1177	/* This is the target bus, pass the write to the device. */
1178	PPCIDEVICE pPciDev = pBus->apDevices[iDevice];
1179	if (pPciDev)
1180	{
1181	Log(("%s: %s: addr=%02x val=%08x len=%d\n", __FUNCTION__, pPciDev->name, u32Address, u32Value, cb));
1182	pPciDev->Int.s.pfnConfigWrite(pPciDev, u32Address, u32Value, cb);
1183	}
1184	}
1185	}
1186
1187	static DECLCALLBACK(uint32_t) ich9pcibridgeConfigRead(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice, uint32_t u32Address, unsigned cb)
1188	{
1189	PICH9PCIBUS pBus = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
1190	uint32_t u32Value;
1191
1192	LogFlowFunc((": pDevIns=%p iBus=%d iDevice=%d u32Address=%u cb=%d\n", pDevIns, iBus, iDevice, u32Address, cb));
1193
1194	/* If the current bus is not the target bus search for the bus which contains the device. */
1195	if (iBus != PCIDevGetByte(&pBus->aPciDev, VBOX_PCI_SECONDARY_BUS))
1196	{
1197	PPCIDEVICE pBridgeDevice = ich9pciFindBridge(pBus, iBus);
1198	if (pBridgeDevice)
1199	{
1200	AssertPtr( pBridgeDevice->Int.s.pfnBridgeConfigRead);
1201	u32Value = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->pDevIns, iBus, iDevice, u32Address, cb);
1202	}
1203	else
1204	ich9pciNoMem(&u32Value, 4);
1205	}
1206	else
1207	{
1208	/* This is the target bus, pass the read to the device. */
1209	PPCIDEVICE pPciDev = pBus->apDevices[iDevice];
1210	if (pPciDev)
1211	{
1212	u32Value = pPciDev->Int.s.pfnConfigRead(pPciDev, u32Address, cb);
1213	Log(("%s: %s: u32Address=%02x u32Value=%08x cb=%d\n", __FUNCTION__, pPciDev->name, u32Address, u32Value, cb));
1214	}
1215	else
1216	ich9pciNoMem(&u32Value, 4);
1217	}
1218
1219	return u32Value;
1220	}
1221
1222
1223	/**
1224	* Common routine for restoring the config registers of a PCI device.
1225	*
1226	* @param pDev The PCI device.
1227	* @param pbSrcConfig The configuration register values to be loaded.
1228	* @param fIsBridge Whether this is a bridge device or not.
1229	*/
1230	static void pciR3CommonRestoreConfig(PPCIDEVICE pDev, uint8_t const *pbSrcConfig, bool fIsBridge)
1231	{
1232	/*
1233	* This table defines the fields for normal devices and bridge devices, and
1234	* the order in which they need to be restored.
1235	*/
1236	static const struct PciField
1237	{
1238	uint8_t off;
1239	uint8_t cb;
1240	uint8_t fWritable;
1241	uint8_t fBridge;
1242	const char *pszName;
1243	} s_aFields[] =
1244	{
1245	/* off,cb,fW,fB, pszName */
1246	{ 0x00, 2, 0, 3, "VENDOR_ID" },
1247	{ 0x02, 2, 0, 3, "DEVICE_ID" },
1248	{ 0x06, 2, 1, 3, "STATUS" },
1249	{ 0x08, 1, 0, 3, "REVISION_ID" },
1250	{ 0x09, 1, 0, 3, "CLASS_PROG" },
1251	{ 0x0a, 1, 0, 3, "CLASS_SUB" },
1252	{ 0x0b, 1, 0, 3, "CLASS_BASE" },
1253	{ 0x0c, 1, 1, 3, "CACHE_LINE_SIZE" },
1254	{ 0x0d, 1, 1, 3, "LATENCY_TIMER" },
1255	{ 0x0e, 1, 0, 3, "HEADER_TYPE" },
1256	{ 0x0f, 1, 1, 3, "BIST" },
1257	{ 0x10, 4, 1, 3, "BASE_ADDRESS_0" },
1258	{ 0x14, 4, 1, 3, "BASE_ADDRESS_1" },
1259	{ 0x18, 4, 1, 1, "BASE_ADDRESS_2" },
1260	{ 0x18, 1, 1, 2, "PRIMARY_BUS" }, // fWritable = ??
1261	{ 0x19, 1, 1, 2, "SECONDARY_BUS" }, // fWritable = ??
1262	{ 0x1a, 1, 1, 2, "SUBORDINATE_BUS" }, // fWritable = ??
1263	{ 0x1b, 1, 1, 2, "SEC_LATENCY_TIMER" }, // fWritable = ??
1264	{ 0x1c, 4, 1, 1, "BASE_ADDRESS_3" },
1265	{ 0x1c, 1, 1, 2, "IO_BASE" }, // fWritable = ??
1266	{ 0x1d, 1, 1, 2, "IO_LIMIT" }, // fWritable = ??
1267	{ 0x1e, 2, 1, 2, "SEC_STATUS" }, // fWritable = ??
1268	{ 0x20, 4, 1, 1, "BASE_ADDRESS_4" },
1269	{ 0x20, 2, 1, 2, "MEMORY_BASE" }, // fWritable = ??
1270	{ 0x22, 2, 1, 2, "MEMORY_LIMIT" }, // fWritable = ??
1271	{ 0x24, 4, 1, 1, "BASE_ADDRESS_5" },
1272	{ 0x24, 2, 1, 2, "PREF_MEMORY_BASE" }, // fWritable = ??
1273	{ 0x26, 2, 1, 2, "PREF_MEMORY_LIMIT" }, // fWritable = ??
1274	{ 0x28, 4, 1, 1, "CARDBUS_CIS" }, // fWritable = ??
1275	{ 0x28, 4, 1, 2, "PREF_BASE_UPPER32" }, // fWritable = ??
1276	{ 0x2c, 2, 0, 1, "SUBSYSTEM_VENDOR_ID" },// fWritable = !?
1277	{ 0x2c, 4, 1, 2, "PREF_LIMIT_UPPER32" },// fWritable = ??
1278	{ 0x2e, 2, 0, 1, "SUBSYSTEM_ID" }, // fWritable = !?
1279	{ 0x30, 4, 1, 1, "ROM_ADDRESS" }, // fWritable = ?!
1280	{ 0x30, 2, 1, 2, "IO_BASE_UPPER16" }, // fWritable = ?!
1281	{ 0x32, 2, 1, 2, "IO_LIMIT_UPPER16" }, // fWritable = ?!
1282	{ 0x34, 4, 0, 3, "CAPABILITY_LIST" }, // fWritable = !? cb=!?
1283	{ 0x38, 4, 1, 1, "RESERVED_38" }, // ???
1284	{ 0x38, 4, 1, 2, "ROM_ADDRESS_BR" }, // fWritable = !? cb=!? fBridge=!?
1285	{ 0x3c, 1, 1, 3, "INTERRUPT_LINE" }, // fBridge=??
1286	{ 0x3d, 1, 0, 3, "INTERRUPT_PIN" }, // fBridge=??
1287	{ 0x3e, 1, 0, 1, "MIN_GNT" },
1288	{ 0x3e, 2, 1, 2, "BRIDGE_CONTROL" }, // fWritable = !?
1289	{ 0x3f, 1, 0, 1, "MAX_LAT" },
1290	/* The COMMAND register must come last as it requires the ADDRESS
1291	registers to be restored before we pretent to change it from 0 to
1292	whatever value the guest assigned it. */
1293	{ 0x04, 2, 1, 3, "COMMAND" },
1294	};
1295
1296	#ifdef RT_STRICT
1297	/* Check that we've got full register coverage. */
1298	uint32_t bmDevice[0x40 / 32];
1299	uint32_t bmBridge[0x40 / 32];
1300	RT_ZERO(bmDevice);
1301	RT_ZERO(bmBridge);
1302	for (uint32_t i = 0; i < RT_ELEMENTS(s_aFields); i++)
1303	{
1304	uint8_t off = s_aFields[i].off;
1305	uint8_t cb = s_aFields[i].cb;
1306	uint8_t f = s_aFields[i].fBridge;
1307	while (cb-- > 0)
1308	{
1309	if (f & 1) AssertMsg(!ASMBitTest(bmDevice, off), ("%#x\n", off));
1310	if (f & 2) AssertMsg(!ASMBitTest(bmBridge, off), ("%#x\n", off));
1311	if (f & 1) ASMBitSet(bmDevice, off);
1312	if (f & 2) ASMBitSet(bmBridge, off);
1313	off++;
1314	}
1315	}
1316	for (uint32_t off = 0; off < 0x40; off++)
1317	{
1318	AssertMsg(ASMBitTest(bmDevice, off), ("%#x\n", off));
1319	AssertMsg(ASMBitTest(bmBridge, off), ("%#x\n", off));
1320	}
1321	#endif
1322
1323	/*
1324	* Loop thru the fields covering the 64 bytes of standard registers.
1325	*/
1326	uint8_t const fBridge = fIsBridge ? 2 : 1;
1327	Assert(!pciDevIsPassthrough(pDev));
1328	uint8_t *pbDstConfig = &pDev->config[0];
1329
1330	for (uint32_t i = 0; i < RT_ELEMENTS(s_aFields); i++)
1331	if (s_aFields[i].fBridge & fBridge)
1332	{
1333	uint8_t const off = s_aFields[i].off;
1334	uint8_t const cb = s_aFields[i].cb;
1335	uint32_t u32Src;
1336	uint32_t u32Dst;
1337	switch (cb)
1338	{
1339	case 1:
1340	u32Src = pbSrcConfig[off];
1341	u32Dst = pbDstConfig[off];
1342	break;
1343	case 2:
1344	u32Src = (uint16_t const )&pbSrcConfig[off];
1345	u32Dst = (uint16_t const )&pbDstConfig[off];
1346	break;
1347	case 4:
1348	u32Src = (uint32_t const )&pbSrcConfig[off];
1349	u32Dst = (uint32_t const )&pbDstConfig[off];
1350	break;
1351	default:
1352	AssertFailed();
1353	continue;
1354	}
1355
1356	if ( u32Src != u32Dst
1357	\|\| off == VBOX_PCI_COMMAND)
1358	{
1359	if (u32Src != u32Dst)
1360	{
1361	if (!s_aFields[i].fWritable)
1362	LogRel(("PCI: %8s/%u: %2u-bit field %s: %x -> %x - !READ ONLY!\n",
1363	pDev->name, pDev->pDevIns->iInstance, cb*8, s_aFields[i].pszName, u32Dst, u32Src));
1364	else
1365	LogRel(("PCI: %8s/%u: %2u-bit field %s: %x -> %x\n",
1366	pDev->name, pDev->pDevIns->iInstance, cb*8, s_aFields[i].pszName, u32Dst, u32Src));
1367	}
1368	if (off == VBOX_PCI_COMMAND)
1369	PCIDevSetCommand(pDev, 0); /* For remapping, see ich9pciR3CommonLoadExec. */
1370	pDev->Int.s.pfnConfigWrite(pDev, off, u32Src, cb);
1371	}
1372	}
1373
1374	/*
1375	* The device dependent registers.
1376	*
1377	* We will not use ConfigWrite here as we have no clue about the size
1378	* of the registers, so the device is responsible for correctly
1379	* restoring functionality governed by these registers.
1380	*/
1381	for (uint32_t off = 0x40; off < sizeof(pDev->config); off++)
1382	if (pbDstConfig[off] != pbSrcConfig[off])
1383	{
1384	LogRel(("PCI: %8s/%u: register %02x: %02x -> %02x\n",
1385	pDev->name, pDev->pDevIns->iInstance, off, pbDstConfig[off], pbSrcConfig[off])); /** @todo make this Log() later. */
1386	pbDstConfig[off] = pbSrcConfig[off];
1387	}
1388	}
1389
1390	/**
1391	* Common worker for ich9pciR3LoadExec and ich9pcibridgeR3LoadExec.
1392	*
1393	* @returns VBox status code.
1394	* @param pBus The bus which data is being loaded.
1395	* @param pSSM The saved state handle.
1396	* @param uVersion The data version.
1397	* @param uPass The pass.
1398	*/
1399	static DECLCALLBACK(int) ich9pciR3CommonLoadExec(PICH9PCIBUS pBus, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1400	{
1401	uint32_t u32;
1402	uint32_t i;
1403	int rc;
1404
1405	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
1406	if (uVersion != VBOX_ICH9PCI_SAVED_STATE_VERSION_CURRENT)
1407	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1408
1409	/*
1410	* Iterate thru all the devices and write 0 to the COMMAND register so
1411	* that all the memory is unmapped before we start restoring the saved
1412	* mapping locations.
1413	*
1414	* The register value is restored afterwards so we can do proper
1415	* LogRels in pciR3CommonRestoreConfig.
1416	*/
1417	for (i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
1418	{
1419	PPCIDEVICE pDev = pBus->apDevices[i];
1420	if (pDev)
1421	{
1422	uint16_t u16 = PCIDevGetCommand(pDev);
1423	pDev->Int.s.pfnConfigWrite(pDev, VBOX_PCI_COMMAND, 0, 2);
1424	PCIDevSetCommand(pDev, u16);
1425	Assert(PCIDevGetCommand(pDev) == u16);
1426	}
1427	}
1428
1429	void *pvMsixPage = RTMemTmpAllocZ(0x1000);
1430	AssertReturn(pvMsixPage, VERR_NO_TMP_MEMORY);
1431
1432	/*
1433	* Iterate all the devices.
1434	*/
1435	for (i = 0;; i++)
1436	{
1437	PPCIDEVICE pDev;
1438	PCIDEVICE DevTmp;
1439
1440	/* index / terminator */
1441	rc = SSMR3GetU32(pSSM, &u32);
1442	if (RT_FAILURE(rc))
1443	break;
1444	if (u32 == (uint32_t)~0)
1445	break;
1446	AssertMsgBreak(u32 < RT_ELEMENTS(pBus->apDevices) && u32 >= i, ("u32=%#x i=%#x\n", u32, i));
1447
1448	/* skip forward to the device checking that no new devices are present. */
1449	for (; i < u32; i++)
1450	{
1451	pDev = pBus->apDevices[i];
1452	if (pDev)
1453	{
1454	LogRel(("PCI: New device in slot %#x, %s (vendor=%#06x device=%#06x)\n", i, pDev->name,
1455	PCIDevGetVendorId(pDev), PCIDevGetDeviceId(pDev)));
1456	if (SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT)
1457	{
1458	rc = SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("New device in slot %#x, %s (vendor=%#06x device=%#06x)"),
1459	i, pDev->name, PCIDevGetVendorId(pDev), PCIDevGetDeviceId(pDev));
1460	break;
1461	}
1462	}
1463	}
1464	if (RT_FAILURE(rc))
1465	break;
1466
1467	/* get the data */
1468	DevTmp.Int.s.fFlags = 0;
1469	DevTmp.Int.s.u8MsiCapOffset = 0;
1470	DevTmp.Int.s.u8MsiCapSize = 0;
1471	DevTmp.Int.s.u8MsixCapOffset = 0;
1472	DevTmp.Int.s.u8MsixCapSize = 0;
1473	DevTmp.Int.s.uIrqPinState = ~0; /* Invalid value in case we have an older saved state to force a state change in pciSetIrq. */
1474	SSMR3GetMem(pSSM, DevTmp.config, sizeof(DevTmp.config));
1475
1476	SSMR3GetU32(pSSM, &DevTmp.Int.s.fFlags);
1477	SSMR3GetS32(pSSM, &DevTmp.Int.s.uIrqPinState);
1478	SSMR3GetU8(pSSM, &DevTmp.Int.s.u8MsiCapOffset);
1479	SSMR3GetU8(pSSM, &DevTmp.Int.s.u8MsiCapSize);
1480	SSMR3GetU8(pSSM, &DevTmp.Int.s.u8MsixCapOffset);
1481	rc = SSMR3GetU8(pSSM, &DevTmp.Int.s.u8MsixCapSize);
1482	if (RT_FAILURE(rc))
1483	break;
1484
1485	/* Load MSI-X page state */
1486	if (DevTmp.Int.s.u8MsixCapOffset != 0)
1487	{
1488	Assert(pvMsixPage != NULL);
1489	rc = SSMR3GetMem(pSSM, pvMsixPage, 0x1000);
1490	if (RT_FAILURE(rc))
1491	break;
1492	}
1493
1494	/* check that it's still around. */
1495	pDev = pBus->apDevices[i];
1496	if (!pDev)
1497	{
1498	LogRel(("PCI: Device in slot %#x has been removed! vendor=%#06x device=%#06x\n", i,
1499	PCIDevGetVendorId(&DevTmp), PCIDevGetDeviceId(&DevTmp)));
1500	if (SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT)
1501	{
1502	rc = SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Device in slot %#x has been removed! vendor=%#06x device=%#06x"),
1503	i, PCIDevGetVendorId(&DevTmp), PCIDevGetDeviceId(&DevTmp));
1504	break;
1505	}
1506	continue;
1507	}
1508
1509	/* match the vendor id assuming that this will never be changed. */
1510	if (PCIDevGetVendorId(&DevTmp) != PCIDevGetVendorId(pDev))
1511	{
1512	rc = SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Device in slot %#x (%s) vendor id mismatch! saved=%.4Rhxs current=%.4Rhxs"),
1513	i, pDev->name, PCIDevGetVendorId(&DevTmp), PCIDevGetVendorId(pDev));
1514	break;
1515	}
1516
1517	/* commit the loaded device config. */
1518	Assert(!pciDevIsPassthrough(pDev));
1519	pciR3CommonRestoreConfig(pDev, &DevTmp.config[0], false ); /** @todo fix bridge fun! */
1520
1521	pDev->Int.s.uIrqPinState = DevTmp.Int.s.uIrqPinState;
1522	pDev->Int.s.u8MsiCapOffset = DevTmp.Int.s.u8MsiCapOffset;
1523	pDev->Int.s.u8MsiCapSize = DevTmp.Int.s.u8MsiCapSize;
1524	pDev->Int.s.u8MsixCapOffset = DevTmp.Int.s.u8MsixCapOffset;
1525	pDev->Int.s.u8MsixCapSize = DevTmp.Int.s.u8MsixCapSize;
1526	if (DevTmp.Int.s.u8MsixCapSize != 0)
1527	{
1528	Assert(pDev->Int.s.pMsixPageR3 != NULL);
1529	memcpy(pDev->Int.s.pMsixPageR3, pvMsixPage, 0x1000);
1530	}
1531	}
1532
1533	RTMemTmpFree(pvMsixPage);
1534
1535	return rc;
1536	}
1537
1538	static DECLCALLBACK(int) ich9pciR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1539	{
1540	PICH9PCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
1541	PICH9PCIBUS pBus = &pThis->aPciBus;
1542	uint32_t u32;
1543	int rc;
1544
1545	/* We ignore this version as there's no saved state with it anyway */
1546	if (uVersion == VBOX_ICH9PCI_SAVED_STATE_VERSION_NOMSI)
1547	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1548	if (uVersion > VBOX_ICH9PCI_SAVED_STATE_VERSION_MSI)
1549	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1550
1551	/*
1552	* Bus state data.
1553	*/
1554	SSMR3GetU32(pSSM, &pThis->uConfigReg);
1555
1556	/*
1557	* Load IRQ states.
1558	*/
1559	for (int i = 0; i < PCI_APIC_IRQ_PINS; i++)
1560	SSMR3GetU32(pSSM, (uint32_t*)&pThis->uaPciApicIrqLevels[i]);
1561
1562	/* separator */
1563	rc = SSMR3GetU32(pSSM, &u32);
1564	if (RT_FAILURE(rc))
1565	return rc;
1566	if (u32 != (uint32_t)~0)
1567	AssertMsgFailedReturn(("u32=%#x\n", u32), rc);
1568
1569	return ich9pciR3CommonLoadExec(pBus, pSSM, uVersion, uPass);
1570	}
1571
1572	static DECLCALLBACK(int) ich9pcibridgeR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1573	{
1574	PICH9PCIBUS pThis = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
1575	if (uVersion > VBOX_ICH9PCI_SAVED_STATE_VERSION_MSI)
1576	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1577	return ich9pciR3CommonLoadExec(pThis, pSSM, uVersion, uPass);
1578	}
1579
1580
1581	/*
1582	* Perform imeediate read of configuration space register.
1583	* Cannot be rescheduled, as already in R3.
1584	*/
1585	static uint32_t ich9pciConfigRead(PICH9PCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t len)
1586	{
1587	PciAddress aPciAddr;
1588	aPciAddr.iBus = uBus;
1589	aPciAddr.iDeviceFunc = uDevFn;
1590	aPciAddr.iRegister = addr;
1591
1592	uint32_t u32Val;
1593	int rc = ich9pciDataReadAddr(pGlobals, &aPciAddr, len, &u32Val, VERR_INTERNAL_ERROR);
1594	AssertRC(rc);
1595
1596	return u32Val;
1597	}
1598
1599
1600	/*
1601	* Perform imeediate write to configuration space register.
1602	* Cannot be rescheduled, as already in R3.
1603	*/
1604	static void ich9pciConfigWrite(PICH9PCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t val, uint32_t len)
1605	{
1606	PciAddress aPciAddr;
1607	aPciAddr.iBus = uBus;
1608	aPciAddr.iDeviceFunc = uDevFn;
1609	aPciAddr.iRegister = addr;
1610
1611	int rc = ich9pciDataWriteAddr(pGlobals, &aPciAddr, val, len, VERR_INTERNAL_ERROR);
1612	AssertRC(rc);
1613	}
1614
1615
1616	static void ich9pciSetRegionAddress(PICH9PCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, int iRegion, uint64_t addr)
1617	{
1618	uint32_t uReg = ich9pciGetRegionReg(iRegion);
1619
1620	/* Read memory type first. */
1621	uint8_t uResourceType = ich9pciConfigRead(pGlobals, uBus, uDevFn, uReg, 1);
1622
1623	Log(("Set region address: %02x:%02x.%d region %d address=%lld\n",
1624	uBus, uDevFn >> 3, uDevFn & 7, iRegion, addr));
1625
1626	bool f64Bit = (uResourceType & PCI_ADDRESS_SPACE_BAR64) != 0;
1627
1628	/* Write address of the device. */
1629	ich9pciConfigWrite(pGlobals, uBus, uDevFn, uReg, (uint32_t)addr, 4);
1630	if (f64Bit)
1631	ich9pciConfigWrite(pGlobals, uBus, uDevFn, uReg + 4, (uint32_t)(addr >> 32), 4);
1632	}
1633
1634
1635	static void ich9pciBiosInitBridge(PICH9PCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn)
1636	{
1637	Log(("BIOS init bridge: %02x::%02x.%d\n", uBus, uDevFn >> 3, uDevFn & 7));
1638
1639	/*
1640	* The I/O range for the bridge must be aligned to a 4KB boundary.
1641	* This does not change anything really as the access to the device is not going
1642	* through the bridge but we want to be compliant to the spec.
1643	*/
1644	if ((pGlobals->uPciBiosIo % 4096) != 0)
1645	{
1646	pGlobals->uPciBiosIo = RT_ALIGN_32(pGlobals->uPciBiosIo, 4*1024);
1647	Log(("%s: Aligned I/O start address. New address %#x\n", __FUNCTION__, pGlobals->uPciBiosIo));
1648	}
1649	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_IO_BASE, (pGlobals->uPciBiosIo >> 8) & 0xf0, 1);
1650
1651	/* The MMIO range for the bridge must be aligned to a 1MB boundary. */
1652	if ((pGlobals->uPciBiosMmio % (1024 * 1024)) != 0)
1653	{
1654	pGlobals->uPciBiosMmio = RT_ALIGN_32(pGlobals->uPciBiosMmio, 1024*1024);
1655	Log(("%s: Aligned MMIO start address. New address %#x\n", __FUNCTION__, pGlobals->uPciBiosMmio));
1656	}
1657	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_MEMORY_BASE, (pGlobals->uPciBiosMmio >> 16) & UINT32_C(0xffff0), 2);
1658
1659	/* Save values to compare later to. */
1660	uint32_t u32IoAddressBase = pGlobals->uPciBiosIo;
1661	uint32_t u32MMIOAddressBase = pGlobals->uPciBiosMmio;
1662	uint8_t uBridgeBus = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_SECONDARY_BUS, 1);
1663
1664	/* Init devices behind the bridge and possibly other bridges as well. */
1665	for (int iDev = 0; iDev <= 255; iDev++)
1666	ich9pciBiosInitDevice(pGlobals, uBridgeBus, iDev);
1667
1668	/*
1669	* Set I/O limit register. If there is no device with I/O space behind the bridge
1670	* we set a lower value than in the base register.
1671	* The result with a real bridge is that no I/O transactions are passed to the secondary
1672	* interface. Again this doesn't really matter here but we want to be compliant to the spec.
1673	*/
1674	if ((u32IoAddressBase != pGlobals->uPciBiosIo) && ((pGlobals->uPciBiosIo % 4096) != 0))
1675	{
1676	/* The upper boundary must be one byte less than a 4KB boundary. */
1677	pGlobals->uPciBiosIo = RT_ALIGN_32(pGlobals->uPciBiosIo, 4*1024);
1678	}
1679
1680	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_IO_LIMIT, ((pGlobals->uPciBiosIo >> 8) & 0xf0) - 1, 1);
1681
1682	/* Same with the MMIO limit register but with 1MB boundary here. */
1683	if ((u32MMIOAddressBase != pGlobals->uPciBiosMmio) && ((pGlobals->uPciBiosMmio % (1024 * 1024)) != 0))
1684	{
1685	/* The upper boundary must be one byte less than a 1MB boundary. */
1686	pGlobals->uPciBiosMmio = RT_ALIGN_32(pGlobals->uPciBiosMmio, 1024*1024);
1687	}
1688	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_MEMORY_LIMIT, ((pGlobals->uPciBiosMmio >> 16) & UINT32_C(0xfff0)) - 1, 2);
1689
1690	/*
1691	* Set the prefetch base and limit registers. We currently have no device with a prefetchable region
1692	* which may be behind a bridge. That's why it is unconditionally disabled here atm by writing a higher value into
1693	* the base register than in the limit register.
1694	*/
1695	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_MEMORY_BASE, 0xfff0, 2);
1696	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_MEMORY_LIMIT, 0x0, 2);
1697	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_BASE_UPPER32, 0x00, 4);
1698	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_LIMIT_UPPER32, 0x00, 4);
1699	}
1700
1701	static void ich9pciBiosInitDevice(PICH9PCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn)
1702	{
1703	uint16_t uDevClass, uVendor, uDevice;
1704	uint8_t uCmd;
1705
1706	uDevClass = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_CLASS_DEVICE, 2);
1707	uVendor = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_VENDOR_ID, 2);
1708	uDevice = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_DEVICE_ID, 2);
1709
1710	/* If device is present */
1711	if (uVendor == 0xffff)
1712	return;
1713
1714	Log(("BIOS init device: %02x:%02x.%d\n", uBus, uDevFn >> 3, uDevFn & 7));
1715
1716	switch (uDevClass)
1717	{
1718	case 0x0101:
1719	/* IDE controller */
1720	ich9pciConfigWrite(pGlobals, uBus, uDevFn, 0x40, 0x8000, 2); /* enable IDE0 */
1721	ich9pciConfigWrite(pGlobals, uBus, uDevFn, 0x42, 0x8000, 2); /* enable IDE1 */
1722	goto default_map;
1723	break;
1724	case 0x0300:
1725	/* VGA controller */
1726	if (uVendor != 0x80ee)
1727	goto default_map;
1728	/* VGA: map frame buffer to default Bochs VBE address */
1729	ich9pciSetRegionAddress(pGlobals, uBus, uDevFn, 0, 0xE0000000);
1730	/*
1731	* Legacy VGA I/O ports are implicitly decoded by a VGA class device. But
1732	* only the framebuffer (i.e., a memory region) is explicitly registered via
1733	* ich9pciSetRegionAddress, so don't forget to enable I/O decoding.
1734	*/
1735	uCmd = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_COMMAND, 1);
1736	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_COMMAND,
1737	uCmd \| PCI_COMMAND_IOACCESS \| PCI_COMMAND_MEMACCESS,
1738	1);
1739	break;
1740	case 0x0604:
1741	/* PCI-to-PCI bridge. */
1742	AssertMsg(pGlobals->uBus < 255, ("Too many bridges on the bus\n"));
1743	ich9pciBiosInitBridge(pGlobals, uBus, uDevFn);
1744	break;
1745	default:
1746	default_map:
1747	{
1748	/* default memory mappings */
1749	bool fActiveMemRegion = false;
1750	bool fActiveIORegion = false;
1751	/*
1752	* We ignore ROM region here.
1753	*/
1754	for (int iRegion = 0; iRegion < (PCI_NUM_REGIONS-1); iRegion++)
1755	{
1756	uint32_t u32Address = ich9pciGetRegionReg(iRegion);
1757
1758	/* Calculate size - we write all 1s into the BAR, and then evaluate which bits
1759	are cleared. */
1760	uint8_t u8ResourceType = ich9pciConfigRead(pGlobals, uBus, uDevFn, u32Address, 1);
1761
1762	bool f64bit = (u8ResourceType & PCI_ADDRESS_SPACE_BAR64) != 0;
1763	bool fIsPio = ((u8ResourceType & PCI_COMMAND_IOACCESS) == PCI_COMMAND_IOACCESS);
1764	uint64_t cbRegSize64 = 0;
1765
1766	if (f64bit)
1767	{
1768	ich9pciConfigWrite(pGlobals, uBus, uDevFn, u32Address, UINT32_C(0xffffffff), 4);
1769	ich9pciConfigWrite(pGlobals, uBus, uDevFn, u32Address+4, UINT32_C(0xffffffff), 4);
1770	cbRegSize64 = ich9pciConfigRead(pGlobals, uBus, uDevFn, u32Address, 4);
1771	cbRegSize64 \|= ((uint64_t)ich9pciConfigRead(pGlobals, uBus, uDevFn, u32Address+4, 4) << 32);
1772	cbRegSize64 &= ~UINT64_C(0x0f);
1773	cbRegSize64 = (~cbRegSize64) + 1;
1774
1775	/* No 64-bit PIO regions possible. */
1776	#ifndef DEBUG_bird /* EFI triggers this for DevAHCI. */
1777	AssertMsg((u8ResourceType & PCI_COMMAND_IOACCESS) == 0, ("type=%#x rgn=%d\n", u8ResourceType, iRegion));
1778	#endif
1779	}
1780	else
1781	{
1782	uint32_t cbRegSize32;
1783	ich9pciConfigWrite(pGlobals, uBus, uDevFn, u32Address, UINT32_C(0xffffffff), 4);
1784	cbRegSize32 = ich9pciConfigRead(pGlobals, uBus, uDevFn, u32Address, 4);
1785
1786	/* Clear resource information depending on resource type. */
1787	if (fIsPio) /* PIO */
1788	cbRegSize32 &= ~UINT32_C(0x01);
1789	else /* MMIO */
1790	cbRegSize32 &= ~UINT32_C(0x0f);
1791
1792	/*
1793	* Invert all bits and add 1 to get size of the region.
1794	* (From PCI implementation note)
1795	*/
1796	if (fIsPio && (cbRegSize32 & UINT32_C(0xffff0000)) == 0)
1797	cbRegSize32 = (~(cbRegSize32 \| UINT32_C(0xffff0000))) + 1;
1798	else
1799	cbRegSize32 = (~cbRegSize32) + 1;
1800
1801	cbRegSize64 = cbRegSize32;
1802	}
1803	#ifndef DEBUG_bird /* EFI triggers this for DevAHCI. */
1804	Assert(cbRegSize64 == (uint32_t)cbRegSize64);
1805	#endif
1806	Log2(("%s: Size of region %u for device %d on bus %d is %lld\n", __FUNCTION__, iRegion, uDevFn, uBus, cbRegSize64));
1807
1808	if (cbRegSize64)
1809	{
1810	/** @todo r=klaus make this code actually handle 64-bit BARs, especially MMIO which can't possibly fit into the memory hole. */
1811	uint32_t cbRegSize32 = (uint32_t)cbRegSize64;
1812	uint32_t* paddr = fIsPio ? &pGlobals->uPciBiosIo : &pGlobals->uPciBiosMmio;
1813	uint32_t uNew = *paddr;
1814	uNew = (uNew + cbRegSize32 - 1) & ~(cbRegSize32 - 1);
1815	if (fIsPio)
1816	uNew &= UINT32_C(0xffff);
1817	/* Unconditionally exclude I/O-APIC/HPET/ROM. Pessimistic, but better than causing a mess. */
1818	if (!uNew \|\| (uNew <= UINT32_C(0xffffffff) && uNew + cbRegSize32 - 1 >= UINT32_C(0xfec00000)))
1819	{
1820	LogRel(("PCI: no space left for BAR%u of device %u/%u/%u (vendor=%#06x device=%#06x)\n",
1821	iRegion, uBus, uDevFn >> 3, uDevFn & 7, uVendor, uDevice)); /** @todo make this a VM start failure later. */
1822	/* Undo the mapping mess caused by the size probing. */
1823	ich9pciConfigWrite(pGlobals, uBus, uDevFn, u32Address, UINT32_C(0), 4);
1824	if (f64bit)
1825	ich9pciConfigWrite(pGlobals, uBus, uDevFn, u32Address+4, UINT32_C(0), 4);
1826	}
1827	else
1828	{
1829	Log(("%s: Start address of %s region %u is %#x\n", __FUNCTION__, (fIsPio ? "I/O" : "MMIO"), iRegion, uNew));
1830	ich9pciSetRegionAddress(pGlobals, uBus, uDevFn, iRegion, uNew);
1831	if (fIsPio)
1832	fActiveIORegion = true;
1833	else
1834	fActiveMemRegion = true;
1835	*paddr = uNew + cbRegSize32;
1836	Log2(("%s: New address is %#x\n", __FUNCTION__, *paddr));
1837	}
1838
1839	if (f64bit)
1840	iRegion++; /* skip next region */
1841	}
1842	}
1843
1844	/* Update the command word appropriately. */
1845	uCmd = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_COMMAND, 2);
1846	if (fActiveMemRegion)
1847	uCmd \|= PCI_COMMAND_MEMACCESS; /* Enable MMIO access. */
1848	if (fActiveIORegion)
1849	uCmd \|= PCI_COMMAND_IOACCESS; /* Enable I/O space access. */
1850	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_COMMAND, uCmd, 2);
1851	break;
1852	}
1853	}
1854
1855	/* map the interrupt */
1856	uint32_t iPin = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_INTERRUPT_PIN, 1);
1857	if (iPin != 0)
1858	{
1859	iPin--;
1860
1861	if (uBus != 0)
1862	{
1863	/* Find bus this device attached to. */
1864	PICH9PCIBUS pBus = &pGlobals->aPciBus;
1865	while (1)
1866	{
1867	PPCIDEVICE pBridge = ich9pciFindBridge(pBus, uBus);
1868	if (!pBridge)
1869	{
1870	Assert(false);
1871	break;
1872	}
1873	if (uBus == PCIDevGetByte(pBridge, VBOX_PCI_SECONDARY_BUS))
1874	{
1875	/* OK, found bus this device attached to. */
1876	break;
1877	}
1878	pBus = PDMINS_2_DATA(pBridge->pDevIns, PICH9PCIBUS);
1879	}
1880
1881	/* We need to go up to the host bus to see which irq pin this
1882	* device will use there. See logic in ich9pcibridgeSetIrq().
1883	*/
1884	while (pBus->iBus != 0)
1885	{
1886	/* Get the pin the device would assert on the bridge. */
1887	iPin = ((pBus->aPciDev.devfn >> 3) + iPin) & 3;
1888	pBus = pBus->aPciDev.Int.s.pBusR3;
1889	};
1890	}
1891
1892	int iIrq = aPciIrqs[ich9pciSlotGetPirq(uBus, uDevFn, iPin)];
1893	Log(("Using pin %d and IRQ %d for device %02x:%02x.%d\n",
1894	iPin, iIrq, uBus, uDevFn>>3, uDevFn&7));
1895	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_INTERRUPT_LINE, iIrq, 1);
1896	}
1897	}
1898
1899	/**
1900	* Initializes bridges registers used for routing.
1901	*
1902	* @returns nothing.
1903	* @param pGlobals Global device instance data used to generate unique bus numbers.
1904	* @param pBus The PCI bus to initialize.
1905	* @param uBusPrimary The primary bus number the bus is connected to.
1906	* @param uBusSecondary The secondary bus number, i.e. the bus number behind the bridge.
1907	*/
1908	static void ich9pciInitBridgeTopology(PICH9PCIGLOBALS pGlobals, PICH9PCIBUS pBus, unsigned uBusPrimary,
1909	unsigned uBusSecondary)
1910	{
1911	PPCIDEVICE pBridgeDev = &pBus->aPciDev;
1912
1913	/* Set only if we are not on the root bus, it has no primary bus attached. */
1914	if (uBusSecondary != 0)
1915	{
1916	PCIDevSetByte(pBridgeDev, VBOX_PCI_PRIMARY_BUS, uBusPrimary);
1917	PCIDevSetByte(pBridgeDev, VBOX_PCI_SECONDARY_BUS, uBusSecondary);
1918	}
1919
1920	for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
1921	{
1922	PPCIDEVICE pBridge = pBus->papBridgesR3[iBridge];
1923	AssertMsg(pBridge && pciDevIsPci2PciBridge(pBridge),
1924	("Device is not a PCI bridge but on the list of PCI bridges\n"));
1925	PICH9PCIBUS pChildBus = PDMINS_2_DATA(pBridge->pDevIns, PICH9PCIBUS);
1926	pGlobals->uBus++;
1927	ich9pciInitBridgeTopology(pGlobals, pChildBus, uBusSecondary, pGlobals->uBus);
1928	}
1929	PCIDevSetByte(pBridgeDev, VBOX_PCI_SUBORDINATE_BUS, pGlobals->uBus);
1930	Log2(("ich9pciInitBridgeTopology: for bus %p: primary=%d secondary=%d subordinate=%d\n",
1931	pBus,
1932	PCIDevGetByte(pBridgeDev, VBOX_PCI_PRIMARY_BUS),
1933	PCIDevGetByte(pBridgeDev, VBOX_PCI_SECONDARY_BUS),
1934	PCIDevGetByte(pBridgeDev, VBOX_PCI_SUBORDINATE_BUS)
1935	));
1936	}
1937
1938
1939	static DECLCALLBACK(int) ich9pciFakePCIBIOS(PPDMDEVINS pDevIns)
1940	{
1941	PICH9PCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
1942	PVM pVM = PDMDevHlpGetVM(pDevIns);
1943	Assert(pVM);
1944
1945	/*
1946	* Set the start addresses.
1947	*/
1948	pGlobals->uPciBiosIo = 0xd000;
1949	pGlobals->uPciBiosMmio = UINT32_C(0xf0000000);
1950	pGlobals->uBus = 0;
1951
1952	/*
1953	* Assign bridge topology, for further routing to work.
1954	*/
1955	PICH9PCIBUS pBus = &pGlobals->aPciBus;
1956	ich9pciInitBridgeTopology(pGlobals, pBus, 0, 0);
1957
1958	/*
1959	* Init the devices.
1960	*/
1961	for (int i = 0; i < 256; i++)
1962	{
1963	ich9pciBiosInitDevice(pGlobals, 0, i);
1964	}
1965
1966	return VINF_SUCCESS;
1967	}
1968
1969
1970	/*
1971	* Configuration space read callback (PCIDEVICEINT::pfnConfigRead) for
1972	* connected devices.
1973	*/
1974	static DECLCALLBACK(uint32_t) ich9pciConfigReadDev(PCIDevice *aDev, uint32_t u32Address, unsigned len)
1975	{
1976	if ((u32Address + len) > 256 && (u32Address + len) < 4096)
1977	{
1978	LogRel(("PCI: %8s/%u: Read from extended register %d fallen back to generic code\n",
1979	aDev->name, aDev->pDevIns->iInstance, u32Address));
1980	return 0;
1981	}
1982
1983	AssertMsgReturn(u32Address + len <= 256, ("Read after the end of PCI config space\n"),
1984	0);
1985	if ( pciDevIsMsiCapable(aDev)
1986	&& (u32Address >= aDev->Int.s.u8MsiCapOffset)
1987	&& (u32Address < (unsigned)(aDev->Int.s.u8MsiCapOffset + aDev->Int.s.u8MsiCapSize))
1988	)
1989	{
1990	return MsiPciConfigRead(aDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pDevIns), aDev, u32Address, len);
1991	}
1992
1993	if ( pciDevIsMsixCapable(aDev)
1994	&& (u32Address >= aDev->Int.s.u8MsixCapOffset)
1995	&& (u32Address < (unsigned)(aDev->Int.s.u8MsixCapOffset + aDev->Int.s.u8MsixCapSize))
1996	)
1997	{
1998	return MsixPciConfigRead(aDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pDevIns), aDev, u32Address, len);
1999	}
2000
2001	AssertMsgReturn(u32Address + len <= 256, ("Read after end of PCI config space\n"),
2002	0);
2003	switch (len)
2004	{
2005	case 1:
2006	return PCIDevGetByte(aDev, u32Address);
2007	case 2:
2008	return PCIDevGetWord(aDev, u32Address);
2009	case 4:
2010	return PCIDevGetDWord(aDev, u32Address);
2011	default:
2012	Assert(false);
2013	return 0;
2014	}
2015	}
2016
2017
2018	DECLINLINE(void) ich9pciWriteBarByte(PCIDevice *aDev, int iRegion, int iOffset, uint8_t u8Val)
2019	{
2020	PCIIORegion * pRegion = &aDev->Int.s.aIORegions[iRegion];
2021	int64_t iRegionSize = pRegion->size;
2022
2023	Log3(("ich9pciWriteBarByte: region=%d off=%d val=%x size=%d\n",
2024	iRegion, iOffset, u8Val, iRegionSize));
2025
2026	if (iOffset > 3)
2027	Assert((pRegion->type & PCI_ADDRESS_SPACE_BAR64) != 0);
2028
2029	/* Check if we're writing to upper part of 64-bit BAR. */
2030	if (pRegion->type == 0xff)
2031	{
2032	ich9pciWriteBarByte(aDev, iRegion-1, iOffset+4, u8Val);
2033	return;
2034	}
2035
2036	/* Region doesn't exist */
2037	if (iRegionSize == 0)
2038	return;
2039
2040	uint32_t uAddr = ich9pciGetRegionReg(iRegion) + iOffset;
2041	/* Region size must be power of two */
2042	Assert((iRegionSize & (iRegionSize - 1)) == 0);
2043	uint8_t uMask = ((iRegionSize - 1) >> (iOffset*8) ) & 0xff;
2044
2045	if (iOffset == 0)
2046	{
2047	uMask \|= (pRegion->type & PCI_ADDRESS_SPACE_IO) ?
2048	(1 << 2) - 1 /* 2 lowest bits for IO region */ :
2049	(1 << 4) - 1 /* 4 lowest bits for memory region, also ROM enable bit for ROM region */;
2050
2051	}
2052
2053	uint8_t u8Old = PCIDevGetByte(aDev, uAddr) & uMask;
2054	u8Val = (u8Old & uMask) \| (u8Val & ~uMask);
2055
2056	Log3(("ich9pciWriteBarByte: was %x writing %x\n", u8Old, u8Val));
2057
2058	PCIDevSetByte(aDev, uAddr, u8Val);
2059	}
2060
2061
2062	/**
2063	* Configuration space write callback (PCIDEVICEINT::pfnConfigWrite)
2064	* for connected devices.
2065	*
2066	* See paragraph 7.5 of PCI Express specification (p. 349) for
2067	* definition of registers and their writability policy.
2068	*/
2069	static DECLCALLBACK(void) ich9pciConfigWriteDev(PCIDevice *aDev, uint32_t u32Address,
2070	uint32_t val, unsigned len)
2071	{
2072	Assert(len <= 4);
2073
2074	if ((u32Address + len) > 256 && (u32Address + len) < 4096)
2075	{
2076	LogRel(("PCI: %8s/%u: Write to extended register %d fallen back to generic code\n",
2077	aDev->name, aDev->pDevIns->iInstance, u32Address));
2078	return;
2079	}
2080
2081	AssertMsgReturnVoid(u32Address + len <= 256, ("Write after end of PCI config space\n"));
2082
2083	if ( pciDevIsMsiCapable(aDev)
2084	&& (u32Address >= aDev->Int.s.u8MsiCapOffset)
2085	&& (u32Address < (unsigned)(aDev->Int.s.u8MsiCapOffset + aDev->Int.s.u8MsiCapSize))
2086	)
2087	{
2088	MsiPciConfigWrite(aDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pDevIns),
2089	aDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pPciHlp),
2090	aDev, u32Address, val, len);
2091	return;
2092	}
2093
2094	if ( pciDevIsMsixCapable(aDev)
2095	&& (u32Address >= aDev->Int.s.u8MsixCapOffset)
2096	&& (u32Address < (unsigned)(aDev->Int.s.u8MsixCapOffset + aDev->Int.s.u8MsixCapSize))
2097	)
2098	{
2099	MsixPciConfigWrite(aDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pDevIns),
2100	aDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pPciHlp),
2101	aDev, u32Address, val, len);
2102	return;
2103	}
2104
2105	uint32_t addr = u32Address;
2106	bool fUpdateMappings = false;
2107	bool fP2PBridge = false;
2108	/bool fPassthrough = pciDevIsPassthrough(aDev);/
2109	uint8_t u8HeaderType = ich9pciGetByte(aDev, VBOX_PCI_HEADER_TYPE);
2110
2111	for (uint32_t i = 0; i < len; i++)
2112	{
2113	bool fWritable = false;
2114	bool fRom = false;
2115	switch (u8HeaderType)
2116	{
2117	case 0x00: /* normal device */
2118	case 0x80: /* multi-function device */
2119	switch (addr)
2120	{
2121	/* Read-only registers */
2122	case VBOX_PCI_VENDOR_ID: case VBOX_PCI_VENDOR_ID+1:
2123	case VBOX_PCI_DEVICE_ID: case VBOX_PCI_DEVICE_ID+1:
2124	case VBOX_PCI_REVISION_ID:
2125	case VBOX_PCI_CLASS_PROG:
2126	case VBOX_PCI_CLASS_SUB:
2127	case VBOX_PCI_CLASS_BASE:
2128	case VBOX_PCI_HEADER_TYPE:
2129	case VBOX_PCI_SUBSYSTEM_VENDOR_ID: case VBOX_PCI_SUBSYSTEM_VENDOR_ID+1:
2130	case VBOX_PCI_SUBSYSTEM_ID: case VBOX_PCI_SUBSYSTEM_ID+1:
2131	case VBOX_PCI_ROM_ADDRESS: case VBOX_PCI_ROM_ADDRESS+1: case VBOX_PCI_ROM_ADDRESS+2: case VBOX_PCI_ROM_ADDRESS+3:
2132	case VBOX_PCI_CAPABILITY_LIST:
2133	case VBOX_PCI_INTERRUPT_PIN:
2134	fWritable = false;
2135	break;
2136	/* Others can be written */
2137	default:
2138	fWritable = true;
2139	break;
2140	}
2141	break;
2142	case 0x01: /* PCI-PCI bridge */
2143	fP2PBridge = true;
2144	switch (addr)
2145	{
2146	/* Read-only registers */
2147	case VBOX_PCI_VENDOR_ID: case VBOX_PCI_VENDOR_ID+1:
2148	case VBOX_PCI_DEVICE_ID: case VBOX_PCI_DEVICE_ID+1:
2149	case VBOX_PCI_REVISION_ID:
2150	case VBOX_PCI_CLASS_PROG:
2151	case VBOX_PCI_CLASS_SUB:
2152	case VBOX_PCI_CLASS_BASE:
2153	case VBOX_PCI_HEADER_TYPE:
2154	case VBOX_PCI_ROM_ADDRESS_BR: case VBOX_PCI_ROM_ADDRESS_BR+1: case VBOX_PCI_ROM_ADDRESS_BR+2: case VBOX_PCI_ROM_ADDRESS_BR+3:
2155	case VBOX_PCI_INTERRUPT_PIN:
2156	fWritable = false;
2157	break;
2158	default:
2159	fWritable = true;
2160	break;
2161	}
2162	break;
2163	default:
2164	AssertMsgFailed(("Unknown header type %x\n", PCIDevGetHeaderType(aDev)));
2165	fWritable = false;
2166	break;
2167	}
2168
2169	uint8_t u8Val = (uint8_t)val;
2170	switch (addr)
2171	{
2172	case VBOX_PCI_COMMAND: /* Command register, bits 0-7. */
2173	fUpdateMappings = true;
2174	goto default_case;
2175	case VBOX_PCI_COMMAND+1: /* Command register, bits 8-15. */
2176	/* don't change reserved bits (11-15) */
2177	u8Val &= UINT32_C(~0xf8);
2178	fUpdateMappings = true;
2179	goto default_case;
2180	case VBOX_PCI_STATUS: /* Status register, bits 0-7. */
2181	/* don't change read-only bits => actually all lower bits are read-only */
2182	u8Val &= UINT32_C(~0xff);
2183	/* status register, low part: clear bits by writing a '1' to the corresponding bit */
2184	aDev->config[addr] &= ~u8Val;
2185	break;
2186	case VBOX_PCI_STATUS+1: /* Status register, bits 8-15. */
2187	/* don't change read-only bits */
2188	u8Val &= UINT32_C(~0x06);
2189	/* status register, high part: clear bits by writing a '1' to the corresponding bit */
2190	aDev->config[addr] &= ~u8Val;
2191	break;
2192	case VBOX_PCI_ROM_ADDRESS: case VBOX_PCI_ROM_ADDRESS +1: case VBOX_PCI_ROM_ADDRESS +2: case VBOX_PCI_ROM_ADDRESS +3:
2193	fRom = true;
2194	case VBOX_PCI_BASE_ADDRESS_0: case VBOX_PCI_BASE_ADDRESS_0+1: case VBOX_PCI_BASE_ADDRESS_0+2: case VBOX_PCI_BASE_ADDRESS_0+3:
2195	case VBOX_PCI_BASE_ADDRESS_1: case VBOX_PCI_BASE_ADDRESS_1+1: case VBOX_PCI_BASE_ADDRESS_1+2: case VBOX_PCI_BASE_ADDRESS_1+3:
2196	case VBOX_PCI_BASE_ADDRESS_2: case VBOX_PCI_BASE_ADDRESS_2+1: case VBOX_PCI_BASE_ADDRESS_2+2: case VBOX_PCI_BASE_ADDRESS_2+3:
2197	case VBOX_PCI_BASE_ADDRESS_3: case VBOX_PCI_BASE_ADDRESS_3+1: case VBOX_PCI_BASE_ADDRESS_3+2: case VBOX_PCI_BASE_ADDRESS_3+3:
2198	case VBOX_PCI_BASE_ADDRESS_4: case VBOX_PCI_BASE_ADDRESS_4+1: case VBOX_PCI_BASE_ADDRESS_4+2: case VBOX_PCI_BASE_ADDRESS_4+3:
2199	case VBOX_PCI_BASE_ADDRESS_5: case VBOX_PCI_BASE_ADDRESS_5+1: case VBOX_PCI_BASE_ADDRESS_5+2: case VBOX_PCI_BASE_ADDRESS_5+3:
2200	{
2201	/* We check that, as same PCI register numbers as BARs may mean different registers for bridges */
2202	if (fP2PBridge)
2203	goto default_case;
2204	else
2205	{
2206	int iRegion = fRom ? VBOX_PCI_ROM_SLOT : (addr - VBOX_PCI_BASE_ADDRESS_0) >> 2;
2207	int iOffset = addr & 0x3;
2208	ich9pciWriteBarByte(aDev, iRegion, iOffset, u8Val);
2209	fUpdateMappings = true;
2210	}
2211	break;
2212	}
2213	default:
2214	default_case:
2215	if (fWritable)
2216	PCIDevSetByte(aDev, addr, u8Val);
2217	}
2218	addr++;
2219	val >>= 8;
2220	}
2221
2222	if (fUpdateMappings)
2223	/* if the command/base address register is modified, we must modify the mappings */
2224	ich9pciUpdateMappings(aDev);
2225	}
2226
2227	static bool assignPosition(PICH9PCIBUS pBus, PPCIDEVICE pPciDev, const char pszName, int iDevFn, PciAddress aPosition)
2228	{
2229	NOREF(pszName);
2230	aPosition->iBus = 0;
2231	aPosition->iDeviceFunc = iDevFn;
2232	aPosition->iRegister = 0; /* N/A */
2233
2234	/* Explicit slot request */
2235	if (iDevFn >= 0 && iDevFn < (int)RT_ELEMENTS(pBus->apDevices))
2236	return true;
2237
2238	int iStartPos = 0;
2239
2240	/* Otherwise when assigning a slot, we need to make sure all its functions are available */
2241	for (int iPos = iStartPos; iPos < (int)RT_ELEMENTS(pBus->apDevices); iPos += 8)
2242	{
2243	if ( !pBus->apDevices[iPos]
2244	&& !pBus->apDevices[iPos + 1]
2245	&& !pBus->apDevices[iPos + 2]
2246	&& !pBus->apDevices[iPos + 3]
2247	&& !pBus->apDevices[iPos + 4]
2248	&& !pBus->apDevices[iPos + 5]
2249	&& !pBus->apDevices[iPos + 6]
2250	&& !pBus->apDevices[iPos + 7])
2251	{
2252	pciDevClearRequestedDevfunc(pPciDev);
2253	aPosition->iDeviceFunc = iPos;
2254	return true;
2255	}
2256	}
2257
2258	return false;
2259	}
2260
2261	#ifdef SOME_UNUSED_FUNCTION
2262	static bool hasHardAssignedDevsInSlot(PICH9PCIBUS pBus, int iSlot)
2263	{
2264	PCIDevice** aSlot = &pBus->apDevices[iSlot << 3];
2265
2266	return (aSlot[0] && pciDevIsRequestedDevfunc(aSlot[0]))
2267	\|\| (aSlot[1] && pciDevIsRequestedDevfunc(aSlot[1]))
2268	\|\| (aSlot[2] && pciDevIsRequestedDevfunc(aSlot[2]))
2269	\|\| (aSlot[3] && pciDevIsRequestedDevfunc(aSlot[3]))
2270	\|\| (aSlot[4] && pciDevIsRequestedDevfunc(aSlot[4]))
2271	\|\| (aSlot[5] && pciDevIsRequestedDevfunc(aSlot[5]))
2272	\|\| (aSlot[6] && pciDevIsRequestedDevfunc(aSlot[6]))
2273	\|\| (aSlot[7] && pciDevIsRequestedDevfunc(aSlot[7]))
2274	;
2275	}
2276	#endif
2277
2278	static int ich9pciRegisterInternal(PICH9PCIBUS pBus, int iDev, PPCIDEVICE pPciDev, const char *pszName)
2279	{
2280	PciAddress aPosition;
2281	aPosition.iBus = 0;
2282	aPosition.iDeviceFunc = 0;
2283	aPosition.iRegister = 0;
2284
2285	/*
2286	* Find device position
2287	*/
2288	if (!assignPosition(pBus, pPciDev, pszName, iDev, &aPosition))
2289	{
2290	AssertMsgFailed(("Couldn't asssign position!\n"));
2291	return VERR_PDM_TOO_PCI_MANY_DEVICES;
2292	}
2293
2294	AssertMsgReturn(aPosition.iBus == 0,
2295	("Assigning behind the bridge not implemented yet\n"),
2296	VERR_PDM_TOO_PCI_MANY_DEVICES);
2297
2298
2299	iDev = aPosition.iDeviceFunc;
2300	/*
2301	* Check if we can really take this slot, possibly by relocating
2302	* its current habitant, if it wasn't hard assigned too.
2303	*/
2304	if (pciDevIsRequestedDevfunc(pPciDev) &&
2305	pBus->apDevices[iDev] &&
2306	pciDevIsRequestedDevfunc(pBus->apDevices[iDev]))
2307	{
2308	AssertReleaseMsgFailed(("Configuration error:'%s' and '%s' are both configured as device %d\n",
2309	pszName, pBus->apDevices[iDev]->name, iDev));
2310	return VERR_INTERNAL_ERROR;
2311	}
2312
2313	if (pBus->apDevices[iDev])
2314	{
2315	/* if we got here, we shall (and usually can) relocate the device */
2316	bool assigned = assignPosition(pBus, pBus->apDevices[iDev], pBus->apDevices[iDev]->name, -1, &aPosition);
2317	AssertMsgReturn(aPosition.iBus == 0,
2318	("Assigning behind the bridge not implemented yet\n"),
2319	VERR_PDM_TOO_PCI_MANY_DEVICES);
2320	int iRelDev = aPosition.iDeviceFunc;
2321	if (!assigned \|\| iRelDev == iDev)
2322	{
2323	AssertMsgFailed(("Couldn't find free spot!\n"));
2324	return VERR_PDM_TOO_PCI_MANY_DEVICES;
2325	}
2326	/* Copy device function by function to its new position */
2327	for (int i = 0; i < 8; i++)
2328	{
2329	if (!pBus->apDevices[iDev + i])
2330	continue;
2331	Log(("PCI: relocating '%s' from slot %#x to %#x\n", pBus->apDevices[iDev + i]->name, iDev + i, iRelDev + i));
2332	pBus->apDevices[iRelDev + i] = pBus->apDevices[iDev + i];
2333	pBus->apDevices[iRelDev + i]->devfn = iRelDev + i;
2334	pBus->apDevices[iDev + i] = NULL;
2335	}
2336	}
2337
2338	/*
2339	* Fill in device information.
2340	*/
2341	pPciDev->devfn = iDev;
2342	pPciDev->name = pszName;
2343	pPciDev->Int.s.pBusR3 = pBus;
2344	pPciDev->Int.s.pBusR0 = MMHyperR3ToR0(PDMDevHlpGetVM(pBus->CTX_SUFF(pDevIns)), pBus);
2345	pPciDev->Int.s.pBusRC = MMHyperR3ToRC(PDMDevHlpGetVM(pBus->CTX_SUFF(pDevIns)), pBus);
2346	pPciDev->Int.s.pfnConfigRead = ich9pciConfigReadDev;
2347	pPciDev->Int.s.pfnConfigWrite = ich9pciConfigWriteDev;
2348	pBus->apDevices[iDev] = pPciDev;
2349	if (pciDevIsPci2PciBridge(pPciDev))
2350	{
2351	AssertMsg(pBus->cBridges < RT_ELEMENTS(pBus->apDevices), ("Number of bridges exceeds the number of possible devices on the bus\n"));
2352	AssertMsg(pPciDev->Int.s.pfnBridgeConfigRead && pPciDev->Int.s.pfnBridgeConfigWrite,
2353	("device is a bridge but does not implement read/write functions\n"));
2354	Log2(("Setting bridge %d on bus %p\n", pBus->cBridges, pBus));
2355	pBus->papBridgesR3[pBus->cBridges] = pPciDev;
2356	pBus->cBridges++;
2357	}
2358
2359	Log(("PCI: Registered device %d function %d on bus %d (%#x) '%s'.\n",
2360	iDev >> 3, iDev & 7, pBus->iBus, 0x80000000 \| (iDev << 8), pszName));
2361
2362	return VINF_SUCCESS;
2363	}
2364
2365	static void printIndent(PCDBGFINFOHLP pHlp, int iIndent)
2366	{
2367	for (int i = 0; i < iIndent; i++)
2368	{
2369	pHlp->pfnPrintf(pHlp, " ");
2370	}
2371	}
2372
2373	static void ich9pciBusInfo(PICH9PCIBUS pBus, PCDBGFINFOHLP pHlp, int iIndent, bool fRegisters)
2374	{
2375	for (uint32_t iDev = 0; iDev < RT_ELEMENTS(pBus->apDevices); iDev++)
2376	{
2377	PPCIDEVICE pPciDev = pBus->apDevices[iDev];
2378	if (pPciDev != NULL)
2379	{
2380	printIndent(pHlp, iIndent);
2381
2382	/*
2383	* For passthrough devices MSI/MSI-X mostly reflects the way interrupts delivered to the guest,
2384	* as host driver handles real devices interrupts.
2385	*/
2386	pHlp->pfnPrintf(pHlp, "%02x:%02x:%02x %s%s: %04x-%04x",
2387	pBus->iBus, (iDev >> 3) & 0xff, iDev & 0x7,
2388	pPciDev->name,
2389	pciDevIsPassthrough(pPciDev) ? " (PASSTHROUGH)" : "",
2390	ich9pciGetWord(pPciDev, VBOX_PCI_VENDOR_ID), ich9pciGetWord(pPciDev, VBOX_PCI_DEVICE_ID)
2391	);
2392	if (ich9pciGetByte(pPciDev, VBOX_PCI_INTERRUPT_PIN) != 0)
2393	pHlp->pfnPrintf(pHlp, " IRQ%d", ich9pciGetByte(pPciDev, VBOX_PCI_INTERRUPT_LINE));
2394	pHlp->pfnPrintf(pHlp, "\n");
2395
2396	if (pciDevIsMsiCapable(pPciDev) \|\| pciDevIsMsixCapable(pPciDev))
2397	{
2398	printIndent(pHlp, iIndent + 2);
2399
2400	if (pciDevIsMsiCapable(pPciDev))
2401	pHlp->pfnPrintf(pHlp, "MSI:%s ", MsiIsEnabled(pPciDev) ? "on" : "off");
2402
2403	if (pciDevIsMsixCapable(pPciDev))
2404	pHlp->pfnPrintf(pHlp, "MSI-X:%s ", MsixIsEnabled(pPciDev) ? "on" : "off");
2405
2406	pHlp->pfnPrintf(pHlp, "\n");
2407	}
2408
2409	uint16_t iCmd = ich9pciGetWord(pPciDev, VBOX_PCI_COMMAND);
2410	if ((iCmd & (VBOX_PCI_COMMAND_IO \| VBOX_PCI_COMMAND_MEMORY)) != 0)
2411	{
2412	for (int iRegion = 0; iRegion < PCI_NUM_REGIONS; iRegion++)
2413	{
2414	PCIIORegion* pRegion = &pPciDev->Int.s.aIORegions[iRegion];
2415	uint64_t iRegionSize = pRegion->size;
2416
2417	if (iRegionSize == 0)
2418	continue;
2419
2420	uint32_t u32Addr = ich9pciGetDWord(pPciDev, ich9pciGetRegionReg(iRegion));
2421	const char * pszDesc;
2422	char szDescBuf[128];
2423
2424	bool f64Bit = !!(pRegion->type & PCI_ADDRESS_SPACE_BAR64);
2425	if (pRegion->type & PCI_ADDRESS_SPACE_IO)
2426	{
2427	pszDesc = "IO";
2428	u32Addr &= ~0x3;
2429	}
2430	else
2431	{
2432	RTStrPrintf(szDescBuf, sizeof(szDescBuf), "MMIO%s%s",
2433	f64Bit ? "64" : "32",
2434	(pRegion->type & PCI_ADDRESS_SPACE_MEM_PREFETCH) ? " PREFETCH" : "");
2435	pszDesc = szDescBuf;
2436	u32Addr &= ~0xf;
2437	}
2438
2439	printIndent(pHlp, iIndent + 2);
2440	pHlp->pfnPrintf(pHlp, "%s region #%d: %x..%x\n",
2441	pszDesc, iRegion, u32Addr, u32Addr+iRegionSize);
2442	if (f64Bit)
2443	iRegion++;
2444	}
2445	}
2446
2447	printIndent(pHlp, iIndent + 2);
2448	uint16_t iStatus = ich9pciGetWord(pPciDev, VBOX_PCI_STATUS);
2449	pHlp->pfnPrintf(pHlp, "Command: %04X, Status: %04X\n",
2450	iCmd, iStatus);
2451	printIndent(pHlp, iIndent + 2);
2452	pHlp->pfnPrintf(pHlp, "Bus master: %s\n",
2453	iCmd & VBOX_PCI_COMMAND_MASTER ? "Yes" : "No");
2454
2455	if (fRegisters)
2456	{
2457	printIndent(pHlp, iIndent + 2);
2458	pHlp->pfnPrintf(pHlp, "PCI registers:\n");
2459	for (int iReg = 0; iReg < 0x100; )
2460	{
2461	int iPerLine = 0x10;
2462	Assert (0x100 % iPerLine == 0);
2463	printIndent(pHlp, iIndent + 3);
2464
2465	while (iPerLine-- > 0)
2466	{
2467	pHlp->pfnPrintf(pHlp, "%02x ", ich9pciGetByte(pPciDev, iReg++));
2468	}
2469	pHlp->pfnPrintf(pHlp, "\n");
2470	}
2471	}
2472	}
2473	}
2474
2475	if (pBus->cBridges > 0)
2476	{
2477	printIndent(pHlp, iIndent);
2478	pHlp->pfnPrintf(pHlp, "Registered %d bridges, subordinate buses info follows\n", pBus->cBridges);
2479	for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
2480	{
2481	PICH9PCIBUS pBusSub = PDMINS_2_DATA(pBus->papBridgesR3[iBridge]->pDevIns, PICH9PCIBUS);
2482	ich9pciBusInfo(pBusSub, pHlp, iIndent + 1, fRegisters);
2483	}
2484	}
2485	}
2486
2487	/**
2488	* Info handler, device version.
2489	*
2490	* @param pDevIns Device instance which registered the info.
2491	* @param pHlp Callback functions for doing output.
2492	* @param pszArgs Argument string. Optional and specific to the handler.
2493	*/
2494	static DECLCALLBACK(void) ich9pciInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
2495	{
2496	PICH9PCIBUS pBus = DEVINS_2_PCIBUS(pDevIns);
2497
2498	if (pszArgs == NULL \|\| !strcmp(pszArgs, "basic"))
2499	{
2500	ich9pciBusInfo(pBus, pHlp, 0, false);
2501	}
2502	else if (!strcmp(pszArgs, "verbose"))
2503	{
2504	ich9pciBusInfo(pBus, pHlp, 0, true);
2505	}
2506	else
2507	{
2508	pHlp->pfnPrintf(pHlp, "Invalid argument. Recognized arguments are 'basic', 'verbose'.\n");
2509	}
2510	}
2511
2512
2513	static DECLCALLBACK(int) ich9pciConstruct(PPDMDEVINS pDevIns,
2514	int iInstance,
2515	PCFGMNODE pCfg)
2516	{
2517	Assert(iInstance == 0);
2518	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
2519
2520	/*
2521	* Validate and read configuration.
2522	*/
2523	if (!CFGMR3AreValuesValid(pCfg,
2524	"IOAPIC\0"
2525	"GCEnabled\0"
2526	"R0Enabled\0"
2527	"McfgBase\0"
2528	"McfgLength\0"
2529	))
2530	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
2531
2532	/* query whether we got an IOAPIC */
2533	bool fUseIoApic;
2534	int rc = CFGMR3QueryBoolDef(pCfg, "IOAPIC", &fUseIoApic, false);
2535	if (RT_FAILURE(rc))
2536	return PDMDEV_SET_ERROR(pDevIns, rc,
2537	N_("Configuration error: Failed to query boolean value \"IOAPIC\""));
2538
2539	/* check if RC code is enabled. */
2540	bool fGCEnabled;
2541	rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
2542	if (RT_FAILURE(rc))
2543	return PDMDEV_SET_ERROR(pDevIns, rc,
2544	N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
2545	/* check if R0 code is enabled. */
2546	bool fR0Enabled;
2547	rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
2548	if (RT_FAILURE(rc))
2549	return PDMDEV_SET_ERROR(pDevIns, rc,
2550	N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
2551
2552	Log(("PCI: fUseIoApic=%RTbool fGCEnabled=%RTbool fR0Enabled=%RTbool\n", fUseIoApic, fGCEnabled, fR0Enabled));
2553
2554	/*
2555	* Init data.
2556	*/
2557	PICH9PCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
2558	PICH9PCIBUS pBus = &pGlobals->aPciBus;
2559	/* Zero out everything */
2560	memset(pGlobals, 0, sizeof(*pGlobals));
2561	/* And fill values */
2562	if (!fUseIoApic)
2563	return PDMDEV_SET_ERROR(pDevIns, rc,
2564	N_("Must use IO-APIC with ICH9 chipset"));
2565	rc = CFGMR3QueryU64Def(pCfg, "McfgBase", &pGlobals->u64PciConfigMMioAddress, 0);
2566	if (RT_FAILURE(rc))
2567	return PDMDEV_SET_ERROR(pDevIns, rc,
2568	N_("Configuration error: Failed to read \"McfgBase\""));
2569	rc = CFGMR3QueryU64Def(pCfg, "McfgLength", &pGlobals->u64PciConfigMMioLength, 0);
2570	if (RT_FAILURE(rc))
2571	return PDMDEV_SET_ERROR(pDevIns, rc,
2572	N_("Configuration error: Failed to read \"McfgLength\""));
2573
2574	pGlobals->pDevInsR3 = pDevIns;
2575	pGlobals->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2576	pGlobals->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2577
2578	pGlobals->aPciBus.pDevInsR3 = pDevIns;
2579	pGlobals->aPciBus.pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2580	pGlobals->aPciBus.pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2581	pGlobals->aPciBus.papBridgesR3 = (PPCIDEVICE )PDMDevHlpMMHeapAllocZ(pDevIns, sizeof(PPCIDEVICE) RT_ELEMENTS(pGlobals->aPciBus.apDevices));
2582
2583	/*
2584	* Register bus
2585	*/
2586	PDMPCIBUSREG PciBusReg;
2587	PciBusReg.u32Version = PDM_PCIBUSREG_VERSION;
2588	PciBusReg.pfnRegisterR3 = ich9pciRegister;
2589	PciBusReg.pfnRegisterMsiR3 = ich9pciRegisterMsi;
2590	PciBusReg.pfnIORegionRegisterR3 = ich9pciIORegionRegister;
2591	PciBusReg.pfnSetConfigCallbacksR3 = ich9pciSetConfigCallbacks;
2592	PciBusReg.pfnSetIrqR3 = ich9pciSetIrq;
2593	PciBusReg.pfnFakePCIBIOSR3 = ich9pciFakePCIBIOS;
2594	PciBusReg.pszSetIrqRC = fGCEnabled ? "ich9pciSetIrq" : NULL;
2595	PciBusReg.pszSetIrqR0 = fR0Enabled ? "ich9pciSetIrq" : NULL;
2596	rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBus->pPciHlpR3);
2597	if (RT_FAILURE(rc))
2598	return PDMDEV_SET_ERROR(pDevIns, rc,
2599	N_("Failed to register ourselves as a PCI Bus"));
2600	if (pBus->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
2601	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
2602	N_("PCI helper version mismatch; got %#x expected %#x"),
2603	pBus->pPciHlpR3->u32Version, PDM_PCIHLPR3_VERSION);
2604
2605	pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
2606	pBus->pPciHlpR0 = pBus->pPciHlpR3->pfnGetR0Helpers(pDevIns);
2607
2608	/*
2609	* Fill in PCI configs and add them to the bus.
2610	*/
2611	/** @todo: Disabled for now because this causes error messages with Linux guests.
2612	* The guest loads the x38_edac device which tries to map a memory region
2613	* using an address given at place 0x48 - 0x4f in the PCi config space.
2614	* This fails. because we don't register such a region.
2615	*/
2616	#if 0
2617	/* Host bridge device */
2618	PCIDevSetVendorId( &pBus->aPciDev, 0x8086); /* Intel */
2619	PCIDevSetDeviceId( &pBus->aPciDev, 0x29e0); /* Desktop */
2620	PCIDevSetRevisionId(&pBus->aPciDev, 0x01); /* rev. 01 */
2621	PCIDevSetClassBase( &pBus->aPciDev, 0x06); /* bridge */
2622	PCIDevSetClassSub( &pBus->aPciDev, 0x00); /* Host/PCI bridge */
2623	PCIDevSetClassProg( &pBus->aPciDev, 0x00); /* Host/PCI bridge */
2624	PCIDevSetHeaderType(&pBus->aPciDev, 0x00); /* bridge */
2625	PCIDevSetWord(&pBus->aPciDev, VBOX_PCI_SEC_STATUS, 0x0280); /* secondary status */
2626
2627	pBus->aPciDev.pDevIns = pDevIns;
2628	/* We register Host<->PCI controller on the bus */
2629	ich9pciRegisterInternal(pBus, 0, &pBus->aPciDev, "dram");
2630	#endif
2631
2632	/*
2633	* Register I/O ports and save state.
2634	*/
2635	rc = PDMDevHlpIOPortRegister(pDevIns, 0x0cf8, 1, NULL, ich9pciIOPortAddressWrite, ich9pciIOPortAddressRead, NULL, NULL, "ICH9 (PCI)");
2636	if (RT_FAILURE(rc))
2637	return rc;
2638	rc = PDMDevHlpIOPortRegister(pDevIns, 0x0cfc, 4, NULL, ich9pciIOPortDataWrite, ich9pciIOPortDataRead, NULL, NULL, "ICH9 (PCI)");
2639	if (RT_FAILURE(rc))
2640	return rc;
2641	if (fGCEnabled)
2642	{
2643	rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x0cf8, 1, NIL_RTGCPTR, "ich9pciIOPortAddressWrite", "ich9pciIOPortAddressRead", NULL, NULL, "ICH9 (PCI)");
2644	if (RT_FAILURE(rc))
2645	return rc;
2646	rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x0cfc, 4, NIL_RTGCPTR, "ich9pciIOPortDataWrite", "ich9pciIOPortDataRead", NULL, NULL, "ICH9 (PCI)");
2647	if (RT_FAILURE(rc))
2648	return rc;
2649	}
2650	if (fR0Enabled)
2651	{
2652	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x0cf8, 1, NIL_RTR0PTR, "ich9pciIOPortAddressWrite", "ich9pciIOPortAddressRead", NULL, NULL, "ICH9 (PCI)");
2653	if (RT_FAILURE(rc))
2654	return rc;
2655	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x0cfc, 4, NIL_RTR0PTR, "ich9pciIOPortDataWrite", "ich9pciIOPortDataRead", NULL, NULL, "ICH9 (PCI)");
2656	if (RT_FAILURE(rc))
2657	return rc;
2658	}
2659
2660	if (pGlobals->u64PciConfigMMioAddress != 0)
2661	{
2662	rc = PDMDevHlpMMIORegister(pDevIns, pGlobals->u64PciConfigMMioAddress, pGlobals->u64PciConfigMMioLength, NULL /pvUser/,
2663	IOMMMIO_FLAGS_READ_PASSTHRU \| IOMMMIO_FLAGS_WRITE_PASSTHRU,
2664	ich9pciMcfgMMIOWrite, ich9pciMcfgMMIORead, "MCFG ranges");
2665	AssertMsgRCReturn(rc, ("rc=%Rrc %#llx/%#llx\n", rc, pGlobals->u64PciConfigMMioAddress, pGlobals->u64PciConfigMMioLength), rc);
2666
2667	if (fGCEnabled)
2668	{
2669	rc = PDMDevHlpMMIORegisterRC(pDevIns, pGlobals->u64PciConfigMMioAddress, pGlobals->u64PciConfigMMioLength,
2670	NIL_RTRCPTR /pvUser/, "ich9pciMcfgMMIOWrite", "ich9pciMcfgMMIORead");
2671	AssertRCReturn(rc, rc);
2672	}
2673
2674
2675	if (fR0Enabled)
2676	{
2677	rc = PDMDevHlpMMIORegisterR0(pDevIns, pGlobals->u64PciConfigMMioAddress, pGlobals->u64PciConfigMMioLength,
2678	NIL_RTR0PTR /pvUser/, "ich9pciMcfgMMIOWrite", "ich9pciMcfgMMIORead");
2679	AssertRCReturn(rc, rc);
2680	}
2681	}
2682
2683	rc = PDMDevHlpSSMRegisterEx(pDevIns, VBOX_ICH9PCI_SAVED_STATE_VERSION_CURRENT,
2684	sizeof(pBus) + 16128, "pgm",
2685	NULL, NULL, NULL,
2686	NULL, ich9pciR3SaveExec, NULL,
2687	NULL, ich9pciR3LoadExec, NULL);
2688	if (RT_FAILURE(rc))
2689	return rc;
2690
2691
2692	/** @todo: other chipset devices shall be registered too */
2693
2694	PDMDevHlpDBGFInfoRegister(pDevIns, "pci", "Display PCI bus status. Recognizes 'basic' or 'verbose' "
2695	"as arguments, defaults to 'basic'.", ich9pciInfo);
2696
2697	return VINF_SUCCESS;
2698	}
2699
2700	static void ich9pciResetDevice(PPCIDEVICE pDev)
2701	{
2702	/* Clear regions */
2703	for (int iRegion = 0; iRegion < PCI_NUM_REGIONS; iRegion++)
2704	{
2705	PCIIORegion* pRegion = &pDev->Int.s.aIORegions[iRegion];
2706	if (pRegion->size == 0)
2707	continue;
2708
2709	ich9pciUnmapRegion(pDev, iRegion);
2710	}
2711
2712	if (pciDevIsPassthrough(pDev))
2713	{
2714	// no reset handler - we can do what we need in PDM reset handler
2715	// @todo: is it correct?
2716	}
2717	else
2718	{
2719	PCIDevSetCommand(pDev,
2720	PCIDevGetCommand(pDev)
2721	&
2722	~(VBOX_PCI_COMMAND_IO \| VBOX_PCI_COMMAND_MEMORY \|
2723	VBOX_PCI_COMMAND_MASTER \| VBOX_PCI_COMMAND_SPECIAL \|
2724	VBOX_PCI_COMMAND_PARITY \| VBOX_PCI_COMMAND_SERR \|
2725	VBOX_PCI_COMMAND_FAST_BACK \| VBOX_PCI_COMMAND_INTX_DISABLE));
2726
2727	/* Bridge device reset handlers processed later */
2728	if (!pciDevIsPci2PciBridge(pDev))
2729	{
2730	PCIDevSetByte(pDev, VBOX_PCI_CACHE_LINE_SIZE, 0x0);
2731	PCIDevSetInterruptLine(pDev, 0x0);
2732	}
2733
2734	/* Reset MSI message control. */
2735	if (pciDevIsMsiCapable(pDev))
2736	{
2737	/* Extracted from MsiPciConfigWrite(). */
2738	pDev->config[pDev->Int.s.u8MsiCapOffset + VBOX_MSI_CAP_MESSAGE_CONTROL] &= 0x8e;
2739	}
2740
2741	/* Reset MSI-X message control. */
2742	if (pciDevIsMsixCapable(pDev))
2743	{
2744	/* Extracted from MsixPciConfigWrite(); no side effects. */
2745	pDev->config[pDev->Int.s.u8MsixCapOffset + VBOX_MSIX_CAP_MESSAGE_CONTROL + 1] &= 0x3f;
2746	}
2747	}
2748	}
2749
2750
2751	/**
2752	* @copydoc FNPDMDEVRESET
2753	*/
2754	static DECLCALLBACK(void) ich9pciReset(PPDMDEVINS pDevIns)
2755	{
2756	PICH9PCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
2757	PICH9PCIBUS pBus = &pGlobals->aPciBus;
2758
2759	/* PCI-specific reset for each device. */
2760	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
2761	{
2762	if (pBus->apDevices[i])
2763	ich9pciResetDevice(pBus->apDevices[i]);
2764	}
2765
2766	for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
2767	{
2768	if (pBus->papBridgesR3[iBridge])
2769	ich9pcibridgeReset(pBus->papBridgesR3[iBridge]->pDevIns);
2770	}
2771
2772	ich9pciFakePCIBIOS(pDevIns);
2773	}
2774
2775	static void ich9pciRelocateDevice(PPCIDEVICE pDev, RTGCINTPTR offDelta)
2776	{
2777	if (pDev)
2778	{
2779	pDev->Int.s.pBusRC += offDelta;
2780	if (pDev->Int.s.pMsixPageRC)
2781	pDev->Int.s.pMsixPageRC += offDelta;
2782	}
2783	}
2784
2785	/**
2786	* @copydoc FNPDMDEVRELOCATE
2787	*/
2788	static DECLCALLBACK(void) ich9pciRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
2789	{
2790	PICH9PCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
2791	PICH9PCIBUS pBus = &pGlobals->aPciBus;
2792	pGlobals->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2793
2794	pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
2795	pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2796
2797	/* Relocate RC pointers for the attached pci devices. */
2798	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
2799	ich9pciRelocateDevice(pBus->apDevices[i], offDelta);
2800
2801	}
2802
2803	/**
2804	* @interface_method_impl{PDMDEVREG,pfnConstruct}
2805	*/
2806	static DECLCALLBACK(int) ich9pcibridgeConstruct(PPDMDEVINS pDevIns,
2807	int iInstance,
2808	PCFGMNODE pCfg)
2809	{
2810	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
2811
2812	/*
2813	* Validate and read configuration.
2814	*/
2815	if (!CFGMR3AreValuesValid(pCfg, "GCEnabled\0" "R0Enabled\0"))
2816	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
2817
2818	/* check if RC code is enabled. */
2819	bool fGCEnabled;
2820	int rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
2821	if (RT_FAILURE(rc))
2822	return PDMDEV_SET_ERROR(pDevIns, rc,
2823	N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
2824
2825	/* check if R0 code is enabled. */
2826	bool fR0Enabled;
2827	rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
2828	if (RT_FAILURE(rc))
2829	return PDMDEV_SET_ERROR(pDevIns, rc,
2830	N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
2831	Log(("PCI: fGCEnabled=%RTbool fR0Enabled=%RTbool\n", fGCEnabled, fR0Enabled));
2832
2833	/*
2834	* Init data and register the PCI bus.
2835	*/
2836	PICH9PCIBUS pBus = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
2837	pBus->pDevInsR3 = pDevIns;
2838	pBus->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2839	pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2840	pBus->papBridgesR3 = (PPCIDEVICE )PDMDevHlpMMHeapAllocZ(pDevIns, sizeof(PPCIDEVICE) RT_ELEMENTS(pBus->apDevices));
2841
2842	PDMPCIBUSREG PciBusReg;
2843	PciBusReg.u32Version = PDM_PCIBUSREG_VERSION;
2844	PciBusReg.pfnRegisterR3 = ich9pcibridgeRegister;
2845	PciBusReg.pfnRegisterMsiR3 = ich9pciRegisterMsi;
2846	PciBusReg.pfnIORegionRegisterR3 = ich9pciIORegionRegister;
2847	PciBusReg.pfnSetConfigCallbacksR3 = ich9pciSetConfigCallbacks;
2848	PciBusReg.pfnSetIrqR3 = ich9pcibridgeSetIrq;
2849	PciBusReg.pfnFakePCIBIOSR3 = NULL; /* Only needed for the first bus. */
2850	PciBusReg.pszSetIrqRC = fGCEnabled ? "ich9pcibridgeSetIrq" : NULL;
2851	PciBusReg.pszSetIrqR0 = fR0Enabled ? "ich9pcibridgeSetIrq" : NULL;
2852	rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBus->pPciHlpR3);
2853	if (RT_FAILURE(rc))
2854	return PDMDEV_SET_ERROR(pDevIns, rc,
2855	N_("Failed to register ourselves as a PCI Bus"));
2856	if (pBus->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
2857	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
2858	N_("PCI helper version mismatch; got %#x expected %#x"),
2859	pBus->pPciHlpR3->u32Version, PDM_PCIHLPR3_VERSION);
2860
2861	pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
2862	pBus->pPciHlpR0 = pBus->pPciHlpR3->pfnGetR0Helpers(pDevIns);
2863
2864	/* Disable default device locking. */
2865	rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
2866	AssertRCReturn(rc, rc);
2867
2868	/*
2869	* Fill in PCI configs and add them to the bus.
2870	*/
2871	PCIDevSetVendorId( &pBus->aPciDev, 0x8086); /* Intel */
2872	PCIDevSetDeviceId( &pBus->aPciDev, 0x2448); /* 82801 Mobile PCI bridge. */
2873	PCIDevSetRevisionId(&pBus->aPciDev, 0xf2);
2874	PCIDevSetClassSub( &pBus->aPciDev, 0x04); /* pci2pci */
2875	PCIDevSetClassBase( &pBus->aPciDev, 0x06); /* PCI_bridge */
2876	PCIDevSetClassProg( &pBus->aPciDev, 0x01); /* Supports subtractive decoding. */
2877	PCIDevSetHeaderType(&pBus->aPciDev, 0x01); /* Single function device which adheres to the PCI-to-PCI bridge spec. */
2878	PCIDevSetCommand( &pBus->aPciDev, 0x00);
2879	PCIDevSetStatus( &pBus->aPciDev, 0x20); /* 66MHz Capable. */
2880	PCIDevSetInterruptLine(&pBus->aPciDev, 0x00); /* This device does not assert interrupts. */
2881
2882	/*
2883	* This device does not generate interrupts. Interrupt delivery from
2884	* devices attached to the bus is unaffected.
2885	*/
2886	PCIDevSetInterruptPin (&pBus->aPciDev, 0x00);
2887
2888	pBus->aPciDev.pDevIns = pDevIns;
2889
2890	/* Bridge-specific data */
2891	pciDevSetPci2PciBridge(&pBus->aPciDev);
2892	pBus->aPciDev.Int.s.pfnBridgeConfigRead = ich9pcibridgeConfigRead;
2893	pBus->aPciDev.Int.s.pfnBridgeConfigWrite = ich9pcibridgeConfigWrite;
2894
2895	/*
2896	* Register this PCI bridge. The called function will take care on which bus we will get registered.
2897	*/
2898	rc = PDMDevHlpPCIRegister (pDevIns, &pBus->aPciDev);
2899	if (RT_FAILURE(rc))
2900	return rc;
2901
2902	/*
2903	* The iBus property doesn't really represent the bus number
2904	* because the guest and the BIOS can choose different bus numbers
2905	* for them.
2906	* The bus number is mainly for the setIrq function to indicate
2907	* when the host bus is reached which will have iBus = 0.
2908	* That's why the + 1.
2909	*/
2910	pBus->iBus = iInstance + 1;
2911
2912	/*
2913	* Register SSM handlers. We use the same saved state version as for the host bridge
2914	* to make changes easier.
2915	*/
2916	rc = PDMDevHlpSSMRegisterEx(pDevIns, VBOX_ICH9PCI_SAVED_STATE_VERSION_CURRENT,
2917	sizeof(pBus) + 16128,
2918	"pgm" /* before */,
2919	NULL, NULL, NULL,
2920	NULL, ich9pcibridgeR3SaveExec, NULL,
2921	NULL, ich9pcibridgeR3LoadExec, NULL);
2922	if (RT_FAILURE(rc))
2923	return rc;
2924
2925
2926	return VINF_SUCCESS;
2927	}
2928
2929	/**
2930	* @copydoc FNPDMDEVRESET
2931	*/
2932	static void ich9pcibridgeReset(PPDMDEVINS pDevIns)
2933	{
2934	PICH9PCIBUS pBus = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
2935
2936	/* Reset config space to default values. */
2937	PCIDevSetByte(&pBus->aPciDev, VBOX_PCI_PRIMARY_BUS, 0);
2938	PCIDevSetByte(&pBus->aPciDev, VBOX_PCI_SECONDARY_BUS, 0);
2939	PCIDevSetByte(&pBus->aPciDev, VBOX_PCI_SUBORDINATE_BUS, 0);
2940
2941	/* PCI-specific reset for each device. */
2942	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
2943	{
2944	if (pBus->apDevices[i])
2945	ich9pciResetDevice(pBus->apDevices[i]);
2946	}
2947	}
2948
2949
2950	/**
2951	* @copydoc FNPDMDEVRELOCATE
2952	*/
2953	static DECLCALLBACK(void) ich9pcibridgeRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
2954	{
2955	PICH9PCIBUS pBus = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
2956	pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2957
2958	/* Relocate RC pointers for the attached pci devices. */
2959	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
2960	ich9pciRelocateDevice(pBus->apDevices[i], offDelta);
2961	}
2962
2963	/**
2964	* The PCI bus device registration structure.
2965	*/
2966	const PDMDEVREG g_DevicePciIch9 =
2967	{
2968	/* u32Version */
2969	PDM_DEVREG_VERSION,
2970	/* szName */
2971	"ich9pci",
2972	/* szRCMod */
2973	"VBoxDDRC.rc",
2974	/* szR0Mod */
2975	"VBoxDDR0.r0",
2976	/* pszDescription */
2977	"ICH9 PCI bridge",
2978	/* fFlags */
2979	PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
2980	/* fClass */
2981	PDM_DEVREG_CLASS_BUS_PCI \| PDM_DEVREG_CLASS_BUS_ISA,
2982	/* cMaxInstances */
2983	1,
2984	/* cbInstance */
2985	sizeof(ICH9PCIGLOBALS),
2986	/* pfnConstruct */
2987	ich9pciConstruct,
2988	/* pfnDestruct */
2989	NULL,
2990	/* pfnRelocate */
2991	ich9pciRelocate,
2992	/* pfnMemSetup */
2993	NULL,
2994	/* pfnPowerOn */
2995	NULL,
2996	/* pfnReset */
2997	ich9pciReset,
2998	/* pfnSuspend */
2999	NULL,
3000	/* pfnResume */
3001	NULL,
3002	/* pfnAttach */
3003	NULL,
3004	/* pfnDetach */
3005	NULL,
3006	/* pfnQueryInterface */
3007	NULL,
3008	/* pfnInitComplete */
3009	NULL,
3010	/* pfnPowerOff */
3011	NULL,
3012	/* pfnSoftReset */
3013	NULL,
3014	/* u32VersionEnd */
3015	PDM_DEVREG_VERSION
3016	};
3017
3018	/**
3019	* The device registration structure
3020	* for the PCI-to-PCI bridge.
3021	*/
3022	const PDMDEVREG g_DevicePciIch9Bridge =
3023	{
3024	/* u32Version */
3025	PDM_DEVREG_VERSION,
3026	/* szName */
3027	"ich9pcibridge",
3028	/* szRCMod */
3029	"VBoxDDRC.rc",
3030	/* szR0Mod */
3031	"VBoxDDR0.r0",
3032	/* pszDescription */
3033	"ICH9 PCI to PCI bridge",
3034	/* fFlags */
3035	PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
3036	/* fClass */
3037	PDM_DEVREG_CLASS_BUS_PCI,
3038	/* cMaxInstances */
3039	~0U,
3040	/* cbInstance */
3041	sizeof(ICH9PCIBUS),
3042	/* pfnConstruct */
3043	ich9pcibridgeConstruct,
3044	/* pfnDestruct */
3045	NULL,
3046	/* pfnRelocate */
3047	ich9pcibridgeRelocate,
3048	/* pfnMemSetup */
3049	NULL,
3050	/* pfnPowerOn */
3051	NULL,
3052	/* pfnReset */
3053	NULL, /* Must be NULL, to make sure only bus driver handles reset */
3054	/* pfnSuspend */
3055	NULL,
3056	/* pfnResume */
3057	NULL,
3058	/* pfnAttach */
3059	NULL,
3060	/* pfnDetach */
3061	NULL,
3062	/* pfnQueryInterface */
3063	NULL,
3064	/* pfnInitComplete */
3065	NULL,
3066	/* pfnPowerOff */
3067	NULL,
3068	/* pfnSoftReset */
3069	NULL,
3070	/* u32VersionEnd */
3071	PDM_DEVREG_VERSION
3072	};
3073
3074	#endif /* IN_RING3 */
3075	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */

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source: vbox/trunk/src/VBox/Devices/Bus/DevPciIch9.cpp@ 61497

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