DevPciIch9.cpp@ 63845

Last change on this file since 63845 was 63777, checked in by vboxsync, 8 years ago
removed assertion
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1	/* $Id: DevPciIch9.cpp 63777 2016-09-09 11:59:12Z vboxsync $ */
2	/** @file
3	* DevPCI - ICH9 southbridge PCI bus emulation device.
4	*
5	* @note bird: I've cleaned up DevPCI.cpp to some extent, this file has not
6	* be cleaned up and because of pending code merge.
7	*/
8
9	/*
10	* Copyright (C) 2010-2016 Oracle Corporation
11	*
12	* This file is part of VirtualBox Open Source Edition (OSE), as
13	* available from http://www.virtualbox.org. This file is free software;
14	* you can redistribute it and/or modify it under the terms of the GNU
15	* General Public License (GPL) as published by the Free Software
16	* Foundation, in version 2 as it comes in the "COPYING" file of the
17	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
18	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
19	*/
20
21
22	/*********************************************************************************************************************************
23	* Header Files *
24	*********************************************************************************************************************************/
25	#define LOG_GROUP LOG_GROUP_DEV_PCI
26	/* Hack to get PCIDEVICEINT declared at the right point - include "PCIInternal.h". */
27	#define PCI_INCLUDE_PRIVATE
28	#define PCIBus ICH9PCIBus
29	#include <VBox/pci.h>
30	#include <VBox/msi.h>
31	#include <VBox/vmm/pdmdev.h>
32	#include <VBox/vmm/mm.h>
33	#include <iprt/asm.h>
34	#include <iprt/assert.h>
35	#include <iprt/string.h>
36	#ifdef IN_RING3
37	#include <iprt/alloc.h>
38	#endif
39
40	#include "VBoxDD.h"
41	#include "MsiCommon.h"
42
43
44	/*********************************************************************************************************************************
45	* Structures and Typedefs *
46	*********************************************************************************************************************************/
47	/**
48	* PCI Bus instance.
49	*/
50	typedef struct ICH9PCIBus
51	{
52	/** Bus number. */
53	int32_t iBus;
54	/** Number of bridges attached to the bus. */
55	uint32_t cBridges;
56
57	/** Array of PCI devices. We assume 32 slots, each with 8 functions. */
58	R3PTRTYPE(PPCIDEVICE) apDevices[256];
59	/** Array of bridges attached to the bus. */
60	R3PTRTYPE(PPCIDEVICE *) papBridgesR3;
61
62	/** R3 pointer to the device instance. */
63	PPDMDEVINSR3 pDevInsR3;
64	/** Pointer to the PCI R3 helpers. */
65	PCPDMPCIHLPR3 pPciHlpR3;
66
67	/** R0 pointer to the device instance. */
68	PPDMDEVINSR0 pDevInsR0;
69	/** Pointer to the PCI R0 helpers. */
70	PCPDMPCIHLPR0 pPciHlpR0;
71
72	/** RC pointer to the device instance. */
73	PPDMDEVINSRC pDevInsRC;
74	/** Pointer to the PCI RC helpers. */
75	PCPDMPCIHLPRC pPciHlpRC;
76
77	/** The PCI device for the PCI bridge. */
78	PCIDEVICE aPciDev;
79
80	} ICH9PCIBUS, *PICH9PCIBUS;
81
82
83	/** @def PCI_APIC_IRQ_PINS
84	* Number of pins for interrupts if the APIC is used.
85	*/
86	#define PCI_APIC_IRQ_PINS 8
87
88	/**
89	* PCI Globals - This is the host-to-pci bridge and the root bus.
90	*/
91	typedef struct
92	{
93	/** R3 pointer to the device instance. */
94	PPDMDEVINSR3 pDevInsR3;
95	/** R0 pointer to the device instance. */
96	PPDMDEVINSR0 pDevInsR0;
97	/** RC pointer to the device instance. */
98	PPDMDEVINSRC pDevInsRC;
99
100	/** Value latched in Configuration Address Port (0CF8h) */
101	uint32_t uConfigReg;
102
103	/** I/O APIC irq levels */
104	volatile uint32_t uaPciApicIrqLevels[PCI_APIC_IRQ_PINS];
105
106	#if 1 /* Will be moved into the BIOS soon. */
107	/** The next I/O port address which the PCI BIOS will use. */
108	uint32_t uPciBiosIo;
109	/** The next MMIO address which the PCI BIOS will use. */
110	uint32_t uPciBiosMmio;
111	/** The next 64-bit MMIO address which the PCI BIOS will use. */
112	uint64_t uPciBiosMmio64;
113	/** Actual bus number. */
114	uint8_t uBus;
115	uint8_t Alignment0[7];
116	#endif
117	/** Physical address of PCI config space MMIO region. */
118	uint64_t u64PciConfigMMioAddress;
119	/** Length of PCI config space MMIO region. */
120	uint64_t u64PciConfigMMioLength;
121
122	/** PCI bus which is attached to the host-to-PCI bridge. */
123	ICH9PCIBUS aPciBus;
124	} ICH9PCIGLOBALS, *PICH9PCIGLOBALS;
125
126
127	/**
128	* PCI configuration space address.
129	*/
130	typedef struct
131	{
132	uint8_t iBus;
133	uint8_t iDeviceFunc;
134	uint16_t iRegister;
135	} PciAddress;
136
137	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
138
139
140	/*********************************************************************************************************************************
141	* Defined Constants And Macros *
142	*********************************************************************************************************************************/
143
144	/** @def VBOX_ICH9PCI_SAVED_STATE_VERSION
145	* Saved state version of the ICH9 PCI bus device.
146	*/
147	#define VBOX_ICH9PCI_SAVED_STATE_VERSION_NOMSI 1
148	#define VBOX_ICH9PCI_SAVED_STATE_VERSION_MSI 2
149	#define VBOX_ICH9PCI_SAVED_STATE_VERSION_CURRENT VBOX_ICH9PCI_SAVED_STATE_VERSION_MSI
150
151	/** Converts a bus instance pointer to a device instance pointer. */
152	#define PCIBUS_2_DEVINS(pPciBus) ((pPciBus)->CTX_SUFF(pDevIns))
153	/** Converts a device instance pointer to a ICH9PCIGLOBALS pointer. */
154	#define DEVINS_2_PCIGLOBALS(pDevIns) ((PICH9PCIGLOBALS)(PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS)))
155	/** Converts a device instance pointer to a PCIBUS pointer. */
156	#define DEVINS_2_PCIBUS(pDevIns) ((PICH9PCIBUS)(&PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS)->aPciBus))
157	/** Converts a pointer to a PCI root bus instance to a PCIGLOBALS pointer. */
158	#define PCIROOTBUS_2_PCIGLOBALS(pPciBus) ( (PICH9PCIGLOBALS)((uintptr_t)(pPciBus) - RT_OFFSETOF(ICH9PCIGLOBALS, aPciBus)) )
159
160	/** @def PCI_LOCK
161	* Acquires the PDM lock. This is a NOP if locking is disabled. */
162	/** @def PCI_UNLOCK
163	* Releases the PDM lock. This is a NOP if locking is disabled. */
164	#define PCI_LOCK(pDevIns, rc) \
165	do { \
166	int rc2 = DEVINS_2_PCIBUS(pDevIns)->CTX_SUFF(pPciHlp)->pfnLock((pDevIns), rc); \
167	if (rc2 != VINF_SUCCESS) \
168	return rc2; \
169	} while (0)
170	#define PCI_UNLOCK(pDevIns) \
171	DEVINS_2_PCIBUS(pDevIns)->CTX_SUFF(pPciHlp)->pfnUnlock(pDevIns)
172
173	/* Prototypes */
174	static void ich9pciSetIrqInternal(PICH9PCIGLOBALS pGlobals, uint8_t uDevFn, PPCIDEVICE pPciDev,
175	int iIrq, int iLevel, uint32_t uTagSrc);
176	#ifdef IN_RING3
177	static void ich9pcibridgeReset(PPDMDEVINS pDevIns);
178	static int ich9pciRegisterInternal(PICH9PCIBUS pBus, int iDev, PPCIDEVICE pPciDev, const char *pszName);
179	static void ich9pciUpdateMappings(PCIDevice *pDev);
180	static DECLCALLBACK(uint32_t) ich9pciConfigReadDev(PCIDevice *aDev, uint32_t u32Address, unsigned len);
181	DECLINLINE(PPCIDEVICE) ich9pciFindBridge(PICH9PCIBUS pBus, uint8_t iBus);
182	static void ich9pciBiosInitDevice(PICH9PCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn);
183	#endif
184
185	// See 7.2.2. PCI Express Enhanced Configuration Mechanism for details of address
186	// mapping, we take n=6 approach
187	DECLINLINE(void) ich9pciPhysToPciAddr(PICH9PCIGLOBALS pGlobals, RTGCPHYS GCPhysAddr, PciAddress* pPciAddr)
188	{
189	NOREF(pGlobals);
190	pPciAddr->iBus = (GCPhysAddr >> 20) & ((1<<6) - 1);
191	pPciAddr->iDeviceFunc = (GCPhysAddr >> 12) & ((1<<(5+3)) - 1); // 5 bits - device, 3 bits - function
192	pPciAddr->iRegister = (GCPhysAddr >> 0) & ((1<<(6+4+2)) - 1); // 6 bits - register, 4 bits - extended register, 2 bits -Byte Enable
193	}
194
195	DECLINLINE(void) ich9pciStateToPciAddr(PICH9PCIGLOBALS pGlobals, RTGCPHYS addr, PciAddress* pPciAddr)
196	{
197	pPciAddr->iBus = (pGlobals->uConfigReg >> 16) & 0xff;
198	pPciAddr->iDeviceFunc = (pGlobals->uConfigReg >> 8) & 0xff;
199	pPciAddr->iRegister = (pGlobals->uConfigReg & 0xfc) \| (addr & 3);
200	}
201
202	PDMBOTHCBDECL(void) ich9pciSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel, uint32_t uTagSrc)
203	{
204	LogFlowFunc(("invoked by %p/%d: iIrq=%d iLevel=%d uTagSrc=%#x\n", pDevIns, pDevIns->iInstance, iIrq, iLevel, uTagSrc));
205	ich9pciSetIrqInternal(PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS), pPciDev->devfn, pPciDev, iIrq, iLevel, uTagSrc);
206	}
207
208	PDMBOTHCBDECL(void) ich9pcibridgeSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel, uint32_t uTagSrc)
209	{
210	/*
211	* The PCI-to-PCI bridge specification defines how the interrupt pins
212	* are routed from the secondary to the primary bus (see chapter 9).
213	* iIrq gives the interrupt pin the pci device asserted.
214	* We change iIrq here according to the spec and call the SetIrq function
215	* of our parent passing the device which asserted the interrupt instead of the device of the bridge.
216	*/
217	PICH9PCIBUS pBus = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
218	PPCIDEVICE pPciDevBus = pPciDev;
219	int iIrqPinBridge = iIrq;
220	uint8_t uDevFnBridge = 0;
221
222	/* Walk the chain until we reach the host bus. */
223	do
224	{
225	uDevFnBridge = pBus->aPciDev.devfn;
226	iIrqPinBridge = ((pPciDevBus->devfn >> 3) + iIrqPinBridge) & 3;
227
228	/* Get the parent. */
229	pBus = pBus->aPciDev.Int.s.CTX_SUFF(pBus);
230	pPciDevBus = &pBus->aPciDev;
231	} while (pBus->iBus != 0);
232
233	AssertMsgReturnVoid(pBus->iBus == 0, ("This is not the host pci bus iBus=%d\n", pBus->iBus));
234	ich9pciSetIrqInternal(PCIROOTBUS_2_PCIGLOBALS(pBus), uDevFnBridge, pPciDev, iIrqPinBridge, iLevel, uTagSrc);
235	}
236
237
238	/**
239	* Port I/O Handler for PCI address OUT operations.
240	*
241	* Emulates writes to Configuration Address Port at 0CF8h for
242	* Configuration Mechanism #1.
243	*
244	* @returns VBox status code.
245	*
246	* @param pDevIns ICH9 device instance.
247	* @param pvUser User argument - ignored.
248	* @param uPort Port number used for the OUT operation.
249	* @param u32 The value to output.
250	* @param cb The value size in bytes.
251	*/
252	PDMBOTHCBDECL(int) ich9pciIOPortAddressWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
253	{
254	LogFlow(("ich9pciIOPortAddressWrite: Port=%#x u32=%#x cb=%d\n", Port, u32, cb));
255	RT_NOREF2(Port, pvUser);
256	if (cb == 4)
257	{
258	PICH9PCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
259
260	/*
261	* bits [1:0] are hard-wired, read-only and must return zeroes
262	* when read.
263	*/
264	u32 &= ~3;
265
266	PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_WRITE);
267	pThis->uConfigReg = u32;
268	PCI_UNLOCK(pDevIns);
269	}
270
271	return VINF_SUCCESS;
272	}
273
274
275	/**
276	* Port I/O Handler for PCI address IN operations.
277	*
278	* Emulates reads from Configuration Address Port at 0CF8h for
279	* Configuration Mechanism #1.
280	*
281	* @returns VBox status code.
282	*
283	* @param pDevIns ICH9 device instance.
284	* @param pvUser User argument - ignored.
285	* @param uPort Port number used for the IN operation.
286	* @param pu32 Where to store the result.
287	* @param cb Number of bytes read.
288	*/
289	PDMBOTHCBDECL(int) ich9pciIOPortAddressRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
290	{
291	RT_NOREF2(Port, pvUser);
292	if (cb == 4)
293	{
294	PICH9PCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
295
296	PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_READ);
297	*pu32 = pThis->uConfigReg;
298	PCI_UNLOCK(pDevIns);
299
300	LogFlow(("ich9pciIOPortAddressRead: Port=%#x cb=%d -> %#x\n", Port, cb, *pu32));
301	return VINF_SUCCESS;
302	}
303
304	Log(("ich9pciIOPortAddressRead: Port=%#x cb=%d VERR_IOM_IOPORT_UNUSED\n", Port, cb));
305	return VERR_IOM_IOPORT_UNUSED;
306	}
307
308
309	/*
310	* Perform configuration space write.
311	*/
312	static int ich9pciDataWriteAddr(PICH9PCIGLOBALS pGlobals, PciAddress* pAddr,
313	uint32_t val, int cb, int rcReschedule)
314	{
315	int rc = VINF_SUCCESS;
316	#ifdef IN_RING3
317	NOREF(rcReschedule);
318	#else
319	RT_NOREF2(val, cb);
320	#endif
321
322	if (pAddr->iBus != 0) /* forward to subordinate bus */
323	{
324	if (pGlobals->aPciBus.cBridges)
325	{
326	#ifdef IN_RING3 /** @todo do lookup in R0/RC too! */
327	PPCIDEVICE pBridgeDevice = ich9pciFindBridge(&pGlobals->aPciBus, pAddr->iBus);
328	if (pBridgeDevice)
329	{
330	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigWrite);
331	pBridgeDevice->Int.s.pfnBridgeConfigWrite(pBridgeDevice->pDevIns, pAddr->iBus, pAddr->iDeviceFunc,
332	pAddr->iRegister, val, cb);
333	}
334	#else
335	rc = rcReschedule;
336	#endif
337	}
338	}
339	else /* forward to directly connected device */
340	{
341	R3PTRTYPE(PCIDevice *) aDev = pGlobals->aPciBus.apDevices[pAddr->iDeviceFunc];
342	if (aDev)
343	{
344	#ifdef IN_RING3
345	aDev->Int.s.pfnConfigWrite(aDev, pAddr->iRegister, val, cb);
346	#else
347	rc = rcReschedule;
348	#endif
349	}
350	}
351
352	Log2(("ich9pciDataWriteAddr: %02x:%02x:%02x reg %x(%d) %x %Rrc\n",
353	pAddr->iBus, pAddr->iDeviceFunc >> 3, pAddr->iDeviceFunc & 0x7, pAddr->iRegister,
354	cb, val, rc));
355	return rc;
356	}
357
358
359	/*
360	* Decode value latched in Configuration Address Port and perform
361	* requsted write to the target configuration space register.
362	*
363	* XXX: This code should be probably moved to its only caller
364	* (ich9pciIOPortDataWrite) to avoid prolifiration of confusingly
365	* similarly named functions.
366	*/
367	static int ich9pciDataWrite(PICH9PCIGLOBALS pGlobals, uint32_t addr, uint32_t val, int len)
368	{
369	LogFlow(("ich9pciDataWrite: config=%08x val=%08x len=%d\n", pGlobals->uConfigReg, val, len));
370
371	/* Configuration space mapping enabled? */
372	if (!(pGlobals->uConfigReg & (1 << 31)))
373	return VINF_SUCCESS;
374
375	/* Decode target device and configuration space register */
376	PciAddress aPciAddr;
377	ich9pciStateToPciAddr(pGlobals, addr, &aPciAddr);
378
379	/* Perform configuration space write */
380	return ich9pciDataWriteAddr(pGlobals, &aPciAddr, val, len, VINF_IOM_R3_IOPORT_WRITE);
381	}
382
383
384	/**
385	* Port I/O Handler for PCI data OUT operations.
386	*
387	* Emulates writes to Configuration Data Port at 0CFCh for
388	* Configuration Mechanism #1.
389	*
390	* @returns VBox status code.
391	*
392	* @param pDevIns ICH9 device instance.
393	* @param pvUser User argument - ignored.
394	* @param uPort Port number used for the OUT operation.
395	* @param u32 The value to output.
396	* @param cb The value size in bytes.
397	*/
398	PDMBOTHCBDECL(int) ich9pciIOPortDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
399	{
400	LogFlow(("ich9pciIOPortDataWrite: Port=%#x u32=%#x cb=%d\n", Port, u32, cb));
401	NOREF(pvUser);
402	int rc = VINF_SUCCESS;
403	if (!(Port % cb))
404	{
405	PICH9PCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
406
407	PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_WRITE);
408	rc = ich9pciDataWrite(pThis, Port, u32, cb);
409	PCI_UNLOCK(pDevIns);
410	}
411	else
412	AssertMsgFailed(("Unaligned write to port %#x u32=%#x cb=%d\n", Port, u32, cb));
413	return rc;
414	}
415
416
417	static void ich9pciNoMem(void* ptr, int cb)
418	{
419	for (int i = 0; i < cb; i++)
420	((uint8_t*)ptr)[i] = 0xff;
421	}
422
423
424	/*
425	* Perform configuration space read.
426	*/
427	static int ich9pciDataReadAddr(PICH9PCIGLOBALS pGlobals, PciAddress* pPciAddr, int cb,
428	uint32_t *pu32, int rcReschedule)
429	{
430	int rc = VINF_SUCCESS;
431	#ifdef IN_RING3
432	NOREF(rcReschedule);
433	#endif
434
435	if (pPciAddr->iBus != 0) /* forward to subordinate bus */
436	{
437	if (pGlobals->aPciBus.cBridges)
438	{
439	#ifdef IN_RING3 /** @todo do lookup in R0/RC too! */
440	PPCIDEVICE pBridgeDevice = ich9pciFindBridge(&pGlobals->aPciBus, pPciAddr->iBus);
441	if (pBridgeDevice)
442	{
443	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigRead);
444	*pu32 = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->pDevIns, pPciAddr->iBus, pPciAddr->iDeviceFunc, pPciAddr->iRegister, cb);
445	}
446	else
447	ich9pciNoMem(pu32, cb);
448	#else
449	rc = rcReschedule;
450	#endif
451	}
452	else
453	ich9pciNoMem(pu32, cb);
454	}
455	else /* forward to directly connected device */
456	{
457	R3PTRTYPE(PCIDevice *) aDev = pGlobals->aPciBus.apDevices[pPciAddr->iDeviceFunc];
458	if (aDev)
459	{
460	#ifdef IN_RING3
461	*pu32 = aDev->Int.s.pfnConfigRead(aDev, pPciAddr->iRegister, cb);
462	#else
463	rc = rcReschedule;
464	#endif
465	}
466	else
467	ich9pciNoMem(pu32, cb);
468	}
469
470	Log3(("ich9pciDataReadAddr: %02x:%02x:%02x reg %x(%d) gave %x %Rrc\n",
471	pPciAddr->iBus, pPciAddr->iDeviceFunc >> 3, pPciAddr->iDeviceFunc & 0x7, pPciAddr->iRegister,
472	cb, *pu32, rc));
473	return rc;
474	}
475
476
477	/*
478	* Decode value latched in Configuration Address Port and perform
479	* requsted read from the target configuration space register.
480	*
481	* XXX: This code should be probably moved to its only caller
482	* (ich9pciIOPortDataRead) to avoid prolifiration of confusingly
483	* similarly named functions.
484	*/
485	static int ich9pciDataRead(PICH9PCIGLOBALS pGlobals, uint32_t addr, int cb, uint32_t *pu32)
486	{
487	LogFlow(("ich9pciDataRead: config=%x cb=%d\n", pGlobals->uConfigReg, cb));
488
489	*pu32 = 0xffffffff;
490
491	/* Configuration space mapping enabled? */
492	if (!(pGlobals->uConfigReg & (1 << 31)))
493	return VINF_SUCCESS;
494
495	/* Decode target device and configuration space register */
496	PciAddress aPciAddr;
497	ich9pciStateToPciAddr(pGlobals, addr, &aPciAddr);
498
499	/* Perform configuration space read */
500	return ich9pciDataReadAddr(pGlobals, &aPciAddr, cb, pu32, VINF_IOM_R3_IOPORT_READ);
501	}
502
503
504	/**
505	* Port I/O Handler for PCI data IN operations.
506	*
507	* Emulates reads from Configuration Data Port at 0CFCh for
508	* Configuration Mechanism #1.
509	*
510	* @returns VBox status code.
511	*
512	* @param pDevIns ICH9 device instance.
513	* @param pvUser User argument - ignored.
514	* @param uPort Port number used for the IN operation.
515	* @param pu32 Where to store the result.
516	* @param cb Number of bytes read.
517	*/
518	PDMBOTHCBDECL(int) ich9pciIOPortDataRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
519	{
520	NOREF(pvUser);
521	if (!(Port % cb))
522	{
523	PICH9PCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
524
525	PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_READ);
526	int rc = ich9pciDataRead(pThis, Port, cb, pu32);
527	PCI_UNLOCK(pDevIns);
528
529	LogFlow(("ich9pciIOPortDataRead: Port=%#x cb=%#x -> %#x (%Rrc)\n", Port, cb, *pu32, rc));
530	return rc;
531	}
532	AssertMsgFailed(("Unaligned read from port %#x cb=%d\n", Port, cb));
533	return VERR_IOM_IOPORT_UNUSED;
534	}
535
536
537	/* Compute mapping of PCI slot and IRQ number to APIC interrupt line */
538	DECLINLINE(int) ich9pciSlot2ApicIrq(uint8_t uSlot, int irq_num)
539	{
540	return (irq_num + uSlot) & 7;
541	}
542
543	#ifdef IN_RING3
544
545	/* return the global irq number corresponding to a given device irq
546	pin. We could also use the bus number to have a more precise
547	mapping. This is the implementation note described in the PCI spec chapter 2.2.6 */
548	DECLINLINE(int) ich9pciSlotGetPirq(uint8_t uBus, uint8_t uDevFn, int iIrqNum)
549	{
550	NOREF(uBus);
551	int iSlotAddend = (uDevFn >> 3) - 1;
552	return (iIrqNum + iSlotAddend) & 3;
553	}
554
555	/* irqs corresponding to PCI irqs A-D, must match pci_irq_list in rombios.c */
556	static const uint8_t aPciIrqs[4] = { 11, 10, 9, 5 };
557
558	#endif /* IN_RING3 */
559
560	/* Add one more level up request on APIC input line */
561	DECLINLINE(void) ich9pciApicLevelUp(PICH9PCIGLOBALS pGlobals, int irq_num)
562	{
563	ASMAtomicIncU32(&pGlobals->uaPciApicIrqLevels[irq_num]);
564	}
565
566	/* Remove one level up request on APIC input line */
567	DECLINLINE(void) ich9pciApicLevelDown(PICH9PCIGLOBALS pGlobals, int irq_num)
568	{
569	ASMAtomicDecU32(&pGlobals->uaPciApicIrqLevels[irq_num]);
570	}
571
572	static void ich9pciApicSetIrq(PICH9PCIBUS pBus, uint8_t uDevFn, PCIDevice *pPciDev, int irq_num1, int iLevel,
573	uint32_t uTagSrc, int iForcedIrq)
574	{
575	/* This is only allowed to be called with a pointer to the root bus. */
576	AssertMsg(pBus->iBus == 0, ("iBus=%u\n", pBus->iBus));
577
578	if (iForcedIrq == -1)
579	{
580	int apic_irq, apic_level;
581	PICH9PCIGLOBALS pGlobals = PCIROOTBUS_2_PCIGLOBALS(pBus);
582	int irq_num = ich9pciSlot2ApicIrq(uDevFn >> 3, irq_num1);
583
584	if ((iLevel & PDM_IRQ_LEVEL_HIGH) == PDM_IRQ_LEVEL_HIGH)
585	ich9pciApicLevelUp(pGlobals, irq_num);
586	else if ((iLevel & PDM_IRQ_LEVEL_HIGH) == PDM_IRQ_LEVEL_LOW)
587	ich9pciApicLevelDown(pGlobals, irq_num);
588
589	apic_irq = irq_num + 0x10;
590	apic_level = pGlobals->uaPciApicIrqLevels[irq_num] != 0;
591	Log3(("ich9pciApicSetIrq: %s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d uTagSrc=%#x\n",
592	R3STRING(pPciDev->name), irq_num1, iLevel, apic_irq, apic_level, irq_num, uTagSrc));
593	pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), apic_irq, apic_level, uTagSrc);
594
595	if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP)
596	{
597	/*
598	* we raised it few lines above, as PDM_IRQ_LEVEL_FLIP_FLOP has
599	* PDM_IRQ_LEVEL_HIGH bit set
600	*/
601	ich9pciApicLevelDown(pGlobals, irq_num);
602	pPciDev->Int.s.uIrqPinState = PDM_IRQ_LEVEL_LOW;
603	apic_level = pGlobals->uaPciApicIrqLevels[irq_num] != 0;
604	Log3(("ich9pciApicSetIrq: %s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d uTagSrc=%#x (flop)\n",
605	R3STRING(pPciDev->name), irq_num1, iLevel, apic_irq, apic_level, irq_num, uTagSrc));
606	pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), apic_irq, apic_level, uTagSrc);
607	}
608	} else {
609	Log3(("ich9pciApicSetIrq: (forced) %s: irq_num1=%d level=%d acpi_irq=%d uTagSrc=%#x\n",
610	R3STRING(pPciDev->name), irq_num1, iLevel, iForcedIrq, uTagSrc));
611	pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), iForcedIrq, iLevel, uTagSrc);
612	}
613	}
614
615	static void ich9pciSetIrqInternal(PICH9PCIGLOBALS pGlobals, uint8_t uDevFn, PPCIDEVICE pPciDev,
616	int iIrq, int iLevel, uint32_t uTagSrc)
617	{
618	/* If MSI or MSI-X is enabled, PCI INTx# signals are disabled regardless of the PCI command
619	* register interrupt bit state.
620	* PCI 3.0 (section 6.8) forbids MSI and MSI-X to be enabled at the same time and makes
621	* that undefined behavior. We check for MSI first, then MSI-X.
622	*/
623	if (MsiIsEnabled(pPciDev))
624	{
625	Assert(!MsixIsEnabled(pPciDev)); /* Not allowed -- see note above. */
626	LogFlowFunc(("PCI Dev %p : MSI\n", pPciDev));
627	PPDMDEVINS pDevIns = pGlobals->aPciBus.CTX_SUFF(pDevIns);
628	MsiNotify(pDevIns, pGlobals->aPciBus.CTX_SUFF(pPciHlp), pPciDev, iIrq, iLevel, uTagSrc);
629	return;
630	}
631
632	if (MsixIsEnabled(pPciDev))
633	{
634	LogFlowFunc(("PCI Dev %p : MSI-X\n", pPciDev));
635	PPDMDEVINS pDevIns = pGlobals->aPciBus.CTX_SUFF(pDevIns);
636	MsixNotify(pDevIns, pGlobals->aPciBus.CTX_SUFF(pPciHlp), pPciDev, iIrq, iLevel, uTagSrc);
637	return;
638	}
639
640	PICH9PCIBUS pBus = &pGlobals->aPciBus;
641	const bool fIsAcpiDevice = PCIDevGetDeviceId(pPciDev) == 0x7113;
642
643	LogFlowFunc(("PCI Dev %p : IRQ\n", pPciDev));
644	/* Check if the state changed. */
645	if (pPciDev->Int.s.uIrqPinState != iLevel)
646	{
647	pPciDev->Int.s.uIrqPinState = (iLevel & PDM_IRQ_LEVEL_HIGH);
648
649	/* Send interrupt to I/O APIC only now. */
650	if (fIsAcpiDevice)
651	/*
652	* ACPI needs special treatment since SCI is hardwired and
653	* should not be affected by PCI IRQ routing tables at the
654	* same time SCI IRQ is shared in PCI sense hence this
655	* kludge (i.e. we fetch the hardwired value from ACPIs
656	* PCI device configuration space).
657	*/
658	ich9pciApicSetIrq(pBus, uDevFn, pPciDev, -1, iLevel, uTagSrc, PCIDevGetInterruptLine(pPciDev));
659	else
660	ich9pciApicSetIrq(pBus, uDevFn, pPciDev, iIrq, iLevel, uTagSrc, -1);
661	}
662	}
663
664
665	/**
666	* Memory mapped I/O Handler for write operations.
667	*
668	* Emulates writes to configuration space.
669	*
670	* @returns VBox status code.
671	*
672	* @param pDevIns The device instance.
673	* @param pvUser User argument.
674	* @param GCPhysAddr Physical address (in GC) where the read starts.
675	* @param pv Where to fetch the result.
676	* @param cb Number of bytes to write.
677	* @remarks Caller enters the device critical section.
678	*/
679	PDMBOTHCBDECL(int) ich9pciMcfgMMIOWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void const pv, unsigned cb)
680	{
681	PICH9PCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
682	uint32_t u32 = 0;
683	NOREF(pvUser);
684
685	Log2(("ich9pciMcfgMMIOWrite: %RGp(%d) \n", GCPhysAddr, cb));
686
687	PCI_LOCK(pDevIns, VINF_IOM_R3_MMIO_WRITE);
688
689	/* Decode target device and configuration space register */
690	PciAddress aDest;
691	ich9pciPhysToPciAddr(pGlobals, GCPhysAddr, &aDest);
692
693	switch (cb)
694	{
695	case 1:
696	u32 = (uint8_t)pv;
697	break;
698	case 2:
699	u32 = (uint16_t)pv;
700	break;
701	case 4:
702	u32 = (uint32_t)pv;
703	break;
704	default:
705	Assert(false);
706	break;
707	}
708
709	/* Perform configuration space write */
710	int rc = ich9pciDataWriteAddr(pGlobals, &aDest, u32, cb, VINF_IOM_R3_MMIO_WRITE);
711	PCI_UNLOCK(pDevIns);
712
713	return rc;
714	}
715
716
717	/**
718	* Memory mapped I/O Handler for read operations.
719	*
720	* Emulates reads from configuration space.
721	*
722	* @returns VBox status code.
723	*
724	* @param pDevIns The device instance.
725	* @param pvUser User argument.
726	* @param GCPhysAddr Physical address (in GC) where the read starts.
727	* @param pv Where to store the result.
728	* @param cb Number of bytes read.
729	* @remarks Caller enters the device critical section.
730	*/
731	PDMBOTHCBDECL(int) ich9pciMcfgMMIORead (PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb)
732	{
733	PICH9PCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
734	uint32_t rv;
735	NOREF(pvUser);
736
737	LogFlow(("ich9pciMcfgMMIORead: %RGp(%d) \n", GCPhysAddr, cb));
738
739	PCI_LOCK(pDevIns, VINF_IOM_R3_MMIO_READ);
740
741	/* Decode target device and configuration space register */
742	PciAddress aDest;
743	ich9pciPhysToPciAddr(pGlobals, GCPhysAddr, &aDest);
744
745	/* Perform configuration space read */
746	int rc = ich9pciDataReadAddr(pGlobals, &aDest, cb, &rv, VINF_IOM_R3_MMIO_READ);
747
748	if (RT_SUCCESS(rc))
749	{
750	switch (cb)
751	{
752	case 1:
753	(uint8_t)pv = (uint8_t)rv;
754	break;
755	case 2:
756	(uint16_t)pv = (uint16_t)rv;
757	break;
758	case 4:
759	(uint32_t)pv = (uint32_t)rv;
760	break;
761	default:
762	Assert(false);
763	break;
764	}
765	}
766	PCI_UNLOCK(pDevIns);
767
768	return rc;
769	}
770
771	#ifdef IN_RING3
772
773	DECLINLINE(PPCIDEVICE) ich9pciFindBridge(PICH9PCIBUS pBus, uint8_t iBus)
774	{
775	/* Search for a fitting bridge. */
776	for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
777	{
778	/*
779	* Examine secondary and subordinate bus number.
780	* If the target bus is in the range we pass the request on to the bridge.
781	*/
782	PPCIDEVICE pBridge = pBus->papBridgesR3[iBridge];
783	AssertMsg(pBridge && pciDevIsPci2PciBridge(pBridge),
784	("Device is not a PCI bridge but on the list of PCI bridges\n"));
785	uint32_t uSecondary = PCIDevGetByte(pBridge, VBOX_PCI_SECONDARY_BUS);
786	uint32_t uSubordinate = PCIDevGetByte(pBridge, VBOX_PCI_SUBORDINATE_BUS);
787	Log3(("ich9pciFindBridge on bus %p, bridge %d: %d in %d..%d\n", pBus, iBridge, iBus, uSecondary, uSubordinate));
788	if (iBus >= uSecondary && iBus <= uSubordinate)
789	return pBridge;
790	}
791
792	/* Nothing found. */
793	return NULL;
794	}
795
796	static uint32_t ich9pciGetCfg(PCIDevice* aDev, int32_t iRegister, int cb)
797	{
798	return aDev->Int.s.pfnConfigRead(aDev, iRegister, cb);
799	}
800
801	static uint8_t ich9pciGetByte(PCIDevice* aDev, int32_t iRegister)
802	{
803	return (uint8_t)ich9pciGetCfg(aDev, iRegister, 1);
804	}
805
806	static uint16_t ich9pciGetWord(PCIDevice* aDev, int32_t iRegister)
807	{
808	return (uint16_t)ich9pciGetCfg(aDev, iRegister, 2);
809	}
810
811	static uint32_t ich9pciGetDWord(PCIDevice* aDev, int32_t iRegister)
812	{
813	return (uint32_t)ich9pciGetCfg(aDev, iRegister, 4);
814	}
815
816	DECLINLINE(uint32_t) ich9pciGetRegionReg(int iRegion)
817	{
818	return (iRegion == VBOX_PCI_ROM_SLOT) ?
819	VBOX_PCI_ROM_ADDRESS : (VBOX_PCI_BASE_ADDRESS_0 + iRegion * 4);
820	}
821
822	#define INVALID_PCI_ADDRESS ~0U
823
824	static int ich9pciUnmapRegion(PPCIDEVICE pDev, int iRegion)
825	{
826	PCIIORegion* pRegion = &pDev->Int.s.aIORegions[iRegion];
827	int rc = VINF_SUCCESS;
828	PICH9PCIBUS pBus = pDev->Int.s.CTX_SUFF(pBus);
829
830	Assert (pRegion->size != 0);
831
832	if (pRegion->addr != INVALID_PCI_ADDRESS)
833	{
834	if (pRegion->type & PCI_ADDRESS_SPACE_IO)
835	{
836	/* Port IO */
837	rc = PDMDevHlpIOPortDeregister(pDev->pDevIns, pRegion->addr, pRegion->size);
838	AssertRC(rc);
839	}
840	else
841	{
842	RTGCPHYS GCPhysBase = pRegion->addr;
843	if (pBus->pPciHlpR3->pfnIsMMIO2Base(pBus->pDevInsR3, pDev->pDevIns, GCPhysBase))
844	{
845	/* unmap it. */
846	rc = pRegion->map_func(pDev, iRegion, NIL_RTGCPHYS, pRegion->size, (PCIADDRESSSPACE)(pRegion->type));
847	AssertRC(rc);
848	rc = PDMDevHlpMMIO2Unmap(pDev->pDevIns, iRegion, GCPhysBase);
849	}
850	else
851	rc = PDMDevHlpMMIODeregister(pDev->pDevIns, GCPhysBase, pRegion->size);
852	}
853
854	pRegion->addr = INVALID_PCI_ADDRESS;
855	}
856
857	return rc;
858	}
859
860	static void ich9pciUpdateMappings(PCIDevice* pDev)
861	{
862	uint64_t uLast, uNew;
863
864	int iCmd = ich9pciGetWord(pDev, VBOX_PCI_COMMAND);
865	for (int iRegion = 0; iRegion < PCI_NUM_REGIONS; iRegion++)
866	{
867	PCIIORegion* pRegion = &pDev->Int.s.aIORegions[iRegion];
868	uint32_t uConfigReg = ich9pciGetRegionReg(iRegion);
869	int64_t iRegionSize = pRegion->size;
870	int rc;
871
872	if (iRegionSize == 0)
873	continue;
874
875	bool f64Bit = (pRegion->type & PCI_ADDRESS_SPACE_BAR64) != 0;
876
877	if (pRegion->type & PCI_ADDRESS_SPACE_IO)
878	{
879	/* port IO region */
880	if (iCmd & PCI_COMMAND_IOACCESS)
881	{
882	/* IO access allowed */
883	uNew = ich9pciGetDWord(pDev, uConfigReg);
884	uNew &= ~(iRegionSize - 1);
885	uLast = uNew + iRegionSize - 1;
886	/* only 64K ioports on PC */
887	if (uLast <= uNew \|\| uNew == 0 \|\| uLast >= 0x10000)
888	uNew = INVALID_PCI_ADDRESS;
889	} else
890	uNew = INVALID_PCI_ADDRESS;
891	}
892	else
893	{
894	/* MMIO region */
895	if (iCmd & PCI_COMMAND_MEMACCESS)
896	{
897	uNew = ich9pciGetDWord(pDev, uConfigReg);
898
899	if (f64Bit)
900	{
901	uNew \|= ((uint64_t)ich9pciGetDWord(pDev, uConfigReg+4)) << 32;
902	/** @todo r=klaus Is this really true? Needs to be fixed properly. */
903	if (uNew > UINT64_C(0x0000010000000000))
904	{
905	/* Workaround for REM being unhapping with mapping very long 64-bit addresses */
906	LogRel(("Ignoring too long 64-bit BAR: %llx\n", uNew));
907	uNew = INVALID_PCI_ADDRESS;
908	}
909	}
910
911	/* the ROM slot has a specific enable bit */
912	if (iRegion == PCI_ROM_SLOT && !(uNew & 1))
913	uNew = INVALID_PCI_ADDRESS;
914	else
915	{
916	uNew &= ~(iRegionSize - 1);
917	uLast = uNew + iRegionSize - 1;
918	/* NOTE: we do not support wrapping */
919	/* XXX: as we cannot support really dynamic
920	mappings, we handle specific values as invalid
921	mappings. */
922	/* Unconditionally exclude I/O-APIC/HPET/ROM. Pessimistic, but better than causing a mess. */
923	if (uLast <= uNew \|\| uNew == 0 \|\| (uNew <= UINT32_C(0xffffffff) && uLast >= UINT32_C(0xfec00000)))
924	uNew = INVALID_PCI_ADDRESS;
925	}
926	} else
927	uNew = INVALID_PCI_ADDRESS;
928	}
929	LogRel2(("PCI: config dev %u/%u BAR%i uOld=%#018llx uNew=%#018llx size=%llu\n", pDev->devfn >> 3, pDev->devfn & 7, iRegion, pRegion->addr, uNew, pRegion->size));
930	/* now do the real mapping */
931	if (uNew != pRegion->addr)
932	{
933	if (pRegion->addr != INVALID_PCI_ADDRESS)
934	ich9pciUnmapRegion(pDev, iRegion);
935
936	pRegion->addr = uNew;
937	if (pRegion->addr != INVALID_PCI_ADDRESS)
938	{
939
940	/* finally, map the region */
941	rc = pRegion->map_func(pDev, iRegion,
942	pRegion->addr, pRegion->size,
943	(PCIADDRESSSPACE)(pRegion->type));
944	AssertRC(rc);
945	}
946	}
947
948	if (f64Bit)
949	iRegion++;
950	}
951	}
952
953	static DECLCALLBACK(int) ich9pciRegister(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, const char *pszName, int iDev)
954	{
955	PICH9PCIBUS pBus = DEVINS_2_PCIBUS(pDevIns);
956
957	/*
958	* Check input.
959	*/
960	if ( !pszName
961	\|\| !pPciDev
962	\|\| iDev >= (int)RT_ELEMENTS(pBus->apDevices)
963	)
964	{
965	AssertMsgFailed(("Invalid argument! pszName=%s pPciDev=%p iDev=%d\n", pszName, pPciDev, iDev));
966	return VERR_INVALID_PARAMETER;
967	}
968
969	/*
970	* Register the device.
971	*/
972	return ich9pciRegisterInternal(pBus, iDev, pPciDev, pszName);
973	}
974
975
976	static DECLCALLBACK(int) ich9pciRegisterMsi(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PPDMMSIREG pMsiReg)
977	{
978	NOREF(pDevIns);
979	int rc;
980
981	rc = MsiInit(pPciDev, pMsiReg);
982	if (RT_FAILURE(rc))
983	return rc;
984
985	rc = MsixInit(pPciDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pPciHlp), pPciDev, pMsiReg);
986	if (RT_FAILURE(rc))
987	return rc;
988
989	return VINF_SUCCESS;
990	}
991
992
993	static DECLCALLBACK(int) ich9pcibridgeRegister(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, const char *pszName, int iDev)
994	{
995
996	PICH9PCIBUS pBus = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
997
998	/*
999	* Check input.
1000	*/
1001	if ( !pszName
1002	\|\| !pPciDev
1003	\|\| iDev >= (int)RT_ELEMENTS(pBus->apDevices))
1004	{
1005	AssertMsgFailed(("Invalid argument! pszName=%s pPciDev=%p iDev=%d\n", pszName, pPciDev, iDev));
1006	return VERR_INVALID_PARAMETER;
1007	}
1008
1009	/*
1010	* Register the device.
1011	*/
1012	return ich9pciRegisterInternal(pBus, iDev, pPciDev, pszName);
1013	}
1014
1015	static DECLCALLBACK(int) ich9pciIORegionRegister(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iRegion, RTGCPHYS cbRegion,
1016	PCIADDRESSSPACE enmType, PFNPCIIOREGIONMAP pfnCallback)
1017	{
1018	NOREF(pDevIns);
1019
1020	/*
1021	* Validate.
1022	*/
1023	AssertMsgReturn( enmType == (PCI_ADDRESS_SPACE_MEM \| PCI_ADDRESS_SPACE_BAR32)
1024	\|\| enmType == (PCI_ADDRESS_SPACE_MEM_PREFETCH \| PCI_ADDRESS_SPACE_BAR32)
1025	\|\| enmType == (PCI_ADDRESS_SPACE_MEM \| PCI_ADDRESS_SPACE_BAR64)
1026	\|\| enmType == (PCI_ADDRESS_SPACE_MEM_PREFETCH \| PCI_ADDRESS_SPACE_BAR64)
1027	\|\| enmType == PCI_ADDRESS_SPACE_IO
1028	,
1029	("Invalid enmType=%#x? Or was this a bitmask after all...\n", enmType),
1030	VERR_INVALID_PARAMETER);
1031	AssertMsgReturn((unsigned)iRegion < PCI_NUM_REGIONS,
1032	("Invalid iRegion=%d PCI_NUM_REGIONS=%d\n", iRegion, PCI_NUM_REGIONS),
1033	VERR_INVALID_PARAMETER);
1034	int iLastSet = ASMBitLastSetU64(cbRegion);
1035	AssertMsgReturn( iLastSet != 0
1036	&& RT_BIT_64(iLastSet - 1) == cbRegion,
1037	("Invalid cbRegion=%RGp iLastSet=%#x (not a power of 2 or 0)\n", cbRegion, iLastSet),
1038	VERR_INVALID_PARAMETER);
1039
1040	Log(("ich9pciIORegionRegister: %s region %d size %RGp type %x\n",
1041	pPciDev->name, iRegion, cbRegion, enmType));
1042
1043	/* Make sure that we haven't marked this region as continuation of 64-bit region. */
1044	Assert(pPciDev->Int.s.aIORegions[iRegion].type != 0xff);
1045
1046	/*
1047	* Register the I/O region.
1048	*/
1049	PPCIIOREGION pRegion = &pPciDev->Int.s.aIORegions[iRegion];
1050	pRegion->addr = INVALID_PCI_ADDRESS;
1051	pRegion->size = cbRegion;
1052	pRegion->type = enmType;
1053	pRegion->map_func = pfnCallback;
1054
1055	if ((enmType & PCI_ADDRESS_SPACE_BAR64) != 0)
1056	{
1057	/* VBOX_PCI_BASE_ADDRESS_5 and VBOX_PCI_ROM_ADDRESS are excluded. */
1058	AssertMsgReturn(iRegion < PCI_NUM_REGIONS - 2,
1059	("Region %d cannot be 64-bit\n", iRegion),
1060	VERR_INVALID_PARAMETER);
1061	/* Mark next region as continuation of this one. */
1062	pPciDev->Int.s.aIORegions[iRegion + 1].type = 0xff;
1063	}
1064
1065	/* Set type in the PCI config space. */
1066	uint32_t u32Value = (uint32_t)enmType & (PCI_ADDRESS_SPACE_IO \| PCI_ADDRESS_SPACE_BAR64 \| PCI_ADDRESS_SPACE_MEM_PREFETCH);
1067	PCIDevSetDWord(pPciDev, ich9pciGetRegionReg(iRegion), u32Value);
1068
1069	return VINF_SUCCESS;
1070	}
1071
1072	static DECLCALLBACK(void) ich9pciSetConfigCallbacks(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PFNPCICONFIGREAD pfnRead, PPFNPCICONFIGREAD ppfnReadOld,
1073	PFNPCICONFIGWRITE pfnWrite, PPFNPCICONFIGWRITE ppfnWriteOld)
1074	{
1075	NOREF(pDevIns);
1076
1077	if (ppfnReadOld)
1078	*ppfnReadOld = pPciDev->Int.s.pfnConfigRead;
1079	pPciDev->Int.s.pfnConfigRead = pfnRead;
1080
1081	if (ppfnWriteOld)
1082	*ppfnWriteOld = pPciDev->Int.s.pfnConfigWrite;
1083	pPciDev->Int.s.pfnConfigWrite = pfnWrite;
1084	}
1085
1086	static int ich9pciR3CommonSaveExec(PICH9PCIBUS pBus, PSSMHANDLE pSSM)
1087	{
1088	/*
1089	* Iterate thru all the devices.
1090	*/
1091	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
1092	{
1093	PPCIDEVICE pDev = pBus->apDevices[i];
1094	if (pDev)
1095	{
1096	/* Device position */
1097	SSMR3PutU32(pSSM, i);
1098	/* PCI config registers */
1099	SSMR3PutMem(pSSM, pDev->config, sizeof(pDev->config));
1100
1101	/* Device flags */
1102	int rc = SSMR3PutU32(pSSM, pDev->Int.s.fFlags);
1103	if (RT_FAILURE(rc))
1104	return rc;
1105
1106	/* IRQ pin state */
1107	rc = SSMR3PutS32(pSSM, pDev->Int.s.uIrqPinState);
1108	if (RT_FAILURE(rc))
1109	return rc;
1110
1111	/* MSI info */
1112	rc = SSMR3PutU8(pSSM, pDev->Int.s.u8MsiCapOffset);
1113	if (RT_FAILURE(rc))
1114	return rc;
1115	rc = SSMR3PutU8(pSSM, pDev->Int.s.u8MsiCapSize);
1116	if (RT_FAILURE(rc))
1117	return rc;
1118
1119	/* MSI-X info */
1120	rc = SSMR3PutU8(pSSM, pDev->Int.s.u8MsixCapOffset);
1121	if (RT_FAILURE(rc))
1122	return rc;
1123	rc = SSMR3PutU8(pSSM, pDev->Int.s.u8MsixCapSize);
1124	if (RT_FAILURE(rc))
1125	return rc;
1126	/* Save MSI-X page state */
1127	if (pDev->Int.s.u8MsixCapOffset != 0)
1128	{
1129	Assert(pDev->Int.s.pMsixPageR3 != NULL);
1130	SSMR3PutMem(pSSM, pDev->Int.s.pMsixPageR3, 0x1000);
1131	if (RT_FAILURE(rc))
1132	return rc;
1133	}
1134	}
1135	}
1136	return SSMR3PutU32(pSSM, UINT32_MAX); /* terminator */
1137	}
1138
1139	static DECLCALLBACK(int) ich9pciR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
1140	{
1141	PICH9PCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
1142
1143	/*
1144	* Bus state data.
1145	*/
1146	SSMR3PutU32(pSSM, pThis->uConfigReg);
1147
1148	/*
1149	* Save IRQ states.
1150	*/
1151	for (int i = 0; i < PCI_APIC_IRQ_PINS; i++)
1152	SSMR3PutU32(pSSM, pThis->uaPciApicIrqLevels[i]);
1153
1154	SSMR3PutU32(pSSM, UINT32_MAX); /* separator */
1155
1156	return ich9pciR3CommonSaveExec(&pThis->aPciBus, pSSM);
1157	}
1158
1159
1160	static DECLCALLBACK(int) ich9pcibridgeR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
1161	{
1162	PICH9PCIBUS pThis = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
1163	return ich9pciR3CommonSaveExec(pThis, pSSM);
1164	}
1165
1166
1167	static DECLCALLBACK(void) ich9pcibridgeConfigWrite(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice, uint32_t u32Address, uint32_t u32Value, unsigned cb)
1168	{
1169	PICH9PCIBUS pBus = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
1170
1171	LogFlowFunc((": pDevIns=%p iBus=%d iDevice=%d u32Address=%u u32Value=%u cb=%d\n", pDevIns, iBus, iDevice, u32Address, u32Value, cb));
1172
1173	/* If the current bus is not the target bus search for the bus which contains the device. */
1174	if (iBus != PCIDevGetByte(&pBus->aPciDev, VBOX_PCI_SECONDARY_BUS))
1175	{
1176	PPCIDEVICE pBridgeDevice = ich9pciFindBridge(pBus, iBus);
1177	if (pBridgeDevice)
1178	{
1179	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigWrite);
1180	pBridgeDevice->Int.s.pfnBridgeConfigWrite(pBridgeDevice->pDevIns, iBus, iDevice, u32Address, u32Value, cb);
1181	}
1182	}
1183	else
1184	{
1185	/* This is the target bus, pass the write to the device. */
1186	PPCIDEVICE pPciDev = pBus->apDevices[iDevice];
1187	if (pPciDev)
1188	{
1189	Log(("%s: %s: addr=%02x val=%08x len=%d\n", __FUNCTION__, pPciDev->name, u32Address, u32Value, cb));
1190	pPciDev->Int.s.pfnConfigWrite(pPciDev, u32Address, u32Value, cb);
1191	}
1192	}
1193	}
1194
1195	static DECLCALLBACK(uint32_t) ich9pcibridgeConfigRead(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice, uint32_t u32Address, unsigned cb)
1196	{
1197	PICH9PCIBUS pBus = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
1198	uint32_t u32Value;
1199
1200	LogFlowFunc((": pDevIns=%p iBus=%d iDevice=%d u32Address=%u cb=%d\n", pDevIns, iBus, iDevice, u32Address, cb));
1201
1202	/* If the current bus is not the target bus search for the bus which contains the device. */
1203	if (iBus != PCIDevGetByte(&pBus->aPciDev, VBOX_PCI_SECONDARY_BUS))
1204	{
1205	PPCIDEVICE pBridgeDevice = ich9pciFindBridge(pBus, iBus);
1206	if (pBridgeDevice)
1207	{
1208	AssertPtr( pBridgeDevice->Int.s.pfnBridgeConfigRead);
1209	u32Value = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->pDevIns, iBus, iDevice, u32Address, cb);
1210	}
1211	else
1212	ich9pciNoMem(&u32Value, 4);
1213	}
1214	else
1215	{
1216	/* This is the target bus, pass the read to the device. */
1217	PPCIDEVICE pPciDev = pBus->apDevices[iDevice];
1218	if (pPciDev)
1219	{
1220	u32Value = pPciDev->Int.s.pfnConfigRead(pPciDev, u32Address, cb);
1221	Log(("%s: %s: u32Address=%02x u32Value=%08x cb=%d\n", __FUNCTION__, pPciDev->name, u32Address, u32Value, cb));
1222	}
1223	else
1224	ich9pciNoMem(&u32Value, 4);
1225	}
1226
1227	return u32Value;
1228	}
1229
1230
1231	/**
1232	* Common routine for restoring the config registers of a PCI device.
1233	*
1234	* @param pDev The PCI device.
1235	* @param pbSrcConfig The configuration register values to be loaded.
1236	* @param fIsBridge Whether this is a bridge device or not.
1237	*/
1238	static void pciR3CommonRestoreConfig(PPCIDEVICE pDev, uint8_t const *pbSrcConfig, bool fIsBridge)
1239	{
1240	/*
1241	* This table defines the fields for normal devices and bridge devices, and
1242	* the order in which they need to be restored.
1243	*/
1244	static const struct PciField
1245	{
1246	uint8_t off;
1247	uint8_t cb;
1248	uint8_t fWritable;
1249	uint8_t fBridge;
1250	const char *pszName;
1251	} s_aFields[] =
1252	{
1253	/* off,cb,fW,fB, pszName */
1254	{ 0x00, 2, 0, 3, "VENDOR_ID" },
1255	{ 0x02, 2, 0, 3, "DEVICE_ID" },
1256	{ 0x06, 2, 1, 3, "STATUS" },
1257	{ 0x08, 1, 0, 3, "REVISION_ID" },
1258	{ 0x09, 1, 0, 3, "CLASS_PROG" },
1259	{ 0x0a, 1, 0, 3, "CLASS_SUB" },
1260	{ 0x0b, 1, 0, 3, "CLASS_BASE" },
1261	{ 0x0c, 1, 1, 3, "CACHE_LINE_SIZE" },
1262	{ 0x0d, 1, 1, 3, "LATENCY_TIMER" },
1263	{ 0x0e, 1, 0, 3, "HEADER_TYPE" },
1264	{ 0x0f, 1, 1, 3, "BIST" },
1265	{ 0x10, 4, 1, 3, "BASE_ADDRESS_0" },
1266	{ 0x14, 4, 1, 3, "BASE_ADDRESS_1" },
1267	{ 0x18, 4, 1, 1, "BASE_ADDRESS_2" },
1268	{ 0x18, 1, 1, 2, "PRIMARY_BUS" }, // fWritable = ??
1269	{ 0x19, 1, 1, 2, "SECONDARY_BUS" }, // fWritable = ??
1270	{ 0x1a, 1, 1, 2, "SUBORDINATE_BUS" }, // fWritable = ??
1271	{ 0x1b, 1, 1, 2, "SEC_LATENCY_TIMER" }, // fWritable = ??
1272	{ 0x1c, 4, 1, 1, "BASE_ADDRESS_3" },
1273	{ 0x1c, 1, 1, 2, "IO_BASE" }, // fWritable = ??
1274	{ 0x1d, 1, 1, 2, "IO_LIMIT" }, // fWritable = ??
1275	{ 0x1e, 2, 1, 2, "SEC_STATUS" }, // fWritable = ??
1276	{ 0x20, 4, 1, 1, "BASE_ADDRESS_4" },
1277	{ 0x20, 2, 1, 2, "MEMORY_BASE" }, // fWritable = ??
1278	{ 0x22, 2, 1, 2, "MEMORY_LIMIT" }, // fWritable = ??
1279	{ 0x24, 4, 1, 1, "BASE_ADDRESS_5" },
1280	{ 0x24, 2, 1, 2, "PREF_MEMORY_BASE" }, // fWritable = ??
1281	{ 0x26, 2, 1, 2, "PREF_MEMORY_LIMIT" }, // fWritable = ??
1282	{ 0x28, 4, 1, 1, "CARDBUS_CIS" }, // fWritable = ??
1283	{ 0x28, 4, 1, 2, "PREF_BASE_UPPER32" }, // fWritable = ??
1284	{ 0x2c, 2, 0, 1, "SUBSYSTEM_VENDOR_ID" },// fWritable = !?
1285	{ 0x2c, 4, 1, 2, "PREF_LIMIT_UPPER32" },// fWritable = ??
1286	{ 0x2e, 2, 0, 1, "SUBSYSTEM_ID" }, // fWritable = !?
1287	{ 0x30, 4, 1, 1, "ROM_ADDRESS" }, // fWritable = ?!
1288	{ 0x30, 2, 1, 2, "IO_BASE_UPPER16" }, // fWritable = ?!
1289	{ 0x32, 2, 1, 2, "IO_LIMIT_UPPER16" }, // fWritable = ?!
1290	{ 0x34, 4, 0, 3, "CAPABILITY_LIST" }, // fWritable = !? cb=!?
1291	{ 0x38, 4, 1, 1, "RESERVED_38" }, // ???
1292	{ 0x38, 4, 1, 2, "ROM_ADDRESS_BR" }, // fWritable = !? cb=!? fBridge=!?
1293	{ 0x3c, 1, 1, 3, "INTERRUPT_LINE" }, // fBridge=??
1294	{ 0x3d, 1, 0, 3, "INTERRUPT_PIN" }, // fBridge=??
1295	{ 0x3e, 1, 0, 1, "MIN_GNT" },
1296	{ 0x3e, 2, 1, 2, "BRIDGE_CONTROL" }, // fWritable = !?
1297	{ 0x3f, 1, 0, 1, "MAX_LAT" },
1298	/* The COMMAND register must come last as it requires the ADDRESS
1299	registers to be restored before we pretent to change it from 0 to
1300	whatever value the guest assigned it. */
1301	{ 0x04, 2, 1, 3, "COMMAND" },
1302	};
1303
1304	#ifdef RT_STRICT
1305	/* Check that we've got full register coverage. */
1306	uint32_t bmDevice[0x40 / 32];
1307	uint32_t bmBridge[0x40 / 32];
1308	RT_ZERO(bmDevice);
1309	RT_ZERO(bmBridge);
1310	for (uint32_t i = 0; i < RT_ELEMENTS(s_aFields); i++)
1311	{
1312	uint8_t off = s_aFields[i].off;
1313	uint8_t cb = s_aFields[i].cb;
1314	uint8_t f = s_aFields[i].fBridge;
1315	while (cb-- > 0)
1316	{
1317	if (f & 1) AssertMsg(!ASMBitTest(bmDevice, off), ("%#x\n", off));
1318	if (f & 2) AssertMsg(!ASMBitTest(bmBridge, off), ("%#x\n", off));
1319	if (f & 1) ASMBitSet(bmDevice, off);
1320	if (f & 2) ASMBitSet(bmBridge, off);
1321	off++;
1322	}
1323	}
1324	for (uint32_t off = 0; off < 0x40; off++)
1325	{
1326	AssertMsg(ASMBitTest(bmDevice, off), ("%#x\n", off));
1327	AssertMsg(ASMBitTest(bmBridge, off), ("%#x\n", off));
1328	}
1329	#endif
1330
1331	/*
1332	* Loop thru the fields covering the 64 bytes of standard registers.
1333	*/
1334	uint8_t const fBridge = fIsBridge ? 2 : 1;
1335	Assert(!pciDevIsPassthrough(pDev));
1336	uint8_t *pbDstConfig = &pDev->config[0];
1337
1338	for (uint32_t i = 0; i < RT_ELEMENTS(s_aFields); i++)
1339	if (s_aFields[i].fBridge & fBridge)
1340	{
1341	uint8_t const off = s_aFields[i].off;
1342	uint8_t const cb = s_aFields[i].cb;
1343	uint32_t u32Src;
1344	uint32_t u32Dst;
1345	switch (cb)
1346	{
1347	case 1:
1348	u32Src = pbSrcConfig[off];
1349	u32Dst = pbDstConfig[off];
1350	break;
1351	case 2:
1352	u32Src = (uint16_t const )&pbSrcConfig[off];
1353	u32Dst = (uint16_t const )&pbDstConfig[off];
1354	break;
1355	case 4:
1356	u32Src = (uint32_t const )&pbSrcConfig[off];
1357	u32Dst = (uint32_t const )&pbDstConfig[off];
1358	break;
1359	default:
1360	AssertFailed();
1361	continue;
1362	}
1363
1364	if ( u32Src != u32Dst
1365	\|\| off == VBOX_PCI_COMMAND)
1366	{
1367	if (u32Src != u32Dst)
1368	{
1369	if (!s_aFields[i].fWritable)
1370	LogRel(("PCI: %8s/%u: %2u-bit field %s: %x -> %x - !READ ONLY!\n",
1371	pDev->name, pDev->pDevIns->iInstance, cb*8, s_aFields[i].pszName, u32Dst, u32Src));
1372	else
1373	LogRel(("PCI: %8s/%u: %2u-bit field %s: %x -> %x\n",
1374	pDev->name, pDev->pDevIns->iInstance, cb*8, s_aFields[i].pszName, u32Dst, u32Src));
1375	}
1376	if (off == VBOX_PCI_COMMAND)
1377	PCIDevSetCommand(pDev, 0); /* For remapping, see ich9pciR3CommonLoadExec. */
1378	pDev->Int.s.pfnConfigWrite(pDev, off, u32Src, cb);
1379	}
1380	}
1381
1382	/*
1383	* The device dependent registers.
1384	*
1385	* We will not use ConfigWrite here as we have no clue about the size
1386	* of the registers, so the device is responsible for correctly
1387	* restoring functionality governed by these registers.
1388	*/
1389	for (uint32_t off = 0x40; off < sizeof(pDev->config); off++)
1390	if (pbDstConfig[off] != pbSrcConfig[off])
1391	{
1392	LogRel(("PCI: %8s/%u: register %02x: %02x -> %02x\n",
1393	pDev->name, pDev->pDevIns->iInstance, off, pbDstConfig[off], pbSrcConfig[off])); /** @todo make this Log() later. */
1394	pbDstConfig[off] = pbSrcConfig[off];
1395	}
1396	}
1397
1398	/**
1399	* Common worker for ich9pciR3LoadExec and ich9pcibridgeR3LoadExec.
1400	*
1401	* @returns VBox status code.
1402	* @param pBus The bus which data is being loaded.
1403	* @param pSSM The saved state handle.
1404	* @param uVersion The data version.
1405	* @param uPass The pass.
1406	*/
1407	static DECLCALLBACK(int) ich9pciR3CommonLoadExec(PICH9PCIBUS pBus, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1408	{
1409	uint32_t u32;
1410	uint32_t i;
1411	int rc;
1412
1413	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
1414	if (uVersion != VBOX_ICH9PCI_SAVED_STATE_VERSION_CURRENT)
1415	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1416
1417	/*
1418	* Iterate thru all the devices and write 0 to the COMMAND register so
1419	* that all the memory is unmapped before we start restoring the saved
1420	* mapping locations.
1421	*
1422	* The register value is restored afterwards so we can do proper
1423	* LogRels in pciR3CommonRestoreConfig.
1424	*/
1425	for (i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
1426	{
1427	PPCIDEVICE pDev = pBus->apDevices[i];
1428	if (pDev)
1429	{
1430	uint16_t u16 = PCIDevGetCommand(pDev);
1431	pDev->Int.s.pfnConfigWrite(pDev, VBOX_PCI_COMMAND, 0, 2);
1432	PCIDevSetCommand(pDev, u16);
1433	Assert(PCIDevGetCommand(pDev) == u16);
1434	}
1435	}
1436
1437	void *pvMsixPage = RTMemTmpAllocZ(0x1000);
1438	AssertReturn(pvMsixPage, VERR_NO_TMP_MEMORY);
1439
1440	/*
1441	* Iterate all the devices.
1442	*/
1443	for (i = 0;; i++)
1444	{
1445	PPCIDEVICE pDev;
1446	PCIDEVICE DevTmp;
1447
1448	/* index / terminator */
1449	rc = SSMR3GetU32(pSSM, &u32);
1450	if (RT_FAILURE(rc))
1451	break;
1452	if (u32 == (uint32_t)~0)
1453	break;
1454	AssertMsgBreak(u32 < RT_ELEMENTS(pBus->apDevices) && u32 >= i, ("u32=%#x i=%#x\n", u32, i));
1455
1456	/* skip forward to the device checking that no new devices are present. */
1457	for (; i < u32; i++)
1458	{
1459	pDev = pBus->apDevices[i];
1460	if (pDev)
1461	{
1462	LogRel(("PCI: New device in slot %#x, %s (vendor=%#06x device=%#06x)\n", i, pDev->name,
1463	PCIDevGetVendorId(pDev), PCIDevGetDeviceId(pDev)));
1464	if (SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT)
1465	{
1466	rc = SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("New device in slot %#x, %s (vendor=%#06x device=%#06x)"),
1467	i, pDev->name, PCIDevGetVendorId(pDev), PCIDevGetDeviceId(pDev));
1468	break;
1469	}
1470	}
1471	}
1472	if (RT_FAILURE(rc))
1473	break;
1474
1475	/* get the data */
1476	DevTmp.Int.s.fFlags = 0;
1477	DevTmp.Int.s.u8MsiCapOffset = 0;
1478	DevTmp.Int.s.u8MsiCapSize = 0;
1479	DevTmp.Int.s.u8MsixCapOffset = 0;
1480	DevTmp.Int.s.u8MsixCapSize = 0;
1481	DevTmp.Int.s.uIrqPinState = ~0; /* Invalid value in case we have an older saved state to force a state change in pciSetIrq. */
1482	SSMR3GetMem(pSSM, DevTmp.config, sizeof(DevTmp.config));
1483
1484	SSMR3GetU32(pSSM, &DevTmp.Int.s.fFlags);
1485	SSMR3GetS32(pSSM, &DevTmp.Int.s.uIrqPinState);
1486	SSMR3GetU8(pSSM, &DevTmp.Int.s.u8MsiCapOffset);
1487	SSMR3GetU8(pSSM, &DevTmp.Int.s.u8MsiCapSize);
1488	SSMR3GetU8(pSSM, &DevTmp.Int.s.u8MsixCapOffset);
1489	rc = SSMR3GetU8(pSSM, &DevTmp.Int.s.u8MsixCapSize);
1490	if (RT_FAILURE(rc))
1491	break;
1492
1493	/* Load MSI-X page state */
1494	if (DevTmp.Int.s.u8MsixCapOffset != 0)
1495	{
1496	Assert(pvMsixPage != NULL);
1497	rc = SSMR3GetMem(pSSM, pvMsixPage, 0x1000);
1498	if (RT_FAILURE(rc))
1499	break;
1500	}
1501
1502	/* check that it's still around. */
1503	pDev = pBus->apDevices[i];
1504	if (!pDev)
1505	{
1506	LogRel(("PCI: Device in slot %#x has been removed! vendor=%#06x device=%#06x\n", i,
1507	PCIDevGetVendorId(&DevTmp), PCIDevGetDeviceId(&DevTmp)));
1508	if (SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT)
1509	{
1510	rc = SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Device in slot %#x has been removed! vendor=%#06x device=%#06x"),
1511	i, PCIDevGetVendorId(&DevTmp), PCIDevGetDeviceId(&DevTmp));
1512	break;
1513	}
1514	continue;
1515	}
1516
1517	/* match the vendor id assuming that this will never be changed. */
1518	if (PCIDevGetVendorId(&DevTmp) != PCIDevGetVendorId(pDev))
1519	{
1520	rc = SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Device in slot %#x (%s) vendor id mismatch! saved=%.4Rhxs current=%.4Rhxs"),
1521	i, pDev->name, PCIDevGetVendorId(&DevTmp), PCIDevGetVendorId(pDev));
1522	break;
1523	}
1524
1525	/* commit the loaded device config. */
1526	Assert(!pciDevIsPassthrough(pDev));
1527	pciR3CommonRestoreConfig(pDev, &DevTmp.config[0], false ); /** @todo fix bridge fun! */
1528
1529	pDev->Int.s.uIrqPinState = DevTmp.Int.s.uIrqPinState;
1530	pDev->Int.s.u8MsiCapOffset = DevTmp.Int.s.u8MsiCapOffset;
1531	pDev->Int.s.u8MsiCapSize = DevTmp.Int.s.u8MsiCapSize;
1532	pDev->Int.s.u8MsixCapOffset = DevTmp.Int.s.u8MsixCapOffset;
1533	pDev->Int.s.u8MsixCapSize = DevTmp.Int.s.u8MsixCapSize;
1534	if (DevTmp.Int.s.u8MsixCapSize != 0)
1535	{
1536	Assert(pDev->Int.s.pMsixPageR3 != NULL);
1537	memcpy(pDev->Int.s.pMsixPageR3, pvMsixPage, 0x1000);
1538	}
1539	}
1540
1541	RTMemTmpFree(pvMsixPage);
1542
1543	return rc;
1544	}
1545
1546	static DECLCALLBACK(int) ich9pciR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1547	{
1548	PICH9PCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
1549	PICH9PCIBUS pBus = &pThis->aPciBus;
1550	uint32_t u32;
1551	int rc;
1552
1553	/* We ignore this version as there's no saved state with it anyway */
1554	if (uVersion == VBOX_ICH9PCI_SAVED_STATE_VERSION_NOMSI)
1555	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1556	if (uVersion > VBOX_ICH9PCI_SAVED_STATE_VERSION_MSI)
1557	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1558
1559	/*
1560	* Bus state data.
1561	*/
1562	SSMR3GetU32(pSSM, &pThis->uConfigReg);
1563
1564	/*
1565	* Load IRQ states.
1566	*/
1567	for (int i = 0; i < PCI_APIC_IRQ_PINS; i++)
1568	SSMR3GetU32(pSSM, (uint32_t*)&pThis->uaPciApicIrqLevels[i]);
1569
1570	/* separator */
1571	rc = SSMR3GetU32(pSSM, &u32);
1572	if (RT_FAILURE(rc))
1573	return rc;
1574	if (u32 != (uint32_t)~0)
1575	AssertMsgFailedReturn(("u32=%#x\n", u32), rc);
1576
1577	return ich9pciR3CommonLoadExec(pBus, pSSM, uVersion, uPass);
1578	}
1579
1580	static DECLCALLBACK(int) ich9pcibridgeR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1581	{
1582	PICH9PCIBUS pThis = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
1583	if (uVersion > VBOX_ICH9PCI_SAVED_STATE_VERSION_MSI)
1584	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1585	return ich9pciR3CommonLoadExec(pThis, pSSM, uVersion, uPass);
1586	}
1587
1588
1589	/*
1590	* Perform imeediate read of configuration space register.
1591	* Cannot be rescheduled, as already in R3.
1592	*/
1593	static uint32_t ich9pciConfigRead(PICH9PCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t len)
1594	{
1595	PciAddress aPciAddr;
1596	aPciAddr.iBus = uBus;
1597	aPciAddr.iDeviceFunc = uDevFn;
1598	aPciAddr.iRegister = addr;
1599
1600	uint32_t u32Val;
1601	int rc = ich9pciDataReadAddr(pGlobals, &aPciAddr, len, &u32Val, VERR_INTERNAL_ERROR);
1602	AssertRC(rc);
1603
1604	return u32Val;
1605	}
1606
1607
1608	/*
1609	* Perform imeediate write to configuration space register.
1610	* Cannot be rescheduled, as already in R3.
1611	*/
1612	static void ich9pciConfigWrite(PICH9PCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t val, uint32_t len)
1613	{
1614	PciAddress aPciAddr;
1615	aPciAddr.iBus = uBus;
1616	aPciAddr.iDeviceFunc = uDevFn;
1617	aPciAddr.iRegister = addr;
1618
1619	int rc = ich9pciDataWriteAddr(pGlobals, &aPciAddr, val, len, VERR_INTERNAL_ERROR);
1620	AssertRC(rc);
1621	}
1622
1623
1624	static void ich9pciSetRegionAddress(PICH9PCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, int iRegion, uint64_t addr)
1625	{
1626	uint32_t uReg = ich9pciGetRegionReg(iRegion);
1627
1628	/* Read memory type first. */
1629	uint8_t uResourceType = ich9pciConfigRead(pGlobals, uBus, uDevFn, uReg, 1);
1630	bool f64Bit = (uResourceType & ((uint8_t)(PCI_ADDRESS_SPACE_BAR64 \| PCI_ADDRESS_SPACE_IO)))
1631	== PCI_ADDRESS_SPACE_BAR64;
1632
1633	Log(("Set region address: %02x:%02x.%d region %d address=%RX64%s\n",
1634	uBus, uDevFn >> 3, uDevFn & 7, iRegion, addr, f64Bit ? " (64-bit)" : ""));
1635
1636	/* Write address of the device. */
1637	ich9pciConfigWrite(pGlobals, uBus, uDevFn, uReg, (uint32_t)addr, 4);
1638	if (f64Bit)
1639	ich9pciConfigWrite(pGlobals, uBus, uDevFn, uReg + 4, (uint32_t)(addr >> 32), 4);
1640	}
1641
1642
1643	static void ich9pciBiosInitBridge(PICH9PCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn)
1644	{
1645	Log(("BIOS init bridge: %02x::%02x.%d\n", uBus, uDevFn >> 3, uDevFn & 7));
1646
1647	/*
1648	* The I/O range for the bridge must be aligned to a 4KB boundary.
1649	* This does not change anything really as the access to the device is not going
1650	* through the bridge but we want to be compliant to the spec.
1651	*/
1652	if ((pGlobals->uPciBiosIo % 4096) != 0)
1653	{
1654	pGlobals->uPciBiosIo = RT_ALIGN_32(pGlobals->uPciBiosIo, 4*1024);
1655	Log(("%s: Aligned I/O start address. New address %#x\n", __FUNCTION__, pGlobals->uPciBiosIo));
1656	}
1657	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_IO_BASE, (pGlobals->uPciBiosIo >> 8) & 0xf0, 1);
1658
1659	/* The MMIO range for the bridge must be aligned to a 1MB boundary. */
1660	if ((pGlobals->uPciBiosMmio % (1024 * 1024)) != 0)
1661	{
1662	pGlobals->uPciBiosMmio = RT_ALIGN_32(pGlobals->uPciBiosMmio, 1024*1024);
1663	Log(("%s: Aligned MMIO start address. New address %#x\n", __FUNCTION__, pGlobals->uPciBiosMmio));
1664	}
1665	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_MEMORY_BASE, (pGlobals->uPciBiosMmio >> 16) & UINT32_C(0xffff0), 2);
1666
1667	/* Save values to compare later to. */
1668	uint32_t u32IoAddressBase = pGlobals->uPciBiosIo;
1669	uint32_t u32MMIOAddressBase = pGlobals->uPciBiosMmio;
1670	uint8_t uBridgeBus = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_SECONDARY_BUS, 1);
1671
1672	/* Init devices behind the bridge and possibly other bridges as well. */
1673	for (int iDev = 0; iDev <= 255; iDev++)
1674	ich9pciBiosInitDevice(pGlobals, uBridgeBus, iDev);
1675
1676	/*
1677	* Set I/O limit register. If there is no device with I/O space behind the bridge
1678	* we set a lower value than in the base register.
1679	* The result with a real bridge is that no I/O transactions are passed to the secondary
1680	* interface. Again this doesn't really matter here but we want to be compliant to the spec.
1681	*/
1682	if ((u32IoAddressBase != pGlobals->uPciBiosIo) && ((pGlobals->uPciBiosIo % 4096) != 0))
1683	{
1684	/* The upper boundary must be one byte less than a 4KB boundary. */
1685	pGlobals->uPciBiosIo = RT_ALIGN_32(pGlobals->uPciBiosIo, 4*1024);
1686	}
1687
1688	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_IO_LIMIT, ((pGlobals->uPciBiosIo >> 8) & 0xf0) - 1, 1);
1689
1690	/* Same with the MMIO limit register but with 1MB boundary here. */
1691	if ((u32MMIOAddressBase != pGlobals->uPciBiosMmio) && ((pGlobals->uPciBiosMmio % (1024 * 1024)) != 0))
1692	{
1693	/* The upper boundary must be one byte less than a 1MB boundary. */
1694	pGlobals->uPciBiosMmio = RT_ALIGN_32(pGlobals->uPciBiosMmio, 1024*1024);
1695	}
1696	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_MEMORY_LIMIT, ((pGlobals->uPciBiosMmio >> 16) & UINT32_C(0xfff0)) - 1, 2);
1697
1698	/*
1699	* Set the prefetch base and limit registers. We currently have no device with a prefetchable region
1700	* which may be behind a bridge. That's why it is unconditionally disabled here atm by writing a higher value into
1701	* the base register than in the limit register.
1702	*/
1703	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_MEMORY_BASE, 0xfff0, 2);
1704	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_MEMORY_LIMIT, 0x0, 2);
1705	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_BASE_UPPER32, 0x00, 4);
1706	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_LIMIT_UPPER32, 0x00, 4);
1707	}
1708
1709	static void ich9pciBiosInitDevice(PICH9PCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn)
1710	{
1711	uint16_t uDevClass, uVendor, uDevice;
1712	uint8_t uCmd;
1713
1714	uDevClass = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_CLASS_DEVICE, 2);
1715	uVendor = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_VENDOR_ID, 2);
1716	uDevice = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_DEVICE_ID, 2);
1717
1718	/* If device is present */
1719	if (uVendor == 0xffff)
1720	return;
1721
1722	Log(("BIOS init device: %02x:%02x.%d\n", uBus, uDevFn >> 3, uDevFn & 7));
1723
1724	switch (uDevClass)
1725	{
1726	case 0x0101:
1727	/* IDE controller */
1728	ich9pciConfigWrite(pGlobals, uBus, uDevFn, 0x40, 0x8000, 2); /* enable IDE0 */
1729	ich9pciConfigWrite(pGlobals, uBus, uDevFn, 0x42, 0x8000, 2); /* enable IDE1 */
1730	goto default_map;
1731	break;
1732	case 0x0300:
1733	/* VGA controller */
1734
1735	/* NB: Default Bochs VGA LFB address is 0xE0000000. Old guest
1736	* software may break if the framebuffer isn't mapped there.
1737	*/
1738
1739	/*
1740	* Legacy VGA I/O ports are implicitly decoded by a VGA class device. But
1741	* only the framebuffer (i.e., a memory region) is explicitly registered via
1742	* ich9pciSetRegionAddress, so don't forget to enable I/O decoding.
1743	*/
1744	uCmd = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_COMMAND, 1);
1745	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_COMMAND,
1746	uCmd \| PCI_COMMAND_IOACCESS,
1747	1);
1748	goto default_map;
1749	break;
1750	case 0x0604:
1751	/* PCI-to-PCI bridge. */
1752	AssertMsg(pGlobals->uBus < 255, ("Too many bridges on the bus\n"));
1753	ich9pciBiosInitBridge(pGlobals, uBus, uDevFn);
1754	break;
1755	default:
1756	default_map:
1757	{
1758	/* default memory mappings */
1759	bool fActiveMemRegion = false;
1760	bool fActiveIORegion = false;
1761	/*
1762	* We ignore ROM region here.
1763	*/
1764	for (int iRegion = 0; iRegion < (PCI_NUM_REGIONS-1); iRegion++)
1765	{
1766	uint32_t u32Address = ich9pciGetRegionReg(iRegion);
1767
1768	/* Calculate size - we write all 1s into the BAR, and then evaluate which bits
1769	are cleared. */
1770	uint8_t u8ResourceType = ich9pciConfigRead(pGlobals, uBus, uDevFn, u32Address, 1);
1771
1772	bool f64Bit = (u8ResourceType & PCI_ADDRESS_SPACE_BAR64) != 0;
1773	bool fIsPio = ((u8ResourceType & PCI_COMMAND_IOACCESS) == PCI_COMMAND_IOACCESS);
1774	uint64_t cbRegSize64 = 0;
1775
1776	if (f64Bit)
1777	{
1778	ich9pciConfigWrite(pGlobals, uBus, uDevFn, u32Address, UINT32_C(0xffffffff), 4);
1779	ich9pciConfigWrite(pGlobals, uBus, uDevFn, u32Address+4, UINT32_C(0xffffffff), 4);
1780	cbRegSize64 = ich9pciConfigRead(pGlobals, uBus, uDevFn, u32Address, 4);
1781	cbRegSize64 \|= ((uint64_t)ich9pciConfigRead(pGlobals, uBus, uDevFn, u32Address+4, 4) << 32);
1782	cbRegSize64 &= ~UINT64_C(0x0f);
1783	cbRegSize64 = (~cbRegSize64) + 1;
1784
1785	/* No 64-bit PIO regions possible. */
1786	#ifndef DEBUG_bird /* EFI triggers this for DevAHCI. */
1787	AssertMsg((u8ResourceType & PCI_COMMAND_IOACCESS) == 0, ("type=%#x rgn=%d\n", u8ResourceType, iRegion));
1788	#endif
1789	}
1790	else
1791	{
1792	uint32_t cbRegSize32;
1793	ich9pciConfigWrite(pGlobals, uBus, uDevFn, u32Address, UINT32_C(0xffffffff), 4);
1794	cbRegSize32 = ich9pciConfigRead(pGlobals, uBus, uDevFn, u32Address, 4);
1795
1796	/* Clear resource information depending on resource type. */
1797	if (fIsPio) /* PIO */
1798	cbRegSize32 &= ~UINT32_C(0x01);
1799	else /* MMIO */
1800	cbRegSize32 &= ~UINT32_C(0x0f);
1801
1802	/*
1803	* Invert all bits and add 1 to get size of the region.
1804	* (From PCI implementation note)
1805	*/
1806	if (fIsPio && (cbRegSize32 & UINT32_C(0xffff0000)) == 0)
1807	cbRegSize32 = (~(cbRegSize32 \| UINT32_C(0xffff0000))) + 1;
1808	else
1809	cbRegSize32 = (~cbRegSize32) + 1;
1810
1811	cbRegSize64 = cbRegSize32;
1812	}
1813	Log2(("%s: Size of region %u for device %d on bus %d is %lld\n", __FUNCTION__, iRegion, uDevFn, uBus, cbRegSize64));
1814
1815	if (cbRegSize64)
1816	{
1817	/* Try 32-bit base first. */
1818	uint32_t* paddr = fIsPio ? &pGlobals->uPciBiosIo : &pGlobals->uPciBiosMmio;
1819	uint64_t uNew = *paddr;
1820	/* Align starting address to region size. */
1821	uNew = (uNew + cbRegSize64 - 1) & ~(cbRegSize64 - 1);
1822	if (fIsPio)
1823	uNew &= UINT32_C(0xffff);
1824	/* Unconditionally exclude I/O-APIC/HPET/ROM. Pessimistic, but better than causing a mess. */
1825	if ( !uNew
1826	\|\| (uNew <= UINT32_C(0xffffffff) && uNew + cbRegSize64 - 1 >= UINT32_C(0xfec00000))
1827	\|\| uNew >= _4G)
1828	{
1829	if (f64Bit)
1830	{
1831	/* Map a 64-bit region above 4GB. */
1832	Assert(!fIsPio);
1833	uNew = pGlobals->uPciBiosMmio64;
1834	/* Align starting address to region size. */
1835	uNew = (uNew + cbRegSize64 - 1) & ~(cbRegSize64 - 1);
1836	LogFunc(("Start address of 64-bit MMIO region %u/%u is %#llx\n", iRegion, iRegion + 1, uNew));
1837	ich9pciSetRegionAddress(pGlobals, uBus, uDevFn, iRegion, uNew);
1838	fActiveMemRegion = true;
1839	pGlobals->uPciBiosMmio64 = uNew + cbRegSize64;
1840	Log2Func(("New 64-bit address is %#llx\n", pGlobals->uPciBiosMmio64));
1841	}
1842	else
1843	{
1844	LogRel(("PCI: no space left for BAR%u of device %u/%u/%u (vendor=%#06x device=%#06x)\n",
1845	iRegion, uBus, uDevFn >> 3, uDevFn & 7, uVendor, uDevice)); /** @todo make this a VM start failure later. */
1846	/* Undo the mapping mess caused by the size probing. */
1847	ich9pciConfigWrite(pGlobals, uBus, uDevFn, u32Address, UINT32_C(0), 4);
1848	}
1849	}
1850	else
1851	{
1852	LogFunc(("Start address of %s region %u is %#x\n", (fIsPio ? "I/O" : "MMIO"), iRegion, uNew));
1853	ich9pciSetRegionAddress(pGlobals, uBus, uDevFn, iRegion, uNew);
1854	if (fIsPio)
1855	fActiveIORegion = true;
1856	else
1857	fActiveMemRegion = true;
1858	*paddr = uNew + cbRegSize64;
1859	Log2Func(("New 32-bit address is %#x\n", *paddr));
1860	}
1861
1862	if (f64Bit)
1863	iRegion++; /* skip next region */
1864	}
1865	}
1866
1867	/* Update the command word appropriately. */
1868	uCmd = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_COMMAND, 2);
1869	if (fActiveMemRegion)
1870	uCmd \|= PCI_COMMAND_MEMACCESS; /* Enable MMIO access. */
1871	if (fActiveIORegion)
1872	uCmd \|= PCI_COMMAND_IOACCESS; /* Enable I/O space access. */
1873	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_COMMAND, uCmd, 2);
1874	break;
1875	}
1876	}
1877
1878	/* map the interrupt */
1879	uint32_t iPin = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_INTERRUPT_PIN, 1);
1880	if (iPin != 0)
1881	{
1882	iPin--;
1883
1884	if (uBus != 0)
1885	{
1886	/* Find bus this device attached to. */
1887	PICH9PCIBUS pBus = &pGlobals->aPciBus;
1888	while (1)
1889	{
1890	PPCIDEVICE pBridge = ich9pciFindBridge(pBus, uBus);
1891	if (!pBridge)
1892	{
1893	Assert(false);
1894	break;
1895	}
1896	if (uBus == PCIDevGetByte(pBridge, VBOX_PCI_SECONDARY_BUS))
1897	{
1898	/* OK, found bus this device attached to. */
1899	break;
1900	}
1901	pBus = PDMINS_2_DATA(pBridge->pDevIns, PICH9PCIBUS);
1902	}
1903
1904	/* We need to go up to the host bus to see which irq pin this
1905	* device will use there. See logic in ich9pcibridgeSetIrq().
1906	*/
1907	while (pBus->iBus != 0)
1908	{
1909	/* Get the pin the device would assert on the bridge. */
1910	iPin = ((pBus->aPciDev.devfn >> 3) + iPin) & 3;
1911	pBus = pBus->aPciDev.Int.s.pBusR3;
1912	};
1913	}
1914
1915	int iIrq = aPciIrqs[ich9pciSlotGetPirq(uBus, uDevFn, iPin)];
1916	Log(("Using pin %d and IRQ %d for device %02x:%02x.%d\n",
1917	iPin, iIrq, uBus, uDevFn>>3, uDevFn&7));
1918	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_INTERRUPT_LINE, iIrq, 1);
1919	}
1920	}
1921
1922	/**
1923	* Initializes bridges registers used for routing.
1924	*
1925	* @returns nothing.
1926	* @param pGlobals Global device instance data used to generate unique bus numbers.
1927	* @param pBus The PCI bus to initialize.
1928	* @param uBusPrimary The primary bus number the bus is connected to.
1929	* @param uBusSecondary The secondary bus number, i.e. the bus number behind the bridge.
1930	*/
1931	static void ich9pciInitBridgeTopology(PICH9PCIGLOBALS pGlobals, PICH9PCIBUS pBus, unsigned uBusPrimary,
1932	unsigned uBusSecondary)
1933	{
1934	PPCIDEVICE pBridgeDev = &pBus->aPciDev;
1935
1936	/* Set only if we are not on the root bus, it has no primary bus attached. */
1937	if (uBusSecondary != 0)
1938	{
1939	PCIDevSetByte(pBridgeDev, VBOX_PCI_PRIMARY_BUS, uBusPrimary);
1940	PCIDevSetByte(pBridgeDev, VBOX_PCI_SECONDARY_BUS, uBusSecondary);
1941	}
1942
1943	for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
1944	{
1945	PPCIDEVICE pBridge = pBus->papBridgesR3[iBridge];
1946	AssertMsg(pBridge && pciDevIsPci2PciBridge(pBridge),
1947	("Device is not a PCI bridge but on the list of PCI bridges\n"));
1948	PICH9PCIBUS pChildBus = PDMINS_2_DATA(pBridge->pDevIns, PICH9PCIBUS);
1949	pGlobals->uBus++;
1950	ich9pciInitBridgeTopology(pGlobals, pChildBus, uBusSecondary, pGlobals->uBus);
1951	}
1952	PCIDevSetByte(pBridgeDev, VBOX_PCI_SUBORDINATE_BUS, pGlobals->uBus);
1953	Log2(("ich9pciInitBridgeTopology: for bus %p: primary=%d secondary=%d subordinate=%d\n",
1954	pBus,
1955	PCIDevGetByte(pBridgeDev, VBOX_PCI_PRIMARY_BUS),
1956	PCIDevGetByte(pBridgeDev, VBOX_PCI_SECONDARY_BUS),
1957	PCIDevGetByte(pBridgeDev, VBOX_PCI_SUBORDINATE_BUS)
1958	));
1959	}
1960
1961
1962	static DECLCALLBACK(int) ich9pciFakePCIBIOS(PPDMDEVINS pDevIns)
1963	{
1964	PICH9PCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
1965	PVM pVM = PDMDevHlpGetVM(pDevIns);
1966	uint32_t const cbBelow4GB = MMR3PhysGetRamSizeBelow4GB(pVM);
1967	uint64_t const cbAbove4GB = MMR3PhysGetRamSizeAbove4GB(pVM);
1968
1969	/*
1970	* Set the start addresses.
1971	*/
1972	pGlobals->uPciBiosIo = 0xd000;
1973	pGlobals->uPciBiosMmio = cbBelow4GB;
1974	pGlobals->uPciBiosMmio64 = cbAbove4GB + _4G;
1975	pGlobals->uBus = 0;
1976
1977	/* NB: Assume that if MMIO range is enabled, it is at the bottom of the memory hole. */
1978	if (pGlobals->u64PciConfigMMioAddress)
1979	{
1980	AssertRelease(pGlobals->u64PciConfigMMioAddress >= cbBelow4GB);
1981	pGlobals->uPciBiosMmio = pGlobals->u64PciConfigMMioAddress + pGlobals->u64PciConfigMMioLength;
1982	}
1983	Log(("cbBelow4GB: %lX, uPciBiosMmio: %lX, cbAbove4GB: %llX\n", cbBelow4GB, pGlobals->uPciBiosMmio, cbAbove4GB));
1984
1985	/*
1986	* Assign bridge topology, for further routing to work.
1987	*/
1988	PICH9PCIBUS pBus = &pGlobals->aPciBus;
1989	ich9pciInitBridgeTopology(pGlobals, pBus, 0, 0);
1990
1991	/*
1992	* Init the devices.
1993	*/
1994	for (int i = 0; i < 256; i++)
1995	ich9pciBiosInitDevice(pGlobals, 0, i);
1996
1997	return VINF_SUCCESS;
1998	}
1999
2000
2001	/*
2002	* Configuration space read callback (PCIDEVICEINT::pfnConfigRead) for
2003	* connected devices.
2004	*/
2005	static DECLCALLBACK(uint32_t) ich9pciConfigReadDev(PCIDevice *aDev, uint32_t u32Address, unsigned len)
2006	{
2007	if ((u32Address + len) > 256 && (u32Address + len) < 4096)
2008	{
2009	LogRel(("PCI: %8s/%u: Read from extended register %d fallen back to generic code\n",
2010	aDev->name, aDev->pDevIns->iInstance, u32Address));
2011	return 0;
2012	}
2013
2014	AssertMsgReturn(u32Address + len <= 256, ("Read after the end of PCI config space\n"),
2015	0);
2016	if ( pciDevIsMsiCapable(aDev)
2017	&& (u32Address >= aDev->Int.s.u8MsiCapOffset)
2018	&& (u32Address < (unsigned)(aDev->Int.s.u8MsiCapOffset + aDev->Int.s.u8MsiCapSize))
2019	)
2020	{
2021	return MsiPciConfigRead(aDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pDevIns), aDev, u32Address, len);
2022	}
2023
2024	if ( pciDevIsMsixCapable(aDev)
2025	&& (u32Address >= aDev->Int.s.u8MsixCapOffset)
2026	&& (u32Address < (unsigned)(aDev->Int.s.u8MsixCapOffset + aDev->Int.s.u8MsixCapSize))
2027	)
2028	{
2029	return MsixPciConfigRead(aDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pDevIns), aDev, u32Address, len);
2030	}
2031
2032	AssertMsgReturn(u32Address + len <= 256, ("Read after end of PCI config space\n"),
2033	0);
2034	switch (len)
2035	{
2036	case 1:
2037	return PCIDevGetByte(aDev, u32Address);
2038	case 2:
2039	return PCIDevGetWord(aDev, u32Address);
2040	case 4:
2041	return PCIDevGetDWord(aDev, u32Address);
2042	default:
2043	Assert(false);
2044	return 0;
2045	}
2046	}
2047
2048
2049	DECLINLINE(void) ich9pciWriteBarByte(PCIDevice *aDev, int iRegion, int iOffset, uint8_t u8Val)
2050	{
2051	PCIIORegion * pRegion = &aDev->Int.s.aIORegions[iRegion];
2052	int64_t iRegionSize = pRegion->size;
2053
2054	Log3(("ich9pciWriteBarByte: region=%d off=%d val=%x size=%d\n",
2055	iRegion, iOffset, u8Val, iRegionSize));
2056
2057	if (iOffset > 3)
2058	Assert((pRegion->type & PCI_ADDRESS_SPACE_BAR64) != 0);
2059
2060	/* Check if we're writing to upper part of 64-bit BAR. */
2061	if (pRegion->type == 0xff)
2062	{
2063	ich9pciWriteBarByte(aDev, iRegion-1, iOffset+4, u8Val);
2064	return;
2065	}
2066
2067	/* Region doesn't exist */
2068	if (iRegionSize == 0)
2069	return;
2070
2071	uint32_t uAddr = ich9pciGetRegionReg(iRegion) + iOffset;
2072	/* Region size must be power of two */
2073	Assert((iRegionSize & (iRegionSize - 1)) == 0);
2074	uint8_t uMask = ((iRegionSize - 1) >> (iOffset*8) ) & 0xff;
2075
2076	if (iOffset == 0)
2077	{
2078	uMask \|= (pRegion->type & PCI_ADDRESS_SPACE_IO) ?
2079	(1 << 2) - 1 /* 2 lowest bits for IO region */ :
2080	(1 << 4) - 1 /* 4 lowest bits for memory region, also ROM enable bit for ROM region */;
2081
2082	}
2083
2084	uint8_t u8Old = PCIDevGetByte(aDev, uAddr) & uMask;
2085	u8Val = (u8Old & uMask) \| (u8Val & ~uMask);
2086
2087	Log3(("ich9pciWriteBarByte: was %x writing %x\n", u8Old, u8Val));
2088
2089	PCIDevSetByte(aDev, uAddr, u8Val);
2090	}
2091
2092
2093	/**
2094	* Configuration space write callback (PCIDEVICEINT::pfnConfigWrite)
2095	* for connected devices.
2096	*
2097	* See paragraph 7.5 of PCI Express specification (p. 349) for
2098	* definition of registers and their writability policy.
2099	*/
2100	static DECLCALLBACK(void) ich9pciConfigWriteDev(PCIDevice *aDev, uint32_t u32Address,
2101	uint32_t val, unsigned len)
2102	{
2103	Assert(len <= 4);
2104
2105	if ((u32Address + len) > 256 && (u32Address + len) < 4096)
2106	{
2107	LogRel(("PCI: %8s/%u: Write to extended register %d fallen back to generic code\n",
2108	aDev->name, aDev->pDevIns->iInstance, u32Address));
2109	return;
2110	}
2111
2112	AssertMsgReturnVoid(u32Address + len <= 256, ("Write after end of PCI config space\n"));
2113
2114	if ( pciDevIsMsiCapable(aDev)
2115	&& (u32Address >= aDev->Int.s.u8MsiCapOffset)
2116	&& (u32Address < (unsigned)(aDev->Int.s.u8MsiCapOffset + aDev->Int.s.u8MsiCapSize))
2117	)
2118	{
2119	MsiPciConfigWrite(aDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pDevIns),
2120	aDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pPciHlp),
2121	aDev, u32Address, val, len);
2122	return;
2123	}
2124
2125	if ( pciDevIsMsixCapable(aDev)
2126	&& (u32Address >= aDev->Int.s.u8MsixCapOffset)
2127	&& (u32Address < (unsigned)(aDev->Int.s.u8MsixCapOffset + aDev->Int.s.u8MsixCapSize))
2128	)
2129	{
2130	MsixPciConfigWrite(aDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pDevIns),
2131	aDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pPciHlp),
2132	aDev, u32Address, val, len);
2133	return;
2134	}
2135
2136	uint32_t addr = u32Address;
2137	bool fUpdateMappings = false;
2138	bool fP2PBridge = false;
2139	/bool fPassthrough = pciDevIsPassthrough(aDev);/
2140	uint8_t u8HeaderType = ich9pciGetByte(aDev, VBOX_PCI_HEADER_TYPE);
2141
2142	for (uint32_t i = 0; i < len; i++)
2143	{
2144	bool fWritable = false;
2145	bool fRom = false;
2146	switch (u8HeaderType)
2147	{
2148	case 0x00: /* normal device */
2149	case 0x80: /* multi-function device */
2150	switch (addr)
2151	{
2152	/* Read-only registers */
2153	case VBOX_PCI_VENDOR_ID: case VBOX_PCI_VENDOR_ID+1:
2154	case VBOX_PCI_DEVICE_ID: case VBOX_PCI_DEVICE_ID+1:
2155	case VBOX_PCI_REVISION_ID:
2156	case VBOX_PCI_CLASS_PROG:
2157	case VBOX_PCI_CLASS_SUB:
2158	case VBOX_PCI_CLASS_BASE:
2159	case VBOX_PCI_HEADER_TYPE:
2160	case VBOX_PCI_SUBSYSTEM_VENDOR_ID: case VBOX_PCI_SUBSYSTEM_VENDOR_ID+1:
2161	case VBOX_PCI_SUBSYSTEM_ID: case VBOX_PCI_SUBSYSTEM_ID+1:
2162	case VBOX_PCI_ROM_ADDRESS: case VBOX_PCI_ROM_ADDRESS+1: case VBOX_PCI_ROM_ADDRESS+2: case VBOX_PCI_ROM_ADDRESS+3:
2163	case VBOX_PCI_CAPABILITY_LIST:
2164	case VBOX_PCI_INTERRUPT_PIN:
2165	fWritable = false;
2166	break;
2167	/* Others can be written */
2168	default:
2169	fWritable = true;
2170	break;
2171	}
2172	break;
2173	case 0x01: /* PCI-PCI bridge */
2174	fP2PBridge = true;
2175	switch (addr)
2176	{
2177	/* Read-only registers */
2178	case VBOX_PCI_VENDOR_ID: case VBOX_PCI_VENDOR_ID+1:
2179	case VBOX_PCI_DEVICE_ID: case VBOX_PCI_DEVICE_ID+1:
2180	case VBOX_PCI_REVISION_ID:
2181	case VBOX_PCI_CLASS_PROG:
2182	case VBOX_PCI_CLASS_SUB:
2183	case VBOX_PCI_CLASS_BASE:
2184	case VBOX_PCI_HEADER_TYPE:
2185	case VBOX_PCI_ROM_ADDRESS_BR: case VBOX_PCI_ROM_ADDRESS_BR+1: case VBOX_PCI_ROM_ADDRESS_BR+2: case VBOX_PCI_ROM_ADDRESS_BR+3:
2186	case VBOX_PCI_INTERRUPT_PIN:
2187	fWritable = false;
2188	break;
2189	default:
2190	fWritable = true;
2191	break;
2192	}
2193	break;
2194	default:
2195	AssertMsgFailed(("Unknown header type %x\n", PCIDevGetHeaderType(aDev)));
2196	fWritable = false;
2197	break;
2198	}
2199
2200	uint8_t u8Val = (uint8_t)val;
2201	switch (addr)
2202	{
2203	case VBOX_PCI_COMMAND: /* Command register, bits 0-7. */
2204	fUpdateMappings = true;
2205	goto default_case;
2206	case VBOX_PCI_COMMAND+1: /* Command register, bits 8-15. */
2207	/* don't change reserved bits (11-15) */
2208	u8Val &= ~UINT32_C(0xf8);
2209	fUpdateMappings = true;
2210	goto default_case;
2211	case VBOX_PCI_STATUS: /* Status register, bits 0-7. */
2212	/* don't change read-only bits => actually all lower bits are read-only */
2213	u8Val &= ~UINT32_C(0xff);
2214	/* status register, low part: clear bits by writing a '1' to the corresponding bit */
2215	aDev->config[addr] &= ~u8Val;
2216	break;
2217	case VBOX_PCI_STATUS+1: /* Status register, bits 8-15. */
2218	/* don't change read-only bits */
2219	u8Val &= ~UINT32_C(0x06);
2220	/* status register, high part: clear bits by writing a '1' to the corresponding bit */
2221	aDev->config[addr] &= ~u8Val;
2222	break;
2223	case VBOX_PCI_ROM_ADDRESS: case VBOX_PCI_ROM_ADDRESS +1: case VBOX_PCI_ROM_ADDRESS +2: case VBOX_PCI_ROM_ADDRESS +3:
2224	fRom = true;
2225	case VBOX_PCI_BASE_ADDRESS_0: case VBOX_PCI_BASE_ADDRESS_0+1: case VBOX_PCI_BASE_ADDRESS_0+2: case VBOX_PCI_BASE_ADDRESS_0+3:
2226	case VBOX_PCI_BASE_ADDRESS_1: case VBOX_PCI_BASE_ADDRESS_1+1: case VBOX_PCI_BASE_ADDRESS_1+2: case VBOX_PCI_BASE_ADDRESS_1+3:
2227	case VBOX_PCI_BASE_ADDRESS_2: case VBOX_PCI_BASE_ADDRESS_2+1: case VBOX_PCI_BASE_ADDRESS_2+2: case VBOX_PCI_BASE_ADDRESS_2+3:
2228	case VBOX_PCI_BASE_ADDRESS_3: case VBOX_PCI_BASE_ADDRESS_3+1: case VBOX_PCI_BASE_ADDRESS_3+2: case VBOX_PCI_BASE_ADDRESS_3+3:
2229	case VBOX_PCI_BASE_ADDRESS_4: case VBOX_PCI_BASE_ADDRESS_4+1: case VBOX_PCI_BASE_ADDRESS_4+2: case VBOX_PCI_BASE_ADDRESS_4+3:
2230	case VBOX_PCI_BASE_ADDRESS_5: case VBOX_PCI_BASE_ADDRESS_5+1: case VBOX_PCI_BASE_ADDRESS_5+2: case VBOX_PCI_BASE_ADDRESS_5+3:
2231	{
2232	/* We check that, as same PCI register numbers as BARs may mean different registers for bridges */
2233	if (fP2PBridge)
2234	goto default_case;
2235	else
2236	{
2237	int iRegion = fRom ? VBOX_PCI_ROM_SLOT : (addr - VBOX_PCI_BASE_ADDRESS_0) >> 2;
2238	int iOffset = addr & 0x3;
2239	ich9pciWriteBarByte(aDev, iRegion, iOffset, u8Val);
2240	fUpdateMappings = true;
2241	}
2242	break;
2243	}
2244	default:
2245	default_case:
2246	if (fWritable)
2247	PCIDevSetByte(aDev, addr, u8Val);
2248	}
2249	addr++;
2250	val >>= 8;
2251	}
2252
2253	if (fUpdateMappings)
2254	/* if the command/base address register is modified, we must modify the mappings */
2255	ich9pciUpdateMappings(aDev);
2256	}
2257
2258	static bool assignPosition(PICH9PCIBUS pBus, PPCIDEVICE pPciDev, const char pszName, int iDevFn, PciAddress aPosition)
2259	{
2260	NOREF(pszName);
2261	aPosition->iBus = 0;
2262	aPosition->iDeviceFunc = iDevFn;
2263	aPosition->iRegister = 0; /* N/A */
2264
2265	/* Explicit slot request */
2266	if (iDevFn >= 0 && iDevFn < (int)RT_ELEMENTS(pBus->apDevices))
2267	return true;
2268
2269	int iStartPos = 0;
2270
2271	/* Otherwise when assigning a slot, we need to make sure all its functions are available */
2272	for (int iPos = iStartPos; iPos < (int)RT_ELEMENTS(pBus->apDevices); iPos += 8)
2273	{
2274	if ( !pBus->apDevices[iPos]
2275	&& !pBus->apDevices[iPos + 1]
2276	&& !pBus->apDevices[iPos + 2]
2277	&& !pBus->apDevices[iPos + 3]
2278	&& !pBus->apDevices[iPos + 4]
2279	&& !pBus->apDevices[iPos + 5]
2280	&& !pBus->apDevices[iPos + 6]
2281	&& !pBus->apDevices[iPos + 7])
2282	{
2283	pciDevClearRequestedDevfunc(pPciDev);
2284	aPosition->iDeviceFunc = iPos;
2285	return true;
2286	}
2287	}
2288
2289	return false;
2290	}
2291
2292	#ifdef SOME_UNUSED_FUNCTION
2293	static bool hasHardAssignedDevsInSlot(PICH9PCIBUS pBus, int iSlot)
2294	{
2295	PCIDevice** aSlot = &pBus->apDevices[iSlot << 3];
2296
2297	return (aSlot[0] && pciDevIsRequestedDevfunc(aSlot[0]))
2298	\|\| (aSlot[1] && pciDevIsRequestedDevfunc(aSlot[1]))
2299	\|\| (aSlot[2] && pciDevIsRequestedDevfunc(aSlot[2]))
2300	\|\| (aSlot[3] && pciDevIsRequestedDevfunc(aSlot[3]))
2301	\|\| (aSlot[4] && pciDevIsRequestedDevfunc(aSlot[4]))
2302	\|\| (aSlot[5] && pciDevIsRequestedDevfunc(aSlot[5]))
2303	\|\| (aSlot[6] && pciDevIsRequestedDevfunc(aSlot[6]))
2304	\|\| (aSlot[7] && pciDevIsRequestedDevfunc(aSlot[7]))
2305	;
2306	}
2307	#endif
2308
2309	static int ich9pciRegisterInternal(PICH9PCIBUS pBus, int iDev, PPCIDEVICE pPciDev, const char *pszName)
2310	{
2311	PciAddress aPosition;
2312	aPosition.iBus = 0;
2313	aPosition.iDeviceFunc = 0;
2314	aPosition.iRegister = 0;
2315
2316	/*
2317	* Find device position
2318	*/
2319	if (!assignPosition(pBus, pPciDev, pszName, iDev, &aPosition))
2320	{
2321	AssertMsgFailed(("Couldn't asssign position!\n"));
2322	return VERR_PDM_TOO_PCI_MANY_DEVICES;
2323	}
2324
2325	AssertMsgReturn(aPosition.iBus == 0,
2326	("Assigning behind the bridge not implemented yet\n"),
2327	VERR_PDM_TOO_PCI_MANY_DEVICES);
2328
2329
2330	iDev = aPosition.iDeviceFunc;
2331	/*
2332	* Check if we can really take this slot, possibly by relocating
2333	* its current habitant, if it wasn't hard assigned too.
2334	*/
2335	if (pciDevIsRequestedDevfunc(pPciDev) &&
2336	pBus->apDevices[iDev] &&
2337	pciDevIsRequestedDevfunc(pBus->apDevices[iDev]))
2338	{
2339	AssertReleaseMsgFailed(("Configuration error:'%s' and '%s' are both configured as device %d\n",
2340	pszName, pBus->apDevices[iDev]->name, iDev));
2341	return VERR_INTERNAL_ERROR;
2342	}
2343
2344	if (pBus->apDevices[iDev])
2345	{
2346	/* if we got here, we shall (and usually can) relocate the device */
2347	bool assigned = assignPosition(pBus, pBus->apDevices[iDev], pBus->apDevices[iDev]->name, -1, &aPosition);
2348	AssertMsgReturn(aPosition.iBus == 0,
2349	("Assigning behind the bridge not implemented yet\n"),
2350	VERR_PDM_TOO_PCI_MANY_DEVICES);
2351	int iRelDev = aPosition.iDeviceFunc;
2352	if (!assigned \|\| iRelDev == iDev)
2353	{
2354	AssertMsgFailed(("Couldn't find free spot!\n"));
2355	return VERR_PDM_TOO_PCI_MANY_DEVICES;
2356	}
2357	/* Copy device function by function to its new position */
2358	for (int i = 0; i < 8; i++)
2359	{
2360	if (!pBus->apDevices[iDev + i])
2361	continue;
2362	Log(("PCI: relocating '%s' from slot %#x to %#x\n", pBus->apDevices[iDev + i]->name, iDev + i, iRelDev + i));
2363	pBus->apDevices[iRelDev + i] = pBus->apDevices[iDev + i];
2364	pBus->apDevices[iRelDev + i]->devfn = iRelDev + i;
2365	pBus->apDevices[iDev + i] = NULL;
2366	}
2367	}
2368
2369	/*
2370	* Fill in device information.
2371	*/
2372	pPciDev->devfn = iDev;
2373	pPciDev->name = pszName;
2374	pPciDev->Int.s.pBusR3 = pBus;
2375	pPciDev->Int.s.pBusR0 = MMHyperR3ToR0(PDMDevHlpGetVM(pBus->CTX_SUFF(pDevIns)), pBus);
2376	pPciDev->Int.s.pBusRC = MMHyperR3ToRC(PDMDevHlpGetVM(pBus->CTX_SUFF(pDevIns)), pBus);
2377	pPciDev->Int.s.pfnConfigRead = ich9pciConfigReadDev;
2378	pPciDev->Int.s.pfnConfigWrite = ich9pciConfigWriteDev;
2379	pBus->apDevices[iDev] = pPciDev;
2380	if (pciDevIsPci2PciBridge(pPciDev))
2381	{
2382	AssertMsg(pBus->cBridges < RT_ELEMENTS(pBus->apDevices), ("Number of bridges exceeds the number of possible devices on the bus\n"));
2383	AssertMsg(pPciDev->Int.s.pfnBridgeConfigRead && pPciDev->Int.s.pfnBridgeConfigWrite,
2384	("device is a bridge but does not implement read/write functions\n"));
2385	Log2(("Setting bridge %d on bus %p\n", pBus->cBridges, pBus));
2386	pBus->papBridgesR3[pBus->cBridges] = pPciDev;
2387	pBus->cBridges++;
2388	}
2389
2390	Log(("PCI: Registered device %d function %d on bus %d (%#x) '%s'.\n",
2391	iDev >> 3, iDev & 7, pBus->iBus, 0x80000000 \| (iDev << 8), pszName));
2392
2393	return VINF_SUCCESS;
2394	}
2395
2396	static void printIndent(PCDBGFINFOHLP pHlp, int iIndent)
2397	{
2398	for (int i = 0; i < iIndent; i++)
2399	{
2400	pHlp->pfnPrintf(pHlp, " ");
2401	}
2402	}
2403
2404	static void ich9pciBusInfo(PICH9PCIBUS pBus, PCDBGFINFOHLP pHlp, int iIndent, bool fRegisters)
2405	{
2406	for (uint32_t iDev = 0; iDev < RT_ELEMENTS(pBus->apDevices); iDev++)
2407	{
2408	PPCIDEVICE pPciDev = pBus->apDevices[iDev];
2409	if (pPciDev != NULL)
2410	{
2411	printIndent(pHlp, iIndent);
2412
2413	/*
2414	* For passthrough devices MSI/MSI-X mostly reflects the way interrupts delivered to the guest,
2415	* as host driver handles real devices interrupts.
2416	*/
2417	pHlp->pfnPrintf(pHlp, "%02x:%02x:%02x %s%s: %04x-%04x",
2418	pBus->iBus, (iDev >> 3) & 0xff, iDev & 0x7,
2419	pPciDev->name,
2420	pciDevIsPassthrough(pPciDev) ? " (PASSTHROUGH)" : "",
2421	ich9pciGetWord(pPciDev, VBOX_PCI_VENDOR_ID), ich9pciGetWord(pPciDev, VBOX_PCI_DEVICE_ID)
2422	);
2423	if (ich9pciGetByte(pPciDev, VBOX_PCI_INTERRUPT_PIN) != 0)
2424	{
2425	pHlp->pfnPrintf(pHlp, " IRQ%d", ich9pciGetByte(pPciDev, VBOX_PCI_INTERRUPT_LINE));
2426	pHlp->pfnPrintf(pHlp, " (INTA#->IRQ%d)", 0x10 + ich9pciSlot2ApicIrq(iDev >> 3, 0));
2427	}
2428	pHlp->pfnPrintf(pHlp, "\n");
2429
2430	if (pciDevIsMsiCapable(pPciDev) \|\| pciDevIsMsixCapable(pPciDev))
2431	{
2432	printIndent(pHlp, iIndent + 2);
2433
2434	if (pciDevIsMsiCapable(pPciDev))
2435	pHlp->pfnPrintf(pHlp, "MSI:%s ", MsiIsEnabled(pPciDev) ? "on" : "off");
2436
2437	if (pciDevIsMsixCapable(pPciDev))
2438	pHlp->pfnPrintf(pHlp, "MSI-X:%s ", MsixIsEnabled(pPciDev) ? "on" : "off");
2439
2440	pHlp->pfnPrintf(pHlp, "\n");
2441	}
2442
2443	uint16_t iCmd = ich9pciGetWord(pPciDev, VBOX_PCI_COMMAND);
2444	if ((iCmd & (VBOX_PCI_COMMAND_IO \| VBOX_PCI_COMMAND_MEMORY)) != 0)
2445	{
2446	for (int iRegion = 0; iRegion < PCI_NUM_REGIONS; iRegion++)
2447	{
2448	PCIIORegion* pRegion = &pPciDev->Int.s.aIORegions[iRegion];
2449	uint64_t iRegionSize = pRegion->size;
2450
2451	if (iRegionSize == 0)
2452	continue;
2453
2454	uint32_t u32Addr = ich9pciGetDWord(pPciDev, ich9pciGetRegionReg(iRegion));
2455	const char * pszDesc;
2456	char szDescBuf[128];
2457
2458	bool f64Bit = !!(pRegion->type & PCI_ADDRESS_SPACE_BAR64);
2459	if (pRegion->type & PCI_ADDRESS_SPACE_IO)
2460	{
2461	pszDesc = "IO";
2462	u32Addr &= ~0x3;
2463	}
2464	else
2465	{
2466	RTStrPrintf(szDescBuf, sizeof(szDescBuf), "MMIO%s%s",
2467	f64Bit ? "64" : "32",
2468	(pRegion->type & PCI_ADDRESS_SPACE_MEM_PREFETCH) ? " PREFETCH" : "");
2469	pszDesc = szDescBuf;
2470	u32Addr &= ~0xf;
2471	}
2472
2473	printIndent(pHlp, iIndent + 2);
2474	pHlp->pfnPrintf(pHlp, "%s region #%d: ",pszDesc, iRegion);
2475	if (f64Bit)
2476	{
2477	uint32_t u32High = ich9pciGetDWord(pPciDev, ich9pciGetRegionReg(iRegion+1));
2478	uint64_t u64Addr = RT_MAKE_U64(u32Addr, u32High);
2479	pHlp->pfnPrintf(pHlp, "%RX64..%RX64\n", u64Addr, u64Addr+iRegionSize);
2480	iRegion++;
2481	}
2482	else
2483	pHlp->pfnPrintf(pHlp, "%x..%x\n", u32Addr, u32Addr+iRegionSize);
2484	}
2485	}
2486
2487	printIndent(pHlp, iIndent + 2);
2488	uint16_t iStatus = ich9pciGetWord(pPciDev, VBOX_PCI_STATUS);
2489	pHlp->pfnPrintf(pHlp, "Command: %04X, Status: %04X\n",
2490	iCmd, iStatus);
2491	printIndent(pHlp, iIndent + 2);
2492	pHlp->pfnPrintf(pHlp, "Bus master: %s\n",
2493	iCmd & VBOX_PCI_COMMAND_MASTER ? "Yes" : "No");
2494
2495	if (fRegisters)
2496	{
2497	printIndent(pHlp, iIndent + 2);
2498	pHlp->pfnPrintf(pHlp, "PCI registers:\n");
2499	for (int iReg = 0; iReg < 0x100; )
2500	{
2501	int iPerLine = 0x10;
2502	Assert (0x100 % iPerLine == 0);
2503	printIndent(pHlp, iIndent + 3);
2504
2505	while (iPerLine-- > 0)
2506	{
2507	pHlp->pfnPrintf(pHlp, "%02x ", ich9pciGetByte(pPciDev, iReg++));
2508	}
2509	pHlp->pfnPrintf(pHlp, "\n");
2510	}
2511	}
2512	}
2513	}
2514
2515	if (pBus->cBridges > 0)
2516	{
2517	printIndent(pHlp, iIndent);
2518	pHlp->pfnPrintf(pHlp, "Registered %d bridges, subordinate buses info follows\n", pBus->cBridges);
2519	for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
2520	{
2521	PICH9PCIBUS pBusSub = PDMINS_2_DATA(pBus->papBridgesR3[iBridge]->pDevIns, PICH9PCIBUS);
2522	ich9pciBusInfo(pBusSub, pHlp, iIndent + 1, fRegisters);
2523	}
2524	}
2525	}
2526
2527	/**
2528	* Info handler, device version.
2529	*
2530	* @param pDevIns Device instance which registered the info.
2531	* @param pHlp Callback functions for doing output.
2532	* @param pszArgs Argument string. Optional and specific to the handler.
2533	*/
2534	static DECLCALLBACK(void) ich9pciInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
2535	{
2536	PICH9PCIBUS pBus = DEVINS_2_PCIBUS(pDevIns);
2537
2538	if (pszArgs == NULL \|\| !strcmp(pszArgs, "basic"))
2539	{
2540	ich9pciBusInfo(pBus, pHlp, 0, false);
2541	}
2542	else if (!strcmp(pszArgs, "verbose"))
2543	{
2544	ich9pciBusInfo(pBus, pHlp, 0, true);
2545	}
2546	else
2547	{
2548	pHlp->pfnPrintf(pHlp, "Invalid argument. Recognized arguments are 'basic', 'verbose'.\n");
2549	}
2550	}
2551
2552
2553	static DECLCALLBACK(int) ich9pciConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
2554	{
2555	RT_NOREF1(iInstance);
2556	Assert(iInstance == 0);
2557	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
2558
2559	/*
2560	* Validate and read configuration.
2561	*/
2562	if (!CFGMR3AreValuesValid(pCfg,
2563	"IOAPIC\0"
2564	"GCEnabled\0"
2565	"R0Enabled\0"
2566	"McfgBase\0"
2567	"McfgLength\0"
2568	))
2569	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
2570
2571	/* query whether we got an IOAPIC */
2572	bool fUseIoApic;
2573	int rc = CFGMR3QueryBoolDef(pCfg, "IOAPIC", &fUseIoApic, false);
2574	if (RT_FAILURE(rc))
2575	return PDMDEV_SET_ERROR(pDevIns, rc,
2576	N_("Configuration error: Failed to query boolean value \"IOAPIC\""));
2577
2578	/* check if RC code is enabled. */
2579	bool fGCEnabled;
2580	rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
2581	if (RT_FAILURE(rc))
2582	return PDMDEV_SET_ERROR(pDevIns, rc,
2583	N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
2584	/* check if R0 code is enabled. */
2585	bool fR0Enabled;
2586	rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
2587	if (RT_FAILURE(rc))
2588	return PDMDEV_SET_ERROR(pDevIns, rc,
2589	N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
2590
2591	Log(("PCI: fUseIoApic=%RTbool fGCEnabled=%RTbool fR0Enabled=%RTbool\n", fUseIoApic, fGCEnabled, fR0Enabled));
2592
2593	/*
2594	* Init data.
2595	*/
2596	PICH9PCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
2597	PICH9PCIBUS pBus = &pGlobals->aPciBus;
2598	/* Zero out everything */
2599	memset(pGlobals, 0, sizeof(*pGlobals));
2600	/* And fill values */
2601	if (!fUseIoApic)
2602	return PDMDEV_SET_ERROR(pDevIns, rc,
2603	N_("Must use IO-APIC with ICH9 chipset"));
2604	rc = CFGMR3QueryU64Def(pCfg, "McfgBase", &pGlobals->u64PciConfigMMioAddress, 0);
2605	if (RT_FAILURE(rc))
2606	return PDMDEV_SET_ERROR(pDevIns, rc,
2607	N_("Configuration error: Failed to read \"McfgBase\""));
2608	rc = CFGMR3QueryU64Def(pCfg, "McfgLength", &pGlobals->u64PciConfigMMioLength, 0);
2609	if (RT_FAILURE(rc))
2610	return PDMDEV_SET_ERROR(pDevIns, rc,
2611	N_("Configuration error: Failed to read \"McfgLength\""));
2612
2613	pGlobals->pDevInsR3 = pDevIns;
2614	pGlobals->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2615	pGlobals->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2616
2617	pGlobals->aPciBus.pDevInsR3 = pDevIns;
2618	pGlobals->aPciBus.pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2619	pGlobals->aPciBus.pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2620	pGlobals->aPciBus.papBridgesR3 = (PPCIDEVICE )PDMDevHlpMMHeapAllocZ(pDevIns, sizeof(PPCIDEVICE) RT_ELEMENTS(pGlobals->aPciBus.apDevices));
2621
2622	/*
2623	* Register bus
2624	*/
2625	PDMPCIBUSREG PciBusReg;
2626	PciBusReg.u32Version = PDM_PCIBUSREG_VERSION;
2627	PciBusReg.pfnRegisterR3 = ich9pciRegister;
2628	PciBusReg.pfnRegisterMsiR3 = ich9pciRegisterMsi;
2629	PciBusReg.pfnIORegionRegisterR3 = ich9pciIORegionRegister;
2630	PciBusReg.pfnSetConfigCallbacksR3 = ich9pciSetConfigCallbacks;
2631	PciBusReg.pfnSetIrqR3 = ich9pciSetIrq;
2632	PciBusReg.pfnFakePCIBIOSR3 = ich9pciFakePCIBIOS;
2633	PciBusReg.pszSetIrqRC = fGCEnabled ? "ich9pciSetIrq" : NULL;
2634	PciBusReg.pszSetIrqR0 = fR0Enabled ? "ich9pciSetIrq" : NULL;
2635	rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBus->pPciHlpR3);
2636	if (RT_FAILURE(rc))
2637	return PDMDEV_SET_ERROR(pDevIns, rc,
2638	N_("Failed to register ourselves as a PCI Bus"));
2639	if (pBus->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
2640	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
2641	N_("PCI helper version mismatch; got %#x expected %#x"),
2642	pBus->pPciHlpR3->u32Version, PDM_PCIHLPR3_VERSION);
2643
2644	pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
2645	pBus->pPciHlpR0 = pBus->pPciHlpR3->pfnGetR0Helpers(pDevIns);
2646
2647	/*
2648	* Fill in PCI configs and add them to the bus.
2649	*/
2650	/** @todo Disabled for now because this causes error messages with Linux guests.
2651	* The guest loads the x38_edac device which tries to map a memory region
2652	* using an address given at place 0x48 - 0x4f in the PCi config space.
2653	* This fails. because we don't register such a region.
2654	*/
2655	#if 0
2656	/* Host bridge device */
2657	PCIDevSetVendorId( &pBus->aPciDev, 0x8086); /* Intel */
2658	PCIDevSetDeviceId( &pBus->aPciDev, 0x29e0); /* Desktop */
2659	PCIDevSetRevisionId(&pBus->aPciDev, 0x01); /* rev. 01 */
2660	PCIDevSetClassBase( &pBus->aPciDev, 0x06); /* bridge */
2661	PCIDevSetClassSub( &pBus->aPciDev, 0x00); /* Host/PCI bridge */
2662	PCIDevSetClassProg( &pBus->aPciDev, 0x00); /* Host/PCI bridge */
2663	PCIDevSetHeaderType(&pBus->aPciDev, 0x00); /* bridge */
2664	PCIDevSetWord(&pBus->aPciDev, VBOX_PCI_SEC_STATUS, 0x0280); /* secondary status */
2665
2666	pBus->aPciDev.pDevIns = pDevIns;
2667	/* We register Host<->PCI controller on the bus */
2668	ich9pciRegisterInternal(pBus, 0, &pBus->aPciDev, "dram");
2669	#endif
2670
2671	/*
2672	* Register I/O ports and save state.
2673	*/
2674	rc = PDMDevHlpIOPortRegister(pDevIns, 0x0cf8, 1, NULL, ich9pciIOPortAddressWrite, ich9pciIOPortAddressRead, NULL, NULL, "ICH9 (PCI)");
2675	if (RT_FAILURE(rc))
2676	return rc;
2677	rc = PDMDevHlpIOPortRegister(pDevIns, 0x0cfc, 4, NULL, ich9pciIOPortDataWrite, ich9pciIOPortDataRead, NULL, NULL, "ICH9 (PCI)");
2678	if (RT_FAILURE(rc))
2679	return rc;
2680	if (fGCEnabled)
2681	{
2682	rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x0cf8, 1, NIL_RTGCPTR, "ich9pciIOPortAddressWrite", "ich9pciIOPortAddressRead", NULL, NULL, "ICH9 (PCI)");
2683	if (RT_FAILURE(rc))
2684	return rc;
2685	rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x0cfc, 4, NIL_RTGCPTR, "ich9pciIOPortDataWrite", "ich9pciIOPortDataRead", NULL, NULL, "ICH9 (PCI)");
2686	if (RT_FAILURE(rc))
2687	return rc;
2688	}
2689	if (fR0Enabled)
2690	{
2691	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x0cf8, 1, NIL_RTR0PTR, "ich9pciIOPortAddressWrite", "ich9pciIOPortAddressRead", NULL, NULL, "ICH9 (PCI)");
2692	if (RT_FAILURE(rc))
2693	return rc;
2694	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x0cfc, 4, NIL_RTR0PTR, "ich9pciIOPortDataWrite", "ich9pciIOPortDataRead", NULL, NULL, "ICH9 (PCI)");
2695	if (RT_FAILURE(rc))
2696	return rc;
2697	}
2698
2699	if (pGlobals->u64PciConfigMMioAddress != 0)
2700	{
2701	rc = PDMDevHlpMMIORegister(pDevIns, pGlobals->u64PciConfigMMioAddress, pGlobals->u64PciConfigMMioLength, NULL /pvUser/,
2702	IOMMMIO_FLAGS_READ_PASSTHRU \| IOMMMIO_FLAGS_WRITE_PASSTHRU,
2703	ich9pciMcfgMMIOWrite, ich9pciMcfgMMIORead, "MCFG ranges");
2704	AssertMsgRCReturn(rc, ("rc=%Rrc %#llx/%#llx\n", rc, pGlobals->u64PciConfigMMioAddress, pGlobals->u64PciConfigMMioLength), rc);
2705
2706	if (fGCEnabled)
2707	{
2708	rc = PDMDevHlpMMIORegisterRC(pDevIns, pGlobals->u64PciConfigMMioAddress, pGlobals->u64PciConfigMMioLength,
2709	NIL_RTRCPTR /pvUser/, "ich9pciMcfgMMIOWrite", "ich9pciMcfgMMIORead");
2710	AssertRCReturn(rc, rc);
2711	}
2712
2713
2714	if (fR0Enabled)
2715	{
2716	rc = PDMDevHlpMMIORegisterR0(pDevIns, pGlobals->u64PciConfigMMioAddress, pGlobals->u64PciConfigMMioLength,
2717	NIL_RTR0PTR /pvUser/, "ich9pciMcfgMMIOWrite", "ich9pciMcfgMMIORead");
2718	AssertRCReturn(rc, rc);
2719	}
2720	}
2721
2722	rc = PDMDevHlpSSMRegisterEx(pDevIns, VBOX_ICH9PCI_SAVED_STATE_VERSION_CURRENT,
2723	sizeof(pBus) + 16128, "pgm",
2724	NULL, NULL, NULL,
2725	NULL, ich9pciR3SaveExec, NULL,
2726	NULL, ich9pciR3LoadExec, NULL);
2727	if (RT_FAILURE(rc))
2728	return rc;
2729
2730
2731	/** @todo other chipset devices shall be registered too */
2732
2733	PDMDevHlpDBGFInfoRegister(pDevIns, "pci", "Display PCI bus status. Recognizes 'basic' or 'verbose' "
2734	"as arguments, defaults to 'basic'.", ich9pciInfo);
2735
2736	return VINF_SUCCESS;
2737	}
2738
2739	static void ich9pciResetDevice(PPCIDEVICE pDev)
2740	{
2741	/* Clear regions */
2742	for (int iRegion = 0; iRegion < PCI_NUM_REGIONS; iRegion++)
2743	{
2744	PCIIORegion* pRegion = &pDev->Int.s.aIORegions[iRegion];
2745	if (pRegion->size == 0)
2746	continue;
2747
2748	ich9pciUnmapRegion(pDev, iRegion);
2749	}
2750
2751	if (pciDevIsPassthrough(pDev))
2752	{
2753	// no reset handler - we can do what we need in PDM reset handler
2754	/// @todo is it correct?
2755	}
2756	else
2757	{
2758	PCIDevSetCommand(pDev,
2759	PCIDevGetCommand(pDev)
2760	&
2761	~(VBOX_PCI_COMMAND_IO \| VBOX_PCI_COMMAND_MEMORY \|
2762	VBOX_PCI_COMMAND_MASTER \| VBOX_PCI_COMMAND_SPECIAL \|
2763	VBOX_PCI_COMMAND_PARITY \| VBOX_PCI_COMMAND_SERR \|
2764	VBOX_PCI_COMMAND_FAST_BACK \| VBOX_PCI_COMMAND_INTX_DISABLE));
2765
2766	/* Bridge device reset handlers processed later */
2767	if (!pciDevIsPci2PciBridge(pDev))
2768	{
2769	PCIDevSetByte(pDev, VBOX_PCI_CACHE_LINE_SIZE, 0x0);
2770	PCIDevSetInterruptLine(pDev, 0x0);
2771	}
2772
2773	/* Reset MSI message control. */
2774	if (pciDevIsMsiCapable(pDev))
2775	{
2776	/* Extracted from MsiPciConfigWrite(). */
2777	pDev->config[pDev->Int.s.u8MsiCapOffset + VBOX_MSI_CAP_MESSAGE_CONTROL] &= 0x8e;
2778	}
2779
2780	/* Reset MSI-X message control. */
2781	if (pciDevIsMsixCapable(pDev))
2782	{
2783	/* Extracted from MsixPciConfigWrite(); no side effects. */
2784	pDev->config[pDev->Int.s.u8MsixCapOffset + VBOX_MSIX_CAP_MESSAGE_CONTROL + 1] &= 0x3f;
2785	}
2786	}
2787	}
2788
2789
2790	/**
2791	* @copydoc FNPDMDEVRESET
2792	*/
2793	static DECLCALLBACK(void) ich9pciReset(PPDMDEVINS pDevIns)
2794	{
2795	PICH9PCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
2796	PICH9PCIBUS pBus = &pGlobals->aPciBus;
2797
2798	/* PCI-specific reset for each device. */
2799	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
2800	{
2801	if (pBus->apDevices[i])
2802	ich9pciResetDevice(pBus->apDevices[i]);
2803	}
2804
2805	for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
2806	{
2807	if (pBus->papBridgesR3[iBridge])
2808	ich9pcibridgeReset(pBus->papBridgesR3[iBridge]->pDevIns);
2809	}
2810
2811	ich9pciFakePCIBIOS(pDevIns);
2812	}
2813
2814	static void ich9pciRelocateDevice(PPCIDEVICE pDev, RTGCINTPTR offDelta)
2815	{
2816	if (pDev)
2817	{
2818	pDev->Int.s.pBusRC += offDelta;
2819	if (pDev->Int.s.pMsixPageRC)
2820	pDev->Int.s.pMsixPageRC += offDelta;
2821	}
2822	}
2823
2824	/**
2825	* @copydoc FNPDMDEVRELOCATE
2826	*/
2827	static DECLCALLBACK(void) ich9pciRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
2828	{
2829	PICH9PCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
2830	PICH9PCIBUS pBus = &pGlobals->aPciBus;
2831	pGlobals->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2832
2833	pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
2834	pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2835
2836	/* Relocate RC pointers for the attached pci devices. */
2837	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
2838	ich9pciRelocateDevice(pBus->apDevices[i], offDelta);
2839
2840	}
2841
2842	/**
2843	* @interface_method_impl{PDMDEVREG,pfnConstruct}
2844	*/
2845	static DECLCALLBACK(int) ich9pcibridgeConstruct(PPDMDEVINS pDevIns,
2846	int iInstance,
2847	PCFGMNODE pCfg)
2848	{
2849	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
2850
2851	/*
2852	* Validate and read configuration.
2853	*/
2854	if (!CFGMR3AreValuesValid(pCfg, "GCEnabled\0" "R0Enabled\0"))
2855	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
2856
2857	/* check if RC code is enabled. */
2858	bool fGCEnabled;
2859	int rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
2860	if (RT_FAILURE(rc))
2861	return PDMDEV_SET_ERROR(pDevIns, rc,
2862	N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
2863
2864	/* check if R0 code is enabled. */
2865	bool fR0Enabled;
2866	rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
2867	if (RT_FAILURE(rc))
2868	return PDMDEV_SET_ERROR(pDevIns, rc,
2869	N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
2870	Log(("PCI: fGCEnabled=%RTbool fR0Enabled=%RTbool\n", fGCEnabled, fR0Enabled));
2871
2872	/*
2873	* Init data and register the PCI bus.
2874	*/
2875	PICH9PCIBUS pBus = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
2876	pBus->pDevInsR3 = pDevIns;
2877	pBus->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2878	pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2879	pBus->papBridgesR3 = (PPCIDEVICE )PDMDevHlpMMHeapAllocZ(pDevIns, sizeof(PPCIDEVICE) RT_ELEMENTS(pBus->apDevices));
2880
2881	PDMPCIBUSREG PciBusReg;
2882	PciBusReg.u32Version = PDM_PCIBUSREG_VERSION;
2883	PciBusReg.pfnRegisterR3 = ich9pcibridgeRegister;
2884	PciBusReg.pfnRegisterMsiR3 = ich9pciRegisterMsi;
2885	PciBusReg.pfnIORegionRegisterR3 = ich9pciIORegionRegister;
2886	PciBusReg.pfnSetConfigCallbacksR3 = ich9pciSetConfigCallbacks;
2887	PciBusReg.pfnSetIrqR3 = ich9pcibridgeSetIrq;
2888	PciBusReg.pfnFakePCIBIOSR3 = NULL; /* Only needed for the first bus. */
2889	PciBusReg.pszSetIrqRC = fGCEnabled ? "ich9pcibridgeSetIrq" : NULL;
2890	PciBusReg.pszSetIrqR0 = fR0Enabled ? "ich9pcibridgeSetIrq" : NULL;
2891	rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBus->pPciHlpR3);
2892	if (RT_FAILURE(rc))
2893	return PDMDEV_SET_ERROR(pDevIns, rc,
2894	N_("Failed to register ourselves as a PCI Bus"));
2895	if (pBus->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
2896	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
2897	N_("PCI helper version mismatch; got %#x expected %#x"),
2898	pBus->pPciHlpR3->u32Version, PDM_PCIHLPR3_VERSION);
2899
2900	pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
2901	pBus->pPciHlpR0 = pBus->pPciHlpR3->pfnGetR0Helpers(pDevIns);
2902
2903	/* Disable default device locking. */
2904	rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
2905	AssertRCReturn(rc, rc);
2906
2907	/*
2908	* Fill in PCI configs and add them to the bus.
2909	*/
2910	PCIDevSetVendorId( &pBus->aPciDev, 0x8086); /* Intel */
2911	PCIDevSetDeviceId( &pBus->aPciDev, 0x2448); /* 82801 Mobile PCI bridge. */
2912	PCIDevSetRevisionId(&pBus->aPciDev, 0xf2);
2913	PCIDevSetClassSub( &pBus->aPciDev, 0x04); /* pci2pci */
2914	PCIDevSetClassBase( &pBus->aPciDev, 0x06); /* PCI_bridge */
2915	PCIDevSetClassProg( &pBus->aPciDev, 0x01); /* Supports subtractive decoding. */
2916	PCIDevSetHeaderType(&pBus->aPciDev, 0x01); /* Single function device which adheres to the PCI-to-PCI bridge spec. */
2917	PCIDevSetCommand( &pBus->aPciDev, 0x00);
2918	PCIDevSetStatus( &pBus->aPciDev, 0x20); /* 66MHz Capable. */
2919	PCIDevSetInterruptLine(&pBus->aPciDev, 0x00); /* This device does not assert interrupts. */
2920
2921	/*
2922	* This device does not generate interrupts. Interrupt delivery from
2923	* devices attached to the bus is unaffected.
2924	*/
2925	PCIDevSetInterruptPin (&pBus->aPciDev, 0x00);
2926
2927	pBus->aPciDev.pDevIns = pDevIns;
2928
2929	/* Bridge-specific data */
2930	pciDevSetPci2PciBridge(&pBus->aPciDev);
2931	pBus->aPciDev.Int.s.pfnBridgeConfigRead = ich9pcibridgeConfigRead;
2932	pBus->aPciDev.Int.s.pfnBridgeConfigWrite = ich9pcibridgeConfigWrite;
2933
2934	/*
2935	* Register this PCI bridge. The called function will take care on which bus we will get registered.
2936	*/
2937	rc = PDMDevHlpPCIRegister (pDevIns, &pBus->aPciDev);
2938	if (RT_FAILURE(rc))
2939	return rc;
2940
2941	/*
2942	* The iBus property doesn't really represent the bus number
2943	* because the guest and the BIOS can choose different bus numbers
2944	* for them.
2945	* The bus number is mainly for the setIrq function to indicate
2946	* when the host bus is reached which will have iBus = 0.
2947	* That's why the + 1.
2948	*/
2949	pBus->iBus = iInstance + 1;
2950
2951	/*
2952	* Register SSM handlers. We use the same saved state version as for the host bridge
2953	* to make changes easier.
2954	*/
2955	rc = PDMDevHlpSSMRegisterEx(pDevIns, VBOX_ICH9PCI_SAVED_STATE_VERSION_CURRENT,
2956	sizeof(pBus) + 16128,
2957	"pgm" /* before */,
2958	NULL, NULL, NULL,
2959	NULL, ich9pcibridgeR3SaveExec, NULL,
2960	NULL, ich9pcibridgeR3LoadExec, NULL);
2961	if (RT_FAILURE(rc))
2962	return rc;
2963
2964
2965	return VINF_SUCCESS;
2966	}
2967
2968	/**
2969	* @copydoc FNPDMDEVRESET
2970	*/
2971	static void ich9pcibridgeReset(PPDMDEVINS pDevIns)
2972	{
2973	PICH9PCIBUS pBus = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
2974
2975	/* Reset config space to default values. */
2976	PCIDevSetByte(&pBus->aPciDev, VBOX_PCI_PRIMARY_BUS, 0);
2977	PCIDevSetByte(&pBus->aPciDev, VBOX_PCI_SECONDARY_BUS, 0);
2978	PCIDevSetByte(&pBus->aPciDev, VBOX_PCI_SUBORDINATE_BUS, 0);
2979
2980	/* PCI-specific reset for each device. */
2981	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
2982	{
2983	if (pBus->apDevices[i])
2984	ich9pciResetDevice(pBus->apDevices[i]);
2985	}
2986	}
2987
2988
2989	/**
2990	* @copydoc FNPDMDEVRELOCATE
2991	*/
2992	static DECLCALLBACK(void) ich9pcibridgeRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
2993	{
2994	PICH9PCIBUS pBus = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
2995	pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2996
2997	/* Relocate RC pointers for the attached pci devices. */
2998	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
2999	ich9pciRelocateDevice(pBus->apDevices[i], offDelta);
3000	}
3001
3002	/**
3003	* The PCI bus device registration structure.
3004	*/
3005	const PDMDEVREG g_DevicePciIch9 =
3006	{
3007	/* u32Version */
3008	PDM_DEVREG_VERSION,
3009	/* szName */
3010	"ich9pci",
3011	/* szRCMod */
3012	"VBoxDDRC.rc",
3013	/* szR0Mod */
3014	"VBoxDDR0.r0",
3015	/* pszDescription */
3016	"ICH9 PCI bridge",
3017	/* fFlags */
3018	PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
3019	/* fClass */
3020	PDM_DEVREG_CLASS_BUS_PCI \| PDM_DEVREG_CLASS_BUS_ISA,
3021	/* cMaxInstances */
3022	1,
3023	/* cbInstance */
3024	sizeof(ICH9PCIGLOBALS),
3025	/* pfnConstruct */
3026	ich9pciConstruct,
3027	/* pfnDestruct */
3028	NULL,
3029	/* pfnRelocate */
3030	ich9pciRelocate,
3031	/* pfnMemSetup */
3032	NULL,
3033	/* pfnPowerOn */
3034	NULL,
3035	/* pfnReset */
3036	ich9pciReset,
3037	/* pfnSuspend */
3038	NULL,
3039	/* pfnResume */
3040	NULL,
3041	/* pfnAttach */
3042	NULL,
3043	/* pfnDetach */
3044	NULL,
3045	/* pfnQueryInterface */
3046	NULL,
3047	/* pfnInitComplete */
3048	NULL,
3049	/* pfnPowerOff */
3050	NULL,
3051	/* pfnSoftReset */
3052	NULL,
3053	/* u32VersionEnd */
3054	PDM_DEVREG_VERSION
3055	};
3056
3057	/**
3058	* The device registration structure
3059	* for the PCI-to-PCI bridge.
3060	*/
3061	const PDMDEVREG g_DevicePciIch9Bridge =
3062	{
3063	/* u32Version */
3064	PDM_DEVREG_VERSION,
3065	/* szName */
3066	"ich9pcibridge",
3067	/* szRCMod */
3068	"VBoxDDRC.rc",
3069	/* szR0Mod */
3070	"VBoxDDR0.r0",
3071	/* pszDescription */
3072	"ICH9 PCI to PCI bridge",
3073	/* fFlags */
3074	PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
3075	/* fClass */
3076	PDM_DEVREG_CLASS_BUS_PCI,
3077	/* cMaxInstances */
3078	~0U,
3079	/* cbInstance */
3080	sizeof(ICH9PCIBUS),
3081	/* pfnConstruct */
3082	ich9pcibridgeConstruct,
3083	/* pfnDestruct */
3084	NULL,
3085	/* pfnRelocate */
3086	ich9pcibridgeRelocate,
3087	/* pfnMemSetup */
3088	NULL,
3089	/* pfnPowerOn */
3090	NULL,
3091	/* pfnReset */
3092	NULL, /* Must be NULL, to make sure only bus driver handles reset */
3093	/* pfnSuspend */
3094	NULL,
3095	/* pfnResume */
3096	NULL,
3097	/* pfnAttach */
3098	NULL,
3099	/* pfnDetach */
3100	NULL,
3101	/* pfnQueryInterface */
3102	NULL,
3103	/* pfnInitComplete */
3104	NULL,
3105	/* pfnPowerOff */
3106	NULL,
3107	/* pfnSoftReset */
3108	NULL,
3109	/* u32VersionEnd */
3110	PDM_DEVREG_VERSION
3111	};
3112
3113	#endif /* IN_RING3 */
3114	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */

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source: vbox/trunk/src/VBox/Devices/Bus/DevPciIch9.cpp@ 63845

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