DevPciIch9.cpp@ 64115

Last change on this file since 64115 was 64115, checked in by vboxsync, 8 years ago
PDM,IOM,PGM: Morphed the MMIO2 API into a mixed MMIO2 and pre-registered MMIO API that is able to deal with really large (<= 64GB) MMIO ranges. Limited testing, so back out at first sign of trouble.
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1	/* $Id: DevPciIch9.cpp 64115 2016-09-30 20:14:27Z vboxsync $ */
2	/** @file
3	* DevPCI - ICH9 southbridge PCI bus emulation device.
4	*
5	* @note bird: I've cleaned up DevPCI.cpp to some extent, this file has not
6	* be cleaned up and because of pending code merge.
7	*/
8
9	/*
10	* Copyright (C) 2010-2016 Oracle Corporation
11	*
12	* This file is part of VirtualBox Open Source Edition (OSE), as
13	* available from http://www.virtualbox.org. This file is free software;
14	* you can redistribute it and/or modify it under the terms of the GNU
15	* General Public License (GPL) as published by the Free Software
16	* Foundation, in version 2 as it comes in the "COPYING" file of the
17	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
18	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
19	*/
20
21
22	/*********************************************************************************************************************************
23	* Header Files *
24	*********************************************************************************************************************************/
25	#define LOG_GROUP LOG_GROUP_DEV_PCI
26	/* Hack to get PCIDEVICEINT declared at the right point - include "PCIInternal.h". */
27	#define PCI_INCLUDE_PRIVATE
28	#define PCIBus ICH9PCIBus
29	#include <VBox/pci.h>
30	#include <VBox/msi.h>
31	#include <VBox/vmm/pdmdev.h>
32	#include <VBox/vmm/mm.h>
33	#include <iprt/asm.h>
34	#include <iprt/assert.h>
35	#include <iprt/string.h>
36	#ifdef IN_RING3
37	#include <iprt/alloc.h>
38	#endif
39
40	#include "VBoxDD.h"
41	#include "MsiCommon.h"
42
43
44	/*********************************************************************************************************************************
45	* Structures and Typedefs *
46	*********************************************************************************************************************************/
47	/**
48	* PCI Bus instance.
49	*/
50	typedef struct ICH9PCIBus
51	{
52	/** Bus number. */
53	int32_t iBus;
54	/** Number of bridges attached to the bus. */
55	uint32_t cBridges;
56
57	/** Array of PCI devices. We assume 32 slots, each with 8 functions. */
58	R3PTRTYPE(PPCIDEVICE) apDevices[256];
59	/** Array of bridges attached to the bus. */
60	R3PTRTYPE(PPCIDEVICE *) papBridgesR3;
61
62	/** R3 pointer to the device instance. */
63	PPDMDEVINSR3 pDevInsR3;
64	/** Pointer to the PCI R3 helpers. */
65	PCPDMPCIHLPR3 pPciHlpR3;
66
67	/** R0 pointer to the device instance. */
68	PPDMDEVINSR0 pDevInsR0;
69	/** Pointer to the PCI R0 helpers. */
70	PCPDMPCIHLPR0 pPciHlpR0;
71
72	/** RC pointer to the device instance. */
73	PPDMDEVINSRC pDevInsRC;
74	/** Pointer to the PCI RC helpers. */
75	PCPDMPCIHLPRC pPciHlpRC;
76
77	/** The PCI device for the PCI bridge. */
78	PCIDEVICE aPciDev;
79
80	} ICH9PCIBUS, *PICH9PCIBUS;
81
82
83	/** @def PCI_APIC_IRQ_PINS
84	* Number of pins for interrupts if the APIC is used.
85	*/
86	#define PCI_APIC_IRQ_PINS 8
87
88	/**
89	* PCI Globals - This is the host-to-pci bridge and the root bus.
90	*/
91	typedef struct
92	{
93	/** R3 pointer to the device instance. */
94	PPDMDEVINSR3 pDevInsR3;
95	/** R0 pointer to the device instance. */
96	PPDMDEVINSR0 pDevInsR0;
97	/** RC pointer to the device instance. */
98	PPDMDEVINSRC pDevInsRC;
99
100	/** Value latched in Configuration Address Port (0CF8h) */
101	uint32_t uConfigReg;
102
103	/** I/O APIC irq levels */
104	volatile uint32_t uaPciApicIrqLevels[PCI_APIC_IRQ_PINS];
105
106	#if 1 /* Will be moved into the BIOS soon. */
107	/** The next I/O port address which the PCI BIOS will use. */
108	uint32_t uPciBiosIo;
109	/** The next MMIO address which the PCI BIOS will use. */
110	uint32_t uPciBiosMmio;
111	/** The next 64-bit MMIO address which the PCI BIOS will use. */
112	uint64_t uPciBiosMmio64;
113	/** Actual bus number. */
114	uint8_t uBus;
115	uint8_t Alignment0[7];
116	#endif
117	/** Physical address of PCI config space MMIO region. */
118	uint64_t u64PciConfigMMioAddress;
119	/** Length of PCI config space MMIO region. */
120	uint64_t u64PciConfigMMioLength;
121
122	/** PCI bus which is attached to the host-to-PCI bridge. */
123	ICH9PCIBUS aPciBus;
124	} ICH9PCIGLOBALS, *PICH9PCIGLOBALS;
125
126
127	/**
128	* PCI configuration space address.
129	*/
130	typedef struct
131	{
132	uint8_t iBus;
133	uint8_t iDeviceFunc;
134	uint16_t iRegister;
135	} PciAddress;
136
137	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
138
139
140	/*********************************************************************************************************************************
141	* Defined Constants And Macros *
142	*********************************************************************************************************************************/
143
144	/** @def VBOX_ICH9PCI_SAVED_STATE_VERSION
145	* Saved state version of the ICH9 PCI bus device.
146	*/
147	#define VBOX_ICH9PCI_SAVED_STATE_VERSION_NOMSI 1
148	#define VBOX_ICH9PCI_SAVED_STATE_VERSION_MSI 2
149	#define VBOX_ICH9PCI_SAVED_STATE_VERSION_CURRENT VBOX_ICH9PCI_SAVED_STATE_VERSION_MSI
150
151	/** Converts a bus instance pointer to a device instance pointer. */
152	#define PCIBUS_2_DEVINS(pPciBus) ((pPciBus)->CTX_SUFF(pDevIns))
153	/** Converts a device instance pointer to a ICH9PCIGLOBALS pointer. */
154	#define DEVINS_2_PCIGLOBALS(pDevIns) ((PICH9PCIGLOBALS)(PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS)))
155	/** Converts a device instance pointer to a PCIBUS pointer. */
156	#define DEVINS_2_PCIBUS(pDevIns) ((PICH9PCIBUS)(&PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS)->aPciBus))
157	/** Converts a pointer to a PCI root bus instance to a PCIGLOBALS pointer. */
158	#define PCIROOTBUS_2_PCIGLOBALS(pPciBus) ( (PICH9PCIGLOBALS)((uintptr_t)(pPciBus) - RT_OFFSETOF(ICH9PCIGLOBALS, aPciBus)) )
159
160	/** @def PCI_LOCK
161	* Acquires the PDM lock. This is a NOP if locking is disabled. */
162	/** @def PCI_UNLOCK
163	* Releases the PDM lock. This is a NOP if locking is disabled. */
164	#define PCI_LOCK(pDevIns, rc) \
165	do { \
166	int rc2 = DEVINS_2_PCIBUS(pDevIns)->CTX_SUFF(pPciHlp)->pfnLock((pDevIns), rc); \
167	if (rc2 != VINF_SUCCESS) \
168	return rc2; \
169	} while (0)
170	#define PCI_UNLOCK(pDevIns) \
171	DEVINS_2_PCIBUS(pDevIns)->CTX_SUFF(pPciHlp)->pfnUnlock(pDevIns)
172
173	/* Prototypes */
174	static void ich9pciSetIrqInternal(PICH9PCIGLOBALS pGlobals, uint8_t uDevFn, PPCIDEVICE pPciDev,
175	int iIrq, int iLevel, uint32_t uTagSrc);
176	#ifdef IN_RING3
177	static void ich9pcibridgeReset(PPDMDEVINS pDevIns);
178	static int ich9pciRegisterInternal(PICH9PCIBUS pBus, int iDev, PPCIDEVICE pPciDev, const char *pszName);
179	static void ich9pciUpdateMappings(PCIDevice *pDev);
180	static DECLCALLBACK(uint32_t) ich9pciConfigReadDev(PCIDevice *aDev, uint32_t u32Address, unsigned len);
181	DECLINLINE(PPCIDEVICE) ich9pciFindBridge(PICH9PCIBUS pBus, uint8_t iBus);
182	static void ich9pciBiosInitDevice(PICH9PCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn);
183	#endif
184
185	// See 7.2.2. PCI Express Enhanced Configuration Mechanism for details of address
186	// mapping, we take n=6 approach
187	DECLINLINE(void) ich9pciPhysToPciAddr(PICH9PCIGLOBALS pGlobals, RTGCPHYS GCPhysAddr, PciAddress* pPciAddr)
188	{
189	NOREF(pGlobals);
190	pPciAddr->iBus = (GCPhysAddr >> 20) & ((1<<6) - 1);
191	pPciAddr->iDeviceFunc = (GCPhysAddr >> 12) & ((1<<(5+3)) - 1); // 5 bits - device, 3 bits - function
192	pPciAddr->iRegister = (GCPhysAddr >> 0) & ((1<<(6+4+2)) - 1); // 6 bits - register, 4 bits - extended register, 2 bits -Byte Enable
193	}
194
195	DECLINLINE(void) ich9pciStateToPciAddr(PICH9PCIGLOBALS pGlobals, RTGCPHYS addr, PciAddress* pPciAddr)
196	{
197	pPciAddr->iBus = (pGlobals->uConfigReg >> 16) & 0xff;
198	pPciAddr->iDeviceFunc = (pGlobals->uConfigReg >> 8) & 0xff;
199	pPciAddr->iRegister = (pGlobals->uConfigReg & 0xfc) \| (addr & 3);
200	}
201
202	PDMBOTHCBDECL(void) ich9pciSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel, uint32_t uTagSrc)
203	{
204	LogFlowFunc(("invoked by %p/%d: iIrq=%d iLevel=%d uTagSrc=%#x\n", pDevIns, pDevIns->iInstance, iIrq, iLevel, uTagSrc));
205	ich9pciSetIrqInternal(PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS), pPciDev->devfn, pPciDev, iIrq, iLevel, uTagSrc);
206	}
207
208	PDMBOTHCBDECL(void) ich9pcibridgeSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel, uint32_t uTagSrc)
209	{
210	/*
211	* The PCI-to-PCI bridge specification defines how the interrupt pins
212	* are routed from the secondary to the primary bus (see chapter 9).
213	* iIrq gives the interrupt pin the pci device asserted.
214	* We change iIrq here according to the spec and call the SetIrq function
215	* of our parent passing the device which asserted the interrupt instead of the device of the bridge.
216	*/
217	PICH9PCIBUS pBus = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
218	PPCIDEVICE pPciDevBus = pPciDev;
219	int iIrqPinBridge = iIrq;
220	uint8_t uDevFnBridge = 0;
221
222	/* Walk the chain until we reach the host bus. */
223	do
224	{
225	uDevFnBridge = pBus->aPciDev.devfn;
226	iIrqPinBridge = ((pPciDevBus->devfn >> 3) + iIrqPinBridge) & 3;
227
228	/* Get the parent. */
229	pBus = pBus->aPciDev.Int.s.CTX_SUFF(pBus);
230	pPciDevBus = &pBus->aPciDev;
231	} while (pBus->iBus != 0);
232
233	AssertMsgReturnVoid(pBus->iBus == 0, ("This is not the host pci bus iBus=%d\n", pBus->iBus));
234	ich9pciSetIrqInternal(PCIROOTBUS_2_PCIGLOBALS(pBus), uDevFnBridge, pPciDev, iIrqPinBridge, iLevel, uTagSrc);
235	}
236
237
238	/**
239	* Port I/O Handler for PCI address OUT operations.
240	*
241	* Emulates writes to Configuration Address Port at 0CF8h for
242	* Configuration Mechanism #1.
243	*
244	* @returns VBox status code.
245	*
246	* @param pDevIns ICH9 device instance.
247	* @param pvUser User argument - ignored.
248	* @param uPort Port number used for the OUT operation.
249	* @param u32 The value to output.
250	* @param cb The value size in bytes.
251	*/
252	PDMBOTHCBDECL(int) ich9pciIOPortAddressWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
253	{
254	LogFlow(("ich9pciIOPortAddressWrite: Port=%#x u32=%#x cb=%d\n", Port, u32, cb));
255	RT_NOREF2(Port, pvUser);
256	if (cb == 4)
257	{
258	PICH9PCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
259
260	/*
261	* bits [1:0] are hard-wired, read-only and must return zeroes
262	* when read.
263	*/
264	u32 &= ~3;
265
266	PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_WRITE);
267	pThis->uConfigReg = u32;
268	PCI_UNLOCK(pDevIns);
269	}
270
271	return VINF_SUCCESS;
272	}
273
274
275	/**
276	* Port I/O Handler for PCI address IN operations.
277	*
278	* Emulates reads from Configuration Address Port at 0CF8h for
279	* Configuration Mechanism #1.
280	*
281	* @returns VBox status code.
282	*
283	* @param pDevIns ICH9 device instance.
284	* @param pvUser User argument - ignored.
285	* @param uPort Port number used for the IN operation.
286	* @param pu32 Where to store the result.
287	* @param cb Number of bytes read.
288	*/
289	PDMBOTHCBDECL(int) ich9pciIOPortAddressRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
290	{
291	RT_NOREF2(Port, pvUser);
292	if (cb == 4)
293	{
294	PICH9PCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
295
296	PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_READ);
297	*pu32 = pThis->uConfigReg;
298	PCI_UNLOCK(pDevIns);
299
300	LogFlow(("ich9pciIOPortAddressRead: Port=%#x cb=%d -> %#x\n", Port, cb, *pu32));
301	return VINF_SUCCESS;
302	}
303
304	Log(("ich9pciIOPortAddressRead: Port=%#x cb=%d VERR_IOM_IOPORT_UNUSED\n", Port, cb));
305	return VERR_IOM_IOPORT_UNUSED;
306	}
307
308
309	/*
310	* Perform configuration space write.
311	*/
312	static int ich9pciDataWriteAddr(PICH9PCIGLOBALS pGlobals, PciAddress* pAddr,
313	uint32_t val, int cb, int rcReschedule)
314	{
315	int rc = VINF_SUCCESS;
316	#ifdef IN_RING3
317	NOREF(rcReschedule);
318	#else
319	RT_NOREF2(val, cb);
320	#endif
321
322	if (pAddr->iBus != 0) /* forward to subordinate bus */
323	{
324	if (pGlobals->aPciBus.cBridges)
325	{
326	#ifdef IN_RING3 /** @todo do lookup in R0/RC too! */
327	PPCIDEVICE pBridgeDevice = ich9pciFindBridge(&pGlobals->aPciBus, pAddr->iBus);
328	if (pBridgeDevice)
329	{
330	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigWrite);
331	pBridgeDevice->Int.s.pfnBridgeConfigWrite(pBridgeDevice->pDevIns, pAddr->iBus, pAddr->iDeviceFunc,
332	pAddr->iRegister, val, cb);
333	}
334	#else
335	rc = rcReschedule;
336	#endif
337	}
338	}
339	else /* forward to directly connected device */
340	{
341	R3PTRTYPE(PCIDevice *) aDev = pGlobals->aPciBus.apDevices[pAddr->iDeviceFunc];
342	if (aDev)
343	{
344	#ifdef IN_RING3
345	aDev->Int.s.pfnConfigWrite(aDev, pAddr->iRegister, val, cb);
346	#else
347	rc = rcReschedule;
348	#endif
349	}
350	}
351
352	Log2(("ich9pciDataWriteAddr: %02x:%02x:%02x reg %x(%d) %x %Rrc\n",
353	pAddr->iBus, pAddr->iDeviceFunc >> 3, pAddr->iDeviceFunc & 0x7, pAddr->iRegister,
354	cb, val, rc));
355	return rc;
356	}
357
358
359	/*
360	* Decode value latched in Configuration Address Port and perform
361	* requsted write to the target configuration space register.
362	*
363	* XXX: This code should be probably moved to its only caller
364	* (ich9pciIOPortDataWrite) to avoid prolifiration of confusingly
365	* similarly named functions.
366	*/
367	static int ich9pciDataWrite(PICH9PCIGLOBALS pGlobals, uint32_t addr, uint32_t val, int len)
368	{
369	LogFlow(("ich9pciDataWrite: config=%08x val=%08x len=%d\n", pGlobals->uConfigReg, val, len));
370
371	/* Configuration space mapping enabled? */
372	if (!(pGlobals->uConfigReg & (1 << 31)))
373	return VINF_SUCCESS;
374
375	/* Decode target device and configuration space register */
376	PciAddress aPciAddr;
377	ich9pciStateToPciAddr(pGlobals, addr, &aPciAddr);
378
379	/* Perform configuration space write */
380	return ich9pciDataWriteAddr(pGlobals, &aPciAddr, val, len, VINF_IOM_R3_IOPORT_WRITE);
381	}
382
383
384	/**
385	* Port I/O Handler for PCI data OUT operations.
386	*
387	* Emulates writes to Configuration Data Port at 0CFCh for
388	* Configuration Mechanism #1.
389	*
390	* @returns VBox status code.
391	*
392	* @param pDevIns ICH9 device instance.
393	* @param pvUser User argument - ignored.
394	* @param uPort Port number used for the OUT operation.
395	* @param u32 The value to output.
396	* @param cb The value size in bytes.
397	*/
398	PDMBOTHCBDECL(int) ich9pciIOPortDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
399	{
400	LogFlow(("ich9pciIOPortDataWrite: Port=%#x u32=%#x cb=%d\n", Port, u32, cb));
401	NOREF(pvUser);
402	int rc = VINF_SUCCESS;
403	if (!(Port % cb))
404	{
405	PICH9PCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
406
407	PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_WRITE);
408	rc = ich9pciDataWrite(pThis, Port, u32, cb);
409	PCI_UNLOCK(pDevIns);
410	}
411	else
412	AssertMsgFailed(("Unaligned write to port %#x u32=%#x cb=%d\n", Port, u32, cb));
413	return rc;
414	}
415
416
417	static void ich9pciNoMem(void* ptr, int cb)
418	{
419	for (int i = 0; i < cb; i++)
420	((uint8_t*)ptr)[i] = 0xff;
421	}
422
423
424	/*
425	* Perform configuration space read.
426	*/
427	static int ich9pciDataReadAddr(PICH9PCIGLOBALS pGlobals, PciAddress* pPciAddr, int cb,
428	uint32_t *pu32, int rcReschedule)
429	{
430	int rc = VINF_SUCCESS;
431	#ifdef IN_RING3
432	NOREF(rcReschedule);
433	#endif
434
435	if (pPciAddr->iBus != 0) /* forward to subordinate bus */
436	{
437	if (pGlobals->aPciBus.cBridges)
438	{
439	#ifdef IN_RING3 /** @todo do lookup in R0/RC too! */
440	PPCIDEVICE pBridgeDevice = ich9pciFindBridge(&pGlobals->aPciBus, pPciAddr->iBus);
441	if (pBridgeDevice)
442	{
443	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigRead);
444	*pu32 = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->pDevIns, pPciAddr->iBus, pPciAddr->iDeviceFunc, pPciAddr->iRegister, cb);
445	}
446	else
447	ich9pciNoMem(pu32, cb);
448	#else
449	rc = rcReschedule;
450	#endif
451	}
452	else
453	ich9pciNoMem(pu32, cb);
454	}
455	else /* forward to directly connected device */
456	{
457	R3PTRTYPE(PCIDevice *) aDev = pGlobals->aPciBus.apDevices[pPciAddr->iDeviceFunc];
458	if (aDev)
459	{
460	#ifdef IN_RING3
461	*pu32 = aDev->Int.s.pfnConfigRead(aDev, pPciAddr->iRegister, cb);
462	#else
463	rc = rcReschedule;
464	#endif
465	}
466	else
467	ich9pciNoMem(pu32, cb);
468	}
469
470	Log3(("ich9pciDataReadAddr: %02x:%02x:%02x reg %x(%d) gave %x %Rrc\n",
471	pPciAddr->iBus, pPciAddr->iDeviceFunc >> 3, pPciAddr->iDeviceFunc & 0x7, pPciAddr->iRegister,
472	cb, *pu32, rc));
473	return rc;
474	}
475
476
477	/*
478	* Decode value latched in Configuration Address Port and perform
479	* requsted read from the target configuration space register.
480	*
481	* XXX: This code should be probably moved to its only caller
482	* (ich9pciIOPortDataRead) to avoid prolifiration of confusingly
483	* similarly named functions.
484	*/
485	static int ich9pciDataRead(PICH9PCIGLOBALS pGlobals, uint32_t addr, int cb, uint32_t *pu32)
486	{
487	LogFlow(("ich9pciDataRead: config=%x cb=%d\n", pGlobals->uConfigReg, cb));
488
489	*pu32 = 0xffffffff;
490
491	/* Configuration space mapping enabled? */
492	if (!(pGlobals->uConfigReg & (1 << 31)))
493	return VINF_SUCCESS;
494
495	/* Decode target device and configuration space register */
496	PciAddress aPciAddr;
497	ich9pciStateToPciAddr(pGlobals, addr, &aPciAddr);
498
499	/* Perform configuration space read */
500	return ich9pciDataReadAddr(pGlobals, &aPciAddr, cb, pu32, VINF_IOM_R3_IOPORT_READ);
501	}
502
503
504	/**
505	* Port I/O Handler for PCI data IN operations.
506	*
507	* Emulates reads from Configuration Data Port at 0CFCh for
508	* Configuration Mechanism #1.
509	*
510	* @returns VBox status code.
511	*
512	* @param pDevIns ICH9 device instance.
513	* @param pvUser User argument - ignored.
514	* @param uPort Port number used for the IN operation.
515	* @param pu32 Where to store the result.
516	* @param cb Number of bytes read.
517	*/
518	PDMBOTHCBDECL(int) ich9pciIOPortDataRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
519	{
520	NOREF(pvUser);
521	if (!(Port % cb))
522	{
523	PICH9PCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
524
525	PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_READ);
526	int rc = ich9pciDataRead(pThis, Port, cb, pu32);
527	PCI_UNLOCK(pDevIns);
528
529	LogFlow(("ich9pciIOPortDataRead: Port=%#x cb=%#x -> %#x (%Rrc)\n", Port, cb, *pu32, rc));
530	return rc;
531	}
532	AssertMsgFailed(("Unaligned read from port %#x cb=%d\n", Port, cb));
533	return VERR_IOM_IOPORT_UNUSED;
534	}
535
536
537	/* Compute mapping of PCI slot and IRQ number to APIC interrupt line */
538	DECLINLINE(int) ich9pciSlot2ApicIrq(uint8_t uSlot, int irq_num)
539	{
540	return (irq_num + uSlot) & 7;
541	}
542
543	#ifdef IN_RING3
544
545	/* return the global irq number corresponding to a given device irq
546	pin. We could also use the bus number to have a more precise
547	mapping. This is the implementation note described in the PCI spec chapter 2.2.6 */
548	DECLINLINE(int) ich9pciSlotGetPirq(uint8_t uBus, uint8_t uDevFn, int iIrqNum)
549	{
550	NOREF(uBus);
551	int iSlotAddend = (uDevFn >> 3) - 1;
552	return (iIrqNum + iSlotAddend) & 3;
553	}
554
555	/* irqs corresponding to PCI irqs A-D, must match pci_irq_list in rombios.c */
556	static const uint8_t aPciIrqs[4] = { 11, 10, 9, 5 };
557
558	#endif /* IN_RING3 */
559
560	/* Add one more level up request on APIC input line */
561	DECLINLINE(void) ich9pciApicLevelUp(PICH9PCIGLOBALS pGlobals, int irq_num)
562	{
563	ASMAtomicIncU32(&pGlobals->uaPciApicIrqLevels[irq_num]);
564	}
565
566	/* Remove one level up request on APIC input line */
567	DECLINLINE(void) ich9pciApicLevelDown(PICH9PCIGLOBALS pGlobals, int irq_num)
568	{
569	ASMAtomicDecU32(&pGlobals->uaPciApicIrqLevels[irq_num]);
570	}
571
572	static void ich9pciApicSetIrq(PICH9PCIBUS pBus, uint8_t uDevFn, PCIDevice *pPciDev, int irq_num1, int iLevel,
573	uint32_t uTagSrc, int iForcedIrq)
574	{
575	/* This is only allowed to be called with a pointer to the root bus. */
576	AssertMsg(pBus->iBus == 0, ("iBus=%u\n", pBus->iBus));
577
578	if (iForcedIrq == -1)
579	{
580	int apic_irq, apic_level;
581	PICH9PCIGLOBALS pGlobals = PCIROOTBUS_2_PCIGLOBALS(pBus);
582	int irq_num = ich9pciSlot2ApicIrq(uDevFn >> 3, irq_num1);
583
584	if ((iLevel & PDM_IRQ_LEVEL_HIGH) == PDM_IRQ_LEVEL_HIGH)
585	ich9pciApicLevelUp(pGlobals, irq_num);
586	else if ((iLevel & PDM_IRQ_LEVEL_HIGH) == PDM_IRQ_LEVEL_LOW)
587	ich9pciApicLevelDown(pGlobals, irq_num);
588
589	apic_irq = irq_num + 0x10;
590	apic_level = pGlobals->uaPciApicIrqLevels[irq_num] != 0;
591	Log3(("ich9pciApicSetIrq: %s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d uTagSrc=%#x\n",
592	R3STRING(pPciDev->name), irq_num1, iLevel, apic_irq, apic_level, irq_num, uTagSrc));
593	pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), apic_irq, apic_level, uTagSrc);
594
595	if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP)
596	{
597	/*
598	* we raised it few lines above, as PDM_IRQ_LEVEL_FLIP_FLOP has
599	* PDM_IRQ_LEVEL_HIGH bit set
600	*/
601	ich9pciApicLevelDown(pGlobals, irq_num);
602	pPciDev->Int.s.uIrqPinState = PDM_IRQ_LEVEL_LOW;
603	apic_level = pGlobals->uaPciApicIrqLevels[irq_num] != 0;
604	Log3(("ich9pciApicSetIrq: %s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d uTagSrc=%#x (flop)\n",
605	R3STRING(pPciDev->name), irq_num1, iLevel, apic_irq, apic_level, irq_num, uTagSrc));
606	pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), apic_irq, apic_level, uTagSrc);
607	}
608	} else {
609	Log3(("ich9pciApicSetIrq: (forced) %s: irq_num1=%d level=%d acpi_irq=%d uTagSrc=%#x\n",
610	R3STRING(pPciDev->name), irq_num1, iLevel, iForcedIrq, uTagSrc));
611	pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), iForcedIrq, iLevel, uTagSrc);
612	}
613	}
614
615	static void ich9pciSetIrqInternal(PICH9PCIGLOBALS pGlobals, uint8_t uDevFn, PPCIDEVICE pPciDev,
616	int iIrq, int iLevel, uint32_t uTagSrc)
617	{
618	/* If MSI or MSI-X is enabled, PCI INTx# signals are disabled regardless of the PCI command
619	* register interrupt bit state.
620	* PCI 3.0 (section 6.8) forbids MSI and MSI-X to be enabled at the same time and makes
621	* that undefined behavior. We check for MSI first, then MSI-X.
622	*/
623	if (MsiIsEnabled(pPciDev))
624	{
625	Assert(!MsixIsEnabled(pPciDev)); /* Not allowed -- see note above. */
626	LogFlowFunc(("PCI Dev %p : MSI\n", pPciDev));
627	PPDMDEVINS pDevIns = pGlobals->aPciBus.CTX_SUFF(pDevIns);
628	MsiNotify(pDevIns, pGlobals->aPciBus.CTX_SUFF(pPciHlp), pPciDev, iIrq, iLevel, uTagSrc);
629	return;
630	}
631
632	if (MsixIsEnabled(pPciDev))
633	{
634	LogFlowFunc(("PCI Dev %p : MSI-X\n", pPciDev));
635	PPDMDEVINS pDevIns = pGlobals->aPciBus.CTX_SUFF(pDevIns);
636	MsixNotify(pDevIns, pGlobals->aPciBus.CTX_SUFF(pPciHlp), pPciDev, iIrq, iLevel, uTagSrc);
637	return;
638	}
639
640	PICH9PCIBUS pBus = &pGlobals->aPciBus;
641	const bool fIsAcpiDevice = PCIDevGetDeviceId(pPciDev) == 0x7113;
642
643	LogFlowFunc(("PCI Dev %p : IRQ\n", pPciDev));
644	/* Check if the state changed. */
645	if (pPciDev->Int.s.uIrqPinState != iLevel)
646	{
647	pPciDev->Int.s.uIrqPinState = (iLevel & PDM_IRQ_LEVEL_HIGH);
648
649	/* Send interrupt to I/O APIC only now. */
650	if (fIsAcpiDevice)
651	/*
652	* ACPI needs special treatment since SCI is hardwired and
653	* should not be affected by PCI IRQ routing tables at the
654	* same time SCI IRQ is shared in PCI sense hence this
655	* kludge (i.e. we fetch the hardwired value from ACPIs
656	* PCI device configuration space).
657	*/
658	ich9pciApicSetIrq(pBus, uDevFn, pPciDev, -1, iLevel, uTagSrc, PCIDevGetInterruptLine(pPciDev));
659	else
660	ich9pciApicSetIrq(pBus, uDevFn, pPciDev, iIrq, iLevel, uTagSrc, -1);
661	}
662	}
663
664
665	/**
666	* Memory mapped I/O Handler for write operations.
667	*
668	* Emulates writes to configuration space.
669	*
670	* @returns VBox status code.
671	*
672	* @param pDevIns The device instance.
673	* @param pvUser User argument.
674	* @param GCPhysAddr Physical address (in GC) where the read starts.
675	* @param pv Where to fetch the result.
676	* @param cb Number of bytes to write.
677	* @remarks Caller enters the device critical section.
678	*/
679	PDMBOTHCBDECL(int) ich9pciMcfgMMIOWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void const pv, unsigned cb)
680	{
681	PICH9PCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
682	uint32_t u32 = 0;
683	NOREF(pvUser);
684
685	Log2(("ich9pciMcfgMMIOWrite: %RGp(%d) \n", GCPhysAddr, cb));
686
687	PCI_LOCK(pDevIns, VINF_IOM_R3_MMIO_WRITE);
688
689	/* Decode target device and configuration space register */
690	PciAddress aDest;
691	ich9pciPhysToPciAddr(pGlobals, GCPhysAddr, &aDest);
692
693	switch (cb)
694	{
695	case 1:
696	u32 = (uint8_t)pv;
697	break;
698	case 2:
699	u32 = (uint16_t)pv;
700	break;
701	case 4:
702	u32 = (uint32_t)pv;
703	break;
704	default:
705	Assert(false);
706	break;
707	}
708
709	/* Perform configuration space write */
710	int rc = ich9pciDataWriteAddr(pGlobals, &aDest, u32, cb, VINF_IOM_R3_MMIO_WRITE);
711	PCI_UNLOCK(pDevIns);
712
713	return rc;
714	}
715
716
717	/**
718	* Memory mapped I/O Handler for read operations.
719	*
720	* Emulates reads from configuration space.
721	*
722	* @returns VBox status code.
723	*
724	* @param pDevIns The device instance.
725	* @param pvUser User argument.
726	* @param GCPhysAddr Physical address (in GC) where the read starts.
727	* @param pv Where to store the result.
728	* @param cb Number of bytes read.
729	* @remarks Caller enters the device critical section.
730	*/
731	PDMBOTHCBDECL(int) ich9pciMcfgMMIORead (PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb)
732	{
733	PICH9PCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
734	uint32_t rv;
735	NOREF(pvUser);
736
737	LogFlow(("ich9pciMcfgMMIORead: %RGp(%d) \n", GCPhysAddr, cb));
738
739	PCI_LOCK(pDevIns, VINF_IOM_R3_MMIO_READ);
740
741	/* Decode target device and configuration space register */
742	PciAddress aDest;
743	ich9pciPhysToPciAddr(pGlobals, GCPhysAddr, &aDest);
744
745	/* Perform configuration space read */
746	int rc = ich9pciDataReadAddr(pGlobals, &aDest, cb, &rv, VINF_IOM_R3_MMIO_READ);
747
748	if (RT_SUCCESS(rc))
749	{
750	switch (cb)
751	{
752	case 1:
753	(uint8_t)pv = (uint8_t)rv;
754	break;
755	case 2:
756	(uint16_t)pv = (uint16_t)rv;
757	break;
758	case 4:
759	(uint32_t)pv = (uint32_t)rv;
760	break;
761	default:
762	Assert(false);
763	break;
764	}
765	}
766	PCI_UNLOCK(pDevIns);
767
768	return rc;
769	}
770
771	#ifdef IN_RING3
772
773	DECLINLINE(PPCIDEVICE) ich9pciFindBridge(PICH9PCIBUS pBus, uint8_t iBus)
774	{
775	/* Search for a fitting bridge. */
776	for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
777	{
778	/*
779	* Examine secondary and subordinate bus number.
780	* If the target bus is in the range we pass the request on to the bridge.
781	*/
782	PPCIDEVICE pBridge = pBus->papBridgesR3[iBridge];
783	AssertMsg(pBridge && pciDevIsPci2PciBridge(pBridge),
784	("Device is not a PCI bridge but on the list of PCI bridges\n"));
785	uint32_t uSecondary = PCIDevGetByte(pBridge, VBOX_PCI_SECONDARY_BUS);
786	uint32_t uSubordinate = PCIDevGetByte(pBridge, VBOX_PCI_SUBORDINATE_BUS);
787	Log3(("ich9pciFindBridge on bus %p, bridge %d: %d in %d..%d\n", pBus, iBridge, iBus, uSecondary, uSubordinate));
788	if (iBus >= uSecondary && iBus <= uSubordinate)
789	return pBridge;
790	}
791
792	/* Nothing found. */
793	return NULL;
794	}
795
796	static uint32_t ich9pciGetCfg(PCIDevice* aDev, int32_t iRegister, int cb)
797	{
798	return aDev->Int.s.pfnConfigRead(aDev, iRegister, cb);
799	}
800
801	static uint8_t ich9pciGetByte(PCIDevice* aDev, int32_t iRegister)
802	{
803	return (uint8_t)ich9pciGetCfg(aDev, iRegister, 1);
804	}
805
806	static uint16_t ich9pciGetWord(PCIDevice* aDev, int32_t iRegister)
807	{
808	return (uint16_t)ich9pciGetCfg(aDev, iRegister, 2);
809	}
810
811	static uint32_t ich9pciGetDWord(PCIDevice* aDev, int32_t iRegister)
812	{
813	return (uint32_t)ich9pciGetCfg(aDev, iRegister, 4);
814	}
815
816	DECLINLINE(uint32_t) ich9pciGetRegionReg(int iRegion)
817	{
818	return (iRegion == VBOX_PCI_ROM_SLOT) ?
819	VBOX_PCI_ROM_ADDRESS : (VBOX_PCI_BASE_ADDRESS_0 + iRegion * 4);
820	}
821
822	#define INVALID_PCI_ADDRESS ~0U
823
824	static int ich9pciUnmapRegion(PPCIDEVICE pDev, int iRegion)
825	{
826	PCIIORegion* pRegion = &pDev->Int.s.aIORegions[iRegion];
827	int rc = VINF_SUCCESS;
828	PICH9PCIBUS pBus = pDev->Int.s.CTX_SUFF(pBus);
829
830	Assert (pRegion->size != 0);
831
832	if (pRegion->addr != INVALID_PCI_ADDRESS)
833	{
834	if (pRegion->type & PCI_ADDRESS_SPACE_IO)
835	{
836	/* Port IO */
837	rc = PDMDevHlpIOPortDeregister(pDev->pDevIns, pRegion->addr, pRegion->size);
838	AssertRC(rc);
839	}
840	else
841	{
842	RTGCPHYS GCPhysBase = pRegion->addr;
843	if (pBus->pPciHlpR3->pfnIsMMIOExBase(pBus->pDevInsR3, pDev->pDevIns, GCPhysBase))
844	{
845	/* unmap it. */
846	rc = pRegion->map_func(pDev, iRegion, NIL_RTGCPHYS, pRegion->size, (PCIADDRESSSPACE)(pRegion->type));
847	AssertRC(rc);
848	rc = PDMDevHlpMMIOExUnmap(pDev->pDevIns, iRegion, GCPhysBase);
849	}
850	else
851	rc = PDMDevHlpMMIODeregister(pDev->pDevIns, GCPhysBase, pRegion->size);
852	}
853
854	pRegion->addr = INVALID_PCI_ADDRESS;
855	}
856
857	return rc;
858	}
859
860	static void ich9pciUpdateMappings(PCIDevice* pDev)
861	{
862	uint64_t uLast, uNew;
863
864	int iCmd = ich9pciGetWord(pDev, VBOX_PCI_COMMAND);
865	for (int iRegion = 0; iRegion < PCI_NUM_REGIONS; iRegion++)
866	{
867	PCIIORegion* pRegion = &pDev->Int.s.aIORegions[iRegion];
868	uint32_t uConfigReg = ich9pciGetRegionReg(iRegion);
869	int64_t iRegionSize = pRegion->size;
870	int rc;
871
872	if (iRegionSize == 0)
873	continue;
874
875	bool f64Bit = (pRegion->type & ((uint8_t)(PCI_ADDRESS_SPACE_BAR64 \| PCI_ADDRESS_SPACE_IO)))
876	== PCI_ADDRESS_SPACE_BAR64;
877
878	if (pRegion->type & PCI_ADDRESS_SPACE_IO)
879	{
880	/* port IO region */
881	if (iCmd & PCI_COMMAND_IOACCESS)
882	{
883	/* IO access allowed */
884	uNew = ich9pciGetDWord(pDev, uConfigReg);
885	uNew &= ~(iRegionSize - 1);
886	uLast = uNew + iRegionSize - 1;
887	/* only 64K ioports on PC */
888	if (uLast <= uNew \|\| uNew == 0 \|\| uLast >= 0x10000)
889	uNew = INVALID_PCI_ADDRESS;
890	} else
891	uNew = INVALID_PCI_ADDRESS;
892	}
893	else
894	{
895	/* MMIO region */
896	if (iCmd & PCI_COMMAND_MEMACCESS)
897	{
898	uNew = ich9pciGetDWord(pDev, uConfigReg);
899
900	if (f64Bit)
901	{
902	uNew \|= ((uint64_t)ich9pciGetDWord(pDev, uConfigReg+4)) << 32;
903	/** @todo r=klaus Is this really true? Needs to be fixed properly. */
904	if (uNew > UINT64_C(0x0000010000000000))
905	{
906	/* Workaround for REM being unhapping with mapping very long 64-bit addresses */
907	LogRel(("Ignoring too long 64-bit BAR: %llx\n", uNew));
908	uNew = INVALID_PCI_ADDRESS;
909	}
910	}
911
912	/* the ROM slot has a specific enable bit */
913	if (iRegion == PCI_ROM_SLOT && !(uNew & 1))
914	uNew = INVALID_PCI_ADDRESS;
915	else
916	{
917	uNew &= ~(iRegionSize - 1);
918	uLast = uNew + iRegionSize - 1;
919	/* NOTE: we do not support wrapping */
920	/* XXX: as we cannot support really dynamic
921	mappings, we handle specific values as invalid
922	mappings. */
923	/* Unconditionally exclude I/O-APIC/HPET/ROM. Pessimistic, but better than causing a mess. */
924	if (uLast <= uNew \|\| uNew == 0 \|\| (uNew <= UINT32_C(0xffffffff) && uLast >= UINT32_C(0xfec00000)))
925	uNew = INVALID_PCI_ADDRESS;
926	}
927	} else
928	uNew = INVALID_PCI_ADDRESS;
929	}
930	LogRel2(("PCI: config dev %u/%u BAR%i uOld=%#018llx uNew=%#018llx size=%llu\n", pDev->devfn >> 3, pDev->devfn & 7, iRegion, pRegion->addr, uNew, pRegion->size));
931	/* now do the real mapping */
932	if (uNew != pRegion->addr)
933	{
934	if (pRegion->addr != INVALID_PCI_ADDRESS)
935	ich9pciUnmapRegion(pDev, iRegion);
936
937	pRegion->addr = uNew;
938	if (pRegion->addr != INVALID_PCI_ADDRESS)
939	{
940
941	/* finally, map the region */
942	rc = pRegion->map_func(pDev, iRegion,
943	pRegion->addr, pRegion->size,
944	(PCIADDRESSSPACE)(pRegion->type));
945	AssertRC(rc);
946	}
947	}
948
949	if (f64Bit)
950	iRegion++;
951	}
952	}
953
954	static DECLCALLBACK(int) ich9pciRegister(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, const char *pszName, int iDev)
955	{
956	PICH9PCIBUS pBus = DEVINS_2_PCIBUS(pDevIns);
957
958	/*
959	* Check input.
960	*/
961	if ( !pszName
962	\|\| !pPciDev
963	\|\| iDev >= (int)RT_ELEMENTS(pBus->apDevices)
964	)
965	{
966	AssertMsgFailed(("Invalid argument! pszName=%s pPciDev=%p iDev=%d\n", pszName, pPciDev, iDev));
967	return VERR_INVALID_PARAMETER;
968	}
969
970	/*
971	* Register the device.
972	*/
973	return ich9pciRegisterInternal(pBus, iDev, pPciDev, pszName);
974	}
975
976
977	static DECLCALLBACK(int) ich9pciRegisterMsi(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PPDMMSIREG pMsiReg)
978	{
979	NOREF(pDevIns);
980	int rc;
981
982	rc = MsiInit(pPciDev, pMsiReg);
983	if (RT_FAILURE(rc))
984	return rc;
985
986	rc = MsixInit(pPciDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pPciHlp), pPciDev, pMsiReg);
987	if (RT_FAILURE(rc))
988	return rc;
989
990	return VINF_SUCCESS;
991	}
992
993
994	static DECLCALLBACK(int) ich9pcibridgeRegister(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, const char *pszName, int iDev)
995	{
996
997	PICH9PCIBUS pBus = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
998
999	/*
1000	* Check input.
1001	*/
1002	if ( !pszName
1003	\|\| !pPciDev
1004	\|\| iDev >= (int)RT_ELEMENTS(pBus->apDevices))
1005	{
1006	AssertMsgFailed(("Invalid argument! pszName=%s pPciDev=%p iDev=%d\n", pszName, pPciDev, iDev));
1007	return VERR_INVALID_PARAMETER;
1008	}
1009
1010	/*
1011	* Register the device.
1012	*/
1013	return ich9pciRegisterInternal(pBus, iDev, pPciDev, pszName);
1014	}
1015
1016	static DECLCALLBACK(int) ich9pciIORegionRegister(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iRegion, RTGCPHYS cbRegion,
1017	PCIADDRESSSPACE enmType, PFNPCIIOREGIONMAP pfnCallback)
1018	{
1019	NOREF(pDevIns);
1020
1021	/*
1022	* Validate.
1023	*/
1024	AssertMsgReturn( enmType == (PCI_ADDRESS_SPACE_MEM \| PCI_ADDRESS_SPACE_BAR32)
1025	\|\| enmType == (PCI_ADDRESS_SPACE_MEM_PREFETCH \| PCI_ADDRESS_SPACE_BAR32)
1026	\|\| enmType == (PCI_ADDRESS_SPACE_MEM \| PCI_ADDRESS_SPACE_BAR64)
1027	\|\| enmType == (PCI_ADDRESS_SPACE_MEM_PREFETCH \| PCI_ADDRESS_SPACE_BAR64)
1028	\|\| enmType == PCI_ADDRESS_SPACE_IO
1029	,
1030	("Invalid enmType=%#x? Or was this a bitmask after all...\n", enmType),
1031	VERR_INVALID_PARAMETER);
1032	AssertMsgReturn((unsigned)iRegion < PCI_NUM_REGIONS,
1033	("Invalid iRegion=%d PCI_NUM_REGIONS=%d\n", iRegion, PCI_NUM_REGIONS),
1034	VERR_INVALID_PARAMETER);
1035	int iLastSet = ASMBitLastSetU64(cbRegion);
1036	AssertMsgReturn( iLastSet != 0
1037	&& RT_BIT_64(iLastSet - 1) == cbRegion,
1038	("Invalid cbRegion=%RGp iLastSet=%#x (not a power of 2 or 0)\n", cbRegion, iLastSet),
1039	VERR_INVALID_PARAMETER);
1040
1041	Log(("ich9pciIORegionRegister: %s region %d size %RGp type %x\n",
1042	pPciDev->name, iRegion, cbRegion, enmType));
1043
1044	/* Make sure that we haven't marked this region as continuation of 64-bit region. */
1045	Assert(pPciDev->Int.s.aIORegions[iRegion].type != 0xff);
1046
1047	/*
1048	* Register the I/O region.
1049	*/
1050	PPCIIOREGION pRegion = &pPciDev->Int.s.aIORegions[iRegion];
1051	pRegion->addr = INVALID_PCI_ADDRESS;
1052	pRegion->size = cbRegion;
1053	pRegion->type = enmType;
1054	pRegion->map_func = pfnCallback;
1055
1056	if ((enmType & PCI_ADDRESS_SPACE_BAR64) != 0)
1057	{
1058	/* VBOX_PCI_BASE_ADDRESS_5 and VBOX_PCI_ROM_ADDRESS are excluded. */
1059	AssertMsgReturn(iRegion < PCI_NUM_REGIONS - 2,
1060	("Region %d cannot be 64-bit\n", iRegion),
1061	VERR_INVALID_PARAMETER);
1062	/* Mark next region as continuation of this one. */
1063	pPciDev->Int.s.aIORegions[iRegion + 1].type = 0xff;
1064	}
1065
1066	/* Set type in the PCI config space. */
1067	uint32_t u32Value = (uint32_t)enmType & (PCI_ADDRESS_SPACE_IO \| PCI_ADDRESS_SPACE_BAR64 \| PCI_ADDRESS_SPACE_MEM_PREFETCH);
1068	PCIDevSetDWord(pPciDev, ich9pciGetRegionReg(iRegion), u32Value);
1069
1070	return VINF_SUCCESS;
1071	}
1072
1073	static DECLCALLBACK(void) ich9pciSetConfigCallbacks(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PFNPCICONFIGREAD pfnRead, PPFNPCICONFIGREAD ppfnReadOld,
1074	PFNPCICONFIGWRITE pfnWrite, PPFNPCICONFIGWRITE ppfnWriteOld)
1075	{
1076	NOREF(pDevIns);
1077
1078	if (ppfnReadOld)
1079	*ppfnReadOld = pPciDev->Int.s.pfnConfigRead;
1080	pPciDev->Int.s.pfnConfigRead = pfnRead;
1081
1082	if (ppfnWriteOld)
1083	*ppfnWriteOld = pPciDev->Int.s.pfnConfigWrite;
1084	pPciDev->Int.s.pfnConfigWrite = pfnWrite;
1085	}
1086
1087	static int ich9pciR3CommonSaveExec(PICH9PCIBUS pBus, PSSMHANDLE pSSM)
1088	{
1089	/*
1090	* Iterate thru all the devices.
1091	*/
1092	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
1093	{
1094	PPCIDEVICE pDev = pBus->apDevices[i];
1095	if (pDev)
1096	{
1097	/* Device position */
1098	SSMR3PutU32(pSSM, i);
1099	/* PCI config registers */
1100	SSMR3PutMem(pSSM, pDev->config, sizeof(pDev->config));
1101
1102	/* Device flags */
1103	int rc = SSMR3PutU32(pSSM, pDev->Int.s.fFlags);
1104	if (RT_FAILURE(rc))
1105	return rc;
1106
1107	/* IRQ pin state */
1108	rc = SSMR3PutS32(pSSM, pDev->Int.s.uIrqPinState);
1109	if (RT_FAILURE(rc))
1110	return rc;
1111
1112	/* MSI info */
1113	rc = SSMR3PutU8(pSSM, pDev->Int.s.u8MsiCapOffset);
1114	if (RT_FAILURE(rc))
1115	return rc;
1116	rc = SSMR3PutU8(pSSM, pDev->Int.s.u8MsiCapSize);
1117	if (RT_FAILURE(rc))
1118	return rc;
1119
1120	/* MSI-X info */
1121	rc = SSMR3PutU8(pSSM, pDev->Int.s.u8MsixCapOffset);
1122	if (RT_FAILURE(rc))
1123	return rc;
1124	rc = SSMR3PutU8(pSSM, pDev->Int.s.u8MsixCapSize);
1125	if (RT_FAILURE(rc))
1126	return rc;
1127	/* Save MSI-X page state */
1128	if (pDev->Int.s.u8MsixCapOffset != 0)
1129	{
1130	Assert(pDev->Int.s.pMsixPageR3 != NULL);
1131	SSMR3PutMem(pSSM, pDev->Int.s.pMsixPageR3, 0x1000);
1132	if (RT_FAILURE(rc))
1133	return rc;
1134	}
1135	}
1136	}
1137	return SSMR3PutU32(pSSM, UINT32_MAX); /* terminator */
1138	}
1139
1140	static DECLCALLBACK(int) ich9pciR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
1141	{
1142	PICH9PCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
1143
1144	/*
1145	* Bus state data.
1146	*/
1147	SSMR3PutU32(pSSM, pThis->uConfigReg);
1148
1149	/*
1150	* Save IRQ states.
1151	*/
1152	for (int i = 0; i < PCI_APIC_IRQ_PINS; i++)
1153	SSMR3PutU32(pSSM, pThis->uaPciApicIrqLevels[i]);
1154
1155	SSMR3PutU32(pSSM, UINT32_MAX); /* separator */
1156
1157	return ich9pciR3CommonSaveExec(&pThis->aPciBus, pSSM);
1158	}
1159
1160
1161	static DECLCALLBACK(int) ich9pcibridgeR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
1162	{
1163	PICH9PCIBUS pThis = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
1164	return ich9pciR3CommonSaveExec(pThis, pSSM);
1165	}
1166
1167
1168	static DECLCALLBACK(void) ich9pcibridgeConfigWrite(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice, uint32_t u32Address, uint32_t u32Value, unsigned cb)
1169	{
1170	PICH9PCIBUS pBus = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
1171
1172	LogFlowFunc((": pDevIns=%p iBus=%d iDevice=%d u32Address=%u u32Value=%u cb=%d\n", pDevIns, iBus, iDevice, u32Address, u32Value, cb));
1173
1174	/* If the current bus is not the target bus search for the bus which contains the device. */
1175	if (iBus != PCIDevGetByte(&pBus->aPciDev, VBOX_PCI_SECONDARY_BUS))
1176	{
1177	PPCIDEVICE pBridgeDevice = ich9pciFindBridge(pBus, iBus);
1178	if (pBridgeDevice)
1179	{
1180	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigWrite);
1181	pBridgeDevice->Int.s.pfnBridgeConfigWrite(pBridgeDevice->pDevIns, iBus, iDevice, u32Address, u32Value, cb);
1182	}
1183	}
1184	else
1185	{
1186	/* This is the target bus, pass the write to the device. */
1187	PPCIDEVICE pPciDev = pBus->apDevices[iDevice];
1188	if (pPciDev)
1189	{
1190	Log(("%s: %s: addr=%02x val=%08x len=%d\n", __FUNCTION__, pPciDev->name, u32Address, u32Value, cb));
1191	pPciDev->Int.s.pfnConfigWrite(pPciDev, u32Address, u32Value, cb);
1192	}
1193	}
1194	}
1195
1196	static DECLCALLBACK(uint32_t) ich9pcibridgeConfigRead(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice, uint32_t u32Address, unsigned cb)
1197	{
1198	PICH9PCIBUS pBus = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
1199	uint32_t u32Value;
1200
1201	LogFlowFunc((": pDevIns=%p iBus=%d iDevice=%d u32Address=%u cb=%d\n", pDevIns, iBus, iDevice, u32Address, cb));
1202
1203	/* If the current bus is not the target bus search for the bus which contains the device. */
1204	if (iBus != PCIDevGetByte(&pBus->aPciDev, VBOX_PCI_SECONDARY_BUS))
1205	{
1206	PPCIDEVICE pBridgeDevice = ich9pciFindBridge(pBus, iBus);
1207	if (pBridgeDevice)
1208	{
1209	AssertPtr( pBridgeDevice->Int.s.pfnBridgeConfigRead);
1210	u32Value = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->pDevIns, iBus, iDevice, u32Address, cb);
1211	}
1212	else
1213	ich9pciNoMem(&u32Value, 4);
1214	}
1215	else
1216	{
1217	/* This is the target bus, pass the read to the device. */
1218	PPCIDEVICE pPciDev = pBus->apDevices[iDevice];
1219	if (pPciDev)
1220	{
1221	u32Value = pPciDev->Int.s.pfnConfigRead(pPciDev, u32Address, cb);
1222	Log(("%s: %s: u32Address=%02x u32Value=%08x cb=%d\n", __FUNCTION__, pPciDev->name, u32Address, u32Value, cb));
1223	}
1224	else
1225	ich9pciNoMem(&u32Value, 4);
1226	}
1227
1228	return u32Value;
1229	}
1230
1231
1232	/**
1233	* Common routine for restoring the config registers of a PCI device.
1234	*
1235	* @param pDev The PCI device.
1236	* @param pbSrcConfig The configuration register values to be loaded.
1237	* @param fIsBridge Whether this is a bridge device or not.
1238	*/
1239	static void pciR3CommonRestoreConfig(PPCIDEVICE pDev, uint8_t const *pbSrcConfig, bool fIsBridge)
1240	{
1241	/*
1242	* This table defines the fields for normal devices and bridge devices, and
1243	* the order in which they need to be restored.
1244	*/
1245	static const struct PciField
1246	{
1247	uint8_t off;
1248	uint8_t cb;
1249	uint8_t fWritable;
1250	uint8_t fBridge;
1251	const char *pszName;
1252	} s_aFields[] =
1253	{
1254	/* off,cb,fW,fB, pszName */
1255	{ 0x00, 2, 0, 3, "VENDOR_ID" },
1256	{ 0x02, 2, 0, 3, "DEVICE_ID" },
1257	{ 0x06, 2, 1, 3, "STATUS" },
1258	{ 0x08, 1, 0, 3, "REVISION_ID" },
1259	{ 0x09, 1, 0, 3, "CLASS_PROG" },
1260	{ 0x0a, 1, 0, 3, "CLASS_SUB" },
1261	{ 0x0b, 1, 0, 3, "CLASS_BASE" },
1262	{ 0x0c, 1, 1, 3, "CACHE_LINE_SIZE" },
1263	{ 0x0d, 1, 1, 3, "LATENCY_TIMER" },
1264	{ 0x0e, 1, 0, 3, "HEADER_TYPE" },
1265	{ 0x0f, 1, 1, 3, "BIST" },
1266	{ 0x10, 4, 1, 3, "BASE_ADDRESS_0" },
1267	{ 0x14, 4, 1, 3, "BASE_ADDRESS_1" },
1268	{ 0x18, 4, 1, 1, "BASE_ADDRESS_2" },
1269	{ 0x18, 1, 1, 2, "PRIMARY_BUS" }, // fWritable = ??
1270	{ 0x19, 1, 1, 2, "SECONDARY_BUS" }, // fWritable = ??
1271	{ 0x1a, 1, 1, 2, "SUBORDINATE_BUS" }, // fWritable = ??
1272	{ 0x1b, 1, 1, 2, "SEC_LATENCY_TIMER" }, // fWritable = ??
1273	{ 0x1c, 4, 1, 1, "BASE_ADDRESS_3" },
1274	{ 0x1c, 1, 1, 2, "IO_BASE" }, // fWritable = ??
1275	{ 0x1d, 1, 1, 2, "IO_LIMIT" }, // fWritable = ??
1276	{ 0x1e, 2, 1, 2, "SEC_STATUS" }, // fWritable = ??
1277	{ 0x20, 4, 1, 1, "BASE_ADDRESS_4" },
1278	{ 0x20, 2, 1, 2, "MEMORY_BASE" }, // fWritable = ??
1279	{ 0x22, 2, 1, 2, "MEMORY_LIMIT" }, // fWritable = ??
1280	{ 0x24, 4, 1, 1, "BASE_ADDRESS_5" },
1281	{ 0x24, 2, 1, 2, "PREF_MEMORY_BASE" }, // fWritable = ??
1282	{ 0x26, 2, 1, 2, "PREF_MEMORY_LIMIT" }, // fWritable = ??
1283	{ 0x28, 4, 1, 1, "CARDBUS_CIS" }, // fWritable = ??
1284	{ 0x28, 4, 1, 2, "PREF_BASE_UPPER32" }, // fWritable = ??
1285	{ 0x2c, 2, 0, 1, "SUBSYSTEM_VENDOR_ID" },// fWritable = !?
1286	{ 0x2c, 4, 1, 2, "PREF_LIMIT_UPPER32" },// fWritable = ??
1287	{ 0x2e, 2, 0, 1, "SUBSYSTEM_ID" }, // fWritable = !?
1288	{ 0x30, 4, 1, 1, "ROM_ADDRESS" }, // fWritable = ?!
1289	{ 0x30, 2, 1, 2, "IO_BASE_UPPER16" }, // fWritable = ?!
1290	{ 0x32, 2, 1, 2, "IO_LIMIT_UPPER16" }, // fWritable = ?!
1291	{ 0x34, 4, 0, 3, "CAPABILITY_LIST" }, // fWritable = !? cb=!?
1292	{ 0x38, 4, 1, 1, "RESERVED_38" }, // ???
1293	{ 0x38, 4, 1, 2, "ROM_ADDRESS_BR" }, // fWritable = !? cb=!? fBridge=!?
1294	{ 0x3c, 1, 1, 3, "INTERRUPT_LINE" }, // fBridge=??
1295	{ 0x3d, 1, 0, 3, "INTERRUPT_PIN" }, // fBridge=??
1296	{ 0x3e, 1, 0, 1, "MIN_GNT" },
1297	{ 0x3e, 2, 1, 2, "BRIDGE_CONTROL" }, // fWritable = !?
1298	{ 0x3f, 1, 0, 1, "MAX_LAT" },
1299	/* The COMMAND register must come last as it requires the ADDRESS
1300	registers to be restored before we pretent to change it from 0 to
1301	whatever value the guest assigned it. */
1302	{ 0x04, 2, 1, 3, "COMMAND" },
1303	};
1304
1305	#ifdef RT_STRICT
1306	/* Check that we've got full register coverage. */
1307	uint32_t bmDevice[0x40 / 32];
1308	uint32_t bmBridge[0x40 / 32];
1309	RT_ZERO(bmDevice);
1310	RT_ZERO(bmBridge);
1311	for (uint32_t i = 0; i < RT_ELEMENTS(s_aFields); i++)
1312	{
1313	uint8_t off = s_aFields[i].off;
1314	uint8_t cb = s_aFields[i].cb;
1315	uint8_t f = s_aFields[i].fBridge;
1316	while (cb-- > 0)
1317	{
1318	if (f & 1) AssertMsg(!ASMBitTest(bmDevice, off), ("%#x\n", off));
1319	if (f & 2) AssertMsg(!ASMBitTest(bmBridge, off), ("%#x\n", off));
1320	if (f & 1) ASMBitSet(bmDevice, off);
1321	if (f & 2) ASMBitSet(bmBridge, off);
1322	off++;
1323	}
1324	}
1325	for (uint32_t off = 0; off < 0x40; off++)
1326	{
1327	AssertMsg(ASMBitTest(bmDevice, off), ("%#x\n", off));
1328	AssertMsg(ASMBitTest(bmBridge, off), ("%#x\n", off));
1329	}
1330	#endif
1331
1332	/*
1333	* Loop thru the fields covering the 64 bytes of standard registers.
1334	*/
1335	uint8_t const fBridge = fIsBridge ? 2 : 1;
1336	Assert(!pciDevIsPassthrough(pDev));
1337	uint8_t *pbDstConfig = &pDev->config[0];
1338
1339	for (uint32_t i = 0; i < RT_ELEMENTS(s_aFields); i++)
1340	if (s_aFields[i].fBridge & fBridge)
1341	{
1342	uint8_t const off = s_aFields[i].off;
1343	uint8_t const cb = s_aFields[i].cb;
1344	uint32_t u32Src;
1345	uint32_t u32Dst;
1346	switch (cb)
1347	{
1348	case 1:
1349	u32Src = pbSrcConfig[off];
1350	u32Dst = pbDstConfig[off];
1351	break;
1352	case 2:
1353	u32Src = (uint16_t const )&pbSrcConfig[off];
1354	u32Dst = (uint16_t const )&pbDstConfig[off];
1355	break;
1356	case 4:
1357	u32Src = (uint32_t const )&pbSrcConfig[off];
1358	u32Dst = (uint32_t const )&pbDstConfig[off];
1359	break;
1360	default:
1361	AssertFailed();
1362	continue;
1363	}
1364
1365	if ( u32Src != u32Dst
1366	\|\| off == VBOX_PCI_COMMAND)
1367	{
1368	if (u32Src != u32Dst)
1369	{
1370	if (!s_aFields[i].fWritable)
1371	LogRel(("PCI: %8s/%u: %2u-bit field %s: %x -> %x - !READ ONLY!\n",
1372	pDev->name, pDev->pDevIns->iInstance, cb*8, s_aFields[i].pszName, u32Dst, u32Src));
1373	else
1374	LogRel(("PCI: %8s/%u: %2u-bit field %s: %x -> %x\n",
1375	pDev->name, pDev->pDevIns->iInstance, cb*8, s_aFields[i].pszName, u32Dst, u32Src));
1376	}
1377	if (off == VBOX_PCI_COMMAND)
1378	PCIDevSetCommand(pDev, 0); /* For remapping, see ich9pciR3CommonLoadExec. */
1379	pDev->Int.s.pfnConfigWrite(pDev, off, u32Src, cb);
1380	}
1381	}
1382
1383	/*
1384	* The device dependent registers.
1385	*
1386	* We will not use ConfigWrite here as we have no clue about the size
1387	* of the registers, so the device is responsible for correctly
1388	* restoring functionality governed by these registers.
1389	*/
1390	for (uint32_t off = 0x40; off < sizeof(pDev->config); off++)
1391	if (pbDstConfig[off] != pbSrcConfig[off])
1392	{
1393	LogRel(("PCI: %8s/%u: register %02x: %02x -> %02x\n",
1394	pDev->name, pDev->pDevIns->iInstance, off, pbDstConfig[off], pbSrcConfig[off])); /** @todo make this Log() later. */
1395	pbDstConfig[off] = pbSrcConfig[off];
1396	}
1397	}
1398
1399	/**
1400	* Common worker for ich9pciR3LoadExec and ich9pcibridgeR3LoadExec.
1401	*
1402	* @returns VBox status code.
1403	* @param pBus The bus which data is being loaded.
1404	* @param pSSM The saved state handle.
1405	* @param uVersion The data version.
1406	* @param uPass The pass.
1407	*/
1408	static DECLCALLBACK(int) ich9pciR3CommonLoadExec(PICH9PCIBUS pBus, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1409	{
1410	uint32_t u32;
1411	uint32_t i;
1412	int rc;
1413
1414	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
1415	if (uVersion != VBOX_ICH9PCI_SAVED_STATE_VERSION_CURRENT)
1416	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1417
1418	/*
1419	* Iterate thru all the devices and write 0 to the COMMAND register so
1420	* that all the memory is unmapped before we start restoring the saved
1421	* mapping locations.
1422	*
1423	* The register value is restored afterwards so we can do proper
1424	* LogRels in pciR3CommonRestoreConfig.
1425	*/
1426	for (i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
1427	{
1428	PPCIDEVICE pDev = pBus->apDevices[i];
1429	if (pDev)
1430	{
1431	uint16_t u16 = PCIDevGetCommand(pDev);
1432	pDev->Int.s.pfnConfigWrite(pDev, VBOX_PCI_COMMAND, 0, 2);
1433	PCIDevSetCommand(pDev, u16);
1434	Assert(PCIDevGetCommand(pDev) == u16);
1435	}
1436	}
1437
1438	void *pvMsixPage = RTMemTmpAllocZ(0x1000);
1439	AssertReturn(pvMsixPage, VERR_NO_TMP_MEMORY);
1440
1441	/*
1442	* Iterate all the devices.
1443	*/
1444	for (i = 0;; i++)
1445	{
1446	PPCIDEVICE pDev;
1447	PCIDEVICE DevTmp;
1448
1449	/* index / terminator */
1450	rc = SSMR3GetU32(pSSM, &u32);
1451	if (RT_FAILURE(rc))
1452	break;
1453	if (u32 == (uint32_t)~0)
1454	break;
1455	AssertMsgBreak(u32 < RT_ELEMENTS(pBus->apDevices) && u32 >= i, ("u32=%#x i=%#x\n", u32, i));
1456
1457	/* skip forward to the device checking that no new devices are present. */
1458	for (; i < u32; i++)
1459	{
1460	pDev = pBus->apDevices[i];
1461	if (pDev)
1462	{
1463	LogRel(("PCI: New device in slot %#x, %s (vendor=%#06x device=%#06x)\n", i, pDev->name,
1464	PCIDevGetVendorId(pDev), PCIDevGetDeviceId(pDev)));
1465	if (SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT)
1466	{
1467	rc = SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("New device in slot %#x, %s (vendor=%#06x device=%#06x)"),
1468	i, pDev->name, PCIDevGetVendorId(pDev), PCIDevGetDeviceId(pDev));
1469	break;
1470	}
1471	}
1472	}
1473	if (RT_FAILURE(rc))
1474	break;
1475
1476	/* get the data */
1477	DevTmp.Int.s.fFlags = 0;
1478	DevTmp.Int.s.u8MsiCapOffset = 0;
1479	DevTmp.Int.s.u8MsiCapSize = 0;
1480	DevTmp.Int.s.u8MsixCapOffset = 0;
1481	DevTmp.Int.s.u8MsixCapSize = 0;
1482	DevTmp.Int.s.uIrqPinState = ~0; /* Invalid value in case we have an older saved state to force a state change in pciSetIrq. */
1483	SSMR3GetMem(pSSM, DevTmp.config, sizeof(DevTmp.config));
1484
1485	SSMR3GetU32(pSSM, &DevTmp.Int.s.fFlags);
1486	SSMR3GetS32(pSSM, &DevTmp.Int.s.uIrqPinState);
1487	SSMR3GetU8(pSSM, &DevTmp.Int.s.u8MsiCapOffset);
1488	SSMR3GetU8(pSSM, &DevTmp.Int.s.u8MsiCapSize);
1489	SSMR3GetU8(pSSM, &DevTmp.Int.s.u8MsixCapOffset);
1490	rc = SSMR3GetU8(pSSM, &DevTmp.Int.s.u8MsixCapSize);
1491	if (RT_FAILURE(rc))
1492	break;
1493
1494	/* Load MSI-X page state */
1495	if (DevTmp.Int.s.u8MsixCapOffset != 0)
1496	{
1497	Assert(pvMsixPage != NULL);
1498	rc = SSMR3GetMem(pSSM, pvMsixPage, 0x1000);
1499	if (RT_FAILURE(rc))
1500	break;
1501	}
1502
1503	/* check that it's still around. */
1504	pDev = pBus->apDevices[i];
1505	if (!pDev)
1506	{
1507	LogRel(("PCI: Device in slot %#x has been removed! vendor=%#06x device=%#06x\n", i,
1508	PCIDevGetVendorId(&DevTmp), PCIDevGetDeviceId(&DevTmp)));
1509	if (SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT)
1510	{
1511	rc = SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Device in slot %#x has been removed! vendor=%#06x device=%#06x"),
1512	i, PCIDevGetVendorId(&DevTmp), PCIDevGetDeviceId(&DevTmp));
1513	break;
1514	}
1515	continue;
1516	}
1517
1518	/* match the vendor id assuming that this will never be changed. */
1519	if (PCIDevGetVendorId(&DevTmp) != PCIDevGetVendorId(pDev))
1520	{
1521	rc = SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Device in slot %#x (%s) vendor id mismatch! saved=%.4Rhxs current=%.4Rhxs"),
1522	i, pDev->name, PCIDevGetVendorId(&DevTmp), PCIDevGetVendorId(pDev));
1523	break;
1524	}
1525
1526	/* commit the loaded device config. */
1527	Assert(!pciDevIsPassthrough(pDev));
1528	pciR3CommonRestoreConfig(pDev, &DevTmp.config[0], false ); /** @todo fix bridge fun! */
1529
1530	pDev->Int.s.uIrqPinState = DevTmp.Int.s.uIrqPinState;
1531	pDev->Int.s.u8MsiCapOffset = DevTmp.Int.s.u8MsiCapOffset;
1532	pDev->Int.s.u8MsiCapSize = DevTmp.Int.s.u8MsiCapSize;
1533	pDev->Int.s.u8MsixCapOffset = DevTmp.Int.s.u8MsixCapOffset;
1534	pDev->Int.s.u8MsixCapSize = DevTmp.Int.s.u8MsixCapSize;
1535	if (DevTmp.Int.s.u8MsixCapSize != 0)
1536	{
1537	Assert(pDev->Int.s.pMsixPageR3 != NULL);
1538	memcpy(pDev->Int.s.pMsixPageR3, pvMsixPage, 0x1000);
1539	}
1540	}
1541
1542	RTMemTmpFree(pvMsixPage);
1543
1544	return rc;
1545	}
1546
1547	static DECLCALLBACK(int) ich9pciR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1548	{
1549	PICH9PCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
1550	PICH9PCIBUS pBus = &pThis->aPciBus;
1551	uint32_t u32;
1552	int rc;
1553
1554	/* We ignore this version as there's no saved state with it anyway */
1555	if (uVersion == VBOX_ICH9PCI_SAVED_STATE_VERSION_NOMSI)
1556	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1557	if (uVersion > VBOX_ICH9PCI_SAVED_STATE_VERSION_MSI)
1558	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1559
1560	/*
1561	* Bus state data.
1562	*/
1563	SSMR3GetU32(pSSM, &pThis->uConfigReg);
1564
1565	/*
1566	* Load IRQ states.
1567	*/
1568	for (int i = 0; i < PCI_APIC_IRQ_PINS; i++)
1569	SSMR3GetU32(pSSM, (uint32_t*)&pThis->uaPciApicIrqLevels[i]);
1570
1571	/* separator */
1572	rc = SSMR3GetU32(pSSM, &u32);
1573	if (RT_FAILURE(rc))
1574	return rc;
1575	if (u32 != (uint32_t)~0)
1576	AssertMsgFailedReturn(("u32=%#x\n", u32), rc);
1577
1578	return ich9pciR3CommonLoadExec(pBus, pSSM, uVersion, uPass);
1579	}
1580
1581	static DECLCALLBACK(int) ich9pcibridgeR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1582	{
1583	PICH9PCIBUS pThis = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
1584	if (uVersion > VBOX_ICH9PCI_SAVED_STATE_VERSION_MSI)
1585	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1586	return ich9pciR3CommonLoadExec(pThis, pSSM, uVersion, uPass);
1587	}
1588
1589
1590	/*
1591	* Perform imeediate read of configuration space register.
1592	* Cannot be rescheduled, as already in R3.
1593	*/
1594	static uint32_t ich9pciConfigRead(PICH9PCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t len)
1595	{
1596	PciAddress aPciAddr;
1597	aPciAddr.iBus = uBus;
1598	aPciAddr.iDeviceFunc = uDevFn;
1599	aPciAddr.iRegister = addr;
1600
1601	uint32_t u32Val;
1602	int rc = ich9pciDataReadAddr(pGlobals, &aPciAddr, len, &u32Val, VERR_INTERNAL_ERROR);
1603	AssertRC(rc);
1604
1605	return u32Val;
1606	}
1607
1608
1609	/*
1610	* Perform imeediate write to configuration space register.
1611	* Cannot be rescheduled, as already in R3.
1612	*/
1613	static void ich9pciConfigWrite(PICH9PCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t val, uint32_t len)
1614	{
1615	PciAddress aPciAddr;
1616	aPciAddr.iBus = uBus;
1617	aPciAddr.iDeviceFunc = uDevFn;
1618	aPciAddr.iRegister = addr;
1619
1620	int rc = ich9pciDataWriteAddr(pGlobals, &aPciAddr, val, len, VERR_INTERNAL_ERROR);
1621	AssertRC(rc);
1622	}
1623
1624
1625	static void ich9pciSetRegionAddress(PICH9PCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, int iRegion, uint64_t addr)
1626	{
1627	uint32_t uReg = ich9pciGetRegionReg(iRegion);
1628
1629	/* Read memory type first. */
1630	uint8_t uResourceType = ich9pciConfigRead(pGlobals, uBus, uDevFn, uReg, 1);
1631	bool f64Bit = (uResourceType & ((uint8_t)(PCI_ADDRESS_SPACE_BAR64 \| PCI_ADDRESS_SPACE_IO)))
1632	== PCI_ADDRESS_SPACE_BAR64;
1633
1634	Log(("Set region address: %02x:%02x.%d region %d address=%RX64%s\n",
1635	uBus, uDevFn >> 3, uDevFn & 7, iRegion, addr, f64Bit ? " (64-bit)" : ""));
1636
1637	/* Write address of the device. */
1638	ich9pciConfigWrite(pGlobals, uBus, uDevFn, uReg, (uint32_t)addr, 4);
1639	if (f64Bit)
1640	ich9pciConfigWrite(pGlobals, uBus, uDevFn, uReg + 4, (uint32_t)(addr >> 32), 4);
1641	}
1642
1643
1644	static void ich9pciBiosInitBridge(PICH9PCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn)
1645	{
1646	Log(("BIOS init bridge: %02x::%02x.%d\n", uBus, uDevFn >> 3, uDevFn & 7));
1647
1648	/*
1649	* The I/O range for the bridge must be aligned to a 4KB boundary.
1650	* This does not change anything really as the access to the device is not going
1651	* through the bridge but we want to be compliant to the spec.
1652	*/
1653	if ((pGlobals->uPciBiosIo % 4096) != 0)
1654	{
1655	pGlobals->uPciBiosIo = RT_ALIGN_32(pGlobals->uPciBiosIo, 4*1024);
1656	Log(("%s: Aligned I/O start address. New address %#x\n", __FUNCTION__, pGlobals->uPciBiosIo));
1657	}
1658	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_IO_BASE, (pGlobals->uPciBiosIo >> 8) & 0xf0, 1);
1659
1660	/* The MMIO range for the bridge must be aligned to a 1MB boundary. */
1661	if ((pGlobals->uPciBiosMmio % (1024 * 1024)) != 0)
1662	{
1663	pGlobals->uPciBiosMmio = RT_ALIGN_32(pGlobals->uPciBiosMmio, 1024*1024);
1664	Log(("%s: Aligned MMIO start address. New address %#x\n", __FUNCTION__, pGlobals->uPciBiosMmio));
1665	}
1666	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_MEMORY_BASE, (pGlobals->uPciBiosMmio >> 16) & UINT32_C(0xffff0), 2);
1667
1668	/* Save values to compare later to. */
1669	uint32_t u32IoAddressBase = pGlobals->uPciBiosIo;
1670	uint32_t u32MMIOAddressBase = pGlobals->uPciBiosMmio;
1671	uint8_t uBridgeBus = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_SECONDARY_BUS, 1);
1672
1673	/* Init devices behind the bridge and possibly other bridges as well. */
1674	for (int iDev = 0; iDev <= 255; iDev++)
1675	ich9pciBiosInitDevice(pGlobals, uBridgeBus, iDev);
1676
1677	/*
1678	* Set I/O limit register. If there is no device with I/O space behind the bridge
1679	* we set a lower value than in the base register.
1680	* The result with a real bridge is that no I/O transactions are passed to the secondary
1681	* interface. Again this doesn't really matter here but we want to be compliant to the spec.
1682	*/
1683	if ((u32IoAddressBase != pGlobals->uPciBiosIo) && ((pGlobals->uPciBiosIo % 4096) != 0))
1684	{
1685	/* The upper boundary must be one byte less than a 4KB boundary. */
1686	pGlobals->uPciBiosIo = RT_ALIGN_32(pGlobals->uPciBiosIo, 4*1024);
1687	}
1688
1689	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_IO_LIMIT, ((pGlobals->uPciBiosIo >> 8) & 0xf0) - 1, 1);
1690
1691	/* Same with the MMIO limit register but with 1MB boundary here. */
1692	if ((u32MMIOAddressBase != pGlobals->uPciBiosMmio) && ((pGlobals->uPciBiosMmio % (1024 * 1024)) != 0))
1693	{
1694	/* The upper boundary must be one byte less than a 1MB boundary. */
1695	pGlobals->uPciBiosMmio = RT_ALIGN_32(pGlobals->uPciBiosMmio, 1024*1024);
1696	}
1697	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_MEMORY_LIMIT, ((pGlobals->uPciBiosMmio >> 16) & UINT32_C(0xfff0)) - 1, 2);
1698
1699	/*
1700	* Set the prefetch base and limit registers. We currently have no device with a prefetchable region
1701	* which may be behind a bridge. That's why it is unconditionally disabled here atm by writing a higher value into
1702	* the base register than in the limit register.
1703	*/
1704	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_MEMORY_BASE, 0xfff0, 2);
1705	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_MEMORY_LIMIT, 0x0, 2);
1706	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_BASE_UPPER32, 0x00, 4);
1707	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_LIMIT_UPPER32, 0x00, 4);
1708	}
1709
1710	static void ich9pciBiosInitDevice(PICH9PCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn)
1711	{
1712	uint16_t uDevClass, uVendor, uDevice;
1713	uint8_t uCmd;
1714
1715	uDevClass = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_CLASS_DEVICE, 2);
1716	uVendor = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_VENDOR_ID, 2);
1717	uDevice = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_DEVICE_ID, 2);
1718
1719	/* If device is present */
1720	if (uVendor == 0xffff)
1721	return;
1722
1723	Log(("BIOS init device: %02x:%02x.%d\n", uBus, uDevFn >> 3, uDevFn & 7));
1724
1725	switch (uDevClass)
1726	{
1727	case 0x0101:
1728	/* IDE controller */
1729	ich9pciConfigWrite(pGlobals, uBus, uDevFn, 0x40, 0x8000, 2); /* enable IDE0 */
1730	ich9pciConfigWrite(pGlobals, uBus, uDevFn, 0x42, 0x8000, 2); /* enable IDE1 */
1731	goto default_map;
1732	break;
1733	case 0x0300:
1734	/* VGA controller */
1735
1736	/* NB: Default Bochs VGA LFB address is 0xE0000000. Old guest
1737	* software may break if the framebuffer isn't mapped there.
1738	*/
1739
1740	/*
1741	* Legacy VGA I/O ports are implicitly decoded by a VGA class device. But
1742	* only the framebuffer (i.e., a memory region) is explicitly registered via
1743	* ich9pciSetRegionAddress, so don't forget to enable I/O decoding.
1744	*/
1745	uCmd = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_COMMAND, 1);
1746	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_COMMAND,
1747	uCmd \| PCI_COMMAND_IOACCESS,
1748	1);
1749	goto default_map;
1750	break;
1751	case 0x0604:
1752	/* PCI-to-PCI bridge. */
1753	AssertMsg(pGlobals->uBus < 255, ("Too many bridges on the bus\n"));
1754	ich9pciBiosInitBridge(pGlobals, uBus, uDevFn);
1755	break;
1756	default:
1757	default_map:
1758	{
1759	/* default memory mappings */
1760	bool fActiveMemRegion = false;
1761	bool fActiveIORegion = false;
1762	/*
1763	* We ignore ROM region here.
1764	*/
1765	for (int iRegion = 0; iRegion < (PCI_NUM_REGIONS-1); iRegion++)
1766	{
1767	uint32_t u32Address = ich9pciGetRegionReg(iRegion);
1768
1769	/* Calculate size - we write all 1s into the BAR, and then evaluate which bits
1770	are cleared. */
1771	uint8_t u8ResourceType = ich9pciConfigRead(pGlobals, uBus, uDevFn, u32Address, 1);
1772
1773	bool f64Bit = (u8ResourceType & ((uint8_t)(PCI_ADDRESS_SPACE_BAR64 \| PCI_ADDRESS_SPACE_IO)))
1774	== PCI_ADDRESS_SPACE_BAR64;
1775	bool fIsPio = ((u8ResourceType & PCI_COMMAND_IOACCESS) == PCI_COMMAND_IOACCESS);
1776	uint64_t cbRegSize64 = 0;
1777
1778	if (f64Bit)
1779	{
1780	ich9pciConfigWrite(pGlobals, uBus, uDevFn, u32Address, UINT32_C(0xffffffff), 4);
1781	ich9pciConfigWrite(pGlobals, uBus, uDevFn, u32Address+4, UINT32_C(0xffffffff), 4);
1782	cbRegSize64 = ich9pciConfigRead(pGlobals, uBus, uDevFn, u32Address, 4);
1783	cbRegSize64 \|= ((uint64_t)ich9pciConfigRead(pGlobals, uBus, uDevFn, u32Address+4, 4) << 32);
1784	cbRegSize64 &= ~UINT64_C(0x0f);
1785	cbRegSize64 = (~cbRegSize64) + 1;
1786
1787	/* No 64-bit PIO regions possible. */
1788	#ifndef DEBUG_bird /* EFI triggers this for DevAHCI. */
1789	AssertMsg((u8ResourceType & PCI_COMMAND_IOACCESS) == 0, ("type=%#x rgn=%d\n", u8ResourceType, iRegion));
1790	#endif
1791	}
1792	else
1793	{
1794	uint32_t cbRegSize32;
1795	ich9pciConfigWrite(pGlobals, uBus, uDevFn, u32Address, UINT32_C(0xffffffff), 4);
1796	cbRegSize32 = ich9pciConfigRead(pGlobals, uBus, uDevFn, u32Address, 4);
1797
1798	/* Clear resource information depending on resource type. */
1799	if (fIsPio) /* PIO */
1800	cbRegSize32 &= ~UINT32_C(0x01);
1801	else /* MMIO */
1802	cbRegSize32 &= ~UINT32_C(0x0f);
1803
1804	/*
1805	* Invert all bits and add 1 to get size of the region.
1806	* (From PCI implementation note)
1807	*/
1808	if (fIsPio && (cbRegSize32 & UINT32_C(0xffff0000)) == 0)
1809	cbRegSize32 = (~(cbRegSize32 \| UINT32_C(0xffff0000))) + 1;
1810	else
1811	cbRegSize32 = (~cbRegSize32) + 1;
1812
1813	cbRegSize64 = cbRegSize32;
1814	}
1815	Log2(("%s: Size of region %u for device %d on bus %d is %lld\n", __FUNCTION__, iRegion, uDevFn, uBus, cbRegSize64));
1816
1817	if (cbRegSize64)
1818	{
1819	/* Try 32-bit base first. */
1820	uint32_t* paddr = fIsPio ? &pGlobals->uPciBiosIo : &pGlobals->uPciBiosMmio;
1821	uint64_t uNew = *paddr;
1822	/* Align starting address to region size. */
1823	uNew = (uNew + cbRegSize64 - 1) & ~(cbRegSize64 - 1);
1824	if (fIsPio)
1825	uNew &= UINT32_C(0xffff);
1826	/* Unconditionally exclude I/O-APIC/HPET/ROM. Pessimistic, but better than causing a mess. */
1827	if ( !uNew
1828	\|\| (uNew <= UINT32_C(0xffffffff) && uNew + cbRegSize64 - 1 >= UINT32_C(0xfec00000))
1829	\|\| uNew >= _4G)
1830	{
1831	if (f64Bit)
1832	{
1833	/* Map a 64-bit region above 4GB. */
1834	Assert(!fIsPio);
1835	uNew = pGlobals->uPciBiosMmio64;
1836	/* Align starting address to region size. */
1837	uNew = (uNew + cbRegSize64 - 1) & ~(cbRegSize64 - 1);
1838	LogFunc(("Start address of 64-bit MMIO region %u/%u is %#llx\n", iRegion, iRegion + 1, uNew));
1839	ich9pciSetRegionAddress(pGlobals, uBus, uDevFn, iRegion, uNew);
1840	fActiveMemRegion = true;
1841	pGlobals->uPciBiosMmio64 = uNew + cbRegSize64;
1842	Log2Func(("New 64-bit address is %#llx\n", pGlobals->uPciBiosMmio64));
1843	}
1844	else
1845	{
1846	LogRel(("PCI: no space left for BAR%u of device %u/%u/%u (vendor=%#06x device=%#06x)\n",
1847	iRegion, uBus, uDevFn >> 3, uDevFn & 7, uVendor, uDevice)); /** @todo make this a VM start failure later. */
1848	/* Undo the mapping mess caused by the size probing. */
1849	ich9pciConfigWrite(pGlobals, uBus, uDevFn, u32Address, UINT32_C(0), 4);
1850	}
1851	}
1852	else
1853	{
1854	LogFunc(("Start address of %s region %u is %#x\n", (fIsPio ? "I/O" : "MMIO"), iRegion, uNew));
1855	ich9pciSetRegionAddress(pGlobals, uBus, uDevFn, iRegion, uNew);
1856	if (fIsPio)
1857	fActiveIORegion = true;
1858	else
1859	fActiveMemRegion = true;
1860	*paddr = uNew + cbRegSize64;
1861	Log2Func(("New 32-bit address is %#x\n", *paddr));
1862	}
1863
1864	if (f64Bit)
1865	iRegion++; /* skip next region */
1866	}
1867	}
1868
1869	/* Update the command word appropriately. */
1870	uCmd = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_COMMAND, 2);
1871	if (fActiveMemRegion)
1872	uCmd \|= PCI_COMMAND_MEMACCESS; /* Enable MMIO access. */
1873	if (fActiveIORegion)
1874	uCmd \|= PCI_COMMAND_IOACCESS; /* Enable I/O space access. */
1875	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_COMMAND, uCmd, 2);
1876	break;
1877	}
1878	}
1879
1880	/* map the interrupt */
1881	uint32_t iPin = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_INTERRUPT_PIN, 1);
1882	if (iPin != 0)
1883	{
1884	iPin--;
1885
1886	if (uBus != 0)
1887	{
1888	/* Find bus this device attached to. */
1889	PICH9PCIBUS pBus = &pGlobals->aPciBus;
1890	while (1)
1891	{
1892	PPCIDEVICE pBridge = ich9pciFindBridge(pBus, uBus);
1893	if (!pBridge)
1894	{
1895	Assert(false);
1896	break;
1897	}
1898	if (uBus == PCIDevGetByte(pBridge, VBOX_PCI_SECONDARY_BUS))
1899	{
1900	/* OK, found bus this device attached to. */
1901	break;
1902	}
1903	pBus = PDMINS_2_DATA(pBridge->pDevIns, PICH9PCIBUS);
1904	}
1905
1906	/* We need to go up to the host bus to see which irq pin this
1907	* device will use there. See logic in ich9pcibridgeSetIrq().
1908	*/
1909	while (pBus->iBus != 0)
1910	{
1911	/* Get the pin the device would assert on the bridge. */
1912	iPin = ((pBus->aPciDev.devfn >> 3) + iPin) & 3;
1913	pBus = pBus->aPciDev.Int.s.pBusR3;
1914	};
1915	}
1916
1917	int iIrq = aPciIrqs[ich9pciSlotGetPirq(uBus, uDevFn, iPin)];
1918	Log(("Using pin %d and IRQ %d for device %02x:%02x.%d\n",
1919	iPin, iIrq, uBus, uDevFn>>3, uDevFn&7));
1920	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_INTERRUPT_LINE, iIrq, 1);
1921	}
1922	}
1923
1924	/**
1925	* Initializes bridges registers used for routing.
1926	*
1927	* @returns nothing.
1928	* @param pGlobals Global device instance data used to generate unique bus numbers.
1929	* @param pBus The PCI bus to initialize.
1930	* @param uBusPrimary The primary bus number the bus is connected to.
1931	* @param uBusSecondary The secondary bus number, i.e. the bus number behind the bridge.
1932	*/
1933	static void ich9pciInitBridgeTopology(PICH9PCIGLOBALS pGlobals, PICH9PCIBUS pBus, unsigned uBusPrimary,
1934	unsigned uBusSecondary)
1935	{
1936	PPCIDEVICE pBridgeDev = &pBus->aPciDev;
1937
1938	/* Set only if we are not on the root bus, it has no primary bus attached. */
1939	if (uBusSecondary != 0)
1940	{
1941	PCIDevSetByte(pBridgeDev, VBOX_PCI_PRIMARY_BUS, uBusPrimary);
1942	PCIDevSetByte(pBridgeDev, VBOX_PCI_SECONDARY_BUS, uBusSecondary);
1943	}
1944
1945	for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
1946	{
1947	PPCIDEVICE pBridge = pBus->papBridgesR3[iBridge];
1948	AssertMsg(pBridge && pciDevIsPci2PciBridge(pBridge),
1949	("Device is not a PCI bridge but on the list of PCI bridges\n"));
1950	PICH9PCIBUS pChildBus = PDMINS_2_DATA(pBridge->pDevIns, PICH9PCIBUS);
1951	pGlobals->uBus++;
1952	ich9pciInitBridgeTopology(pGlobals, pChildBus, uBusSecondary, pGlobals->uBus);
1953	}
1954	PCIDevSetByte(pBridgeDev, VBOX_PCI_SUBORDINATE_BUS, pGlobals->uBus);
1955	Log2(("ich9pciInitBridgeTopology: for bus %p: primary=%d secondary=%d subordinate=%d\n",
1956	pBus,
1957	PCIDevGetByte(pBridgeDev, VBOX_PCI_PRIMARY_BUS),
1958	PCIDevGetByte(pBridgeDev, VBOX_PCI_SECONDARY_BUS),
1959	PCIDevGetByte(pBridgeDev, VBOX_PCI_SUBORDINATE_BUS)
1960	));
1961	}
1962
1963
1964	static DECLCALLBACK(int) ich9pciFakePCIBIOS(PPDMDEVINS pDevIns)
1965	{
1966	PICH9PCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
1967	PVM pVM = PDMDevHlpGetVM(pDevIns);
1968	uint32_t const cbBelow4GB = MMR3PhysGetRamSizeBelow4GB(pVM);
1969	uint64_t const cbAbove4GB = MMR3PhysGetRamSizeAbove4GB(pVM);
1970
1971	/*
1972	* Set the start addresses.
1973	*/
1974	pGlobals->uPciBiosIo = 0xd000;
1975	pGlobals->uPciBiosMmio = cbBelow4GB;
1976	pGlobals->uPciBiosMmio64 = cbAbove4GB + _4G;
1977	pGlobals->uBus = 0;
1978
1979	/* NB: Assume that if MMIO range is enabled, it is at the bottom of the memory hole. */
1980	if (pGlobals->u64PciConfigMMioAddress)
1981	{
1982	AssertRelease(pGlobals->u64PciConfigMMioAddress >= cbBelow4GB);
1983	pGlobals->uPciBiosMmio = pGlobals->u64PciConfigMMioAddress + pGlobals->u64PciConfigMMioLength;
1984	}
1985	Log(("cbBelow4GB: %lX, uPciBiosMmio: %lX, cbAbove4GB: %llX\n", cbBelow4GB, pGlobals->uPciBiosMmio, cbAbove4GB));
1986
1987	/*
1988	* Assign bridge topology, for further routing to work.
1989	*/
1990	PICH9PCIBUS pBus = &pGlobals->aPciBus;
1991	ich9pciInitBridgeTopology(pGlobals, pBus, 0, 0);
1992
1993	/*
1994	* Init the devices.
1995	*/
1996	for (int i = 0; i < 256; i++)
1997	ich9pciBiosInitDevice(pGlobals, 0, i);
1998
1999	return VINF_SUCCESS;
2000	}
2001
2002
2003	/*
2004	* Configuration space read callback (PCIDEVICEINT::pfnConfigRead) for
2005	* connected devices.
2006	*/
2007	static DECLCALLBACK(uint32_t) ich9pciConfigReadDev(PCIDevice *aDev, uint32_t u32Address, unsigned len)
2008	{
2009	if ((u32Address + len) > 256 && (u32Address + len) < 4096)
2010	{
2011	LogRel(("PCI: %8s/%u: Read from extended register %d fallen back to generic code\n",
2012	aDev->name, aDev->pDevIns->iInstance, u32Address));
2013	return 0;
2014	}
2015
2016	AssertMsgReturn(u32Address + len <= 256, ("Read after the end of PCI config space\n"),
2017	0);
2018	if ( pciDevIsMsiCapable(aDev)
2019	&& (u32Address >= aDev->Int.s.u8MsiCapOffset)
2020	&& (u32Address < (unsigned)(aDev->Int.s.u8MsiCapOffset + aDev->Int.s.u8MsiCapSize))
2021	)
2022	{
2023	return MsiPciConfigRead(aDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pDevIns), aDev, u32Address, len);
2024	}
2025
2026	if ( pciDevIsMsixCapable(aDev)
2027	&& (u32Address >= aDev->Int.s.u8MsixCapOffset)
2028	&& (u32Address < (unsigned)(aDev->Int.s.u8MsixCapOffset + aDev->Int.s.u8MsixCapSize))
2029	)
2030	{
2031	return MsixPciConfigRead(aDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pDevIns), aDev, u32Address, len);
2032	}
2033
2034	AssertMsgReturn(u32Address + len <= 256, ("Read after end of PCI config space\n"),
2035	0);
2036	switch (len)
2037	{
2038	case 1:
2039	return PCIDevGetByte(aDev, u32Address);
2040	case 2:
2041	return PCIDevGetWord(aDev, u32Address);
2042	case 4:
2043	return PCIDevGetDWord(aDev, u32Address);
2044	default:
2045	Assert(false);
2046	return 0;
2047	}
2048	}
2049
2050
2051	DECLINLINE(void) ich9pciWriteBarByte(PCIDevice *aDev, int iRegion, int iOffset, uint8_t u8Val)
2052	{
2053	PCIIORegion * pRegion = &aDev->Int.s.aIORegions[iRegion];
2054	int64_t iRegionSize = pRegion->size;
2055
2056	Log3(("ich9pciWriteBarByte: region=%d off=%d val=%x size=%d\n",
2057	iRegion, iOffset, u8Val, iRegionSize));
2058
2059	if (iOffset > 3)
2060	Assert((pRegion->type & PCI_ADDRESS_SPACE_BAR64) != 0);
2061
2062	/* Check if we're writing to upper part of 64-bit BAR. */
2063	if (pRegion->type == 0xff)
2064	{
2065	ich9pciWriteBarByte(aDev, iRegion-1, iOffset+4, u8Val);
2066	return;
2067	}
2068
2069	/* Region doesn't exist */
2070	if (iRegionSize == 0)
2071	return;
2072
2073	uint32_t uAddr = ich9pciGetRegionReg(iRegion) + iOffset;
2074	/* Region size must be power of two */
2075	Assert((iRegionSize & (iRegionSize - 1)) == 0);
2076	uint8_t uMask = ((iRegionSize - 1) >> (iOffset*8) ) & 0xff;
2077
2078	if (iOffset == 0)
2079	{
2080	uMask \|= (pRegion->type & PCI_ADDRESS_SPACE_IO) ?
2081	(1 << 2) - 1 /* 2 lowest bits for IO region */ :
2082	(1 << 4) - 1 /* 4 lowest bits for memory region, also ROM enable bit for ROM region */;
2083
2084	}
2085
2086	uint8_t u8Old = PCIDevGetByte(aDev, uAddr) & uMask;
2087	u8Val = (u8Old & uMask) \| (u8Val & ~uMask);
2088
2089	Log3(("ich9pciWriteBarByte: was %x writing %x\n", u8Old, u8Val));
2090
2091	PCIDevSetByte(aDev, uAddr, u8Val);
2092	}
2093
2094
2095	/**
2096	* Configuration space write callback (PCIDEVICEINT::pfnConfigWrite)
2097	* for connected devices.
2098	*
2099	* See paragraph 7.5 of PCI Express specification (p. 349) for
2100	* definition of registers and their writability policy.
2101	*/
2102	static DECLCALLBACK(void) ich9pciConfigWriteDev(PCIDevice *aDev, uint32_t u32Address,
2103	uint32_t val, unsigned len)
2104	{
2105	Assert(len <= 4);
2106
2107	if ((u32Address + len) > 256 && (u32Address + len) < 4096)
2108	{
2109	LogRel(("PCI: %8s/%u: Write to extended register %d fallen back to generic code\n",
2110	aDev->name, aDev->pDevIns->iInstance, u32Address));
2111	return;
2112	}
2113
2114	AssertMsgReturnVoid(u32Address + len <= 256, ("Write after end of PCI config space\n"));
2115
2116	if ( pciDevIsMsiCapable(aDev)
2117	&& (u32Address >= aDev->Int.s.u8MsiCapOffset)
2118	&& (u32Address < (unsigned)(aDev->Int.s.u8MsiCapOffset + aDev->Int.s.u8MsiCapSize))
2119	)
2120	{
2121	MsiPciConfigWrite(aDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pDevIns),
2122	aDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pPciHlp),
2123	aDev, u32Address, val, len);
2124	return;
2125	}
2126
2127	if ( pciDevIsMsixCapable(aDev)
2128	&& (u32Address >= aDev->Int.s.u8MsixCapOffset)
2129	&& (u32Address < (unsigned)(aDev->Int.s.u8MsixCapOffset + aDev->Int.s.u8MsixCapSize))
2130	)
2131	{
2132	MsixPciConfigWrite(aDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pDevIns),
2133	aDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pPciHlp),
2134	aDev, u32Address, val, len);
2135	return;
2136	}
2137
2138	uint32_t addr = u32Address;
2139	bool fUpdateMappings = false;
2140	bool fP2PBridge = false;
2141	/bool fPassthrough = pciDevIsPassthrough(aDev);/
2142	uint8_t u8HeaderType = ich9pciGetByte(aDev, VBOX_PCI_HEADER_TYPE);
2143
2144	for (uint32_t i = 0; i < len; i++)
2145	{
2146	bool fWritable = false;
2147	bool fRom = false;
2148	switch (u8HeaderType)
2149	{
2150	case 0x00: /* normal device */
2151	case 0x80: /* multi-function device */
2152	switch (addr)
2153	{
2154	/* Read-only registers */
2155	case VBOX_PCI_VENDOR_ID: case VBOX_PCI_VENDOR_ID+1:
2156	case VBOX_PCI_DEVICE_ID: case VBOX_PCI_DEVICE_ID+1:
2157	case VBOX_PCI_REVISION_ID:
2158	case VBOX_PCI_CLASS_PROG:
2159	case VBOX_PCI_CLASS_SUB:
2160	case VBOX_PCI_CLASS_BASE:
2161	case VBOX_PCI_HEADER_TYPE:
2162	case VBOX_PCI_SUBSYSTEM_VENDOR_ID: case VBOX_PCI_SUBSYSTEM_VENDOR_ID+1:
2163	case VBOX_PCI_SUBSYSTEM_ID: case VBOX_PCI_SUBSYSTEM_ID+1:
2164	case VBOX_PCI_ROM_ADDRESS: case VBOX_PCI_ROM_ADDRESS+1: case VBOX_PCI_ROM_ADDRESS+2: case VBOX_PCI_ROM_ADDRESS+3:
2165	case VBOX_PCI_CAPABILITY_LIST:
2166	case VBOX_PCI_INTERRUPT_PIN:
2167	fWritable = false;
2168	break;
2169	/* Others can be written */
2170	default:
2171	fWritable = true;
2172	break;
2173	}
2174	break;
2175	case 0x01: /* PCI-PCI bridge */
2176	fP2PBridge = true;
2177	switch (addr)
2178	{
2179	/* Read-only registers */
2180	case VBOX_PCI_VENDOR_ID: case VBOX_PCI_VENDOR_ID+1:
2181	case VBOX_PCI_DEVICE_ID: case VBOX_PCI_DEVICE_ID+1:
2182	case VBOX_PCI_REVISION_ID:
2183	case VBOX_PCI_CLASS_PROG:
2184	case VBOX_PCI_CLASS_SUB:
2185	case VBOX_PCI_CLASS_BASE:
2186	case VBOX_PCI_HEADER_TYPE:
2187	case VBOX_PCI_ROM_ADDRESS_BR: case VBOX_PCI_ROM_ADDRESS_BR+1: case VBOX_PCI_ROM_ADDRESS_BR+2: case VBOX_PCI_ROM_ADDRESS_BR+3:
2188	case VBOX_PCI_INTERRUPT_PIN:
2189	fWritable = false;
2190	break;
2191	default:
2192	fWritable = true;
2193	break;
2194	}
2195	break;
2196	default:
2197	AssertMsgFailed(("Unknown header type %x\n", PCIDevGetHeaderType(aDev)));
2198	fWritable = false;
2199	break;
2200	}
2201
2202	uint8_t u8Val = (uint8_t)val;
2203	switch (addr)
2204	{
2205	case VBOX_PCI_COMMAND: /* Command register, bits 0-7. */
2206	fUpdateMappings = true;
2207	goto default_case;
2208	case VBOX_PCI_COMMAND+1: /* Command register, bits 8-15. */
2209	/* don't change reserved bits (11-15) */
2210	u8Val &= ~UINT32_C(0xf8);
2211	fUpdateMappings = true;
2212	goto default_case;
2213	case VBOX_PCI_STATUS: /* Status register, bits 0-7. */
2214	/* don't change read-only bits => actually all lower bits are read-only */
2215	u8Val &= ~UINT32_C(0xff);
2216	/* status register, low part: clear bits by writing a '1' to the corresponding bit */
2217	aDev->config[addr] &= ~u8Val;
2218	break;
2219	case VBOX_PCI_STATUS+1: /* Status register, bits 8-15. */
2220	/* don't change read-only bits */
2221	u8Val &= ~UINT32_C(0x06);
2222	/* status register, high part: clear bits by writing a '1' to the corresponding bit */
2223	aDev->config[addr] &= ~u8Val;
2224	break;
2225	case VBOX_PCI_ROM_ADDRESS: case VBOX_PCI_ROM_ADDRESS +1: case VBOX_PCI_ROM_ADDRESS +2: case VBOX_PCI_ROM_ADDRESS +3:
2226	fRom = true;
2227	case VBOX_PCI_BASE_ADDRESS_0: case VBOX_PCI_BASE_ADDRESS_0+1: case VBOX_PCI_BASE_ADDRESS_0+2: case VBOX_PCI_BASE_ADDRESS_0+3:
2228	case VBOX_PCI_BASE_ADDRESS_1: case VBOX_PCI_BASE_ADDRESS_1+1: case VBOX_PCI_BASE_ADDRESS_1+2: case VBOX_PCI_BASE_ADDRESS_1+3:
2229	case VBOX_PCI_BASE_ADDRESS_2: case VBOX_PCI_BASE_ADDRESS_2+1: case VBOX_PCI_BASE_ADDRESS_2+2: case VBOX_PCI_BASE_ADDRESS_2+3:
2230	case VBOX_PCI_BASE_ADDRESS_3: case VBOX_PCI_BASE_ADDRESS_3+1: case VBOX_PCI_BASE_ADDRESS_3+2: case VBOX_PCI_BASE_ADDRESS_3+3:
2231	case VBOX_PCI_BASE_ADDRESS_4: case VBOX_PCI_BASE_ADDRESS_4+1: case VBOX_PCI_BASE_ADDRESS_4+2: case VBOX_PCI_BASE_ADDRESS_4+3:
2232	case VBOX_PCI_BASE_ADDRESS_5: case VBOX_PCI_BASE_ADDRESS_5+1: case VBOX_PCI_BASE_ADDRESS_5+2: case VBOX_PCI_BASE_ADDRESS_5+3:
2233	{
2234	/* We check that, as same PCI register numbers as BARs may mean different registers for bridges */
2235	if (fP2PBridge)
2236	goto default_case;
2237	else
2238	{
2239	int iRegion = fRom ? VBOX_PCI_ROM_SLOT : (addr - VBOX_PCI_BASE_ADDRESS_0) >> 2;
2240	int iOffset = addr & 0x3;
2241	ich9pciWriteBarByte(aDev, iRegion, iOffset, u8Val);
2242	fUpdateMappings = true;
2243	}
2244	break;
2245	}
2246	default:
2247	default_case:
2248	if (fWritable)
2249	PCIDevSetByte(aDev, addr, u8Val);
2250	}
2251	addr++;
2252	val >>= 8;
2253	}
2254
2255	if (fUpdateMappings)
2256	/* if the command/base address register is modified, we must modify the mappings */
2257	ich9pciUpdateMappings(aDev);
2258	}
2259
2260	static bool assignPosition(PICH9PCIBUS pBus, PPCIDEVICE pPciDev, const char pszName, int iDevFn, PciAddress aPosition)
2261	{
2262	NOREF(pszName);
2263	aPosition->iBus = 0;
2264	aPosition->iDeviceFunc = iDevFn;
2265	aPosition->iRegister = 0; /* N/A */
2266
2267	/* Explicit slot request */
2268	if (iDevFn >= 0 && iDevFn < (int)RT_ELEMENTS(pBus->apDevices))
2269	return true;
2270
2271	int iStartPos = 0;
2272
2273	/* Otherwise when assigning a slot, we need to make sure all its functions are available */
2274	for (int iPos = iStartPos; iPos < (int)RT_ELEMENTS(pBus->apDevices); iPos += 8)
2275	{
2276	if ( !pBus->apDevices[iPos]
2277	&& !pBus->apDevices[iPos + 1]
2278	&& !pBus->apDevices[iPos + 2]
2279	&& !pBus->apDevices[iPos + 3]
2280	&& !pBus->apDevices[iPos + 4]
2281	&& !pBus->apDevices[iPos + 5]
2282	&& !pBus->apDevices[iPos + 6]
2283	&& !pBus->apDevices[iPos + 7])
2284	{
2285	pciDevClearRequestedDevfunc(pPciDev);
2286	aPosition->iDeviceFunc = iPos;
2287	return true;
2288	}
2289	}
2290
2291	return false;
2292	}
2293
2294	#ifdef SOME_UNUSED_FUNCTION
2295	static bool hasHardAssignedDevsInSlot(PICH9PCIBUS pBus, int iSlot)
2296	{
2297	PCIDevice** aSlot = &pBus->apDevices[iSlot << 3];
2298
2299	return (aSlot[0] && pciDevIsRequestedDevfunc(aSlot[0]))
2300	\|\| (aSlot[1] && pciDevIsRequestedDevfunc(aSlot[1]))
2301	\|\| (aSlot[2] && pciDevIsRequestedDevfunc(aSlot[2]))
2302	\|\| (aSlot[3] && pciDevIsRequestedDevfunc(aSlot[3]))
2303	\|\| (aSlot[4] && pciDevIsRequestedDevfunc(aSlot[4]))
2304	\|\| (aSlot[5] && pciDevIsRequestedDevfunc(aSlot[5]))
2305	\|\| (aSlot[6] && pciDevIsRequestedDevfunc(aSlot[6]))
2306	\|\| (aSlot[7] && pciDevIsRequestedDevfunc(aSlot[7]))
2307	;
2308	}
2309	#endif
2310
2311	static int ich9pciRegisterInternal(PICH9PCIBUS pBus, int iDev, PPCIDEVICE pPciDev, const char *pszName)
2312	{
2313	PciAddress aPosition;
2314	aPosition.iBus = 0;
2315	aPosition.iDeviceFunc = 0;
2316	aPosition.iRegister = 0;
2317
2318	/*
2319	* Find device position
2320	*/
2321	if (!assignPosition(pBus, pPciDev, pszName, iDev, &aPosition))
2322	{
2323	AssertMsgFailed(("Couldn't asssign position!\n"));
2324	return VERR_PDM_TOO_PCI_MANY_DEVICES;
2325	}
2326
2327	AssertMsgReturn(aPosition.iBus == 0,
2328	("Assigning behind the bridge not implemented yet\n"),
2329	VERR_PDM_TOO_PCI_MANY_DEVICES);
2330
2331
2332	iDev = aPosition.iDeviceFunc;
2333	/*
2334	* Check if we can really take this slot, possibly by relocating
2335	* its current habitant, if it wasn't hard assigned too.
2336	*/
2337	if (pciDevIsRequestedDevfunc(pPciDev) &&
2338	pBus->apDevices[iDev] &&
2339	pciDevIsRequestedDevfunc(pBus->apDevices[iDev]))
2340	{
2341	AssertReleaseMsgFailed(("Configuration error:'%s' and '%s' are both configured as device %d\n",
2342	pszName, pBus->apDevices[iDev]->name, iDev));
2343	return VERR_INTERNAL_ERROR;
2344	}
2345
2346	if (pBus->apDevices[iDev])
2347	{
2348	/* if we got here, we shall (and usually can) relocate the device */
2349	bool assigned = assignPosition(pBus, pBus->apDevices[iDev], pBus->apDevices[iDev]->name, -1, &aPosition);
2350	AssertMsgReturn(aPosition.iBus == 0,
2351	("Assigning behind the bridge not implemented yet\n"),
2352	VERR_PDM_TOO_PCI_MANY_DEVICES);
2353	int iRelDev = aPosition.iDeviceFunc;
2354	if (!assigned \|\| iRelDev == iDev)
2355	{
2356	AssertMsgFailed(("Couldn't find free spot!\n"));
2357	return VERR_PDM_TOO_PCI_MANY_DEVICES;
2358	}
2359	/* Copy device function by function to its new position */
2360	for (int i = 0; i < 8; i++)
2361	{
2362	if (!pBus->apDevices[iDev + i])
2363	continue;
2364	Log(("PCI: relocating '%s' from slot %#x to %#x\n", pBus->apDevices[iDev + i]->name, iDev + i, iRelDev + i));
2365	pBus->apDevices[iRelDev + i] = pBus->apDevices[iDev + i];
2366	pBus->apDevices[iRelDev + i]->devfn = iRelDev + i;
2367	pBus->apDevices[iDev + i] = NULL;
2368	}
2369	}
2370
2371	/*
2372	* Fill in device information.
2373	*/
2374	pPciDev->devfn = iDev;
2375	pPciDev->name = pszName;
2376	pPciDev->Int.s.pBusR3 = pBus;
2377	pPciDev->Int.s.pBusR0 = MMHyperR3ToR0(PDMDevHlpGetVM(pBus->CTX_SUFF(pDevIns)), pBus);
2378	pPciDev->Int.s.pBusRC = MMHyperR3ToRC(PDMDevHlpGetVM(pBus->CTX_SUFF(pDevIns)), pBus);
2379	pPciDev->Int.s.pfnConfigRead = ich9pciConfigReadDev;
2380	pPciDev->Int.s.pfnConfigWrite = ich9pciConfigWriteDev;
2381	pBus->apDevices[iDev] = pPciDev;
2382	if (pciDevIsPci2PciBridge(pPciDev))
2383	{
2384	AssertMsg(pBus->cBridges < RT_ELEMENTS(pBus->apDevices), ("Number of bridges exceeds the number of possible devices on the bus\n"));
2385	AssertMsg(pPciDev->Int.s.pfnBridgeConfigRead && pPciDev->Int.s.pfnBridgeConfigWrite,
2386	("device is a bridge but does not implement read/write functions\n"));
2387	Log2(("Setting bridge %d on bus %p\n", pBus->cBridges, pBus));
2388	pBus->papBridgesR3[pBus->cBridges] = pPciDev;
2389	pBus->cBridges++;
2390	}
2391
2392	Log(("PCI: Registered device %d function %d on bus %d (%#x) '%s'.\n",
2393	iDev >> 3, iDev & 7, pBus->iBus, 0x80000000 \| (iDev << 8), pszName));
2394
2395	return VINF_SUCCESS;
2396	}
2397
2398	static void printIndent(PCDBGFINFOHLP pHlp, int iIndent)
2399	{
2400	for (int i = 0; i < iIndent; i++)
2401	{
2402	pHlp->pfnPrintf(pHlp, " ");
2403	}
2404	}
2405
2406	static void ich9pciBusInfo(PICH9PCIBUS pBus, PCDBGFINFOHLP pHlp, int iIndent, bool fRegisters)
2407	{
2408	for (uint32_t iDev = 0; iDev < RT_ELEMENTS(pBus->apDevices); iDev++)
2409	{
2410	PPCIDEVICE pPciDev = pBus->apDevices[iDev];
2411	if (pPciDev != NULL)
2412	{
2413	printIndent(pHlp, iIndent);
2414
2415	/*
2416	* For passthrough devices MSI/MSI-X mostly reflects the way interrupts delivered to the guest,
2417	* as host driver handles real devices interrupts.
2418	*/
2419	pHlp->pfnPrintf(pHlp, "%02x:%02x:%02x %s%s: %04x-%04x",
2420	pBus->iBus, (iDev >> 3) & 0xff, iDev & 0x7,
2421	pPciDev->name,
2422	pciDevIsPassthrough(pPciDev) ? " (PASSTHROUGH)" : "",
2423	ich9pciGetWord(pPciDev, VBOX_PCI_VENDOR_ID), ich9pciGetWord(pPciDev, VBOX_PCI_DEVICE_ID)
2424	);
2425	if (ich9pciGetByte(pPciDev, VBOX_PCI_INTERRUPT_PIN) != 0)
2426	{
2427	pHlp->pfnPrintf(pHlp, " IRQ%d", ich9pciGetByte(pPciDev, VBOX_PCI_INTERRUPT_LINE));
2428	pHlp->pfnPrintf(pHlp, " (INTA#->IRQ%d)", 0x10 + ich9pciSlot2ApicIrq(iDev >> 3, 0));
2429	}
2430	pHlp->pfnPrintf(pHlp, "\n");
2431
2432	if (pciDevIsMsiCapable(pPciDev) \|\| pciDevIsMsixCapable(pPciDev))
2433	{
2434	printIndent(pHlp, iIndent + 2);
2435
2436	if (pciDevIsMsiCapable(pPciDev))
2437	pHlp->pfnPrintf(pHlp, "MSI:%s ", MsiIsEnabled(pPciDev) ? "on" : "off");
2438
2439	if (pciDevIsMsixCapable(pPciDev))
2440	pHlp->pfnPrintf(pHlp, "MSI-X:%s ", MsixIsEnabled(pPciDev) ? "on" : "off");
2441
2442	pHlp->pfnPrintf(pHlp, "\n");
2443	}
2444
2445	uint16_t iCmd = ich9pciGetWord(pPciDev, VBOX_PCI_COMMAND);
2446	if ((iCmd & (VBOX_PCI_COMMAND_IO \| VBOX_PCI_COMMAND_MEMORY)) != 0)
2447	{
2448	for (int iRegion = 0; iRegion < PCI_NUM_REGIONS; iRegion++)
2449	{
2450	PCIIORegion* pRegion = &pPciDev->Int.s.aIORegions[iRegion];
2451	uint64_t iRegionSize = pRegion->size;
2452
2453	if (iRegionSize == 0)
2454	continue;
2455
2456	uint32_t u32Addr = ich9pciGetDWord(pPciDev, ich9pciGetRegionReg(iRegion));
2457	const char * pszDesc;
2458	char szDescBuf[128];
2459
2460	bool f64Bit = (pRegion->type & ((uint8_t)(PCI_ADDRESS_SPACE_BAR64 \| PCI_ADDRESS_SPACE_IO)))
2461	== PCI_ADDRESS_SPACE_BAR64;
2462	if (pRegion->type & PCI_ADDRESS_SPACE_IO)
2463	{
2464	pszDesc = "IO";
2465	u32Addr &= ~0x3;
2466	}
2467	else
2468	{
2469	RTStrPrintf(szDescBuf, sizeof(szDescBuf), "MMIO%s%s",
2470	f64Bit ? "64" : "32",
2471	(pRegion->type & PCI_ADDRESS_SPACE_MEM_PREFETCH) ? " PREFETCH" : "");
2472	pszDesc = szDescBuf;
2473	u32Addr &= ~0xf;
2474	}
2475
2476	printIndent(pHlp, iIndent + 2);
2477	pHlp->pfnPrintf(pHlp, "%s region #%d: ",pszDesc, iRegion);
2478	if (f64Bit)
2479	{
2480	uint32_t u32High = ich9pciGetDWord(pPciDev, ich9pciGetRegionReg(iRegion+1));
2481	uint64_t u64Addr = RT_MAKE_U64(u32Addr, u32High);
2482	pHlp->pfnPrintf(pHlp, "%RX64..%RX64\n", u64Addr, u64Addr+iRegionSize);
2483	iRegion++;
2484	}
2485	else
2486	pHlp->pfnPrintf(pHlp, "%x..%x\n", u32Addr, u32Addr+iRegionSize);
2487	}
2488	}
2489
2490	printIndent(pHlp, iIndent + 2);
2491	uint16_t iStatus = ich9pciGetWord(pPciDev, VBOX_PCI_STATUS);
2492	pHlp->pfnPrintf(pHlp, "Command: %04X, Status: %04X\n",
2493	iCmd, iStatus);
2494	printIndent(pHlp, iIndent + 2);
2495	pHlp->pfnPrintf(pHlp, "Bus master: %s\n",
2496	iCmd & VBOX_PCI_COMMAND_MASTER ? "Yes" : "No");
2497
2498	if (fRegisters)
2499	{
2500	printIndent(pHlp, iIndent + 2);
2501	pHlp->pfnPrintf(pHlp, "PCI registers:\n");
2502	for (int iReg = 0; iReg < 0x100; )
2503	{
2504	int iPerLine = 0x10;
2505	Assert (0x100 % iPerLine == 0);
2506	printIndent(pHlp, iIndent + 3);
2507
2508	while (iPerLine-- > 0)
2509	{
2510	pHlp->pfnPrintf(pHlp, "%02x ", ich9pciGetByte(pPciDev, iReg++));
2511	}
2512	pHlp->pfnPrintf(pHlp, "\n");
2513	}
2514	}
2515	}
2516	}
2517
2518	if (pBus->cBridges > 0)
2519	{
2520	printIndent(pHlp, iIndent);
2521	pHlp->pfnPrintf(pHlp, "Registered %d bridges, subordinate buses info follows\n", pBus->cBridges);
2522	for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
2523	{
2524	PICH9PCIBUS pBusSub = PDMINS_2_DATA(pBus->papBridgesR3[iBridge]->pDevIns, PICH9PCIBUS);
2525	ich9pciBusInfo(pBusSub, pHlp, iIndent + 1, fRegisters);
2526	}
2527	}
2528	}
2529
2530	/**
2531	* Info handler, device version.
2532	*
2533	* @param pDevIns Device instance which registered the info.
2534	* @param pHlp Callback functions for doing output.
2535	* @param pszArgs Argument string. Optional and specific to the handler.
2536	*/
2537	static DECLCALLBACK(void) ich9pciInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
2538	{
2539	PICH9PCIBUS pBus = DEVINS_2_PCIBUS(pDevIns);
2540
2541	if (pszArgs == NULL \|\| !strcmp(pszArgs, "basic"))
2542	{
2543	ich9pciBusInfo(pBus, pHlp, 0, false);
2544	}
2545	else if (!strcmp(pszArgs, "verbose"))
2546	{
2547	ich9pciBusInfo(pBus, pHlp, 0, true);
2548	}
2549	else
2550	{
2551	pHlp->pfnPrintf(pHlp, "Invalid argument. Recognized arguments are 'basic', 'verbose'.\n");
2552	}
2553	}
2554
2555
2556	static DECLCALLBACK(int) ich9pciConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
2557	{
2558	RT_NOREF1(iInstance);
2559	Assert(iInstance == 0);
2560	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
2561
2562	/*
2563	* Validate and read configuration.
2564	*/
2565	if (!CFGMR3AreValuesValid(pCfg,
2566	"IOAPIC\0"
2567	"GCEnabled\0"
2568	"R0Enabled\0"
2569	"McfgBase\0"
2570	"McfgLength\0"
2571	))
2572	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
2573
2574	/* query whether we got an IOAPIC */
2575	bool fUseIoApic;
2576	int rc = CFGMR3QueryBoolDef(pCfg, "IOAPIC", &fUseIoApic, false);
2577	if (RT_FAILURE(rc))
2578	return PDMDEV_SET_ERROR(pDevIns, rc,
2579	N_("Configuration error: Failed to query boolean value \"IOAPIC\""));
2580
2581	/* check if RC code is enabled. */
2582	bool fGCEnabled;
2583	rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
2584	if (RT_FAILURE(rc))
2585	return PDMDEV_SET_ERROR(pDevIns, rc,
2586	N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
2587	/* check if R0 code is enabled. */
2588	bool fR0Enabled;
2589	rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
2590	if (RT_FAILURE(rc))
2591	return PDMDEV_SET_ERROR(pDevIns, rc,
2592	N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
2593
2594	Log(("PCI: fUseIoApic=%RTbool fGCEnabled=%RTbool fR0Enabled=%RTbool\n", fUseIoApic, fGCEnabled, fR0Enabled));
2595
2596	/*
2597	* Init data.
2598	*/
2599	PICH9PCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
2600	PICH9PCIBUS pBus = &pGlobals->aPciBus;
2601	/* Zero out everything */
2602	memset(pGlobals, 0, sizeof(*pGlobals));
2603	/* And fill values */
2604	if (!fUseIoApic)
2605	return PDMDEV_SET_ERROR(pDevIns, rc,
2606	N_("Must use IO-APIC with ICH9 chipset"));
2607	rc = CFGMR3QueryU64Def(pCfg, "McfgBase", &pGlobals->u64PciConfigMMioAddress, 0);
2608	if (RT_FAILURE(rc))
2609	return PDMDEV_SET_ERROR(pDevIns, rc,
2610	N_("Configuration error: Failed to read \"McfgBase\""));
2611	rc = CFGMR3QueryU64Def(pCfg, "McfgLength", &pGlobals->u64PciConfigMMioLength, 0);
2612	if (RT_FAILURE(rc))
2613	return PDMDEV_SET_ERROR(pDevIns, rc,
2614	N_("Configuration error: Failed to read \"McfgLength\""));
2615
2616	pGlobals->pDevInsR3 = pDevIns;
2617	pGlobals->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2618	pGlobals->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2619
2620	pGlobals->aPciBus.pDevInsR3 = pDevIns;
2621	pGlobals->aPciBus.pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2622	pGlobals->aPciBus.pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2623	pGlobals->aPciBus.papBridgesR3 = (PPCIDEVICE )PDMDevHlpMMHeapAllocZ(pDevIns, sizeof(PPCIDEVICE) RT_ELEMENTS(pGlobals->aPciBus.apDevices));
2624
2625	/*
2626	* Register bus
2627	*/
2628	PDMPCIBUSREG PciBusReg;
2629	PciBusReg.u32Version = PDM_PCIBUSREG_VERSION;
2630	PciBusReg.pfnRegisterR3 = ich9pciRegister;
2631	PciBusReg.pfnRegisterMsiR3 = ich9pciRegisterMsi;
2632	PciBusReg.pfnIORegionRegisterR3 = ich9pciIORegionRegister;
2633	PciBusReg.pfnSetConfigCallbacksR3 = ich9pciSetConfigCallbacks;
2634	PciBusReg.pfnSetIrqR3 = ich9pciSetIrq;
2635	PciBusReg.pfnFakePCIBIOSR3 = ich9pciFakePCIBIOS;
2636	PciBusReg.pszSetIrqRC = fGCEnabled ? "ich9pciSetIrq" : NULL;
2637	PciBusReg.pszSetIrqR0 = fR0Enabled ? "ich9pciSetIrq" : NULL;
2638	rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBus->pPciHlpR3);
2639	if (RT_FAILURE(rc))
2640	return PDMDEV_SET_ERROR(pDevIns, rc,
2641	N_("Failed to register ourselves as a PCI Bus"));
2642	if (pBus->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
2643	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
2644	N_("PCI helper version mismatch; got %#x expected %#x"),
2645	pBus->pPciHlpR3->u32Version, PDM_PCIHLPR3_VERSION);
2646
2647	pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
2648	pBus->pPciHlpR0 = pBus->pPciHlpR3->pfnGetR0Helpers(pDevIns);
2649
2650	/*
2651	* Fill in PCI configs and add them to the bus.
2652	*/
2653	/** @todo Disabled for now because this causes error messages with Linux guests.
2654	* The guest loads the x38_edac device which tries to map a memory region
2655	* using an address given at place 0x48 - 0x4f in the PCi config space.
2656	* This fails. because we don't register such a region.
2657	*/
2658	#if 0
2659	/* Host bridge device */
2660	PCIDevSetVendorId( &pBus->aPciDev, 0x8086); /* Intel */
2661	PCIDevSetDeviceId( &pBus->aPciDev, 0x29e0); /* Desktop */
2662	PCIDevSetRevisionId(&pBus->aPciDev, 0x01); /* rev. 01 */
2663	PCIDevSetClassBase( &pBus->aPciDev, 0x06); /* bridge */
2664	PCIDevSetClassSub( &pBus->aPciDev, 0x00); /* Host/PCI bridge */
2665	PCIDevSetClassProg( &pBus->aPciDev, 0x00); /* Host/PCI bridge */
2666	PCIDevSetHeaderType(&pBus->aPciDev, 0x00); /* bridge */
2667	PCIDevSetWord(&pBus->aPciDev, VBOX_PCI_SEC_STATUS, 0x0280); /* secondary status */
2668
2669	pBus->aPciDev.pDevIns = pDevIns;
2670	/* We register Host<->PCI controller on the bus */
2671	ich9pciRegisterInternal(pBus, 0, &pBus->aPciDev, "dram");
2672	#endif
2673
2674	/*
2675	* Register I/O ports and save state.
2676	*/
2677	rc = PDMDevHlpIOPortRegister(pDevIns, 0x0cf8, 1, NULL, ich9pciIOPortAddressWrite, ich9pciIOPortAddressRead, NULL, NULL, "ICH9 (PCI)");
2678	if (RT_FAILURE(rc))
2679	return rc;
2680	rc = PDMDevHlpIOPortRegister(pDevIns, 0x0cfc, 4, NULL, ich9pciIOPortDataWrite, ich9pciIOPortDataRead, NULL, NULL, "ICH9 (PCI)");
2681	if (RT_FAILURE(rc))
2682	return rc;
2683	if (fGCEnabled)
2684	{
2685	rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x0cf8, 1, NIL_RTGCPTR, "ich9pciIOPortAddressWrite", "ich9pciIOPortAddressRead", NULL, NULL, "ICH9 (PCI)");
2686	if (RT_FAILURE(rc))
2687	return rc;
2688	rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x0cfc, 4, NIL_RTGCPTR, "ich9pciIOPortDataWrite", "ich9pciIOPortDataRead", NULL, NULL, "ICH9 (PCI)");
2689	if (RT_FAILURE(rc))
2690	return rc;
2691	}
2692	if (fR0Enabled)
2693	{
2694	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x0cf8, 1, NIL_RTR0PTR, "ich9pciIOPortAddressWrite", "ich9pciIOPortAddressRead", NULL, NULL, "ICH9 (PCI)");
2695	if (RT_FAILURE(rc))
2696	return rc;
2697	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x0cfc, 4, NIL_RTR0PTR, "ich9pciIOPortDataWrite", "ich9pciIOPortDataRead", NULL, NULL, "ICH9 (PCI)");
2698	if (RT_FAILURE(rc))
2699	return rc;
2700	}
2701
2702	if (pGlobals->u64PciConfigMMioAddress != 0)
2703	{
2704	rc = PDMDevHlpMMIORegister(pDevIns, pGlobals->u64PciConfigMMioAddress, pGlobals->u64PciConfigMMioLength, NULL /pvUser/,
2705	IOMMMIO_FLAGS_READ_PASSTHRU \| IOMMMIO_FLAGS_WRITE_PASSTHRU,
2706	ich9pciMcfgMMIOWrite, ich9pciMcfgMMIORead, "MCFG ranges");
2707	AssertMsgRCReturn(rc, ("rc=%Rrc %#llx/%#llx\n", rc, pGlobals->u64PciConfigMMioAddress, pGlobals->u64PciConfigMMioLength), rc);
2708
2709	if (fGCEnabled)
2710	{
2711	rc = PDMDevHlpMMIORegisterRC(pDevIns, pGlobals->u64PciConfigMMioAddress, pGlobals->u64PciConfigMMioLength,
2712	NIL_RTRCPTR /pvUser/, "ich9pciMcfgMMIOWrite", "ich9pciMcfgMMIORead");
2713	AssertRCReturn(rc, rc);
2714	}
2715
2716
2717	if (fR0Enabled)
2718	{
2719	rc = PDMDevHlpMMIORegisterR0(pDevIns, pGlobals->u64PciConfigMMioAddress, pGlobals->u64PciConfigMMioLength,
2720	NIL_RTR0PTR /pvUser/, "ich9pciMcfgMMIOWrite", "ich9pciMcfgMMIORead");
2721	AssertRCReturn(rc, rc);
2722	}
2723	}
2724
2725	rc = PDMDevHlpSSMRegisterEx(pDevIns, VBOX_ICH9PCI_SAVED_STATE_VERSION_CURRENT,
2726	sizeof(pBus) + 16128, "pgm",
2727	NULL, NULL, NULL,
2728	NULL, ich9pciR3SaveExec, NULL,
2729	NULL, ich9pciR3LoadExec, NULL);
2730	if (RT_FAILURE(rc))
2731	return rc;
2732
2733
2734	/** @todo other chipset devices shall be registered too */
2735
2736	PDMDevHlpDBGFInfoRegister(pDevIns, "pci", "Display PCI bus status. Recognizes 'basic' or 'verbose' "
2737	"as arguments, defaults to 'basic'.", ich9pciInfo);
2738
2739	return VINF_SUCCESS;
2740	}
2741
2742	static void ich9pciResetDevice(PPCIDEVICE pDev)
2743	{
2744	/* Clear regions */
2745	for (int iRegion = 0; iRegion < PCI_NUM_REGIONS; iRegion++)
2746	{
2747	PCIIORegion* pRegion = &pDev->Int.s.aIORegions[iRegion];
2748	if (pRegion->size == 0)
2749	continue;
2750
2751	ich9pciUnmapRegion(pDev, iRegion);
2752	}
2753
2754	if (pciDevIsPassthrough(pDev))
2755	{
2756	// no reset handler - we can do what we need in PDM reset handler
2757	/// @todo is it correct?
2758	}
2759	else
2760	{
2761	PCIDevSetCommand(pDev,
2762	PCIDevGetCommand(pDev)
2763	&
2764	~(VBOX_PCI_COMMAND_IO \| VBOX_PCI_COMMAND_MEMORY \|
2765	VBOX_PCI_COMMAND_MASTER \| VBOX_PCI_COMMAND_SPECIAL \|
2766	VBOX_PCI_COMMAND_PARITY \| VBOX_PCI_COMMAND_SERR \|
2767	VBOX_PCI_COMMAND_FAST_BACK \| VBOX_PCI_COMMAND_INTX_DISABLE));
2768
2769	/* Bridge device reset handlers processed later */
2770	if (!pciDevIsPci2PciBridge(pDev))
2771	{
2772	PCIDevSetByte(pDev, VBOX_PCI_CACHE_LINE_SIZE, 0x0);
2773	PCIDevSetInterruptLine(pDev, 0x0);
2774	}
2775
2776	/* Reset MSI message control. */
2777	if (pciDevIsMsiCapable(pDev))
2778	{
2779	/* Extracted from MsiPciConfigWrite(). */
2780	pDev->config[pDev->Int.s.u8MsiCapOffset + VBOX_MSI_CAP_MESSAGE_CONTROL] &= 0x8e;
2781	}
2782
2783	/* Reset MSI-X message control. */
2784	if (pciDevIsMsixCapable(pDev))
2785	{
2786	/* Extracted from MsixPciConfigWrite(); no side effects. */
2787	pDev->config[pDev->Int.s.u8MsixCapOffset + VBOX_MSIX_CAP_MESSAGE_CONTROL + 1] &= 0x3f;
2788	}
2789	}
2790	}
2791
2792
2793	/**
2794	* @copydoc FNPDMDEVRESET
2795	*/
2796	static DECLCALLBACK(void) ich9pciReset(PPDMDEVINS pDevIns)
2797	{
2798	PICH9PCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
2799	PICH9PCIBUS pBus = &pGlobals->aPciBus;
2800
2801	/* PCI-specific reset for each device. */
2802	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
2803	{
2804	if (pBus->apDevices[i])
2805	ich9pciResetDevice(pBus->apDevices[i]);
2806	}
2807
2808	for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
2809	{
2810	if (pBus->papBridgesR3[iBridge])
2811	ich9pcibridgeReset(pBus->papBridgesR3[iBridge]->pDevIns);
2812	}
2813
2814	ich9pciFakePCIBIOS(pDevIns);
2815	}
2816
2817	static void ich9pciRelocateDevice(PPCIDEVICE pDev, RTGCINTPTR offDelta)
2818	{
2819	if (pDev)
2820	{
2821	pDev->Int.s.pBusRC += offDelta;
2822	if (pDev->Int.s.pMsixPageRC)
2823	pDev->Int.s.pMsixPageRC += offDelta;
2824	}
2825	}
2826
2827	/**
2828	* @copydoc FNPDMDEVRELOCATE
2829	*/
2830	static DECLCALLBACK(void) ich9pciRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
2831	{
2832	PICH9PCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
2833	PICH9PCIBUS pBus = &pGlobals->aPciBus;
2834	pGlobals->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2835
2836	pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
2837	pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2838
2839	/* Relocate RC pointers for the attached pci devices. */
2840	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
2841	ich9pciRelocateDevice(pBus->apDevices[i], offDelta);
2842
2843	}
2844
2845	/**
2846	* @interface_method_impl{PDMDEVREG,pfnConstruct}
2847	*/
2848	static DECLCALLBACK(int) ich9pcibridgeConstruct(PPDMDEVINS pDevIns,
2849	int iInstance,
2850	PCFGMNODE pCfg)
2851	{
2852	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
2853
2854	/*
2855	* Validate and read configuration.
2856	*/
2857	if (!CFGMR3AreValuesValid(pCfg, "GCEnabled\0" "R0Enabled\0"))
2858	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
2859
2860	/* check if RC code is enabled. */
2861	bool fGCEnabled;
2862	int rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
2863	if (RT_FAILURE(rc))
2864	return PDMDEV_SET_ERROR(pDevIns, rc,
2865	N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
2866
2867	/* check if R0 code is enabled. */
2868	bool fR0Enabled;
2869	rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
2870	if (RT_FAILURE(rc))
2871	return PDMDEV_SET_ERROR(pDevIns, rc,
2872	N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
2873	Log(("PCI: fGCEnabled=%RTbool fR0Enabled=%RTbool\n", fGCEnabled, fR0Enabled));
2874
2875	/*
2876	* Init data and register the PCI bus.
2877	*/
2878	PICH9PCIBUS pBus = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
2879	pBus->pDevInsR3 = pDevIns;
2880	pBus->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2881	pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2882	pBus->papBridgesR3 = (PPCIDEVICE )PDMDevHlpMMHeapAllocZ(pDevIns, sizeof(PPCIDEVICE) RT_ELEMENTS(pBus->apDevices));
2883
2884	PDMPCIBUSREG PciBusReg;
2885	PciBusReg.u32Version = PDM_PCIBUSREG_VERSION;
2886	PciBusReg.pfnRegisterR3 = ich9pcibridgeRegister;
2887	PciBusReg.pfnRegisterMsiR3 = ich9pciRegisterMsi;
2888	PciBusReg.pfnIORegionRegisterR3 = ich9pciIORegionRegister;
2889	PciBusReg.pfnSetConfigCallbacksR3 = ich9pciSetConfigCallbacks;
2890	PciBusReg.pfnSetIrqR3 = ich9pcibridgeSetIrq;
2891	PciBusReg.pfnFakePCIBIOSR3 = NULL; /* Only needed for the first bus. */
2892	PciBusReg.pszSetIrqRC = fGCEnabled ? "ich9pcibridgeSetIrq" : NULL;
2893	PciBusReg.pszSetIrqR0 = fR0Enabled ? "ich9pcibridgeSetIrq" : NULL;
2894	rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBus->pPciHlpR3);
2895	if (RT_FAILURE(rc))
2896	return PDMDEV_SET_ERROR(pDevIns, rc,
2897	N_("Failed to register ourselves as a PCI Bus"));
2898	if (pBus->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
2899	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
2900	N_("PCI helper version mismatch; got %#x expected %#x"),
2901	pBus->pPciHlpR3->u32Version, PDM_PCIHLPR3_VERSION);
2902
2903	pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
2904	pBus->pPciHlpR0 = pBus->pPciHlpR3->pfnGetR0Helpers(pDevIns);
2905
2906	/* Disable default device locking. */
2907	rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
2908	AssertRCReturn(rc, rc);
2909
2910	/*
2911	* Fill in PCI configs and add them to the bus.
2912	*/
2913	PCIDevSetVendorId( &pBus->aPciDev, 0x8086); /* Intel */
2914	PCIDevSetDeviceId( &pBus->aPciDev, 0x2448); /* 82801 Mobile PCI bridge. */
2915	PCIDevSetRevisionId(&pBus->aPciDev, 0xf2);
2916	PCIDevSetClassSub( &pBus->aPciDev, 0x04); /* pci2pci */
2917	PCIDevSetClassBase( &pBus->aPciDev, 0x06); /* PCI_bridge */
2918	PCIDevSetClassProg( &pBus->aPciDev, 0x01); /* Supports subtractive decoding. */
2919	PCIDevSetHeaderType(&pBus->aPciDev, 0x01); /* Single function device which adheres to the PCI-to-PCI bridge spec. */
2920	PCIDevSetCommand( &pBus->aPciDev, 0x00);
2921	PCIDevSetStatus( &pBus->aPciDev, 0x20); /* 66MHz Capable. */
2922	PCIDevSetInterruptLine(&pBus->aPciDev, 0x00); /* This device does not assert interrupts. */
2923
2924	/*
2925	* This device does not generate interrupts. Interrupt delivery from
2926	* devices attached to the bus is unaffected.
2927	*/
2928	PCIDevSetInterruptPin (&pBus->aPciDev, 0x00);
2929
2930	pBus->aPciDev.pDevIns = pDevIns;
2931
2932	/* Bridge-specific data */
2933	pciDevSetPci2PciBridge(&pBus->aPciDev);
2934	pBus->aPciDev.Int.s.pfnBridgeConfigRead = ich9pcibridgeConfigRead;
2935	pBus->aPciDev.Int.s.pfnBridgeConfigWrite = ich9pcibridgeConfigWrite;
2936
2937	/*
2938	* Register this PCI bridge. The called function will take care on which bus we will get registered.
2939	*/
2940	rc = PDMDevHlpPCIRegister (pDevIns, &pBus->aPciDev);
2941	if (RT_FAILURE(rc))
2942	return rc;
2943
2944	/*
2945	* The iBus property doesn't really represent the bus number
2946	* because the guest and the BIOS can choose different bus numbers
2947	* for them.
2948	* The bus number is mainly for the setIrq function to indicate
2949	* when the host bus is reached which will have iBus = 0.
2950	* That's why the + 1.
2951	*/
2952	pBus->iBus = iInstance + 1;
2953
2954	/*
2955	* Register SSM handlers. We use the same saved state version as for the host bridge
2956	* to make changes easier.
2957	*/
2958	rc = PDMDevHlpSSMRegisterEx(pDevIns, VBOX_ICH9PCI_SAVED_STATE_VERSION_CURRENT,
2959	sizeof(pBus) + 16128,
2960	"pgm" /* before */,
2961	NULL, NULL, NULL,
2962	NULL, ich9pcibridgeR3SaveExec, NULL,
2963	NULL, ich9pcibridgeR3LoadExec, NULL);
2964	if (RT_FAILURE(rc))
2965	return rc;
2966
2967
2968	return VINF_SUCCESS;
2969	}
2970
2971	/**
2972	* @copydoc FNPDMDEVRESET
2973	*/
2974	static void ich9pcibridgeReset(PPDMDEVINS pDevIns)
2975	{
2976	PICH9PCIBUS pBus = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
2977
2978	/* Reset config space to default values. */
2979	PCIDevSetByte(&pBus->aPciDev, VBOX_PCI_PRIMARY_BUS, 0);
2980	PCIDevSetByte(&pBus->aPciDev, VBOX_PCI_SECONDARY_BUS, 0);
2981	PCIDevSetByte(&pBus->aPciDev, VBOX_PCI_SUBORDINATE_BUS, 0);
2982
2983	/* PCI-specific reset for each device. */
2984	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
2985	{
2986	if (pBus->apDevices[i])
2987	ich9pciResetDevice(pBus->apDevices[i]);
2988	}
2989	}
2990
2991
2992	/**
2993	* @copydoc FNPDMDEVRELOCATE
2994	*/
2995	static DECLCALLBACK(void) ich9pcibridgeRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
2996	{
2997	PICH9PCIBUS pBus = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
2998	pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2999
3000	/* Relocate RC pointers for the attached pci devices. */
3001	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
3002	ich9pciRelocateDevice(pBus->apDevices[i], offDelta);
3003	}
3004
3005	/**
3006	* The PCI bus device registration structure.
3007	*/
3008	const PDMDEVREG g_DevicePciIch9 =
3009	{
3010	/* u32Version */
3011	PDM_DEVREG_VERSION,
3012	/* szName */
3013	"ich9pci",
3014	/* szRCMod */
3015	"VBoxDDRC.rc",
3016	/* szR0Mod */
3017	"VBoxDDR0.r0",
3018	/* pszDescription */
3019	"ICH9 PCI bridge",
3020	/* fFlags */
3021	PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
3022	/* fClass */
3023	PDM_DEVREG_CLASS_BUS_PCI \| PDM_DEVREG_CLASS_BUS_ISA,
3024	/* cMaxInstances */
3025	1,
3026	/* cbInstance */
3027	sizeof(ICH9PCIGLOBALS),
3028	/* pfnConstruct */
3029	ich9pciConstruct,
3030	/* pfnDestruct */
3031	NULL,
3032	/* pfnRelocate */
3033	ich9pciRelocate,
3034	/* pfnMemSetup */
3035	NULL,
3036	/* pfnPowerOn */
3037	NULL,
3038	/* pfnReset */
3039	ich9pciReset,
3040	/* pfnSuspend */
3041	NULL,
3042	/* pfnResume */
3043	NULL,
3044	/* pfnAttach */
3045	NULL,
3046	/* pfnDetach */
3047	NULL,
3048	/* pfnQueryInterface */
3049	NULL,
3050	/* pfnInitComplete */
3051	NULL,
3052	/* pfnPowerOff */
3053	NULL,
3054	/* pfnSoftReset */
3055	NULL,
3056	/* u32VersionEnd */
3057	PDM_DEVREG_VERSION
3058	};
3059
3060	/**
3061	* The device registration structure
3062	* for the PCI-to-PCI bridge.
3063	*/
3064	const PDMDEVREG g_DevicePciIch9Bridge =
3065	{
3066	/* u32Version */
3067	PDM_DEVREG_VERSION,
3068	/* szName */
3069	"ich9pcibridge",
3070	/* szRCMod */
3071	"VBoxDDRC.rc",
3072	/* szR0Mod */
3073	"VBoxDDR0.r0",
3074	/* pszDescription */
3075	"ICH9 PCI to PCI bridge",
3076	/* fFlags */
3077	PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
3078	/* fClass */
3079	PDM_DEVREG_CLASS_BUS_PCI,
3080	/* cMaxInstances */
3081	~0U,
3082	/* cbInstance */
3083	sizeof(ICH9PCIBUS),
3084	/* pfnConstruct */
3085	ich9pcibridgeConstruct,
3086	/* pfnDestruct */
3087	NULL,
3088	/* pfnRelocate */
3089	ich9pcibridgeRelocate,
3090	/* pfnMemSetup */
3091	NULL,
3092	/* pfnPowerOn */
3093	NULL,
3094	/* pfnReset */
3095	NULL, /* Must be NULL, to make sure only bus driver handles reset */
3096	/* pfnSuspend */
3097	NULL,
3098	/* pfnResume */
3099	NULL,
3100	/* pfnAttach */
3101	NULL,
3102	/* pfnDetach */
3103	NULL,
3104	/* pfnQueryInterface */
3105	NULL,
3106	/* pfnInitComplete */
3107	NULL,
3108	/* pfnPowerOff */
3109	NULL,
3110	/* pfnSoftReset */
3111	NULL,
3112	/* u32VersionEnd */
3113	PDM_DEVREG_VERSION
3114	};
3115
3116	#endif /* IN_RING3 */
3117	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */

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source: vbox/trunk/src/VBox/Devices/Bus/DevPciIch9.cpp@ 64115

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