DevPciIch9.cpp@ 64459

Last change on this file since 64459 was 64459, checked in by vboxsync, 8 years ago
DevPci: Cleaning up ich9pciConfigWriteDev.
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1	/* $Id: DevPciIch9.cpp 64459 2016-10-28 14:12:20Z vboxsync $ */
2	/** @file
3	* DevPCI - ICH9 southbridge PCI bus emulation device.
4	*
5	* @remarks We'll be slowly promoting the code in this file to common PCI bus
6	* code. Function without 'static' and using 'devpci' as prefix is
7	* also used by DevPCI.cpp and have a prototype in DevPciInternal.h.
8	*
9	* For the time being the DevPciMerge1.cpp.h file will remain separate,
10	* due to 5.1. We can merge it into this one later in the dev cycle.
11	*/
12
13	/*
14	* Copyright (C) 2010-2016 Oracle Corporation
15	*
16	* This file is part of VirtualBox Open Source Edition (OSE), as
17	* available from http://www.virtualbox.org. This file is free software;
18	* you can redistribute it and/or modify it under the terms of the GNU
19	* General Public License (GPL) as published by the Free Software
20	* Foundation, in version 2 as it comes in the "COPYING" file of the
21	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
22	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
23	*/
24
25
26	/*********************************************************************************************************************************
27	* Header Files *
28	*********************************************************************************************************************************/
29	#define LOG_GROUP LOG_GROUP_DEV_PCI
30	#define PDMPCIDEV_INCLUDE_PRIVATE /* Hack to get pdmpcidevint.h included at the right point. */
31	#include <VBox/vmm/pdmpcidev.h>
32
33	#include <VBox/msi.h>
34	#include <VBox/vmm/pdmdev.h>
35	#include <VBox/vmm/mm.h>
36	#include <iprt/asm.h>
37	#include <iprt/assert.h>
38	#include <iprt/string.h>
39	#ifdef IN_RING3
40	# include <iprt/mem.h>
41	#endif
42
43	#include "PciInline.h"
44	#include "VBoxDD.h"
45	#include "MsiCommon.h"
46	#include "DevPciInternal.h"
47
48
49	/*********************************************************************************************************************************
50	* Structures and Typedefs *
51	*********************************************************************************************************************************/
52	/**
53	* PCI configuration space address.
54	*/
55	typedef struct
56	{
57	uint8_t iBus;
58	uint8_t iDeviceFunc;
59	uint16_t iRegister;
60	} PciAddress;
61
62
63	/*********************************************************************************************************************************
64	* Defined Constants And Macros *
65	*********************************************************************************************************************************/
66	/** @def VBOX_ICH9PCI_SAVED_STATE_VERSION
67	* Saved state version of the ICH9 PCI bus device.
68	*/
69	#define VBOX_ICH9PCI_SAVED_STATE_VERSION_NOMSI 1
70	#define VBOX_ICH9PCI_SAVED_STATE_VERSION_MSI 2
71	#define VBOX_ICH9PCI_SAVED_STATE_VERSION_CURRENT VBOX_ICH9PCI_SAVED_STATE_VERSION_MSI
72
73
74	/*********************************************************************************************************************************
75	* Internal Functions *
76	*********************************************************************************************************************************/
77	/* Prototypes */
78	static void ich9pciSetIrqInternal(PDEVPCIROOT pGlobals, uint8_t uDevFn, PPDMPCIDEV pPciDev,
79	int iIrq, int iLevel, uint32_t uTagSrc);
80	#ifdef IN_RING3
81	static void ich9pcibridgeReset(PPDMDEVINS pDevIns);
82	static void ich9pciUpdateMappings(PDMPCIDEV *pDev);
83	static DECLCALLBACK(void) ich9pciConfigWriteDev(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t u32Address, uint32_t val, unsigned len);
84	DECLINLINE(PPDMPCIDEV) ich9pciFindBridge(PDEVPCIBUS pBus, uint8_t iBus);
85	static void ich9pciBiosInitDevice(PDEVPCIROOT pGlobals, uint8_t uBus, uint8_t uDevFn);
86	#endif
87
88
89	// See 7.2.2. PCI Express Enhanced Configuration Mechanism for details of address
90	// mapping, we take n=6 approach
91	DECLINLINE(void) ich9pciPhysToPciAddr(PDEVPCIROOT pGlobals, RTGCPHYS GCPhysAddr, PciAddress* pPciAddr)
92	{
93	NOREF(pGlobals);
94	pPciAddr->iBus = (GCPhysAddr >> 20) & ((1<<6) - 1);
95	pPciAddr->iDeviceFunc = (GCPhysAddr >> 12) & ((1<<(5+3)) - 1); // 5 bits - device, 3 bits - function
96	pPciAddr->iRegister = (GCPhysAddr >> 0) & ((1<<(6+4+2)) - 1); // 6 bits - register, 4 bits - extended register, 2 bits -Byte Enable
97	}
98
99	DECLINLINE(void) ich9pciStateToPciAddr(PDEVPCIROOT pGlobals, RTGCPHYS addr, PciAddress* pPciAddr)
100	{
101	pPciAddr->iBus = (pGlobals->uConfigReg >> 16) & 0xff;
102	pPciAddr->iDeviceFunc = (pGlobals->uConfigReg >> 8) & 0xff;
103	pPciAddr->iRegister = (pGlobals->uConfigReg & 0xfc) \| (addr & 3);
104	}
105
106	PDMBOTHCBDECL(void) ich9pciSetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc)
107	{
108	LogFlowFunc(("invoked by %p/%d: iIrq=%d iLevel=%d uTagSrc=%#x\n", pDevIns, pDevIns->iInstance, iIrq, iLevel, uTagSrc));
109	ich9pciSetIrqInternal(PDMINS_2_DATA(pDevIns, PDEVPCIROOT), pPciDev->uDevFn, pPciDev, iIrq, iLevel, uTagSrc);
110	}
111
112	PDMBOTHCBDECL(void) ich9pcibridgeSetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc)
113	{
114	/*
115	* The PCI-to-PCI bridge specification defines how the interrupt pins
116	* are routed from the secondary to the primary bus (see chapter 9).
117	* iIrq gives the interrupt pin the pci device asserted.
118	* We change iIrq here according to the spec and call the SetIrq function
119	* of our parent passing the device which asserted the interrupt instead of the device of the bridge.
120	*/
121	PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
122	PPDMPCIDEV pPciDevBus = pPciDev;
123	int iIrqPinBridge = iIrq;
124	uint8_t uDevFnBridge = 0;
125
126	/* Walk the chain until we reach the host bus. */
127	do
128	{
129	uDevFnBridge = pBus->PciDev.uDevFn;
130	iIrqPinBridge = ((pPciDevBus->uDevFn >> 3) + iIrqPinBridge) & 3;
131
132	/* Get the parent. */
133	pBus = pBus->PciDev.Int.s.CTX_SUFF(pBus);
134	pPciDevBus = &pBus->PciDev;
135	} while (pBus->iBus != 0);
136
137	AssertMsgReturnVoid(pBus->iBus == 0, ("This is not the host pci bus iBus=%d\n", pBus->iBus));
138	ich9pciSetIrqInternal(DEVPCIBUS_2_DEVPCIROOT(pBus), uDevFnBridge, pPciDev, iIrqPinBridge, iLevel, uTagSrc);
139	}
140
141
142	/**
143	* Port I/O Handler for PCI address OUT operations.
144	*
145	* Emulates writes to Configuration Address Port at 0CF8h for
146	* Configuration Mechanism #1.
147	*
148	* @returns VBox status code.
149	*
150	* @param pDevIns ICH9 device instance.
151	* @param pvUser User argument - ignored.
152	* @param uPort Port number used for the OUT operation.
153	* @param u32 The value to output.
154	* @param cb The value size in bytes.
155	*/
156	PDMBOTHCBDECL(int) ich9pciIOPortAddressWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
157	{
158	LogFlow(("ich9pciIOPortAddressWrite: Port=%#x u32=%#x cb=%d\n", Port, u32, cb));
159	RT_NOREF2(Port, pvUser);
160	if (cb == 4)
161	{
162	PDEVPCIROOT pThis = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
163
164	/*
165	* bits [1:0] are hard-wired, read-only and must return zeroes
166	* when read.
167	*/
168	u32 &= ~3;
169
170	PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_WRITE);
171	pThis->uConfigReg = u32;
172	PCI_UNLOCK(pDevIns);
173	}
174
175	return VINF_SUCCESS;
176	}
177
178
179	/**
180	* Port I/O Handler for PCI address IN operations.
181	*
182	* Emulates reads from Configuration Address Port at 0CF8h for
183	* Configuration Mechanism #1.
184	*
185	* @returns VBox status code.
186	*
187	* @param pDevIns ICH9 device instance.
188	* @param pvUser User argument - ignored.
189	* @param uPort Port number used for the IN operation.
190	* @param pu32 Where to store the result.
191	* @param cb Number of bytes read.
192	*/
193	PDMBOTHCBDECL(int) ich9pciIOPortAddressRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
194	{
195	RT_NOREF2(Port, pvUser);
196	if (cb == 4)
197	{
198	PDEVPCIROOT pThis = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
199
200	PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_READ);
201	*pu32 = pThis->uConfigReg;
202	PCI_UNLOCK(pDevIns);
203
204	LogFlow(("ich9pciIOPortAddressRead: Port=%#x cb=%d -> %#x\n", Port, cb, *pu32));
205	return VINF_SUCCESS;
206	}
207
208	Log(("ich9pciIOPortAddressRead: Port=%#x cb=%d VERR_IOM_IOPORT_UNUSED\n", Port, cb));
209	return VERR_IOM_IOPORT_UNUSED;
210	}
211
212
213	/*
214	* Perform configuration space write.
215	*/
216	static int ich9pciDataWriteAddr(PDEVPCIROOT pGlobals, PciAddress* pAddr,
217	uint32_t val, int cb, int rcReschedule)
218	{
219	int rc = VINF_SUCCESS;
220	#ifdef IN_RING3
221	NOREF(rcReschedule);
222	#else
223	RT_NOREF2(val, cb);
224	#endif
225
226	if (pAddr->iBus != 0) /* forward to subordinate bus */
227	{
228	if (pGlobals->PciBus.cBridges)
229	{
230	#ifdef IN_RING3 /** @todo do lookup in R0/RC too! */
231	PPDMPCIDEV pBridgeDevice = ich9pciFindBridge(&pGlobals->PciBus, pAddr->iBus);
232	if (pBridgeDevice)
233	{
234	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigWrite);
235	pBridgeDevice->Int.s.pfnBridgeConfigWrite(pBridgeDevice->Int.s.CTX_SUFF(pDevIns), pAddr->iBus, pAddr->iDeviceFunc,
236	pAddr->iRegister, val, cb);
237	}
238	#else
239	rc = rcReschedule;
240	#endif
241	}
242	}
243	else /* forward to directly connected device */
244	{
245	R3PTRTYPE(PDMPCIDEV *) pPciDev = pGlobals->PciBus.apDevices[pAddr->iDeviceFunc];
246	if (pPciDev)
247	{
248	#ifdef IN_RING3
249	pPciDev->Int.s.pfnConfigWrite(pPciDev->Int.s.CTX_SUFF(pDevIns), pPciDev, pAddr->iRegister, val, cb);
250	#else
251	rc = rcReschedule;
252	#endif
253	}
254	}
255
256	Log2(("ich9pciDataWriteAddr: %02x:%02x:%02x reg %x(%d) %x %Rrc\n",
257	pAddr->iBus, pAddr->iDeviceFunc >> 3, pAddr->iDeviceFunc & 0x7, pAddr->iRegister,
258	cb, val, rc));
259	return rc;
260	}
261
262
263	/*
264	* Decode value latched in Configuration Address Port and perform
265	* requsted write to the target configuration space register.
266	*
267	* XXX: This code should be probably moved to its only caller
268	* (ich9pciIOPortDataWrite) to avoid prolifiration of confusingly
269	* similarly named functions.
270	*/
271	static int ich9pciDataWrite(PDEVPCIROOT pGlobals, uint32_t addr, uint32_t val, int len)
272	{
273	LogFlow(("ich9pciDataWrite: config=%08x val=%08x len=%d\n", pGlobals->uConfigReg, val, len));
274
275	/* Configuration space mapping enabled? */
276	if (!(pGlobals->uConfigReg & (1 << 31)))
277	return VINF_SUCCESS;
278
279	/* Decode target device and configuration space register */
280	PciAddress aPciAddr;
281	ich9pciStateToPciAddr(pGlobals, addr, &aPciAddr);
282
283	/* Perform configuration space write */
284	return ich9pciDataWriteAddr(pGlobals, &aPciAddr, val, len, VINF_IOM_R3_IOPORT_WRITE);
285	}
286
287
288	/**
289	* Port I/O Handler for PCI data OUT operations.
290	*
291	* Emulates writes to Configuration Data Port at 0CFCh for
292	* Configuration Mechanism #1.
293	*
294	* @returns VBox status code.
295	*
296	* @param pDevIns ICH9 device instance.
297	* @param pvUser User argument - ignored.
298	* @param uPort Port number used for the OUT operation.
299	* @param u32 The value to output.
300	* @param cb The value size in bytes.
301	*/
302	PDMBOTHCBDECL(int) ich9pciIOPortDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
303	{
304	LogFlow(("ich9pciIOPortDataWrite: Port=%#x u32=%#x cb=%d\n", Port, u32, cb));
305	NOREF(pvUser);
306	int rc = VINF_SUCCESS;
307	if (!(Port % cb))
308	{
309	PDEVPCIROOT pThis = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
310
311	PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_WRITE);
312	rc = ich9pciDataWrite(pThis, Port, u32, cb);
313	PCI_UNLOCK(pDevIns);
314	}
315	else
316	AssertMsgFailed(("Unaligned write to port %#x u32=%#x cb=%d\n", Port, u32, cb));
317	return rc;
318	}
319
320
321	static void ich9pciNoMem(void* ptr, int cb)
322	{
323	for (int i = 0; i < cb; i++)
324	((uint8_t*)ptr)[i] = 0xff;
325	}
326
327
328	/*
329	* Perform configuration space read.
330	*/
331	static int ich9pciDataReadAddr(PDEVPCIROOT pGlobals, PciAddress* pPciAddr, int cb,
332	uint32_t *pu32, int rcReschedule)
333	{
334	int rc = VINF_SUCCESS;
335	#ifdef IN_RING3
336	NOREF(rcReschedule);
337	#endif
338
339	if (pPciAddr->iBus != 0) /* forward to subordinate bus */
340	{
341	if (pGlobals->PciBus.cBridges)
342	{
343	#ifdef IN_RING3 /** @todo do lookup in R0/RC too! */
344	PPDMPCIDEV pBridgeDevice = ich9pciFindBridge(&pGlobals->PciBus, pPciAddr->iBus);
345	if (pBridgeDevice)
346	{
347	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigRead);
348	*pu32 = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->Int.s.CTX_SUFF(pDevIns), pPciAddr->iBus,
349	pPciAddr->iDeviceFunc, pPciAddr->iRegister, cb);
350	}
351	else
352	ich9pciNoMem(pu32, cb);
353	#else
354	rc = rcReschedule;
355	#endif
356	}
357	else
358	ich9pciNoMem(pu32, cb);
359	}
360	else /* forward to directly connected device */
361	{
362	R3PTRTYPE(PDMPCIDEV *) pPciDev = pGlobals->PciBus.apDevices[pPciAddr->iDeviceFunc];
363	if (pPciDev)
364	{
365	#ifdef IN_RING3
366	*pu32 = pPciDev->Int.s.pfnConfigRead(pPciDev->Int.s.CTX_SUFF(pDevIns), pPciDev, pPciAddr->iRegister, cb);
367	#else
368	rc = rcReschedule;
369	#endif
370	}
371	else
372	ich9pciNoMem(pu32, cb);
373	}
374
375	Log3(("ich9pciDataReadAddr: %02x:%02x:%02x reg %x(%d) gave %x %Rrc\n",
376	pPciAddr->iBus, pPciAddr->iDeviceFunc >> 3, pPciAddr->iDeviceFunc & 0x7, pPciAddr->iRegister,
377	cb, *pu32, rc));
378	return rc;
379	}
380
381
382	/*
383	* Decode value latched in Configuration Address Port and perform
384	* requsted read from the target configuration space register.
385	*
386	* XXX: This code should be probably moved to its only caller
387	* (ich9pciIOPortDataRead) to avoid prolifiration of confusingly
388	* similarly named functions.
389	*/
390	static int ich9pciDataRead(PDEVPCIROOT pGlobals, uint32_t addr, int cb, uint32_t *pu32)
391	{
392	LogFlow(("ich9pciDataRead: config=%x cb=%d\n", pGlobals->uConfigReg, cb));
393
394	*pu32 = 0xffffffff;
395
396	/* Configuration space mapping enabled? */
397	if (!(pGlobals->uConfigReg & (1 << 31)))
398	return VINF_SUCCESS;
399
400	/* Decode target device and configuration space register */
401	PciAddress aPciAddr;
402	ich9pciStateToPciAddr(pGlobals, addr, &aPciAddr);
403
404	/* Perform configuration space read */
405	return ich9pciDataReadAddr(pGlobals, &aPciAddr, cb, pu32, VINF_IOM_R3_IOPORT_READ);
406	}
407
408
409	/**
410	* Port I/O Handler for PCI data IN operations.
411	*
412	* Emulates reads from Configuration Data Port at 0CFCh for
413	* Configuration Mechanism #1.
414	*
415	* @returns VBox status code.
416	*
417	* @param pDevIns ICH9 device instance.
418	* @param pvUser User argument - ignored.
419	* @param uPort Port number used for the IN operation.
420	* @param pu32 Where to store the result.
421	* @param cb Number of bytes read.
422	*/
423	PDMBOTHCBDECL(int) ich9pciIOPortDataRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
424	{
425	NOREF(pvUser);
426	if (!(Port % cb))
427	{
428	PDEVPCIROOT pThis = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
429
430	PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_READ);
431	int rc = ich9pciDataRead(pThis, Port, cb, pu32);
432	PCI_UNLOCK(pDevIns);
433
434	LogFlow(("ich9pciIOPortDataRead: Port=%#x cb=%#x -> %#x (%Rrc)\n", Port, cb, *pu32, rc));
435	return rc;
436	}
437	AssertMsgFailed(("Unaligned read from port %#x cb=%d\n", Port, cb));
438	return VERR_IOM_IOPORT_UNUSED;
439	}
440
441
442	/* Compute mapping of PCI slot and IRQ number to APIC interrupt line */
443	DECLINLINE(int) ich9pciSlot2ApicIrq(uint8_t uSlot, int irq_num)
444	{
445	return (irq_num + uSlot) & 7;
446	}
447
448	#ifdef IN_RING3
449
450	/* return the global irq number corresponding to a given device irq
451	pin. We could also use the bus number to have a more precise
452	mapping. This is the implementation note described in the PCI spec chapter 2.2.6 */
453	DECLINLINE(int) ich9pciSlotGetPirq(uint8_t uBus, uint8_t uDevFn, int iIrqNum)
454	{
455	NOREF(uBus);
456	int iSlotAddend = (uDevFn >> 3) - 1;
457	return (iIrqNum + iSlotAddend) & 3;
458	}
459
460	/* irqs corresponding to PCI irqs A-D, must match pci_irq_list in rombios.c */
461	static const uint8_t aPciIrqs[4] = { 11, 10, 9, 5 };
462
463	#endif /* IN_RING3 */
464
465	/* Add one more level up request on APIC input line */
466	DECLINLINE(void) ich9pciApicLevelUp(PDEVPCIROOT pGlobals, int irq_num)
467	{
468	ASMAtomicIncU32(&pGlobals->auPciApicIrqLevels[irq_num]);
469	}
470
471	/* Remove one level up request on APIC input line */
472	DECLINLINE(void) ich9pciApicLevelDown(PDEVPCIROOT pGlobals, int irq_num)
473	{
474	ASMAtomicDecU32(&pGlobals->auPciApicIrqLevels[irq_num]);
475	}
476
477	static void ich9pciApicSetIrq(PDEVPCIBUS pBus, uint8_t uDevFn, PDMPCIDEV *pPciDev, int irq_num1, int iLevel,
478	uint32_t uTagSrc, int iForcedIrq)
479	{
480	/* This is only allowed to be called with a pointer to the root bus. */
481	AssertMsg(pBus->iBus == 0, ("iBus=%u\n", pBus->iBus));
482
483	if (iForcedIrq == -1)
484	{
485	int apic_irq, apic_level;
486	PDEVPCIROOT pGlobals = DEVPCIBUS_2_DEVPCIROOT(pBus);
487	int irq_num = ich9pciSlot2ApicIrq(uDevFn >> 3, irq_num1);
488
489	if ((iLevel & PDM_IRQ_LEVEL_HIGH) == PDM_IRQ_LEVEL_HIGH)
490	ich9pciApicLevelUp(pGlobals, irq_num);
491	else if ((iLevel & PDM_IRQ_LEVEL_HIGH) == PDM_IRQ_LEVEL_LOW)
492	ich9pciApicLevelDown(pGlobals, irq_num);
493
494	apic_irq = irq_num + 0x10;
495	apic_level = pGlobals->auPciApicIrqLevels[irq_num] != 0;
496	Log3(("ich9pciApicSetIrq: %s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d uTagSrc=%#x\n",
497	R3STRING(pPciDev->pszNameR3), irq_num1, iLevel, apic_irq, apic_level, irq_num, uTagSrc));
498	pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), apic_irq, apic_level, uTagSrc);
499
500	if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP)
501	{
502	/*
503	* we raised it few lines above, as PDM_IRQ_LEVEL_FLIP_FLOP has
504	* PDM_IRQ_LEVEL_HIGH bit set
505	*/
506	ich9pciApicLevelDown(pGlobals, irq_num);
507	pPciDev->Int.s.uIrqPinState = PDM_IRQ_LEVEL_LOW;
508	apic_level = pGlobals->auPciApicIrqLevels[irq_num] != 0;
509	Log3(("ich9pciApicSetIrq: %s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d uTagSrc=%#x (flop)\n",
510	R3STRING(pPciDev->pszNameR3), irq_num1, iLevel, apic_irq, apic_level, irq_num, uTagSrc));
511	pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), apic_irq, apic_level, uTagSrc);
512	}
513	} else {
514	Log3(("ich9pciApicSetIrq: (forced) %s: irq_num1=%d level=%d acpi_irq=%d uTagSrc=%#x\n",
515	R3STRING(pPciDev->pszNameR3), irq_num1, iLevel, iForcedIrq, uTagSrc));
516	pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), iForcedIrq, iLevel, uTagSrc);
517	}
518	}
519
520	static void ich9pciSetIrqInternal(PDEVPCIROOT pGlobals, uint8_t uDevFn, PPDMPCIDEV pPciDev,
521	int iIrq, int iLevel, uint32_t uTagSrc)
522	{
523	/* If MSI or MSI-X is enabled, PCI INTx# signals are disabled regardless of the PCI command
524	* register interrupt bit state.
525	* PCI 3.0 (section 6.8) forbids MSI and MSI-X to be enabled at the same time and makes
526	* that undefined behavior. We check for MSI first, then MSI-X.
527	*/
528	if (MsiIsEnabled(pPciDev))
529	{
530	Assert(!MsixIsEnabled(pPciDev)); /* Not allowed -- see note above. */
531	LogFlowFunc(("PCI Dev %p : MSI\n", pPciDev));
532	PPDMDEVINS pDevIns = pGlobals->PciBus.CTX_SUFF(pDevIns);
533	MsiNotify(pDevIns, pGlobals->PciBus.CTX_SUFF(pPciHlp), pPciDev, iIrq, iLevel, uTagSrc);
534	return;
535	}
536
537	if (MsixIsEnabled(pPciDev))
538	{
539	LogFlowFunc(("PCI Dev %p : MSI-X\n", pPciDev));
540	PPDMDEVINS pDevIns = pGlobals->PciBus.CTX_SUFF(pDevIns);
541	MsixNotify(pDevIns, pGlobals->PciBus.CTX_SUFF(pPciHlp), pPciDev, iIrq, iLevel, uTagSrc);
542	return;
543	}
544
545	PDEVPCIBUS pBus = &pGlobals->PciBus;
546	const bool fIsAcpiDevice = PCIDevGetDeviceId(pPciDev) == 0x7113;
547
548	LogFlowFunc(("PCI Dev %p : IRQ\n", pPciDev));
549	/* Check if the state changed. */
550	if (pPciDev->Int.s.uIrqPinState != iLevel)
551	{
552	pPciDev->Int.s.uIrqPinState = (iLevel & PDM_IRQ_LEVEL_HIGH);
553
554	/* Send interrupt to I/O APIC only now. */
555	if (fIsAcpiDevice)
556	/*
557	* ACPI needs special treatment since SCI is hardwired and
558	* should not be affected by PCI IRQ routing tables at the
559	* same time SCI IRQ is shared in PCI sense hence this
560	* kludge (i.e. we fetch the hardwired value from ACPIs
561	* PCI device configuration space).
562	*/
563	ich9pciApicSetIrq(pBus, uDevFn, pPciDev, -1, iLevel, uTagSrc, PCIDevGetInterruptLine(pPciDev));
564	else
565	ich9pciApicSetIrq(pBus, uDevFn, pPciDev, iIrq, iLevel, uTagSrc, -1);
566	}
567	}
568
569
570	/**
571	* Memory mapped I/O Handler for write operations.
572	*
573	* Emulates writes to configuration space.
574	*
575	* @returns VBox status code.
576	*
577	* @param pDevIns The device instance.
578	* @param pvUser User argument.
579	* @param GCPhysAddr Physical address (in GC) where the read starts.
580	* @param pv Where to fetch the result.
581	* @param cb Number of bytes to write.
582	* @remarks Caller enters the device critical section.
583	*/
584	PDMBOTHCBDECL(int) ich9pciMcfgMMIOWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void const pv, unsigned cb)
585	{
586	PDEVPCIROOT pGlobals = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
587	uint32_t u32 = 0;
588	NOREF(pvUser);
589
590	Log2(("ich9pciMcfgMMIOWrite: %RGp(%d) \n", GCPhysAddr, cb));
591
592	PCI_LOCK(pDevIns, VINF_IOM_R3_MMIO_WRITE);
593
594	/* Decode target device and configuration space register */
595	PciAddress aDest;
596	ich9pciPhysToPciAddr(pGlobals, GCPhysAddr, &aDest);
597
598	switch (cb)
599	{
600	case 1:
601	u32 = (uint8_t)pv;
602	break;
603	case 2:
604	u32 = (uint16_t)pv;
605	break;
606	case 4:
607	u32 = (uint32_t)pv;
608	break;
609	default:
610	Assert(false);
611	break;
612	}
613
614	/* Perform configuration space write */
615	int rc = ich9pciDataWriteAddr(pGlobals, &aDest, u32, cb, VINF_IOM_R3_MMIO_WRITE);
616	PCI_UNLOCK(pDevIns);
617
618	return rc;
619	}
620
621
622	/**
623	* Memory mapped I/O Handler for read operations.
624	*
625	* Emulates reads from configuration space.
626	*
627	* @returns VBox status code.
628	*
629	* @param pDevIns The device instance.
630	* @param pvUser User argument.
631	* @param GCPhysAddr Physical address (in GC) where the read starts.
632	* @param pv Where to store the result.
633	* @param cb Number of bytes read.
634	* @remarks Caller enters the device critical section.
635	*/
636	PDMBOTHCBDECL(int) ich9pciMcfgMMIORead (PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb)
637	{
638	PDEVPCIROOT pGlobals = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
639	uint32_t rv;
640	NOREF(pvUser);
641
642	LogFlow(("ich9pciMcfgMMIORead: %RGp(%d) \n", GCPhysAddr, cb));
643
644	PCI_LOCK(pDevIns, VINF_IOM_R3_MMIO_READ);
645
646	/* Decode target device and configuration space register */
647	PciAddress aDest;
648	ich9pciPhysToPciAddr(pGlobals, GCPhysAddr, &aDest);
649
650	/* Perform configuration space read */
651	int rc = ich9pciDataReadAddr(pGlobals, &aDest, cb, &rv, VINF_IOM_R3_MMIO_READ);
652
653	if (RT_SUCCESS(rc))
654	{
655	switch (cb)
656	{
657	case 1:
658	(uint8_t)pv = (uint8_t)rv;
659	break;
660	case 2:
661	(uint16_t)pv = (uint16_t)rv;
662	break;
663	case 4:
664	(uint32_t)pv = (uint32_t)rv;
665	break;
666	default:
667	Assert(false);
668	break;
669	}
670	}
671	PCI_UNLOCK(pDevIns);
672
673	return rc;
674	}
675
676	#ifdef IN_RING3
677
678	/*
679	* Include code we share with the other PCI bus implementation.
680	*
681	* Note! No #ifdefs, use instant data booleans/flags/whatever. Goal is to
682	* completely merge these files! File #1 contains code we write, where
683	* as a possible file #2 contains external code if there's any left.
684	*/
685	# define pciR3UnmergedConfigWriteDev ich9pciConfigWriteDev
686	# include "DevPciMerge1.cpp.h"
687
688
689	DECLINLINE(PPDMPCIDEV) ich9pciFindBridge(PDEVPCIBUS pBus, uint8_t iBus)
690	{
691	/* Search for a fitting bridge. */
692	for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
693	{
694	/*
695	* Examine secondary and subordinate bus number.
696	* If the target bus is in the range we pass the request on to the bridge.
697	*/
698	PPDMPCIDEV pBridge = pBus->papBridgesR3[iBridge];
699	AssertMsg(pBridge && pciDevIsPci2PciBridge(pBridge),
700	("Device is not a PCI bridge but on the list of PCI bridges\n"));
701	uint32_t uSecondary = PDMPciDevGetByte(pBridge, VBOX_PCI_SECONDARY_BUS);
702	uint32_t uSubordinate = PDMPciDevGetByte(pBridge, VBOX_PCI_SUBORDINATE_BUS);
703	Log3(("ich9pciFindBridge on bus %p, bridge %d: %d in %d..%d\n", pBus, iBridge, iBus, uSecondary, uSubordinate));
704	if (iBus >= uSecondary && iBus <= uSubordinate)
705	return pBridge;
706	}
707
708	/* Nothing found. */
709	return NULL;
710	}
711
712	static uint32_t ich9pciGetCfg(PPDMPCIDEV pPciDev, int32_t iRegister, int cb)
713	{
714	return pPciDev->Int.s.pfnConfigRead(pPciDev->Int.s.CTX_SUFF(pDevIns), pPciDev, iRegister, cb);
715	}
716
717	static uint8_t ich9pciGetByte(PPDMPCIDEV pPciDev, int32_t iRegister)
718	{
719	return (uint8_t)ich9pciGetCfg(pPciDev, iRegister, 1);
720	}
721
722	static uint16_t ich9pciGetWord(PPDMPCIDEV pPciDev, int32_t iRegister)
723	{
724	return (uint16_t)ich9pciGetCfg(pPciDev, iRegister, 2);
725	}
726
727	static uint32_t ich9pciGetDWord(PPDMPCIDEV pPciDev, int32_t iRegister)
728	{
729	return (uint32_t)ich9pciGetCfg(pPciDev, iRegister, 4);
730	}
731
732	DECLINLINE(uint32_t) ich9pciGetRegionReg(int iRegion)
733	{
734	return iRegion == VBOX_PCI_ROM_SLOT
735	? VBOX_PCI_ROM_ADDRESS : (VBOX_PCI_BASE_ADDRESS_0 + iRegion * 4);
736	}
737
738	#define INVALID_PCI_ADDRESS ~0U
739
740	static int ich9pciUnmapRegion(PPDMPCIDEV pDev, int iRegion)
741	{
742	PCIIORegion* pRegion = &pDev->Int.s.aIORegions[iRegion];
743	int rc = VINF_SUCCESS;
744	PDEVPCIBUS pBus = pDev->Int.s.CTX_SUFF(pBus);
745
746	Assert (pRegion->size != 0);
747
748	if (pRegion->addr != INVALID_PCI_ADDRESS)
749	{
750	if (pRegion->type & PCI_ADDRESS_SPACE_IO)
751	{
752	/* Port IO */
753	rc = PDMDevHlpIOPortDeregister(pDev->Int.s.pDevInsR3, pRegion->addr, pRegion->size);
754	AssertRC(rc);
755	}
756	else
757	{
758	RTGCPHYS GCPhysBase = pRegion->addr;
759	if (pBus->pPciHlpR3->pfnIsMMIOExBase(pBus->pDevInsR3, pDev->Int.s.pDevInsR3, GCPhysBase))
760	{
761	/* unmap it. */
762	rc = pRegion->map_func(pDev->Int.s.pDevInsR3, pDev, iRegion,
763	NIL_RTGCPHYS, pRegion->size, (PCIADDRESSSPACE)(pRegion->type));
764	AssertRC(rc);
765	rc = PDMDevHlpMMIOExUnmap(pDev->Int.s.pDevInsR3, pDev, iRegion, GCPhysBase);
766	}
767	else
768	rc = PDMDevHlpMMIODeregister(pDev->Int.s.pDevInsR3, GCPhysBase, pRegion->size);
769	}
770
771	pRegion->addr = INVALID_PCI_ADDRESS;
772	}
773
774	return rc;
775	}
776
777	static void ich9pciUpdateMappings(PDMPCIDEV* pDev)
778	{
779	uint64_t uLast, uNew;
780
781	int iCmd = ich9pciGetWord(pDev, VBOX_PCI_COMMAND);
782	for (int iRegion = 0; iRegion < VBOX_PCI_NUM_REGIONS; iRegion++)
783	{
784	PCIIORegion* pRegion = &pDev->Int.s.aIORegions[iRegion];
785	uint32_t uConfigReg = ich9pciGetRegionReg(iRegion);
786	int64_t iRegionSize = pRegion->size;
787	int rc;
788
789	if (iRegionSize == 0)
790	continue;
791
792	bool f64Bit = (pRegion->type & ((uint8_t)(PCI_ADDRESS_SPACE_BAR64 \| PCI_ADDRESS_SPACE_IO)))
793	== PCI_ADDRESS_SPACE_BAR64;
794
795	if (pRegion->type & PCI_ADDRESS_SPACE_IO)
796	{
797	/* port IO region */
798	if (iCmd & PCI_COMMAND_IOACCESS)
799	{
800	/* IO access allowed */
801	uNew = ich9pciGetDWord(pDev, uConfigReg);
802	uNew &= ~(iRegionSize - 1);
803	uLast = uNew + iRegionSize - 1;
804	/* only 64K ioports on PC */
805	if (uLast <= uNew \|\| uNew == 0 \|\| uLast >= 0x10000)
806	uNew = INVALID_PCI_ADDRESS;
807	} else
808	uNew = INVALID_PCI_ADDRESS;
809	}
810	else
811	{
812	/* MMIO region */
813	if (iCmd & PCI_COMMAND_MEMACCESS)
814	{
815	uNew = ich9pciGetDWord(pDev, uConfigReg);
816	if (f64Bit)
817	uNew \|= (uint64_t)ich9pciGetDWord(pDev, uConfigReg + 4) << 32;
818
819	/* the ROM slot has a specific enable bit */
820	if (iRegion == PCI_ROM_SLOT && !(uNew & 1))
821	uNew = INVALID_PCI_ADDRESS;
822	else
823	{
824	uNew &= ~(iRegionSize - 1);
825	uLast = uNew + iRegionSize - 1;
826	/* NOTE: we do not support wrapping */
827	/* XXX: as we cannot support really dynamic
828	mappings, we handle specific values as invalid
829	mappings. */
830	/* Unconditionally exclude I/O-APIC/HPET/ROM. Pessimistic, but better than causing a mess. */
831	if (uLast <= uNew \|\| uNew == 0 \|\| (uNew <= UINT32_C(0xffffffff) && uLast >= UINT32_C(0xfec00000)))
832	uNew = INVALID_PCI_ADDRESS;
833	}
834	} else
835	uNew = INVALID_PCI_ADDRESS;
836	}
837	LogRel2(("PCI: config dev %u/%u BAR%i uOld=%#018llx uNew=%#018llx size=%llu\n", pDev->uDevFn >> 3, pDev->uDevFn & 7, iRegion, pRegion->addr, uNew, pRegion->size));
838	/* now do the real mapping */
839	if (uNew != pRegion->addr)
840	{
841	if (pRegion->addr != INVALID_PCI_ADDRESS)
842	ich9pciUnmapRegion(pDev, iRegion);
843
844	pRegion->addr = uNew;
845	if (pRegion->addr != INVALID_PCI_ADDRESS)
846	{
847
848	/* finally, map the region */
849	rc = pRegion->map_func(pDev->Int.s.pDevInsR3, pDev, iRegion,
850	pRegion->addr, pRegion->size,
851	(PCIADDRESSSPACE)(pRegion->type));
852	AssertRC(rc);
853	}
854	}
855
856	if (f64Bit)
857	iRegion++;
858	}
859	}
860
861
862	/* -=-=-=-=-=- PCI Bus Interface Methods (PDMPCIBUSREG) -=-=-=-=-=- */
863
864
865	static DECLCALLBACK(int) ich9pciRegisterMsi(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, PPDMMSIREG pMsiReg)
866	{
867	NOREF(pDevIns);
868	int rc;
869
870	rc = MsiInit(pPciDev, pMsiReg);
871	if (RT_FAILURE(rc))
872	return rc;
873
874	rc = MsixInit(pPciDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pPciHlp), pPciDev, pMsiReg);
875	if (RT_FAILURE(rc))
876	return rc;
877
878	return VINF_SUCCESS;
879	}
880
881
882	/**
883	* @interface_method_impl{PDMPCIBUSREG,pfnIORegionRegisterR3}
884	*/
885	DECLCALLBACK(int) devpciR3CommonIORegionRegister(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iRegion, RTGCPHYS cbRegion,
886	PCIADDRESSSPACE enmType, PFNPCIIOREGIONMAP pfnCallback)
887	{
888	NOREF(pDevIns);
889
890	/*
891	* Validate.
892	*/
893	AssertMsgReturn( enmType == (PCI_ADDRESS_SPACE_MEM \| PCI_ADDRESS_SPACE_BAR32)
894	\|\| enmType == (PCI_ADDRESS_SPACE_MEM_PREFETCH \| PCI_ADDRESS_SPACE_BAR32)
895	\|\| enmType == (PCI_ADDRESS_SPACE_MEM \| PCI_ADDRESS_SPACE_BAR64)
896	\|\| enmType == (PCI_ADDRESS_SPACE_MEM_PREFETCH \| PCI_ADDRESS_SPACE_BAR64)
897	\|\| enmType == PCI_ADDRESS_SPACE_IO
898	,
899	("Invalid enmType=%#x? Or was this a bitmask after all...\n", enmType),
900	VERR_INVALID_PARAMETER);
901	AssertMsgReturn((unsigned)iRegion < VBOX_PCI_NUM_REGIONS,
902	("Invalid iRegion=%d VBOX_PCI_NUM_REGIONS=%d\n", iRegion, VBOX_PCI_NUM_REGIONS),
903	VERR_INVALID_PARAMETER);
904	int iLastSet = ASMBitLastSetU64(cbRegion);
905	AssertMsgReturn( iLastSet != 0
906	&& RT_BIT_64(iLastSet - 1) == cbRegion,
907	("Invalid cbRegion=%RGp iLastSet=%#x (not a power of 2 or 0)\n", cbRegion, iLastSet),
908	VERR_INVALID_PARAMETER);
909
910	Log(("devpciR3CommonIORegionRegister: %s region %d size %RGp type %x\n",
911	pPciDev->pszNameR3, iRegion, cbRegion, enmType));
912
913	/* Make sure that we haven't marked this region as continuation of 64-bit region. */
914	Assert(pPciDev->Int.s.aIORegions[iRegion].type != 0xff);
915
916	/*
917	* Register the I/O region.
918	*/
919	PPCIIOREGION pRegion = &pPciDev->Int.s.aIORegions[iRegion];
920	pRegion->addr = INVALID_PCI_ADDRESS;
921	pRegion->size = cbRegion;
922	pRegion->type = enmType;
923	pRegion->map_func = pfnCallback;
924
925	if ((enmType & PCI_ADDRESS_SPACE_BAR64) != 0)
926	{
927	/* VBOX_PCI_BASE_ADDRESS_5 and VBOX_PCI_ROM_ADDRESS are excluded. */
928	AssertMsgReturn(iRegion < VBOX_PCI_NUM_REGIONS - 2,
929	("Region %d cannot be 64-bit\n", iRegion),
930	VERR_INVALID_PARAMETER);
931	/* Mark next region as continuation of this one. */
932	pPciDev->Int.s.aIORegions[iRegion + 1].type = 0xff;
933	}
934
935	/* Set type in the PCI config space. */
936	AssertCompile(PCI_ADDRESS_SPACE_MEM == 0);
937	AssertCompile(PCI_ADDRESS_SPACE_IO == 1);
938	AssertCompile(PCI_ADDRESS_SPACE_BAR64 == RT_BIT_32(2));
939	AssertCompile(PCI_ADDRESS_SPACE_MEM_PREFETCH == RT_BIT_32(3));
940	uint32_t u32Value = (uint32_t)enmType & (PCI_ADDRESS_SPACE_IO \| PCI_ADDRESS_SPACE_BAR64 \| PCI_ADDRESS_SPACE_MEM_PREFETCH);
941	PCIDevSetDWord(pPciDev, ich9pciGetRegionReg(iRegion), u32Value);
942
943	return VINF_SUCCESS;
944	}
945
946
947	/**
948	* @interface_method_impl{PDMPCIBUSREG,pfnSetConfigCallbacksR3}
949	*/
950	DECLCALLBACK(void) devpciR3CommonSetConfigCallbacks(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
951	PFNPCICONFIGREAD pfnRead, PPFNPCICONFIGREAD ppfnReadOld,
952	PFNPCICONFIGWRITE pfnWrite, PPFNPCICONFIGWRITE ppfnWriteOld)
953	{
954	NOREF(pDevIns);
955
956	if (ppfnReadOld)
957	*ppfnReadOld = pPciDev->Int.s.pfnConfigRead;
958	pPciDev->Int.s.pfnConfigRead = pfnRead;
959
960	if (ppfnWriteOld)
961	*ppfnWriteOld = pPciDev->Int.s.pfnConfigWrite;
962	pPciDev->Int.s.pfnConfigWrite = pfnWrite;
963	}
964
965
966	static int ich9pciR3CommonSaveExec(PDEVPCIBUS pBus, PSSMHANDLE pSSM)
967	{
968	/*
969	* Iterate thru all the devices.
970	*/
971	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
972	{
973	PPDMPCIDEV pDev = pBus->apDevices[i];
974	if (pDev)
975	{
976	/* Device position */
977	SSMR3PutU32(pSSM, i);
978	/* PCI config registers */
979	SSMR3PutMem(pSSM, pDev->abConfig, sizeof(pDev->abConfig));
980
981	/* Device flags */
982	int rc = SSMR3PutU32(pSSM, pDev->Int.s.fFlags);
983	if (RT_FAILURE(rc))
984	return rc;
985
986	/* IRQ pin state */
987	rc = SSMR3PutS32(pSSM, pDev->Int.s.uIrqPinState);
988	if (RT_FAILURE(rc))
989	return rc;
990
991	/* MSI info */
992	rc = SSMR3PutU8(pSSM, pDev->Int.s.u8MsiCapOffset);
993	if (RT_FAILURE(rc))
994	return rc;
995	rc = SSMR3PutU8(pSSM, pDev->Int.s.u8MsiCapSize);
996	if (RT_FAILURE(rc))
997	return rc;
998
999	/* MSI-X info */
1000	rc = SSMR3PutU8(pSSM, pDev->Int.s.u8MsixCapOffset);
1001	if (RT_FAILURE(rc))
1002	return rc;
1003	rc = SSMR3PutU8(pSSM, pDev->Int.s.u8MsixCapSize);
1004	if (RT_FAILURE(rc))
1005	return rc;
1006	/* Save MSI-X page state */
1007	if (pDev->Int.s.u8MsixCapOffset != 0)
1008	{
1009	Assert(pDev->Int.s.pMsixPageR3 != NULL);
1010	SSMR3PutMem(pSSM, pDev->Int.s.pMsixPageR3, 0x1000);
1011	if (RT_FAILURE(rc))
1012	return rc;
1013	}
1014	}
1015	}
1016	return SSMR3PutU32(pSSM, UINT32_MAX); /* terminator */
1017	}
1018
1019	static DECLCALLBACK(int) ich9pciR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
1020	{
1021	PDEVPCIROOT pThis = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
1022
1023	/*
1024	* Bus state data.
1025	*/
1026	SSMR3PutU32(pSSM, pThis->uConfigReg);
1027
1028	/*
1029	* Save IRQ states.
1030	*/
1031	for (unsigned i = 0; i < RT_ELEMENTS(pThis->auPciApicIrqLevels); i++)
1032	SSMR3PutU32(pSSM, pThis->auPciApicIrqLevels[i]);
1033
1034	SSMR3PutU32(pSSM, UINT32_MAX); /* separator */
1035
1036	return ich9pciR3CommonSaveExec(&pThis->PciBus, pSSM);
1037	}
1038
1039
1040	static DECLCALLBACK(int) ich9pcibridgeR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
1041	{
1042	PDEVPCIBUS pThis = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
1043	return ich9pciR3CommonSaveExec(pThis, pSSM);
1044	}
1045
1046
1047	static DECLCALLBACK(void) ich9pcibridgeConfigWrite(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice, uint32_t u32Address, uint32_t u32Value, unsigned cb)
1048	{
1049	PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
1050
1051	LogFlowFunc((": pDevIns=%p iBus=%d iDevice=%d u32Address=%u u32Value=%u cb=%d\n", pDevIns, iBus, iDevice, u32Address, u32Value, cb));
1052
1053	/* If the current bus is not the target bus search for the bus which contains the device. */
1054	if (iBus != PDMPciDevGetByte(&pBus->PciDev, VBOX_PCI_SECONDARY_BUS))
1055	{
1056	PPDMPCIDEV pBridgeDevice = ich9pciFindBridge(pBus, iBus);
1057	if (pBridgeDevice)
1058	{
1059	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigWrite);
1060	pBridgeDevice->Int.s.pfnBridgeConfigWrite(pBridgeDevice->Int.s.CTX_SUFF(pDevIns), iBus, iDevice,
1061	u32Address, u32Value, cb);
1062	}
1063	}
1064	else
1065	{
1066	/* This is the target bus, pass the write to the device. */
1067	PPDMPCIDEV pPciDev = pBus->apDevices[iDevice];
1068	if (pPciDev)
1069	{
1070	Log(("%s: %s: addr=%02x val=%08x len=%d\n", __FUNCTION__, pPciDev->pszNameR3, u32Address, u32Value, cb));
1071	pPciDev->Int.s.pfnConfigWrite(pPciDev->Int.s.CTX_SUFF(pDevIns), pPciDev, u32Address, u32Value, cb);
1072	}
1073	}
1074	}
1075
1076	static DECLCALLBACK(uint32_t) ich9pcibridgeConfigRead(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice, uint32_t u32Address, unsigned cb)
1077	{
1078	PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
1079	uint32_t u32Value;
1080
1081	LogFlowFunc((": pDevIns=%p iBus=%d iDevice=%d u32Address=%u cb=%d\n", pDevIns, iBus, iDevice, u32Address, cb));
1082
1083	/* If the current bus is not the target bus search for the bus which contains the device. */
1084	if (iBus != PDMPciDevGetByte(&pBus->PciDev, VBOX_PCI_SECONDARY_BUS))
1085	{
1086	PPDMPCIDEV pBridgeDevice = ich9pciFindBridge(pBus, iBus);
1087	if (pBridgeDevice)
1088	{
1089	AssertPtr( pBridgeDevice->Int.s.pfnBridgeConfigRead);
1090	u32Value = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->Int.s.CTX_SUFF(pDevIns), iBus, iDevice,
1091	u32Address, cb);
1092	}
1093	else
1094	ich9pciNoMem(&u32Value, 4);
1095	}
1096	else
1097	{
1098	/* This is the target bus, pass the read to the device. */
1099	PPDMPCIDEV pPciDev = pBus->apDevices[iDevice];
1100	if (pPciDev)
1101	{
1102	u32Value = pPciDev->Int.s.pfnConfigRead(pPciDev->Int.s.CTX_SUFF(pDevIns), pPciDev, u32Address, cb);
1103	Log(("%s: %s: u32Address=%02x u32Value=%08x cb=%d\n", __FUNCTION__, pPciDev->pszNameR3, u32Address, u32Value, cb));
1104	}
1105	else
1106	ich9pciNoMem(&u32Value, 4);
1107	}
1108
1109	return u32Value;
1110	}
1111
1112
1113	/**
1114	* Common routine for restoring the config registers of a PCI device.
1115	*
1116	* @param pDev The PCI device.
1117	* @param pbSrcConfig The configuration register values to be loaded.
1118	* @param fIsBridge Whether this is a bridge device or not.
1119	*/
1120	void devpciR3CommonRestoreConfig(PPDMPCIDEV pDev, uint8_t const *pbSrcConfig, bool fIsBridge)
1121	{
1122	/*
1123	* This table defines the fields for normal devices and bridge devices, and
1124	* the order in which they need to be restored.
1125	*/
1126	static const struct PciField
1127	{
1128	uint8_t off;
1129	uint8_t cb;
1130	uint8_t fWritable;
1131	uint8_t fBridge;
1132	const char *pszName;
1133	} s_aFields[] =
1134	{
1135	/* off,cb,fW,fB, pszName */
1136	{ 0x00, 2, 0, 3, "VENDOR_ID" },
1137	{ 0x02, 2, 0, 3, "DEVICE_ID" },
1138	{ 0x06, 2, 1, 3, "STATUS" },
1139	{ 0x08, 1, 0, 3, "REVISION_ID" },
1140	{ 0x09, 1, 0, 3, "CLASS_PROG" },
1141	{ 0x0a, 1, 0, 3, "CLASS_SUB" },
1142	{ 0x0b, 1, 0, 3, "CLASS_BASE" },
1143	{ 0x0c, 1, 1, 3, "CACHE_LINE_SIZE" },
1144	{ 0x0d, 1, 1, 3, "LATENCY_TIMER" },
1145	{ 0x0e, 1, 0, 3, "HEADER_TYPE" },
1146	{ 0x0f, 1, 1, 3, "BIST" },
1147	{ 0x10, 4, 1, 3, "BASE_ADDRESS_0" },
1148	{ 0x14, 4, 1, 3, "BASE_ADDRESS_1" },
1149	{ 0x18, 4, 1, 1, "BASE_ADDRESS_2" },
1150	{ 0x18, 1, 1, 2, "PRIMARY_BUS" }, // fWritable = ??
1151	{ 0x19, 1, 1, 2, "SECONDARY_BUS" }, // fWritable = ??
1152	{ 0x1a, 1, 1, 2, "SUBORDINATE_BUS" }, // fWritable = ??
1153	{ 0x1b, 1, 1, 2, "SEC_LATENCY_TIMER" }, // fWritable = ??
1154	{ 0x1c, 4, 1, 1, "BASE_ADDRESS_3" },
1155	{ 0x1c, 1, 1, 2, "IO_BASE" }, // fWritable = ??
1156	{ 0x1d, 1, 1, 2, "IO_LIMIT" }, // fWritable = ??
1157	{ 0x1e, 2, 1, 2, "SEC_STATUS" }, // fWritable = ??
1158	{ 0x20, 4, 1, 1, "BASE_ADDRESS_4" },
1159	{ 0x20, 2, 1, 2, "MEMORY_BASE" }, // fWritable = ??
1160	{ 0x22, 2, 1, 2, "MEMORY_LIMIT" }, // fWritable = ??
1161	{ 0x24, 4, 1, 1, "BASE_ADDRESS_5" },
1162	{ 0x24, 2, 1, 2, "PREF_MEMORY_BASE" }, // fWritable = ??
1163	{ 0x26, 2, 1, 2, "PREF_MEMORY_LIMIT" }, // fWritable = ??
1164	{ 0x28, 4, 1, 1, "CARDBUS_CIS" }, // fWritable = ??
1165	{ 0x28, 4, 1, 2, "PREF_BASE_UPPER32" }, // fWritable = ??
1166	{ 0x2c, 2, 0, 1, "SUBSYSTEM_VENDOR_ID" },// fWritable = !?
1167	{ 0x2c, 4, 1, 2, "PREF_LIMIT_UPPER32" },// fWritable = ??
1168	{ 0x2e, 2, 0, 1, "SUBSYSTEM_ID" }, // fWritable = !?
1169	{ 0x30, 4, 1, 1, "ROM_ADDRESS" }, // fWritable = ?!
1170	{ 0x30, 2, 1, 2, "IO_BASE_UPPER16" }, // fWritable = ?!
1171	{ 0x32, 2, 1, 2, "IO_LIMIT_UPPER16" }, // fWritable = ?!
1172	{ 0x34, 4, 0, 3, "CAPABILITY_LIST" }, // fWritable = !? cb=!?
1173	{ 0x38, 4, 1, 1, "RESERVED_38" }, // ???
1174	{ 0x38, 4, 1, 2, "ROM_ADDRESS_BR" }, // fWritable = !? cb=!? fBridge=!?
1175	{ 0x3c, 1, 1, 3, "INTERRUPT_LINE" }, // fBridge=??
1176	{ 0x3d, 1, 0, 3, "INTERRUPT_PIN" }, // fBridge=??
1177	{ 0x3e, 1, 0, 1, "MIN_GNT" },
1178	{ 0x3e, 2, 1, 2, "BRIDGE_CONTROL" }, // fWritable = !?
1179	{ 0x3f, 1, 0, 1, "MAX_LAT" },
1180	/* The COMMAND register must come last as it requires the ADDRESS
1181	registers to be restored before we pretent to change it from 0 to
1182	whatever value the guest assigned it. */
1183	{ 0x04, 2, 1, 3, "COMMAND" },
1184	};
1185
1186	#ifdef RT_STRICT
1187	/* Check that we've got full register coverage. */
1188	uint32_t bmDevice[0x40 / 32];
1189	uint32_t bmBridge[0x40 / 32];
1190	RT_ZERO(bmDevice);
1191	RT_ZERO(bmBridge);
1192	for (uint32_t i = 0; i < RT_ELEMENTS(s_aFields); i++)
1193	{
1194	uint8_t off = s_aFields[i].off;
1195	uint8_t cb = s_aFields[i].cb;
1196	uint8_t f = s_aFields[i].fBridge;
1197	while (cb-- > 0)
1198	{
1199	if (f & 1) AssertMsg(!ASMBitTest(bmDevice, off), ("%#x\n", off));
1200	if (f & 2) AssertMsg(!ASMBitTest(bmBridge, off), ("%#x\n", off));
1201	if (f & 1) ASMBitSet(bmDevice, off);
1202	if (f & 2) ASMBitSet(bmBridge, off);
1203	off++;
1204	}
1205	}
1206	for (uint32_t off = 0; off < 0x40; off++)
1207	{
1208	AssertMsg(ASMBitTest(bmDevice, off), ("%#x\n", off));
1209	AssertMsg(ASMBitTest(bmBridge, off), ("%#x\n", off));
1210	}
1211	#endif
1212
1213	/*
1214	* Loop thru the fields covering the 64 bytes of standard registers.
1215	*/
1216	uint8_t const fBridge = fIsBridge ? 2 : 1;
1217	Assert(!pciDevIsPassthrough(pDev));
1218	uint8_t *pbDstConfig = &pDev->abConfig[0];
1219
1220	for (uint32_t i = 0; i < RT_ELEMENTS(s_aFields); i++)
1221	if (s_aFields[i].fBridge & fBridge)
1222	{
1223	uint8_t const off = s_aFields[i].off;
1224	uint8_t const cb = s_aFields[i].cb;
1225	uint32_t u32Src;
1226	uint32_t u32Dst;
1227	switch (cb)
1228	{
1229	case 1:
1230	u32Src = pbSrcConfig[off];
1231	u32Dst = pbDstConfig[off];
1232	break;
1233	case 2:
1234	u32Src = (uint16_t const )&pbSrcConfig[off];
1235	u32Dst = (uint16_t const )&pbDstConfig[off];
1236	break;
1237	case 4:
1238	u32Src = (uint32_t const )&pbSrcConfig[off];
1239	u32Dst = (uint32_t const )&pbDstConfig[off];
1240	break;
1241	default:
1242	AssertFailed();
1243	continue;
1244	}
1245
1246	if ( u32Src != u32Dst
1247	\|\| off == VBOX_PCI_COMMAND)
1248	{
1249	if (u32Src != u32Dst)
1250	{
1251	if (!s_aFields[i].fWritable)
1252	LogRel(("PCI: %8s/%u: %2u-bit field %s: %x -> %x - !READ ONLY!\n",
1253	pDev->pszNameR3, pDev->Int.s.CTX_SUFF(pDevIns)->iInstance, cb*8, s_aFields[i].pszName, u32Dst, u32Src));
1254	else
1255	LogRel(("PCI: %8s/%u: %2u-bit field %s: %x -> %x\n",
1256	pDev->pszNameR3, pDev->Int.s.CTX_SUFF(pDevIns)->iInstance, cb*8, s_aFields[i].pszName, u32Dst, u32Src));
1257	}
1258	if (off == VBOX_PCI_COMMAND)
1259	PCIDevSetCommand(pDev, 0); /* For remapping, see ich9pciR3CommonLoadExec. */
1260	pDev->Int.s.pfnConfigWrite(pDev->Int.s.CTX_SUFF(pDevIns), pDev, off, u32Src, cb);
1261	}
1262	}
1263
1264	/*
1265	* The device dependent registers.
1266	*
1267	* We will not use ConfigWrite here as we have no clue about the size
1268	* of the registers, so the device is responsible for correctly
1269	* restoring functionality governed by these registers.
1270	*/
1271	for (uint32_t off = 0x40; off < sizeof(pDev->abConfig); off++)
1272	if (pbDstConfig[off] != pbSrcConfig[off])
1273	{
1274	LogRel(("PCI: %8s/%u: register %02x: %02x -> %02x\n",
1275	pDev->pszNameR3, pDev->Int.s.CTX_SUFF(pDevIns)->iInstance, off, pbDstConfig[off], pbSrcConfig[off])); /** @todo make this Log() later. */
1276	pbDstConfig[off] = pbSrcConfig[off];
1277	}
1278	}
1279
1280	/**
1281	* Common worker for ich9pciR3LoadExec and ich9pcibridgeR3LoadExec.
1282	*
1283	* @returns VBox status code.
1284	* @param pBus The bus which data is being loaded.
1285	* @param pSSM The saved state handle.
1286	* @param uVersion The data version.
1287	* @param uPass The pass.
1288	*/
1289	static DECLCALLBACK(int) ich9pciR3CommonLoadExec(PDEVPCIBUS pBus, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1290	{
1291	uint32_t u32;
1292	uint32_t i;
1293	int rc;
1294
1295	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
1296	if (uVersion != VBOX_ICH9PCI_SAVED_STATE_VERSION_CURRENT)
1297	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1298
1299	/*
1300	* Iterate thru all the devices and write 0 to the COMMAND register so
1301	* that all the memory is unmapped before we start restoring the saved
1302	* mapping locations.
1303	*
1304	* The register value is restored afterwards so we can do proper
1305	* LogRels in devpciR3CommonRestoreConfig.
1306	*/
1307	for (i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
1308	{
1309	PPDMPCIDEV pDev = pBus->apDevices[i];
1310	if (pDev)
1311	{
1312	uint16_t u16 = PCIDevGetCommand(pDev);
1313	pDev->Int.s.pfnConfigWrite(pDev->Int.s.CTX_SUFF(pDevIns), pDev, VBOX_PCI_COMMAND, 0, 2);
1314	PCIDevSetCommand(pDev, u16);
1315	Assert(PCIDevGetCommand(pDev) == u16);
1316	}
1317	}
1318
1319	void *pvMsixPage = RTMemTmpAllocZ(0x1000);
1320	AssertReturn(pvMsixPage, VERR_NO_TMP_MEMORY);
1321
1322	/*
1323	* Iterate all the devices.
1324	*/
1325	for (i = 0;; i++)
1326	{
1327	PPDMPCIDEV pDev;
1328	PDMPCIDEV DevTmp;
1329
1330	/* index / terminator */
1331	rc = SSMR3GetU32(pSSM, &u32);
1332	if (RT_FAILURE(rc))
1333	break;
1334	if (u32 == (uint32_t)~0)
1335	break;
1336	AssertMsgBreak(u32 < RT_ELEMENTS(pBus->apDevices) && u32 >= i, ("u32=%#x i=%#x\n", u32, i));
1337
1338	/* skip forward to the device checking that no new devices are present. */
1339	for (; i < u32; i++)
1340	{
1341	pDev = pBus->apDevices[i];
1342	if (pDev)
1343	{
1344	LogRel(("PCI: New device in slot %#x, %s (vendor=%#06x device=%#06x)\n", i, pDev->pszNameR3,
1345	PCIDevGetVendorId(pDev), PCIDevGetDeviceId(pDev)));
1346	if (SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT)
1347	{
1348	rc = SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("New device in slot %#x, %s (vendor=%#06x device=%#06x)"),
1349	i, pDev->pszNameR3, PCIDevGetVendorId(pDev), PCIDevGetDeviceId(pDev));
1350	break;
1351	}
1352	}
1353	}
1354	if (RT_FAILURE(rc))
1355	break;
1356
1357	/* get the data */
1358	DevTmp.Int.s.fFlags = 0;
1359	DevTmp.Int.s.u8MsiCapOffset = 0;
1360	DevTmp.Int.s.u8MsiCapSize = 0;
1361	DevTmp.Int.s.u8MsixCapOffset = 0;
1362	DevTmp.Int.s.u8MsixCapSize = 0;
1363	DevTmp.Int.s.uIrqPinState = ~0; /* Invalid value in case we have an older saved state to force a state change in pciSetIrq. */
1364	SSMR3GetMem(pSSM, DevTmp.abConfig, sizeof(DevTmp.abConfig));
1365
1366	SSMR3GetU32(pSSM, &DevTmp.Int.s.fFlags);
1367	SSMR3GetS32(pSSM, &DevTmp.Int.s.uIrqPinState);
1368	SSMR3GetU8(pSSM, &DevTmp.Int.s.u8MsiCapOffset);
1369	SSMR3GetU8(pSSM, &DevTmp.Int.s.u8MsiCapSize);
1370	SSMR3GetU8(pSSM, &DevTmp.Int.s.u8MsixCapOffset);
1371	rc = SSMR3GetU8(pSSM, &DevTmp.Int.s.u8MsixCapSize);
1372	if (RT_FAILURE(rc))
1373	break;
1374
1375	/* Load MSI-X page state */
1376	if (DevTmp.Int.s.u8MsixCapOffset != 0)
1377	{
1378	Assert(pvMsixPage != NULL);
1379	rc = SSMR3GetMem(pSSM, pvMsixPage, 0x1000);
1380	if (RT_FAILURE(rc))
1381	break;
1382	}
1383
1384	/* check that it's still around. */
1385	pDev = pBus->apDevices[i];
1386	if (!pDev)
1387	{
1388	LogRel(("PCI: Device in slot %#x has been removed! vendor=%#06x device=%#06x\n", i,
1389	PCIDevGetVendorId(&DevTmp), PCIDevGetDeviceId(&DevTmp)));
1390	if (SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT)
1391	{
1392	rc = SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Device in slot %#x has been removed! vendor=%#06x device=%#06x"),
1393	i, PCIDevGetVendorId(&DevTmp), PCIDevGetDeviceId(&DevTmp));
1394	break;
1395	}
1396	continue;
1397	}
1398
1399	/* match the vendor id assuming that this will never be changed. */
1400	if (PCIDevGetVendorId(&DevTmp) != PCIDevGetVendorId(pDev))
1401	{
1402	rc = SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Device in slot %#x (%s) vendor id mismatch! saved=%.4Rhxs current=%.4Rhxs"),
1403	i, pDev->pszNameR3, PCIDevGetVendorId(&DevTmp), PCIDevGetVendorId(pDev));
1404	break;
1405	}
1406
1407	/* commit the loaded device config. */
1408	Assert(!pciDevIsPassthrough(pDev));
1409	devpciR3CommonRestoreConfig(pDev, &DevTmp.abConfig[0], false ); /** @todo fix bridge fun! */
1410
1411	pDev->Int.s.uIrqPinState = DevTmp.Int.s.uIrqPinState;
1412	pDev->Int.s.u8MsiCapOffset = DevTmp.Int.s.u8MsiCapOffset;
1413	pDev->Int.s.u8MsiCapSize = DevTmp.Int.s.u8MsiCapSize;
1414	pDev->Int.s.u8MsixCapOffset = DevTmp.Int.s.u8MsixCapOffset;
1415	pDev->Int.s.u8MsixCapSize = DevTmp.Int.s.u8MsixCapSize;
1416	if (DevTmp.Int.s.u8MsixCapSize != 0)
1417	{
1418	Assert(pDev->Int.s.pMsixPageR3 != NULL);
1419	memcpy(pDev->Int.s.pMsixPageR3, pvMsixPage, 0x1000);
1420	}
1421	}
1422
1423	RTMemTmpFree(pvMsixPage);
1424
1425	return rc;
1426	}
1427
1428	static DECLCALLBACK(int) ich9pciR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1429	{
1430	PDEVPCIROOT pThis = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
1431	PDEVPCIBUS pBus = &pThis->PciBus;
1432	uint32_t u32;
1433	int rc;
1434
1435	/* We ignore this version as there's no saved state with it anyway */
1436	if (uVersion == VBOX_ICH9PCI_SAVED_STATE_VERSION_NOMSI)
1437	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1438	if (uVersion > VBOX_ICH9PCI_SAVED_STATE_VERSION_MSI)
1439	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1440
1441	/*
1442	* Bus state data.
1443	*/
1444	SSMR3GetU32(pSSM, &pThis->uConfigReg);
1445
1446	/*
1447	* Load IRQ states.
1448	*/
1449	for (unsigned i = 0; i < RT_ELEMENTS(pThis->auPciApicIrqLevels); i++)
1450	SSMR3GetU32(pSSM, (uint32_t*)&pThis->auPciApicIrqLevels[i]);
1451
1452	/* separator */
1453	rc = SSMR3GetU32(pSSM, &u32);
1454	if (RT_FAILURE(rc))
1455	return rc;
1456	if (u32 != (uint32_t)~0)
1457	AssertMsgFailedReturn(("u32=%#x\n", u32), rc);
1458
1459	return ich9pciR3CommonLoadExec(pBus, pSSM, uVersion, uPass);
1460	}
1461
1462	static DECLCALLBACK(int) ich9pcibridgeR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1463	{
1464	PDEVPCIBUS pThis = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
1465	if (uVersion > VBOX_ICH9PCI_SAVED_STATE_VERSION_MSI)
1466	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1467	return ich9pciR3CommonLoadExec(pThis, pSSM, uVersion, uPass);
1468	}
1469
1470
1471	/*
1472	* Perform imeediate read of configuration space register.
1473	* Cannot be rescheduled, as already in R3.
1474	*/
1475	static uint32_t ich9pciConfigRead(PDEVPCIROOT pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t len)
1476	{
1477	PciAddress aPciAddr;
1478	aPciAddr.iBus = uBus;
1479	aPciAddr.iDeviceFunc = uDevFn;
1480	aPciAddr.iRegister = addr;
1481
1482	uint32_t u32Val;
1483	int rc = ich9pciDataReadAddr(pGlobals, &aPciAddr, len, &u32Val, VERR_INTERNAL_ERROR);
1484	AssertRC(rc);
1485
1486	return u32Val;
1487	}
1488
1489
1490	/*
1491	* Perform imeediate write to configuration space register.
1492	* Cannot be rescheduled, as already in R3.
1493	*/
1494	static void ich9pciConfigWrite(PDEVPCIROOT pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t val, uint32_t len)
1495	{
1496	PciAddress aPciAddr;
1497	aPciAddr.iBus = uBus;
1498	aPciAddr.iDeviceFunc = uDevFn;
1499	aPciAddr.iRegister = addr;
1500
1501	int rc = ich9pciDataWriteAddr(pGlobals, &aPciAddr, val, len, VERR_INTERNAL_ERROR);
1502	AssertRC(rc);
1503	}
1504
1505
1506	static void ich9pciSetRegionAddress(PDEVPCIROOT pGlobals, uint8_t uBus, uint8_t uDevFn, int iRegion, uint64_t addr)
1507	{
1508	uint32_t uReg = ich9pciGetRegionReg(iRegion);
1509
1510	/* Read memory type first. */
1511	uint8_t uResourceType = ich9pciConfigRead(pGlobals, uBus, uDevFn, uReg, 1);
1512	bool f64Bit = (uResourceType & ((uint8_t)(PCI_ADDRESS_SPACE_BAR64 \| PCI_ADDRESS_SPACE_IO)))
1513	== PCI_ADDRESS_SPACE_BAR64;
1514
1515	Log(("Set region address: %02x:%02x.%d region %d address=%RX64%s\n",
1516	uBus, uDevFn >> 3, uDevFn & 7, iRegion, addr, f64Bit ? " (64-bit)" : ""));
1517
1518	/* Write address of the device. */
1519	ich9pciConfigWrite(pGlobals, uBus, uDevFn, uReg, (uint32_t)addr, 4);
1520	if (f64Bit)
1521	ich9pciConfigWrite(pGlobals, uBus, uDevFn, uReg + 4, (uint32_t)(addr >> 32), 4);
1522	}
1523
1524
1525	static void ich9pciBiosInitBridge(PDEVPCIROOT pGlobals, uint8_t uBus, uint8_t uDevFn)
1526	{
1527	Log(("BIOS init bridge: %02x::%02x.%d\n", uBus, uDevFn >> 3, uDevFn & 7));
1528
1529	/*
1530	* The I/O range for the bridge must be aligned to a 4KB boundary.
1531	* This does not change anything really as the access to the device is not going
1532	* through the bridge but we want to be compliant to the spec.
1533	*/
1534	if ((pGlobals->uPciBiosIo % 4096) != 0)
1535	{
1536	pGlobals->uPciBiosIo = RT_ALIGN_32(pGlobals->uPciBiosIo, 4*1024);
1537	Log(("%s: Aligned I/O start address. New address %#x\n", __FUNCTION__, pGlobals->uPciBiosIo));
1538	}
1539	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_IO_BASE, (pGlobals->uPciBiosIo >> 8) & 0xf0, 1);
1540
1541	/* The MMIO range for the bridge must be aligned to a 1MB boundary. */
1542	if ((pGlobals->uPciBiosMmio % (1024 * 1024)) != 0)
1543	{
1544	pGlobals->uPciBiosMmio = RT_ALIGN_32(pGlobals->uPciBiosMmio, 1024*1024);
1545	Log(("%s: Aligned MMIO start address. New address %#x\n", __FUNCTION__, pGlobals->uPciBiosMmio));
1546	}
1547	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_MEMORY_BASE, (pGlobals->uPciBiosMmio >> 16) & UINT32_C(0xffff0), 2);
1548
1549	/* Save values to compare later to. */
1550	uint32_t u32IoAddressBase = pGlobals->uPciBiosIo;
1551	uint32_t u32MMIOAddressBase = pGlobals->uPciBiosMmio;
1552	uint8_t uBridgeBus = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_SECONDARY_BUS, 1);
1553
1554	/* Init devices behind the bridge and possibly other bridges as well. */
1555	for (int iDev = 0; iDev <= 255; iDev++)
1556	ich9pciBiosInitDevice(pGlobals, uBridgeBus, iDev);
1557
1558	/*
1559	* Set I/O limit register. If there is no device with I/O space behind the bridge
1560	* we set a lower value than in the base register.
1561	* The result with a real bridge is that no I/O transactions are passed to the secondary
1562	* interface. Again this doesn't really matter here but we want to be compliant to the spec.
1563	*/
1564	if ((u32IoAddressBase != pGlobals->uPciBiosIo) && ((pGlobals->uPciBiosIo % 4096) != 0))
1565	{
1566	/* The upper boundary must be one byte less than a 4KB boundary. */
1567	pGlobals->uPciBiosIo = RT_ALIGN_32(pGlobals->uPciBiosIo, 4*1024);
1568	}
1569
1570	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_IO_LIMIT, ((pGlobals->uPciBiosIo >> 8) & 0xf0) - 1, 1);
1571
1572	/* Same with the MMIO limit register but with 1MB boundary here. */
1573	if ((u32MMIOAddressBase != pGlobals->uPciBiosMmio) && ((pGlobals->uPciBiosMmio % (1024 * 1024)) != 0))
1574	{
1575	/* The upper boundary must be one byte less than a 1MB boundary. */
1576	pGlobals->uPciBiosMmio = RT_ALIGN_32(pGlobals->uPciBiosMmio, 1024*1024);
1577	}
1578	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_MEMORY_LIMIT, ((pGlobals->uPciBiosMmio >> 16) & UINT32_C(0xfff0)) - 1, 2);
1579
1580	/*
1581	* Set the prefetch base and limit registers. We currently have no device with a prefetchable region
1582	* which may be behind a bridge. That's why it is unconditionally disabled here atm by writing a higher value into
1583	* the base register than in the limit register.
1584	*/
1585	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_MEMORY_BASE, 0xfff0, 2);
1586	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_MEMORY_LIMIT, 0x0, 2);
1587	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_BASE_UPPER32, 0x00, 4);
1588	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_LIMIT_UPPER32, 0x00, 4);
1589	}
1590
1591	static void ich9pciBiosInitDevice(PDEVPCIROOT pGlobals, uint8_t uBus, uint8_t uDevFn)
1592	{
1593	uint16_t uDevClass, uVendor, uDevice;
1594	uint8_t uCmd;
1595
1596	uDevClass = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_CLASS_DEVICE, 2);
1597	uVendor = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_VENDOR_ID, 2);
1598	uDevice = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_DEVICE_ID, 2);
1599
1600	/* If device is present */
1601	if (uVendor == 0xffff)
1602	return;
1603
1604	Log(("BIOS init device: %02x:%02x.%d\n", uBus, uDevFn >> 3, uDevFn & 7));
1605
1606	switch (uDevClass)
1607	{
1608	case 0x0101:
1609	/* IDE controller */
1610	ich9pciConfigWrite(pGlobals, uBus, uDevFn, 0x40, 0x8000, 2); /* enable IDE0 */
1611	ich9pciConfigWrite(pGlobals, uBus, uDevFn, 0x42, 0x8000, 2); /* enable IDE1 */
1612	goto default_map;
1613	break;
1614	case 0x0300:
1615	/* VGA controller */
1616
1617	/* NB: Default Bochs VGA LFB address is 0xE0000000. Old guest
1618	* software may break if the framebuffer isn't mapped there.
1619	*/
1620
1621	/*
1622	* Legacy VGA I/O ports are implicitly decoded by a VGA class device. But
1623	* only the framebuffer (i.e., a memory region) is explicitly registered via
1624	* ich9pciSetRegionAddress, so don't forget to enable I/O decoding.
1625	*/
1626	uCmd = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_COMMAND, 1);
1627	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_COMMAND,
1628	uCmd \| PCI_COMMAND_IOACCESS,
1629	1);
1630	goto default_map;
1631	break;
1632	case 0x0604:
1633	/* PCI-to-PCI bridge. */
1634	AssertMsg(pGlobals->uPciBiosBus < 255, ("Too many bridges on the bus\n"));
1635	ich9pciBiosInitBridge(pGlobals, uBus, uDevFn);
1636	break;
1637	default:
1638	default_map:
1639	{
1640	/* default memory mappings */
1641	bool fActiveMemRegion = false;
1642	bool fActiveIORegion = false;
1643	/*
1644	* We ignore ROM region here.
1645	*/
1646	for (int iRegion = 0; iRegion < VBOX_PCI_NUM_REGIONS - 1; iRegion++)
1647	{
1648	uint32_t u32Address = ich9pciGetRegionReg(iRegion);
1649
1650	/* Calculate size - we write all 1s into the BAR, and then evaluate which bits
1651	are cleared. */
1652	uint8_t u8ResourceType = ich9pciConfigRead(pGlobals, uBus, uDevFn, u32Address, 1);
1653
1654	bool f64Bit = (u8ResourceType & ((uint8_t)(PCI_ADDRESS_SPACE_BAR64 \| PCI_ADDRESS_SPACE_IO)))
1655	== PCI_ADDRESS_SPACE_BAR64;
1656	bool fIsPio = ((u8ResourceType & PCI_COMMAND_IOACCESS) == PCI_COMMAND_IOACCESS);
1657	uint64_t cbRegSize64 = 0;
1658
1659	if (f64Bit)
1660	{
1661	ich9pciConfigWrite(pGlobals, uBus, uDevFn, u32Address, UINT32_C(0xffffffff), 4);
1662	ich9pciConfigWrite(pGlobals, uBus, uDevFn, u32Address+4, UINT32_C(0xffffffff), 4);
1663	cbRegSize64 = ich9pciConfigRead(pGlobals, uBus, uDevFn, u32Address, 4);
1664	cbRegSize64 \|= ((uint64_t)ich9pciConfigRead(pGlobals, uBus, uDevFn, u32Address+4, 4) << 32);
1665	cbRegSize64 &= ~UINT64_C(0x0f);
1666	cbRegSize64 = (~cbRegSize64) + 1;
1667
1668	/* No 64-bit PIO regions possible. */
1669	#ifndef DEBUG_bird /* EFI triggers this for DevAHCI. */
1670	AssertMsg((u8ResourceType & PCI_COMMAND_IOACCESS) == 0, ("type=%#x rgn=%d\n", u8ResourceType, iRegion));
1671	#endif
1672	}
1673	else
1674	{
1675	uint32_t cbRegSize32;
1676	ich9pciConfigWrite(pGlobals, uBus, uDevFn, u32Address, UINT32_C(0xffffffff), 4);
1677	cbRegSize32 = ich9pciConfigRead(pGlobals, uBus, uDevFn, u32Address, 4);
1678
1679	/* Clear resource information depending on resource type. */
1680	if (fIsPio) /* PIO */
1681	cbRegSize32 &= ~UINT32_C(0x01);
1682	else /* MMIO */
1683	cbRegSize32 &= ~UINT32_C(0x0f);
1684
1685	/*
1686	* Invert all bits and add 1 to get size of the region.
1687	* (From PCI implementation note)
1688	*/
1689	if (fIsPio && (cbRegSize32 & UINT32_C(0xffff0000)) == 0)
1690	cbRegSize32 = (~(cbRegSize32 \| UINT32_C(0xffff0000))) + 1;
1691	else
1692	cbRegSize32 = (~cbRegSize32) + 1;
1693
1694	cbRegSize64 = cbRegSize32;
1695	}
1696	Log2(("%s: Size of region %u for device %d on bus %d is %lld\n", __FUNCTION__, iRegion, uDevFn, uBus, cbRegSize64));
1697
1698	if (cbRegSize64)
1699	{
1700	/* Try 32-bit base first. */
1701	uint32_t* paddr = fIsPio ? &pGlobals->uPciBiosIo : &pGlobals->uPciBiosMmio;
1702	uint64_t uNew = *paddr;
1703	/* Align starting address to region size. */
1704	uNew = (uNew + cbRegSize64 - 1) & ~(cbRegSize64 - 1);
1705	if (fIsPio)
1706	uNew &= UINT32_C(0xffff);
1707	/* Unconditionally exclude I/O-APIC/HPET/ROM. Pessimistic, but better than causing a mess. */
1708	if ( !uNew
1709	\|\| (uNew <= UINT32_C(0xffffffff) && uNew + cbRegSize64 - 1 >= UINT32_C(0xfec00000))
1710	\|\| uNew >= _4G)
1711	{
1712	if (f64Bit)
1713	{
1714	/* Map a 64-bit region above 4GB. */
1715	Assert(!fIsPio);
1716	uNew = pGlobals->uPciBiosMmio64;
1717	/* Align starting address to region size. */
1718	uNew = (uNew + cbRegSize64 - 1) & ~(cbRegSize64 - 1);
1719	LogFunc(("Start address of 64-bit MMIO region %u/%u is %#llx\n", iRegion, iRegion + 1, uNew));
1720	ich9pciSetRegionAddress(pGlobals, uBus, uDevFn, iRegion, uNew);
1721	fActiveMemRegion = true;
1722	pGlobals->uPciBiosMmio64 = uNew + cbRegSize64;
1723	Log2Func(("New 64-bit address is %#llx\n", pGlobals->uPciBiosMmio64));
1724	}
1725	else
1726	{
1727	LogRel(("PCI: no space left for BAR%u of device %u/%u/%u (vendor=%#06x device=%#06x)\n",
1728	iRegion, uBus, uDevFn >> 3, uDevFn & 7, uVendor, uDevice)); /** @todo make this a VM start failure later. */
1729	/* Undo the mapping mess caused by the size probing. */
1730	ich9pciConfigWrite(pGlobals, uBus, uDevFn, u32Address, UINT32_C(0), 4);
1731	}
1732	}
1733	else
1734	{
1735	LogFunc(("Start address of %s region %u is %#x\n", (fIsPio ? "I/O" : "MMIO"), iRegion, uNew));
1736	ich9pciSetRegionAddress(pGlobals, uBus, uDevFn, iRegion, uNew);
1737	if (fIsPio)
1738	fActiveIORegion = true;
1739	else
1740	fActiveMemRegion = true;
1741	*paddr = uNew + cbRegSize64;
1742	Log2Func(("New 32-bit address is %#x\n", *paddr));
1743	}
1744
1745	if (f64Bit)
1746	iRegion++; /* skip next region */
1747	}
1748	}
1749
1750	/* Update the command word appropriately. */
1751	uCmd = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_COMMAND, 2);
1752	if (fActiveMemRegion)
1753	uCmd \|= PCI_COMMAND_MEMACCESS; /* Enable MMIO access. */
1754	if (fActiveIORegion)
1755	uCmd \|= PCI_COMMAND_IOACCESS; /* Enable I/O space access. */
1756	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_COMMAND, uCmd, 2);
1757	break;
1758	}
1759	}
1760
1761	/* map the interrupt */
1762	uint32_t iPin = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_INTERRUPT_PIN, 1);
1763	if (iPin != 0)
1764	{
1765	iPin--;
1766
1767	if (uBus != 0)
1768	{
1769	/* Find bus this device attached to. */
1770	PDEVPCIBUS pBus = &pGlobals->PciBus;
1771	while (1)
1772	{
1773	PPDMPCIDEV pBridge = ich9pciFindBridge(pBus, uBus);
1774	if (!pBridge)
1775	{
1776	Assert(false);
1777	break;
1778	}
1779	if (uBus == PDMPciDevGetByte(pBridge, VBOX_PCI_SECONDARY_BUS))
1780	{
1781	/* OK, found bus this device attached to. */
1782	break;
1783	}
1784	pBus = PDMINS_2_DATA(pBridge->Int.s.CTX_SUFF(pDevIns), PDEVPCIBUS);
1785	}
1786
1787	/* We need to go up to the host bus to see which irq pin this
1788	* device will use there. See logic in ich9pcibridgeSetIrq().
1789	*/
1790	while (pBus->iBus != 0)
1791	{
1792	/* Get the pin the device would assert on the bridge. */
1793	iPin = ((pBus->PciDev.uDevFn >> 3) + iPin) & 3;
1794	pBus = pBus->PciDev.Int.s.pBusR3;
1795	};
1796	}
1797
1798	int iIrq = aPciIrqs[ich9pciSlotGetPirq(uBus, uDevFn, iPin)];
1799	Log(("Using pin %d and IRQ %d for device %02x:%02x.%d\n",
1800	iPin, iIrq, uBus, uDevFn>>3, uDevFn&7));
1801	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_INTERRUPT_LINE, iIrq, 1);
1802	}
1803	}
1804
1805	/**
1806	* Initializes bridges registers used for routing.
1807	*
1808	* @returns nothing.
1809	* @param pGlobals Global device instance data used to generate unique bus numbers.
1810	* @param pBus The PCI bus to initialize.
1811	* @param uBusPrimary The primary bus number the bus is connected to.
1812	* @param uBusSecondary The secondary bus number, i.e. the bus number behind the bridge.
1813	*/
1814	static void ich9pciInitBridgeTopology(PDEVPCIROOT pGlobals, PDEVPCIBUS pBus, unsigned uBusPrimary,
1815	unsigned uBusSecondary)
1816	{
1817	PPDMPCIDEV pBridgeDev = &pBus->PciDev;
1818
1819	/* Set only if we are not on the root bus, it has no primary bus attached. */
1820	if (uBusSecondary != 0)
1821	{
1822	PCIDevSetByte(pBridgeDev, VBOX_PCI_PRIMARY_BUS, uBusPrimary);
1823	PCIDevSetByte(pBridgeDev, VBOX_PCI_SECONDARY_BUS, uBusSecondary);
1824	}
1825
1826	for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
1827	{
1828	PPDMPCIDEV pBridge = pBus->papBridgesR3[iBridge];
1829	AssertMsg(pBridge && pciDevIsPci2PciBridge(pBridge),
1830	("Device is not a PCI bridge but on the list of PCI bridges\n"));
1831	PDEVPCIBUS pChildBus = PDMINS_2_DATA(pBridge->Int.s.CTX_SUFF(pDevIns), PDEVPCIBUS);
1832	pGlobals->uPciBiosBus++;
1833	ich9pciInitBridgeTopology(pGlobals, pChildBus, uBusSecondary, pGlobals->uPciBiosBus);
1834	}
1835	PCIDevSetByte(pBridgeDev, VBOX_PCI_SUBORDINATE_BUS, pGlobals->uPciBiosBus);
1836	Log2(("ich9pciInitBridgeTopology: for bus %p: primary=%d secondary=%d subordinate=%d\n",
1837	pBus,
1838	PDMPciDevGetByte(pBridgeDev, VBOX_PCI_PRIMARY_BUS),
1839	PDMPciDevGetByte(pBridgeDev, VBOX_PCI_SECONDARY_BUS),
1840	PDMPciDevGetByte(pBridgeDev, VBOX_PCI_SUBORDINATE_BUS)
1841	));
1842	}
1843
1844
1845	static DECLCALLBACK(int) ich9pciFakePCIBIOS(PPDMDEVINS pDevIns)
1846	{
1847	PDEVPCIROOT pGlobals = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
1848	PVM pVM = PDMDevHlpGetVM(pDevIns);
1849	uint32_t const cbBelow4GB = MMR3PhysGetRamSizeBelow4GB(pVM);
1850	uint64_t const cbAbove4GB = MMR3PhysGetRamSizeAbove4GB(pVM);
1851
1852	/*
1853	* Set the start addresses.
1854	*/
1855	pGlobals->uPciBiosBus = 0;
1856	pGlobals->uPciBiosIo = 0xd000;
1857	pGlobals->uPciBiosMmio = cbBelow4GB;
1858	pGlobals->uPciBiosMmio64 = cbAbove4GB + _4G;
1859
1860	/* NB: Assume that if MMIO range is enabled, it is at the bottom of the memory hole. */
1861	if (pGlobals->u64PciConfigMMioAddress)
1862	{
1863	AssertRelease(pGlobals->u64PciConfigMMioAddress >= cbBelow4GB);
1864	pGlobals->uPciBiosMmio = pGlobals->u64PciConfigMMioAddress + pGlobals->u64PciConfigMMioLength;
1865	}
1866	Log(("cbBelow4GB: %lX, uPciBiosMmio: %lX, cbAbove4GB: %llX\n", cbBelow4GB, pGlobals->uPciBiosMmio, cbAbove4GB));
1867
1868	/*
1869	* Assign bridge topology, for further routing to work.
1870	*/
1871	PDEVPCIBUS pBus = &pGlobals->PciBus;
1872	ich9pciInitBridgeTopology(pGlobals, pBus, 0, 0);
1873
1874	/*
1875	* Init the devices.
1876	*/
1877	for (int i = 0; i < 256; i++)
1878	ich9pciBiosInitDevice(pGlobals, 0, i);
1879
1880	return VINF_SUCCESS;
1881	}
1882
1883
1884	/**
1885	* @callback_method_impl{PFNPCICONFIGREAD, Default config space read callback.}
1886	*/
1887	DECLCALLBACK(uint32_t) devpciR3CommonDefaultConfigRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress, unsigned cb)
1888	{
1889	NOREF(pDevIns);
1890
1891	uint32_t uValue;
1892	if (uAddress + cb <= 256)
1893	{
1894	switch (cb)
1895	{
1896	case 1:
1897	uValue = PDMPciDevGetByte(pPciDev, uAddress);
1898	break;
1899	case 2:
1900	uValue = PDMPciDevGetWord(pPciDev, uAddress);
1901	break;
1902	case 4:
1903	uValue = PDMPciDevGetDWord(pPciDev, uAddress);
1904	break;
1905	default:
1906	AssertFailed();
1907	uValue = 0;
1908	break;
1909	}
1910
1911	#ifdef LOG_ENABLED
1912	if ( pciDevIsMsiCapable(pPciDev)
1913	&& uAddress - (uint32_t)pPciDev->Int.s.u8MsiCapOffset < (uint32_t)pPciDev->Int.s.u8MsiCapSize )
1914	Log2(("devpciR3CommonDefaultConfigRead: MSI CAP: %#x LB %u -> %#x\n", uAddress - (uint32_t)pPciDev->Int.s.u8MsiCapOffset, cb, uValue));
1915	else if ( pciDevIsMsixCapable(pPciDev)
1916	&& uAddress - (uint32_t)pPciDev->Int.s.u8MsixCapOffset < (uint32_t)pPciDev->Int.s.u8MsixCapSize)
1917	Log2(("devpciR3CommonDefaultConfigRead: MSI-X CAP: %#x LB %u -> %#x\n", uAddress - (uint32_t)pPciDev->Int.s.u8MsiCapOffset, cb, uValue));
1918	#endif
1919	}
1920	else
1921	{
1922	if (uAddress + cb < 4096)
1923	LogRel(("PCI: %8s/%u: Read from extended register %d fallen back to generic code\n",
1924	pPciDev->pszNameR3, pPciDev->Int.s.CTX_SUFF(pDevIns)->iInstance, uAddress));
1925	else
1926	AssertFailed();
1927	uValue = 0;
1928	}
1929	return uValue;
1930	}
1931
1932
1933	DECLINLINE(void) ich9pciWriteBarByte(PPDMPCIDEV pPciDev, uint32_t iRegion, uint32_t off, uint8_t bVal)
1934	{
1935	PCIIORegion *pRegion = &pPciDev->Int.s.aIORegions[iRegion];
1936	Log3(("ich9pciWriteBarByte: region=%d off=%d val=%#x size=%#llx\n", iRegion, off, bVal, pRegion->size));
1937	Assert(off <= 3);
1938
1939	/* Check if we're writing to upper part of 64-bit BAR. */
1940	if (pRegion->type == 0xff)
1941	{
1942	AssertLogRelReturnVoid(iRegion > 0 && iRegion < VBOX_PCI_ROM_SLOT);
1943	pRegion--;
1944	iRegion--;
1945	off += 4;
1946	Assert(pRegion->type & PCI_ADDRESS_SPACE_BAR64);
1947	}
1948
1949	/* Ignore zero sized regions (they don't exist). */
1950	if (pRegion->size != 0)
1951	{
1952	uint32_t uAddr = ich9pciGetRegionReg(iRegion) + off;
1953	Assert((pRegion->size & (pRegion->size - 1)) == 0); /* Region size must be power of two. */
1954	uint8_t bMask = ( (pRegion->size - 1) >> (off * 8) ) & 0xff;
1955	if (off == 0)
1956	bMask \|= (pRegion->type & PCI_ADDRESS_SPACE_IO)
1957	? (1 << 2) - 1 /* 2 lowest bits for IO region */ :
1958	(1 << 4) - 1 /* 4 lowest bits for memory region, also ROM enable bit for ROM region */;
1959
1960	uint8_t bOld = PDMPciDevGetByte(pPciDev, uAddr) & bMask;
1961	bVal = (bOld & bMask) \| (bVal & ~bMask);
1962
1963	Log3(("ich9pciWriteBarByte: %x changed to %x\n", bOld, bVal));
1964
1965	PCIDevSetByte(pPciDev, uAddr, bVal);
1966	}
1967	}
1968
1969
1970	/**
1971	* @callback_method_impl{PFNPCICONFIGWRITE,
1972	* Default config space write callback.}
1973	*
1974	* See paragraph 7.5 of PCI Express specification (p. 349) for
1975	* definition of registers and their writability policy.
1976	*/
1977	static DECLCALLBACK(void) ich9pciConfigWriteDev(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
1978	uint32_t uAddress, uint32_t u32Value, unsigned cb)
1979	{
1980	NOREF(pDevIns);
1981	Assert(cb <= 4);
1982
1983	if (uAddress + cb <= 256)
1984	{
1985	/*
1986	* MSI and MSI-X capabilites needs to be handled separately.
1987	*/
1988	if ( pciDevIsMsiCapable(pPciDev)
1989	&& uAddress - (uint32_t)pPciDev->Int.s.u8MsiCapOffset < (uint32_t)pPciDev->Int.s.u8MsiCapSize)
1990	MsiPciConfigWrite(pPciDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pDevIns),
1991	pPciDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pPciHlp),
1992	pPciDev, uAddress, u32Value, cb);
1993	else if ( pciDevIsMsixCapable(pPciDev)
1994	&& uAddress - (uint32_t)pPciDev->Int.s.u8MsixCapOffset < (uint32_t)pPciDev->Int.s.u8MsixCapSize)
1995	MsixPciConfigWrite(pPciDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pDevIns),
1996	pPciDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pPciHlp),
1997	pPciDev, uAddress, u32Value, cb);
1998	else
1999	{
2000	/*
2001	* Handle the writes byte-by-byte to catch all possible cases.
2002	*
2003	* Note! Real hardware may not necessarily handle non-dword writes like
2004	* we do here and even produce erratic behavior. We don't (yet)
2005	* try emulate that.
2006	*/
2007	bool fUpdateMappings = false;
2008	bool fP2PBridge = false;
2009	uint8_t bHeaderType = ich9pciGetByte(pPciDev, VBOX_PCI_HEADER_TYPE);
2010	while (cb-- > 0)
2011	{
2012	/*
2013	* Check writability first.
2014	*/
2015	bool fWritable = false;
2016	switch (bHeaderType)
2017	{
2018	case 0x00: /* normal device */
2019	case 0x80: /* multi-function device */
2020	switch (uAddress)
2021	{
2022	/* Read-only registers. */
2023	case VBOX_PCI_VENDOR_ID:
2024	case VBOX_PCI_VENDOR_ID+1:
2025	case VBOX_PCI_DEVICE_ID:
2026	case VBOX_PCI_DEVICE_ID+1:
2027	case VBOX_PCI_REVISION_ID:
2028	case VBOX_PCI_CLASS_PROG:
2029	case VBOX_PCI_CLASS_SUB:
2030	case VBOX_PCI_CLASS_BASE:
2031	case VBOX_PCI_HEADER_TYPE:
2032	case VBOX_PCI_SUBSYSTEM_VENDOR_ID:
2033	case VBOX_PCI_SUBSYSTEM_VENDOR_ID+1:
2034	case VBOX_PCI_SUBSYSTEM_ID:
2035	case VBOX_PCI_SUBSYSTEM_ID+1:
2036	case VBOX_PCI_ROM_ADDRESS:
2037	case VBOX_PCI_ROM_ADDRESS+1:
2038	case VBOX_PCI_ROM_ADDRESS+2:
2039	case VBOX_PCI_ROM_ADDRESS+3:
2040	case VBOX_PCI_CAPABILITY_LIST:
2041	case VBOX_PCI_INTERRUPT_PIN:
2042	fWritable = false;
2043	break;
2044	/* Other registers can be written. */
2045	default:
2046	fWritable = true;
2047	break;
2048	}
2049	break;
2050	case 0x01: /* PCI-PCI bridge */
2051	fP2PBridge = true;
2052	switch (uAddress)
2053	{
2054	/* Read-only registers. */
2055	case VBOX_PCI_VENDOR_ID:
2056	case VBOX_PCI_VENDOR_ID+1:
2057	case VBOX_PCI_DEVICE_ID:
2058	case VBOX_PCI_DEVICE_ID+1:
2059	case VBOX_PCI_REVISION_ID:
2060	case VBOX_PCI_CLASS_PROG:
2061	case VBOX_PCI_CLASS_SUB:
2062	case VBOX_PCI_CLASS_BASE:
2063	case VBOX_PCI_HEADER_TYPE:
2064	case VBOX_PCI_ROM_ADDRESS_BR:
2065	case VBOX_PCI_ROM_ADDRESS_BR+1:
2066	case VBOX_PCI_ROM_ADDRESS_BR+2:
2067	case VBOX_PCI_ROM_ADDRESS_BR+3:
2068	case VBOX_PCI_INTERRUPT_PIN:
2069	fWritable = false;
2070	break;
2071	/* Other registers can be written. */
2072	default:
2073	fWritable = true;
2074	break;
2075	}
2076	break;
2077	default:
2078	AssertMsgFailed(("Unknown header type %#x\n", bHeaderType));
2079	fWritable = false;
2080	break;
2081	}
2082
2083	bool fRom = false;
2084	uint8_t bVal = (uint8_t)u32Value;
2085	switch (uAddress)
2086	{
2087	case VBOX_PCI_COMMAND: /* Command register, bits 0-7. */
2088	if (fWritable)
2089	{
2090	PCIDevSetByte(pPciDev, uAddress, bVal);
2091	fUpdateMappings = true; /** @todo r=bird: Probably not necessary to update mappings on VBOX_PCI_COMMAND changes for bridges? */
2092	}
2093	break;
2094
2095	case VBOX_PCI_COMMAND+1: /* Command register, bits 8-15. */
2096	if (fWritable)
2097	{
2098	/* don't change reserved bits (11-15) */
2099	bVal &= ~UINT32_C(0xf8);
2100	PCIDevSetByte(pPciDev, uAddress, bVal);
2101	fUpdateMappings = true;
2102	}
2103	break;
2104
2105	case VBOX_PCI_STATUS: /* Status register, bits 0-7. */
2106	/* don't change read-only bits => actually all lower bits are read-only */
2107	bVal &= ~UINT32_C(0xff);
2108	/* status register, low part: clear bits by writing a '1' to the corresponding bit */
2109	pPciDev->abConfig[uAddress] &= ~bVal;
2110	break;
2111
2112	case VBOX_PCI_STATUS+1: /* Status register, bits 8-15. */
2113	/* don't change read-only bits */
2114	bVal &= ~UINT32_C(0x06);
2115	/* status register, high part: clear bits by writing a '1' to the corresponding bit */
2116	pPciDev->abConfig[uAddress] &= ~bVal;
2117	break;
2118
2119	case VBOX_PCI_ROM_ADDRESS: case VBOX_PCI_ROM_ADDRESS +1: case VBOX_PCI_ROM_ADDRESS +2: case VBOX_PCI_ROM_ADDRESS +3:
2120	fRom = true;
2121	case VBOX_PCI_BASE_ADDRESS_0: case VBOX_PCI_BASE_ADDRESS_0+1: case VBOX_PCI_BASE_ADDRESS_0+2: case VBOX_PCI_BASE_ADDRESS_0+3:
2122	case VBOX_PCI_BASE_ADDRESS_1: case VBOX_PCI_BASE_ADDRESS_1+1: case VBOX_PCI_BASE_ADDRESS_1+2: case VBOX_PCI_BASE_ADDRESS_1+3:
2123	case VBOX_PCI_BASE_ADDRESS_2: case VBOX_PCI_BASE_ADDRESS_2+1: case VBOX_PCI_BASE_ADDRESS_2+2: case VBOX_PCI_BASE_ADDRESS_2+3:
2124	case VBOX_PCI_BASE_ADDRESS_3: case VBOX_PCI_BASE_ADDRESS_3+1: case VBOX_PCI_BASE_ADDRESS_3+2: case VBOX_PCI_BASE_ADDRESS_3+3:
2125	case VBOX_PCI_BASE_ADDRESS_4: case VBOX_PCI_BASE_ADDRESS_4+1: case VBOX_PCI_BASE_ADDRESS_4+2: case VBOX_PCI_BASE_ADDRESS_4+3:
2126	case VBOX_PCI_BASE_ADDRESS_5: case VBOX_PCI_BASE_ADDRESS_5+1: case VBOX_PCI_BASE_ADDRESS_5+2: case VBOX_PCI_BASE_ADDRESS_5+3:
2127	/* We check that, as same PCI register numbers as BARs may mean different registers for bridges */
2128	if (!fP2PBridge)
2129	{
2130	uint32_t iRegion = fRom ? VBOX_PCI_ROM_SLOT : (uAddress - VBOX_PCI_BASE_ADDRESS_0) >> 2;
2131	ich9pciWriteBarByte(pPciDev, iRegion, uAddress & 0x3, bVal);
2132	fUpdateMappings = true;
2133	break;
2134	}
2135	/* fall thru (bridge) */
2136	default:
2137	if (fWritable)
2138	PCIDevSetByte(pPciDev, uAddress, bVal);
2139	break;
2140	}
2141	uAddress++;
2142	u32Value >>= 8;
2143	}
2144
2145	/*
2146	* Update the region mappings if anything changed related to them (command, BARs, ROM).
2147	*/
2148	if (fUpdateMappings)
2149	ich9pciUpdateMappings(pPciDev);
2150	}
2151	}
2152	else if (uAddress + cb <= 4096)
2153	LogRel(("PCI: %8s/%u: Write to extended register %d fallen back to generic code\n",
2154	pPciDev->pszNameR3, pPciDev->Int.s.CTX_SUFF(pDevIns)->iInstance, uAddress));
2155	else
2156	AssertMsgFailed(("Write after end of PCI config space\n"));
2157	}
2158
2159
2160	/* -=-=-=-=-=- Debug Info Handlers -=-=-=-=-=- */
2161
2162	/**
2163	* Indents an info line.
2164	* @param pHlp The info helper.
2165	* @param iIndentLvl The desired indentation level.
2166	*/
2167	static void devpciR3InfoIndent(PCDBGFINFOHLP pHlp, unsigned iIndentLvl)
2168	{
2169	for (unsigned i = 0; i < iIndentLvl; i++)
2170	pHlp->pfnPrintf(pHlp, " ");
2171	}
2172
2173
2174	/**
2175	* Recursive worker for devpciR3InfoPci.
2176	*
2177	* @param pBus The bus to show info for.
2178	* @param pHlp The info helpers.
2179	* @param iIndentLvl The indentation level.
2180	* @param fRegisters Whether to show device registers or not.
2181	*/
2182	static void devpciR3InfoPciBus(PDEVPCIBUS pBus, PCDBGFINFOHLP pHlp, unsigned iIndentLvl, bool fRegisters)
2183	{
2184	/** @todo r=bird: Not sure if we should actually do PCI config space
2185	* callbacks from this code!! */
2186
2187	for (uint32_t iDev = 0; iDev < RT_ELEMENTS(pBus->apDevices); iDev++)
2188	{
2189	PPDMPCIDEV pPciDev = pBus->apDevices[iDev];
2190	if (pPciDev != NULL)
2191	{
2192	devpciR3InfoIndent(pHlp, iIndentLvl);
2193
2194	/*
2195	* For passthrough devices MSI/MSI-X mostly reflects the way interrupts delivered to the guest,
2196	* as host driver handles real devices interrupts.
2197	*/
2198	pHlp->pfnPrintf(pHlp, "%02x:%02x:%02x %s%s: %04x-%04x %s%s%s",
2199	pBus->iBus, (iDev >> 3) & 0xff, iDev & 0x7,
2200	pPciDev->pszNameR3,
2201	pciDevIsPassthrough(pPciDev) ? " (PASSTHROUGH)" : "",
2202	ich9pciGetWord(pPciDev, VBOX_PCI_VENDOR_ID), ich9pciGetWord(pPciDev, VBOX_PCI_DEVICE_ID),
2203	pBus->fTypeIch9 ? "ICH9" : pBus->fTypePiix3 ? "PIIX3" : "?type?",
2204	pciDevIsMsiCapable(pPciDev) ? " MSI" : "",
2205	pciDevIsMsixCapable(pPciDev) ? " MSI-X" : ""
2206	);
2207	if (ich9pciGetByte(pPciDev, VBOX_PCI_INTERRUPT_PIN) != 0)
2208	{
2209	pHlp->pfnPrintf(pHlp, " IRQ%d", ich9pciGetByte(pPciDev, VBOX_PCI_INTERRUPT_LINE));
2210	pHlp->pfnPrintf(pHlp, " (INTA#->IRQ%d)", 0x10 + ich9pciSlot2ApicIrq(iDev >> 3, 0));
2211	}
2212	pHlp->pfnPrintf(pHlp, "\n");
2213
2214	if (pciDevIsMsiCapable(pPciDev) \|\| pciDevIsMsixCapable(pPciDev))
2215	{
2216	devpciR3InfoIndent(pHlp, iIndentLvl + 2);
2217
2218	if (pciDevIsMsiCapable(pPciDev))
2219	pHlp->pfnPrintf(pHlp, "MSI:%s ", MsiIsEnabled(pPciDev) ? "on" : "off");
2220
2221	if (pciDevIsMsixCapable(pPciDev))
2222	pHlp->pfnPrintf(pHlp, "MSI-X:%s ", MsixIsEnabled(pPciDev) ? "on" : "off");
2223
2224	pHlp->pfnPrintf(pHlp, "\n");
2225	}
2226
2227	uint16_t iCmd = ich9pciGetWord(pPciDev, VBOX_PCI_COMMAND);
2228	if ((iCmd & (VBOX_PCI_COMMAND_IO \| VBOX_PCI_COMMAND_MEMORY)) != 0)
2229	{
2230	for (unsigned iRegion = 0; iRegion < VBOX_PCI_NUM_REGIONS; iRegion++)
2231	{
2232	PCIIORegion const *pRegion = &pPciDev->Int.s.aIORegions[iRegion];
2233	uint64_t const cbRegion = pRegion->size;
2234
2235	if (cbRegion == 0)
2236	continue;
2237
2238	uint32_t uAddr = ich9pciGetDWord(pPciDev, ich9pciGetRegionReg(iRegion));
2239	const char * pszDesc;
2240	char szDescBuf[128];
2241
2242	bool f64Bit = (pRegion->type & ((uint8_t)(PCI_ADDRESS_SPACE_BAR64 \| PCI_ADDRESS_SPACE_IO)))
2243	== PCI_ADDRESS_SPACE_BAR64;
2244	if (pRegion->type & PCI_ADDRESS_SPACE_IO)
2245	{
2246	pszDesc = "IO";
2247	uAddr &= ~0x3;
2248	}
2249	else
2250	{
2251	RTStrPrintf(szDescBuf, sizeof(szDescBuf), "MMIO%s%s",
2252	f64Bit ? "64" : "32",
2253	pRegion->type & PCI_ADDRESS_SPACE_MEM_PREFETCH ? " PREFETCH" : "");
2254	pszDesc = szDescBuf;
2255	uAddr &= ~0xf;
2256	}
2257
2258	devpciR3InfoIndent(pHlp, iIndentLvl + 2);
2259	pHlp->pfnPrintf(pHlp, "%s region #%u: ", pszDesc, iRegion);
2260	if (f64Bit)
2261	{
2262	uint32_t u32High = ich9pciGetDWord(pPciDev, ich9pciGetRegionReg(iRegion+1));
2263	uint64_t u64Addr = RT_MAKE_U64(uAddr, u32High);
2264	pHlp->pfnPrintf(pHlp, "%RX64..%RX64\n", u64Addr, u64Addr + cbRegion);
2265	iRegion++;
2266	}
2267	else
2268	pHlp->pfnPrintf(pHlp, "%x..%x\n", uAddr, uAddr + (uint32_t)cbRegion);
2269	}
2270	}
2271
2272	devpciR3InfoIndent(pHlp, iIndentLvl + 2);
2273	uint16_t iStatus = ich9pciGetWord(pPciDev, VBOX_PCI_STATUS);
2274	pHlp->pfnPrintf(pHlp, "Command: %04X, Status: %04x\n", iCmd, iStatus);
2275	devpciR3InfoIndent(pHlp, iIndentLvl + 2);
2276	pHlp->pfnPrintf(pHlp, "Bus master: %s\n", iCmd & VBOX_PCI_COMMAND_MASTER ? "Yes" : "No");
2277
2278	if (fRegisters)
2279	{
2280	devpciR3InfoIndent(pHlp, iIndentLvl + 2);
2281	pHlp->pfnPrintf(pHlp, "PCI registers:\n");
2282	for (unsigned iReg = 0; iReg < 0x100; )
2283	{
2284	unsigned iPerLine = 0x10;
2285	Assert(0x100 % iPerLine == 0);
2286	devpciR3InfoIndent(pHlp, iIndentLvl + 3);
2287
2288	while (iPerLine-- > 0)
2289	pHlp->pfnPrintf(pHlp, "%02x ", ich9pciGetByte(pPciDev, iReg++));
2290	pHlp->pfnPrintf(pHlp, "\n");
2291	}
2292	}
2293	}
2294	}
2295
2296	if (pBus->cBridges > 0)
2297	{
2298	devpciR3InfoIndent(pHlp, iIndentLvl);
2299	pHlp->pfnPrintf(pHlp, "Registered %d bridges, subordinate buses info follows\n", pBus->cBridges);
2300	for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
2301	{
2302	PDEVPCIBUS pBusSub = PDMINS_2_DATA(pBus->papBridgesR3[iBridge]->Int.s.CTX_SUFF(pDevIns), PDEVPCIBUS);
2303	devpciR3InfoPciBus(pBusSub, pHlp, iIndentLvl + 1, fRegisters);
2304	}
2305	}
2306	}
2307
2308
2309	/**
2310	* @callback_method_impl{FNDBGFHANDLERDEV, 'pci'}
2311	*/
2312	DECLCALLBACK(void) devpciR3InfoPci(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
2313	{
2314	PDEVPCIBUS pBus = DEVINS_2_DEVPCIBUS(pDevIns);
2315
2316	if (pszArgs == NULL \|\| !*pszArgs \|\| !strcmp(pszArgs, "basic"))
2317	devpciR3InfoPciBus(pBus, pHlp, 0 /iIndentLvl/, false /fRegisters/);
2318	else if (!strcmp(pszArgs, "verbose"))
2319	devpciR3InfoPciBus(pBus, pHlp, 0 /iIndentLvl/, true /fRegisters/);
2320	else
2321	pHlp->pfnPrintf(pHlp, "Invalid argument. Recognized arguments are 'basic', 'verbose'.\n");
2322	}
2323
2324
2325	/**
2326	* @callback_method_impl{FNDBGFHANDLERDEV, 'pciirq'}
2327	*/
2328	DECLCALLBACK(void) devpciR3InfoPciIrq(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
2329	{
2330	PDEVPCIROOT pGlobals = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
2331	NOREF(pszArgs);
2332
2333	pHlp->pfnPrintf(pHlp, "PCI I/O APIC IRQ levels:\n");
2334	for (int i = 0; i < DEVPCI_APIC_IRQ_PINS; ++i)
2335	pHlp->pfnPrintf(pHlp, " IRQ%02d: %u\n", 0x10 + i, pGlobals->auPciApicIrqLevels[i]);
2336	}
2337
2338
2339
2340	static DECLCALLBACK(int) ich9pciConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
2341	{
2342	RT_NOREF1(iInstance);
2343	Assert(iInstance == 0);
2344	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
2345
2346	/*
2347	* Validate and read configuration.
2348	*/
2349	if (!CFGMR3AreValuesValid(pCfg,
2350	"IOAPIC\0"
2351	"GCEnabled\0"
2352	"R0Enabled\0"
2353	"McfgBase\0"
2354	"McfgLength\0"
2355	))
2356	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
2357
2358	/* query whether we got an IOAPIC */
2359	bool fUseIoApic;
2360	int rc = CFGMR3QueryBoolDef(pCfg, "IOAPIC", &fUseIoApic, false);
2361	if (RT_FAILURE(rc))
2362	return PDMDEV_SET_ERROR(pDevIns, rc,
2363	N_("Configuration error: Failed to query boolean value \"IOAPIC\""));
2364
2365	/* check if RC code is enabled. */
2366	bool fGCEnabled;
2367	rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
2368	if (RT_FAILURE(rc))
2369	return PDMDEV_SET_ERROR(pDevIns, rc,
2370	N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
2371	/* check if R0 code is enabled. */
2372	bool fR0Enabled;
2373	rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
2374	if (RT_FAILURE(rc))
2375	return PDMDEV_SET_ERROR(pDevIns, rc,
2376	N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
2377
2378	Log(("PCI: fUseIoApic=%RTbool fGCEnabled=%RTbool fR0Enabled=%RTbool\n", fUseIoApic, fGCEnabled, fR0Enabled));
2379
2380	/*
2381	* Init data.
2382	*/
2383	PDEVPCIROOT pGlobals = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
2384	PDEVPCIBUS pBus = &pGlobals->PciBus;
2385	/* Zero out everything */
2386	memset(pGlobals, 0, sizeof(*pGlobals));
2387	/* And fill values */
2388	if (!fUseIoApic)
2389	return PDMDEV_SET_ERROR(pDevIns, rc,
2390	N_("Must use IO-APIC with ICH9 chipset"));
2391	rc = CFGMR3QueryU64Def(pCfg, "McfgBase", &pGlobals->u64PciConfigMMioAddress, 0);
2392	if (RT_FAILURE(rc))
2393	return PDMDEV_SET_ERROR(pDevIns, rc,
2394	N_("Configuration error: Failed to read \"McfgBase\""));
2395	rc = CFGMR3QueryU64Def(pCfg, "McfgLength", &pGlobals->u64PciConfigMMioLength, 0);
2396	if (RT_FAILURE(rc))
2397	return PDMDEV_SET_ERROR(pDevIns, rc,
2398	N_("Configuration error: Failed to read \"McfgLength\""));
2399
2400	pGlobals->fUseIoApic = fUseIoApic;
2401	pGlobals->pDevInsR3 = pDevIns;
2402	pGlobals->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2403	pGlobals->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2404
2405	pGlobals->PciBus.fTypePiix3 = false;
2406	pGlobals->PciBus.fTypeIch9 = true;
2407	pGlobals->PciBus.fPureBridge = false;
2408	pGlobals->PciBus.pDevInsR3 = pDevIns;
2409	pGlobals->PciBus.pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2410	pGlobals->PciBus.pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2411	pGlobals->PciBus.papBridgesR3 = (PPDMPCIDEV )PDMDevHlpMMHeapAllocZ(pDevIns, sizeof(PPDMPCIDEV) RT_ELEMENTS(pGlobals->PciBus.apDevices));
2412	AssertLogRelReturn(pGlobals->PciBus.papBridgesR3, VERR_NO_MEMORY);
2413
2414	/*
2415	* Register bus
2416	*/
2417	PDMPCIBUSREG PciBusReg;
2418	PciBusReg.u32Version = PDM_PCIBUSREG_VERSION;
2419	PciBusReg.pfnRegisterR3 = pciR3MergedRegister;
2420	PciBusReg.pfnRegisterMsiR3 = ich9pciRegisterMsi;
2421	PciBusReg.pfnIORegionRegisterR3 = devpciR3CommonIORegionRegister;
2422	PciBusReg.pfnSetConfigCallbacksR3 = devpciR3CommonSetConfigCallbacks;
2423	PciBusReg.pfnSetIrqR3 = ich9pciSetIrq;
2424	PciBusReg.pfnFakePCIBIOSR3 = ich9pciFakePCIBIOS;
2425	PciBusReg.pszSetIrqRC = fGCEnabled ? "ich9pciSetIrq" : NULL;
2426	PciBusReg.pszSetIrqR0 = fR0Enabled ? "ich9pciSetIrq" : NULL;
2427	rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBus->pPciHlpR3);
2428	if (RT_FAILURE(rc))
2429	return PDMDEV_SET_ERROR(pDevIns, rc,
2430	N_("Failed to register ourselves as a PCI Bus"));
2431	if (pBus->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
2432	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
2433	N_("PCI helper version mismatch; got %#x expected %#x"),
2434	pBus->pPciHlpR3->u32Version, PDM_PCIHLPR3_VERSION);
2435
2436	pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
2437	pBus->pPciHlpR0 = pBus->pPciHlpR3->pfnGetR0Helpers(pDevIns);
2438
2439	/*
2440	* Fill in PCI configs and add them to the bus.
2441	*/
2442	/** @todo Disabled for now because this causes error messages with Linux guests.
2443	* The guest loads the x38_edac device which tries to map a memory region
2444	* using an address given at place 0x48 - 0x4f in the PCi config space.
2445	* This fails. because we don't register such a region.
2446	*/
2447	#if 0
2448	/* Host bridge device */
2449	PCIDevSetVendorId( &pBus->PciDev, 0x8086); /* Intel */
2450	PCIDevSetDeviceId( &pBus->PciDev, 0x29e0); /* Desktop */
2451	PCIDevSetRevisionId(&pBus->PciDev, 0x01); /* rev. 01 */
2452	PCIDevSetClassBase( &pBus->PciDev, 0x06); /* bridge */
2453	PCIDevSetClassSub( &pBus->PciDev, 0x00); /* Host/PCI bridge */
2454	PCIDevSetClassProg( &pBus->PciDev, 0x00); /* Host/PCI bridge */
2455	PCIDevSetHeaderType(&pBus->PciDev, 0x00); /* bridge */
2456	PCIDevSetWord(&pBus->PciDev, VBOX_PCI_SEC_STATUS, 0x0280); /* secondary status */
2457
2458	pBus->PciDev.pDevIns = pDevIns;
2459	/* We register Host<->PCI controller on the bus */
2460	ich9pciRegisterInternal(pBus, 0, &pBus->PciDev, "dram");
2461	#endif
2462
2463	/*
2464	* Register I/O ports and save state.
2465	*/
2466	rc = PDMDevHlpIOPortRegister(pDevIns, 0x0cf8, 1, NULL, ich9pciIOPortAddressWrite, ich9pciIOPortAddressRead, NULL, NULL, "ICH9 (PCI)");
2467	if (RT_FAILURE(rc))
2468	return rc;
2469	rc = PDMDevHlpIOPortRegister(pDevIns, 0x0cfc, 4, NULL, ich9pciIOPortDataWrite, ich9pciIOPortDataRead, NULL, NULL, "ICH9 (PCI)");
2470	if (RT_FAILURE(rc))
2471	return rc;
2472	if (fGCEnabled)
2473	{
2474	rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x0cf8, 1, NIL_RTGCPTR, "ich9pciIOPortAddressWrite", "ich9pciIOPortAddressRead", NULL, NULL, "ICH9 (PCI)");
2475	if (RT_FAILURE(rc))
2476	return rc;
2477	rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x0cfc, 4, NIL_RTGCPTR, "ich9pciIOPortDataWrite", "ich9pciIOPortDataRead", NULL, NULL, "ICH9 (PCI)");
2478	if (RT_FAILURE(rc))
2479	return rc;
2480	}
2481	if (fR0Enabled)
2482	{
2483	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x0cf8, 1, NIL_RTR0PTR, "ich9pciIOPortAddressWrite", "ich9pciIOPortAddressRead", NULL, NULL, "ICH9 (PCI)");
2484	if (RT_FAILURE(rc))
2485	return rc;
2486	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x0cfc, 4, NIL_RTR0PTR, "ich9pciIOPortDataWrite", "ich9pciIOPortDataRead", NULL, NULL, "ICH9 (PCI)");
2487	if (RT_FAILURE(rc))
2488	return rc;
2489	}
2490
2491	if (pGlobals->u64PciConfigMMioAddress != 0)
2492	{
2493	rc = PDMDevHlpMMIORegister(pDevIns, pGlobals->u64PciConfigMMioAddress, pGlobals->u64PciConfigMMioLength, NULL /pvUser/,
2494	IOMMMIO_FLAGS_READ_PASSTHRU \| IOMMMIO_FLAGS_WRITE_PASSTHRU,
2495	ich9pciMcfgMMIOWrite, ich9pciMcfgMMIORead, "MCFG ranges");
2496	AssertMsgRCReturn(rc, ("rc=%Rrc %#llx/%#llx\n", rc, pGlobals->u64PciConfigMMioAddress, pGlobals->u64PciConfigMMioLength), rc);
2497
2498	if (fGCEnabled)
2499	{
2500	rc = PDMDevHlpMMIORegisterRC(pDevIns, pGlobals->u64PciConfigMMioAddress, pGlobals->u64PciConfigMMioLength,
2501	NIL_RTRCPTR /pvUser/, "ich9pciMcfgMMIOWrite", "ich9pciMcfgMMIORead");
2502	AssertRCReturn(rc, rc);
2503	}
2504
2505
2506	if (fR0Enabled)
2507	{
2508	rc = PDMDevHlpMMIORegisterR0(pDevIns, pGlobals->u64PciConfigMMioAddress, pGlobals->u64PciConfigMMioLength,
2509	NIL_RTR0PTR /pvUser/, "ich9pciMcfgMMIOWrite", "ich9pciMcfgMMIORead");
2510	AssertRCReturn(rc, rc);
2511	}
2512	}
2513
2514	rc = PDMDevHlpSSMRegisterEx(pDevIns, VBOX_ICH9PCI_SAVED_STATE_VERSION_CURRENT,
2515	sizeof(pBus) + 16128, "pgm",
2516	NULL, NULL, NULL,
2517	NULL, ich9pciR3SaveExec, NULL,
2518	NULL, ich9pciR3LoadExec, NULL);
2519	if (RT_FAILURE(rc))
2520	return rc;
2521
2522
2523	/** @todo other chipset devices shall be registered too */
2524
2525	PDMDevHlpDBGFInfoRegister(pDevIns, "pci",
2526	"Display PCI bus status. Recognizes 'basic' or 'verbose' as arguments, defaults to 'basic'.",
2527	devpciR3InfoPci);
2528	PDMDevHlpDBGFInfoRegister(pDevIns, "pciirq", "Display PCI IRQ state. (no arguments)", devpciR3InfoPciIrq);
2529
2530	return VINF_SUCCESS;
2531	}
2532
2533	static void ich9pciResetDevice(PPDMPCIDEV pDev)
2534	{
2535	/* Clear regions */
2536	for (int iRegion = 0; iRegion < VBOX_PCI_NUM_REGIONS; iRegion++)
2537	{
2538	PCIIORegion* pRegion = &pDev->Int.s.aIORegions[iRegion];
2539	if (pRegion->size == 0)
2540	continue;
2541
2542	ich9pciUnmapRegion(pDev, iRegion);
2543	}
2544
2545	if (pciDevIsPassthrough(pDev))
2546	{
2547	// no reset handler - we can do what we need in PDM reset handler
2548	/// @todo is it correct?
2549	}
2550	else
2551	{
2552	PCIDevSetCommand(pDev,
2553	PCIDevGetCommand(pDev)
2554	&
2555	~(VBOX_PCI_COMMAND_IO \| VBOX_PCI_COMMAND_MEMORY \|
2556	VBOX_PCI_COMMAND_MASTER \| VBOX_PCI_COMMAND_SPECIAL \|
2557	VBOX_PCI_COMMAND_PARITY \| VBOX_PCI_COMMAND_SERR \|
2558	VBOX_PCI_COMMAND_FAST_BACK \| VBOX_PCI_COMMAND_INTX_DISABLE));
2559
2560	/* Bridge device reset handlers processed later */
2561	if (!pciDevIsPci2PciBridge(pDev))
2562	{
2563	PCIDevSetByte(pDev, VBOX_PCI_CACHE_LINE_SIZE, 0x0);
2564	PCIDevSetInterruptLine(pDev, 0x0);
2565	}
2566
2567	/* Reset MSI message control. */
2568	if (pciDevIsMsiCapable(pDev))
2569	{
2570	/* Extracted from MsiPciConfigWrite(). */
2571	pDev->abConfig[pDev->Int.s.u8MsiCapOffset + VBOX_MSI_CAP_MESSAGE_CONTROL] &= 0x8e;
2572	}
2573
2574	/* Reset MSI-X message control. */
2575	if (pciDevIsMsixCapable(pDev))
2576	{
2577	/* Extracted from MsixPciConfigWrite(); no side effects. */
2578	pDev->abConfig[pDev->Int.s.u8MsixCapOffset + VBOX_MSIX_CAP_MESSAGE_CONTROL + 1] &= 0x3f;
2579	}
2580	}
2581	}
2582
2583
2584	/**
2585	* @copydoc FNPDMDEVRESET
2586	*/
2587	static DECLCALLBACK(void) ich9pciReset(PPDMDEVINS pDevIns)
2588	{
2589	PDEVPCIROOT pGlobals = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
2590	PDEVPCIBUS pBus = &pGlobals->PciBus;
2591
2592	/* PCI-specific reset for each device. */
2593	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
2594	{
2595	if (pBus->apDevices[i])
2596	ich9pciResetDevice(pBus->apDevices[i]);
2597	}
2598
2599	for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
2600	{
2601	if (pBus->papBridgesR3[iBridge])
2602	ich9pcibridgeReset(pBus->papBridgesR3[iBridge]->Int.s.CTX_SUFF(pDevIns));
2603	}
2604
2605	ich9pciFakePCIBIOS(pDevIns);
2606	}
2607
2608
2609	/**
2610	* @interface_method_impl{PDMDEVREG,pfnRelocate}
2611	*/
2612	DECLCALLBACK(void) devpciR3BusRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
2613	{
2614	PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
2615
2616	pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2617	pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
2618
2619	/* Relocate RC pointers for the attached pci devices. */
2620	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
2621	{
2622	PPDMPCIDEV pDev = pBus->apDevices[i];
2623	if (pDev)
2624	{
2625	pDev->Int.s.pBusRC += offDelta;
2626	if (pDev->Int.s.pMsixPageRC)
2627	pDev->Int.s.pMsixPageRC += offDelta;
2628	}
2629	}
2630	}
2631
2632
2633	/**
2634	* @interface_method_impl{PDMDEVREG,pfnRelocate}
2635	*/
2636	DECLCALLBACK(void) devpciR3RootRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
2637	{
2638	PDEVPCIROOT pGlobals = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
2639	pGlobals->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2640
2641	AssertCompileMemberOffset(DEVPCIROOT, PciBus, 0);
2642	devpciR3BusRelocate(pDevIns, offDelta);
2643	}
2644
2645
2646	/**
2647	* @interface_method_impl{PDMDEVREG,pfnConstruct}
2648	*/
2649	static DECLCALLBACK(int) ich9pcibridgeConstruct(PPDMDEVINS pDevIns,
2650	int iInstance,
2651	PCFGMNODE pCfg)
2652	{
2653	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
2654
2655	/*
2656	* Validate and read configuration.
2657	*/
2658	if (!CFGMR3AreValuesValid(pCfg, "GCEnabled\0" "R0Enabled\0"))
2659	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
2660
2661	/* check if RC code is enabled. */
2662	bool fGCEnabled;
2663	int rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
2664	if (RT_FAILURE(rc))
2665	return PDMDEV_SET_ERROR(pDevIns, rc,
2666	N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
2667
2668	/* check if R0 code is enabled. */
2669	bool fR0Enabled;
2670	rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
2671	if (RT_FAILURE(rc))
2672	return PDMDEV_SET_ERROR(pDevIns, rc,
2673	N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
2674	Log(("PCI: fGCEnabled=%RTbool fR0Enabled=%RTbool\n", fGCEnabled, fR0Enabled));
2675
2676	/*
2677	* Init data and register the PCI bus.
2678	*/
2679	PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
2680	pBus->fTypePiix3 = false;
2681	pBus->fTypeIch9 = true;
2682	pBus->fPureBridge = true;
2683	pBus->pDevInsR3 = pDevIns;
2684	pBus->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2685	pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2686	pBus->papBridgesR3 = (PPDMPCIDEV )PDMDevHlpMMHeapAllocZ(pDevIns, sizeof(PPDMPCIDEV) RT_ELEMENTS(pBus->apDevices));
2687	AssertLogRelReturn(pBus->papBridgesR3, VERR_NO_MEMORY);
2688
2689	PDMPCIBUSREG PciBusReg;
2690	PciBusReg.u32Version = PDM_PCIBUSREG_VERSION;
2691	PciBusReg.pfnRegisterR3 = pcibridgeR3MergedRegisterDevice;
2692	PciBusReg.pfnRegisterMsiR3 = ich9pciRegisterMsi;
2693	PciBusReg.pfnIORegionRegisterR3 = devpciR3CommonIORegionRegister;
2694	PciBusReg.pfnSetConfigCallbacksR3 = devpciR3CommonSetConfigCallbacks;
2695	PciBusReg.pfnSetIrqR3 = ich9pcibridgeSetIrq;
2696	PciBusReg.pfnFakePCIBIOSR3 = NULL; /* Only needed for the first bus. */
2697	PciBusReg.pszSetIrqRC = fGCEnabled ? "ich9pcibridgeSetIrq" : NULL;
2698	PciBusReg.pszSetIrqR0 = fR0Enabled ? "ich9pcibridgeSetIrq" : NULL;
2699	rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBus->pPciHlpR3);
2700	if (RT_FAILURE(rc))
2701	return PDMDEV_SET_ERROR(pDevIns, rc,
2702	N_("Failed to register ourselves as a PCI Bus"));
2703	if (pBus->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
2704	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
2705	N_("PCI helper version mismatch; got %#x expected %#x"),
2706	pBus->pPciHlpR3->u32Version, PDM_PCIHLPR3_VERSION);
2707
2708	pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
2709	pBus->pPciHlpR0 = pBus->pPciHlpR3->pfnGetR0Helpers(pDevIns);
2710
2711	/* Disable default device locking. */
2712	rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
2713	AssertRCReturn(rc, rc);
2714
2715	/*
2716	* Fill in PCI configs and add them to the bus.
2717	*/
2718	PCIDevSetVendorId( &pBus->PciDev, 0x8086); /* Intel */
2719	PCIDevSetDeviceId( &pBus->PciDev, 0x2448); /* 82801 Mobile PCI bridge. */
2720	PCIDevSetRevisionId(&pBus->PciDev, 0xf2);
2721	PCIDevSetClassSub( &pBus->PciDev, 0x04); /* pci2pci */
2722	PCIDevSetClassBase( &pBus->PciDev, 0x06); /* PCI_bridge */
2723	PCIDevSetClassProg( &pBus->PciDev, 0x01); /* Supports subtractive decoding. */
2724	PCIDevSetHeaderType(&pBus->PciDev, 0x01); /* Single function device which adheres to the PCI-to-PCI bridge spec. */
2725	PCIDevSetCommand( &pBus->PciDev, 0x00);
2726	PCIDevSetStatus( &pBus->PciDev, 0x20); /* 66MHz Capable. */
2727	PCIDevSetInterruptLine(&pBus->PciDev, 0x00); /* This device does not assert interrupts. */
2728
2729	/*
2730	* This device does not generate interrupts. Interrupt delivery from
2731	* devices attached to the bus is unaffected.
2732	*/
2733	PCIDevSetInterruptPin (&pBus->PciDev, 0x00);
2734
2735	/*
2736	* Register this PCI bridge. The called function will take care on which bus we will get registered.
2737	*/
2738	rc = PDMDevHlpPCIRegisterEx(pDevIns, &pBus->PciDev, PDMPCIDEVREG_CFG_PRIMARY, PDMPCIDEVREG_F_PCI_BRIDGE,
2739	PDMPCIDEVREG_DEV_NO_FIRST_UNUSED, PDMPCIDEVREG_FUN_NO_FIRST_UNUSED, "ich9pcibridge");
2740	if (RT_FAILURE(rc))
2741	return rc;
2742	pBus->PciDev.Int.s.pfnBridgeConfigRead = ich9pcibridgeConfigRead;
2743	pBus->PciDev.Int.s.pfnBridgeConfigWrite = ich9pcibridgeConfigWrite;
2744
2745	/*
2746	* The iBus property doesn't really represent the bus number
2747	* because the guest and the BIOS can choose different bus numbers
2748	* for them.
2749	* The bus number is mainly for the setIrq function to indicate
2750	* when the host bus is reached which will have iBus = 0.
2751	* That's why the + 1.
2752	*/
2753	pBus->iBus = iInstance + 1;
2754
2755	/*
2756	* Register SSM handlers. We use the same saved state version as for the host bridge
2757	* to make changes easier.
2758	*/
2759	rc = PDMDevHlpSSMRegisterEx(pDevIns, VBOX_ICH9PCI_SAVED_STATE_VERSION_CURRENT,
2760	sizeof(pBus) + 16128,
2761	"pgm" /* before */,
2762	NULL, NULL, NULL,
2763	NULL, ich9pcibridgeR3SaveExec, NULL,
2764	NULL, ich9pcibridgeR3LoadExec, NULL);
2765	if (RT_FAILURE(rc))
2766	return rc;
2767
2768
2769	return VINF_SUCCESS;
2770	}
2771
2772	/**
2773	* @copydoc FNPDMDEVRESET
2774	*/
2775	static void ich9pcibridgeReset(PPDMDEVINS pDevIns)
2776	{
2777	PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
2778
2779	/* Reset config space to default values. */
2780	PCIDevSetByte(&pBus->PciDev, VBOX_PCI_PRIMARY_BUS, 0);
2781	PCIDevSetByte(&pBus->PciDev, VBOX_PCI_SECONDARY_BUS, 0);
2782	PCIDevSetByte(&pBus->PciDev, VBOX_PCI_SUBORDINATE_BUS, 0);
2783
2784	/* PCI-specific reset for each device. */
2785	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
2786	{
2787	if (pBus->apDevices[i])
2788	ich9pciResetDevice(pBus->apDevices[i]);
2789	}
2790	}
2791
2792
2793
2794	/**
2795	* The PCI bus device registration structure.
2796	*/
2797	const PDMDEVREG g_DevicePciIch9 =
2798	{
2799	/* u32Version */
2800	PDM_DEVREG_VERSION,
2801	/* szName */
2802	"ich9pci",
2803	/* szRCMod */
2804	"VBoxDDRC.rc",
2805	/* szR0Mod */
2806	"VBoxDDR0.r0",
2807	/* pszDescription */
2808	"ICH9 PCI bridge",
2809	/* fFlags */
2810	PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
2811	/* fClass */
2812	PDM_DEVREG_CLASS_BUS_PCI \| PDM_DEVREG_CLASS_BUS_ISA,
2813	/* cMaxInstances */
2814	1,
2815	/* cbInstance */
2816	sizeof(DEVPCIROOT),
2817	/* pfnConstruct */
2818	ich9pciConstruct,
2819	/* pfnDestruct */
2820	NULL,
2821	/* pfnRelocate */
2822	devpciR3RootRelocate,
2823	/* pfnMemSetup */
2824	NULL,
2825	/* pfnPowerOn */
2826	NULL,
2827	/* pfnReset */
2828	ich9pciReset,
2829	/* pfnSuspend */
2830	NULL,
2831	/* pfnResume */
2832	NULL,
2833	/* pfnAttach */
2834	NULL,
2835	/* pfnDetach */
2836	NULL,
2837	/* pfnQueryInterface */
2838	NULL,
2839	/* pfnInitComplete */
2840	NULL,
2841	/* pfnPowerOff */
2842	NULL,
2843	/* pfnSoftReset */
2844	NULL,
2845	/* u32VersionEnd */
2846	PDM_DEVREG_VERSION
2847	};
2848
2849	/**
2850	* The device registration structure
2851	* for the PCI-to-PCI bridge.
2852	*/
2853	const PDMDEVREG g_DevicePciIch9Bridge =
2854	{
2855	/* u32Version */
2856	PDM_DEVREG_VERSION,
2857	/* szName */
2858	"ich9pcibridge",
2859	/* szRCMod */
2860	"VBoxDDRC.rc",
2861	/* szR0Mod */
2862	"VBoxDDR0.r0",
2863	/* pszDescription */
2864	"ICH9 PCI to PCI bridge",
2865	/* fFlags */
2866	PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
2867	/* fClass */
2868	PDM_DEVREG_CLASS_BUS_PCI,
2869	/* cMaxInstances */
2870	~0U,
2871	/* cbInstance */
2872	sizeof(DEVPCIBUS),
2873	/* pfnConstruct */
2874	ich9pcibridgeConstruct,
2875	/* pfnDestruct */
2876	NULL,
2877	/* pfnRelocate */
2878	devpciR3BusRelocate,
2879	/* pfnMemSetup */
2880	NULL,
2881	/* pfnPowerOn */
2882	NULL,
2883	/* pfnReset */
2884	NULL, /* Must be NULL, to make sure only bus driver handles reset */
2885	/* pfnSuspend */
2886	NULL,
2887	/* pfnResume */
2888	NULL,
2889	/* pfnAttach */
2890	NULL,
2891	/* pfnDetach */
2892	NULL,
2893	/* pfnQueryInterface */
2894	NULL,
2895	/* pfnInitComplete */
2896	NULL,
2897	/* pfnPowerOff */
2898	NULL,
2899	/* pfnSoftReset */
2900	NULL,
2901	/* u32VersionEnd */
2902	PDM_DEVREG_VERSION
2903	};
2904
2905	#endif /* IN_RING3 */
2906

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source: vbox/trunk/src/VBox/Devices/Bus/DevPciIch9.cpp@ 64459

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