DevPciIch9.cpp@ 64467

Last change on this file since 64467 was 64467, checked in by vboxsync, 8 years ago
DevPci: Cleaning up ich9pciUpdateMappings and friends.
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1	/* $Id: DevPciIch9.cpp 64467 2016-10-28 15:19:42Z vboxsync $ */
2	/** @file
3	* DevPCI - ICH9 southbridge PCI bus emulation device.
4	*
5	* @remarks We'll be slowly promoting the code in this file to common PCI bus
6	* code. Function without 'static' and using 'devpci' as prefix is
7	* also used by DevPCI.cpp and have a prototype in DevPciInternal.h.
8	*
9	* For the time being the DevPciMerge1.cpp.h file will remain separate,
10	* due to 5.1. We can merge it into this one later in the dev cycle.
11	*/
12
13	/*
14	* Copyright (C) 2010-2016 Oracle Corporation
15	*
16	* This file is part of VirtualBox Open Source Edition (OSE), as
17	* available from http://www.virtualbox.org. This file is free software;
18	* you can redistribute it and/or modify it under the terms of the GNU
19	* General Public License (GPL) as published by the Free Software
20	* Foundation, in version 2 as it comes in the "COPYING" file of the
21	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
22	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
23	*/
24
25
26	/*********************************************************************************************************************************
27	* Header Files *
28	*********************************************************************************************************************************/
29	#define LOG_GROUP LOG_GROUP_DEV_PCI
30	#define PDMPCIDEV_INCLUDE_PRIVATE /* Hack to get pdmpcidevint.h included at the right point. */
31	#include <VBox/vmm/pdmpcidev.h>
32
33	#include <VBox/msi.h>
34	#include <VBox/vmm/pdmdev.h>
35	#include <VBox/vmm/mm.h>
36	#include <iprt/asm.h>
37	#include <iprt/assert.h>
38	#include <iprt/string.h>
39	#ifdef IN_RING3
40	# include <iprt/mem.h>
41	#endif
42
43	#include "PciInline.h"
44	#include "VBoxDD.h"
45	#include "MsiCommon.h"
46	#include "DevPciInternal.h"
47
48
49	/*********************************************************************************************************************************
50	* Structures and Typedefs *
51	*********************************************************************************************************************************/
52	/**
53	* PCI configuration space address.
54	*/
55	typedef struct
56	{
57	uint8_t iBus;
58	uint8_t iDeviceFunc;
59	uint16_t iRegister;
60	} PciAddress;
61
62
63	/*********************************************************************************************************************************
64	* Defined Constants And Macros *
65	*********************************************************************************************************************************/
66	/** @def VBOX_ICH9PCI_SAVED_STATE_VERSION
67	* Saved state version of the ICH9 PCI bus device.
68	*/
69	#define VBOX_ICH9PCI_SAVED_STATE_VERSION_NOMSI 1
70	#define VBOX_ICH9PCI_SAVED_STATE_VERSION_MSI 2
71	#define VBOX_ICH9PCI_SAVED_STATE_VERSION_CURRENT VBOX_ICH9PCI_SAVED_STATE_VERSION_MSI
72
73	/** Invalid PCI region mapping address. */
74	#define INVALID_PCI_ADDRESS UINT32_MAX
75
76
77	/*********************************************************************************************************************************
78	* Internal Functions *
79	*********************************************************************************************************************************/
80	/* Prototypes */
81	static void ich9pciSetIrqInternal(PDEVPCIROOT pGlobals, uint8_t uDevFn, PPDMPCIDEV pPciDev,
82	int iIrq, int iLevel, uint32_t uTagSrc);
83	#ifdef IN_RING3
84	static void ich9pcibridgeReset(PPDMDEVINS pDevIns);
85	DECLINLINE(PPDMPCIDEV) ich9pciFindBridge(PDEVPCIBUS pBus, uint8_t iBus);
86	static void ich9pciBiosInitDevice(PDEVPCIROOT pGlobals, uint8_t uBus, uint8_t uDevFn);
87	#endif
88
89
90	// See 7.2.2. PCI Express Enhanced Configuration Mechanism for details of address
91	// mapping, we take n=6 approach
92	DECLINLINE(void) ich9pciPhysToPciAddr(PDEVPCIROOT pGlobals, RTGCPHYS GCPhysAddr, PciAddress* pPciAddr)
93	{
94	NOREF(pGlobals);
95	pPciAddr->iBus = (GCPhysAddr >> 20) & ((1<<6) - 1);
96	pPciAddr->iDeviceFunc = (GCPhysAddr >> 12) & ((1<<(5+3)) - 1); // 5 bits - device, 3 bits - function
97	pPciAddr->iRegister = (GCPhysAddr >> 0) & ((1<<(6+4+2)) - 1); // 6 bits - register, 4 bits - extended register, 2 bits -Byte Enable
98	}
99
100	DECLINLINE(void) ich9pciStateToPciAddr(PDEVPCIROOT pGlobals, RTGCPHYS addr, PciAddress* pPciAddr)
101	{
102	pPciAddr->iBus = (pGlobals->uConfigReg >> 16) & 0xff;
103	pPciAddr->iDeviceFunc = (pGlobals->uConfigReg >> 8) & 0xff;
104	pPciAddr->iRegister = (pGlobals->uConfigReg & 0xfc) \| (addr & 3);
105	}
106
107	PDMBOTHCBDECL(void) ich9pciSetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc)
108	{
109	LogFlowFunc(("invoked by %p/%d: iIrq=%d iLevel=%d uTagSrc=%#x\n", pDevIns, pDevIns->iInstance, iIrq, iLevel, uTagSrc));
110	ich9pciSetIrqInternal(PDMINS_2_DATA(pDevIns, PDEVPCIROOT), pPciDev->uDevFn, pPciDev, iIrq, iLevel, uTagSrc);
111	}
112
113	PDMBOTHCBDECL(void) ich9pcibridgeSetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc)
114	{
115	/*
116	* The PCI-to-PCI bridge specification defines how the interrupt pins
117	* are routed from the secondary to the primary bus (see chapter 9).
118	* iIrq gives the interrupt pin the pci device asserted.
119	* We change iIrq here according to the spec and call the SetIrq function
120	* of our parent passing the device which asserted the interrupt instead of the device of the bridge.
121	*/
122	PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
123	PPDMPCIDEV pPciDevBus = pPciDev;
124	int iIrqPinBridge = iIrq;
125	uint8_t uDevFnBridge = 0;
126
127	/* Walk the chain until we reach the host bus. */
128	do
129	{
130	uDevFnBridge = pBus->PciDev.uDevFn;
131	iIrqPinBridge = ((pPciDevBus->uDevFn >> 3) + iIrqPinBridge) & 3;
132
133	/* Get the parent. */
134	pBus = pBus->PciDev.Int.s.CTX_SUFF(pBus);
135	pPciDevBus = &pBus->PciDev;
136	} while (pBus->iBus != 0);
137
138	AssertMsgReturnVoid(pBus->iBus == 0, ("This is not the host pci bus iBus=%d\n", pBus->iBus));
139	ich9pciSetIrqInternal(DEVPCIBUS_2_DEVPCIROOT(pBus), uDevFnBridge, pPciDev, iIrqPinBridge, iLevel, uTagSrc);
140	}
141
142
143	/**
144	* Port I/O Handler for PCI address OUT operations.
145	*
146	* Emulates writes to Configuration Address Port at 0CF8h for
147	* Configuration Mechanism #1.
148	*
149	* @returns VBox status code.
150	*
151	* @param pDevIns ICH9 device instance.
152	* @param pvUser User argument - ignored.
153	* @param uPort Port number used for the OUT operation.
154	* @param u32 The value to output.
155	* @param cb The value size in bytes.
156	*/
157	PDMBOTHCBDECL(int) ich9pciIOPortAddressWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
158	{
159	LogFlow(("ich9pciIOPortAddressWrite: Port=%#x u32=%#x cb=%d\n", Port, u32, cb));
160	RT_NOREF2(Port, pvUser);
161	if (cb == 4)
162	{
163	PDEVPCIROOT pThis = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
164
165	/*
166	* bits [1:0] are hard-wired, read-only and must return zeroes
167	* when read.
168	*/
169	u32 &= ~3;
170
171	PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_WRITE);
172	pThis->uConfigReg = u32;
173	PCI_UNLOCK(pDevIns);
174	}
175
176	return VINF_SUCCESS;
177	}
178
179
180	/**
181	* Port I/O Handler for PCI address IN operations.
182	*
183	* Emulates reads from Configuration Address Port at 0CF8h for
184	* Configuration Mechanism #1.
185	*
186	* @returns VBox status code.
187	*
188	* @param pDevIns ICH9 device instance.
189	* @param pvUser User argument - ignored.
190	* @param uPort Port number used for the IN operation.
191	* @param pu32 Where to store the result.
192	* @param cb Number of bytes read.
193	*/
194	PDMBOTHCBDECL(int) ich9pciIOPortAddressRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
195	{
196	RT_NOREF2(Port, pvUser);
197	if (cb == 4)
198	{
199	PDEVPCIROOT pThis = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
200
201	PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_READ);
202	*pu32 = pThis->uConfigReg;
203	PCI_UNLOCK(pDevIns);
204
205	LogFlow(("ich9pciIOPortAddressRead: Port=%#x cb=%d -> %#x\n", Port, cb, *pu32));
206	return VINF_SUCCESS;
207	}
208
209	Log(("ich9pciIOPortAddressRead: Port=%#x cb=%d VERR_IOM_IOPORT_UNUSED\n", Port, cb));
210	return VERR_IOM_IOPORT_UNUSED;
211	}
212
213
214	/*
215	* Perform configuration space write.
216	*/
217	static int ich9pciDataWriteAddr(PDEVPCIROOT pGlobals, PciAddress* pAddr,
218	uint32_t val, int cb, int rcReschedule)
219	{
220	int rc = VINF_SUCCESS;
221	#ifdef IN_RING3
222	NOREF(rcReschedule);
223	#else
224	RT_NOREF2(val, cb);
225	#endif
226
227	if (pAddr->iBus != 0) /* forward to subordinate bus */
228	{
229	if (pGlobals->PciBus.cBridges)
230	{
231	#ifdef IN_RING3 /** @todo do lookup in R0/RC too! */
232	PPDMPCIDEV pBridgeDevice = ich9pciFindBridge(&pGlobals->PciBus, pAddr->iBus);
233	if (pBridgeDevice)
234	{
235	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigWrite);
236	pBridgeDevice->Int.s.pfnBridgeConfigWrite(pBridgeDevice->Int.s.CTX_SUFF(pDevIns), pAddr->iBus, pAddr->iDeviceFunc,
237	pAddr->iRegister, val, cb);
238	}
239	#else
240	rc = rcReschedule;
241	#endif
242	}
243	}
244	else /* forward to directly connected device */
245	{
246	R3PTRTYPE(PDMPCIDEV *) pPciDev = pGlobals->PciBus.apDevices[pAddr->iDeviceFunc];
247	if (pPciDev)
248	{
249	#ifdef IN_RING3
250	pPciDev->Int.s.pfnConfigWrite(pPciDev->Int.s.CTX_SUFF(pDevIns), pPciDev, pAddr->iRegister, val, cb);
251	#else
252	rc = rcReschedule;
253	#endif
254	}
255	}
256
257	Log2(("ich9pciDataWriteAddr: %02x:%02x:%02x reg %x(%d) %x %Rrc\n",
258	pAddr->iBus, pAddr->iDeviceFunc >> 3, pAddr->iDeviceFunc & 0x7, pAddr->iRegister,
259	cb, val, rc));
260	return rc;
261	}
262
263
264	/*
265	* Decode value latched in Configuration Address Port and perform
266	* requsted write to the target configuration space register.
267	*
268	* XXX: This code should be probably moved to its only caller
269	* (ich9pciIOPortDataWrite) to avoid prolifiration of confusingly
270	* similarly named functions.
271	*/
272	static int ich9pciDataWrite(PDEVPCIROOT pGlobals, uint32_t addr, uint32_t val, int len)
273	{
274	LogFlow(("ich9pciDataWrite: config=%08x val=%08x len=%d\n", pGlobals->uConfigReg, val, len));
275
276	/* Configuration space mapping enabled? */
277	if (!(pGlobals->uConfigReg & (1 << 31)))
278	return VINF_SUCCESS;
279
280	/* Decode target device and configuration space register */
281	PciAddress aPciAddr;
282	ich9pciStateToPciAddr(pGlobals, addr, &aPciAddr);
283
284	/* Perform configuration space write */
285	return ich9pciDataWriteAddr(pGlobals, &aPciAddr, val, len, VINF_IOM_R3_IOPORT_WRITE);
286	}
287
288
289	/**
290	* Port I/O Handler for PCI data OUT operations.
291	*
292	* Emulates writes to Configuration Data Port at 0CFCh for
293	* Configuration Mechanism #1.
294	*
295	* @returns VBox status code.
296	*
297	* @param pDevIns ICH9 device instance.
298	* @param pvUser User argument - ignored.
299	* @param uPort Port number used for the OUT operation.
300	* @param u32 The value to output.
301	* @param cb The value size in bytes.
302	*/
303	PDMBOTHCBDECL(int) ich9pciIOPortDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
304	{
305	LogFlow(("ich9pciIOPortDataWrite: Port=%#x u32=%#x cb=%d\n", Port, u32, cb));
306	NOREF(pvUser);
307	int rc = VINF_SUCCESS;
308	if (!(Port % cb))
309	{
310	PDEVPCIROOT pThis = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
311
312	PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_WRITE);
313	rc = ich9pciDataWrite(pThis, Port, u32, cb);
314	PCI_UNLOCK(pDevIns);
315	}
316	else
317	AssertMsgFailed(("Unaligned write to port %#x u32=%#x cb=%d\n", Port, u32, cb));
318	return rc;
319	}
320
321
322	static void ich9pciNoMem(void* ptr, int cb)
323	{
324	for (int i = 0; i < cb; i++)
325	((uint8_t*)ptr)[i] = 0xff;
326	}
327
328
329	/*
330	* Perform configuration space read.
331	*/
332	static int ich9pciDataReadAddr(PDEVPCIROOT pGlobals, PciAddress* pPciAddr, int cb,
333	uint32_t *pu32, int rcReschedule)
334	{
335	int rc = VINF_SUCCESS;
336	#ifdef IN_RING3
337	NOREF(rcReschedule);
338	#endif
339
340	if (pPciAddr->iBus != 0) /* forward to subordinate bus */
341	{
342	if (pGlobals->PciBus.cBridges)
343	{
344	#ifdef IN_RING3 /** @todo do lookup in R0/RC too! */
345	PPDMPCIDEV pBridgeDevice = ich9pciFindBridge(&pGlobals->PciBus, pPciAddr->iBus);
346	if (pBridgeDevice)
347	{
348	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigRead);
349	*pu32 = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->Int.s.CTX_SUFF(pDevIns), pPciAddr->iBus,
350	pPciAddr->iDeviceFunc, pPciAddr->iRegister, cb);
351	}
352	else
353	ich9pciNoMem(pu32, cb);
354	#else
355	rc = rcReschedule;
356	#endif
357	}
358	else
359	ich9pciNoMem(pu32, cb);
360	}
361	else /* forward to directly connected device */
362	{
363	R3PTRTYPE(PDMPCIDEV *) pPciDev = pGlobals->PciBus.apDevices[pPciAddr->iDeviceFunc];
364	if (pPciDev)
365	{
366	#ifdef IN_RING3
367	*pu32 = pPciDev->Int.s.pfnConfigRead(pPciDev->Int.s.CTX_SUFF(pDevIns), pPciDev, pPciAddr->iRegister, cb);
368	#else
369	rc = rcReschedule;
370	#endif
371	}
372	else
373	ich9pciNoMem(pu32, cb);
374	}
375
376	Log3(("ich9pciDataReadAddr: %02x:%02x:%02x reg %x(%d) gave %x %Rrc\n",
377	pPciAddr->iBus, pPciAddr->iDeviceFunc >> 3, pPciAddr->iDeviceFunc & 0x7, pPciAddr->iRegister,
378	cb, *pu32, rc));
379	return rc;
380	}
381
382
383	/*
384	* Decode value latched in Configuration Address Port and perform
385	* requsted read from the target configuration space register.
386	*
387	* XXX: This code should be probably moved to its only caller
388	* (ich9pciIOPortDataRead) to avoid prolifiration of confusingly
389	* similarly named functions.
390	*/
391	static int ich9pciDataRead(PDEVPCIROOT pGlobals, uint32_t addr, int cb, uint32_t *pu32)
392	{
393	LogFlow(("ich9pciDataRead: config=%x cb=%d\n", pGlobals->uConfigReg, cb));
394
395	*pu32 = 0xffffffff;
396
397	/* Configuration space mapping enabled? */
398	if (!(pGlobals->uConfigReg & (1 << 31)))
399	return VINF_SUCCESS;
400
401	/* Decode target device and configuration space register */
402	PciAddress aPciAddr;
403	ich9pciStateToPciAddr(pGlobals, addr, &aPciAddr);
404
405	/* Perform configuration space read */
406	return ich9pciDataReadAddr(pGlobals, &aPciAddr, cb, pu32, VINF_IOM_R3_IOPORT_READ);
407	}
408
409
410	/**
411	* Port I/O Handler for PCI data IN operations.
412	*
413	* Emulates reads from Configuration Data Port at 0CFCh for
414	* Configuration Mechanism #1.
415	*
416	* @returns VBox status code.
417	*
418	* @param pDevIns ICH9 device instance.
419	* @param pvUser User argument - ignored.
420	* @param uPort Port number used for the IN operation.
421	* @param pu32 Where to store the result.
422	* @param cb Number of bytes read.
423	*/
424	PDMBOTHCBDECL(int) ich9pciIOPortDataRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
425	{
426	NOREF(pvUser);
427	if (!(Port % cb))
428	{
429	PDEVPCIROOT pThis = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
430
431	PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_READ);
432	int rc = ich9pciDataRead(pThis, Port, cb, pu32);
433	PCI_UNLOCK(pDevIns);
434
435	LogFlow(("ich9pciIOPortDataRead: Port=%#x cb=%#x -> %#x (%Rrc)\n", Port, cb, *pu32, rc));
436	return rc;
437	}
438	AssertMsgFailed(("Unaligned read from port %#x cb=%d\n", Port, cb));
439	return VERR_IOM_IOPORT_UNUSED;
440	}
441
442
443	/* Compute mapping of PCI slot and IRQ number to APIC interrupt line */
444	DECLINLINE(int) ich9pciSlot2ApicIrq(uint8_t uSlot, int irq_num)
445	{
446	return (irq_num + uSlot) & 7;
447	}
448
449	#ifdef IN_RING3
450
451	/* return the global irq number corresponding to a given device irq
452	pin. We could also use the bus number to have a more precise
453	mapping. This is the implementation note described in the PCI spec chapter 2.2.6 */
454	DECLINLINE(int) ich9pciSlotGetPirq(uint8_t uBus, uint8_t uDevFn, int iIrqNum)
455	{
456	NOREF(uBus);
457	int iSlotAddend = (uDevFn >> 3) - 1;
458	return (iIrqNum + iSlotAddend) & 3;
459	}
460
461	/* irqs corresponding to PCI irqs A-D, must match pci_irq_list in rombios.c */
462	static const uint8_t aPciIrqs[4] = { 11, 10, 9, 5 };
463
464	#endif /* IN_RING3 */
465
466	/* Add one more level up request on APIC input line */
467	DECLINLINE(void) ich9pciApicLevelUp(PDEVPCIROOT pGlobals, int irq_num)
468	{
469	ASMAtomicIncU32(&pGlobals->auPciApicIrqLevels[irq_num]);
470	}
471
472	/* Remove one level up request on APIC input line */
473	DECLINLINE(void) ich9pciApicLevelDown(PDEVPCIROOT pGlobals, int irq_num)
474	{
475	ASMAtomicDecU32(&pGlobals->auPciApicIrqLevels[irq_num]);
476	}
477
478	static void ich9pciApicSetIrq(PDEVPCIBUS pBus, uint8_t uDevFn, PDMPCIDEV *pPciDev, int irq_num1, int iLevel,
479	uint32_t uTagSrc, int iForcedIrq)
480	{
481	/* This is only allowed to be called with a pointer to the root bus. */
482	AssertMsg(pBus->iBus == 0, ("iBus=%u\n", pBus->iBus));
483
484	if (iForcedIrq == -1)
485	{
486	int apic_irq, apic_level;
487	PDEVPCIROOT pGlobals = DEVPCIBUS_2_DEVPCIROOT(pBus);
488	int irq_num = ich9pciSlot2ApicIrq(uDevFn >> 3, irq_num1);
489
490	if ((iLevel & PDM_IRQ_LEVEL_HIGH) == PDM_IRQ_LEVEL_HIGH)
491	ich9pciApicLevelUp(pGlobals, irq_num);
492	else if ((iLevel & PDM_IRQ_LEVEL_HIGH) == PDM_IRQ_LEVEL_LOW)
493	ich9pciApicLevelDown(pGlobals, irq_num);
494
495	apic_irq = irq_num + 0x10;
496	apic_level = pGlobals->auPciApicIrqLevels[irq_num] != 0;
497	Log3(("ich9pciApicSetIrq: %s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d uTagSrc=%#x\n",
498	R3STRING(pPciDev->pszNameR3), irq_num1, iLevel, apic_irq, apic_level, irq_num, uTagSrc));
499	pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), apic_irq, apic_level, uTagSrc);
500
501	if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP)
502	{
503	/*
504	* we raised it few lines above, as PDM_IRQ_LEVEL_FLIP_FLOP has
505	* PDM_IRQ_LEVEL_HIGH bit set
506	*/
507	ich9pciApicLevelDown(pGlobals, irq_num);
508	pPciDev->Int.s.uIrqPinState = PDM_IRQ_LEVEL_LOW;
509	apic_level = pGlobals->auPciApicIrqLevels[irq_num] != 0;
510	Log3(("ich9pciApicSetIrq: %s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d uTagSrc=%#x (flop)\n",
511	R3STRING(pPciDev->pszNameR3), irq_num1, iLevel, apic_irq, apic_level, irq_num, uTagSrc));
512	pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), apic_irq, apic_level, uTagSrc);
513	}
514	} else {
515	Log3(("ich9pciApicSetIrq: (forced) %s: irq_num1=%d level=%d acpi_irq=%d uTagSrc=%#x\n",
516	R3STRING(pPciDev->pszNameR3), irq_num1, iLevel, iForcedIrq, uTagSrc));
517	pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), iForcedIrq, iLevel, uTagSrc);
518	}
519	}
520
521	static void ich9pciSetIrqInternal(PDEVPCIROOT pGlobals, uint8_t uDevFn, PPDMPCIDEV pPciDev,
522	int iIrq, int iLevel, uint32_t uTagSrc)
523	{
524	/* If MSI or MSI-X is enabled, PCI INTx# signals are disabled regardless of the PCI command
525	* register interrupt bit state.
526	* PCI 3.0 (section 6.8) forbids MSI and MSI-X to be enabled at the same time and makes
527	* that undefined behavior. We check for MSI first, then MSI-X.
528	*/
529	if (MsiIsEnabled(pPciDev))
530	{
531	Assert(!MsixIsEnabled(pPciDev)); /* Not allowed -- see note above. */
532	LogFlowFunc(("PCI Dev %p : MSI\n", pPciDev));
533	PPDMDEVINS pDevIns = pGlobals->PciBus.CTX_SUFF(pDevIns);
534	MsiNotify(pDevIns, pGlobals->PciBus.CTX_SUFF(pPciHlp), pPciDev, iIrq, iLevel, uTagSrc);
535	return;
536	}
537
538	if (MsixIsEnabled(pPciDev))
539	{
540	LogFlowFunc(("PCI Dev %p : MSI-X\n", pPciDev));
541	PPDMDEVINS pDevIns = pGlobals->PciBus.CTX_SUFF(pDevIns);
542	MsixNotify(pDevIns, pGlobals->PciBus.CTX_SUFF(pPciHlp), pPciDev, iIrq, iLevel, uTagSrc);
543	return;
544	}
545
546	PDEVPCIBUS pBus = &pGlobals->PciBus;
547	const bool fIsAcpiDevice = PCIDevGetDeviceId(pPciDev) == 0x7113;
548
549	LogFlowFunc(("PCI Dev %p : IRQ\n", pPciDev));
550	/* Check if the state changed. */
551	if (pPciDev->Int.s.uIrqPinState != iLevel)
552	{
553	pPciDev->Int.s.uIrqPinState = (iLevel & PDM_IRQ_LEVEL_HIGH);
554
555	/* Send interrupt to I/O APIC only now. */
556	if (fIsAcpiDevice)
557	/*
558	* ACPI needs special treatment since SCI is hardwired and
559	* should not be affected by PCI IRQ routing tables at the
560	* same time SCI IRQ is shared in PCI sense hence this
561	* kludge (i.e. we fetch the hardwired value from ACPIs
562	* PCI device configuration space).
563	*/
564	ich9pciApicSetIrq(pBus, uDevFn, pPciDev, -1, iLevel, uTagSrc, PCIDevGetInterruptLine(pPciDev));
565	else
566	ich9pciApicSetIrq(pBus, uDevFn, pPciDev, iIrq, iLevel, uTagSrc, -1);
567	}
568	}
569
570
571	/**
572	* Memory mapped I/O Handler for write operations.
573	*
574	* Emulates writes to configuration space.
575	*
576	* @returns VBox status code.
577	*
578	* @param pDevIns The device instance.
579	* @param pvUser User argument.
580	* @param GCPhysAddr Physical address (in GC) where the read starts.
581	* @param pv Where to fetch the result.
582	* @param cb Number of bytes to write.
583	* @remarks Caller enters the device critical section.
584	*/
585	PDMBOTHCBDECL(int) ich9pciMcfgMMIOWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void const pv, unsigned cb)
586	{
587	PDEVPCIROOT pGlobals = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
588	uint32_t u32 = 0;
589	NOREF(pvUser);
590
591	Log2(("ich9pciMcfgMMIOWrite: %RGp(%d) \n", GCPhysAddr, cb));
592
593	PCI_LOCK(pDevIns, VINF_IOM_R3_MMIO_WRITE);
594
595	/* Decode target device and configuration space register */
596	PciAddress aDest;
597	ich9pciPhysToPciAddr(pGlobals, GCPhysAddr, &aDest);
598
599	switch (cb)
600	{
601	case 1:
602	u32 = (uint8_t)pv;
603	break;
604	case 2:
605	u32 = (uint16_t)pv;
606	break;
607	case 4:
608	u32 = (uint32_t)pv;
609	break;
610	default:
611	Assert(false);
612	break;
613	}
614
615	/* Perform configuration space write */
616	int rc = ich9pciDataWriteAddr(pGlobals, &aDest, u32, cb, VINF_IOM_R3_MMIO_WRITE);
617	PCI_UNLOCK(pDevIns);
618
619	return rc;
620	}
621
622
623	/**
624	* Memory mapped I/O Handler for read operations.
625	*
626	* Emulates reads from configuration space.
627	*
628	* @returns VBox status code.
629	*
630	* @param pDevIns The device instance.
631	* @param pvUser User argument.
632	* @param GCPhysAddr Physical address (in GC) where the read starts.
633	* @param pv Where to store the result.
634	* @param cb Number of bytes read.
635	* @remarks Caller enters the device critical section.
636	*/
637	PDMBOTHCBDECL(int) ich9pciMcfgMMIORead (PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb)
638	{
639	PDEVPCIROOT pGlobals = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
640	uint32_t rv;
641	NOREF(pvUser);
642
643	LogFlow(("ich9pciMcfgMMIORead: %RGp(%d) \n", GCPhysAddr, cb));
644
645	PCI_LOCK(pDevIns, VINF_IOM_R3_MMIO_READ);
646
647	/* Decode target device and configuration space register */
648	PciAddress aDest;
649	ich9pciPhysToPciAddr(pGlobals, GCPhysAddr, &aDest);
650
651	/* Perform configuration space read */
652	int rc = ich9pciDataReadAddr(pGlobals, &aDest, cb, &rv, VINF_IOM_R3_MMIO_READ);
653
654	if (RT_SUCCESS(rc))
655	{
656	switch (cb)
657	{
658	case 1:
659	(uint8_t)pv = (uint8_t)rv;
660	break;
661	case 2:
662	(uint16_t)pv = (uint16_t)rv;
663	break;
664	case 4:
665	(uint32_t)pv = (uint32_t)rv;
666	break;
667	default:
668	Assert(false);
669	break;
670	}
671	}
672	PCI_UNLOCK(pDevIns);
673
674	return rc;
675	}
676
677	#ifdef IN_RING3
678
679	/*
680	* Include code we share with the other PCI bus implementation.
681	*
682	* Note! No #ifdefs, use instant data booleans/flags/whatever. Goal is to
683	* completely merge these files! File #1 contains code we write, where
684	* as a possible file #2 contains external code if there's any left.
685	*/
686	# define pciR3UnmergedConfigWriteDev ich9pciConfigWriteDev
687	# include "DevPciMerge1.cpp.h"
688
689
690	DECLINLINE(PPDMPCIDEV) ich9pciFindBridge(PDEVPCIBUS pBus, uint8_t iBus)
691	{
692	/* Search for a fitting bridge. */
693	for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
694	{
695	/*
696	* Examine secondary and subordinate bus number.
697	* If the target bus is in the range we pass the request on to the bridge.
698	*/
699	PPDMPCIDEV pBridge = pBus->papBridgesR3[iBridge];
700	AssertMsg(pBridge && pciDevIsPci2PciBridge(pBridge),
701	("Device is not a PCI bridge but on the list of PCI bridges\n"));
702	uint32_t uSecondary = PDMPciDevGetByte(pBridge, VBOX_PCI_SECONDARY_BUS);
703	uint32_t uSubordinate = PDMPciDevGetByte(pBridge, VBOX_PCI_SUBORDINATE_BUS);
704	Log3(("ich9pciFindBridge on bus %p, bridge %d: %d in %d..%d\n", pBus, iBridge, iBus, uSecondary, uSubordinate));
705	if (iBus >= uSecondary && iBus <= uSubordinate)
706	return pBridge;
707	}
708
709	/* Nothing found. */
710	return NULL;
711	}
712
713	static uint32_t ich9pciGetCfg(PPDMPCIDEV pPciDev, int32_t iRegister, int cb)
714	{
715	return pPciDev->Int.s.pfnConfigRead(pPciDev->Int.s.CTX_SUFF(pDevIns), pPciDev, iRegister, cb);
716	}
717
718	static uint8_t ich9pciGetByte(PPDMPCIDEV pPciDev, int32_t iRegister)
719	{
720	return (uint8_t)ich9pciGetCfg(pPciDev, iRegister, 1);
721	}
722
723	static uint16_t ich9pciGetWord(PPDMPCIDEV pPciDev, int32_t iRegister)
724	{
725	return (uint16_t)ich9pciGetCfg(pPciDev, iRegister, 2);
726	}
727
728	static uint32_t ich9pciGetDWord(PPDMPCIDEV pPciDev, int32_t iRegister)
729	{
730	return (uint32_t)ich9pciGetCfg(pPciDev, iRegister, 4);
731	}
732
733	DECLINLINE(uint32_t) ich9pciGetRegionReg(int iRegion)
734	{
735	return iRegion == VBOX_PCI_ROM_SLOT
736	? VBOX_PCI_ROM_ADDRESS : (VBOX_PCI_BASE_ADDRESS_0 + iRegion * 4);
737	}
738
739
740	/* -=-=-=-=-=- PCI Bus Interface Methods (PDMPCIBUSREG) -=-=-=-=-=- */
741
742
743	static DECLCALLBACK(int) ich9pciRegisterMsi(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, PPDMMSIREG pMsiReg)
744	{
745	NOREF(pDevIns);
746	int rc;
747
748	rc = MsiInit(pPciDev, pMsiReg);
749	if (RT_FAILURE(rc))
750	return rc;
751
752	rc = MsixInit(pPciDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pPciHlp), pPciDev, pMsiReg);
753	if (RT_FAILURE(rc))
754	return rc;
755
756	return VINF_SUCCESS;
757	}
758
759
760	/**
761	* @interface_method_impl{PDMPCIBUSREG,pfnIORegionRegisterR3}
762	*/
763	DECLCALLBACK(int) devpciR3CommonIORegionRegister(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iRegion, RTGCPHYS cbRegion,
764	PCIADDRESSSPACE enmType, PFNPCIIOREGIONMAP pfnCallback)
765	{
766	NOREF(pDevIns);
767
768	/*
769	* Validate.
770	*/
771	AssertMsgReturn( enmType == (PCI_ADDRESS_SPACE_MEM \| PCI_ADDRESS_SPACE_BAR32)
772	\|\| enmType == (PCI_ADDRESS_SPACE_MEM_PREFETCH \| PCI_ADDRESS_SPACE_BAR32)
773	\|\| enmType == (PCI_ADDRESS_SPACE_MEM \| PCI_ADDRESS_SPACE_BAR64)
774	\|\| enmType == (PCI_ADDRESS_SPACE_MEM_PREFETCH \| PCI_ADDRESS_SPACE_BAR64)
775	\|\| enmType == PCI_ADDRESS_SPACE_IO
776	,
777	("Invalid enmType=%#x? Or was this a bitmask after all...\n", enmType),
778	VERR_INVALID_PARAMETER);
779	AssertMsgReturn((unsigned)iRegion < VBOX_PCI_NUM_REGIONS,
780	("Invalid iRegion=%d VBOX_PCI_NUM_REGIONS=%d\n", iRegion, VBOX_PCI_NUM_REGIONS),
781	VERR_INVALID_PARAMETER);
782	int iLastSet = ASMBitLastSetU64(cbRegion);
783	AssertMsgReturn( iLastSet != 0
784	&& RT_BIT_64(iLastSet - 1) == cbRegion,
785	("Invalid cbRegion=%RGp iLastSet=%#x (not a power of 2 or 0)\n", cbRegion, iLastSet),
786	VERR_INVALID_PARAMETER);
787
788	Log(("devpciR3CommonIORegionRegister: %s region %d size %RGp type %x\n",
789	pPciDev->pszNameR3, iRegion, cbRegion, enmType));
790
791	/* Make sure that we haven't marked this region as continuation of 64-bit region. */
792	Assert(pPciDev->Int.s.aIORegions[iRegion].type != 0xff);
793
794	/*
795	* Register the I/O region.
796	*/
797	PPCIIOREGION pRegion = &pPciDev->Int.s.aIORegions[iRegion];
798	pRegion->addr = INVALID_PCI_ADDRESS;
799	pRegion->size = cbRegion;
800	pRegion->type = enmType;
801	pRegion->map_func = pfnCallback;
802
803	if ((enmType & PCI_ADDRESS_SPACE_BAR64) != 0)
804	{
805	/* VBOX_PCI_BASE_ADDRESS_5 and VBOX_PCI_ROM_ADDRESS are excluded. */
806	AssertMsgReturn(iRegion < VBOX_PCI_NUM_REGIONS - 2,
807	("Region %d cannot be 64-bit\n", iRegion),
808	VERR_INVALID_PARAMETER);
809	/* Mark next region as continuation of this one. */
810	pPciDev->Int.s.aIORegions[iRegion + 1].type = 0xff;
811	}
812
813	/* Set type in the PCI config space. */
814	AssertCompile(PCI_ADDRESS_SPACE_MEM == 0);
815	AssertCompile(PCI_ADDRESS_SPACE_IO == 1);
816	AssertCompile(PCI_ADDRESS_SPACE_BAR64 == RT_BIT_32(2));
817	AssertCompile(PCI_ADDRESS_SPACE_MEM_PREFETCH == RT_BIT_32(3));
818	uint32_t u32Value = (uint32_t)enmType & (PCI_ADDRESS_SPACE_IO \| PCI_ADDRESS_SPACE_BAR64 \| PCI_ADDRESS_SPACE_MEM_PREFETCH);
819	PCIDevSetDWord(pPciDev, ich9pciGetRegionReg(iRegion), u32Value);
820
821	return VINF_SUCCESS;
822	}
823
824
825	/**
826	* @interface_method_impl{PDMPCIBUSREG,pfnSetConfigCallbacksR3}
827	*/
828	DECLCALLBACK(void) devpciR3CommonSetConfigCallbacks(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
829	PFNPCICONFIGREAD pfnRead, PPFNPCICONFIGREAD ppfnReadOld,
830	PFNPCICONFIGWRITE pfnWrite, PPFNPCICONFIGWRITE ppfnWriteOld)
831	{
832	NOREF(pDevIns);
833
834	if (ppfnReadOld)
835	*ppfnReadOld = pPciDev->Int.s.pfnConfigRead;
836	pPciDev->Int.s.pfnConfigRead = pfnRead;
837
838	if (ppfnWriteOld)
839	*ppfnWriteOld = pPciDev->Int.s.pfnConfigWrite;
840	pPciDev->Int.s.pfnConfigWrite = pfnWrite;
841	}
842
843
844	static int ich9pciR3CommonSaveExec(PDEVPCIBUS pBus, PSSMHANDLE pSSM)
845	{
846	/*
847	* Iterate thru all the devices.
848	*/
849	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
850	{
851	PPDMPCIDEV pDev = pBus->apDevices[i];
852	if (pDev)
853	{
854	/* Device position */
855	SSMR3PutU32(pSSM, i);
856	/* PCI config registers */
857	SSMR3PutMem(pSSM, pDev->abConfig, sizeof(pDev->abConfig));
858
859	/* Device flags */
860	int rc = SSMR3PutU32(pSSM, pDev->Int.s.fFlags);
861	if (RT_FAILURE(rc))
862	return rc;
863
864	/* IRQ pin state */
865	rc = SSMR3PutS32(pSSM, pDev->Int.s.uIrqPinState);
866	if (RT_FAILURE(rc))
867	return rc;
868
869	/* MSI info */
870	rc = SSMR3PutU8(pSSM, pDev->Int.s.u8MsiCapOffset);
871	if (RT_FAILURE(rc))
872	return rc;
873	rc = SSMR3PutU8(pSSM, pDev->Int.s.u8MsiCapSize);
874	if (RT_FAILURE(rc))
875	return rc;
876
877	/* MSI-X info */
878	rc = SSMR3PutU8(pSSM, pDev->Int.s.u8MsixCapOffset);
879	if (RT_FAILURE(rc))
880	return rc;
881	rc = SSMR3PutU8(pSSM, pDev->Int.s.u8MsixCapSize);
882	if (RT_FAILURE(rc))
883	return rc;
884	/* Save MSI-X page state */
885	if (pDev->Int.s.u8MsixCapOffset != 0)
886	{
887	Assert(pDev->Int.s.pMsixPageR3 != NULL);
888	SSMR3PutMem(pSSM, pDev->Int.s.pMsixPageR3, 0x1000);
889	if (RT_FAILURE(rc))
890	return rc;
891	}
892	}
893	}
894	return SSMR3PutU32(pSSM, UINT32_MAX); /* terminator */
895	}
896
897	static DECLCALLBACK(int) ich9pciR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
898	{
899	PDEVPCIROOT pThis = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
900
901	/*
902	* Bus state data.
903	*/
904	SSMR3PutU32(pSSM, pThis->uConfigReg);
905
906	/*
907	* Save IRQ states.
908	*/
909	for (unsigned i = 0; i < RT_ELEMENTS(pThis->auPciApicIrqLevels); i++)
910	SSMR3PutU32(pSSM, pThis->auPciApicIrqLevels[i]);
911
912	SSMR3PutU32(pSSM, UINT32_MAX); /* separator */
913
914	return ich9pciR3CommonSaveExec(&pThis->PciBus, pSSM);
915	}
916
917
918	static DECLCALLBACK(int) ich9pcibridgeR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
919	{
920	PDEVPCIBUS pThis = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
921	return ich9pciR3CommonSaveExec(pThis, pSSM);
922	}
923
924
925	static DECLCALLBACK(void) ich9pcibridgeConfigWrite(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice, uint32_t u32Address, uint32_t u32Value, unsigned cb)
926	{
927	PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
928
929	LogFlowFunc((": pDevIns=%p iBus=%d iDevice=%d u32Address=%u u32Value=%u cb=%d\n", pDevIns, iBus, iDevice, u32Address, u32Value, cb));
930
931	/* If the current bus is not the target bus search for the bus which contains the device. */
932	if (iBus != PDMPciDevGetByte(&pBus->PciDev, VBOX_PCI_SECONDARY_BUS))
933	{
934	PPDMPCIDEV pBridgeDevice = ich9pciFindBridge(pBus, iBus);
935	if (pBridgeDevice)
936	{
937	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigWrite);
938	pBridgeDevice->Int.s.pfnBridgeConfigWrite(pBridgeDevice->Int.s.CTX_SUFF(pDevIns), iBus, iDevice,
939	u32Address, u32Value, cb);
940	}
941	}
942	else
943	{
944	/* This is the target bus, pass the write to the device. */
945	PPDMPCIDEV pPciDev = pBus->apDevices[iDevice];
946	if (pPciDev)
947	{
948	Log(("%s: %s: addr=%02x val=%08x len=%d\n", __FUNCTION__, pPciDev->pszNameR3, u32Address, u32Value, cb));
949	pPciDev->Int.s.pfnConfigWrite(pPciDev->Int.s.CTX_SUFF(pDevIns), pPciDev, u32Address, u32Value, cb);
950	}
951	}
952	}
953
954	static DECLCALLBACK(uint32_t) ich9pcibridgeConfigRead(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice, uint32_t u32Address, unsigned cb)
955	{
956	PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
957	uint32_t u32Value;
958
959	LogFlowFunc((": pDevIns=%p iBus=%d iDevice=%d u32Address=%u cb=%d\n", pDevIns, iBus, iDevice, u32Address, cb));
960
961	/* If the current bus is not the target bus search for the bus which contains the device. */
962	if (iBus != PDMPciDevGetByte(&pBus->PciDev, VBOX_PCI_SECONDARY_BUS))
963	{
964	PPDMPCIDEV pBridgeDevice = ich9pciFindBridge(pBus, iBus);
965	if (pBridgeDevice)
966	{
967	AssertPtr( pBridgeDevice->Int.s.pfnBridgeConfigRead);
968	u32Value = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->Int.s.CTX_SUFF(pDevIns), iBus, iDevice,
969	u32Address, cb);
970	}
971	else
972	ich9pciNoMem(&u32Value, 4);
973	}
974	else
975	{
976	/* This is the target bus, pass the read to the device. */
977	PPDMPCIDEV pPciDev = pBus->apDevices[iDevice];
978	if (pPciDev)
979	{
980	u32Value = pPciDev->Int.s.pfnConfigRead(pPciDev->Int.s.CTX_SUFF(pDevIns), pPciDev, u32Address, cb);
981	Log(("%s: %s: u32Address=%02x u32Value=%08x cb=%d\n", __FUNCTION__, pPciDev->pszNameR3, u32Address, u32Value, cb));
982	}
983	else
984	ich9pciNoMem(&u32Value, 4);
985	}
986
987	return u32Value;
988	}
989
990
991	/**
992	* Common routine for restoring the config registers of a PCI device.
993	*
994	* @param pDev The PCI device.
995	* @param pbSrcConfig The configuration register values to be loaded.
996	* @param fIsBridge Whether this is a bridge device or not.
997	*/
998	void devpciR3CommonRestoreConfig(PPDMPCIDEV pDev, uint8_t const *pbSrcConfig, bool fIsBridge)
999	{
1000	/*
1001	* This table defines the fields for normal devices and bridge devices, and
1002	* the order in which they need to be restored.
1003	*/
1004	static const struct PciField
1005	{
1006	uint8_t off;
1007	uint8_t cb;
1008	uint8_t fWritable;
1009	uint8_t fBridge;
1010	const char *pszName;
1011	} s_aFields[] =
1012	{
1013	/* off,cb,fW,fB, pszName */
1014	{ 0x00, 2, 0, 3, "VENDOR_ID" },
1015	{ 0x02, 2, 0, 3, "DEVICE_ID" },
1016	{ 0x06, 2, 1, 3, "STATUS" },
1017	{ 0x08, 1, 0, 3, "REVISION_ID" },
1018	{ 0x09, 1, 0, 3, "CLASS_PROG" },
1019	{ 0x0a, 1, 0, 3, "CLASS_SUB" },
1020	{ 0x0b, 1, 0, 3, "CLASS_BASE" },
1021	{ 0x0c, 1, 1, 3, "CACHE_LINE_SIZE" },
1022	{ 0x0d, 1, 1, 3, "LATENCY_TIMER" },
1023	{ 0x0e, 1, 0, 3, "HEADER_TYPE" },
1024	{ 0x0f, 1, 1, 3, "BIST" },
1025	{ 0x10, 4, 1, 3, "BASE_ADDRESS_0" },
1026	{ 0x14, 4, 1, 3, "BASE_ADDRESS_1" },
1027	{ 0x18, 4, 1, 1, "BASE_ADDRESS_2" },
1028	{ 0x18, 1, 1, 2, "PRIMARY_BUS" }, // fWritable = ??
1029	{ 0x19, 1, 1, 2, "SECONDARY_BUS" }, // fWritable = ??
1030	{ 0x1a, 1, 1, 2, "SUBORDINATE_BUS" }, // fWritable = ??
1031	{ 0x1b, 1, 1, 2, "SEC_LATENCY_TIMER" }, // fWritable = ??
1032	{ 0x1c, 4, 1, 1, "BASE_ADDRESS_3" },
1033	{ 0x1c, 1, 1, 2, "IO_BASE" }, // fWritable = ??
1034	{ 0x1d, 1, 1, 2, "IO_LIMIT" }, // fWritable = ??
1035	{ 0x1e, 2, 1, 2, "SEC_STATUS" }, // fWritable = ??
1036	{ 0x20, 4, 1, 1, "BASE_ADDRESS_4" },
1037	{ 0x20, 2, 1, 2, "MEMORY_BASE" }, // fWritable = ??
1038	{ 0x22, 2, 1, 2, "MEMORY_LIMIT" }, // fWritable = ??
1039	{ 0x24, 4, 1, 1, "BASE_ADDRESS_5" },
1040	{ 0x24, 2, 1, 2, "PREF_MEMORY_BASE" }, // fWritable = ??
1041	{ 0x26, 2, 1, 2, "PREF_MEMORY_LIMIT" }, // fWritable = ??
1042	{ 0x28, 4, 1, 1, "CARDBUS_CIS" }, // fWritable = ??
1043	{ 0x28, 4, 1, 2, "PREF_BASE_UPPER32" }, // fWritable = ??
1044	{ 0x2c, 2, 0, 1, "SUBSYSTEM_VENDOR_ID" },// fWritable = !?
1045	{ 0x2c, 4, 1, 2, "PREF_LIMIT_UPPER32" },// fWritable = ??
1046	{ 0x2e, 2, 0, 1, "SUBSYSTEM_ID" }, // fWritable = !?
1047	{ 0x30, 4, 1, 1, "ROM_ADDRESS" }, // fWritable = ?!
1048	{ 0x30, 2, 1, 2, "IO_BASE_UPPER16" }, // fWritable = ?!
1049	{ 0x32, 2, 1, 2, "IO_LIMIT_UPPER16" }, // fWritable = ?!
1050	{ 0x34, 4, 0, 3, "CAPABILITY_LIST" }, // fWritable = !? cb=!?
1051	{ 0x38, 4, 1, 1, "RESERVED_38" }, // ???
1052	{ 0x38, 4, 1, 2, "ROM_ADDRESS_BR" }, // fWritable = !? cb=!? fBridge=!?
1053	{ 0x3c, 1, 1, 3, "INTERRUPT_LINE" }, // fBridge=??
1054	{ 0x3d, 1, 0, 3, "INTERRUPT_PIN" }, // fBridge=??
1055	{ 0x3e, 1, 0, 1, "MIN_GNT" },
1056	{ 0x3e, 2, 1, 2, "BRIDGE_CONTROL" }, // fWritable = !?
1057	{ 0x3f, 1, 0, 1, "MAX_LAT" },
1058	/* The COMMAND register must come last as it requires the ADDRESS
1059	registers to be restored before we pretent to change it from 0 to
1060	whatever value the guest assigned it. */
1061	{ 0x04, 2, 1, 3, "COMMAND" },
1062	};
1063
1064	#ifdef RT_STRICT
1065	/* Check that we've got full register coverage. */
1066	uint32_t bmDevice[0x40 / 32];
1067	uint32_t bmBridge[0x40 / 32];
1068	RT_ZERO(bmDevice);
1069	RT_ZERO(bmBridge);
1070	for (uint32_t i = 0; i < RT_ELEMENTS(s_aFields); i++)
1071	{
1072	uint8_t off = s_aFields[i].off;
1073	uint8_t cb = s_aFields[i].cb;
1074	uint8_t f = s_aFields[i].fBridge;
1075	while (cb-- > 0)
1076	{
1077	if (f & 1) AssertMsg(!ASMBitTest(bmDevice, off), ("%#x\n", off));
1078	if (f & 2) AssertMsg(!ASMBitTest(bmBridge, off), ("%#x\n", off));
1079	if (f & 1) ASMBitSet(bmDevice, off);
1080	if (f & 2) ASMBitSet(bmBridge, off);
1081	off++;
1082	}
1083	}
1084	for (uint32_t off = 0; off < 0x40; off++)
1085	{
1086	AssertMsg(ASMBitTest(bmDevice, off), ("%#x\n", off));
1087	AssertMsg(ASMBitTest(bmBridge, off), ("%#x\n", off));
1088	}
1089	#endif
1090
1091	/*
1092	* Loop thru the fields covering the 64 bytes of standard registers.
1093	*/
1094	uint8_t const fBridge = fIsBridge ? 2 : 1;
1095	Assert(!pciDevIsPassthrough(pDev));
1096	uint8_t *pbDstConfig = &pDev->abConfig[0];
1097
1098	for (uint32_t i = 0; i < RT_ELEMENTS(s_aFields); i++)
1099	if (s_aFields[i].fBridge & fBridge)
1100	{
1101	uint8_t const off = s_aFields[i].off;
1102	uint8_t const cb = s_aFields[i].cb;
1103	uint32_t u32Src;
1104	uint32_t u32Dst;
1105	switch (cb)
1106	{
1107	case 1:
1108	u32Src = pbSrcConfig[off];
1109	u32Dst = pbDstConfig[off];
1110	break;
1111	case 2:
1112	u32Src = (uint16_t const )&pbSrcConfig[off];
1113	u32Dst = (uint16_t const )&pbDstConfig[off];
1114	break;
1115	case 4:
1116	u32Src = (uint32_t const )&pbSrcConfig[off];
1117	u32Dst = (uint32_t const )&pbDstConfig[off];
1118	break;
1119	default:
1120	AssertFailed();
1121	continue;
1122	}
1123
1124	if ( u32Src != u32Dst
1125	\|\| off == VBOX_PCI_COMMAND)
1126	{
1127	if (u32Src != u32Dst)
1128	{
1129	if (!s_aFields[i].fWritable)
1130	LogRel(("PCI: %8s/%u: %2u-bit field %s: %x -> %x - !READ ONLY!\n",
1131	pDev->pszNameR3, pDev->Int.s.CTX_SUFF(pDevIns)->iInstance, cb*8, s_aFields[i].pszName, u32Dst, u32Src));
1132	else
1133	LogRel(("PCI: %8s/%u: %2u-bit field %s: %x -> %x\n",
1134	pDev->pszNameR3, pDev->Int.s.CTX_SUFF(pDevIns)->iInstance, cb*8, s_aFields[i].pszName, u32Dst, u32Src));
1135	}
1136	if (off == VBOX_PCI_COMMAND)
1137	PCIDevSetCommand(pDev, 0); /* For remapping, see ich9pciR3CommonLoadExec. */
1138	pDev->Int.s.pfnConfigWrite(pDev->Int.s.CTX_SUFF(pDevIns), pDev, off, u32Src, cb);
1139	}
1140	}
1141
1142	/*
1143	* The device dependent registers.
1144	*
1145	* We will not use ConfigWrite here as we have no clue about the size
1146	* of the registers, so the device is responsible for correctly
1147	* restoring functionality governed by these registers.
1148	*/
1149	for (uint32_t off = 0x40; off < sizeof(pDev->abConfig); off++)
1150	if (pbDstConfig[off] != pbSrcConfig[off])
1151	{
1152	LogRel(("PCI: %8s/%u: register %02x: %02x -> %02x\n",
1153	pDev->pszNameR3, pDev->Int.s.CTX_SUFF(pDevIns)->iInstance, off, pbDstConfig[off], pbSrcConfig[off])); /** @todo make this Log() later. */
1154	pbDstConfig[off] = pbSrcConfig[off];
1155	}
1156	}
1157
1158	/**
1159	* Common worker for ich9pciR3LoadExec and ich9pcibridgeR3LoadExec.
1160	*
1161	* @returns VBox status code.
1162	* @param pBus The bus which data is being loaded.
1163	* @param pSSM The saved state handle.
1164	* @param uVersion The data version.
1165	* @param uPass The pass.
1166	*/
1167	static DECLCALLBACK(int) ich9pciR3CommonLoadExec(PDEVPCIBUS pBus, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1168	{
1169	uint32_t u32;
1170	uint32_t i;
1171	int rc;
1172
1173	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
1174	if (uVersion != VBOX_ICH9PCI_SAVED_STATE_VERSION_CURRENT)
1175	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1176
1177	/*
1178	* Iterate thru all the devices and write 0 to the COMMAND register so
1179	* that all the memory is unmapped before we start restoring the saved
1180	* mapping locations.
1181	*
1182	* The register value is restored afterwards so we can do proper
1183	* LogRels in devpciR3CommonRestoreConfig.
1184	*/
1185	for (i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
1186	{
1187	PPDMPCIDEV pDev = pBus->apDevices[i];
1188	if (pDev)
1189	{
1190	uint16_t u16 = PCIDevGetCommand(pDev);
1191	pDev->Int.s.pfnConfigWrite(pDev->Int.s.CTX_SUFF(pDevIns), pDev, VBOX_PCI_COMMAND, 0, 2);
1192	PCIDevSetCommand(pDev, u16);
1193	Assert(PCIDevGetCommand(pDev) == u16);
1194	}
1195	}
1196
1197	void *pvMsixPage = RTMemTmpAllocZ(0x1000);
1198	AssertReturn(pvMsixPage, VERR_NO_TMP_MEMORY);
1199
1200	/*
1201	* Iterate all the devices.
1202	*/
1203	for (i = 0;; i++)
1204	{
1205	PPDMPCIDEV pDev;
1206	PDMPCIDEV DevTmp;
1207
1208	/* index / terminator */
1209	rc = SSMR3GetU32(pSSM, &u32);
1210	if (RT_FAILURE(rc))
1211	break;
1212	if (u32 == (uint32_t)~0)
1213	break;
1214	AssertMsgBreak(u32 < RT_ELEMENTS(pBus->apDevices) && u32 >= i, ("u32=%#x i=%#x\n", u32, i));
1215
1216	/* skip forward to the device checking that no new devices are present. */
1217	for (; i < u32; i++)
1218	{
1219	pDev = pBus->apDevices[i];
1220	if (pDev)
1221	{
1222	LogRel(("PCI: New device in slot %#x, %s (vendor=%#06x device=%#06x)\n", i, pDev->pszNameR3,
1223	PCIDevGetVendorId(pDev), PCIDevGetDeviceId(pDev)));
1224	if (SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT)
1225	{
1226	rc = SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("New device in slot %#x, %s (vendor=%#06x device=%#06x)"),
1227	i, pDev->pszNameR3, PCIDevGetVendorId(pDev), PCIDevGetDeviceId(pDev));
1228	break;
1229	}
1230	}
1231	}
1232	if (RT_FAILURE(rc))
1233	break;
1234
1235	/* get the data */
1236	DevTmp.Int.s.fFlags = 0;
1237	DevTmp.Int.s.u8MsiCapOffset = 0;
1238	DevTmp.Int.s.u8MsiCapSize = 0;
1239	DevTmp.Int.s.u8MsixCapOffset = 0;
1240	DevTmp.Int.s.u8MsixCapSize = 0;
1241	DevTmp.Int.s.uIrqPinState = ~0; /* Invalid value in case we have an older saved state to force a state change in pciSetIrq. */
1242	SSMR3GetMem(pSSM, DevTmp.abConfig, sizeof(DevTmp.abConfig));
1243
1244	SSMR3GetU32(pSSM, &DevTmp.Int.s.fFlags);
1245	SSMR3GetS32(pSSM, &DevTmp.Int.s.uIrqPinState);
1246	SSMR3GetU8(pSSM, &DevTmp.Int.s.u8MsiCapOffset);
1247	SSMR3GetU8(pSSM, &DevTmp.Int.s.u8MsiCapSize);
1248	SSMR3GetU8(pSSM, &DevTmp.Int.s.u8MsixCapOffset);
1249	rc = SSMR3GetU8(pSSM, &DevTmp.Int.s.u8MsixCapSize);
1250	if (RT_FAILURE(rc))
1251	break;
1252
1253	/* Load MSI-X page state */
1254	if (DevTmp.Int.s.u8MsixCapOffset != 0)
1255	{
1256	Assert(pvMsixPage != NULL);
1257	rc = SSMR3GetMem(pSSM, pvMsixPage, 0x1000);
1258	if (RT_FAILURE(rc))
1259	break;
1260	}
1261
1262	/* check that it's still around. */
1263	pDev = pBus->apDevices[i];
1264	if (!pDev)
1265	{
1266	LogRel(("PCI: Device in slot %#x has been removed! vendor=%#06x device=%#06x\n", i,
1267	PCIDevGetVendorId(&DevTmp), PCIDevGetDeviceId(&DevTmp)));
1268	if (SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT)
1269	{
1270	rc = SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Device in slot %#x has been removed! vendor=%#06x device=%#06x"),
1271	i, PCIDevGetVendorId(&DevTmp), PCIDevGetDeviceId(&DevTmp));
1272	break;
1273	}
1274	continue;
1275	}
1276
1277	/* match the vendor id assuming that this will never be changed. */
1278	if (PCIDevGetVendorId(&DevTmp) != PCIDevGetVendorId(pDev))
1279	{
1280	rc = SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Device in slot %#x (%s) vendor id mismatch! saved=%.4Rhxs current=%.4Rhxs"),
1281	i, pDev->pszNameR3, PCIDevGetVendorId(&DevTmp), PCIDevGetVendorId(pDev));
1282	break;
1283	}
1284
1285	/* commit the loaded device config. */
1286	Assert(!pciDevIsPassthrough(pDev));
1287	devpciR3CommonRestoreConfig(pDev, &DevTmp.abConfig[0], false ); /** @todo fix bridge fun! */
1288
1289	pDev->Int.s.uIrqPinState = DevTmp.Int.s.uIrqPinState;
1290	pDev->Int.s.u8MsiCapOffset = DevTmp.Int.s.u8MsiCapOffset;
1291	pDev->Int.s.u8MsiCapSize = DevTmp.Int.s.u8MsiCapSize;
1292	pDev->Int.s.u8MsixCapOffset = DevTmp.Int.s.u8MsixCapOffset;
1293	pDev->Int.s.u8MsixCapSize = DevTmp.Int.s.u8MsixCapSize;
1294	if (DevTmp.Int.s.u8MsixCapSize != 0)
1295	{
1296	Assert(pDev->Int.s.pMsixPageR3 != NULL);
1297	memcpy(pDev->Int.s.pMsixPageR3, pvMsixPage, 0x1000);
1298	}
1299	}
1300
1301	RTMemTmpFree(pvMsixPage);
1302
1303	return rc;
1304	}
1305
1306	static DECLCALLBACK(int) ich9pciR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1307	{
1308	PDEVPCIROOT pThis = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
1309	PDEVPCIBUS pBus = &pThis->PciBus;
1310	uint32_t u32;
1311	int rc;
1312
1313	/* We ignore this version as there's no saved state with it anyway */
1314	if (uVersion == VBOX_ICH9PCI_SAVED_STATE_VERSION_NOMSI)
1315	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1316	if (uVersion > VBOX_ICH9PCI_SAVED_STATE_VERSION_MSI)
1317	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1318
1319	/*
1320	* Bus state data.
1321	*/
1322	SSMR3GetU32(pSSM, &pThis->uConfigReg);
1323
1324	/*
1325	* Load IRQ states.
1326	*/
1327	for (unsigned i = 0; i < RT_ELEMENTS(pThis->auPciApicIrqLevels); i++)
1328	SSMR3GetU32(pSSM, (uint32_t*)&pThis->auPciApicIrqLevels[i]);
1329
1330	/* separator */
1331	rc = SSMR3GetU32(pSSM, &u32);
1332	if (RT_FAILURE(rc))
1333	return rc;
1334	if (u32 != (uint32_t)~0)
1335	AssertMsgFailedReturn(("u32=%#x\n", u32), rc);
1336
1337	return ich9pciR3CommonLoadExec(pBus, pSSM, uVersion, uPass);
1338	}
1339
1340	static DECLCALLBACK(int) ich9pcibridgeR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1341	{
1342	PDEVPCIBUS pThis = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
1343	if (uVersion > VBOX_ICH9PCI_SAVED_STATE_VERSION_MSI)
1344	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1345	return ich9pciR3CommonLoadExec(pThis, pSSM, uVersion, uPass);
1346	}
1347
1348
1349	/*
1350	* Perform imeediate read of configuration space register.
1351	* Cannot be rescheduled, as already in R3.
1352	*/
1353	static uint32_t ich9pciConfigRead(PDEVPCIROOT pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t len)
1354	{
1355	PciAddress aPciAddr;
1356	aPciAddr.iBus = uBus;
1357	aPciAddr.iDeviceFunc = uDevFn;
1358	aPciAddr.iRegister = addr;
1359
1360	uint32_t u32Val;
1361	int rc = ich9pciDataReadAddr(pGlobals, &aPciAddr, len, &u32Val, VERR_INTERNAL_ERROR);
1362	AssertRC(rc);
1363
1364	return u32Val;
1365	}
1366
1367
1368	/*
1369	* Perform imeediate write to configuration space register.
1370	* Cannot be rescheduled, as already in R3.
1371	*/
1372	static void ich9pciConfigWrite(PDEVPCIROOT pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t val, uint32_t len)
1373	{
1374	PciAddress aPciAddr;
1375	aPciAddr.iBus = uBus;
1376	aPciAddr.iDeviceFunc = uDevFn;
1377	aPciAddr.iRegister = addr;
1378
1379	int rc = ich9pciDataWriteAddr(pGlobals, &aPciAddr, val, len, VERR_INTERNAL_ERROR);
1380	AssertRC(rc);
1381	}
1382
1383
1384	static void ich9pciSetRegionAddress(PDEVPCIROOT pGlobals, uint8_t uBus, uint8_t uDevFn, int iRegion, uint64_t addr)
1385	{
1386	uint32_t uReg = ich9pciGetRegionReg(iRegion);
1387
1388	/* Read memory type first. */
1389	uint8_t uResourceType = ich9pciConfigRead(pGlobals, uBus, uDevFn, uReg, 1);
1390	bool f64Bit = (uResourceType & ((uint8_t)(PCI_ADDRESS_SPACE_BAR64 \| PCI_ADDRESS_SPACE_IO)))
1391	== PCI_ADDRESS_SPACE_BAR64;
1392
1393	Log(("Set region address: %02x:%02x.%d region %d address=%RX64%s\n",
1394	uBus, uDevFn >> 3, uDevFn & 7, iRegion, addr, f64Bit ? " (64-bit)" : ""));
1395
1396	/* Write address of the device. */
1397	ich9pciConfigWrite(pGlobals, uBus, uDevFn, uReg, (uint32_t)addr, 4);
1398	if (f64Bit)
1399	ich9pciConfigWrite(pGlobals, uBus, uDevFn, uReg + 4, (uint32_t)(addr >> 32), 4);
1400	}
1401
1402
1403	static void ich9pciBiosInitBridge(PDEVPCIROOT pGlobals, uint8_t uBus, uint8_t uDevFn)
1404	{
1405	Log(("BIOS init bridge: %02x::%02x.%d\n", uBus, uDevFn >> 3, uDevFn & 7));
1406
1407	/*
1408	* The I/O range for the bridge must be aligned to a 4KB boundary.
1409	* This does not change anything really as the access to the device is not going
1410	* through the bridge but we want to be compliant to the spec.
1411	*/
1412	if ((pGlobals->uPciBiosIo % 4096) != 0)
1413	{
1414	pGlobals->uPciBiosIo = RT_ALIGN_32(pGlobals->uPciBiosIo, 4*1024);
1415	Log(("%s: Aligned I/O start address. New address %#x\n", __FUNCTION__, pGlobals->uPciBiosIo));
1416	}
1417	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_IO_BASE, (pGlobals->uPciBiosIo >> 8) & 0xf0, 1);
1418
1419	/* The MMIO range for the bridge must be aligned to a 1MB boundary. */
1420	if ((pGlobals->uPciBiosMmio % (1024 * 1024)) != 0)
1421	{
1422	pGlobals->uPciBiosMmio = RT_ALIGN_32(pGlobals->uPciBiosMmio, 1024*1024);
1423	Log(("%s: Aligned MMIO start address. New address %#x\n", __FUNCTION__, pGlobals->uPciBiosMmio));
1424	}
1425	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_MEMORY_BASE, (pGlobals->uPciBiosMmio >> 16) & UINT32_C(0xffff0), 2);
1426
1427	/* Save values to compare later to. */
1428	uint32_t u32IoAddressBase = pGlobals->uPciBiosIo;
1429	uint32_t u32MMIOAddressBase = pGlobals->uPciBiosMmio;
1430	uint8_t uBridgeBus = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_SECONDARY_BUS, 1);
1431
1432	/* Init devices behind the bridge and possibly other bridges as well. */
1433	for (int iDev = 0; iDev <= 255; iDev++)
1434	ich9pciBiosInitDevice(pGlobals, uBridgeBus, iDev);
1435
1436	/*
1437	* Set I/O limit register. If there is no device with I/O space behind the bridge
1438	* we set a lower value than in the base register.
1439	* The result with a real bridge is that no I/O transactions are passed to the secondary
1440	* interface. Again this doesn't really matter here but we want to be compliant to the spec.
1441	*/
1442	if ((u32IoAddressBase != pGlobals->uPciBiosIo) && ((pGlobals->uPciBiosIo % 4096) != 0))
1443	{
1444	/* The upper boundary must be one byte less than a 4KB boundary. */
1445	pGlobals->uPciBiosIo = RT_ALIGN_32(pGlobals->uPciBiosIo, 4*1024);
1446	}
1447
1448	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_IO_LIMIT, ((pGlobals->uPciBiosIo >> 8) & 0xf0) - 1, 1);
1449
1450	/* Same with the MMIO limit register but with 1MB boundary here. */
1451	if ((u32MMIOAddressBase != pGlobals->uPciBiosMmio) && ((pGlobals->uPciBiosMmio % (1024 * 1024)) != 0))
1452	{
1453	/* The upper boundary must be one byte less than a 1MB boundary. */
1454	pGlobals->uPciBiosMmio = RT_ALIGN_32(pGlobals->uPciBiosMmio, 1024*1024);
1455	}
1456	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_MEMORY_LIMIT, ((pGlobals->uPciBiosMmio >> 16) & UINT32_C(0xfff0)) - 1, 2);
1457
1458	/*
1459	* Set the prefetch base and limit registers. We currently have no device with a prefetchable region
1460	* which may be behind a bridge. That's why it is unconditionally disabled here atm by writing a higher value into
1461	* the base register than in the limit register.
1462	*/
1463	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_MEMORY_BASE, 0xfff0, 2);
1464	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_MEMORY_LIMIT, 0x0, 2);
1465	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_BASE_UPPER32, 0x00, 4);
1466	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_LIMIT_UPPER32, 0x00, 4);
1467	}
1468
1469	static void ich9pciBiosInitDevice(PDEVPCIROOT pGlobals, uint8_t uBus, uint8_t uDevFn)
1470	{
1471	uint16_t uDevClass, uVendor, uDevice;
1472	uint8_t uCmd;
1473
1474	uDevClass = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_CLASS_DEVICE, 2);
1475	uVendor = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_VENDOR_ID, 2);
1476	uDevice = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_DEVICE_ID, 2);
1477
1478	/* If device is present */
1479	if (uVendor == 0xffff)
1480	return;
1481
1482	Log(("BIOS init device: %02x:%02x.%d\n", uBus, uDevFn >> 3, uDevFn & 7));
1483
1484	switch (uDevClass)
1485	{
1486	case 0x0101:
1487	/* IDE controller */
1488	ich9pciConfigWrite(pGlobals, uBus, uDevFn, 0x40, 0x8000, 2); /* enable IDE0 */
1489	ich9pciConfigWrite(pGlobals, uBus, uDevFn, 0x42, 0x8000, 2); /* enable IDE1 */
1490	goto default_map;
1491	break;
1492	case 0x0300:
1493	/* VGA controller */
1494
1495	/* NB: Default Bochs VGA LFB address is 0xE0000000. Old guest
1496	* software may break if the framebuffer isn't mapped there.
1497	*/
1498
1499	/*
1500	* Legacy VGA I/O ports are implicitly decoded by a VGA class device. But
1501	* only the framebuffer (i.e., a memory region) is explicitly registered via
1502	* ich9pciSetRegionAddress, so don't forget to enable I/O decoding.
1503	*/
1504	uCmd = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_COMMAND, 1);
1505	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_COMMAND,
1506	uCmd \| PCI_COMMAND_IOACCESS,
1507	1);
1508	goto default_map;
1509	break;
1510	case 0x0604:
1511	/* PCI-to-PCI bridge. */
1512	AssertMsg(pGlobals->uPciBiosBus < 255, ("Too many bridges on the bus\n"));
1513	ich9pciBiosInitBridge(pGlobals, uBus, uDevFn);
1514	break;
1515	default:
1516	default_map:
1517	{
1518	/* default memory mappings */
1519	bool fActiveMemRegion = false;
1520	bool fActiveIORegion = false;
1521	/*
1522	* We ignore ROM region here.
1523	*/
1524	for (int iRegion = 0; iRegion < VBOX_PCI_NUM_REGIONS - 1; iRegion++)
1525	{
1526	uint32_t u32Address = ich9pciGetRegionReg(iRegion);
1527
1528	/* Calculate size - we write all 1s into the BAR, and then evaluate which bits
1529	are cleared. */
1530	uint8_t u8ResourceType = ich9pciConfigRead(pGlobals, uBus, uDevFn, u32Address, 1);
1531
1532	bool f64Bit = (u8ResourceType & ((uint8_t)(PCI_ADDRESS_SPACE_BAR64 \| PCI_ADDRESS_SPACE_IO)))
1533	== PCI_ADDRESS_SPACE_BAR64;
1534	bool fIsPio = ((u8ResourceType & PCI_COMMAND_IOACCESS) == PCI_COMMAND_IOACCESS);
1535	uint64_t cbRegSize64 = 0;
1536
1537	if (f64Bit)
1538	{
1539	ich9pciConfigWrite(pGlobals, uBus, uDevFn, u32Address, UINT32_C(0xffffffff), 4);
1540	ich9pciConfigWrite(pGlobals, uBus, uDevFn, u32Address+4, UINT32_C(0xffffffff), 4);
1541	cbRegSize64 = ich9pciConfigRead(pGlobals, uBus, uDevFn, u32Address, 4);
1542	cbRegSize64 \|= ((uint64_t)ich9pciConfigRead(pGlobals, uBus, uDevFn, u32Address+4, 4) << 32);
1543	cbRegSize64 &= ~UINT64_C(0x0f);
1544	cbRegSize64 = (~cbRegSize64) + 1;
1545
1546	/* No 64-bit PIO regions possible. */
1547	#ifndef DEBUG_bird /* EFI triggers this for DevAHCI. */
1548	AssertMsg((u8ResourceType & PCI_COMMAND_IOACCESS) == 0, ("type=%#x rgn=%d\n", u8ResourceType, iRegion));
1549	#endif
1550	}
1551	else
1552	{
1553	uint32_t cbRegSize32;
1554	ich9pciConfigWrite(pGlobals, uBus, uDevFn, u32Address, UINT32_C(0xffffffff), 4);
1555	cbRegSize32 = ich9pciConfigRead(pGlobals, uBus, uDevFn, u32Address, 4);
1556
1557	/* Clear resource information depending on resource type. */
1558	if (fIsPio) /* PIO */
1559	cbRegSize32 &= ~UINT32_C(0x01);
1560	else /* MMIO */
1561	cbRegSize32 &= ~UINT32_C(0x0f);
1562
1563	/*
1564	* Invert all bits and add 1 to get size of the region.
1565	* (From PCI implementation note)
1566	*/
1567	if (fIsPio && (cbRegSize32 & UINT32_C(0xffff0000)) == 0)
1568	cbRegSize32 = (~(cbRegSize32 \| UINT32_C(0xffff0000))) + 1;
1569	else
1570	cbRegSize32 = (~cbRegSize32) + 1;
1571
1572	cbRegSize64 = cbRegSize32;
1573	}
1574	Log2(("%s: Size of region %u for device %d on bus %d is %lld\n", __FUNCTION__, iRegion, uDevFn, uBus, cbRegSize64));
1575
1576	if (cbRegSize64)
1577	{
1578	/* Try 32-bit base first. */
1579	uint32_t* paddr = fIsPio ? &pGlobals->uPciBiosIo : &pGlobals->uPciBiosMmio;
1580	uint64_t uNew = *paddr;
1581	/* Align starting address to region size. */
1582	uNew = (uNew + cbRegSize64 - 1) & ~(cbRegSize64 - 1);
1583	if (fIsPio)
1584	uNew &= UINT32_C(0xffff);
1585	/* Unconditionally exclude I/O-APIC/HPET/ROM. Pessimistic, but better than causing a mess. */
1586	if ( !uNew
1587	\|\| (uNew <= UINT32_C(0xffffffff) && uNew + cbRegSize64 - 1 >= UINT32_C(0xfec00000))
1588	\|\| uNew >= _4G)
1589	{
1590	if (f64Bit)
1591	{
1592	/* Map a 64-bit region above 4GB. */
1593	Assert(!fIsPio);
1594	uNew = pGlobals->uPciBiosMmio64;
1595	/* Align starting address to region size. */
1596	uNew = (uNew + cbRegSize64 - 1) & ~(cbRegSize64 - 1);
1597	LogFunc(("Start address of 64-bit MMIO region %u/%u is %#llx\n", iRegion, iRegion + 1, uNew));
1598	ich9pciSetRegionAddress(pGlobals, uBus, uDevFn, iRegion, uNew);
1599	fActiveMemRegion = true;
1600	pGlobals->uPciBiosMmio64 = uNew + cbRegSize64;
1601	Log2Func(("New 64-bit address is %#llx\n", pGlobals->uPciBiosMmio64));
1602	}
1603	else
1604	{
1605	LogRel(("PCI: no space left for BAR%u of device %u/%u/%u (vendor=%#06x device=%#06x)\n",
1606	iRegion, uBus, uDevFn >> 3, uDevFn & 7, uVendor, uDevice)); /** @todo make this a VM start failure later. */
1607	/* Undo the mapping mess caused by the size probing. */
1608	ich9pciConfigWrite(pGlobals, uBus, uDevFn, u32Address, UINT32_C(0), 4);
1609	}
1610	}
1611	else
1612	{
1613	LogFunc(("Start address of %s region %u is %#x\n", (fIsPio ? "I/O" : "MMIO"), iRegion, uNew));
1614	ich9pciSetRegionAddress(pGlobals, uBus, uDevFn, iRegion, uNew);
1615	if (fIsPio)
1616	fActiveIORegion = true;
1617	else
1618	fActiveMemRegion = true;
1619	*paddr = uNew + cbRegSize64;
1620	Log2Func(("New 32-bit address is %#x\n", *paddr));
1621	}
1622
1623	if (f64Bit)
1624	iRegion++; /* skip next region */
1625	}
1626	}
1627
1628	/* Update the command word appropriately. */
1629	uCmd = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_COMMAND, 2);
1630	if (fActiveMemRegion)
1631	uCmd \|= PCI_COMMAND_MEMACCESS; /* Enable MMIO access. */
1632	if (fActiveIORegion)
1633	uCmd \|= PCI_COMMAND_IOACCESS; /* Enable I/O space access. */
1634	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_COMMAND, uCmd, 2);
1635	break;
1636	}
1637	}
1638
1639	/* map the interrupt */
1640	uint32_t iPin = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_INTERRUPT_PIN, 1);
1641	if (iPin != 0)
1642	{
1643	iPin--;
1644
1645	if (uBus != 0)
1646	{
1647	/* Find bus this device attached to. */
1648	PDEVPCIBUS pBus = &pGlobals->PciBus;
1649	while (1)
1650	{
1651	PPDMPCIDEV pBridge = ich9pciFindBridge(pBus, uBus);
1652	if (!pBridge)
1653	{
1654	Assert(false);
1655	break;
1656	}
1657	if (uBus == PDMPciDevGetByte(pBridge, VBOX_PCI_SECONDARY_BUS))
1658	{
1659	/* OK, found bus this device attached to. */
1660	break;
1661	}
1662	pBus = PDMINS_2_DATA(pBridge->Int.s.CTX_SUFF(pDevIns), PDEVPCIBUS);
1663	}
1664
1665	/* We need to go up to the host bus to see which irq pin this
1666	* device will use there. See logic in ich9pcibridgeSetIrq().
1667	*/
1668	while (pBus->iBus != 0)
1669	{
1670	/* Get the pin the device would assert on the bridge. */
1671	iPin = ((pBus->PciDev.uDevFn >> 3) + iPin) & 3;
1672	pBus = pBus->PciDev.Int.s.pBusR3;
1673	};
1674	}
1675
1676	int iIrq = aPciIrqs[ich9pciSlotGetPirq(uBus, uDevFn, iPin)];
1677	Log(("Using pin %d and IRQ %d for device %02x:%02x.%d\n",
1678	iPin, iIrq, uBus, uDevFn>>3, uDevFn&7));
1679	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_INTERRUPT_LINE, iIrq, 1);
1680	}
1681	}
1682
1683	/**
1684	* Initializes bridges registers used for routing.
1685	*
1686	* @returns nothing.
1687	* @param pGlobals Global device instance data used to generate unique bus numbers.
1688	* @param pBus The PCI bus to initialize.
1689	* @param uBusPrimary The primary bus number the bus is connected to.
1690	* @param uBusSecondary The secondary bus number, i.e. the bus number behind the bridge.
1691	*/
1692	static void ich9pciInitBridgeTopology(PDEVPCIROOT pGlobals, PDEVPCIBUS pBus, unsigned uBusPrimary,
1693	unsigned uBusSecondary)
1694	{
1695	PPDMPCIDEV pBridgeDev = &pBus->PciDev;
1696
1697	/* Set only if we are not on the root bus, it has no primary bus attached. */
1698	if (uBusSecondary != 0)
1699	{
1700	PCIDevSetByte(pBridgeDev, VBOX_PCI_PRIMARY_BUS, uBusPrimary);
1701	PCIDevSetByte(pBridgeDev, VBOX_PCI_SECONDARY_BUS, uBusSecondary);
1702	}
1703
1704	for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
1705	{
1706	PPDMPCIDEV pBridge = pBus->papBridgesR3[iBridge];
1707	AssertMsg(pBridge && pciDevIsPci2PciBridge(pBridge),
1708	("Device is not a PCI bridge but on the list of PCI bridges\n"));
1709	PDEVPCIBUS pChildBus = PDMINS_2_DATA(pBridge->Int.s.CTX_SUFF(pDevIns), PDEVPCIBUS);
1710	pGlobals->uPciBiosBus++;
1711	ich9pciInitBridgeTopology(pGlobals, pChildBus, uBusSecondary, pGlobals->uPciBiosBus);
1712	}
1713	PCIDevSetByte(pBridgeDev, VBOX_PCI_SUBORDINATE_BUS, pGlobals->uPciBiosBus);
1714	Log2(("ich9pciInitBridgeTopology: for bus %p: primary=%d secondary=%d subordinate=%d\n",
1715	pBus,
1716	PDMPciDevGetByte(pBridgeDev, VBOX_PCI_PRIMARY_BUS),
1717	PDMPciDevGetByte(pBridgeDev, VBOX_PCI_SECONDARY_BUS),
1718	PDMPciDevGetByte(pBridgeDev, VBOX_PCI_SUBORDINATE_BUS)
1719	));
1720	}
1721
1722
1723	static DECLCALLBACK(int) ich9pciFakePCIBIOS(PPDMDEVINS pDevIns)
1724	{
1725	PDEVPCIROOT pGlobals = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
1726	PVM pVM = PDMDevHlpGetVM(pDevIns);
1727	uint32_t const cbBelow4GB = MMR3PhysGetRamSizeBelow4GB(pVM);
1728	uint64_t const cbAbove4GB = MMR3PhysGetRamSizeAbove4GB(pVM);
1729
1730	/*
1731	* Set the start addresses.
1732	*/
1733	pGlobals->uPciBiosBus = 0;
1734	pGlobals->uPciBiosIo = 0xd000;
1735	pGlobals->uPciBiosMmio = cbBelow4GB;
1736	pGlobals->uPciBiosMmio64 = cbAbove4GB + _4G;
1737
1738	/* NB: Assume that if MMIO range is enabled, it is at the bottom of the memory hole. */
1739	if (pGlobals->u64PciConfigMMioAddress)
1740	{
1741	AssertRelease(pGlobals->u64PciConfigMMioAddress >= cbBelow4GB);
1742	pGlobals->uPciBiosMmio = pGlobals->u64PciConfigMMioAddress + pGlobals->u64PciConfigMMioLength;
1743	}
1744	Log(("cbBelow4GB: %lX, uPciBiosMmio: %lX, cbAbove4GB: %llX\n", cbBelow4GB, pGlobals->uPciBiosMmio, cbAbove4GB));
1745
1746	/*
1747	* Assign bridge topology, for further routing to work.
1748	*/
1749	PDEVPCIBUS pBus = &pGlobals->PciBus;
1750	ich9pciInitBridgeTopology(pGlobals, pBus, 0, 0);
1751
1752	/*
1753	* Init the devices.
1754	*/
1755	for (int i = 0; i < 256; i++)
1756	ich9pciBiosInitDevice(pGlobals, 0, i);
1757
1758	return VINF_SUCCESS;
1759	}
1760
1761
1762	/**
1763	* @callback_method_impl{PFNPCICONFIGREAD, Default config space read callback.}
1764	*/
1765	DECLCALLBACK(uint32_t) devpciR3CommonDefaultConfigRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress, unsigned cb)
1766	{
1767	NOREF(pDevIns);
1768
1769	uint32_t uValue;
1770	if (uAddress + cb <= 256)
1771	{
1772	switch (cb)
1773	{
1774	case 1:
1775	uValue = PDMPciDevGetByte(pPciDev, uAddress);
1776	break;
1777	case 2:
1778	uValue = PDMPciDevGetWord(pPciDev, uAddress);
1779	break;
1780	case 4:
1781	uValue = PDMPciDevGetDWord(pPciDev, uAddress);
1782	break;
1783	default:
1784	AssertFailed();
1785	uValue = 0;
1786	break;
1787	}
1788
1789	#ifdef LOG_ENABLED
1790	if ( pciDevIsMsiCapable(pPciDev)
1791	&& uAddress - (uint32_t)pPciDev->Int.s.u8MsiCapOffset < (uint32_t)pPciDev->Int.s.u8MsiCapSize )
1792	Log2(("devpciR3CommonDefaultConfigRead: MSI CAP: %#x LB %u -> %#x\n", uAddress - (uint32_t)pPciDev->Int.s.u8MsiCapOffset, cb, uValue));
1793	else if ( pciDevIsMsixCapable(pPciDev)
1794	&& uAddress - (uint32_t)pPciDev->Int.s.u8MsixCapOffset < (uint32_t)pPciDev->Int.s.u8MsixCapSize)
1795	Log2(("devpciR3CommonDefaultConfigRead: MSI-X CAP: %#x LB %u -> %#x\n", uAddress - (uint32_t)pPciDev->Int.s.u8MsiCapOffset, cb, uValue));
1796	#endif
1797	}
1798	else
1799	{
1800	if (uAddress + cb < 4096)
1801	LogRel(("PCI: %8s/%u: Read from extended register %d fallen back to generic code\n",
1802	pPciDev->pszNameR3, pPciDev->Int.s.CTX_SUFF(pDevIns)->iInstance, uAddress));
1803	else
1804	AssertFailed();
1805	uValue = 0;
1806	}
1807	return uValue;
1808	}
1809
1810	/**
1811	* Worker for ich9pciResetDevice and devpciR3UpdateMappings that unmaps a region.
1812	*
1813	* @returns VBox status code.
1814	* @param pDev The PCI device.
1815	* @param iRegion The region to unmap.
1816	*/
1817	static int ich9pciUnmapRegion(PPDMPCIDEV pDev, int iRegion)
1818	{
1819	PCIIORegion *pRegion = &pDev->Int.s.aIORegions[iRegion];
1820	AssertReturn(pRegion->size != 0, VINF_SUCCESS);
1821
1822	int rc;
1823	if (pRegion->addr == INVALID_PCI_ADDRESS)
1824	rc = VINF_SUCCESS;
1825	else
1826	{
1827	if (pRegion->type & PCI_ADDRESS_SPACE_IO)
1828	{
1829	/* Port IO */
1830	rc = PDMDevHlpIOPortDeregister(pDev->Int.s.pDevInsR3, pRegion->addr, pRegion->size);
1831	AssertRC(rc);
1832	}
1833	else
1834	{
1835	PDEVPCIBUS pBus = pDev->Int.s.CTX_SUFF(pBus);
1836	RTGCPHYS GCPhysBase = pRegion->addr;
1837	if (pBus->pPciHlpR3->pfnIsMMIOExBase(pBus->pDevInsR3, pDev->Int.s.pDevInsR3, GCPhysBase))
1838	{
1839	/* unmap it. */
1840	rc = pRegion->map_func(pDev->Int.s.pDevInsR3, pDev, iRegion,
1841	NIL_RTGCPHYS, pRegion->size, (PCIADDRESSSPACE)(pRegion->type));
1842	AssertRC(rc);
1843	rc = PDMDevHlpMMIOExUnmap(pDev->Int.s.pDevInsR3, pDev, iRegion, GCPhysBase);
1844	}
1845	else
1846	rc = PDMDevHlpMMIODeregister(pDev->Int.s.pDevInsR3, GCPhysBase, pRegion->size);
1847	}
1848	pRegion->addr = INVALID_PCI_ADDRESS;
1849	}
1850	return rc;
1851	}
1852
1853	static void devpciR3UpdateMappings(PDMPCIDEV* pDev)
1854	{
1855	uint16_t const u16Cmd = ich9pciGetWord(pDev, VBOX_PCI_COMMAND);
1856	for (unsigned iRegion = 0; iRegion < VBOX_PCI_NUM_REGIONS; iRegion++)
1857	{
1858	PCIIORegion *pRegion = &pDev->Int.s.aIORegions[iRegion];
1859	uint64_t const cbRegion = pRegion->size;
1860	if (cbRegion != 0)
1861	{
1862	uint32_t const offCfgReg = ich9pciGetRegionReg(iRegion);
1863	bool const f64Bit = (pRegion->type & ((uint8_t)(PCI_ADDRESS_SPACE_BAR64 \| PCI_ADDRESS_SPACE_IO)))
1864	== PCI_ADDRESS_SPACE_BAR64;
1865	uint64_t uNew = INVALID_PCI_ADDRESS;
1866
1867	/*
1868	* Port I/O region. Check if mapped and within 1..65535 range.
1869	*/
1870	if (pRegion->type & PCI_ADDRESS_SPACE_IO)
1871	{
1872	if (u16Cmd & PCI_COMMAND_IOACCESS)
1873	{
1874	uint32_t uIoBase = ich9pciGetDWord(pDev, offCfgReg);
1875	uIoBase &= ~(uint32_t)(cbRegion - 1);
1876
1877	uint64_t uLast = cbRegion - 1 + uIoBase;
1878	if ( uLast < _64K
1879	&& uIoBase < uLast
1880	&& uIoBase > 0)
1881	uNew = uIoBase;
1882	}
1883	}
1884	/*
1885	* MMIO or ROM. Check ROM enable bit and range.
1886	*
1887	* Note! We exclude the I/O-APIC/HPET/ROM area at the end of the first 4GB to
1888	* prevent the (fake) PCI BIOS and others from making a mess. Pure paranoia.
1889	*/
1890	else if (u16Cmd & PCI_COMMAND_MEMACCESS)
1891	{
1892	uint64_t uMemBase = ich9pciGetDWord(pDev, offCfgReg);
1893	if (f64Bit)
1894	{
1895	Assert(iRegion < VBOX_PCI_ROM_SLOT);
1896	uMemBase \|= (uint64_t)ich9pciGetDWord(pDev, offCfgReg + 4) << 32;
1897	}
1898	if ( iRegion != PCI_ROM_SLOT
1899	\|\| (uMemBase & RT_BIT_32(0))) /* ROM enable bit. */
1900	{
1901	uMemBase &= ~(cbRegion - 1);
1902
1903	uint64_t uLast = uNew + cbRegion - 1;
1904	if ( uMemBase < uLast
1905	&& uMemBase > 0
1906	&& !( uNew <= UINT32_C(0xffffffff)
1907	&& uLast >= UINT32_C(0xfec00000)) )
1908	uNew = uMemBase;
1909	}
1910	}
1911
1912	/*
1913	* Do real unmapping and/or mapping if the address change.
1914	*/
1915	if (uNew != pRegion->addr)
1916	{
1917	LogRel2(("PCI: config dev %u/%u (%s) BAR%i: %#RX64 -> %#RX64 (LB %RX64 (%RU64))\n",
1918	pDev->uDevFn >> VBOX_PCI_DEVFN_DEV_SHIFT, pDev->uDevFn & VBOX_PCI_DEVFN_FUN_MASK, pDev->pszNameR3,
1919	iRegion, pRegion->addr, uNew, cbRegion, cbRegion));
1920
1921	ich9pciUnmapRegion(pDev, iRegion);
1922	pRegion->addr = uNew;
1923	if (uNew != INVALID_PCI_ADDRESS)
1924	{
1925	int rc = pRegion->map_func(pDev->Int.s.pDevInsR3, pDev, iRegion,
1926	pRegion->addr, pRegion->size,
1927	(PCIADDRESSSPACE)(pRegion->type));
1928	AssertRC(rc);
1929	}
1930	}
1931
1932	if (f64Bit)
1933	iRegion++;
1934	}
1935	/* else: size == 0: unused region */
1936	}
1937	}
1938
1939
1940	/**
1941	* Worker for devpciR3CommonDefaultConfigWrite that write a byte to a BAR.
1942	*
1943	* @param pPciDev The PCI device.
1944	* @param iRegion The region.
1945	* @param off The BAR offset.
1946	* @param bVal The byte to write.
1947	*/
1948	DECLINLINE(void) devpciR3WriteBarByte(PPDMPCIDEV pPciDev, uint32_t iRegion, uint32_t off, uint8_t bVal)
1949	{
1950	PCIIORegion *pRegion = &pPciDev->Int.s.aIORegions[iRegion];
1951	Log3(("devpciR3WriteBarByte: region=%d off=%d val=%#x size=%#llx\n", iRegion, off, bVal, pRegion->size));
1952	Assert(off <= 3);
1953
1954	/* Check if we're writing to upper part of 64-bit BAR. */
1955	if (pRegion->type == 0xff)
1956	{
1957	AssertLogRelReturnVoid(iRegion > 0 && iRegion < VBOX_PCI_ROM_SLOT);
1958	pRegion--;
1959	iRegion--;
1960	off += 4;
1961	Assert(pRegion->type & PCI_ADDRESS_SPACE_BAR64);
1962	}
1963
1964	/* Ignore zero sized regions (they don't exist). */
1965	if (pRegion->size != 0)
1966	{
1967	uint32_t uAddr = ich9pciGetRegionReg(iRegion) + off;
1968	Assert((pRegion->size & (pRegion->size - 1)) == 0); /* Region size must be power of two. */
1969	uint8_t bMask = ( (pRegion->size - 1) >> (off * 8) ) & 0xff;
1970	if (off == 0)
1971	bMask \|= (pRegion->type & PCI_ADDRESS_SPACE_IO)
1972	? (1 << 2) - 1 /* 2 lowest bits for IO region */ :
1973	(1 << 4) - 1 /* 4 lowest bits for memory region, also ROM enable bit for ROM region */;
1974
1975	uint8_t bOld = PDMPciDevGetByte(pPciDev, uAddr) & bMask;
1976	bVal = (bOld & bMask) \| (bVal & ~bMask);
1977
1978	Log3(("devpciR3WriteBarByte: %x changed to %x\n", bOld, bVal));
1979
1980	PCIDevSetByte(pPciDev, uAddr, bVal);
1981	}
1982	}
1983
1984
1985	/**
1986	* Checks if the given configuration byte is writable.
1987	*
1988	* @returns true if writable, false if not
1989	* @param uAddress The config space byte byte.
1990	* @param bHeaderType The device header byte.
1991	*/
1992	DECLINLINE(bool) devpciR3IsConfigByteWritable(uint32_t uAddress, uint8_t bHeaderType)
1993	{
1994	switch (bHeaderType)
1995	{
1996	case 0x00: /* normal device */
1997	case 0x80: /* multi-function device */
1998	switch (uAddress)
1999	{
2000	/* Read-only registers. */
2001	case VBOX_PCI_VENDOR_ID:
2002	case VBOX_PCI_VENDOR_ID+1:
2003	case VBOX_PCI_DEVICE_ID:
2004	case VBOX_PCI_DEVICE_ID+1:
2005	case VBOX_PCI_REVISION_ID:
2006	case VBOX_PCI_CLASS_PROG:
2007	case VBOX_PCI_CLASS_SUB:
2008	case VBOX_PCI_CLASS_BASE:
2009	case VBOX_PCI_HEADER_TYPE:
2010	case VBOX_PCI_SUBSYSTEM_VENDOR_ID:
2011	case VBOX_PCI_SUBSYSTEM_VENDOR_ID+1:
2012	case VBOX_PCI_SUBSYSTEM_ID:
2013	case VBOX_PCI_SUBSYSTEM_ID+1:
2014	case VBOX_PCI_ROM_ADDRESS:
2015	case VBOX_PCI_ROM_ADDRESS+1:
2016	case VBOX_PCI_ROM_ADDRESS+2:
2017	case VBOX_PCI_ROM_ADDRESS+3:
2018	case VBOX_PCI_CAPABILITY_LIST:
2019	case VBOX_PCI_INTERRUPT_PIN:
2020	return false;
2021	/* Other registers can be written. */
2022	default:
2023	return true;
2024	}
2025	break;
2026	case 0x01: /* PCI-PCI bridge */
2027	switch (uAddress)
2028	{
2029	/* Read-only registers. */
2030	case VBOX_PCI_VENDOR_ID:
2031	case VBOX_PCI_VENDOR_ID+1:
2032	case VBOX_PCI_DEVICE_ID:
2033	case VBOX_PCI_DEVICE_ID+1:
2034	case VBOX_PCI_REVISION_ID:
2035	case VBOX_PCI_CLASS_PROG:
2036	case VBOX_PCI_CLASS_SUB:
2037	case VBOX_PCI_CLASS_BASE:
2038	case VBOX_PCI_HEADER_TYPE:
2039	case VBOX_PCI_ROM_ADDRESS_BR:
2040	case VBOX_PCI_ROM_ADDRESS_BR+1:
2041	case VBOX_PCI_ROM_ADDRESS_BR+2:
2042	case VBOX_PCI_ROM_ADDRESS_BR+3:
2043	case VBOX_PCI_INTERRUPT_PIN:
2044	return false;
2045	/* Other registers can be written. */
2046	default:
2047	return true;
2048	}
2049	break;
2050	default:
2051	AssertMsgFailed(("Unknown header type %#x\n", bHeaderType));
2052	return false;
2053	}
2054	}
2055
2056
2057	/**
2058	* @callback_method_impl{PFNPCICONFIGWRITE,
2059	* Default config space write callback.}
2060	*
2061	* See paragraph 7.5 of PCI Express specification (p. 349) for
2062	* definition of registers and their writability policy.
2063	*/
2064	DECLCALLBACK(void) devpciR3CommonDefaultConfigWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
2065	uint32_t uAddress, uint32_t u32Value, unsigned cb)
2066	{
2067	NOREF(pDevIns);
2068	Assert(cb <= 4);
2069
2070	if (uAddress + cb <= 256)
2071	{
2072	/*
2073	* MSI and MSI-X capabilites needs to be handled separately.
2074	*/
2075	if ( pciDevIsMsiCapable(pPciDev)
2076	&& uAddress - (uint32_t)pPciDev->Int.s.u8MsiCapOffset < (uint32_t)pPciDev->Int.s.u8MsiCapSize)
2077	MsiPciConfigWrite(pPciDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pDevIns),
2078	pPciDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pPciHlp),
2079	pPciDev, uAddress, u32Value, cb);
2080	else if ( pciDevIsMsixCapable(pPciDev)
2081	&& uAddress - (uint32_t)pPciDev->Int.s.u8MsixCapOffset < (uint32_t)pPciDev->Int.s.u8MsixCapSize)
2082	MsixPciConfigWrite(pPciDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pDevIns),
2083	pPciDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pPciHlp),
2084	pPciDev, uAddress, u32Value, cb);
2085	else
2086	{
2087	/*
2088	* Handle the writes byte-by-byte to catch all possible cases.
2089	*
2090	* Note! Real hardware may not necessarily handle non-dword writes like
2091	* we do here and even produce erratic behavior. We don't (yet)
2092	* try emulate that.
2093	*/
2094	uint8_t const bHeaderType = ich9pciGetByte(pPciDev, VBOX_PCI_HEADER_TYPE);
2095	bool const fP2PBridge = bHeaderType == 0x01; /* PCI-PCI bridge */
2096	bool fUpdateMappings = false;
2097	while (cb-- > 0)
2098	{
2099	bool fWritable = devpciR3IsConfigByteWritable(uAddress, bHeaderType);
2100	uint8_t bVal = (uint8_t)u32Value;
2101	bool fRom = false;
2102	switch (uAddress)
2103	{
2104	case VBOX_PCI_COMMAND: /* Command register, bits 0-7. */
2105	if (fWritable)
2106	{
2107	PCIDevSetByte(pPciDev, uAddress, bVal);
2108	fUpdateMappings = true; /** @todo r=bird: Probably not necessary to update mappings on VBOX_PCI_COMMAND changes for bridges? */
2109	}
2110	break;
2111
2112	case VBOX_PCI_COMMAND+1: /* Command register, bits 8-15. */
2113	if (fWritable)
2114	{
2115	/* don't change reserved bits (11-15) */
2116	bVal &= ~UINT8_C(0xf8);
2117	PCIDevSetByte(pPciDev, uAddress, bVal);
2118	fUpdateMappings = true;
2119	}
2120	break;
2121
2122	case VBOX_PCI_STATUS: /* Status register, bits 0-7. */
2123	/* don't change read-only bits => actually all lower bits are read-only */
2124	bVal &= ~UINT8_C(0xff);
2125	/* status register, low part: clear bits by writing a '1' to the corresponding bit */
2126	pPciDev->abConfig[uAddress] &= ~bVal;
2127	break;
2128
2129	case VBOX_PCI_STATUS+1: /* Status register, bits 8-15. */
2130	/* don't change read-only bits */
2131	bVal &= ~UINT8_C(0x06);
2132	/* status register, high part: clear bits by writing a '1' to the corresponding bit */
2133	pPciDev->abConfig[uAddress] &= ~bVal;
2134	break;
2135
2136	case VBOX_PCI_ROM_ADDRESS: case VBOX_PCI_ROM_ADDRESS +1: case VBOX_PCI_ROM_ADDRESS +2: case VBOX_PCI_ROM_ADDRESS +3:
2137	fRom = true;
2138	case VBOX_PCI_BASE_ADDRESS_0: case VBOX_PCI_BASE_ADDRESS_0+1: case VBOX_PCI_BASE_ADDRESS_0+2: case VBOX_PCI_BASE_ADDRESS_0+3:
2139	case VBOX_PCI_BASE_ADDRESS_1: case VBOX_PCI_BASE_ADDRESS_1+1: case VBOX_PCI_BASE_ADDRESS_1+2: case VBOX_PCI_BASE_ADDRESS_1+3:
2140	case VBOX_PCI_BASE_ADDRESS_2: case VBOX_PCI_BASE_ADDRESS_2+1: case VBOX_PCI_BASE_ADDRESS_2+2: case VBOX_PCI_BASE_ADDRESS_2+3:
2141	case VBOX_PCI_BASE_ADDRESS_3: case VBOX_PCI_BASE_ADDRESS_3+1: case VBOX_PCI_BASE_ADDRESS_3+2: case VBOX_PCI_BASE_ADDRESS_3+3:
2142	case VBOX_PCI_BASE_ADDRESS_4: case VBOX_PCI_BASE_ADDRESS_4+1: case VBOX_PCI_BASE_ADDRESS_4+2: case VBOX_PCI_BASE_ADDRESS_4+3:
2143	case VBOX_PCI_BASE_ADDRESS_5: case VBOX_PCI_BASE_ADDRESS_5+1: case VBOX_PCI_BASE_ADDRESS_5+2: case VBOX_PCI_BASE_ADDRESS_5+3:
2144	/* We check that, as same PCI register numbers as BARs may mean different registers for bridges */
2145	if (!fP2PBridge)
2146	{
2147	uint32_t iRegion = fRom ? VBOX_PCI_ROM_SLOT : (uAddress - VBOX_PCI_BASE_ADDRESS_0) >> 2;
2148	devpciR3WriteBarByte(pPciDev, iRegion, uAddress & 0x3, bVal);
2149	fUpdateMappings = true;
2150	break;
2151	}
2152	/* fall thru (bridge) */
2153	default:
2154	if (fWritable)
2155	PCIDevSetByte(pPciDev, uAddress, bVal);
2156	break;
2157	}
2158	uAddress++;
2159	u32Value >>= 8;
2160	}
2161
2162	/*
2163	* Update the region mappings if anything changed related to them (command, BARs, ROM).
2164	*/
2165	if (fUpdateMappings)
2166	devpciR3UpdateMappings(pPciDev);
2167	}
2168	}
2169	else if (uAddress + cb <= 4096)
2170	LogRel(("PCI: %8s/%u: Write to extended register %d fallen back to generic code\n",
2171	pPciDev->pszNameR3, pPciDev->Int.s.CTX_SUFF(pDevIns)->iInstance, uAddress));
2172	else
2173	AssertMsgFailed(("Write after end of PCI config space\n"));
2174	}
2175
2176
2177	/* -=-=-=-=-=- Debug Info Handlers -=-=-=-=-=- */
2178
2179	/**
2180	* Indents an info line.
2181	* @param pHlp The info helper.
2182	* @param iIndentLvl The desired indentation level.
2183	*/
2184	static void devpciR3InfoIndent(PCDBGFINFOHLP pHlp, unsigned iIndentLvl)
2185	{
2186	for (unsigned i = 0; i < iIndentLvl; i++)
2187	pHlp->pfnPrintf(pHlp, " ");
2188	}
2189
2190
2191	/**
2192	* Recursive worker for devpciR3InfoPci.
2193	*
2194	* @param pBus The bus to show info for.
2195	* @param pHlp The info helpers.
2196	* @param iIndentLvl The indentation level.
2197	* @param fRegisters Whether to show device registers or not.
2198	*/
2199	static void devpciR3InfoPciBus(PDEVPCIBUS pBus, PCDBGFINFOHLP pHlp, unsigned iIndentLvl, bool fRegisters)
2200	{
2201	/** @todo r=bird: Not sure if we should actually do PCI config space
2202	* callbacks from this code!! */
2203
2204	for (uint32_t iDev = 0; iDev < RT_ELEMENTS(pBus->apDevices); iDev++)
2205	{
2206	PPDMPCIDEV pPciDev = pBus->apDevices[iDev];
2207	if (pPciDev != NULL)
2208	{
2209	devpciR3InfoIndent(pHlp, iIndentLvl);
2210
2211	/*
2212	* For passthrough devices MSI/MSI-X mostly reflects the way interrupts delivered to the guest,
2213	* as host driver handles real devices interrupts.
2214	*/
2215	pHlp->pfnPrintf(pHlp, "%02x:%02x:%02x %s%s: %04x-%04x %s%s%s",
2216	pBus->iBus, (iDev >> 3) & 0xff, iDev & 0x7,
2217	pPciDev->pszNameR3,
2218	pciDevIsPassthrough(pPciDev) ? " (PASSTHROUGH)" : "",
2219	ich9pciGetWord(pPciDev, VBOX_PCI_VENDOR_ID), ich9pciGetWord(pPciDev, VBOX_PCI_DEVICE_ID),
2220	pBus->fTypeIch9 ? "ICH9" : pBus->fTypePiix3 ? "PIIX3" : "?type?",
2221	pciDevIsMsiCapable(pPciDev) ? " MSI" : "",
2222	pciDevIsMsixCapable(pPciDev) ? " MSI-X" : ""
2223	);
2224	if (ich9pciGetByte(pPciDev, VBOX_PCI_INTERRUPT_PIN) != 0)
2225	{
2226	pHlp->pfnPrintf(pHlp, " IRQ%d", ich9pciGetByte(pPciDev, VBOX_PCI_INTERRUPT_LINE));
2227	pHlp->pfnPrintf(pHlp, " (INTA#->IRQ%d)", 0x10 + ich9pciSlot2ApicIrq(iDev >> 3, 0));
2228	}
2229	pHlp->pfnPrintf(pHlp, "\n");
2230
2231	if (pciDevIsMsiCapable(pPciDev) \|\| pciDevIsMsixCapable(pPciDev))
2232	{
2233	devpciR3InfoIndent(pHlp, iIndentLvl + 2);
2234
2235	if (pciDevIsMsiCapable(pPciDev))
2236	pHlp->pfnPrintf(pHlp, "MSI:%s ", MsiIsEnabled(pPciDev) ? "on" : "off");
2237
2238	if (pciDevIsMsixCapable(pPciDev))
2239	pHlp->pfnPrintf(pHlp, "MSI-X:%s ", MsixIsEnabled(pPciDev) ? "on" : "off");
2240
2241	pHlp->pfnPrintf(pHlp, "\n");
2242	}
2243
2244	uint16_t iCmd = ich9pciGetWord(pPciDev, VBOX_PCI_COMMAND);
2245	if ((iCmd & (VBOX_PCI_COMMAND_IO \| VBOX_PCI_COMMAND_MEMORY)) != 0)
2246	{
2247	for (unsigned iRegion = 0; iRegion < VBOX_PCI_NUM_REGIONS; iRegion++)
2248	{
2249	PCIIORegion const *pRegion = &pPciDev->Int.s.aIORegions[iRegion];
2250	uint64_t const cbRegion = pRegion->size;
2251
2252	if (cbRegion == 0)
2253	continue;
2254
2255	uint32_t uAddr = ich9pciGetDWord(pPciDev, ich9pciGetRegionReg(iRegion));
2256	const char * pszDesc;
2257	char szDescBuf[128];
2258
2259	bool f64Bit = (pRegion->type & ((uint8_t)(PCI_ADDRESS_SPACE_BAR64 \| PCI_ADDRESS_SPACE_IO)))
2260	== PCI_ADDRESS_SPACE_BAR64;
2261	if (pRegion->type & PCI_ADDRESS_SPACE_IO)
2262	{
2263	pszDesc = "IO";
2264	uAddr &= ~0x3;
2265	}
2266	else
2267	{
2268	RTStrPrintf(szDescBuf, sizeof(szDescBuf), "MMIO%s%s",
2269	f64Bit ? "64" : "32",
2270	pRegion->type & PCI_ADDRESS_SPACE_MEM_PREFETCH ? " PREFETCH" : "");
2271	pszDesc = szDescBuf;
2272	uAddr &= ~0xf;
2273	}
2274
2275	devpciR3InfoIndent(pHlp, iIndentLvl + 2);
2276	pHlp->pfnPrintf(pHlp, "%s region #%u: ", pszDesc, iRegion);
2277	if (f64Bit)
2278	{
2279	uint32_t u32High = ich9pciGetDWord(pPciDev, ich9pciGetRegionReg(iRegion+1));
2280	uint64_t u64Addr = RT_MAKE_U64(uAddr, u32High);
2281	pHlp->pfnPrintf(pHlp, "%RX64..%RX64\n", u64Addr, u64Addr + cbRegion);
2282	iRegion++;
2283	}
2284	else
2285	pHlp->pfnPrintf(pHlp, "%x..%x\n", uAddr, uAddr + (uint32_t)cbRegion);
2286	}
2287	}
2288
2289	devpciR3InfoIndent(pHlp, iIndentLvl + 2);
2290	uint16_t iStatus = ich9pciGetWord(pPciDev, VBOX_PCI_STATUS);
2291	pHlp->pfnPrintf(pHlp, "Command: %04X, Status: %04x\n", iCmd, iStatus);
2292	devpciR3InfoIndent(pHlp, iIndentLvl + 2);
2293	pHlp->pfnPrintf(pHlp, "Bus master: %s\n", iCmd & VBOX_PCI_COMMAND_MASTER ? "Yes" : "No");
2294
2295	if (fRegisters)
2296	{
2297	devpciR3InfoIndent(pHlp, iIndentLvl + 2);
2298	pHlp->pfnPrintf(pHlp, "PCI registers:\n");
2299	for (unsigned iReg = 0; iReg < 0x100; )
2300	{
2301	unsigned iPerLine = 0x10;
2302	Assert(0x100 % iPerLine == 0);
2303	devpciR3InfoIndent(pHlp, iIndentLvl + 3);
2304
2305	while (iPerLine-- > 0)
2306	pHlp->pfnPrintf(pHlp, "%02x ", ich9pciGetByte(pPciDev, iReg++));
2307	pHlp->pfnPrintf(pHlp, "\n");
2308	}
2309	}
2310	}
2311	}
2312
2313	if (pBus->cBridges > 0)
2314	{
2315	devpciR3InfoIndent(pHlp, iIndentLvl);
2316	pHlp->pfnPrintf(pHlp, "Registered %d bridges, subordinate buses info follows\n", pBus->cBridges);
2317	for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
2318	{
2319	PDEVPCIBUS pBusSub = PDMINS_2_DATA(pBus->papBridgesR3[iBridge]->Int.s.CTX_SUFF(pDevIns), PDEVPCIBUS);
2320	devpciR3InfoPciBus(pBusSub, pHlp, iIndentLvl + 1, fRegisters);
2321	}
2322	}
2323	}
2324
2325
2326	/**
2327	* @callback_method_impl{FNDBGFHANDLERDEV, 'pci'}
2328	*/
2329	DECLCALLBACK(void) devpciR3InfoPci(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
2330	{
2331	PDEVPCIBUS pBus = DEVINS_2_DEVPCIBUS(pDevIns);
2332
2333	if (pszArgs == NULL \|\| !*pszArgs \|\| !strcmp(pszArgs, "basic"))
2334	devpciR3InfoPciBus(pBus, pHlp, 0 /iIndentLvl/, false /fRegisters/);
2335	else if (!strcmp(pszArgs, "verbose"))
2336	devpciR3InfoPciBus(pBus, pHlp, 0 /iIndentLvl/, true /fRegisters/);
2337	else
2338	pHlp->pfnPrintf(pHlp, "Invalid argument. Recognized arguments are 'basic', 'verbose'.\n");
2339	}
2340
2341
2342	/**
2343	* @callback_method_impl{FNDBGFHANDLERDEV, 'pciirq'}
2344	*/
2345	DECLCALLBACK(void) devpciR3InfoPciIrq(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
2346	{
2347	PDEVPCIROOT pGlobals = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
2348	NOREF(pszArgs);
2349
2350	pHlp->pfnPrintf(pHlp, "PCI I/O APIC IRQ levels:\n");
2351	for (int i = 0; i < DEVPCI_APIC_IRQ_PINS; ++i)
2352	pHlp->pfnPrintf(pHlp, " IRQ%02d: %u\n", 0x10 + i, pGlobals->auPciApicIrqLevels[i]);
2353	}
2354
2355
2356
2357	static DECLCALLBACK(int) ich9pciConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
2358	{
2359	RT_NOREF1(iInstance);
2360	Assert(iInstance == 0);
2361	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
2362
2363	/*
2364	* Validate and read configuration.
2365	*/
2366	if (!CFGMR3AreValuesValid(pCfg,
2367	"IOAPIC\0"
2368	"GCEnabled\0"
2369	"R0Enabled\0"
2370	"McfgBase\0"
2371	"McfgLength\0"
2372	))
2373	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
2374
2375	/* query whether we got an IOAPIC */
2376	bool fUseIoApic;
2377	int rc = CFGMR3QueryBoolDef(pCfg, "IOAPIC", &fUseIoApic, false);
2378	if (RT_FAILURE(rc))
2379	return PDMDEV_SET_ERROR(pDevIns, rc,
2380	N_("Configuration error: Failed to query boolean value \"IOAPIC\""));
2381
2382	/* check if RC code is enabled. */
2383	bool fGCEnabled;
2384	rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
2385	if (RT_FAILURE(rc))
2386	return PDMDEV_SET_ERROR(pDevIns, rc,
2387	N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
2388	/* check if R0 code is enabled. */
2389	bool fR0Enabled;
2390	rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
2391	if (RT_FAILURE(rc))
2392	return PDMDEV_SET_ERROR(pDevIns, rc,
2393	N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
2394
2395	Log(("PCI: fUseIoApic=%RTbool fGCEnabled=%RTbool fR0Enabled=%RTbool\n", fUseIoApic, fGCEnabled, fR0Enabled));
2396
2397	/*
2398	* Init data.
2399	*/
2400	PDEVPCIROOT pGlobals = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
2401	PDEVPCIBUS pBus = &pGlobals->PciBus;
2402	/* Zero out everything */
2403	memset(pGlobals, 0, sizeof(*pGlobals));
2404	/* And fill values */
2405	if (!fUseIoApic)
2406	return PDMDEV_SET_ERROR(pDevIns, rc,
2407	N_("Must use IO-APIC with ICH9 chipset"));
2408	rc = CFGMR3QueryU64Def(pCfg, "McfgBase", &pGlobals->u64PciConfigMMioAddress, 0);
2409	if (RT_FAILURE(rc))
2410	return PDMDEV_SET_ERROR(pDevIns, rc,
2411	N_("Configuration error: Failed to read \"McfgBase\""));
2412	rc = CFGMR3QueryU64Def(pCfg, "McfgLength", &pGlobals->u64PciConfigMMioLength, 0);
2413	if (RT_FAILURE(rc))
2414	return PDMDEV_SET_ERROR(pDevIns, rc,
2415	N_("Configuration error: Failed to read \"McfgLength\""));
2416
2417	pGlobals->fUseIoApic = fUseIoApic;
2418	pGlobals->pDevInsR3 = pDevIns;
2419	pGlobals->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2420	pGlobals->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2421
2422	pGlobals->PciBus.fTypePiix3 = false;
2423	pGlobals->PciBus.fTypeIch9 = true;
2424	pGlobals->PciBus.fPureBridge = false;
2425	pGlobals->PciBus.pDevInsR3 = pDevIns;
2426	pGlobals->PciBus.pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2427	pGlobals->PciBus.pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2428	pGlobals->PciBus.papBridgesR3 = (PPDMPCIDEV )PDMDevHlpMMHeapAllocZ(pDevIns, sizeof(PPDMPCIDEV) RT_ELEMENTS(pGlobals->PciBus.apDevices));
2429	AssertLogRelReturn(pGlobals->PciBus.papBridgesR3, VERR_NO_MEMORY);
2430
2431	/*
2432	* Register bus
2433	*/
2434	PDMPCIBUSREG PciBusReg;
2435	PciBusReg.u32Version = PDM_PCIBUSREG_VERSION;
2436	PciBusReg.pfnRegisterR3 = pciR3MergedRegister;
2437	PciBusReg.pfnRegisterMsiR3 = ich9pciRegisterMsi;
2438	PciBusReg.pfnIORegionRegisterR3 = devpciR3CommonIORegionRegister;
2439	PciBusReg.pfnSetConfigCallbacksR3 = devpciR3CommonSetConfigCallbacks;
2440	PciBusReg.pfnSetIrqR3 = ich9pciSetIrq;
2441	PciBusReg.pfnFakePCIBIOSR3 = ich9pciFakePCIBIOS;
2442	PciBusReg.pszSetIrqRC = fGCEnabled ? "ich9pciSetIrq" : NULL;
2443	PciBusReg.pszSetIrqR0 = fR0Enabled ? "ich9pciSetIrq" : NULL;
2444	rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBus->pPciHlpR3);
2445	if (RT_FAILURE(rc))
2446	return PDMDEV_SET_ERROR(pDevIns, rc,
2447	N_("Failed to register ourselves as a PCI Bus"));
2448	if (pBus->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
2449	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
2450	N_("PCI helper version mismatch; got %#x expected %#x"),
2451	pBus->pPciHlpR3->u32Version, PDM_PCIHLPR3_VERSION);
2452
2453	pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
2454	pBus->pPciHlpR0 = pBus->pPciHlpR3->pfnGetR0Helpers(pDevIns);
2455
2456	/*
2457	* Fill in PCI configs and add them to the bus.
2458	*/
2459	/** @todo Disabled for now because this causes error messages with Linux guests.
2460	* The guest loads the x38_edac device which tries to map a memory region
2461	* using an address given at place 0x48 - 0x4f in the PCi config space.
2462	* This fails. because we don't register such a region.
2463	*/
2464	#if 0
2465	/* Host bridge device */
2466	PCIDevSetVendorId( &pBus->PciDev, 0x8086); /* Intel */
2467	PCIDevSetDeviceId( &pBus->PciDev, 0x29e0); /* Desktop */
2468	PCIDevSetRevisionId(&pBus->PciDev, 0x01); /* rev. 01 */
2469	PCIDevSetClassBase( &pBus->PciDev, 0x06); /* bridge */
2470	PCIDevSetClassSub( &pBus->PciDev, 0x00); /* Host/PCI bridge */
2471	PCIDevSetClassProg( &pBus->PciDev, 0x00); /* Host/PCI bridge */
2472	PCIDevSetHeaderType(&pBus->PciDev, 0x00); /* bridge */
2473	PCIDevSetWord(&pBus->PciDev, VBOX_PCI_SEC_STATUS, 0x0280); /* secondary status */
2474
2475	pBus->PciDev.pDevIns = pDevIns;
2476	/* We register Host<->PCI controller on the bus */
2477	ich9pciRegisterInternal(pBus, 0, &pBus->PciDev, "dram");
2478	#endif
2479
2480	/*
2481	* Register I/O ports and save state.
2482	*/
2483	rc = PDMDevHlpIOPortRegister(pDevIns, 0x0cf8, 1, NULL, ich9pciIOPortAddressWrite, ich9pciIOPortAddressRead, NULL, NULL, "ICH9 (PCI)");
2484	if (RT_FAILURE(rc))
2485	return rc;
2486	rc = PDMDevHlpIOPortRegister(pDevIns, 0x0cfc, 4, NULL, ich9pciIOPortDataWrite, ich9pciIOPortDataRead, NULL, NULL, "ICH9 (PCI)");
2487	if (RT_FAILURE(rc))
2488	return rc;
2489	if (fGCEnabled)
2490	{
2491	rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x0cf8, 1, NIL_RTGCPTR, "ich9pciIOPortAddressWrite", "ich9pciIOPortAddressRead", NULL, NULL, "ICH9 (PCI)");
2492	if (RT_FAILURE(rc))
2493	return rc;
2494	rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x0cfc, 4, NIL_RTGCPTR, "ich9pciIOPortDataWrite", "ich9pciIOPortDataRead", NULL, NULL, "ICH9 (PCI)");
2495	if (RT_FAILURE(rc))
2496	return rc;
2497	}
2498	if (fR0Enabled)
2499	{
2500	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x0cf8, 1, NIL_RTR0PTR, "ich9pciIOPortAddressWrite", "ich9pciIOPortAddressRead", NULL, NULL, "ICH9 (PCI)");
2501	if (RT_FAILURE(rc))
2502	return rc;
2503	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x0cfc, 4, NIL_RTR0PTR, "ich9pciIOPortDataWrite", "ich9pciIOPortDataRead", NULL, NULL, "ICH9 (PCI)");
2504	if (RT_FAILURE(rc))
2505	return rc;
2506	}
2507
2508	if (pGlobals->u64PciConfigMMioAddress != 0)
2509	{
2510	rc = PDMDevHlpMMIORegister(pDevIns, pGlobals->u64PciConfigMMioAddress, pGlobals->u64PciConfigMMioLength, NULL /pvUser/,
2511	IOMMMIO_FLAGS_READ_PASSTHRU \| IOMMMIO_FLAGS_WRITE_PASSTHRU,
2512	ich9pciMcfgMMIOWrite, ich9pciMcfgMMIORead, "MCFG ranges");
2513	AssertMsgRCReturn(rc, ("rc=%Rrc %#llx/%#llx\n", rc, pGlobals->u64PciConfigMMioAddress, pGlobals->u64PciConfigMMioLength), rc);
2514
2515	if (fGCEnabled)
2516	{
2517	rc = PDMDevHlpMMIORegisterRC(pDevIns, pGlobals->u64PciConfigMMioAddress, pGlobals->u64PciConfigMMioLength,
2518	NIL_RTRCPTR /pvUser/, "ich9pciMcfgMMIOWrite", "ich9pciMcfgMMIORead");
2519	AssertRCReturn(rc, rc);
2520	}
2521
2522
2523	if (fR0Enabled)
2524	{
2525	rc = PDMDevHlpMMIORegisterR0(pDevIns, pGlobals->u64PciConfigMMioAddress, pGlobals->u64PciConfigMMioLength,
2526	NIL_RTR0PTR /pvUser/, "ich9pciMcfgMMIOWrite", "ich9pciMcfgMMIORead");
2527	AssertRCReturn(rc, rc);
2528	}
2529	}
2530
2531	rc = PDMDevHlpSSMRegisterEx(pDevIns, VBOX_ICH9PCI_SAVED_STATE_VERSION_CURRENT,
2532	sizeof(pBus) + 16128, "pgm",
2533	NULL, NULL, NULL,
2534	NULL, ich9pciR3SaveExec, NULL,
2535	NULL, ich9pciR3LoadExec, NULL);
2536	if (RT_FAILURE(rc))
2537	return rc;
2538
2539
2540	/** @todo other chipset devices shall be registered too */
2541
2542	PDMDevHlpDBGFInfoRegister(pDevIns, "pci",
2543	"Display PCI bus status. Recognizes 'basic' or 'verbose' as arguments, defaults to 'basic'.",
2544	devpciR3InfoPci);
2545	PDMDevHlpDBGFInfoRegister(pDevIns, "pciirq", "Display PCI IRQ state. (no arguments)", devpciR3InfoPciIrq);
2546
2547	return VINF_SUCCESS;
2548	}
2549
2550	static void ich9pciResetDevice(PPDMPCIDEV pDev)
2551	{
2552	/* Clear regions */
2553	for (int iRegion = 0; iRegion < VBOX_PCI_NUM_REGIONS; iRegion++)
2554	{
2555	PCIIORegion* pRegion = &pDev->Int.s.aIORegions[iRegion];
2556	if (pRegion->size == 0)
2557	continue;
2558
2559	ich9pciUnmapRegion(pDev, iRegion);
2560	}
2561
2562	if (pciDevIsPassthrough(pDev))
2563	{
2564	// no reset handler - we can do what we need in PDM reset handler
2565	/// @todo is it correct?
2566	}
2567	else
2568	{
2569	PCIDevSetCommand(pDev,
2570	PCIDevGetCommand(pDev)
2571	&
2572	~(VBOX_PCI_COMMAND_IO \| VBOX_PCI_COMMAND_MEMORY \|
2573	VBOX_PCI_COMMAND_MASTER \| VBOX_PCI_COMMAND_SPECIAL \|
2574	VBOX_PCI_COMMAND_PARITY \| VBOX_PCI_COMMAND_SERR \|
2575	VBOX_PCI_COMMAND_FAST_BACK \| VBOX_PCI_COMMAND_INTX_DISABLE));
2576
2577	/* Bridge device reset handlers processed later */
2578	if (!pciDevIsPci2PciBridge(pDev))
2579	{
2580	PCIDevSetByte(pDev, VBOX_PCI_CACHE_LINE_SIZE, 0x0);
2581	PCIDevSetInterruptLine(pDev, 0x0);
2582	}
2583
2584	/* Reset MSI message control. */
2585	if (pciDevIsMsiCapable(pDev))
2586	{
2587	/* Extracted from MsiPciConfigWrite(). */
2588	pDev->abConfig[pDev->Int.s.u8MsiCapOffset + VBOX_MSI_CAP_MESSAGE_CONTROL] &= 0x8e;
2589	}
2590
2591	/* Reset MSI-X message control. */
2592	if (pciDevIsMsixCapable(pDev))
2593	{
2594	/* Extracted from MsixPciConfigWrite(); no side effects. */
2595	pDev->abConfig[pDev->Int.s.u8MsixCapOffset + VBOX_MSIX_CAP_MESSAGE_CONTROL + 1] &= 0x3f;
2596	}
2597	}
2598	}
2599
2600
2601	/**
2602	* @copydoc FNPDMDEVRESET
2603	*/
2604	static DECLCALLBACK(void) ich9pciReset(PPDMDEVINS pDevIns)
2605	{
2606	PDEVPCIROOT pGlobals = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
2607	PDEVPCIBUS pBus = &pGlobals->PciBus;
2608
2609	/* PCI-specific reset for each device. */
2610	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
2611	{
2612	if (pBus->apDevices[i])
2613	ich9pciResetDevice(pBus->apDevices[i]);
2614	}
2615
2616	for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
2617	{
2618	if (pBus->papBridgesR3[iBridge])
2619	ich9pcibridgeReset(pBus->papBridgesR3[iBridge]->Int.s.CTX_SUFF(pDevIns));
2620	}
2621
2622	ich9pciFakePCIBIOS(pDevIns);
2623	}
2624
2625
2626	/**
2627	* @interface_method_impl{PDMDEVREG,pfnRelocate}
2628	*/
2629	DECLCALLBACK(void) devpciR3BusRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
2630	{
2631	PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
2632
2633	pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2634	pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
2635
2636	/* Relocate RC pointers for the attached pci devices. */
2637	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
2638	{
2639	PPDMPCIDEV pDev = pBus->apDevices[i];
2640	if (pDev)
2641	{
2642	pDev->Int.s.pBusRC += offDelta;
2643	if (pDev->Int.s.pMsixPageRC)
2644	pDev->Int.s.pMsixPageRC += offDelta;
2645	}
2646	}
2647	}
2648
2649
2650	/**
2651	* @interface_method_impl{PDMDEVREG,pfnRelocate}
2652	*/
2653	DECLCALLBACK(void) devpciR3RootRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
2654	{
2655	PDEVPCIROOT pGlobals = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
2656	pGlobals->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2657
2658	AssertCompileMemberOffset(DEVPCIROOT, PciBus, 0);
2659	devpciR3BusRelocate(pDevIns, offDelta);
2660	}
2661
2662
2663	/**
2664	* @interface_method_impl{PDMDEVREG,pfnConstruct}
2665	*/
2666	static DECLCALLBACK(int) ich9pcibridgeConstruct(PPDMDEVINS pDevIns,
2667	int iInstance,
2668	PCFGMNODE pCfg)
2669	{
2670	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
2671
2672	/*
2673	* Validate and read configuration.
2674	*/
2675	if (!CFGMR3AreValuesValid(pCfg, "GCEnabled\0" "R0Enabled\0"))
2676	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
2677
2678	/* check if RC code is enabled. */
2679	bool fGCEnabled;
2680	int rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
2681	if (RT_FAILURE(rc))
2682	return PDMDEV_SET_ERROR(pDevIns, rc,
2683	N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
2684
2685	/* check if R0 code is enabled. */
2686	bool fR0Enabled;
2687	rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
2688	if (RT_FAILURE(rc))
2689	return PDMDEV_SET_ERROR(pDevIns, rc,
2690	N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
2691	Log(("PCI: fGCEnabled=%RTbool fR0Enabled=%RTbool\n", fGCEnabled, fR0Enabled));
2692
2693	/*
2694	* Init data and register the PCI bus.
2695	*/
2696	PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
2697	pBus->fTypePiix3 = false;
2698	pBus->fTypeIch9 = true;
2699	pBus->fPureBridge = true;
2700	pBus->pDevInsR3 = pDevIns;
2701	pBus->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2702	pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2703	pBus->papBridgesR3 = (PPDMPCIDEV )PDMDevHlpMMHeapAllocZ(pDevIns, sizeof(PPDMPCIDEV) RT_ELEMENTS(pBus->apDevices));
2704	AssertLogRelReturn(pBus->papBridgesR3, VERR_NO_MEMORY);
2705
2706	PDMPCIBUSREG PciBusReg;
2707	PciBusReg.u32Version = PDM_PCIBUSREG_VERSION;
2708	PciBusReg.pfnRegisterR3 = pcibridgeR3MergedRegisterDevice;
2709	PciBusReg.pfnRegisterMsiR3 = ich9pciRegisterMsi;
2710	PciBusReg.pfnIORegionRegisterR3 = devpciR3CommonIORegionRegister;
2711	PciBusReg.pfnSetConfigCallbacksR3 = devpciR3CommonSetConfigCallbacks;
2712	PciBusReg.pfnSetIrqR3 = ich9pcibridgeSetIrq;
2713	PciBusReg.pfnFakePCIBIOSR3 = NULL; /* Only needed for the first bus. */
2714	PciBusReg.pszSetIrqRC = fGCEnabled ? "ich9pcibridgeSetIrq" : NULL;
2715	PciBusReg.pszSetIrqR0 = fR0Enabled ? "ich9pcibridgeSetIrq" : NULL;
2716	rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBus->pPciHlpR3);
2717	if (RT_FAILURE(rc))
2718	return PDMDEV_SET_ERROR(pDevIns, rc,
2719	N_("Failed to register ourselves as a PCI Bus"));
2720	if (pBus->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
2721	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
2722	N_("PCI helper version mismatch; got %#x expected %#x"),
2723	pBus->pPciHlpR3->u32Version, PDM_PCIHLPR3_VERSION);
2724
2725	pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
2726	pBus->pPciHlpR0 = pBus->pPciHlpR3->pfnGetR0Helpers(pDevIns);
2727
2728	/* Disable default device locking. */
2729	rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
2730	AssertRCReturn(rc, rc);
2731
2732	/*
2733	* Fill in PCI configs and add them to the bus.
2734	*/
2735	PCIDevSetVendorId( &pBus->PciDev, 0x8086); /* Intel */
2736	PCIDevSetDeviceId( &pBus->PciDev, 0x2448); /* 82801 Mobile PCI bridge. */
2737	PCIDevSetRevisionId(&pBus->PciDev, 0xf2);
2738	PCIDevSetClassSub( &pBus->PciDev, 0x04); /* pci2pci */
2739	PCIDevSetClassBase( &pBus->PciDev, 0x06); /* PCI_bridge */
2740	PCIDevSetClassProg( &pBus->PciDev, 0x01); /* Supports subtractive decoding. */
2741	PCIDevSetHeaderType(&pBus->PciDev, 0x01); /* Single function device which adheres to the PCI-to-PCI bridge spec. */
2742	PCIDevSetCommand( &pBus->PciDev, 0x00);
2743	PCIDevSetStatus( &pBus->PciDev, 0x20); /* 66MHz Capable. */
2744	PCIDevSetInterruptLine(&pBus->PciDev, 0x00); /* This device does not assert interrupts. */
2745
2746	/*
2747	* This device does not generate interrupts. Interrupt delivery from
2748	* devices attached to the bus is unaffected.
2749	*/
2750	PCIDevSetInterruptPin (&pBus->PciDev, 0x00);
2751
2752	/*
2753	* Register this PCI bridge. The called function will take care on which bus we will get registered.
2754	*/
2755	rc = PDMDevHlpPCIRegisterEx(pDevIns, &pBus->PciDev, PDMPCIDEVREG_CFG_PRIMARY, PDMPCIDEVREG_F_PCI_BRIDGE,
2756	PDMPCIDEVREG_DEV_NO_FIRST_UNUSED, PDMPCIDEVREG_FUN_NO_FIRST_UNUSED, "ich9pcibridge");
2757	if (RT_FAILURE(rc))
2758	return rc;
2759	pBus->PciDev.Int.s.pfnBridgeConfigRead = ich9pcibridgeConfigRead;
2760	pBus->PciDev.Int.s.pfnBridgeConfigWrite = ich9pcibridgeConfigWrite;
2761
2762	/*
2763	* The iBus property doesn't really represent the bus number
2764	* because the guest and the BIOS can choose different bus numbers
2765	* for them.
2766	* The bus number is mainly for the setIrq function to indicate
2767	* when the host bus is reached which will have iBus = 0.
2768	* That's why the + 1.
2769	*/
2770	pBus->iBus = iInstance + 1;
2771
2772	/*
2773	* Register SSM handlers. We use the same saved state version as for the host bridge
2774	* to make changes easier.
2775	*/
2776	rc = PDMDevHlpSSMRegisterEx(pDevIns, VBOX_ICH9PCI_SAVED_STATE_VERSION_CURRENT,
2777	sizeof(pBus) + 16128,
2778	"pgm" /* before */,
2779	NULL, NULL, NULL,
2780	NULL, ich9pcibridgeR3SaveExec, NULL,
2781	NULL, ich9pcibridgeR3LoadExec, NULL);
2782	if (RT_FAILURE(rc))
2783	return rc;
2784
2785
2786	return VINF_SUCCESS;
2787	}
2788
2789	/**
2790	* @copydoc FNPDMDEVRESET
2791	*/
2792	static void ich9pcibridgeReset(PPDMDEVINS pDevIns)
2793	{
2794	PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
2795
2796	/* Reset config space to default values. */
2797	PCIDevSetByte(&pBus->PciDev, VBOX_PCI_PRIMARY_BUS, 0);
2798	PCIDevSetByte(&pBus->PciDev, VBOX_PCI_SECONDARY_BUS, 0);
2799	PCIDevSetByte(&pBus->PciDev, VBOX_PCI_SUBORDINATE_BUS, 0);
2800
2801	/* PCI-specific reset for each device. */
2802	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
2803	{
2804	if (pBus->apDevices[i])
2805	ich9pciResetDevice(pBus->apDevices[i]);
2806	}
2807	}
2808
2809
2810
2811	/**
2812	* The PCI bus device registration structure.
2813	*/
2814	const PDMDEVREG g_DevicePciIch9 =
2815	{
2816	/* u32Version */
2817	PDM_DEVREG_VERSION,
2818	/* szName */
2819	"ich9pci",
2820	/* szRCMod */
2821	"VBoxDDRC.rc",
2822	/* szR0Mod */
2823	"VBoxDDR0.r0",
2824	/* pszDescription */
2825	"ICH9 PCI bridge",
2826	/* fFlags */
2827	PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
2828	/* fClass */
2829	PDM_DEVREG_CLASS_BUS_PCI \| PDM_DEVREG_CLASS_BUS_ISA,
2830	/* cMaxInstances */
2831	1,
2832	/* cbInstance */
2833	sizeof(DEVPCIROOT),
2834	/* pfnConstruct */
2835	ich9pciConstruct,
2836	/* pfnDestruct */
2837	NULL,
2838	/* pfnRelocate */
2839	devpciR3RootRelocate,
2840	/* pfnMemSetup */
2841	NULL,
2842	/* pfnPowerOn */
2843	NULL,
2844	/* pfnReset */
2845	ich9pciReset,
2846	/* pfnSuspend */
2847	NULL,
2848	/* pfnResume */
2849	NULL,
2850	/* pfnAttach */
2851	NULL,
2852	/* pfnDetach */
2853	NULL,
2854	/* pfnQueryInterface */
2855	NULL,
2856	/* pfnInitComplete */
2857	NULL,
2858	/* pfnPowerOff */
2859	NULL,
2860	/* pfnSoftReset */
2861	NULL,
2862	/* u32VersionEnd */
2863	PDM_DEVREG_VERSION
2864	};
2865
2866	/**
2867	* The device registration structure
2868	* for the PCI-to-PCI bridge.
2869	*/
2870	const PDMDEVREG g_DevicePciIch9Bridge =
2871	{
2872	/* u32Version */
2873	PDM_DEVREG_VERSION,
2874	/* szName */
2875	"ich9pcibridge",
2876	/* szRCMod */
2877	"VBoxDDRC.rc",
2878	/* szR0Mod */
2879	"VBoxDDR0.r0",
2880	/* pszDescription */
2881	"ICH9 PCI to PCI bridge",
2882	/* fFlags */
2883	PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
2884	/* fClass */
2885	PDM_DEVREG_CLASS_BUS_PCI,
2886	/* cMaxInstances */
2887	~0U,
2888	/* cbInstance */
2889	sizeof(DEVPCIBUS),
2890	/* pfnConstruct */
2891	ich9pcibridgeConstruct,
2892	/* pfnDestruct */
2893	NULL,
2894	/* pfnRelocate */
2895	devpciR3BusRelocate,
2896	/* pfnMemSetup */
2897	NULL,
2898	/* pfnPowerOn */
2899	NULL,
2900	/* pfnReset */
2901	NULL, /* Must be NULL, to make sure only bus driver handles reset */
2902	/* pfnSuspend */
2903	NULL,
2904	/* pfnResume */
2905	NULL,
2906	/* pfnAttach */
2907	NULL,
2908	/* pfnDetach */
2909	NULL,
2910	/* pfnQueryInterface */
2911	NULL,
2912	/* pfnInitComplete */
2913	NULL,
2914	/* pfnPowerOff */
2915	NULL,
2916	/* pfnSoftReset */
2917	NULL,
2918	/* u32VersionEnd */
2919	PDM_DEVREG_VERSION
2920	};
2921
2922	#endif /* IN_RING3 */
2923

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source: vbox/trunk/src/VBox/Devices/Bus/DevPciIch9.cpp@ 64467

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