DevPciIch9.cpp@ 65324

Last change on this file since 65324 was 65324, checked in by vboxsync, 8 years ago
DevPciIch9.cpp: only place prefetchable regions beyond 4GB, due to decoding limitations in the bridges
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1	/* $Id: DevPciIch9.cpp 65324 2017-01-16 13:00:38Z vboxsync $ */
2	/** @file
3	* DevPCI - ICH9 southbridge PCI bus emulation device.
4	*
5	* @remarks We'll be slowly promoting the code in this file to common PCI bus
6	* code. Function without 'static' and using 'devpci' as prefix is
7	* also used by DevPCI.cpp and have a prototype in DevPciInternal.h.
8	*
9	* For the time being the DevPciMerge1.cpp.h file will remain separate,
10	* due to 5.1. We can merge it into this one later in the dev cycle.
11	*
12	* DO NOT use the PDMPciDev* or PCIDev* family of functions in this
13	* file except in the two callbacks for config space access (and the
14	* functions which are used exclusively by that code) and the two
15	* device constructors when setting up the config space for the
16	* bridges. Everything else need extremely careful review. Using
17	* them elsewhere (especially in the init code) causes weird failures
18	* with PCI passthrough, as it would only update the array of
19	* (emulated) config space, but not talk to the actual device (needs
20	* invoking the respective callback).
21	*/
22
23	/*
24	* Copyright (C) 2010-2017 Oracle Corporation
25	*
26	* This file is part of VirtualBox Open Source Edition (OSE), as
27	* available from http://www.virtualbox.org. This file is free software;
28	* you can redistribute it and/or modify it under the terms of the GNU
29	* General Public License (GPL) as published by the Free Software
30	* Foundation, in version 2 as it comes in the "COPYING" file of the
31	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
32	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
33	*/
34
35
36	/*********************************************************************************************************************************
37	* Header Files *
38	*********************************************************************************************************************************/
39	#define LOG_GROUP LOG_GROUP_DEV_PCI
40	#define PDMPCIDEV_INCLUDE_PRIVATE /* Hack to get pdmpcidevint.h included at the right point. */
41	#include <VBox/vmm/pdmpcidev.h>
42
43	#include <VBox/msi.h>
44	#include <VBox/vmm/pdmdev.h>
45	#include <VBox/vmm/mm.h>
46	#include <iprt/asm.h>
47	#include <iprt/assert.h>
48	#include <iprt/string.h>
49	#ifdef IN_RING3
50	# include <iprt/mem.h>
51	#endif
52
53	#include "PciInline.h"
54	#include "VBoxDD.h"
55	#include "MsiCommon.h"
56	#include "DevPciInternal.h"
57
58
59	/*********************************************************************************************************************************
60	* Structures and Typedefs *
61	*********************************************************************************************************************************/
62	/**
63	* PCI configuration space address.
64	*/
65	typedef struct
66	{
67	uint8_t iBus;
68	uint8_t iDeviceFunc;
69	uint16_t iRegister;
70	} PciAddress;
71
72
73	/*********************************************************************************************************************************
74	* Defined Constants And Macros *
75	*********************************************************************************************************************************/
76	/** Saved state version of the ICH9 PCI bus device. */
77	#define VBOX_ICH9PCI_SAVED_STATE_VERSION VBOX_ICH9PCI_SAVED_STATE_VERSION_REGION_SIZES
78	/** Adds I/O region types and sizes for dealing changes in resource regions. */
79	#define VBOX_ICH9PCI_SAVED_STATE_VERSION_REGION_SIZES 3
80	/** This appears to be the first state we need to care about. */
81	#define VBOX_ICH9PCI_SAVED_STATE_VERSION_MSI 2
82	/** This is apparently not supported or has a grossly incomplete state, juding
83	* from hints in the code. */
84	#define VBOX_ICH9PCI_SAVED_STATE_VERSION_NOMSI 1
85
86	/** Invalid PCI region mapping address. */
87	#define INVALID_PCI_ADDRESS UINT32_MAX
88
89
90	/*********************************************************************************************************************************
91	* Internal Functions *
92	*********************************************************************************************************************************/
93	/* Prototypes */
94	static void ich9pciSetIrqInternal(PDEVPCIROOT pPciRoot, uint8_t uDevFn, PPDMPCIDEV pPciDev,
95	int iIrq, int iLevel, uint32_t uTagSrc);
96	#ifdef IN_RING3
97	static void ich9pcibridgeReset(PPDMDEVINS pDevIns);
98	DECLINLINE(PPDMPCIDEV) ich9pciFindBridge(PDEVPCIBUS pBus, uint8_t uBus);
99	static void ich9pciBiosInitAllDevicesOnBus(PDEVPCIROOT pPciRoot, uint8_t uBus);
100	#endif
101
102
103	// See 7.2.2. PCI Express Enhanced Configuration Mechanism for details of address
104	// mapping, we take n=6 approach
105	DECLINLINE(void) ich9pciPhysToPciAddr(PDEVPCIROOT pPciRoot, RTGCPHYS GCPhysAddr, PciAddress* pPciAddr)
106	{
107	NOREF(pPciRoot);
108	pPciAddr->iBus = (GCPhysAddr >> 20) & ((1<<6) - 1);
109	pPciAddr->iDeviceFunc = (GCPhysAddr >> 12) & ((1<<(5+3)) - 1); // 5 bits - device, 3 bits - function
110	pPciAddr->iRegister = (GCPhysAddr >> 0) & ((1<<(6+4+2)) - 1); // 6 bits - register, 4 bits - extended register, 2 bits -Byte Enable
111	}
112
113	DECLINLINE(void) ich9pciStateToPciAddr(PDEVPCIROOT pPciRoot, RTGCPHYS addr, PciAddress* pPciAddr)
114	{
115	pPciAddr->iBus = (pPciRoot->uConfigReg >> 16) & 0xff;
116	pPciAddr->iDeviceFunc = (pPciRoot->uConfigReg >> 8) & 0xff;
117	pPciAddr->iRegister = (pPciRoot->uConfigReg & 0xfc) \| (addr & 3);
118	}
119
120	PDMBOTHCBDECL(void) ich9pciSetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc)
121	{
122	LogFlowFunc(("invoked by %p/%d: iIrq=%d iLevel=%d uTagSrc=%#x\n", pDevIns, pDevIns->iInstance, iIrq, iLevel, uTagSrc));
123	ich9pciSetIrqInternal(PDMINS_2_DATA(pDevIns, PDEVPCIROOT), pPciDev->uDevFn, pPciDev, iIrq, iLevel, uTagSrc);
124	}
125
126	PDMBOTHCBDECL(void) ich9pcibridgeSetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc)
127	{
128	/*
129	* The PCI-to-PCI bridge specification defines how the interrupt pins
130	* are routed from the secondary to the primary bus (see chapter 9).
131	* iIrq gives the interrupt pin the pci device asserted.
132	* We change iIrq here according to the spec and call the SetIrq function
133	* of our parent passing the device which asserted the interrupt instead of the device of the bridge.
134	*/
135	PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
136	PPDMPCIDEV pPciDevBus = pPciDev;
137	int iIrqPinBridge = iIrq;
138	uint8_t uDevFnBridge = 0;
139
140	/* Walk the chain until we reach the host bus. */
141	do
142	{
143	uDevFnBridge = pBus->PciDev.uDevFn;
144	iIrqPinBridge = ((pPciDevBus->uDevFn >> 3) + iIrqPinBridge) & 3;
145
146	/* Get the parent. */
147	pBus = pBus->PciDev.Int.s.CTX_SUFF(pBus);
148	pPciDevBus = &pBus->PciDev;
149	} while (pBus->iBus != 0);
150
151	AssertMsgReturnVoid(pBus->iBus == 0, ("This is not the host pci bus iBus=%d\n", pBus->iBus));
152	ich9pciSetIrqInternal(DEVPCIBUS_2_DEVPCIROOT(pBus), uDevFnBridge, pPciDev, iIrqPinBridge, iLevel, uTagSrc);
153	}
154
155
156	/**
157	* Port I/O Handler for PCI address OUT operations.
158	*
159	* Emulates writes to Configuration Address Port at 0CF8h for
160	* Configuration Mechanism #1.
161	*
162	* @returns VBox status code.
163	*
164	* @param pDevIns ICH9 device instance.
165	* @param pvUser User argument - ignored.
166	* @param uPort Port number used for the OUT operation.
167	* @param u32 The value to output.
168	* @param cb The value size in bytes.
169	*/
170	PDMBOTHCBDECL(int) ich9pciIOPortAddressWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT uPort, uint32_t u32, unsigned cb)
171	{
172	LogFlow(("ich9pciIOPortAddressWrite: Port=%#x u32=%#x cb=%d\n", uPort, u32, cb));
173	RT_NOREF2(uPort, pvUser);
174	if (cb == 4)
175	{
176	PDEVPCIROOT pThis = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
177
178	/*
179	* bits [1:0] are hard-wired, read-only and must return zeroes
180	* when read.
181	*/
182	u32 &= ~3;
183
184	PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_WRITE);
185	pThis->uConfigReg = u32;
186	PCI_UNLOCK(pDevIns);
187	}
188
189	return VINF_SUCCESS;
190	}
191
192
193	/**
194	* Port I/O Handler for PCI address IN operations.
195	*
196	* Emulates reads from Configuration Address Port at 0CF8h for
197	* Configuration Mechanism #1.
198	*
199	* @returns VBox status code.
200	*
201	* @param pDevIns ICH9 device instance.
202	* @param pvUser User argument - ignored.
203	* @param uPort Port number used for the IN operation.
204	* @param pu32 Where to store the result.
205	* @param cb Number of bytes read.
206	*/
207	PDMBOTHCBDECL(int) ich9pciIOPortAddressRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT uPort, uint32_t pu32, unsigned cb)
208	{
209	RT_NOREF2(uPort, pvUser);
210	if (cb == 4)
211	{
212	PDEVPCIROOT pThis = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
213
214	PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_READ);
215	*pu32 = pThis->uConfigReg;
216	PCI_UNLOCK(pDevIns);
217
218	LogFlow(("ich9pciIOPortAddressRead: Port=%#x cb=%d -> %#x\n", uPort, cb, *pu32));
219	return VINF_SUCCESS;
220	}
221
222	Log(("ich9pciIOPortAddressRead: Port=%#x cb=%d VERR_IOM_IOPORT_UNUSED\n", uPort, cb));
223	return VERR_IOM_IOPORT_UNUSED;
224	}
225
226
227	/*
228	* Perform configuration space write.
229	*/
230	static int ich9pciDataWriteAddr(PDEVPCIROOT pPciRoot, PciAddress* pAddr,
231	uint32_t val, int cb, int rcReschedule)
232	{
233	int rc = VINF_SUCCESS;
234	#ifdef IN_RING3
235	NOREF(rcReschedule);
236	#else
237	RT_NOREF2(val, cb);
238	#endif
239
240	if (pAddr->iBus != 0) /* forward to subordinate bus */
241	{
242	if (pPciRoot->PciBus.cBridges)
243	{
244	#ifdef IN_RING3 /** @todo do lookup in R0/RC too! r=klaus don't think that it can work, since the config space access callback only works in R3 */
245	PPDMPCIDEV pBridgeDevice = ich9pciFindBridge(&pPciRoot->PciBus, pAddr->iBus);
246	if (pBridgeDevice)
247	{
248	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigWrite);
249	pBridgeDevice->Int.s.pfnBridgeConfigWrite(pBridgeDevice->Int.s.CTX_SUFF(pDevIns), pAddr->iBus, pAddr->iDeviceFunc,
250	pAddr->iRegister, val, cb);
251	}
252	#else
253	rc = rcReschedule;
254	#endif
255	}
256	}
257	else /* forward to directly connected device */
258	{
259	R3PTRTYPE(PDMPCIDEV *) pPciDev = pPciRoot->PciBus.apDevices[pAddr->iDeviceFunc];
260	if (pPciDev)
261	{
262	#ifdef IN_RING3
263	pPciDev->Int.s.pfnConfigWrite(pPciDev->Int.s.CTX_SUFF(pDevIns), pPciDev, pAddr->iRegister, val, cb);
264	#else
265	rc = rcReschedule;
266	#endif
267	}
268	}
269
270	Log2(("ich9pciDataWriteAddr: %02x:%02x.%d reg %x(%d) %x %Rrc\n",
271	pAddr->iBus, pAddr->iDeviceFunc >> 3, pAddr->iDeviceFunc & 0x7, pAddr->iRegister,
272	cb, val, rc));
273	return rc;
274	}
275
276
277	/*
278	* Decode value latched in Configuration Address Port and perform
279	* requsted write to the target configuration space register.
280	*
281	* XXX: This code should be probably moved to its only caller
282	* (ich9pciIOPortDataWrite) to avoid prolifiration of confusingly
283	* similarly named functions.
284	*/
285	static int ich9pciDataWrite(PDEVPCIROOT pPciRoot, uint32_t addr, uint32_t val, int len)
286	{
287	LogFlow(("ich9pciDataWrite: config=%08x val=%08x len=%d\n", pPciRoot->uConfigReg, val, len));
288
289	/* Configuration space mapping enabled? */
290	if (!(pPciRoot->uConfigReg & (1 << 31)))
291	return VINF_SUCCESS;
292
293	/* Decode target device and configuration space register */
294	PciAddress aPciAddr;
295	ich9pciStateToPciAddr(pPciRoot, addr, &aPciAddr);
296
297	/* Perform configuration space write */
298	return ich9pciDataWriteAddr(pPciRoot, &aPciAddr, val, len, VINF_IOM_R3_IOPORT_WRITE);
299	}
300
301
302	/**
303	* Port I/O Handler for PCI data OUT operations.
304	*
305	* Emulates writes to Configuration Data Port at 0CFCh for
306	* Configuration Mechanism #1.
307	*
308	* @returns VBox status code.
309	*
310	* @param pDevIns ICH9 device instance.
311	* @param pvUser User argument - ignored.
312	* @param uPort Port number used for the OUT operation.
313	* @param u32 The value to output.
314	* @param cb The value size in bytes.
315	*/
316	PDMBOTHCBDECL(int) ich9pciIOPortDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT uPort, uint32_t u32, unsigned cb)
317	{
318	LogFlow(("ich9pciIOPortDataWrite: Port=%#x u32=%#x cb=%d\n", uPort, u32, cb));
319	NOREF(pvUser);
320	int rc = VINF_SUCCESS;
321	if (!(uPort % cb))
322	{
323	PDEVPCIROOT pThis = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
324
325	PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_WRITE);
326	rc = ich9pciDataWrite(pThis, uPort, u32, cb);
327	PCI_UNLOCK(pDevIns);
328	}
329	else
330	AssertMsgFailed(("Unaligned write to port %#x u32=%#x cb=%d\n", uPort, u32, cb));
331	return rc;
332	}
333
334
335	static void ich9pciNoMem(void* ptr, int cb)
336	{
337	for (int i = 0; i < cb; i++)
338	((uint8_t*)ptr)[i] = 0xff;
339	}
340
341
342	/*
343	* Perform configuration space read.
344	*/
345	static int ich9pciDataReadAddr(PDEVPCIROOT pPciRoot, PciAddress* pPciAddr, int cb,
346	uint32_t *pu32, int rcReschedule)
347	{
348	int rc = VINF_SUCCESS;
349	#ifdef IN_RING3
350	NOREF(rcReschedule);
351	#endif
352
353	if (pPciAddr->iBus != 0) /* forward to subordinate bus */
354	{
355	if (pPciRoot->PciBus.cBridges)
356	{
357	#ifdef IN_RING3 /** @todo do lookup in R0/RC too! r=klaus don't think that it can work, since the config space access callback only works in R3 */
358	PPDMPCIDEV pBridgeDevice = ich9pciFindBridge(&pPciRoot->PciBus, pPciAddr->iBus);
359	if (pBridgeDevice)
360	{
361	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigRead);
362	*pu32 = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->Int.s.CTX_SUFF(pDevIns), pPciAddr->iBus,
363	pPciAddr->iDeviceFunc, pPciAddr->iRegister, cb);
364	}
365	else
366	ich9pciNoMem(pu32, cb);
367	#else
368	rc = rcReschedule;
369	#endif
370	}
371	else
372	ich9pciNoMem(pu32, cb);
373	}
374	else /* forward to directly connected device */
375	{
376	R3PTRTYPE(PDMPCIDEV *) pPciDev = pPciRoot->PciBus.apDevices[pPciAddr->iDeviceFunc];
377	if (pPciDev)
378	{
379	#ifdef IN_RING3
380	*pu32 = pPciDev->Int.s.pfnConfigRead(pPciDev->Int.s.CTX_SUFF(pDevIns), pPciDev, pPciAddr->iRegister, cb);
381	#else
382	rc = rcReschedule;
383	#endif
384	}
385	else
386	ich9pciNoMem(pu32, cb);
387	}
388
389	Log3(("ich9pciDataReadAddr: %02x:%02x.%d reg %x(%d) gave %x %Rrc\n",
390	pPciAddr->iBus, pPciAddr->iDeviceFunc >> 3, pPciAddr->iDeviceFunc & 0x7, pPciAddr->iRegister,
391	cb, *pu32, rc));
392	return rc;
393	}
394
395
396	/*
397	* Decode value latched in Configuration Address Port and perform
398	* requsted read from the target configuration space register.
399	*
400	* XXX: This code should be probably moved to its only caller
401	* (ich9pciIOPortDataRead) to avoid prolifiration of confusingly
402	* similarly named functions.
403	*/
404	static int ich9pciDataRead(PDEVPCIROOT pPciRoot, uint32_t addr, int cb, uint32_t *pu32)
405	{
406	LogFlow(("ich9pciDataRead: config=%x cb=%d\n", pPciRoot->uConfigReg, cb));
407
408	*pu32 = 0xffffffff;
409
410	/* Configuration space mapping enabled? */
411	if (!(pPciRoot->uConfigReg & (1 << 31)))
412	return VINF_SUCCESS;
413
414	/* Decode target device and configuration space register */
415	PciAddress aPciAddr;
416	ich9pciStateToPciAddr(pPciRoot, addr, &aPciAddr);
417
418	/* Perform configuration space read */
419	return ich9pciDataReadAddr(pPciRoot, &aPciAddr, cb, pu32, VINF_IOM_R3_IOPORT_READ);
420	}
421
422
423	/**
424	* Port I/O Handler for PCI data IN operations.
425	*
426	* Emulates reads from Configuration Data Port at 0CFCh for
427	* Configuration Mechanism #1.
428	*
429	* @returns VBox status code.
430	*
431	* @param pDevIns ICH9 device instance.
432	* @param pvUser User argument - ignored.
433	* @param uPort Port number used for the IN operation.
434	* @param pu32 Where to store the result.
435	* @param cb Number of bytes read.
436	*/
437	PDMBOTHCBDECL(int) ich9pciIOPortDataRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT uPort, uint32_t pu32, unsigned cb)
438	{
439	NOREF(pvUser);
440	if (!(uPort % cb))
441	{
442	PDEVPCIROOT pThis = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
443
444	PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_READ);
445	int rc = ich9pciDataRead(pThis, uPort, cb, pu32);
446	PCI_UNLOCK(pDevIns);
447
448	LogFlow(("ich9pciIOPortDataRead: Port=%#x cb=%#x -> %#x (%Rrc)\n", uPort, cb, *pu32, rc));
449	return rc;
450	}
451	AssertMsgFailed(("Unaligned read from port %#x cb=%d\n", uPort, cb));
452	return VERR_IOM_IOPORT_UNUSED;
453	}
454
455
456	/* Compute mapping of PCI slot and IRQ number to APIC interrupt line */
457	DECLINLINE(int) ich9pciSlot2ApicIrq(uint8_t uSlot, int irq_num)
458	{
459	return (irq_num + uSlot) & 7;
460	}
461
462	#ifdef IN_RING3
463
464	/* return the global irq number corresponding to a given device irq
465	pin. We could also use the bus number to have a more precise
466	mapping. This is the implementation note described in the PCI spec chapter 2.2.6 */
467	DECLINLINE(int) ich9pciSlotGetPirq(uint8_t uBus, uint8_t uDevFn, int iIrqNum)
468	{
469	NOREF(uBus);
470	int iSlotAddend = (uDevFn >> 3) - 1;
471	return (iIrqNum + iSlotAddend) & 3;
472	}
473
474	/* irqs corresponding to PCI irqs A-D, must match pci_irq_list in rombios.c */
475	static const uint8_t aPciIrqs[4] = { 11, 10, 9, 5 };
476
477	#endif /* IN_RING3 */
478
479	/* Add one more level up request on APIC input line */
480	DECLINLINE(void) ich9pciApicLevelUp(PDEVPCIROOT pPciRoot, int irq_num)
481	{
482	ASMAtomicIncU32(&pPciRoot->auPciApicIrqLevels[irq_num]);
483	}
484
485	/* Remove one level up request on APIC input line */
486	DECLINLINE(void) ich9pciApicLevelDown(PDEVPCIROOT pPciRoot, int irq_num)
487	{
488	ASMAtomicDecU32(&pPciRoot->auPciApicIrqLevels[irq_num]);
489	}
490
491	static void ich9pciApicSetIrq(PDEVPCIBUS pBus, uint8_t uDevFn, PDMPCIDEV *pPciDev, int irq_num1, int iLevel,
492	uint32_t uTagSrc, int iForcedIrq)
493	{
494	/* This is only allowed to be called with a pointer to the root bus. */
495	AssertMsg(pBus->iBus == 0, ("iBus=%u\n", pBus->iBus));
496
497	if (iForcedIrq == -1)
498	{
499	int apic_irq, apic_level;
500	PDEVPCIROOT pPciRoot = DEVPCIBUS_2_DEVPCIROOT(pBus);
501	int irq_num = ich9pciSlot2ApicIrq(uDevFn >> 3, irq_num1);
502
503	if ((iLevel & PDM_IRQ_LEVEL_HIGH) == PDM_IRQ_LEVEL_HIGH)
504	ich9pciApicLevelUp(pPciRoot, irq_num);
505	else if ((iLevel & PDM_IRQ_LEVEL_HIGH) == PDM_IRQ_LEVEL_LOW)
506	ich9pciApicLevelDown(pPciRoot, irq_num);
507
508	apic_irq = irq_num + 0x10;
509	apic_level = pPciRoot->auPciApicIrqLevels[irq_num] != 0;
510	Log3(("ich9pciApicSetIrq: %s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d uTagSrc=%#x\n",
511	R3STRING(pPciDev->pszNameR3), irq_num1, iLevel, apic_irq, apic_level, irq_num, uTagSrc));
512	pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), apic_irq, apic_level, uTagSrc);
513
514	if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP)
515	{
516	/*
517	* we raised it few lines above, as PDM_IRQ_LEVEL_FLIP_FLOP has
518	* PDM_IRQ_LEVEL_HIGH bit set
519	*/
520	ich9pciApicLevelDown(pPciRoot, irq_num);
521	pPciDev->Int.s.uIrqPinState = PDM_IRQ_LEVEL_LOW;
522	apic_level = pPciRoot->auPciApicIrqLevels[irq_num] != 0;
523	Log3(("ich9pciApicSetIrq: %s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d uTagSrc=%#x (flop)\n",
524	R3STRING(pPciDev->pszNameR3), irq_num1, iLevel, apic_irq, apic_level, irq_num, uTagSrc));
525	pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), apic_irq, apic_level, uTagSrc);
526	}
527	} else {
528	Log3(("ich9pciApicSetIrq: (forced) %s: irq_num1=%d level=%d acpi_irq=%d uTagSrc=%#x\n",
529	R3STRING(pPciDev->pszNameR3), irq_num1, iLevel, iForcedIrq, uTagSrc));
530	pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), iForcedIrq, iLevel, uTagSrc);
531	}
532	}
533
534	static void ich9pciSetIrqInternal(PDEVPCIROOT pPciRoot, uint8_t uDevFn, PPDMPCIDEV pPciDev,
535	int iIrq, int iLevel, uint32_t uTagSrc)
536	{
537	/* If MSI or MSI-X is enabled, PCI INTx# signals are disabled regardless of the PCI command
538	* register interrupt bit state.
539	* PCI 3.0 (section 6.8) forbids MSI and MSI-X to be enabled at the same time and makes
540	* that undefined behavior. We check for MSI first, then MSI-X.
541	*/
542	if (MsiIsEnabled(pPciDev))
543	{
544	Assert(!MsixIsEnabled(pPciDev)); /* Not allowed -- see note above. */
545	LogFlowFunc(("PCI Dev %p : MSI\n", pPciDev));
546	PPDMDEVINS pDevIns = pPciRoot->PciBus.CTX_SUFF(pDevIns);
547	MsiNotify(pDevIns, pPciRoot->PciBus.CTX_SUFF(pPciHlp), pPciDev, iIrq, iLevel, uTagSrc);
548	return;
549	}
550
551	if (MsixIsEnabled(pPciDev))
552	{
553	LogFlowFunc(("PCI Dev %p : MSI-X\n", pPciDev));
554	PPDMDEVINS pDevIns = pPciRoot->PciBus.CTX_SUFF(pDevIns);
555	MsixNotify(pDevIns, pPciRoot->PciBus.CTX_SUFF(pPciHlp), pPciDev, iIrq, iLevel, uTagSrc);
556	return;
557	}
558
559	PDEVPCIBUS pBus = &pPciRoot->PciBus;
560	/* safe, only needs to go to the config space array */
561	const bool fIsAcpiDevice = PDMPciDevGetDeviceId(pPciDev) == 0x7113;
562
563	LogFlowFunc(("PCI Dev %p : IRQ\n", pPciDev));
564	/* Check if the state changed. */
565	if (pPciDev->Int.s.uIrqPinState != iLevel)
566	{
567	pPciDev->Int.s.uIrqPinState = (iLevel & PDM_IRQ_LEVEL_HIGH);
568
569	/* Send interrupt to I/O APIC only now. */
570	if (fIsAcpiDevice)
571	/*
572	* ACPI needs special treatment since SCI is hardwired and
573	* should not be affected by PCI IRQ routing tables at the
574	* same time SCI IRQ is shared in PCI sense hence this
575	* kludge (i.e. we fetch the hardwired value from ACPIs
576	* PCI device configuration space).
577	*/
578	/* safe, only needs to go to the config space array */
579	ich9pciApicSetIrq(pBus, uDevFn, pPciDev, -1, iLevel, uTagSrc, PDMPciDevGetInterruptLine(pPciDev));
580	else
581	ich9pciApicSetIrq(pBus, uDevFn, pPciDev, iIrq, iLevel, uTagSrc, -1);
582	}
583	}
584
585
586	/**
587	* Memory mapped I/O Handler for write operations.
588	*
589	* Emulates writes to configuration space.
590	*
591	* @returns VBox status code.
592	*
593	* @param pDevIns The device instance.
594	* @param pvUser User argument.
595	* @param GCPhysAddr Physical address (in GC) where the read starts.
596	* @param pv Where to fetch the result.
597	* @param cb Number of bytes to write.
598	* @remarks Caller enters the device critical section.
599	*/
600	PDMBOTHCBDECL(int) ich9pciMcfgMMIOWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void const pv, unsigned cb)
601	{
602	PDEVPCIROOT pPciRoot = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
603	uint32_t u32 = 0;
604	NOREF(pvUser);
605
606	Log2(("ich9pciMcfgMMIOWrite: %RGp(%d) \n", GCPhysAddr, cb));
607
608	PCI_LOCK(pDevIns, VINF_IOM_R3_MMIO_WRITE);
609
610	/* Decode target device and configuration space register */
611	PciAddress aDest;
612	ich9pciPhysToPciAddr(pPciRoot, GCPhysAddr, &aDest);
613
614	switch (cb)
615	{
616	case 1:
617	u32 = (uint8_t)pv;
618	break;
619	case 2:
620	u32 = (uint16_t)pv;
621	break;
622	case 4:
623	u32 = (uint32_t)pv;
624	break;
625	default:
626	Assert(false);
627	break;
628	}
629
630	/* Perform configuration space write */
631	int rc = ich9pciDataWriteAddr(pPciRoot, &aDest, u32, cb, VINF_IOM_R3_MMIO_WRITE);
632	PCI_UNLOCK(pDevIns);
633
634	return rc;
635	}
636
637
638	/**
639	* Memory mapped I/O Handler for read operations.
640	*
641	* Emulates reads from configuration space.
642	*
643	* @returns VBox status code.
644	*
645	* @param pDevIns The device instance.
646	* @param pvUser User argument.
647	* @param GCPhysAddr Physical address (in GC) where the read starts.
648	* @param pv Where to store the result.
649	* @param cb Number of bytes read.
650	* @remarks Caller enters the device critical section.
651	*/
652	PDMBOTHCBDECL(int) ich9pciMcfgMMIORead (PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb)
653	{
654	PDEVPCIROOT pPciRoot = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
655	uint32_t rv;
656	NOREF(pvUser);
657
658	LogFlow(("ich9pciMcfgMMIORead: %RGp(%d) \n", GCPhysAddr, cb));
659
660	PCI_LOCK(pDevIns, VINF_IOM_R3_MMIO_READ);
661
662	/* Decode target device and configuration space register */
663	PciAddress aDest;
664	ich9pciPhysToPciAddr(pPciRoot, GCPhysAddr, &aDest);
665
666	/* Perform configuration space read */
667	int rc = ich9pciDataReadAddr(pPciRoot, &aDest, cb, &rv, VINF_IOM_R3_MMIO_READ);
668
669	if (RT_SUCCESS(rc))
670	{
671	switch (cb)
672	{
673	case 1:
674	(uint8_t)pv = (uint8_t)rv;
675	break;
676	case 2:
677	(uint16_t)pv = (uint16_t)rv;
678	break;
679	case 4:
680	(uint32_t)pv = (uint32_t)rv;
681	break;
682	default:
683	Assert(false);
684	break;
685	}
686	}
687	PCI_UNLOCK(pDevIns);
688
689	return rc;
690	}
691
692	#ifdef IN_RING3
693
694	/*
695	* Include code we share with the other PCI bus implementation.
696	*
697	* Note! No #ifdefs, use instant data booleans/flags/whatever. Goal is to
698	* completely merge these files! File #1 contains code we write, where
699	* as a possible file #2 contains external code if there's any left.
700	*/
701	# include "DevPciMerge1.cpp.h"
702
703
704	DECLINLINE(PPDMPCIDEV) ich9pciFindBridge(PDEVPCIBUS pBus, uint8_t uBus)
705	{
706	/* Search for a fitting bridge. */
707	for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
708	{
709	/*
710	* Examine secondary and subordinate bus number.
711	* If the target bus is in the range we pass the request on to the bridge.
712	*/
713	PPDMPCIDEV pBridge = pBus->papBridgesR3[iBridge];
714	AssertMsg(pBridge && pciDevIsPci2PciBridge(pBridge),
715	("Device is not a PCI bridge but on the list of PCI bridges\n"));
716	/* safe, only needs to go to the config space array */
717	uint32_t uSecondary = PDMPciDevGetByte(pBridge, VBOX_PCI_SECONDARY_BUS);
718	/* safe, only needs to go to the config space array */
719	uint32_t uSubordinate = PDMPciDevGetByte(pBridge, VBOX_PCI_SUBORDINATE_BUS);
720	Log3(("ich9pciFindBridge on bus %p, bridge %d: %d in %d..%d\n", pBus, iBridge, uBus, uSecondary, uSubordinate));
721	if (uBus >= uSecondary && uBus <= uSubordinate)
722	return pBridge;
723	}
724
725	/* Nothing found. */
726	return NULL;
727	}
728
729	static uint32_t ich9pciGetCfg(PPDMPCIDEV pPciDev, int32_t iRegister, int cb)
730	{
731	return pPciDev->Int.s.pfnConfigRead(pPciDev->Int.s.CTX_SUFF(pDevIns), pPciDev, iRegister, cb);
732	}
733
734	DECLINLINE(uint8_t) ich9pciGetByte(PPDMPCIDEV pPciDev, int32_t iRegister)
735	{
736	return (uint8_t)ich9pciGetCfg(pPciDev, iRegister, 1);
737	}
738
739	DECLINLINE(uint16_t) ich9pciGetWord(PPDMPCIDEV pPciDev, int32_t iRegister)
740	{
741	return (uint16_t)ich9pciGetCfg(pPciDev, iRegister, 2);
742	}
743
744	DECLINLINE(uint32_t) ich9pciGetDWord(PPDMPCIDEV pPciDev, int32_t iRegister)
745	{
746	return (uint32_t)ich9pciGetCfg(pPciDev, iRegister, 4);
747	}
748
749	DECLINLINE(uint32_t) ich9pciGetRegionReg(int iRegion)
750	{
751	return iRegion == VBOX_PCI_ROM_SLOT
752	? VBOX_PCI_ROM_ADDRESS : (VBOX_PCI_BASE_ADDRESS_0 + iRegion * 4);
753	}
754
755	static void ich9pciSetCfg(PPDMPCIDEV pPciDev, int32_t iRegister, uint32_t u32, int cb)
756	{
757	pPciDev->Int.s.pfnConfigWrite(pPciDev->Int.s.CTX_SUFF(pDevIns), pPciDev, iRegister, u32, cb);
758	}
759
760	DECLINLINE(void) ich9pciSetByte(PPDMPCIDEV pPciDev, int32_t iRegister, uint8_t u8)
761	{
762	ich9pciSetCfg(pPciDev, iRegister, u8, 1);
763	}
764
765	DECLINLINE(void) ich9pciSetWord(PPDMPCIDEV pPciDev, int32_t iRegister, uint16_t u16)
766	{
767	ich9pciSetCfg(pPciDev, iRegister, u16, 2);
768	}
769
770	#if 0
771	DECLINLINE(void) ich9pciSetDWord(PPDMPCIDEV pPciDev, int32_t iRegister, uint32_t u32)
772	{
773	ich9pciSetCfg(pPciDev, iRegister, u32, 4);
774	}
775	#endif
776
777
778	/* -=-=-=-=-=- PCI Bus Interface Methods (PDMPCIBUSREG) -=-=-=-=-=- */
779
780
781	static DECLCALLBACK(int) ich9pciRegisterMsi(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, PPDMMSIREG pMsiReg)
782	{
783	NOREF(pDevIns);
784	int rc;
785
786	rc = MsiInit(pPciDev, pMsiReg);
787	if (RT_FAILURE(rc))
788	return rc;
789
790	rc = MsixInit(pPciDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pPciHlp), pPciDev, pMsiReg);
791	if (RT_FAILURE(rc))
792	return rc;
793
794	return VINF_SUCCESS;
795	}
796
797
798	/**
799	* @interface_method_impl{PDMPCIBUSREG,pfnIORegionRegisterR3}
800	*/
801	DECLCALLBACK(int) devpciR3CommonIORegionRegister(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iRegion, RTGCPHYS cbRegion,
802	PCIADDRESSSPACE enmType, PFNPCIIOREGIONMAP pfnCallback)
803	{
804	NOREF(pDevIns);
805
806	/*
807	* Validate.
808	*/
809	AssertMsgReturn( enmType == (PCI_ADDRESS_SPACE_MEM \| PCI_ADDRESS_SPACE_BAR32)
810	\|\| enmType == (PCI_ADDRESS_SPACE_MEM_PREFETCH \| PCI_ADDRESS_SPACE_BAR32)
811	\|\| enmType == (PCI_ADDRESS_SPACE_MEM \| PCI_ADDRESS_SPACE_BAR64)
812	\|\| enmType == (PCI_ADDRESS_SPACE_MEM_PREFETCH \| PCI_ADDRESS_SPACE_BAR64)
813	\|\| enmType == PCI_ADDRESS_SPACE_IO
814	,
815	("Invalid enmType=%#x? Or was this a bitmask after all...\n", enmType),
816	VERR_INVALID_PARAMETER);
817	AssertMsgReturn((unsigned)iRegion < VBOX_PCI_NUM_REGIONS,
818	("Invalid iRegion=%d VBOX_PCI_NUM_REGIONS=%d\n", iRegion, VBOX_PCI_NUM_REGIONS),
819	VERR_INVALID_PARAMETER);
820	int iLastSet = ASMBitLastSetU64(cbRegion);
821	AssertMsgReturn( iLastSet != 0
822	&& RT_BIT_64(iLastSet - 1) == cbRegion,
823	("Invalid cbRegion=%RGp iLastSet=%#x (not a power of 2 or 0)\n", cbRegion, iLastSet),
824	VERR_INVALID_PARAMETER);
825
826	Log(("devpciR3CommonIORegionRegister: %s region %d size %RGp type %x\n",
827	pPciDev->pszNameR3, iRegion, cbRegion, enmType));
828
829	/* Make sure that we haven't marked this region as continuation of 64-bit region. */
830	Assert(pPciDev->Int.s.aIORegions[iRegion].type != 0xff);
831
832	/*
833	* Register the I/O region.
834	*/
835	PPCIIOREGION pRegion = &pPciDev->Int.s.aIORegions[iRegion];
836	pRegion->addr = INVALID_PCI_ADDRESS;
837	pRegion->size = cbRegion;
838	pRegion->type = enmType;
839	pRegion->map_func = pfnCallback;
840
841	if ((enmType & PCI_ADDRESS_SPACE_BAR64) != 0)
842	{
843	/* VBOX_PCI_BASE_ADDRESS_5 and VBOX_PCI_ROM_ADDRESS are excluded. */
844	AssertMsgReturn(iRegion < VBOX_PCI_NUM_REGIONS - 2,
845	("Region %d cannot be 64-bit\n", iRegion),
846	VERR_INVALID_PARAMETER);
847	/* Mark next region as continuation of this one. */
848	pPciDev->Int.s.aIORegions[iRegion + 1].type = 0xff;
849	}
850
851	/* Set type in the PCI config space. */
852	AssertCompile(PCI_ADDRESS_SPACE_MEM == 0);
853	AssertCompile(PCI_ADDRESS_SPACE_IO == 1);
854	AssertCompile(PCI_ADDRESS_SPACE_BAR64 == RT_BIT_32(2));
855	AssertCompile(PCI_ADDRESS_SPACE_MEM_PREFETCH == RT_BIT_32(3));
856	uint32_t u32Value = (uint32_t)enmType & (PCI_ADDRESS_SPACE_IO \| PCI_ADDRESS_SPACE_BAR64 \| PCI_ADDRESS_SPACE_MEM_PREFETCH);
857	/* safe, only needs to go to the config space array */
858	PDMPciDevSetDWord(pPciDev, ich9pciGetRegionReg(iRegion), u32Value);
859
860	return VINF_SUCCESS;
861	}
862
863
864	/**
865	* @interface_method_impl{PDMPCIBUSREG,pfnSetConfigCallbacksR3}
866	*/
867	DECLCALLBACK(void) devpciR3CommonSetConfigCallbacks(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
868	PFNPCICONFIGREAD pfnRead, PPFNPCICONFIGREAD ppfnReadOld,
869	PFNPCICONFIGWRITE pfnWrite, PPFNPCICONFIGWRITE ppfnWriteOld)
870	{
871	NOREF(pDevIns);
872
873	if (ppfnReadOld)
874	*ppfnReadOld = pPciDev->Int.s.pfnConfigRead;
875	pPciDev->Int.s.pfnConfigRead = pfnRead;
876
877	if (ppfnWriteOld)
878	*ppfnWriteOld = pPciDev->Int.s.pfnConfigWrite;
879	pPciDev->Int.s.pfnConfigWrite = pfnWrite;
880	}
881
882
883	static int ich9pciR3CommonSaveExec(PDEVPCIBUS pBus, PSSMHANDLE pSSM)
884	{
885	/*
886	* Iterate thru all the devices.
887	*/
888	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
889	{
890	PPDMPCIDEV pDev = pBus->apDevices[i];
891	if (pDev)
892	{
893	/* Device position */
894	SSMR3PutU32(pSSM, i);
895	/* PCI config registers */
896	SSMR3PutMem(pSSM, pDev->abConfig, sizeof(pDev->abConfig));
897
898	/* Device flags */
899	int rc = SSMR3PutU32(pSSM, pDev->Int.s.fFlags);
900	if (RT_FAILURE(rc))
901	return rc;
902
903	/* IRQ pin state */
904	rc = SSMR3PutS32(pSSM, pDev->Int.s.uIrqPinState);
905	if (RT_FAILURE(rc))
906	return rc;
907
908	/* MSI info */
909	rc = SSMR3PutU8(pSSM, pDev->Int.s.u8MsiCapOffset);
910	if (RT_FAILURE(rc))
911	return rc;
912	rc = SSMR3PutU8(pSSM, pDev->Int.s.u8MsiCapSize);
913	if (RT_FAILURE(rc))
914	return rc;
915
916	/* MSI-X info */
917	rc = SSMR3PutU8(pSSM, pDev->Int.s.u8MsixCapOffset);
918	if (RT_FAILURE(rc))
919	return rc;
920	rc = SSMR3PutU8(pSSM, pDev->Int.s.u8MsixCapSize);
921	if (RT_FAILURE(rc))
922	return rc;
923
924	/* Save MSI-X page state */
925	if (pDev->Int.s.u8MsixCapOffset != 0)
926	{
927	Assert(pDev->Int.s.pMsixPageR3 != NULL);
928	SSMR3PutMem(pSSM, pDev->Int.s.pMsixPageR3, 0x1000);
929	if (RT_FAILURE(rc))
930	return rc;
931	}
932
933	/* Save the type an size of all the regions. */
934	for (uint32_t iRegion = 0; iRegion < VBOX_PCI_NUM_REGIONS; iRegion++)
935	{
936	SSMR3PutU8(pSSM, pDev->Int.s.aIORegions[iRegion].type);
937	rc = SSMR3PutU64(pSSM, pDev->Int.s.aIORegions[iRegion].size);
938	AssertRCReturn(rc, rc);
939	}
940	}
941	}
942	return SSMR3PutU32(pSSM, UINT32_MAX); /* terminator */
943	}
944
945	static DECLCALLBACK(int) ich9pciR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
946	{
947	PDEVPCIROOT pThis = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
948
949	/*
950	* Bus state data.
951	*/
952	SSMR3PutU32(pSSM, pThis->uConfigReg);
953
954	/*
955	* Save IRQ states.
956	*/
957	for (unsigned i = 0; i < RT_ELEMENTS(pThis->auPciApicIrqLevels); i++)
958	SSMR3PutU32(pSSM, pThis->auPciApicIrqLevels[i]);
959
960	SSMR3PutU32(pSSM, UINT32_MAX); /* separator */
961
962	return ich9pciR3CommonSaveExec(&pThis->PciBus, pSSM);
963	}
964
965
966	static DECLCALLBACK(int) ich9pcibridgeR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
967	{
968	PDEVPCIBUS pThis = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
969	return ich9pciR3CommonSaveExec(pThis, pSSM);
970	}
971
972
973	static DECLCALLBACK(void) ich9pcibridgeConfigWrite(PPDMDEVINSR3 pDevIns, uint8_t uBus, uint8_t uDevice, uint32_t u32Address, uint32_t u32Value, unsigned cb)
974	{
975	PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
976
977	LogFlowFunc((": pDevIns=%p uBus=%d uDevice=%d u32Address=%u u32Value=%u cb=%d\n", pDevIns, uBus, uDevice, u32Address, u32Value, cb));
978
979	/* If the current bus is not the target bus search for the bus which contains the device. */
980	/* safe, only needs to go to the config space array */
981	if (uBus != PDMPciDevGetByte(&pBus->PciDev, VBOX_PCI_SECONDARY_BUS))
982	{
983	PPDMPCIDEV pBridgeDevice = ich9pciFindBridge(pBus, uBus);
984	if (pBridgeDevice)
985	{
986	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigWrite);
987	pBridgeDevice->Int.s.pfnBridgeConfigWrite(pBridgeDevice->Int.s.CTX_SUFF(pDevIns), uBus, uDevice,
988	u32Address, u32Value, cb);
989	}
990	}
991	else
992	{
993	/* This is the target bus, pass the write to the device. */
994	PPDMPCIDEV pPciDev = pBus->apDevices[uDevice];
995	if (pPciDev)
996	{
997	Log(("%s: %s: addr=%02x val=%08x len=%d\n", __FUNCTION__, pPciDev->pszNameR3, u32Address, u32Value, cb));
998	pPciDev->Int.s.pfnConfigWrite(pPciDev->Int.s.CTX_SUFF(pDevIns), pPciDev, u32Address, u32Value, cb);
999	}
1000	}
1001	}
1002
1003	static DECLCALLBACK(uint32_t) ich9pcibridgeConfigRead(PPDMDEVINSR3 pDevIns, uint8_t uBus, uint8_t uDevice, uint32_t u32Address, unsigned cb)
1004	{
1005	PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
1006	uint32_t u32Value;
1007
1008	LogFlowFunc((": pDevIns=%p uBus=%d uDevice=%d u32Address=%u cb=%d\n", pDevIns, uBus, uDevice, u32Address, cb));
1009
1010	/* If the current bus is not the target bus search for the bus which contains the device. */
1011	/* safe, only needs to go to the config space array */
1012	if (uBus != PDMPciDevGetByte(&pBus->PciDev, VBOX_PCI_SECONDARY_BUS))
1013	{
1014	PPDMPCIDEV pBridgeDevice = ich9pciFindBridge(pBus, uBus);
1015	if (pBridgeDevice)
1016	{
1017	AssertPtr( pBridgeDevice->Int.s.pfnBridgeConfigRead);
1018	u32Value = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->Int.s.CTX_SUFF(pDevIns), uBus, uDevice,
1019	u32Address, cb);
1020	}
1021	else
1022	ich9pciNoMem(&u32Value, 4);
1023	}
1024	else
1025	{
1026	/* This is the target bus, pass the read to the device. */
1027	PPDMPCIDEV pPciDev = pBus->apDevices[uDevice];
1028	if (pPciDev)
1029	{
1030	u32Value = pPciDev->Int.s.pfnConfigRead(pPciDev->Int.s.CTX_SUFF(pDevIns), pPciDev, u32Address, cb);
1031	Log(("%s: %s: u32Address=%02x u32Value=%08x cb=%d\n", __FUNCTION__, pPciDev->pszNameR3, u32Address, u32Value, cb));
1032	}
1033	else
1034	ich9pciNoMem(&u32Value, 4);
1035	}
1036
1037	return u32Value;
1038	}
1039
1040
1041
1042	/* -=-=-=-=-=- Saved State -=-=-=-=-=- */
1043
1044
1045	/**
1046	* Common routine for restoring the config registers of a PCI device.
1047	*
1048	* @param pDev The PCI device.
1049	* @param pbSrcConfig The configuration register values to be loaded.
1050	*/
1051	void devpciR3CommonRestoreConfig(PPDMPCIDEV pDev, uint8_t const *pbSrcConfig)
1052	{
1053	/*
1054	* This table defines the fields for normal devices and bridge devices, and
1055	* the order in which they need to be restored.
1056	*/
1057	static const struct PciField
1058	{
1059	uint8_t off;
1060	uint8_t cb;
1061	uint8_t fWritable;
1062	uint8_t fBridge;
1063	const char *pszName;
1064	} s_aFields[] =
1065	{
1066	/* off,cb,fW,fB, pszName */
1067	{ 0x00, 2, 0, 3, "VENDOR_ID" },
1068	{ 0x02, 2, 0, 3, "DEVICE_ID" },
1069	{ 0x06, 2, 1, 3, "STATUS" },
1070	{ 0x08, 1, 0, 3, "REVISION_ID" },
1071	{ 0x09, 1, 0, 3, "CLASS_PROG" },
1072	{ 0x0a, 1, 0, 3, "CLASS_SUB" },
1073	{ 0x0b, 1, 0, 3, "CLASS_BASE" },
1074	{ 0x0c, 1, 1, 3, "CACHE_LINE_SIZE" },
1075	{ 0x0d, 1, 1, 3, "LATENCY_TIMER" },
1076	{ 0x0e, 1, 0, 3, "HEADER_TYPE" },
1077	{ 0x0f, 1, 1, 3, "BIST" },
1078	{ 0x10, 4, 1, 3, "BASE_ADDRESS_0" },
1079	{ 0x14, 4, 1, 3, "BASE_ADDRESS_1" },
1080	{ 0x18, 4, 1, 1, "BASE_ADDRESS_2" },
1081	{ 0x18, 1, 1, 2, "PRIMARY_BUS" },
1082	{ 0x19, 1, 1, 2, "SECONDARY_BUS" },
1083	{ 0x1a, 1, 1, 2, "SUBORDINATE_BUS" },
1084	{ 0x1b, 1, 1, 2, "SEC_LATENCY_TIMER" },
1085	{ 0x1c, 4, 1, 1, "BASE_ADDRESS_3" },
1086	{ 0x1c, 1, 1, 2, "IO_BASE" },
1087	{ 0x1d, 1, 1, 2, "IO_LIMIT" },
1088	{ 0x1e, 2, 1, 2, "SEC_STATUS" },
1089	{ 0x20, 4, 1, 1, "BASE_ADDRESS_4" },
1090	{ 0x20, 2, 1, 2, "MEMORY_BASE" },
1091	{ 0x22, 2, 1, 2, "MEMORY_LIMIT" },
1092	{ 0x24, 4, 1, 1, "BASE_ADDRESS_5" },
1093	{ 0x24, 2, 1, 2, "PREF_MEMORY_BASE" },
1094	{ 0x26, 2, 1, 2, "PREF_MEMORY_LIMIT" },
1095	{ 0x28, 4, 0, 1, "CARDBUS_CIS" },
1096	{ 0x28, 4, 1, 2, "PREF_BASE_UPPER32" },
1097	{ 0x2c, 2, 0, 1, "SUBSYSTEM_VENDOR_ID" },
1098	{ 0x2c, 4, 1, 2, "PREF_LIMIT_UPPER32" },
1099	{ 0x2e, 2, 0, 1, "SUBSYSTEM_ID" },
1100	{ 0x30, 4, 1, 1, "ROM_ADDRESS" },
1101	{ 0x30, 2, 1, 2, "IO_BASE_UPPER16" },
1102	{ 0x32, 2, 1, 2, "IO_LIMIT_UPPER16" },
1103	{ 0x34, 4, 0, 3, "CAPABILITY_LIST" },
1104	{ 0x38, 4, 1, 1, "RESERVED_38" },
1105	{ 0x38, 4, 1, 2, "ROM_ADDRESS_BR" },
1106	{ 0x3c, 1, 1, 3, "INTERRUPT_LINE" },
1107	{ 0x3d, 1, 0, 3, "INTERRUPT_PIN" },
1108	{ 0x3e, 1, 0, 1, "MIN_GNT" },
1109	{ 0x3e, 2, 1, 2, "BRIDGE_CONTROL" },
1110	{ 0x3f, 1, 0, 1, "MAX_LAT" },
1111	/* The COMMAND register must come last as it requires the ADDRESS
1112	registers to be restored before we pretent to change it from 0 to
1113	whatever value the guest assigned it. */
1114	{ 0x04, 2, 1, 3, "COMMAND" },
1115	};
1116
1117	#ifdef RT_STRICT
1118	/* Check that we've got full register coverage. */
1119	uint32_t bmDevice[0x40 / 32];
1120	uint32_t bmBridge[0x40 / 32];
1121	RT_ZERO(bmDevice);
1122	RT_ZERO(bmBridge);
1123	for (uint32_t i = 0; i < RT_ELEMENTS(s_aFields); i++)
1124	{
1125	uint8_t off = s_aFields[i].off;
1126	uint8_t cb = s_aFields[i].cb;
1127	uint8_t f = s_aFields[i].fBridge;
1128	while (cb-- > 0)
1129	{
1130	if (f & 1) AssertMsg(!ASMBitTest(bmDevice, off), ("%#x\n", off));
1131	if (f & 2) AssertMsg(!ASMBitTest(bmBridge, off), ("%#x\n", off));
1132	if (f & 1) ASMBitSet(bmDevice, off);
1133	if (f & 2) ASMBitSet(bmBridge, off);
1134	off++;
1135	}
1136	}
1137	for (uint32_t off = 0; off < 0x40; off++)
1138	{
1139	AssertMsg(ASMBitTest(bmDevice, off), ("%#x\n", off));
1140	AssertMsg(ASMBitTest(bmBridge, off), ("%#x\n", off));
1141	}
1142	#endif
1143
1144	/*
1145	* Loop thru the fields covering the 64 bytes of standard registers.
1146	*/
1147	uint8_t const fBridge = pciDevIsPci2PciBridge(pDev) ? 2 : 1;
1148	Assert(!pciDevIsPassthrough(pDev));
1149	uint8_t *pbDstConfig = &pDev->abConfig[0];
1150
1151	for (uint32_t i = 0; i < RT_ELEMENTS(s_aFields); i++)
1152	if (s_aFields[i].fBridge & fBridge)
1153	{
1154	uint8_t const off = s_aFields[i].off;
1155	uint8_t const cb = s_aFields[i].cb;
1156	uint32_t u32Src;
1157	uint32_t u32Dst;
1158	switch (cb)
1159	{
1160	case 1:
1161	u32Src = pbSrcConfig[off];
1162	u32Dst = pbDstConfig[off];
1163	break;
1164	case 2:
1165	u32Src = (uint16_t const )&pbSrcConfig[off];
1166	u32Dst = (uint16_t const )&pbDstConfig[off];
1167	break;
1168	case 4:
1169	u32Src = (uint32_t const )&pbSrcConfig[off];
1170	u32Dst = (uint32_t const )&pbDstConfig[off];
1171	break;
1172	default:
1173	AssertFailed();
1174	continue;
1175	}
1176
1177	if ( u32Src != u32Dst
1178	\|\| off == VBOX_PCI_COMMAND)
1179	{
1180	if (u32Src != u32Dst)
1181	{
1182	if (!s_aFields[i].fWritable)
1183	LogRel(("PCI: %8s/%u: %2u-bit field %s: %x -> %x - !READ ONLY!\n",
1184	pDev->pszNameR3, pDev->Int.s.CTX_SUFF(pDevIns)->iInstance, cb*8, s_aFields[i].pszName, u32Dst, u32Src));
1185	else
1186	LogRel(("PCI: %8s/%u: %2u-bit field %s: %x -> %x\n",
1187	pDev->pszNameR3, pDev->Int.s.CTX_SUFF(pDevIns)->iInstance, cb*8, s_aFields[i].pszName, u32Dst, u32Src));
1188	}
1189	if (off == VBOX_PCI_COMMAND)
1190	/* safe, only needs to go to the config space array */
1191	PDMPciDevSetCommand(pDev, 0); /* For remapping, see ich9pciR3CommonLoadExec. */
1192	pDev->Int.s.pfnConfigWrite(pDev->Int.s.CTX_SUFF(pDevIns), pDev, off, u32Src, cb);
1193	}
1194	}
1195
1196	/*
1197	* The device dependent registers.
1198	*
1199	* We will not use ConfigWrite here as we have no clue about the size
1200	* of the registers, so the device is responsible for correctly
1201	* restoring functionality governed by these registers.
1202	*/
1203	for (uint32_t off = 0x40; off < sizeof(pDev->abConfig); off++)
1204	if (pbDstConfig[off] != pbSrcConfig[off])
1205	{
1206	LogRel(("PCI: %8s/%u: register %02x: %02x -> %02x\n",
1207	pDev->pszNameR3, pDev->Int.s.CTX_SUFF(pDevIns)->iInstance, off, pbDstConfig[off], pbSrcConfig[off])); /** @todo make this Log() later. */
1208	pbDstConfig[off] = pbSrcConfig[off];
1209	}
1210	}
1211
1212
1213	/**
1214	* @callback_method_impl{FNPCIIOREGIONOLDSETTER}
1215	*/
1216	static DECLCALLBACK(int) devpciR3CommonRestoreOldSetRegion(PPDMPCIDEV pPciDev, uint32_t iRegion,
1217	RTGCPHYS cbRegion, PCIADDRESSSPACE enmType)
1218	{
1219	AssertLogRelReturn(iRegion < RT_ELEMENTS(pPciDev->Int.s.aIORegions), VERR_INVALID_PARAMETER);
1220	pPciDev->Int.s.aIORegions[iRegion].type = enmType;
1221	pPciDev->Int.s.aIORegions[iRegion].size = cbRegion;
1222	return VINF_SUCCESS;
1223	}
1224
1225
1226	/**
1227	* Checks for and deals with changes in resource sizes and types.
1228	*
1229	* @returns VBox status code.
1230	* @param pSSM The Saved state handle.
1231	* @param pPciDev The PCI device in question.
1232	* @param paIoRegions I/O regions with the size and type fields from
1233	* the saved state.
1234	* @param fNewState Set if this is a new state with I/O region sizes
1235	* and types, clear if old one.
1236	*/
1237	int devpciR3CommonRestoreRegions(PSSMHANDLE pSSM, PPDMPCIDEV pPciDev, PPCIIOREGION paIoRegions, bool fNewState)
1238	{
1239	int rc;
1240	if (fNewState)
1241	{
1242	for (uint32_t iRegion = 0; iRegion < VBOX_PCI_NUM_REGIONS; iRegion++)
1243	{
1244	if ( pPciDev->Int.s.aIORegions[iRegion].type != paIoRegions[iRegion].type
1245	\|\| pPciDev->Int.s.aIORegions[iRegion].size != paIoRegions[iRegion].size)
1246	{
1247	AssertLogRelMsgFailed(("PCI: %8s/%u: region #%u size/type load change: %#RGp/%#x -> %#RGp/%#x\n",
1248	pPciDev->pszNameR3, pPciDev->Int.s.CTX_SUFF(pDevIns)->iInstance, iRegion,
1249	pPciDev->Int.s.aIORegions[iRegion].size, pPciDev->Int.s.aIORegions[iRegion].type,
1250	paIoRegions[iRegion].size, paIoRegions[iRegion].type));
1251	if (pPciDev->pfnRegionLoadChangeHookR3)
1252	{
1253	rc = pPciDev->pfnRegionLoadChangeHookR3(pPciDev->Int.s.pDevInsR3, pPciDev, iRegion, paIoRegions[iRegion].size,
1254	(PCIADDRESSSPACE)paIoRegions[iRegion].type, NULL /pfnOldSetter/);
1255	if (RT_FAILURE(rc))
1256	return SSMR3SetLoadError(pSSM, rc, RT_SRC_POS,
1257	N_("Device %s/%u failed to respond to region #%u size/type changing from %#RGp/%#x to %#RGp/%#x: %Rrc"),
1258	pPciDev->pszNameR3, pPciDev->Int.s.CTX_SUFF(pDevIns)->iInstance, iRegion,
1259	pPciDev->Int.s.aIORegions[iRegion].size, pPciDev->Int.s.aIORegions[iRegion].type,
1260	paIoRegions[iRegion].size, paIoRegions[iRegion].type, rc);
1261	}
1262	pPciDev->Int.s.aIORegions[iRegion].type = paIoRegions[iRegion].type;
1263	pPciDev->Int.s.aIORegions[iRegion].size = paIoRegions[iRegion].size;
1264	}
1265	}
1266	}
1267	/* Old saved state without sizes and types. Do a special hook call to give
1268	devices with changes a chance to adjust resources back to old values. */
1269	else if (pPciDev->pfnRegionLoadChangeHookR3)
1270	{
1271	rc = pPciDev->pfnRegionLoadChangeHookR3(pPciDev->Int.s.pDevInsR3, pPciDev, UINT32_MAX, RTGCPHYS_MAX, (PCIADDRESSSPACE)-1,
1272	devpciR3CommonRestoreOldSetRegion);
1273	if (RT_FAILURE(rc))
1274	return SSMR3SetLoadError(pSSM, rc, RT_SRC_POS, N_("Device %s/%u failed to resize its resources: %Rrc"),
1275	pPciDev->pszNameR3, pPciDev->Int.s.CTX_SUFF(pDevIns)->iInstance, rc);
1276	}
1277	return VINF_SUCCESS;
1278	}
1279
1280
1281	/**
1282	* Common worker for ich9pciR3LoadExec and ich9pcibridgeR3LoadExec.
1283	*
1284	* @returns VBox status code.
1285	* @param pBus The bus which data is being loaded.
1286	* @param pSSM The saved state handle.
1287	* @param uVersion The data version.
1288	* @param uPass The pass.
1289	*/
1290	static DECLCALLBACK(int) ich9pciR3CommonLoadExec(PDEVPCIBUS pBus, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1291	{
1292	uint32_t u32;
1293	uint32_t i;
1294	int rc;
1295
1296	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
1297	if ( uVersion < VBOX_ICH9PCI_SAVED_STATE_VERSION_MSI
1298	\|\| uVersion > VBOX_ICH9PCI_SAVED_STATE_VERSION)
1299	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1300
1301	/*
1302	* Iterate thru all the devices and write 0 to the COMMAND register so
1303	* that all the memory is unmapped before we start restoring the saved
1304	* mapping locations.
1305	*
1306	* The register value is restored afterwards so we can do proper
1307	* LogRels in devpciR3CommonRestoreConfig.
1308	*/
1309	for (i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
1310	{
1311	PPDMPCIDEV pDev = pBus->apDevices[i];
1312	if (pDev)
1313	{
1314	/* safe, only needs to go to the config space array */
1315	uint16_t u16 = PDMPciDevGetCommand(pDev);
1316	pDev->Int.s.pfnConfigWrite(pDev->Int.s.CTX_SUFF(pDevIns), pDev, VBOX_PCI_COMMAND, 0, 2);
1317	/* safe, only needs to go to the config space array */
1318	PDMPciDevSetCommand(pDev, u16);
1319	/* safe, only needs to go to the config space array */
1320	Assert(PDMPciDevGetCommand(pDev) == u16);
1321	}
1322	}
1323
1324	void *pvMsixPage = RTMemTmpAllocZ(0x1000);
1325	AssertReturn(pvMsixPage, VERR_NO_TMP_MEMORY);
1326
1327	/*
1328	* Iterate all the devices.
1329	*/
1330	for (i = 0;; i++)
1331	{
1332	/* index / terminator */
1333	rc = SSMR3GetU32(pSSM, &u32);
1334	if (RT_FAILURE(rc))
1335	break;
1336	if (u32 == (uint32_t)~0)
1337	break;
1338	AssertMsgBreak(u32 < RT_ELEMENTS(pBus->apDevices) && u32 >= i, ("u32=%#x i=%#x\n", u32, i));
1339
1340	/* skip forward to the device checking that no new devices are present. */
1341	PPDMPCIDEV pDev;
1342	for (; i < u32; i++)
1343	{
1344	pDev = pBus->apDevices[i];
1345	if (pDev)
1346	{
1347	/* safe, only needs to go to the config space array */
1348	LogRel(("PCI: New device in slot %#x, %s (vendor=%#06x device=%#06x)\n", i, pDev->pszNameR3,
1349	PDMPciDevGetVendorId(pDev), PDMPciDevGetDeviceId(pDev)));
1350	if (SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT)
1351	{
1352	/* safe, only needs to go to the config space array */
1353	rc = SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("New device in slot %#x, %s (vendor=%#06x device=%#06x)"),
1354	i, pDev->pszNameR3, PDMPciDevGetVendorId(pDev), PDMPciDevGetDeviceId(pDev));
1355	break;
1356	}
1357	}
1358	}
1359	if (RT_FAILURE(rc))
1360	break;
1361
1362	/* get the data */
1363	PDMPCIDEV DevTmp;
1364	RT_ZERO(DevTmp);
1365	DevTmp.Int.s.fFlags = 0;
1366	DevTmp.Int.s.u8MsiCapOffset = 0;
1367	DevTmp.Int.s.u8MsiCapSize = 0;
1368	DevTmp.Int.s.u8MsixCapOffset = 0;
1369	DevTmp.Int.s.u8MsixCapSize = 0;
1370	DevTmp.Int.s.uIrqPinState = ~0; /* Invalid value in case we have an older saved state to force a state change in pciSetIrq. */
1371	SSMR3GetMem(pSSM, DevTmp.abConfig, sizeof(DevTmp.abConfig));
1372
1373	SSMR3GetU32(pSSM, &DevTmp.Int.s.fFlags);
1374	SSMR3GetS32(pSSM, &DevTmp.Int.s.uIrqPinState);
1375	SSMR3GetU8(pSSM, &DevTmp.Int.s.u8MsiCapOffset);
1376	SSMR3GetU8(pSSM, &DevTmp.Int.s.u8MsiCapSize);
1377	SSMR3GetU8(pSSM, &DevTmp.Int.s.u8MsixCapOffset);
1378	rc = SSMR3GetU8(pSSM, &DevTmp.Int.s.u8MsixCapSize);
1379	if (RT_FAILURE(rc))
1380	break;
1381
1382	/* Load MSI-X page state */
1383	if (DevTmp.Int.s.u8MsixCapOffset != 0)
1384	{
1385	Assert(pvMsixPage != NULL);
1386	rc = SSMR3GetMem(pSSM, pvMsixPage, 0x1000);
1387	if (RT_FAILURE(rc))
1388	break;
1389	}
1390
1391	/* Load the region types and sizes. */
1392	if (uVersion >= VBOX_ICH9PCI_SAVED_STATE_VERSION_REGION_SIZES)
1393	{
1394	for (uint32_t iRegion = 0; iRegion < VBOX_PCI_NUM_REGIONS; iRegion++)
1395	{
1396	SSMR3GetU8(pSSM, &DevTmp.Int.s.aIORegions[iRegion].type);
1397	rc = SSMR3GetU64(pSSM, &DevTmp.Int.s.aIORegions[iRegion].size);
1398	AssertLogRelRCReturn(rc, rc);
1399	}
1400	}
1401
1402	/*
1403	* Check that it's still around.
1404	*/
1405	pDev = pBus->apDevices[i];
1406	if (!pDev)
1407	{
1408	/* safe, only needs to go to the config space array */
1409	LogRel(("PCI: Device in slot %#x has been removed! vendor=%#06x device=%#06x\n", i,
1410	PDMPciDevGetVendorId(&DevTmp), PDMPciDevGetDeviceId(&DevTmp)));
1411	if (SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT)
1412	{
1413	/* safe, only needs to go to the config space array */
1414	rc = SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Device in slot %#x has been removed! vendor=%#06x device=%#06x"),
1415	i, PDMPciDevGetVendorId(&DevTmp), PDMPciDevGetDeviceId(&DevTmp));
1416	break;
1417	}
1418	continue;
1419	}
1420
1421	/* match the vendor id assuming that this will never be changed. */
1422	/* safe, only needs to go to the config space array */
1423	if (PDMPciDevGetVendorId(&DevTmp) != PDMPciDevGetVendorId(pDev))
1424	{
1425	/* safe, only needs to go to the config space array */
1426	rc = SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Device in slot %#x (%s) vendor id mismatch! saved=%.4Rhxs current=%.4Rhxs"),
1427	i, pDev->pszNameR3, PDMPciDevGetVendorId(&DevTmp), PDMPciDevGetVendorId(pDev));
1428	break;
1429	}
1430
1431	/* commit the loaded device config. */
1432	rc = devpciR3CommonRestoreRegions(pSSM, pDev, DevTmp.Int.s.aIORegions,
1433	uVersion >= VBOX_ICH9PCI_SAVED_STATE_VERSION_REGION_SIZES);
1434	if (RT_FAILURE(rc))
1435	break;
1436	Assert(!pciDevIsPassthrough(pDev));
1437	devpciR3CommonRestoreConfig(pDev, &DevTmp.abConfig[0]);
1438
1439	pDev->Int.s.uIrqPinState = DevTmp.Int.s.uIrqPinState;
1440	pDev->Int.s.u8MsiCapOffset = DevTmp.Int.s.u8MsiCapOffset;
1441	pDev->Int.s.u8MsiCapSize = DevTmp.Int.s.u8MsiCapSize;
1442	pDev->Int.s.u8MsixCapOffset = DevTmp.Int.s.u8MsixCapOffset;
1443	pDev->Int.s.u8MsixCapSize = DevTmp.Int.s.u8MsixCapSize;
1444	if (DevTmp.Int.s.u8MsixCapSize != 0)
1445	{
1446	Assert(pDev->Int.s.pMsixPageR3 != NULL);
1447	memcpy(pDev->Int.s.pMsixPageR3, pvMsixPage, 0x1000);
1448	}
1449	}
1450
1451	RTMemTmpFree(pvMsixPage);
1452
1453	return rc;
1454	}
1455
1456	static DECLCALLBACK(int) ich9pciR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1457	{
1458	PDEVPCIROOT pThis = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
1459	PDEVPCIBUS pBus = &pThis->PciBus;
1460	uint32_t u32;
1461	int rc;
1462
1463	/* We ignore this version as there's no saved state with it anyway */
1464	if (uVersion <= VBOX_ICH9PCI_SAVED_STATE_VERSION_NOMSI)
1465	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1466	if (uVersion > VBOX_ICH9PCI_SAVED_STATE_VERSION)
1467	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1468
1469	/*
1470	* Bus state data.
1471	*/
1472	SSMR3GetU32(pSSM, &pThis->uConfigReg);
1473
1474	/*
1475	* Load IRQ states.
1476	*/
1477	for (unsigned i = 0; i < RT_ELEMENTS(pThis->auPciApicIrqLevels); i++)
1478	SSMR3GetU32(pSSM, (uint32_t*)&pThis->auPciApicIrqLevels[i]);
1479
1480	/* separator */
1481	rc = SSMR3GetU32(pSSM, &u32);
1482	if (RT_FAILURE(rc))
1483	return rc;
1484	if (u32 != (uint32_t)~0)
1485	AssertMsgFailedReturn(("u32=%#x\n", u32), rc);
1486
1487	return ich9pciR3CommonLoadExec(pBus, pSSM, uVersion, uPass);
1488	}
1489
1490	static DECLCALLBACK(int) ich9pcibridgeR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1491	{
1492	PDEVPCIBUS pThis = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
1493	return ich9pciR3CommonLoadExec(pThis, pSSM, uVersion, uPass);
1494	}
1495
1496
1497
1498	/* -=-=-=-=-=- Fake PCI BIOS Init -=-=-=-=-=- */
1499
1500
1501	/*
1502	* Perform immediate read of configuration space register.
1503	* Cannot be rescheduled, as already in R3.
1504	*/
1505	static uint32_t ich9pciBiosInitReadConfig(PDEVPCIROOT pPciRoot, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t len)
1506	{
1507	PciAddress aPciAddr;
1508	aPciAddr.iBus = uBus;
1509	aPciAddr.iDeviceFunc = uDevFn;
1510	aPciAddr.iRegister = addr;
1511
1512	uint32_t u32Val = 0;
1513	int rc = ich9pciDataReadAddr(pPciRoot, &aPciAddr, len, &u32Val, VERR_INTERNAL_ERROR);
1514	AssertRC(rc);
1515
1516	return u32Val;
1517	}
1518
1519
1520	/*
1521	* Perform imeediate write to configuration space register.
1522	* Cannot be rescheduled, as already in R3.
1523	*/
1524	static void ich9pciBiosInitWriteConfig(PDEVPCIROOT pPciRoot, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t val, uint32_t len)
1525	{
1526	PciAddress aPciAddr;
1527	aPciAddr.iBus = uBus;
1528	aPciAddr.iDeviceFunc = uDevFn;
1529	aPciAddr.iRegister = addr;
1530
1531	int rc = ich9pciDataWriteAddr(pPciRoot, &aPciAddr, val, len, VERR_INTERNAL_ERROR);
1532	AssertRC(rc);
1533	}
1534
1535
1536	static void ich9pciBiosInitSetRegionAddress(PDEVPCIROOT pPciRoot, uint8_t uBus, uint8_t uDevFn, int iRegion, uint64_t addr)
1537	{
1538	uint32_t uReg = ich9pciGetRegionReg(iRegion);
1539
1540	/* Read memory type first. */
1541	uint8_t uResourceType = ich9pciBiosInitReadConfig(pPciRoot, uBus, uDevFn, uReg, 1);
1542	bool f64Bit = (uResourceType & ((uint8_t)(PCI_ADDRESS_SPACE_BAR64 \| PCI_ADDRESS_SPACE_IO)))
1543	== PCI_ADDRESS_SPACE_BAR64;
1544
1545	Log(("Set region address: %02x:%02x.%d region %d address=%RX64%s\n",
1546	uBus, uDevFn >> 3, uDevFn & 7, iRegion, addr, f64Bit ? " (64-bit)" : ""));
1547
1548	/* Write address of the device. */
1549	ich9pciBiosInitWriteConfig(pPciRoot, uBus, uDevFn, uReg, (uint32_t)addr, 4);
1550	if (f64Bit)
1551	ich9pciBiosInitWriteConfig(pPciRoot, uBus, uDevFn, uReg + 4, (uint32_t)(addr >> 32), 4);
1552	}
1553
1554
1555	static void ich9pciBiosInitBridge(PDEVPCIROOT pPciRoot, uint8_t uBus, uint8_t uDevFn)
1556	{
1557	Log(("BIOS init bridge: %02x:%02x.%d\n", uBus, uDevFn >> 3, uDevFn & 7));
1558
1559	/*
1560	* The I/O range for the bridge must be aligned to a 4KB boundary.
1561	* This does not change anything really as the access to the device is not going
1562	* through the bridge but we want to be compliant to the spec.
1563	*/
1564	if ((pPciRoot->uPciBiosIo % 4096) != 0)
1565	{
1566	pPciRoot->uPciBiosIo = RT_ALIGN_32(pPciRoot->uPciBiosIo, 4*1024);
1567	Log(("%s: Aligned I/O start address. New address %#x\n", __FUNCTION__, pPciRoot->uPciBiosIo));
1568	}
1569	ich9pciBiosInitWriteConfig(pPciRoot, uBus, uDevFn, VBOX_PCI_IO_BASE, (pPciRoot->uPciBiosIo >> 8) & 0xf0, 1);
1570
1571	/* The MMIO range for the bridge must be aligned to a 1MB boundary. */
1572	if ((pPciRoot->uPciBiosMmio % (1024 * 1024)) != 0)
1573	{
1574	pPciRoot->uPciBiosMmio = RT_ALIGN_32(pPciRoot->uPciBiosMmio, 1024*1024);
1575	Log(("%s: Aligned MMIO start address. New address %#x\n", __FUNCTION__, pPciRoot->uPciBiosMmio));
1576	}
1577	ich9pciBiosInitWriteConfig(pPciRoot, uBus, uDevFn, VBOX_PCI_MEMORY_BASE, (pPciRoot->uPciBiosMmio >> 16) & UINT32_C(0xffff0), 2);
1578
1579	/* Save values to compare later to. */
1580	uint32_t u32IoAddressBase = pPciRoot->uPciBiosIo;
1581	uint32_t u32MMIOAddressBase = pPciRoot->uPciBiosMmio;
1582	uint8_t uBridgeBus = ich9pciBiosInitReadConfig(pPciRoot, uBus, uDevFn, VBOX_PCI_SECONDARY_BUS, 1);
1583
1584	/* Init all devices behind the bridge (recursing to further buses). */
1585	ich9pciBiosInitAllDevicesOnBus(pPciRoot, uBridgeBus);
1586
1587	/*
1588	* Set I/O limit register. If there is no device with I/O space behind the
1589	* bridge we set a lower value than in the base register.
1590	*/
1591	if (u32IoAddressBase != pPciRoot->uPciBiosIo)
1592	{
1593	/* Need again alignment to a 4KB boundary. */
1594	pPciRoot->uPciBiosIo = RT_ALIGN_32(pPciRoot->uPciBiosIo, 4*1024);
1595	ich9pciBiosInitWriteConfig(pPciRoot, uBus, uDevFn, VBOX_PCI_IO_LIMIT, ((pPciRoot->uPciBiosIo >> 8) & 0xf0) - 1, 1);
1596	}
1597	else
1598	{
1599	ich9pciBiosInitWriteConfig(pPciRoot, uBus, uDevFn, VBOX_PCI_IO_BASE, 0xf0, 1);
1600	ich9pciBiosInitWriteConfig(pPciRoot, uBus, uDevFn, VBOX_PCI_IO_LIMIT, 0x00, 1);
1601	}
1602
1603	/* Same with the MMIO limit register but with 1MB boundary here. */
1604	if (u32MMIOAddressBase != pPciRoot->uPciBiosMmio)
1605	{
1606	pPciRoot->uPciBiosMmio = RT_ALIGN_32(pPciRoot->uPciBiosMmio, 1024*1024);
1607	ich9pciBiosInitWriteConfig(pPciRoot, uBus, uDevFn, VBOX_PCI_MEMORY_LIMIT, ((pPciRoot->uPciBiosMmio >> 16) & UINT32_C(0xfff0)) - 1, 2);
1608	}
1609	else
1610	{
1611	ich9pciBiosInitWriteConfig(pPciRoot, uBus, uDevFn, VBOX_PCI_MEMORY_BASE, 0xfff0, 2);
1612	ich9pciBiosInitWriteConfig(pPciRoot, uBus, uDevFn, VBOX_PCI_MEMORY_LIMIT, 0x0000, 2);
1613	}
1614
1615	/*
1616	* Set the prefetch base and limit registers. We currently have no device with a prefetchable region
1617	* which may be behind a bridge. That's why it is unconditionally disabled here atm by writing a higher value into
1618	* the base register than in the limit register.
1619	*/
1620	ich9pciBiosInitWriteConfig(pPciRoot, uBus, uDevFn, VBOX_PCI_PREF_MEMORY_BASE, 0xfff0, 2);
1621	ich9pciBiosInitWriteConfig(pPciRoot, uBus, uDevFn, VBOX_PCI_PREF_MEMORY_LIMIT, 0x0, 2);
1622	ich9pciBiosInitWriteConfig(pPciRoot, uBus, uDevFn, VBOX_PCI_PREF_BASE_UPPER32, 0x00, 4);
1623	ich9pciBiosInitWriteConfig(pPciRoot, uBus, uDevFn, VBOX_PCI_PREF_LIMIT_UPPER32, 0x00, 4);
1624	}
1625
1626	static void ich9pciBiosInitDeviceBARs(PDEVPCIROOT pPciRoot, uint8_t uBus, uint8_t uDevFn)
1627	{
1628	uint8_t uHeaderType = ich9pciBiosInitReadConfig(pPciRoot, uBus, uDevFn, VBOX_PCI_HEADER_TYPE, 1) & 0x7f;
1629	int cRegions = 0;
1630	if (uHeaderType == 0x00)
1631	/* Ignore ROM region here, which is included in VBOX_PCI_NUM_REGIONS. */
1632	cRegions = VBOX_PCI_NUM_REGIONS - 1;
1633	else if (uHeaderType == 0x01)
1634	/* PCI bridges have 2 BARs. */
1635	cRegions = 2;
1636
1637	bool fSuppressMem = false;
1638	bool fActiveMemRegion = false;
1639	bool fActiveIORegion = false;
1640	for (int iRegion = 0; iRegion < cRegions; iRegion++)
1641	{
1642	uint32_t u32Address = ich9pciGetRegionReg(iRegion);
1643
1644	/* Calculate size - we write all 1s into the BAR, and then evaluate which bits
1645	are cleared. */
1646	uint8_t u8ResourceType = ich9pciBiosInitReadConfig(pPciRoot, uBus, uDevFn, u32Address, 1);
1647
1648	bool fPrefetch = (u8ResourceType & ((uint8_t)(PCI_ADDRESS_SPACE_MEM_PREFETCH \| PCI_ADDRESS_SPACE_IO)))
1649	== PCI_ADDRESS_SPACE_MEM_PREFETCH;
1650	bool f64Bit = (u8ResourceType & ((uint8_t)(PCI_ADDRESS_SPACE_BAR64 \| PCI_ADDRESS_SPACE_IO)))
1651	== PCI_ADDRESS_SPACE_BAR64;
1652	bool fIsPio = ((u8ResourceType & PCI_ADDRESS_SPACE_IO) == PCI_ADDRESS_SPACE_IO);
1653	uint64_t cbRegSize64 = 0;
1654
1655	/* Hack: since this PCI init code cannot handle prefetchable BARs on
1656	* anything besides the primary bus, it's for now the best solution
1657	* to leave such BARs uninitialized and keep memory transactions
1658	* disabled. The OS will hopefully be clever enough to fix this.
1659	* Prefetchable BARs are the only ones which can be truly big (and
1660	* are almost always 64-bit BARs). The non-prefetchable ones will not
1661	* cause running out of space in the PCI memory hole. */
1662	if (fPrefetch && uBus != 0)
1663	{
1664	fSuppressMem = true;
1665	if (f64Bit)
1666	iRegion++; /* skip next region */
1667	continue;
1668	}
1669
1670	if (f64Bit)
1671	{
1672	ich9pciBiosInitWriteConfig(pPciRoot, uBus, uDevFn, u32Address, UINT32_C(0xffffffff), 4);
1673	ich9pciBiosInitWriteConfig(pPciRoot, uBus, uDevFn, u32Address+4, UINT32_C(0xffffffff), 4);
1674	cbRegSize64 = ich9pciBiosInitReadConfig(pPciRoot, uBus, uDevFn, u32Address, 4);
1675	cbRegSize64 \|= ((uint64_t)ich9pciBiosInitReadConfig(pPciRoot, uBus, uDevFn, u32Address+4, 4) << 32);
1676	cbRegSize64 &= ~UINT64_C(0x0f);
1677	cbRegSize64 = (~cbRegSize64) + 1;
1678
1679	/* No 64-bit PIO regions possible. */
1680	#ifndef DEBUG_bird /* EFI triggers this for DevAHCI. */
1681	AssertMsg((u8ResourceType & PCI_ADDRESS_SPACE_IO) == 0, ("type=%#x rgn=%d\n", u8ResourceType, iRegion));
1682	#endif
1683	}
1684	else
1685	{
1686	uint32_t cbRegSize32;
1687	ich9pciBiosInitWriteConfig(pPciRoot, uBus, uDevFn, u32Address, UINT32_C(0xffffffff), 4);
1688	cbRegSize32 = ich9pciBiosInitReadConfig(pPciRoot, uBus, uDevFn, u32Address, 4);
1689
1690	/* Clear resource information depending on resource type. */
1691	if (fIsPio) /* PIO */
1692	cbRegSize32 &= ~UINT32_C(0x01);
1693	else /* MMIO */
1694	cbRegSize32 &= ~UINT32_C(0x0f);
1695
1696	/*
1697	* Invert all bits and add 1 to get size of the region.
1698	* (From PCI implementation note)
1699	*/
1700	if (fIsPio && (cbRegSize32 & UINT32_C(0xffff0000)) == 0)
1701	cbRegSize32 = (~(cbRegSize32 \| UINT32_C(0xffff0000))) + 1;
1702	else
1703	cbRegSize32 = (~cbRegSize32) + 1;
1704
1705	cbRegSize64 = cbRegSize32;
1706	}
1707	Log2(("%s: Size of region %u for device %d on bus %d is %lld\n", __FUNCTION__, iRegion, uDevFn, uBus, cbRegSize64));
1708
1709	if (cbRegSize64)
1710	{
1711	/* Try 32-bit base first. */
1712	uint32_t* paddr = fIsPio ? &pPciRoot->uPciBiosIo : &pPciRoot->uPciBiosMmio;
1713	uint64_t uNew = *paddr;
1714	/* Align starting address to region size. */
1715	uNew = (uNew + cbRegSize64 - 1) & ~(cbRegSize64 - 1);
1716	if (fIsPio)
1717	uNew &= UINT32_C(0xffff);
1718	/* Unconditionally exclude I/O-APIC/HPET/ROM. Pessimistic, but better than causing a mess. */
1719	if ( !uNew
1720	\|\| (uNew <= UINT32_C(0xffffffff) && uNew + cbRegSize64 - 1 >= UINT32_C(0xfec00000))
1721	\|\| uNew >= _4G)
1722	{
1723	/* Only prefetchable regions can be placed above 4GB, as the
1724	* address decoder for non-prefetchable addresses in bridges
1725	* is limited to 32 bits. */
1726	if (f64Bit && fPrefetch)
1727	{
1728	/* Map a 64-bit region above 4GB. */
1729	Assert(!fIsPio);
1730	uNew = pPciRoot->uPciBiosMmio64;
1731	/* Align starting address to region size. */
1732	uNew = (uNew + cbRegSize64 - 1) & ~(cbRegSize64 - 1);
1733	LogFunc(("Start address of 64-bit MMIO region %u/%u is %#llx\n", iRegion, iRegion + 1, uNew));
1734	ich9pciBiosInitSetRegionAddress(pPciRoot, uBus, uDevFn, iRegion, uNew);
1735	fActiveMemRegion = true;
1736	pPciRoot->uPciBiosMmio64 = uNew + cbRegSize64;
1737	Log2Func(("New 64-bit address is %#llx\n", pPciRoot->uPciBiosMmio64));
1738	}
1739	else
1740	{
1741	uint16_t uVendor = ich9pciBiosInitReadConfig(pPciRoot, uBus, uDevFn, VBOX_PCI_VENDOR_ID, 2);
1742	uint16_t uDevice = ich9pciBiosInitReadConfig(pPciRoot, uBus, uDevFn, VBOX_PCI_DEVICE_ID, 2);
1743	LogRel(("PCI: no space left for BAR%u of device %u/%u/%u (vendor=%#06x device=%#06x)\n",
1744	iRegion, uBus, uDevFn >> 3, uDevFn & 7, uVendor, uDevice)); /** @todo make this a VM start failure later. */
1745	/* Undo the mapping mess caused by the size probing. */
1746	ich9pciBiosInitWriteConfig(pPciRoot, uBus, uDevFn, u32Address, UINT32_C(0), 4);
1747	}
1748	}
1749	else
1750	{
1751	LogFunc(("Start address of %s region %u is %#x\n", (fIsPio ? "I/O" : "MMIO"), iRegion, uNew));
1752	ich9pciBiosInitSetRegionAddress(pPciRoot, uBus, uDevFn, iRegion, uNew);
1753	if (fIsPio)
1754	fActiveIORegion = true;
1755	else
1756	fActiveMemRegion = true;
1757	*paddr = uNew + cbRegSize64;
1758	Log2Func(("New 32-bit address is %#x\n", *paddr));
1759	}
1760
1761	if (f64Bit)
1762	iRegion++; /* skip next region */
1763	}
1764	}
1765
1766	/* Update the command word appropriately. */
1767	uint8_t uCmd = ich9pciBiosInitReadConfig(pPciRoot, uBus, uDevFn, VBOX_PCI_COMMAND, 2);
1768	if (fActiveMemRegion && !fSuppressMem)
1769	uCmd \|= VBOX_PCI_COMMAND_MEMORY; /* Enable MMIO access. */
1770	if (fActiveIORegion)
1771	uCmd \|= VBOX_PCI_COMMAND_IO; /* Enable I/O space access. */
1772	ich9pciBiosInitWriteConfig(pPciRoot, uBus, uDevFn, VBOX_PCI_COMMAND, uCmd, 2);
1773	}
1774
1775	static void ich9pciBiosInitAllDevicesOnBus(PDEVPCIROOT pPciRoot, uint8_t uBus)
1776	{
1777	/* First pass: assign resources to all devices and map the interrupt. */
1778	for (uint32_t uDevFn = 0; uDevFn < 256; uDevFn++)
1779	{
1780	/* check if device is present */
1781	uint16_t uVendor = ich9pciBiosInitReadConfig(pPciRoot, uBus, uDevFn, VBOX_PCI_VENDOR_ID, 2);
1782	if (uVendor == 0xffff)
1783	continue;
1784
1785	Log(("BIOS init device: %02x:%02x.%d\n", uBus, uDevFn >> 3, uDevFn & 7));
1786
1787	/* default memory mappings */
1788	ich9pciBiosInitDeviceBARs(pPciRoot, uBus, uDevFn);
1789	uint16_t uDevClass = ich9pciBiosInitReadConfig(pPciRoot, uBus, uDevFn, VBOX_PCI_CLASS_DEVICE, 2);
1790	switch (uDevClass)
1791	{
1792	case 0x0101:
1793	/* IDE controller */
1794	ich9pciBiosInitWriteConfig(pPciRoot, uBus, uDevFn, 0x40, 0x8000, 2); /* enable IDE0 */
1795	ich9pciBiosInitWriteConfig(pPciRoot, uBus, uDevFn, 0x42, 0x8000, 2); /* enable IDE1 */
1796	break;
1797	case 0x0300:
1798	{
1799	/* VGA controller */
1800
1801	/* NB: Default Bochs VGA LFB address is 0xE0000000. Old guest
1802	* software may break if the framebuffer isn't mapped there.
1803	*/
1804
1805	/*
1806	* Legacy VGA I/O ports are implicitly decoded by a VGA class device. But
1807	* only the framebuffer (i.e., a memory region) is explicitly registered via
1808	* ich9pciSetRegionAddress, so don't forget to enable I/O decoding.
1809	*/
1810	uint8_t uCmd = ich9pciBiosInitReadConfig(pPciRoot, uBus, uDevFn, VBOX_PCI_COMMAND, 1);
1811	ich9pciBiosInitWriteConfig(pPciRoot, uBus, uDevFn, VBOX_PCI_COMMAND,
1812	uCmd \| VBOX_PCI_COMMAND_IO,
1813	1);
1814	break;
1815	}
1816	default:
1817	break;
1818	}
1819
1820	/* map the interrupt */
1821	uint32_t iPin = ich9pciBiosInitReadConfig(pPciRoot, uBus, uDevFn, VBOX_PCI_INTERRUPT_PIN, 1);
1822	if (iPin != 0)
1823	{
1824	iPin--;
1825
1826	if (uBus != 0)
1827	{
1828	/* Find bus this device attached to. */
1829	PDEVPCIBUS pBus = &pPciRoot->PciBus;
1830	while (1)
1831	{
1832	PPDMPCIDEV pBridge = ich9pciFindBridge(pBus, uBus);
1833	if (!pBridge)
1834	{
1835	Assert(false);
1836	break;
1837	}
1838	/* safe, only needs to go to the config space array */
1839	if (uBus == PDMPciDevGetByte(pBridge, VBOX_PCI_SECONDARY_BUS))
1840	{
1841	/* OK, found bus this device attached to. */
1842	break;
1843	}
1844	pBus = PDMINS_2_DATA(pBridge->Int.s.CTX_SUFF(pDevIns), PDEVPCIBUS);
1845	}
1846
1847	/* We need to go up to the host bus to see which irq pin this
1848	* device will use there. See logic in ich9pcibridgeSetIrq().
1849	*/
1850	while (pBus->iBus != 0)
1851	{
1852	/* Get the pin the device would assert on the bridge. */
1853	iPin = ((pBus->PciDev.uDevFn >> 3) + iPin) & 3;
1854	pBus = pBus->PciDev.Int.s.pBusR3;
1855	};
1856	}
1857
1858	int iIrq = aPciIrqs[ich9pciSlotGetPirq(uBus, uDevFn, iPin)];
1859	Log(("Using pin %d and IRQ %d for device %02x:%02x.%d\n",
1860	iPin, iIrq, uBus, uDevFn>>3, uDevFn&7));
1861	ich9pciBiosInitWriteConfig(pPciRoot, uBus, uDevFn, VBOX_PCI_INTERRUPT_LINE, iIrq, 1);
1862	}
1863	}
1864
1865	/* Second pass: handle bridges recursively. */
1866	for (uint32_t uDevFn = 0; uDevFn < 256; uDevFn++)
1867	{
1868	/* check if device is present */
1869	uint16_t uVendor = ich9pciBiosInitReadConfig(pPciRoot, uBus, uDevFn, VBOX_PCI_VENDOR_ID, 2);
1870	if (uVendor == 0xffff)
1871	continue;
1872
1873	/* only handle PCI-to-PCI bridges */
1874	uint16_t uDevClass = ich9pciBiosInitReadConfig(pPciRoot, uBus, uDevFn, VBOX_PCI_CLASS_DEVICE, 2);
1875	if (uDevClass != 0x0604)
1876	continue;
1877
1878	Log(("BIOS init bridge: %02x:%02x.%d\n", uBus, uDevFn >> 3, uDevFn & 7));
1879	ich9pciBiosInitBridge(pPciRoot, uBus, uDevFn);
1880	}
1881	}
1882
1883	/**
1884	* Initializes bridges registers used for routing.
1885	*
1886	* We ASSUME PDM bus assignments are the same as the PCI bus assignments and
1887	* will complain if we find any conflicts. This because it is just soo much
1888	* simpler to have the two numbers match one another by default.
1889	*
1890	* @returns Max subordinate bus number.
1891	* @param pPciRoot Global device instance data used to generate unique bus numbers.
1892	* @param pBus The PCI bus to initialize.
1893	* @param pbmUsed Pointer to a 32-bit bitmap tracking which device
1894	* (ranges) has been used.
1895	* @param uBusPrimary The primary bus number the bus is connected to.
1896	*/
1897	static uint8_t ich9pciBiosInitBridgeTopology(PDEVPCIROOT pPciRoot, PDEVPCIBUS pBus, uint32_t *pbmUsed, uint8_t uBusPrimary)
1898	{
1899	PPDMPCIDEV pBridgeDev = &pBus->PciDev;
1900
1901	/* Check if the PDM bus assignment makes sense. */
1902	AssertLogRelMsg(!(*pbmUsed & RT_BIT_32(pBus->iBus)),
1903	("PCIBIOS: Bad PCI bridge config! Conflict for bus %#x. Make sure to instantiate bridges for a sub-trees in sequence!\n",
1904	pBus->iBus));
1905	*pbmUsed \|= RT_BIT_32(pBus->iBus);
1906
1907	/* Set only if we are not on the root bus, it has no primary bus attached. */
1908	if (pBus->iBus != 0)
1909	{
1910	ich9pciSetByte(pBridgeDev, VBOX_PCI_PRIMARY_BUS, uBusPrimary);
1911	ich9pciSetByte(pBridgeDev, VBOX_PCI_SECONDARY_BUS, pBus->iBus);
1912	/* Since the subordinate bus value can only be finalized once we
1913	* finished recursing through everything behind the bridge, the only
1914	* solution is temporarily configuring the subordinate to the maximum
1915	* possible value. This makes sure that the config space accesses work
1916	* (for our own sloppy emulation it apparently doesn't matter, but
1917	* this is vital for real PCI bridges/devices in passthrough mode). */
1918	ich9pciSetByte(pBridgeDev, VBOX_PCI_SUBORDINATE_BUS, 0xff);
1919	}
1920
1921	uint8_t uMaxSubNum = pBus->iBus;
1922	for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
1923	{
1924	PPDMPCIDEV pBridge = pBus->papBridgesR3[iBridge];
1925	AssertMsg(pBridge && pciDevIsPci2PciBridge(pBridge),
1926	("Device is not a PCI bridge but on the list of PCI bridges\n"));
1927	PDEVPCIBUS pChildBus = PDMINS_2_DATA(pBridge->Int.s.CTX_SUFF(pDevIns), PDEVPCIBUS);
1928	uint8_t uMaxChildSubBus = ich9pciBiosInitBridgeTopology(pPciRoot, pChildBus, pbmUsed, pBus->iBus);
1929	uMaxSubNum = RT_MAX(uMaxSubNum, uMaxChildSubBus);
1930	}
1931
1932	if (pBus->iBus != 0)
1933	ich9pciSetByte(pBridgeDev, VBOX_PCI_SUBORDINATE_BUS, uMaxSubNum);
1934	for (uint32_t i = pBus->iBus; i <= uMaxSubNum; i++)
1935	*pbmUsed \|= RT_BIT_32(i);
1936
1937	/* Make sure that transactions are able to get through the bridge. Not
1938	* strictly speaking necessary this early (before any device is set up),
1939	* but on the other hand it can't hurt either. */
1940	if (pBus->iBus != 0)
1941	ich9pciSetWord(pBridgeDev, VBOX_PCI_COMMAND,
1942	VBOX_PCI_COMMAND_IO
1943	\| VBOX_PCI_COMMAND_MEMORY
1944	\| VBOX_PCI_COMMAND_MASTER);
1945
1946	/* safe, only needs to go to the config space array */
1947	Log2(("ich9pciBiosInitBridgeTopology: for bus %p: primary=%d secondary=%d subordinate=%d\n",
1948	pBus,
1949	PDMPciDevGetByte(pBridgeDev, VBOX_PCI_PRIMARY_BUS),
1950	PDMPciDevGetByte(pBridgeDev, VBOX_PCI_SECONDARY_BUS),
1951	PDMPciDevGetByte(pBridgeDev, VBOX_PCI_SUBORDINATE_BUS)
1952	));
1953
1954	return uMaxSubNum;
1955	}
1956
1957
1958	/**
1959	* @interface_method_impl{PDMPCIBUSREG,pfnFakePCIBIOSR3}
1960	*/
1961	static DECLCALLBACK(int) ich9pciFakePCIBIOS(PPDMDEVINS pDevIns)
1962	{
1963	PDEVPCIROOT pPciRoot = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
1964	PVM pVM = PDMDevHlpGetVM(pDevIns);
1965	uint32_t const cbBelow4GB = MMR3PhysGetRamSizeBelow4GB(pVM);
1966	uint64_t const cbAbove4GB = MMR3PhysGetRamSizeAbove4GB(pVM);
1967
1968	/*
1969	* Set the start addresses.
1970	*/
1971	pPciRoot->uPciBiosBus = 0;
1972	pPciRoot->uPciBiosIo = 0xd000;
1973	pPciRoot->uPciBiosMmio = cbBelow4GB;
1974	pPciRoot->uPciBiosMmio64 = cbAbove4GB + _4G;
1975
1976	/* NB: Assume that if PCI controller MMIO range is enabled, it is below the beginning of the memory hole. */
1977	if (pPciRoot->u64PciConfigMMioAddress)
1978	{
1979	AssertRelease(pPciRoot->u64PciConfigMMioAddress >= cbBelow4GB);
1980	pPciRoot->uPciBiosMmio = pPciRoot->u64PciConfigMMioAddress + pPciRoot->u64PciConfigMMioLength;
1981	}
1982	Log(("cbBelow4GB: %#RX32, uPciBiosMmio: %#RX64, cbAbove4GB: %#RX64, uPciBiosMmio64=%#RX64\n",
1983	cbBelow4GB, pPciRoot->uPciBiosMmio, cbAbove4GB, pPciRoot->uPciBiosMmio64));
1984
1985	/*
1986	* Assign bridge topology, for further routing to work.
1987	*/
1988	PDEVPCIBUS pBus = &pPciRoot->PciBus;
1989	AssertLogRel(pBus->iBus == 0);
1990	uint32_t bmUsed = 0;
1991	ich9pciBiosInitBridgeTopology(pPciRoot, pBus, &bmUsed, 0);
1992
1993	/*
1994	* Init all devices on bus 0 (recursing to further buses).
1995	*/
1996	ich9pciBiosInitAllDevicesOnBus(pPciRoot, 0);
1997
1998	return VINF_SUCCESS;
1999	}
2000
2001
2002	/* -=-=-=-=-=- PCI Config Space -=-=-=-=-=- */
2003
2004
2005	/**
2006	* @callback_method_impl{PFNPCICONFIGREAD, Default config space read callback.}
2007	*/
2008	DECLCALLBACK(uint32_t) devpciR3CommonDefaultConfigRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress, unsigned cb)
2009	{
2010	NOREF(pDevIns);
2011
2012	uint32_t uValue;
2013	if (uAddress + cb <= 256)
2014	{
2015	switch (cb)
2016	{
2017	case 1:
2018	/* safe, only needs to go to the config space array */
2019	uValue = PDMPciDevGetByte(pPciDev, uAddress);
2020	break;
2021	case 2:
2022	/* safe, only needs to go to the config space array */
2023	uValue = PDMPciDevGetWord(pPciDev, uAddress);
2024	break;
2025	case 4:
2026	/* safe, only needs to go to the config space array */
2027	uValue = PDMPciDevGetDWord(pPciDev, uAddress);
2028	break;
2029	default:
2030	AssertFailed();
2031	uValue = 0;
2032	break;
2033	}
2034
2035	#ifdef LOG_ENABLED
2036	if ( pciDevIsMsiCapable(pPciDev)
2037	&& uAddress - (uint32_t)pPciDev->Int.s.u8MsiCapOffset < (uint32_t)pPciDev->Int.s.u8MsiCapSize )
2038	Log2(("devpciR3CommonDefaultConfigRead: MSI CAP: %#x LB %u -> %#x\n", uAddress - (uint32_t)pPciDev->Int.s.u8MsiCapOffset, cb, uValue));
2039	else if ( pciDevIsMsixCapable(pPciDev)
2040	&& uAddress - (uint32_t)pPciDev->Int.s.u8MsixCapOffset < (uint32_t)pPciDev->Int.s.u8MsixCapSize)
2041	Log2(("devpciR3CommonDefaultConfigRead: MSI-X CAP: %#x LB %u -> %#x\n", uAddress - (uint32_t)pPciDev->Int.s.u8MsiCapOffset, cb, uValue));
2042	#endif
2043	}
2044	else
2045	{
2046	if (uAddress + cb < 4096)
2047	LogRel(("PCI: %8s/%u: Read from extended register %d fallen back to generic code\n",
2048	pPciDev->pszNameR3, pPciDev->Int.s.CTX_SUFF(pDevIns)->iInstance, uAddress));
2049	else
2050	AssertFailed();
2051	uValue = 0;
2052	}
2053	return uValue;
2054	}
2055
2056
2057	/**
2058	* Worker for ich9pciResetDevice and devpciR3UpdateMappings that unmaps a region.
2059	*
2060	* @returns VBox status code.
2061	* @param pDev The PCI device.
2062	* @param iRegion The region to unmap.
2063	*/
2064	static int ich9pciUnmapRegion(PPDMPCIDEV pDev, int iRegion)
2065	{
2066	PCIIORegion *pRegion = &pDev->Int.s.aIORegions[iRegion];
2067	AssertReturn(pRegion->size != 0, VINF_SUCCESS);
2068
2069	int rc;
2070	if (pRegion->addr == INVALID_PCI_ADDRESS)
2071	rc = VINF_SUCCESS;
2072	else
2073	{
2074	if (pRegion->type & PCI_ADDRESS_SPACE_IO)
2075	{
2076	/* Port IO */
2077	rc = PDMDevHlpIOPortDeregister(pDev->Int.s.pDevInsR3, pRegion->addr, pRegion->size);
2078	AssertRC(rc);
2079	}
2080	else
2081	{
2082	PDEVPCIBUS pBus = pDev->Int.s.CTX_SUFF(pBus);
2083	RTGCPHYS GCPhysBase = pRegion->addr;
2084	if (pBus->pPciHlpR3->pfnIsMMIOExBase(pBus->pDevInsR3, pDev->Int.s.pDevInsR3, GCPhysBase))
2085	{
2086	/* unmap it. */
2087	rc = pRegion->map_func(pDev->Int.s.pDevInsR3, pDev, iRegion,
2088	NIL_RTGCPHYS, pRegion->size, (PCIADDRESSSPACE)(pRegion->type));
2089	AssertRC(rc);
2090	rc = PDMDevHlpMMIOExUnmap(pDev->Int.s.pDevInsR3, pDev, iRegion, GCPhysBase);
2091	}
2092	else
2093	rc = PDMDevHlpMMIODeregister(pDev->Int.s.pDevInsR3, GCPhysBase, pRegion->size);
2094	AssertRC(rc);
2095	}
2096	pRegion->addr = INVALID_PCI_ADDRESS;
2097	}
2098	return rc;
2099	}
2100
2101
2102	/**
2103	* Worker for devpciR3IsConfigByteWritable that update BAR and ROM mappings.
2104	*
2105	* @param pPciDev The PCI device to update the mappings for.
2106	* @param fP2PBridge Whether this is a PCI to PCI bridge or not.
2107	*/
2108	static void devpciR3UpdateMappings(PPDMPCIDEV pPciDev, bool fP2PBridge)
2109	{
2110	uint16_t const u16Cmd = ich9pciGetWord(pPciDev, VBOX_PCI_COMMAND);
2111	for (unsigned iRegion = 0; iRegion < VBOX_PCI_NUM_REGIONS; iRegion++)
2112	{
2113	/* Skip over BAR2..BAR5 for bridges, as they have a different meaning there. */
2114	if (fP2PBridge && iRegion >= 2 && iRegion <= 5)
2115	continue;
2116	PCIIORegion *pRegion = &pPciDev->Int.s.aIORegions[iRegion];
2117	uint64_t const cbRegion = pRegion->size;
2118	if (cbRegion != 0)
2119	{
2120	uint32_t const offCfgReg = ich9pciGetRegionReg(iRegion);
2121	bool const f64Bit = (pRegion->type & ((uint8_t)(PCI_ADDRESS_SPACE_BAR64 \| PCI_ADDRESS_SPACE_IO)))
2122	== PCI_ADDRESS_SPACE_BAR64;
2123	uint64_t uNew = INVALID_PCI_ADDRESS;
2124
2125	/*
2126	* Port I/O region. Check if mapped and within 1..65535 range.
2127	*/
2128	if (pRegion->type & PCI_ADDRESS_SPACE_IO)
2129	{
2130	if (u16Cmd & VBOX_PCI_COMMAND_IO)
2131	{
2132	uint32_t uIoBase = ich9pciGetDWord(pPciDev, offCfgReg);
2133	uIoBase &= ~(uint32_t)(cbRegion - 1);
2134
2135	uint64_t uLast = cbRegion - 1 + uIoBase;
2136	if ( uLast < _64K
2137	&& uIoBase < uLast
2138	&& uIoBase > 0)
2139	uNew = uIoBase;
2140	}
2141	}
2142	/*
2143	* MMIO or ROM. Check ROM enable bit and range.
2144	*
2145	* Note! We exclude the I/O-APIC/HPET/ROM area at the end of the first 4GB to
2146	* prevent the (fake) PCI BIOS and others from making a mess. Pure paranoia.
2147	* Additionally addresses with the top 32 bits all set are excluded, to
2148	* catch silly OSes which probe 64-bit BARs without disabling the
2149	* corresponding transactions.
2150	*/
2151	else if (u16Cmd & VBOX_PCI_COMMAND_MEMORY)
2152	{
2153	uint64_t uMemBase = ich9pciGetDWord(pPciDev, offCfgReg);
2154	if (f64Bit)
2155	{
2156	Assert(iRegion < VBOX_PCI_ROM_SLOT);
2157	uMemBase \|= (uint64_t)ich9pciGetDWord(pPciDev, offCfgReg + 4) << 32;
2158	}
2159	if ( iRegion != PCI_ROM_SLOT
2160	\|\| (uMemBase & RT_BIT_32(0))) /* ROM enable bit. */
2161	{
2162	uMemBase &= ~(cbRegion - 1);
2163
2164	uint64_t uLast = uMemBase + cbRegion - 1;
2165	if ( uMemBase < uLast
2166	&& uMemBase > 0
2167	&& !( uMemBase <= UINT32_C(0xffffffff)
2168	&& uLast >= UINT32_C(0xfec00000))
2169	&& uMemBase < UINT64_C(0xffffffff00000000) )
2170	uNew = uMemBase;
2171	}
2172	}
2173
2174	/*
2175	* Do real unmapping and/or mapping if the address change.
2176	*/
2177	if (uNew != pRegion->addr)
2178	{
2179	LogRel2(("PCI: config dev %u/%u (%s) BAR%i: %#RX64 -> %#RX64 (LB %RX64 (%RU64))\n",
2180	pPciDev->uDevFn >> VBOX_PCI_DEVFN_DEV_SHIFT, pPciDev->uDevFn & VBOX_PCI_DEVFN_FUN_MASK,
2181	pPciDev->pszNameR3, iRegion, pRegion->addr, uNew, cbRegion, cbRegion));
2182
2183	ich9pciUnmapRegion(pPciDev, iRegion);
2184	pRegion->addr = uNew;
2185	if (uNew != INVALID_PCI_ADDRESS)
2186	{
2187	int rc = pRegion->map_func(pPciDev->Int.s.pDevInsR3, pPciDev, iRegion, uNew, cbRegion,
2188	(PCIADDRESSSPACE)(pRegion->type));
2189	AssertRC(rc);
2190	}
2191	}
2192
2193	if (f64Bit)
2194	iRegion++;
2195	}
2196	/* else: size == 0: unused region */
2197	}
2198	}
2199
2200
2201	/**
2202	* Worker for devpciR3CommonDefaultConfigWrite that write a byte to a BAR.
2203	*
2204	* @param pPciDev The PCI device.
2205	* @param iRegion The region.
2206	* @param off The BAR offset.
2207	* @param bVal The byte to write.
2208	*/
2209	DECLINLINE(void) devpciR3WriteBarByte(PPDMPCIDEV pPciDev, uint32_t iRegion, uint32_t off, uint8_t bVal)
2210	{
2211	PCIIORegion *pRegion = &pPciDev->Int.s.aIORegions[iRegion];
2212	Log3(("devpciR3WriteBarByte: region=%d off=%d val=%#x size=%#llx\n", iRegion, off, bVal, pRegion->size));
2213	Assert(off <= 3);
2214
2215	/* Check if we're writing to upper part of 64-bit BAR. */
2216	if (pRegion->type == 0xff)
2217	{
2218	AssertLogRelReturnVoid(iRegion > 0 && iRegion < VBOX_PCI_ROM_SLOT);
2219	pRegion--;
2220	iRegion--;
2221	off += 4;
2222	Assert(pRegion->type & PCI_ADDRESS_SPACE_BAR64);
2223	}
2224
2225	/* Ignore zero sized regions (they don't exist). */
2226	if (pRegion->size != 0)
2227	{
2228	uint32_t uAddr = ich9pciGetRegionReg(iRegion) + off;
2229	Assert((pRegion->size & (pRegion->size - 1)) == 0); /* Region size must be power of two. */
2230	uint8_t bMask = ( (pRegion->size - 1) >> (off * 8) ) & 0xff;
2231	if (off == 0)
2232	bMask \|= (pRegion->type & PCI_ADDRESS_SPACE_IO)
2233	? (1 << 2) - 1 /* 2 lowest bits for IO region */ :
2234	(1 << 4) - 1 /* 4 lowest bits for memory region, also ROM enable bit for ROM region */;
2235
2236	/* safe, only needs to go to the config space array */
2237	uint8_t bOld = PDMPciDevGetByte(pPciDev, uAddr) & bMask;
2238	bVal = (bOld & bMask) \| (bVal & ~bMask);
2239
2240	Log3(("devpciR3WriteBarByte: %x changed to %x\n", bOld, bVal));
2241
2242	/* safe, only needs to go to the config space array */
2243	PDMPciDevSetByte(pPciDev, uAddr, bVal);
2244	}
2245	}
2246
2247
2248	/**
2249	* Checks if the given configuration byte is writable.
2250	*
2251	* @returns true if writable, false if not
2252	* @param uAddress The config space byte byte.
2253	* @param bHeaderType The device header byte.
2254	*/
2255	DECLINLINE(bool) devpciR3IsConfigByteWritable(uint32_t uAddress, uint8_t bHeaderType)
2256	{
2257	switch (bHeaderType)
2258	{
2259	case 0x00: /* normal device */
2260	case 0x80: /* multi-function device */
2261	switch (uAddress)
2262	{
2263	/* Read-only registers. */
2264	case VBOX_PCI_VENDOR_ID:
2265	case VBOX_PCI_VENDOR_ID+1:
2266	case VBOX_PCI_DEVICE_ID:
2267	case VBOX_PCI_DEVICE_ID+1:
2268	case VBOX_PCI_REVISION_ID:
2269	case VBOX_PCI_CLASS_PROG:
2270	case VBOX_PCI_CLASS_SUB:
2271	case VBOX_PCI_CLASS_BASE:
2272	case VBOX_PCI_HEADER_TYPE:
2273	case VBOX_PCI_SUBSYSTEM_VENDOR_ID:
2274	case VBOX_PCI_SUBSYSTEM_VENDOR_ID+1:
2275	case VBOX_PCI_SUBSYSTEM_ID:
2276	case VBOX_PCI_SUBSYSTEM_ID+1:
2277	case VBOX_PCI_ROM_ADDRESS:
2278	case VBOX_PCI_ROM_ADDRESS+1:
2279	case VBOX_PCI_ROM_ADDRESS+2:
2280	case VBOX_PCI_ROM_ADDRESS+3:
2281	case VBOX_PCI_CAPABILITY_LIST:
2282	case VBOX_PCI_INTERRUPT_PIN:
2283	return false;
2284	/* Other registers can be written. */
2285	default:
2286	return true;
2287	}
2288	break;
2289	case 0x01: /* PCI-PCI bridge */
2290	switch (uAddress)
2291	{
2292	/* Read-only registers. */
2293	case VBOX_PCI_VENDOR_ID:
2294	case VBOX_PCI_VENDOR_ID+1:
2295	case VBOX_PCI_DEVICE_ID:
2296	case VBOX_PCI_DEVICE_ID+1:
2297	case VBOX_PCI_REVISION_ID:
2298	case VBOX_PCI_CLASS_PROG:
2299	case VBOX_PCI_CLASS_SUB:
2300	case VBOX_PCI_CLASS_BASE:
2301	case VBOX_PCI_HEADER_TYPE:
2302	case VBOX_PCI_ROM_ADDRESS_BR:
2303	case VBOX_PCI_ROM_ADDRESS_BR+1:
2304	case VBOX_PCI_ROM_ADDRESS_BR+2:
2305	case VBOX_PCI_ROM_ADDRESS_BR+3:
2306	case VBOX_PCI_INTERRUPT_PIN:
2307	return false;
2308	/* Other registers can be written. */
2309	default:
2310	return true;
2311	}
2312	break;
2313	default:
2314	AssertMsgFailed(("Unknown header type %#x\n", bHeaderType));
2315	return false;
2316	}
2317	}
2318
2319
2320	/**
2321	* @callback_method_impl{PFNPCICONFIGWRITE,
2322	* Default config space write callback.}
2323	*
2324	* See paragraph 7.5 of PCI Express specification (p. 349) for
2325	* definition of registers and their writability policy.
2326	*/
2327	DECLCALLBACK(void) devpciR3CommonDefaultConfigWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
2328	uint32_t uAddress, uint32_t u32Value, unsigned cb)
2329	{
2330	NOREF(pDevIns);
2331	Assert(cb <= 4);
2332
2333	if (uAddress + cb <= 256)
2334	{
2335	/*
2336	* MSI and MSI-X capabilites needs to be handled separately.
2337	*/
2338	if ( pciDevIsMsiCapable(pPciDev)
2339	&& uAddress - (uint32_t)pPciDev->Int.s.u8MsiCapOffset < (uint32_t)pPciDev->Int.s.u8MsiCapSize)
2340	MsiPciConfigWrite(pPciDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pDevIns),
2341	pPciDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pPciHlp),
2342	pPciDev, uAddress, u32Value, cb);
2343	else if ( pciDevIsMsixCapable(pPciDev)
2344	&& uAddress - (uint32_t)pPciDev->Int.s.u8MsixCapOffset < (uint32_t)pPciDev->Int.s.u8MsixCapSize)
2345	MsixPciConfigWrite(pPciDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pDevIns),
2346	pPciDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pPciHlp),
2347	pPciDev, uAddress, u32Value, cb);
2348	else
2349	{
2350	/*
2351	* Handle the writes byte-by-byte to catch all possible cases.
2352	*
2353	* Note! Real hardware may not necessarily handle non-dword writes like
2354	* we do here and even produce erratic behavior. We don't (yet)
2355	* try emulate that.
2356	*/
2357	uint8_t const bHeaderType = ich9pciGetByte(pPciDev, VBOX_PCI_HEADER_TYPE);
2358	bool const fP2PBridge = bHeaderType == 0x01; /* PCI-PCI bridge */
2359	bool fUpdateMappings = false;
2360	while (cb-- > 0)
2361	{
2362	bool fWritable = devpciR3IsConfigByteWritable(uAddress, bHeaderType);
2363	uint8_t bVal = (uint8_t)u32Value;
2364	bool fRom = false;
2365	switch (uAddress)
2366	{
2367	case VBOX_PCI_COMMAND: /* Command register, bits 0-7. */
2368	if (fWritable)
2369	{
2370	/* safe, only needs to go to the config space array */
2371	PDMPciDevSetByte(pPciDev, uAddress, bVal);
2372	fUpdateMappings = true;
2373	}
2374	break;
2375
2376	case VBOX_PCI_COMMAND+1: /* Command register, bits 8-15. */
2377	if (fWritable)
2378	{
2379	/* don't change reserved bits (11-15) */
2380	bVal &= ~UINT8_C(0xf8);
2381	/* safe, only needs to go to the config space array */
2382	PDMPciDevSetByte(pPciDev, uAddress, bVal);
2383	fUpdateMappings = true;
2384	}
2385	break;
2386
2387	case VBOX_PCI_STATUS: /* Status register, bits 0-7. */
2388	/* don't change read-only bits => actually all lower bits are read-only */
2389	bVal &= ~UINT8_C(0xff);
2390	/* status register, low part: clear bits by writing a '1' to the corresponding bit */
2391	pPciDev->abConfig[uAddress] &= ~bVal;
2392	break;
2393
2394	case VBOX_PCI_STATUS+1: /* Status register, bits 8-15. */
2395	/* don't change read-only bits */
2396	bVal &= ~UINT8_C(0x06);
2397	/* status register, high part: clear bits by writing a '1' to the corresponding bit */
2398	pPciDev->abConfig[uAddress] &= ~bVal;
2399	break;
2400
2401	case VBOX_PCI_ROM_ADDRESS: case VBOX_PCI_ROM_ADDRESS +1: case VBOX_PCI_ROM_ADDRESS +2: case VBOX_PCI_ROM_ADDRESS +3:
2402	fRom = true;
2403	case VBOX_PCI_BASE_ADDRESS_0: case VBOX_PCI_BASE_ADDRESS_0+1: case VBOX_PCI_BASE_ADDRESS_0+2: case VBOX_PCI_BASE_ADDRESS_0+3:
2404	case VBOX_PCI_BASE_ADDRESS_1: case VBOX_PCI_BASE_ADDRESS_1+1: case VBOX_PCI_BASE_ADDRESS_1+2: case VBOX_PCI_BASE_ADDRESS_1+3:
2405	case VBOX_PCI_BASE_ADDRESS_2: case VBOX_PCI_BASE_ADDRESS_2+1: case VBOX_PCI_BASE_ADDRESS_2+2: case VBOX_PCI_BASE_ADDRESS_2+3:
2406	case VBOX_PCI_BASE_ADDRESS_3: case VBOX_PCI_BASE_ADDRESS_3+1: case VBOX_PCI_BASE_ADDRESS_3+2: case VBOX_PCI_BASE_ADDRESS_3+3:
2407	case VBOX_PCI_BASE_ADDRESS_4: case VBOX_PCI_BASE_ADDRESS_4+1: case VBOX_PCI_BASE_ADDRESS_4+2: case VBOX_PCI_BASE_ADDRESS_4+3:
2408	case VBOX_PCI_BASE_ADDRESS_5: case VBOX_PCI_BASE_ADDRESS_5+1: case VBOX_PCI_BASE_ADDRESS_5+2: case VBOX_PCI_BASE_ADDRESS_5+3:
2409	/* We check that, as same PCI register numbers as BARs may mean different registers for bridges */
2410	if (!fP2PBridge)
2411	{
2412	uint32_t iRegion = fRom ? VBOX_PCI_ROM_SLOT : (uAddress - VBOX_PCI_BASE_ADDRESS_0) >> 2;
2413	devpciR3WriteBarByte(pPciDev, iRegion, uAddress & 0x3, bVal);
2414	fUpdateMappings = true;
2415	break;
2416	}
2417	else if (uAddress < VBOX_PCI_BASE_ADDRESS_2 \|\| uAddress > VBOX_PCI_BASE_ADDRESS_5+3)
2418	{
2419	/* PCI bridges have only BAR0, BAR1 and ROM */
2420	uint32_t iRegion = fRom ? VBOX_PCI_ROM_SLOT : (uAddress - VBOX_PCI_BASE_ADDRESS_0) >> 2;
2421	devpciR3WriteBarByte(pPciDev, iRegion, uAddress & 0x3, bVal);
2422	fUpdateMappings = true;
2423	break;
2424	}
2425	/* fall thru (bridge config space which isn't a BAR) */
2426	default:
2427	if (fWritable)
2428	/* safe, only needs to go to the config space array */
2429	PDMPciDevSetByte(pPciDev, uAddress, bVal);
2430	break;
2431	}
2432	uAddress++;
2433	u32Value >>= 8;
2434	}
2435
2436	/*
2437	* Update the region mappings if anything changed related to them (command, BARs, ROM).
2438	*/
2439	if (fUpdateMappings)
2440	devpciR3UpdateMappings(pPciDev, fP2PBridge);
2441	}
2442	}
2443	else if (uAddress + cb <= 4096)
2444	LogRel(("PCI: %8s/%u: Write to extended register %d fallen back to generic code\n",
2445	pPciDev->pszNameR3, pPciDev->Int.s.CTX_SUFF(pDevIns)->iInstance, uAddress));
2446	else
2447	AssertMsgFailed(("Write after end of PCI config space\n"));
2448	}
2449
2450
2451	/* -=-=-=-=-=- Debug Info Handlers -=-=-=-=-=- */
2452
2453	/**
2454	* Indents an info line.
2455	* @param pHlp The info helper.
2456	* @param iIndentLvl The desired indentation level.
2457	*/
2458	static void devpciR3InfoIndent(PCDBGFINFOHLP pHlp, unsigned iIndentLvl)
2459	{
2460	for (unsigned i = 0; i < iIndentLvl; i++)
2461	pHlp->pfnPrintf(pHlp, " ");
2462	}
2463
2464
2465	/**
2466	* Recursive worker for devpciR3InfoPci.
2467	*
2468	* @param pBus The bus to show info for.
2469	* @param pHlp The info helpers.
2470	* @param iIndentLvl The indentation level.
2471	* @param fRegisters Whether to show device registers or not.
2472	*/
2473	static void devpciR3InfoPciBus(PDEVPCIBUS pBus, PCDBGFINFOHLP pHlp, unsigned iIndentLvl, bool fRegisters)
2474	{
2475	/* This has to use the callbacks for accuracy reasons. Otherwise it can get
2476	* confusing in the passthrough case or when the callbacks for some device
2477	* are doing something non-trivial (like implementing an indirect
2478	* passthrough approach), because then the abConfig array is an imprecise
2479	* cache needed for efficiency (so that certain reads can be done from
2480	* R0/RC), but far from authoritative or what the guest would see. */
2481
2482	for (uint32_t iDev = 0; iDev < RT_ELEMENTS(pBus->apDevices); iDev++)
2483	{
2484	PPDMPCIDEV pPciDev = pBus->apDevices[iDev];
2485	if (pPciDev != NULL)
2486	{
2487	devpciR3InfoIndent(pHlp, iIndentLvl);
2488
2489	/*
2490	* For passthrough devices MSI/MSI-X mostly reflects the way interrupts delivered to the guest,
2491	* as host driver handles real devices interrupts.
2492	*/
2493	pHlp->pfnPrintf(pHlp, "%02x:%02x.%d %s%s: %04x-%04x %s%s%s",
2494	pBus->iBus, (iDev >> 3) & 0xff, iDev & 0x7,
2495	pPciDev->pszNameR3,
2496	pciDevIsPassthrough(pPciDev) ? " (PASSTHROUGH)" : "",
2497	ich9pciGetWord(pPciDev, VBOX_PCI_VENDOR_ID), ich9pciGetWord(pPciDev, VBOX_PCI_DEVICE_ID),
2498	pBus->fTypeIch9 ? "ICH9" : pBus->fTypePiix3 ? "PIIX3" : "?type?",
2499	pciDevIsMsiCapable(pPciDev) ? " MSI" : "",
2500	pciDevIsMsixCapable(pPciDev) ? " MSI-X" : ""
2501	);
2502	if (ich9pciGetByte(pPciDev, VBOX_PCI_INTERRUPT_PIN) != 0)
2503	{
2504	pHlp->pfnPrintf(pHlp, " IRQ%d", ich9pciGetByte(pPciDev, VBOX_PCI_INTERRUPT_LINE));
2505	pHlp->pfnPrintf(pHlp, " (INTA#->IRQ%d)", 0x10 + ich9pciSlot2ApicIrq(iDev >> 3, 0));
2506	}
2507	pHlp->pfnPrintf(pHlp, "\n");
2508
2509	if (pciDevIsMsiCapable(pPciDev) \|\| pciDevIsMsixCapable(pPciDev))
2510	{
2511	devpciR3InfoIndent(pHlp, iIndentLvl + 2);
2512
2513	if (pciDevIsMsiCapable(pPciDev))
2514	pHlp->pfnPrintf(pHlp, "MSI:%s ", MsiIsEnabled(pPciDev) ? "on" : "off");
2515
2516	if (pciDevIsMsixCapable(pPciDev))
2517	pHlp->pfnPrintf(pHlp, "MSI-X:%s ", MsixIsEnabled(pPciDev) ? "on" : "off");
2518
2519	pHlp->pfnPrintf(pHlp, "\n");
2520	}
2521
2522	for (unsigned iRegion = 0; iRegion < VBOX_PCI_NUM_REGIONS; iRegion++)
2523	{
2524	PCIIORegion const *pRegion = &pPciDev->Int.s.aIORegions[iRegion];
2525	uint64_t const cbRegion = pRegion->size;
2526
2527	if (cbRegion == 0)
2528	continue;
2529
2530	uint32_t uAddr = ich9pciGetDWord(pPciDev, ich9pciGetRegionReg(iRegion));
2531	const char * pszDesc;
2532	char szDescBuf[128];
2533
2534	bool f64Bit = (pRegion->type & ((uint8_t)(PCI_ADDRESS_SPACE_BAR64 \| PCI_ADDRESS_SPACE_IO)))
2535	== PCI_ADDRESS_SPACE_BAR64;
2536	if (pRegion->type & PCI_ADDRESS_SPACE_IO)
2537	{
2538	pszDesc = "IO";
2539	uAddr &= ~0x3;
2540	}
2541	else
2542	{
2543	RTStrPrintf(szDescBuf, sizeof(szDescBuf), "MMIO%s%s",
2544	f64Bit ? "64" : "32",
2545	pRegion->type & PCI_ADDRESS_SPACE_MEM_PREFETCH ? " PREFETCH" : "");
2546	pszDesc = szDescBuf;
2547	uAddr &= ~0xf;
2548	}
2549
2550	devpciR3InfoIndent(pHlp, iIndentLvl + 2);
2551	pHlp->pfnPrintf(pHlp, "%s region #%u: ", pszDesc, iRegion);
2552	if (f64Bit)
2553	{
2554	uint32_t u32High = ich9pciGetDWord(pPciDev, ich9pciGetRegionReg(iRegion+1));
2555	uint64_t u64Addr = RT_MAKE_U64(uAddr, u32High);
2556	pHlp->pfnPrintf(pHlp, "%RX64..%RX64\n", u64Addr, u64Addr + cbRegion - 1);
2557	iRegion++;
2558	}
2559	else
2560	pHlp->pfnPrintf(pHlp, "%x..%x\n", uAddr, uAddr + (uint32_t)cbRegion - 1);
2561	}
2562
2563	devpciR3InfoIndent(pHlp, iIndentLvl + 2);
2564	uint16_t iCmd = ich9pciGetWord(pPciDev, VBOX_PCI_COMMAND);
2565	uint16_t iStatus = ich9pciGetWord(pPciDev, VBOX_PCI_STATUS);
2566	pHlp->pfnPrintf(pHlp, "Command: %04x, Status: %04x\n", iCmd, iStatus);
2567	devpciR3InfoIndent(pHlp, iIndentLvl + 2);
2568	pHlp->pfnPrintf(pHlp, "Bus master: %s\n", iCmd & VBOX_PCI_COMMAND_MASTER ? "Yes" : "No");
2569	if (iCmd != PDMPciDevGetCommand(pPciDev))
2570	{
2571	devpciR3InfoIndent(pHlp, iIndentLvl + 2);
2572	pHlp->pfnPrintf(pHlp, "CACHE INCONSISTENCY: Command: %04x\n", PDMPciDevGetCommand(pPciDev));
2573	}
2574
2575	if (fRegisters)
2576	{
2577	devpciR3InfoIndent(pHlp, iIndentLvl + 2);
2578	pHlp->pfnPrintf(pHlp, "PCI registers:\n");
2579	for (unsigned iReg = 0; iReg < 0x100; )
2580	{
2581	unsigned iPerLine = 0x10;
2582	Assert(0x100 % iPerLine == 0);
2583	devpciR3InfoIndent(pHlp, iIndentLvl + 3);
2584
2585	while (iPerLine-- > 0)
2586	pHlp->pfnPrintf(pHlp, "%02x ", ich9pciGetByte(pPciDev, iReg++));
2587	pHlp->pfnPrintf(pHlp, "\n");
2588	}
2589	}
2590	}
2591	}
2592
2593	if (pBus->cBridges > 0)
2594	{
2595	devpciR3InfoIndent(pHlp, iIndentLvl);
2596	pHlp->pfnPrintf(pHlp, "Registered %d bridges, subordinate buses info follows\n", pBus->cBridges);
2597	for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
2598	{
2599	PDEVPCIBUS pBusSub = PDMINS_2_DATA(pBus->papBridgesR3[iBridge]->Int.s.CTX_SUFF(pDevIns), PDEVPCIBUS);
2600	uint8_t uPrimary = ich9pciGetByte(&pBusSub->PciDev, VBOX_PCI_PRIMARY_BUS);
2601	uint8_t uSecondary = ich9pciGetByte(&pBusSub->PciDev, VBOX_PCI_SECONDARY_BUS);
2602	uint8_t uSubordinate = ich9pciGetByte(&pBusSub->PciDev, VBOX_PCI_SUBORDINATE_BUS);
2603	devpciR3InfoIndent(pHlp, iIndentLvl);
2604	pHlp->pfnPrintf(pHlp, "bridge topology: primary=%d secondary=%d subordinate=%d\n",
2605	uPrimary, uSecondary, uSubordinate);
2606	if ( uPrimary != PDMPciDevGetByte(&pBusSub->PciDev, VBOX_PCI_PRIMARY_BUS)
2607	\|\| uSecondary != PDMPciDevGetByte(&pBusSub->PciDev, VBOX_PCI_SECONDARY_BUS)
2608	\|\| uSubordinate != PDMPciDevGetByte(&pBusSub->PciDev, VBOX_PCI_SUBORDINATE_BUS))
2609	{
2610	devpciR3InfoIndent(pHlp, iIndentLvl);
2611	pHlp->pfnPrintf(pHlp, "CACHE INCONSISTENCY: primary=%d secondary=%d subordinate=%d\n",
2612	PDMPciDevGetByte(&pBusSub->PciDev, VBOX_PCI_PRIMARY_BUS),
2613	PDMPciDevGetByte(&pBusSub->PciDev, VBOX_PCI_SECONDARY_BUS),
2614	PDMPciDevGetByte(&pBusSub->PciDev, VBOX_PCI_SUBORDINATE_BUS));
2615	}
2616	devpciR3InfoIndent(pHlp, iIndentLvl);
2617	pHlp->pfnPrintf(pHlp, "behind bridge: I/O %#06x..%#06x\n",
2618	(ich9pciGetByte(&pBusSub->PciDev, VBOX_PCI_IO_BASE) & 0xf0) << 8,
2619	(ich9pciGetByte(&pBusSub->PciDev, VBOX_PCI_IO_LIMIT) & 0xf0) << 8 \| 0xfff);
2620	devpciR3InfoIndent(pHlp, iIndentLvl);
2621	pHlp->pfnPrintf(pHlp, "behind bridge: memory %#010x..%#010x\n",
2622	(ich9pciGetWord(&pBusSub->PciDev, VBOX_PCI_MEMORY_BASE) & 0xfff0) << 16,
2623	(ich9pciGetWord(&pBusSub->PciDev, VBOX_PCI_MEMORY_LIMIT) & 0xfff0) << 16 \| 0xfffff);
2624	devpciR3InfoIndent(pHlp, iIndentLvl);
2625	pHlp->pfnPrintf(pHlp, "behind bridge: prefetch memory %#018x..%#018x\n",
2626	( ((uint64_t)ich9pciGetDWord(&pBusSub->PciDev, VBOX_PCI_PREF_BASE_UPPER32) << 32)
2627	\| (ich9pciGetWord(&pBusSub->PciDev, VBOX_PCI_PREF_MEMORY_BASE) & 0xfff0) << 16),
2628	( ((uint64_t)ich9pciGetDWord(&pBusSub->PciDev, VBOX_PCI_PREF_LIMIT_UPPER32) << 32)
2629	\| (ich9pciGetWord(&pBusSub->PciDev, VBOX_PCI_PREF_MEMORY_LIMIT) & 0xfff0) << 16)
2630	\| 0xfffff);
2631	devpciR3InfoPciBus(pBusSub, pHlp, iIndentLvl + 1, fRegisters);
2632	}
2633	}
2634	}
2635
2636
2637	/**
2638	* @callback_method_impl{FNDBGFHANDLERDEV, 'pci'}
2639	*/
2640	DECLCALLBACK(void) devpciR3InfoPci(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
2641	{
2642	PDEVPCIBUS pBus = DEVINS_2_DEVPCIBUS(pDevIns);
2643
2644	if (pszArgs == NULL \|\| !*pszArgs \|\| !strcmp(pszArgs, "basic"))
2645	devpciR3InfoPciBus(pBus, pHlp, 0 /iIndentLvl/, false /fRegisters/);
2646	else if (!strcmp(pszArgs, "verbose"))
2647	devpciR3InfoPciBus(pBus, pHlp, 0 /iIndentLvl/, true /fRegisters/);
2648	else
2649	pHlp->pfnPrintf(pHlp, "Invalid argument. Recognized arguments are 'basic', 'verbose'.\n");
2650	}
2651
2652
2653	/**
2654	* @callback_method_impl{FNDBGFHANDLERDEV, 'pciirq'}
2655	*/
2656	DECLCALLBACK(void) devpciR3InfoPciIrq(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
2657	{
2658	PDEVPCIROOT pPciRoot = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
2659	NOREF(pszArgs);
2660
2661	pHlp->pfnPrintf(pHlp, "PCI I/O APIC IRQ levels:\n");
2662	for (int i = 0; i < DEVPCI_APIC_IRQ_PINS; ++i)
2663	pHlp->pfnPrintf(pHlp, " IRQ%02d: %u\n", 0x10 + i, pPciRoot->auPciApicIrqLevels[i]);
2664	}
2665
2666
2667
2668	static DECLCALLBACK(int) ich9pciConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
2669	{
2670	RT_NOREF1(iInstance);
2671	Assert(iInstance == 0);
2672	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
2673
2674	/*
2675	* Validate and read configuration.
2676	*/
2677	if (!CFGMR3AreValuesValid(pCfg,
2678	"IOAPIC\0"
2679	"GCEnabled\0"
2680	"R0Enabled\0"
2681	"McfgBase\0"
2682	"McfgLength\0"
2683	))
2684	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
2685
2686	/* query whether we got an IOAPIC */
2687	bool fUseIoApic;
2688	int rc = CFGMR3QueryBoolDef(pCfg, "IOAPIC", &fUseIoApic, false);
2689	if (RT_FAILURE(rc))
2690	return PDMDEV_SET_ERROR(pDevIns, rc,
2691	N_("Configuration error: Failed to query boolean value \"IOAPIC\""));
2692
2693	/* check if RC code is enabled. */
2694	bool fGCEnabled;
2695	rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
2696	if (RT_FAILURE(rc))
2697	return PDMDEV_SET_ERROR(pDevIns, rc,
2698	N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
2699	/* check if R0 code is enabled. */
2700	bool fR0Enabled;
2701	rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
2702	if (RT_FAILURE(rc))
2703	return PDMDEV_SET_ERROR(pDevIns, rc,
2704	N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
2705
2706	Log(("PCI: fUseIoApic=%RTbool fGCEnabled=%RTbool fR0Enabled=%RTbool\n", fUseIoApic, fGCEnabled, fR0Enabled));
2707
2708	/*
2709	* Init data.
2710	*/
2711	PDEVPCIROOT pPciRoot = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
2712	PDEVPCIBUS pBus = &pPciRoot->PciBus;
2713	/* Zero out everything */
2714	memset(pPciRoot, 0, sizeof(*pPciRoot));
2715	/* And fill values */
2716	if (!fUseIoApic)
2717	return PDMDEV_SET_ERROR(pDevIns, rc,
2718	N_("Must use IO-APIC with ICH9 chipset"));
2719	rc = CFGMR3QueryU64Def(pCfg, "McfgBase", &pPciRoot->u64PciConfigMMioAddress, 0);
2720	if (RT_FAILURE(rc))
2721	return PDMDEV_SET_ERROR(pDevIns, rc,
2722	N_("Configuration error: Failed to read \"McfgBase\""));
2723	rc = CFGMR3QueryU64Def(pCfg, "McfgLength", &pPciRoot->u64PciConfigMMioLength, 0);
2724	if (RT_FAILURE(rc))
2725	return PDMDEV_SET_ERROR(pDevIns, rc,
2726	N_("Configuration error: Failed to read \"McfgLength\""));
2727
2728	pPciRoot->fUseIoApic = fUseIoApic;
2729	pPciRoot->pDevInsR3 = pDevIns;
2730	pPciRoot->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2731	pPciRoot->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2732
2733	pPciRoot->PciBus.fTypePiix3 = false;
2734	pPciRoot->PciBus.fTypeIch9 = true;
2735	pPciRoot->PciBus.fPureBridge = false;
2736	pPciRoot->PciBus.pDevInsR3 = pDevIns;
2737	pPciRoot->PciBus.pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2738	pPciRoot->PciBus.pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2739	pPciRoot->PciBus.papBridgesR3 = (PPDMPCIDEV )PDMDevHlpMMHeapAllocZ(pDevIns, sizeof(PPDMPCIDEV) RT_ELEMENTS(pPciRoot->PciBus.apDevices));
2740	AssertLogRelReturn(pPciRoot->PciBus.papBridgesR3, VERR_NO_MEMORY);
2741
2742	/*
2743	* Register bus
2744	*/
2745	PDMPCIBUSREG PciBusReg;
2746	PciBusReg.u32Version = PDM_PCIBUSREG_VERSION;
2747	PciBusReg.pfnRegisterR3 = pciR3MergedRegister;
2748	PciBusReg.pfnRegisterMsiR3 = ich9pciRegisterMsi;
2749	PciBusReg.pfnIORegionRegisterR3 = devpciR3CommonIORegionRegister;
2750	PciBusReg.pfnSetConfigCallbacksR3 = devpciR3CommonSetConfigCallbacks;
2751	PciBusReg.pfnSetIrqR3 = ich9pciSetIrq;
2752	PciBusReg.pfnFakePCIBIOSR3 = ich9pciFakePCIBIOS;
2753	PciBusReg.pszSetIrqRC = fGCEnabled ? "ich9pciSetIrq" : NULL;
2754	PciBusReg.pszSetIrqR0 = fR0Enabled ? "ich9pciSetIrq" : NULL;
2755	#if PDM_DEVHLPR3_VERSION >= PDM_VERSION_MAKE_PP(0xffe7, 20, 0)
2756	rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBus->pPciHlpR3, &pBus->iBus);
2757	#else
2758	rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBus->pPciHlpR3);
2759	pBus->iBus = rc;
2760	#endif
2761	if (RT_FAILURE(rc))
2762	return PDMDEV_SET_ERROR(pDevIns, rc,
2763	N_("Failed to register ourselves as a PCI Bus"));
2764	Assert(pBus->iBus == 0);
2765	if (pBus->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
2766	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
2767	N_("PCI helper version mismatch; got %#x expected %#x"),
2768	pBus->pPciHlpR3->u32Version, PDM_PCIHLPR3_VERSION);
2769
2770	pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
2771	pBus->pPciHlpR0 = pBus->pPciHlpR3->pfnGetR0Helpers(pDevIns);
2772
2773	/*
2774	* Fill in PCI configs and add them to the bus.
2775	*/
2776	/** @todo Disabled for now because this causes error messages with Linux guests.
2777	* The guest loads the x38_edac device which tries to map a memory region
2778	* using an address given at place 0x48 - 0x4f in the PCi config space.
2779	* This fails. because we don't register such a region.
2780	*/
2781	#if 0
2782	/* Host bridge device */
2783	PDMPciDevSetVendorId( &pBus->PciDev, 0x8086); /* Intel */
2784	PDMPciDevSetDeviceId( &pBus->PciDev, 0x29e0); /* Desktop */
2785	PDMPciDevSetRevisionId(&pBus->PciDev, 0x01); /* rev. 01 */
2786	PDMPciDevSetClassBase( &pBus->PciDev, 0x06); /* bridge */
2787	PDMPciDevSetClassSub( &pBus->PciDev, 0x00); /* Host/PCI bridge */
2788	PDMPciDevSetClassProg( &pBus->PciDev, 0x00); /* Host/PCI bridge */
2789	PDMPciDevSetHeaderType(&pBus->PciDev, 0x00); /* bridge */
2790	PDMPciDevSetWord(&pBus->PciDev, VBOX_PCI_SEC_STATUS, 0x0280); /* secondary status */
2791
2792	pBus->PciDev.pDevIns = pDevIns;
2793	/* We register Host<->PCI controller on the bus */
2794	ich9pciRegisterInternal(pBus, 0, &pBus->PciDev, "dram");
2795	#endif
2796
2797	/*
2798	* Register I/O ports and save state.
2799	*/
2800	rc = PDMDevHlpIOPortRegister(pDevIns, 0x0cf8, 1, NULL, ich9pciIOPortAddressWrite, ich9pciIOPortAddressRead, NULL, NULL, "ICH9 (PCI)");
2801	if (RT_FAILURE(rc))
2802	return rc;
2803	rc = PDMDevHlpIOPortRegister(pDevIns, 0x0cfc, 4, NULL, ich9pciIOPortDataWrite, ich9pciIOPortDataRead, NULL, NULL, "ICH9 (PCI)");
2804	if (RT_FAILURE(rc))
2805	return rc;
2806	if (fGCEnabled)
2807	{
2808	rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x0cf8, 1, NIL_RTGCPTR, "ich9pciIOPortAddressWrite", "ich9pciIOPortAddressRead", NULL, NULL, "ICH9 (PCI)");
2809	if (RT_FAILURE(rc))
2810	return rc;
2811	rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x0cfc, 4, NIL_RTGCPTR, "ich9pciIOPortDataWrite", "ich9pciIOPortDataRead", NULL, NULL, "ICH9 (PCI)");
2812	if (RT_FAILURE(rc))
2813	return rc;
2814	}
2815	if (fR0Enabled)
2816	{
2817	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x0cf8, 1, NIL_RTR0PTR, "ich9pciIOPortAddressWrite", "ich9pciIOPortAddressRead", NULL, NULL, "ICH9 (PCI)");
2818	if (RT_FAILURE(rc))
2819	return rc;
2820	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x0cfc, 4, NIL_RTR0PTR, "ich9pciIOPortDataWrite", "ich9pciIOPortDataRead", NULL, NULL, "ICH9 (PCI)");
2821	if (RT_FAILURE(rc))
2822	return rc;
2823	}
2824
2825	if (pPciRoot->u64PciConfigMMioAddress != 0)
2826	{
2827	rc = PDMDevHlpMMIORegister(pDevIns, pPciRoot->u64PciConfigMMioAddress, pPciRoot->u64PciConfigMMioLength, NULL /pvUser/,
2828	IOMMMIO_FLAGS_READ_PASSTHRU \| IOMMMIO_FLAGS_WRITE_PASSTHRU,
2829	ich9pciMcfgMMIOWrite, ich9pciMcfgMMIORead, "MCFG ranges");
2830	AssertMsgRCReturn(rc, ("rc=%Rrc %#llx/%#llx\n", rc, pPciRoot->u64PciConfigMMioAddress, pPciRoot->u64PciConfigMMioLength), rc);
2831
2832	if (fGCEnabled)
2833	{
2834	rc = PDMDevHlpMMIORegisterRC(pDevIns, pPciRoot->u64PciConfigMMioAddress, pPciRoot->u64PciConfigMMioLength,
2835	NIL_RTRCPTR /pvUser/, "ich9pciMcfgMMIOWrite", "ich9pciMcfgMMIORead");
2836	AssertRCReturn(rc, rc);
2837	}
2838
2839
2840	if (fR0Enabled)
2841	{
2842	rc = PDMDevHlpMMIORegisterR0(pDevIns, pPciRoot->u64PciConfigMMioAddress, pPciRoot->u64PciConfigMMioLength,
2843	NIL_RTR0PTR /pvUser/, "ich9pciMcfgMMIOWrite", "ich9pciMcfgMMIORead");
2844	AssertRCReturn(rc, rc);
2845	}
2846	}
2847
2848	rc = PDMDevHlpSSMRegisterEx(pDevIns, VBOX_ICH9PCI_SAVED_STATE_VERSION,
2849	sizeof(pBus) + 16128, "pgm",
2850	NULL, NULL, NULL,
2851	NULL, ich9pciR3SaveExec, NULL,
2852	NULL, ich9pciR3LoadExec, NULL);
2853	if (RT_FAILURE(rc))
2854	return rc;
2855
2856
2857	/** @todo other chipset devices shall be registered too */
2858
2859	PDMDevHlpDBGFInfoRegister(pDevIns, "pci",
2860	"Display PCI bus status. Recognizes 'basic' or 'verbose' as arguments, defaults to 'basic'.",
2861	devpciR3InfoPci);
2862	PDMDevHlpDBGFInfoRegister(pDevIns, "pciirq", "Display PCI IRQ state. (no arguments)", devpciR3InfoPciIrq);
2863
2864	return VINF_SUCCESS;
2865	}
2866
2867	static void ich9pciResetDevice(PPDMPCIDEV pDev)
2868	{
2869	/* Clear regions */
2870	for (int iRegion = 0; iRegion < VBOX_PCI_NUM_REGIONS; iRegion++)
2871	{
2872	PCIIORegion* pRegion = &pDev->Int.s.aIORegions[iRegion];
2873	if (pRegion->size == 0)
2874	continue;
2875
2876	ich9pciUnmapRegion(pDev, iRegion);
2877	}
2878
2879	if (pciDevIsPassthrough(pDev))
2880	{
2881	// no reset handler - we can do what we need in PDM reset handler
2882	/// @todo is it correct?
2883	}
2884	else
2885	{
2886	ich9pciSetWord(pDev, VBOX_PCI_COMMAND,
2887	ich9pciGetWord(pDev, VBOX_PCI_COMMAND)
2888	& ~(VBOX_PCI_COMMAND_IO \| VBOX_PCI_COMMAND_MEMORY \|
2889	VBOX_PCI_COMMAND_MASTER \| VBOX_PCI_COMMAND_SPECIAL \|
2890	VBOX_PCI_COMMAND_PARITY \| VBOX_PCI_COMMAND_SERR \|
2891	VBOX_PCI_COMMAND_FAST_BACK \| VBOX_PCI_COMMAND_INTX_DISABLE));
2892
2893	/* Bridge device reset handlers processed later */
2894	if (!pciDevIsPci2PciBridge(pDev))
2895	{
2896	ich9pciSetByte(pDev, VBOX_PCI_CACHE_LINE_SIZE, 0x0);
2897	ich9pciSetByte(pDev, VBOX_PCI_INTERRUPT_LINE, 0x0);
2898	}
2899
2900	/* Reset MSI message control. */
2901	if (pciDevIsMsiCapable(pDev))
2902	{
2903	/* Extracted from MsiPciConfigWrite(). */
2904	pDev->abConfig[pDev->Int.s.u8MsiCapOffset + VBOX_MSI_CAP_MESSAGE_CONTROL] &= 0x8e;
2905	}
2906
2907	/* Reset MSI-X message control. */
2908	if (pciDevIsMsixCapable(pDev))
2909	{
2910	/* Extracted from MsixPciConfigWrite(); no side effects. */
2911	pDev->abConfig[pDev->Int.s.u8MsixCapOffset + VBOX_MSIX_CAP_MESSAGE_CONTROL + 1] &= 0x3f;
2912	}
2913	}
2914	}
2915
2916
2917	/**
2918	* @copydoc FNPDMDEVRESET
2919	*/
2920	static DECLCALLBACK(void) ich9pciReset(PPDMDEVINS pDevIns)
2921	{
2922	PDEVPCIROOT pPciRoot = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
2923	PDEVPCIBUS pBus = &pPciRoot->PciBus;
2924
2925	/* PCI-specific reset for each device. */
2926	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
2927	{
2928	if (pBus->apDevices[i])
2929	ich9pciResetDevice(pBus->apDevices[i]);
2930	}
2931
2932	for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
2933	{
2934	if (pBus->papBridgesR3[iBridge])
2935	ich9pcibridgeReset(pBus->papBridgesR3[iBridge]->Int.s.CTX_SUFF(pDevIns));
2936	}
2937
2938	ich9pciFakePCIBIOS(pDevIns);
2939	}
2940
2941
2942	/**
2943	* @interface_method_impl{PDMDEVREG,pfnRelocate}
2944	*/
2945	DECLCALLBACK(void) devpciR3BusRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
2946	{
2947	PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
2948
2949	pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2950	pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
2951
2952	/* Relocate RC pointers for the attached pci devices. */
2953	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
2954	{
2955	PPDMPCIDEV pDev = pBus->apDevices[i];
2956	if (pDev)
2957	{
2958	pDev->Int.s.pBusRC += offDelta;
2959	if (pDev->Int.s.pMsixPageRC)
2960	pDev->Int.s.pMsixPageRC += offDelta;
2961	}
2962	}
2963	}
2964
2965
2966	/**
2967	* @interface_method_impl{PDMDEVREG,pfnRelocate}
2968	*/
2969	DECLCALLBACK(void) devpciR3RootRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
2970	{
2971	PDEVPCIROOT pPciRoot = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
2972	pPciRoot->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2973
2974	AssertCompileMemberOffset(DEVPCIROOT, PciBus, 0);
2975	devpciR3BusRelocate(pDevIns, offDelta);
2976	}
2977
2978
2979	/**
2980	* @interface_method_impl{PDMDEVREG,pfnConstruct}
2981	*/
2982	static DECLCALLBACK(int) ich9pcibridgeConstruct(PPDMDEVINS pDevIns,
2983	int iInstance,
2984	PCFGMNODE pCfg)
2985	{
2986	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
2987
2988	/*
2989	* Validate and read configuration.
2990	*/
2991	if (!CFGMR3AreValuesValid(pCfg, "GCEnabled\0" "R0Enabled\0"))
2992	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
2993
2994	/* check if RC code is enabled. */
2995	bool fGCEnabled;
2996	int rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
2997	if (RT_FAILURE(rc))
2998	return PDMDEV_SET_ERROR(pDevIns, rc,
2999	N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
3000
3001	/* check if R0 code is enabled. */
3002	bool fR0Enabled;
3003	rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
3004	if (RT_FAILURE(rc))
3005	return PDMDEV_SET_ERROR(pDevIns, rc,
3006	N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
3007	Log(("PCI: fGCEnabled=%RTbool fR0Enabled=%RTbool\n", fGCEnabled, fR0Enabled));
3008
3009	/*
3010	* Init data and register the PCI bus.
3011	*/
3012	PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
3013	pBus->fTypePiix3 = false;
3014	pBus->fTypeIch9 = true;
3015	pBus->fPureBridge = true;
3016	pBus->pDevInsR3 = pDevIns;
3017	pBus->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
3018	pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
3019	pBus->papBridgesR3 = (PPDMPCIDEV )PDMDevHlpMMHeapAllocZ(pDevIns, sizeof(PPDMPCIDEV) RT_ELEMENTS(pBus->apDevices));
3020	AssertLogRelReturn(pBus->papBridgesR3, VERR_NO_MEMORY);
3021
3022	PDMPCIBUSREG PciBusReg;
3023	PciBusReg.u32Version = PDM_PCIBUSREG_VERSION;
3024	PciBusReg.pfnRegisterR3 = pcibridgeR3MergedRegisterDevice;
3025	PciBusReg.pfnRegisterMsiR3 = ich9pciRegisterMsi;
3026	PciBusReg.pfnIORegionRegisterR3 = devpciR3CommonIORegionRegister;
3027	PciBusReg.pfnSetConfigCallbacksR3 = devpciR3CommonSetConfigCallbacks;
3028	PciBusReg.pfnSetIrqR3 = ich9pcibridgeSetIrq;
3029	PciBusReg.pfnFakePCIBIOSR3 = NULL; /* Only needed for the first bus. */
3030	PciBusReg.pszSetIrqRC = fGCEnabled ? "ich9pcibridgeSetIrq" : NULL;
3031	PciBusReg.pszSetIrqR0 = fR0Enabled ? "ich9pcibridgeSetIrq" : NULL;
3032	#if PDM_DEVHLPR3_VERSION >= PDM_VERSION_MAKE_PP(0xffe7, 20, 0)
3033	rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBus->pPciHlpR3, &pBus->iBus);
3034	#else
3035	rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBus->pPciHlpR3);
3036	pBus->iBus = rc;
3037	#endif
3038	if (RT_FAILURE(rc))
3039	return PDMDEV_SET_ERROR(pDevIns, rc,
3040	N_("Failed to register ourselves as a PCI Bus"));
3041	Assert(pBus->iBus == (uint32_t)iInstance + 1); /* Can be removed when adding support for multiple bridge implementations. */
3042	if (pBus->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
3043	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
3044	N_("PCI helper version mismatch; got %#x expected %#x"),
3045	pBus->pPciHlpR3->u32Version, PDM_PCIHLPR3_VERSION);
3046
3047	pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
3048	pBus->pPciHlpR0 = pBus->pPciHlpR3->pfnGetR0Helpers(pDevIns);
3049	LogRel(("PCI: Registered bridge instance #%u as PDM bus no %u.\n", iInstance, pBus->iBus));
3050
3051
3052	/* Disable default device locking. */
3053	rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
3054	AssertRCReturn(rc, rc);
3055
3056	/*
3057	* Fill in PCI configs and add them to the bus.
3058	*/
3059	PDMPciDevSetVendorId( &pBus->PciDev, 0x8086); /* Intel */
3060	PDMPciDevSetDeviceId( &pBus->PciDev, 0x2448); /* 82801 Mobile PCI bridge. */
3061	PDMPciDevSetRevisionId(&pBus->PciDev, 0xf2);
3062	PDMPciDevSetClassSub( &pBus->PciDev, 0x04); /* pci2pci */
3063	PDMPciDevSetClassBase( &pBus->PciDev, 0x06); /* PCI_bridge */
3064	PDMPciDevSetClassProg( &pBus->PciDev, 0x01); /* Supports subtractive decoding. */
3065	PDMPciDevSetHeaderType(&pBus->PciDev, 0x01); /* Single function device which adheres to the PCI-to-PCI bridge spec. */
3066	PDMPciDevSetCommand( &pBus->PciDev, 0x00);
3067	PDMPciDevSetStatus( &pBus->PciDev, 0x20); /* 66MHz Capable. */
3068	PDMPciDevSetInterruptLine(&pBus->PciDev, 0x00); /* This device does not assert interrupts. */
3069
3070	/*
3071	* This device does not generate interrupts. Interrupt delivery from
3072	* devices attached to the bus is unaffected.
3073	*/
3074	PDMPciDevSetInterruptPin (&pBus->PciDev, 0x00);
3075
3076	/*
3077	* Register this PCI bridge. The called function will take care on which bus we will get registered.
3078	*/
3079	rc = PDMDevHlpPCIRegisterEx(pDevIns, &pBus->PciDev, PDMPCIDEVREG_CFG_PRIMARY, PDMPCIDEVREG_F_PCI_BRIDGE,
3080	PDMPCIDEVREG_DEV_NO_FIRST_UNUSED, PDMPCIDEVREG_FUN_NO_FIRST_UNUSED, "ich9pcibridge");
3081	if (RT_FAILURE(rc))
3082	return rc;
3083	pBus->PciDev.Int.s.pfnBridgeConfigRead = ich9pcibridgeConfigRead;
3084	pBus->PciDev.Int.s.pfnBridgeConfigWrite = ich9pcibridgeConfigWrite;
3085
3086	/*
3087	* Register SSM handlers. We use the same saved state version as for the host bridge
3088	* to make changes easier.
3089	*/
3090	rc = PDMDevHlpSSMRegisterEx(pDevIns, VBOX_ICH9PCI_SAVED_STATE_VERSION,
3091	sizeof(pBus) + 16128,
3092	"pgm" /* before */,
3093	NULL, NULL, NULL,
3094	NULL, ich9pcibridgeR3SaveExec, NULL,
3095	NULL, ich9pcibridgeR3LoadExec, NULL);
3096	if (RT_FAILURE(rc))
3097	return rc;
3098
3099
3100	return VINF_SUCCESS;
3101	}
3102
3103	/**
3104	* @copydoc FNPDMDEVRESET
3105	*/
3106	static void ich9pcibridgeReset(PPDMDEVINS pDevIns)
3107	{
3108	PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
3109
3110	/* Reset config space to default values. */
3111	ich9pciSetByte(&pBus->PciDev, VBOX_PCI_PRIMARY_BUS, 0);
3112	ich9pciSetByte(&pBus->PciDev, VBOX_PCI_SECONDARY_BUS, 0);
3113	ich9pciSetByte(&pBus->PciDev, VBOX_PCI_SUBORDINATE_BUS, 0);
3114
3115	/* PCI-specific reset for each device. */
3116	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
3117	{
3118	if (pBus->apDevices[i])
3119	ich9pciResetDevice(pBus->apDevices[i]);
3120	}
3121	}
3122
3123
3124
3125	/**
3126	* The PCI bus device registration structure.
3127	*/
3128	const PDMDEVREG g_DevicePciIch9 =
3129	{
3130	/* u32Version */
3131	PDM_DEVREG_VERSION,
3132	/* szName */
3133	"ich9pci",
3134	/* szRCMod */
3135	"VBoxDDRC.rc",
3136	/* szR0Mod */
3137	"VBoxDDR0.r0",
3138	/* pszDescription */
3139	"ICH9 PCI bridge",
3140	/* fFlags */
3141	PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
3142	/* fClass */
3143	PDM_DEVREG_CLASS_BUS_PCI \| PDM_DEVREG_CLASS_BUS_ISA,
3144	/* cMaxInstances */
3145	1,
3146	/* cbInstance */
3147	sizeof(DEVPCIROOT),
3148	/* pfnConstruct */
3149	ich9pciConstruct,
3150	/* pfnDestruct */
3151	NULL,
3152	/* pfnRelocate */
3153	devpciR3RootRelocate,
3154	/* pfnMemSetup */
3155	NULL,
3156	/* pfnPowerOn */
3157	NULL,
3158	/* pfnReset */
3159	ich9pciReset,
3160	/* pfnSuspend */
3161	NULL,
3162	/* pfnResume */
3163	NULL,
3164	/* pfnAttach */
3165	NULL,
3166	/* pfnDetach */
3167	NULL,
3168	/* pfnQueryInterface */
3169	NULL,
3170	/* pfnInitComplete */
3171	NULL,
3172	/* pfnPowerOff */
3173	NULL,
3174	/* pfnSoftReset */
3175	NULL,
3176	/* u32VersionEnd */
3177	PDM_DEVREG_VERSION
3178	};
3179
3180	/**
3181	* The device registration structure
3182	* for the PCI-to-PCI bridge.
3183	*/
3184	const PDMDEVREG g_DevicePciIch9Bridge =
3185	{
3186	/* u32Version */
3187	PDM_DEVREG_VERSION,
3188	/* szName */
3189	"ich9pcibridge",
3190	/* szRCMod */
3191	"VBoxDDRC.rc",
3192	/* szR0Mod */
3193	"VBoxDDR0.r0",
3194	/* pszDescription */
3195	"ICH9 PCI to PCI bridge",
3196	/* fFlags */
3197	PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
3198	/* fClass */
3199	PDM_DEVREG_CLASS_BUS_PCI,
3200	/* cMaxInstances */
3201	~0U,
3202	/* cbInstance */
3203	sizeof(DEVPCIBUS),
3204	/* pfnConstruct */
3205	ich9pcibridgeConstruct,
3206	/* pfnDestruct */
3207	NULL,
3208	/* pfnRelocate */
3209	devpciR3BusRelocate,
3210	/* pfnMemSetup */
3211	NULL,
3212	/* pfnPowerOn */
3213	NULL,
3214	/* pfnReset */
3215	NULL, /* Must be NULL, to make sure only bus driver handles reset */
3216	/* pfnSuspend */
3217	NULL,
3218	/* pfnResume */
3219	NULL,
3220	/* pfnAttach */
3221	NULL,
3222	/* pfnDetach */
3223	NULL,
3224	/* pfnQueryInterface */
3225	NULL,
3226	/* pfnInitComplete */
3227	NULL,
3228	/* pfnPowerOff */
3229	NULL,
3230	/* pfnSoftReset */
3231	NULL,
3232	/* u32VersionEnd */
3233	PDM_DEVREG_VERSION
3234	};
3235
3236	#endif /* IN_RING3 */
3237

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source: vbox/trunk/src/VBox/Devices/Bus/DevPciIch9.cpp@ 65324

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