VirtualBox

source: vbox/trunk/src/VBox/Devices/Bus/MsiCommon.cpp@ 33096

Last change on this file since 33096 was 32935, checked in by vboxsync, 14 years ago

PDM, VMM, PCI: reworked MSI API: now MSIs delivered via IOAPIC API, not with MMIO access, LSI logic now can work in MSI mode
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 8.0 KB
Line 
1/* $Id: MsiCommon.cpp 32935 2010-10-06 09:28:42Z vboxsync $ */
2/** @file
3 * MSI support routines
4 */
5
6/*
7 * Copyright (C) 2010 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17#define LOG_GROUP LOG_GROUP_DEV_PCI
18/* Hack to get PCIDEVICEINT declare at the right point - include "PCIInternal.h". */
19#define PCI_INCLUDE_PRIVATE
20#include <VBox/pci.h>
21#include <VBox/msi.h>
22#include <VBox/pdmdev.h>
23#include <VBox/log.h>
24
25#include "MsiCommon.h"
26
27DECLINLINE(uint16_t) msiGetMessageControl(PPCIDEVICE pDev)
28{
29 return PCIDevGetWord(pDev, pDev->Int.s.u8MsiCapOffset + VBOX_MSI_CAP_MESSAGE_CONTROL);
30}
31
32DECLINLINE(bool) msiIs64Bit(PPCIDEVICE pDev)
33{
34 return (msiGetMessageControl(pDev) & VBOX_PCI_MSI_FLAGS_64BIT) != 0;
35}
36
37DECLINLINE(uint32_t*) msiGetMaskBits(PPCIDEVICE pDev)
38{
39 uint8_t iOff = msiIs64Bit(pDev) ? VBOX_MSI_CAP_MASK_BITS_64 : VBOX_MSI_CAP_MASK_BITS_32;
40 iOff += pDev->Int.s.u8MsiCapOffset;
41 return (uint32_t*)(pDev->config + iOff);
42}
43
44DECLINLINE(uint32_t*) msiGetPendingBits(PPCIDEVICE pDev)
45{
46 uint8_t iOff = msiIs64Bit(pDev) ? VBOX_MSI_CAP_PENDING_BITS_64 : VBOX_MSI_CAP_PENDING_BITS_32;
47 iOff += pDev->Int.s.u8MsiCapOffset;
48 return (uint32_t*)(pDev->config + iOff);
49}
50
51DECLINLINE(bool) msiIsEnabled(PPCIDEVICE pDev)
52{
53 return (msiGetMessageControl(pDev) & VBOX_PCI_MSI_FLAGS_ENABLE) != 0;
54}
55
56DECLINLINE(bool) msiIsMME(PPCIDEVICE pDev)
57{
58 return (msiGetMessageControl(pDev) & VBOX_PCI_MSI_FLAGS_QSIZE) != 0;
59}
60
61DECLINLINE(RTGCPHYS) msiGetMsiAddress(PPCIDEVICE pDev)
62{
63 if (msiIs64Bit(pDev))
64 {
65 uint32_t lo = PCIDevGetDWord(pDev, pDev->Int.s.u8MsiCapOffset + VBOX_MSI_CAP_MESSAGE_ADDRESS_LO);
66 uint32_t hi = PCIDevGetDWord(pDev, pDev->Int.s.u8MsiCapOffset + VBOX_MSI_CAP_MESSAGE_ADDRESS_HI);
67 return RT_MAKE_U64(lo, hi);
68 }
69 else
70 {
71 return PCIDevGetDWord(pDev, pDev->Int.s.u8MsiCapOffset + VBOX_MSI_CAP_MESSAGE_ADDRESS_32);
72 }
73}
74
75DECLINLINE(uint32_t) msiGetMsiData(PPCIDEVICE pDev, int32_t iVector)
76{
77 int16_t iOff = msiIs64Bit(pDev) ? VBOX_MSI_CAP_MESSAGE_DATA_64 : VBOX_MSI_CAP_MESSAGE_DATA_32;
78 uint16_t lo = PCIDevGetWord(pDev, pDev->Int.s.u8MsiCapOffset + iOff);
79
80 /// @todo: vector encoding into lower bits of message data, for Multiple Message Enable
81 Assert(!msiIsMME(pDev));
82
83 return RT_MAKE_U32(lo, 0);
84}
85
86DECLINLINE(bool) msiBitJustCleared(uint32_t u32OldValue,
87 uint32_t u32NewValue,
88 uint32_t u32Mask)
89{
90 return (!!(u32OldValue & u32Mask) && !(u32NewValue & u32Mask));
91}
92
93
94void MsiPciConfigWrite(PPDMDEVINS pDevIns, PCPDMPCIHLP pPciHlp, PPCIDEVICE pDev, uint32_t u32Address, uint32_t val, unsigned len)
95{
96 int32_t iOff = u32Address - pDev->Int.s.u8MsiCapOffset;
97 Assert(iOff >= 0 && (PCIIsMsiCapable(pDev) && iOff < pDev->Int.s.u8MsiCapSize));
98
99 Log2(("MSIPciConfigWrite: %d <- %x (%d)\n", iOff, val, len));
100
101 uint32_t uAddr = u32Address;
102 bool f64Bit = msiIs64Bit(pDev);
103
104 for (uint32_t i = 0; i < len; i++)
105 {
106 uint32_t reg = i + iOff;
107 switch (reg)
108 {
109 case 0: /* Capability ID, ro */
110 case 1: /* Next pointer, ro */
111 break;
112 case VBOX_MSI_CAP_MESSAGE_CONTROL:
113 /* don't change read-only bits: 1-3,7 */
114 val &= UINT32_C(~0x8e);
115 pDev->config[uAddr] = val;
116 break;
117 case VBOX_MSI_CAP_MESSAGE_CONTROL + 1:
118 /* don't change read-only bit 8, and reserved 9-15 */
119 break;
120 default:
121 if (pDev->config[uAddr] != val)
122 {
123 int32_t maskUpdated = -1;
124
125 /* If we're enabling masked vector, and have pending messages
126 for this vector, we have to send this message now */
127 if ( !f64Bit
128 && (reg >= VBOX_MSI_CAP_MASK_BITS_32)
129 && (reg < VBOX_MSI_CAP_MASK_BITS_32 + 4)
130 )
131 {
132 maskUpdated = reg - VBOX_MSI_CAP_MASK_BITS_32;
133 }
134 if ( f64Bit
135 && (reg >= VBOX_MSI_CAP_MASK_BITS_64)
136 && (reg < VBOX_MSI_CAP_MASK_BITS_64 + 4)
137 )
138 {
139 maskUpdated = reg - VBOX_MSI_CAP_MASK_BITS_64;
140 }
141
142 if (maskUpdated != -1 && msiIsEnabled(pDev))
143 {
144 for (int iBitNum = 0; i<8; i++)
145 {
146 int32_t iBit = 1 << iBitNum;
147 if (msiBitJustCleared(pDev->config[uAddr], val, iBit))
148 {
149 /* To ensure that we're no longer masked */
150 pDev->config[uAddr] &= ~iBit;
151 MsiNotify(pDevIns, pPciHlp, pDev, maskUpdated*8 + iBitNum);
152 }
153 }
154 }
155
156 pDev->config[uAddr] = val;
157 }
158 }
159 uAddr++;
160 val >>= 8;
161 }
162}
163
164uint32_t MsiPciConfigRead (PPDMDEVINS pDevIns, PPCIDEVICE pDev, uint32_t u32Address, unsigned len)
165{
166 int32_t iOff = u32Address - pDev->Int.s.u8MsiCapOffset;
167
168 Assert(iOff >= 0 && (PCIIsMsiCapable(pDev) && iOff < pDev->Int.s.u8MsiCapSize));
169 uint32_t rv = 0;
170
171 switch (len)
172 {
173 case 1:
174 rv = PCIDevGetByte(pDev, u32Address);
175 break;
176 case 2:
177 rv = PCIDevGetWord(pDev, u32Address);
178 break;
179 case 4:
180 rv = PCIDevGetDWord(pDev, u32Address);
181 break;
182 default:
183 Assert(false);
184 }
185
186 Log2(("MSIPciConfigRead: %d (%d) -> %x\n", iOff, len, rv));
187
188 return rv;
189}
190
191
192int MsiInit(PPCIDEVICE pDev, PPDMMSIREG pMsiReg)
193{
194 uint16_t cVectors = pMsiReg->cVectors;
195 uint8_t iCapOffset = pMsiReg->iCapOffset;
196 uint8_t iNextOffset = pMsiReg->iNextOffset;
197 uint16_t iMsiFlags = pMsiReg->iMsiFlags;
198
199 Assert(cVectors > 0);
200
201 if (cVectors != 1)
202 /* We cannot handle multiple vectors yet */
203 return VERR_TOO_MUCH_DATA;
204
205 if (cVectors > VBOX_MSI_MAX_ENTRIES)
206 return VERR_TOO_MUCH_DATA;
207
208 Assert(iCapOffset != 0 && iCapOffset < 0xff && iNextOffset < 0xff);
209
210 bool f64bit = (iMsiFlags & VBOX_PCI_MSI_FLAGS_64BIT) != 0;
211 /* We always support per-vector masking */
212 iMsiFlags |= VBOX_PCI_MSI_FLAGS_MASKBIT;
213
214 pDev->Int.s.u8MsiCapOffset = iCapOffset;
215 pDev->Int.s.u8MsiCapSize = f64bit ? VBOX_MSI_CAP_SIZE_64 : VBOX_MSI_CAP_SIZE_32;
216
217 PCIDevSetByte(pDev, iCapOffset + 0, VBOX_PCI_CAP_ID_MSI);
218 PCIDevSetByte(pDev, iCapOffset + 1, iNextOffset); /* next */
219 PCIDevSetWord(pDev, iCapOffset + VBOX_MSI_CAP_MESSAGE_CONTROL, iMsiFlags);
220
221 PCISetMsiCapable(pDev);
222
223 return VINF_SUCCESS;
224}
225
226
227bool MsiIsEnabled(PPCIDEVICE pDev)
228{
229 return PCIIsMsiCapable(pDev) && msiIsEnabled(pDev);
230}
231
232void MsiNotify(PPDMDEVINS pDevIns, PCPDMPCIHLP pPciHlp, PPCIDEVICE pDev, int iVector)
233{
234 Log2(("MSINotify: %d\n", iVector));
235
236 AssertMsg(msiIsEnabled(pDev), ("Must be enabled to use that"));
237
238 uint32_t uMask = *msiGetMaskBits(pDev);
239 uint32_t* upPending = msiGetPendingBits(pDev);
240
241 if ((uMask & (1<<iVector)) != 0)
242 {
243 *upPending |= (1<<iVector);
244 return;
245 }
246
247 RTGCPHYS GCAddr = msiGetMsiAddress(pDev);
248 uint32_t u32Value = msiGetMsiData(pDev, iVector);
249
250 *upPending &= ~(1<<iVector);
251
252 Assert(pPciHlp->pfnIoApicSendMsi != NULL);
253 pPciHlp->pfnIoApicSendMsi(pDevIns, GCAddr, u32Value);
254}
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