1 | /* $Id: MsiCommon.cpp 36663 2011-04-13 15:57:33Z vboxsync $ */
|
---|
2 | /** @file
|
---|
3 | * MSI support routines
|
---|
4 | */
|
---|
5 |
|
---|
6 | /*
|
---|
7 | * Copyright (C) 2010 Oracle Corporation
|
---|
8 | *
|
---|
9 | * This file is part of VirtualBox Open Source Edition (OSE), as
|
---|
10 | * available from http://www.virtualbox.org. This file is free software;
|
---|
11 | * you can redistribute it and/or modify it under the terms of the GNU
|
---|
12 | * General Public License (GPL) as published by the Free Software
|
---|
13 | * Foundation, in version 2 as it comes in the "COPYING" file of the
|
---|
14 | * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
|
---|
15 | * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
|
---|
16 | */
|
---|
17 | #define LOG_GROUP LOG_GROUP_DEV_PCI
|
---|
18 | /* Hack to get PCIDEVICEINT declare at the right point - include "PCIInternal.h". */
|
---|
19 | #define PCI_INCLUDE_PRIVATE
|
---|
20 | #include <VBox/pci.h>
|
---|
21 | #include <VBox/msi.h>
|
---|
22 | #include <VBox/vmm/pdmdev.h>
|
---|
23 | #include <VBox/log.h>
|
---|
24 |
|
---|
25 | #include "MsiCommon.h"
|
---|
26 |
|
---|
27 | /** @todo: use accessors so that raw PCI devices work correctly with MSI. */
|
---|
28 | DECLINLINE(uint16_t) msiGetMessageControl(PPCIDEVICE pDev)
|
---|
29 | {
|
---|
30 | return PCIDevGetWord(pDev, pDev->Int.s.u8MsiCapOffset + VBOX_MSI_CAP_MESSAGE_CONTROL);
|
---|
31 | }
|
---|
32 |
|
---|
33 | DECLINLINE(bool) msiIs64Bit(PPCIDEVICE pDev)
|
---|
34 | {
|
---|
35 | return pciDevIsMsi64Capable(pDev);
|
---|
36 | }
|
---|
37 |
|
---|
38 | DECLINLINE(uint32_t*) msiGetMaskBits(PPCIDEVICE pDev)
|
---|
39 | {
|
---|
40 | uint8_t iOff = msiIs64Bit(pDev) ? VBOX_MSI_CAP_MASK_BITS_64 : VBOX_MSI_CAP_MASK_BITS_32;
|
---|
41 | iOff += pDev->Int.s.u8MsiCapOffset;
|
---|
42 | return (uint32_t*)(pDev->config + iOff);
|
---|
43 | }
|
---|
44 |
|
---|
45 | DECLINLINE(uint32_t*) msiGetPendingBits(PPCIDEVICE pDev)
|
---|
46 | {
|
---|
47 | uint8_t iOff = msiIs64Bit(pDev) ? VBOX_MSI_CAP_PENDING_BITS_64 : VBOX_MSI_CAP_PENDING_BITS_32;
|
---|
48 | iOff += pDev->Int.s.u8MsiCapOffset;
|
---|
49 | return (uint32_t*)(pDev->config + iOff);
|
---|
50 | }
|
---|
51 |
|
---|
52 | DECLINLINE(bool) msiIsEnabled(PPCIDEVICE pDev)
|
---|
53 | {
|
---|
54 | return (msiGetMessageControl(pDev) & VBOX_PCI_MSI_FLAGS_ENABLE) != 0;
|
---|
55 | }
|
---|
56 |
|
---|
57 | DECLINLINE(uint8_t) msiGetMme(PPCIDEVICE pDev)
|
---|
58 | {
|
---|
59 | return (msiGetMessageControl(pDev) & VBOX_PCI_MSI_FLAGS_QSIZE) >> 4;
|
---|
60 | }
|
---|
61 |
|
---|
62 | DECLINLINE(RTGCPHYS) msiGetMsiAddress(PPCIDEVICE pDev)
|
---|
63 | {
|
---|
64 | if (msiIs64Bit(pDev))
|
---|
65 | {
|
---|
66 | uint32_t lo = PCIDevGetDWord(pDev, pDev->Int.s.u8MsiCapOffset + VBOX_MSI_CAP_MESSAGE_ADDRESS_LO);
|
---|
67 | uint32_t hi = PCIDevGetDWord(pDev, pDev->Int.s.u8MsiCapOffset + VBOX_MSI_CAP_MESSAGE_ADDRESS_HI);
|
---|
68 | return RT_MAKE_U64(lo, hi);
|
---|
69 | }
|
---|
70 | else
|
---|
71 | {
|
---|
72 | return PCIDevGetDWord(pDev, pDev->Int.s.u8MsiCapOffset + VBOX_MSI_CAP_MESSAGE_ADDRESS_32);
|
---|
73 | }
|
---|
74 | }
|
---|
75 |
|
---|
76 | DECLINLINE(uint32_t) msiGetMsiData(PPCIDEVICE pDev, int32_t iVector)
|
---|
77 | {
|
---|
78 | int16_t iOff = msiIs64Bit(pDev) ? VBOX_MSI_CAP_MESSAGE_DATA_64 : VBOX_MSI_CAP_MESSAGE_DATA_32;
|
---|
79 | uint16_t lo = PCIDevGetWord(pDev, pDev->Int.s.u8MsiCapOffset + iOff);
|
---|
80 |
|
---|
81 | // vector encoding into lower bits of message data
|
---|
82 | uint8_t bits = msiGetMme(pDev);
|
---|
83 | uint16_t uMask = ((1 << bits) - 1);
|
---|
84 | lo &= ~uMask;
|
---|
85 | lo |= iVector & uMask;
|
---|
86 |
|
---|
87 | return RT_MAKE_U32(lo, 0);
|
---|
88 | }
|
---|
89 |
|
---|
90 | DECLINLINE(bool) msiBitJustCleared(uint32_t uOldValue,
|
---|
91 | uint32_t uNewValue,
|
---|
92 | uint32_t uMask)
|
---|
93 | {
|
---|
94 | return (!!(uOldValue & uMask) && !(uNewValue & uMask));
|
---|
95 | }
|
---|
96 |
|
---|
97 | DECLINLINE(bool) msiBitJustSet(uint32_t uOldValue,
|
---|
98 | uint32_t uNewValue,
|
---|
99 | uint32_t uMask)
|
---|
100 | {
|
---|
101 | return (!(uOldValue & uMask) && !!(uNewValue & uMask));
|
---|
102 | }
|
---|
103 |
|
---|
104 | #ifdef IN_RING3
|
---|
105 | void MsiPciConfigWrite(PPDMDEVINS pDevIns, PCPDMPCIHLP pPciHlp, PPCIDEVICE pDev, uint32_t u32Address, uint32_t val, unsigned len)
|
---|
106 | {
|
---|
107 | int32_t iOff = u32Address - pDev->Int.s.u8MsiCapOffset;
|
---|
108 | Assert(iOff >= 0 && (pciDevIsMsiCapable(pDev) && iOff < pDev->Int.s.u8MsiCapSize));
|
---|
109 |
|
---|
110 | Log2(("MsiPciConfigWrite: %d <- %x (%d)\n", iOff, val, len));
|
---|
111 |
|
---|
112 | uint32_t uAddr = u32Address;
|
---|
113 | bool f64Bit = msiIs64Bit(pDev);
|
---|
114 |
|
---|
115 | for (uint32_t i = 0; i < len; i++)
|
---|
116 | {
|
---|
117 | uint32_t reg = i + iOff;
|
---|
118 | uint8_t u8Val = (uint8_t)val;
|
---|
119 | switch (reg)
|
---|
120 | {
|
---|
121 | case 0: /* Capability ID, ro */
|
---|
122 | case 1: /* Next pointer, ro */
|
---|
123 | break;
|
---|
124 | case VBOX_MSI_CAP_MESSAGE_CONTROL:
|
---|
125 | /* don't change read-only bits: 1-3,7 */
|
---|
126 | u8Val &= UINT8_C(~0x8e);
|
---|
127 | pDev->config[uAddr] = u8Val | (pDev->config[uAddr] & UINT8_C(0x8e));
|
---|
128 | break;
|
---|
129 | case VBOX_MSI_CAP_MESSAGE_CONTROL + 1:
|
---|
130 | /* don't change read-only bit 8, and reserved 9-15 */
|
---|
131 | break;
|
---|
132 | default:
|
---|
133 | if (pDev->config[uAddr] != u8Val)
|
---|
134 | {
|
---|
135 | int32_t maskUpdated = -1;
|
---|
136 |
|
---|
137 | /* If we're enabling masked vector, and have pending messages
|
---|
138 | for this vector, we have to send this message now */
|
---|
139 | if ( !f64Bit
|
---|
140 | && (reg >= VBOX_MSI_CAP_MASK_BITS_32)
|
---|
141 | && (reg < VBOX_MSI_CAP_MASK_BITS_32 + 4)
|
---|
142 | )
|
---|
143 | {
|
---|
144 | maskUpdated = reg - VBOX_MSI_CAP_MASK_BITS_32;
|
---|
145 | }
|
---|
146 | if ( f64Bit
|
---|
147 | && (reg >= VBOX_MSI_CAP_MASK_BITS_64)
|
---|
148 | && (reg < VBOX_MSI_CAP_MASK_BITS_64 + 4)
|
---|
149 | )
|
---|
150 | {
|
---|
151 | maskUpdated = reg - VBOX_MSI_CAP_MASK_BITS_64;
|
---|
152 | }
|
---|
153 |
|
---|
154 | if (maskUpdated != -1 && msiIsEnabled(pDev))
|
---|
155 | {
|
---|
156 | uint32_t* puPending = msiGetPendingBits(pDev);
|
---|
157 | for (int iBitNum = 0; iBitNum < 8; iBitNum++)
|
---|
158 | {
|
---|
159 | int32_t iBit = 1 << iBitNum;
|
---|
160 | uint32_t uVector = maskUpdated*8 + iBitNum;
|
---|
161 |
|
---|
162 | if (msiBitJustCleared(pDev->config[uAddr], u8Val, iBit))
|
---|
163 | {
|
---|
164 | Log(("msi: mask updated bit %d@%x (%d)\n", iBitNum, uAddr, maskUpdated));
|
---|
165 |
|
---|
166 | /* To ensure that we're no longer masked */
|
---|
167 | pDev->config[uAddr] &= ~iBit;
|
---|
168 | if ((*puPending & (1 << uVector)) != 0)
|
---|
169 | {
|
---|
170 | Log(("msi: notify earlier masked pending vector: %d\n", uVector));
|
---|
171 | MsiNotify(pDevIns, pPciHlp, pDev, uVector, PDM_IRQ_LEVEL_HIGH);
|
---|
172 | }
|
---|
173 | }
|
---|
174 | if (msiBitJustSet(pDev->config[uAddr], u8Val, iBit))
|
---|
175 | {
|
---|
176 | Log(("msi: mask vector: %d\n", uVector));
|
---|
177 | }
|
---|
178 | }
|
---|
179 | }
|
---|
180 |
|
---|
181 | pDev->config[uAddr] = u8Val;
|
---|
182 | }
|
---|
183 | }
|
---|
184 | uAddr++;
|
---|
185 | val >>= 8;
|
---|
186 | }
|
---|
187 | }
|
---|
188 |
|
---|
189 | uint32_t MsiPciConfigRead (PPDMDEVINS pDevIns, PPCIDEVICE pDev, uint32_t u32Address, unsigned len)
|
---|
190 | {
|
---|
191 | int32_t iOff = u32Address - pDev->Int.s.u8MsiCapOffset;
|
---|
192 |
|
---|
193 | Assert(iOff >= 0 && (pciDevIsMsiCapable(pDev) && iOff < pDev->Int.s.u8MsiCapSize));
|
---|
194 | uint32_t rv = 0;
|
---|
195 |
|
---|
196 | switch (len)
|
---|
197 | {
|
---|
198 | case 1:
|
---|
199 | rv = PCIDevGetByte(pDev, u32Address);
|
---|
200 | break;
|
---|
201 | case 2:
|
---|
202 | rv = PCIDevGetWord(pDev, u32Address);
|
---|
203 | break;
|
---|
204 | case 4:
|
---|
205 | rv = PCIDevGetDWord(pDev, u32Address);
|
---|
206 | break;
|
---|
207 | default:
|
---|
208 | Assert(false);
|
---|
209 | }
|
---|
210 |
|
---|
211 | Log2(("MsiPciConfigRead: %d (%d) -> %x\n", iOff, len, rv));
|
---|
212 |
|
---|
213 | return rv;
|
---|
214 | }
|
---|
215 |
|
---|
216 | int MsiInit(PPCIDEVICE pDev, PPDMMSIREG pMsiReg)
|
---|
217 | {
|
---|
218 | if (pMsiReg->cMsiVectors == 0)
|
---|
219 | return VINF_SUCCESS;
|
---|
220 |
|
---|
221 | /* We cannot init MSI on raw devices yet. */
|
---|
222 | Assert(!pciDevIsPassthrough(pDev));
|
---|
223 |
|
---|
224 | uint16_t cVectors = pMsiReg->cMsiVectors;
|
---|
225 | uint8_t iCapOffset = pMsiReg->iMsiCapOffset;
|
---|
226 | uint8_t iNextOffset = pMsiReg->iMsiNextOffset;
|
---|
227 | bool f64bit = pMsiReg->fMsi64bit;
|
---|
228 | uint16_t iFlags = 0;
|
---|
229 | int iMmc;
|
---|
230 |
|
---|
231 | /* Compute multiple-message capable bitfield */
|
---|
232 | for (iMmc = 0; iMmc < 6; iMmc++)
|
---|
233 | {
|
---|
234 | if ((1 << iMmc) >= cVectors)
|
---|
235 | break;
|
---|
236 | }
|
---|
237 |
|
---|
238 | if ((cVectors > VBOX_MSI_MAX_ENTRIES) || (1 << iMmc) < cVectors)
|
---|
239 | return VERR_TOO_MUCH_DATA;
|
---|
240 |
|
---|
241 | Assert(iCapOffset != 0 && iCapOffset < 0xff && iNextOffset < 0xff);
|
---|
242 |
|
---|
243 | /* We always support per-vector masking */
|
---|
244 | iFlags |= VBOX_PCI_MSI_FLAGS_MASKBIT | iMmc;
|
---|
245 | if (f64bit)
|
---|
246 | iFlags |= VBOX_PCI_MSI_FLAGS_64BIT;
|
---|
247 | /* How many vectors we're capable of */
|
---|
248 | iFlags |= iMmc;
|
---|
249 |
|
---|
250 | pDev->Int.s.u8MsiCapOffset = iCapOffset;
|
---|
251 | pDev->Int.s.u8MsiCapSize = f64bit ? VBOX_MSI_CAP_SIZE_64 : VBOX_MSI_CAP_SIZE_32;
|
---|
252 |
|
---|
253 | PCIDevSetByte(pDev, iCapOffset + 0, VBOX_PCI_CAP_ID_MSI);
|
---|
254 | PCIDevSetByte(pDev, iCapOffset + 1, iNextOffset); /* next */
|
---|
255 | PCIDevSetWord(pDev, iCapOffset + VBOX_MSI_CAP_MESSAGE_CONTROL, iFlags);
|
---|
256 |
|
---|
257 | *msiGetMaskBits(pDev) = 0;
|
---|
258 | *msiGetPendingBits(pDev) = 0;
|
---|
259 |
|
---|
260 | pciDevSetMsiCapable(pDev);
|
---|
261 |
|
---|
262 | return VINF_SUCCESS;
|
---|
263 | }
|
---|
264 |
|
---|
265 | #endif /* IN_RING3 */
|
---|
266 |
|
---|
267 |
|
---|
268 | bool MsiIsEnabled(PPCIDEVICE pDev)
|
---|
269 | {
|
---|
270 | return pciDevIsMsiCapable(pDev) && msiIsEnabled(pDev);
|
---|
271 | }
|
---|
272 |
|
---|
273 | void MsiNotify(PPDMDEVINS pDevIns, PCPDMPCIHLP pPciHlp, PPCIDEVICE pDev, int iVector, int iLevel)
|
---|
274 | {
|
---|
275 | AssertMsg(msiIsEnabled(pDev), ("Must be enabled to use that"));
|
---|
276 |
|
---|
277 | uint32_t uMask = *msiGetMaskBits(pDev);
|
---|
278 | uint32_t* puPending = msiGetPendingBits(pDev);
|
---|
279 |
|
---|
280 | LogFlow(("MsiNotify: %d pending=%x mask=%x\n", iVector, *puPending, uMask));
|
---|
281 |
|
---|
282 | /* We only trigger MSI on level up */
|
---|
283 | if ((iLevel & PDM_IRQ_LEVEL_HIGH) == 0)
|
---|
284 | {
|
---|
285 | /* @todo: maybe clear pending interrupts on level down? */
|
---|
286 | #if 0
|
---|
287 | *puPending &= ~(1<<iVector);
|
---|
288 | LogFlow(("msi: clear pending %d, now %x\n", iVector, *puPending));
|
---|
289 | #endif
|
---|
290 | return;
|
---|
291 | }
|
---|
292 |
|
---|
293 | if ((uMask & (1<<iVector)) != 0)
|
---|
294 | {
|
---|
295 | *puPending |= (1<<iVector);
|
---|
296 | LogFlow(("msi: %d is masked, mark pending, now %x\n", iVector, *puPending));
|
---|
297 | return;
|
---|
298 | }
|
---|
299 |
|
---|
300 | RTGCPHYS GCAddr = msiGetMsiAddress(pDev);
|
---|
301 | uint32_t u32Value = msiGetMsiData(pDev, iVector);
|
---|
302 |
|
---|
303 | *puPending &= ~(1<<iVector);
|
---|
304 |
|
---|
305 | Assert(pPciHlp->pfnIoApicSendMsi != NULL);
|
---|
306 | pPciHlp->pfnIoApicSendMsi(pDevIns, GCAddr, u32Value);
|
---|
307 | }
|
---|