VirtualBox

source: vbox/trunk/src/VBox/Devices/Bus/MsiCommon.cpp@ 64387

Last change on this file since 64387 was 64387, checked in by vboxsync, 8 years ago

PDM,Devices: Some PCI device type cleanup.
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File size: 10.8 KB
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1/* $Id: MsiCommon.cpp 64387 2016-10-24 14:06:02Z vboxsync $ */
2/** @file
3 * MSI support routines
4 *
5 * @todo Straighten up this file!!
6 */
7
8/*
9 * Copyright (C) 2010-2016 Oracle Corporation
10 *
11 * This file is part of VirtualBox Open Source Edition (OSE), as
12 * available from http://www.virtualbox.org. This file is free software;
13 * you can redistribute it and/or modify it under the terms of the GNU
14 * General Public License (GPL) as published by the Free Software
15 * Foundation, in version 2 as it comes in the "COPYING" file of the
16 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
17 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
18 */
19#define LOG_GROUP LOG_GROUP_DEV_PCI
20#define PDMPCIDEV_INCLUDE_PRIVATE /* Hack to get pdmpcidevint.h included at the right point. */
21#include <VBox/pci.h>
22#include <VBox/msi.h>
23#include <VBox/vmm/pdmdev.h>
24#include <VBox/log.h>
25
26#include "MsiCommon.h"
27#include "PciInline.h"
28
29DECLINLINE(uint16_t) msiGetMessageControl(PPDMPCIDEV pDev)
30{
31 uint32_t idxMessageControl = pDev->Int.s.u8MsiCapOffset + VBOX_MSI_CAP_MESSAGE_CONTROL;
32#ifdef IN_RING3
33 if (pciDevIsPassthrough(pDev)) {
34 return pDev->Int.s.pfnConfigRead(pDev->Int.s.CTX_SUFF(pDevIns), pDev, idxMessageControl, 2);
35 }
36#endif
37 return PCIDevGetWord(pDev, idxMessageControl);
38}
39
40DECLINLINE(bool) msiIs64Bit(PPDMPCIDEV pDev)
41{
42 return pciDevIsMsi64Capable(pDev);
43}
44
45DECLINLINE(uint32_t*) msiGetMaskBits(PPDMPCIDEV pDev)
46{
47 uint8_t iOff = msiIs64Bit(pDev) ? VBOX_MSI_CAP_MASK_BITS_64 : VBOX_MSI_CAP_MASK_BITS_32;
48 /* passthrough devices may have no masked/pending support */
49 if (iOff >= pDev->Int.s.u8MsiCapSize)
50 return NULL;
51 iOff += pDev->Int.s.u8MsiCapOffset;
52 return (uint32_t*)(pDev->config + iOff);
53}
54
55DECLINLINE(uint32_t*) msiGetPendingBits(PPDMPCIDEV pDev)
56{
57 uint8_t iOff = msiIs64Bit(pDev) ? VBOX_MSI_CAP_PENDING_BITS_64 : VBOX_MSI_CAP_PENDING_BITS_32;
58 /* passthrough devices may have no masked/pending support */
59 if (iOff >= pDev->Int.s.u8MsiCapSize)
60 return NULL;
61 iOff += pDev->Int.s.u8MsiCapOffset;
62 return (uint32_t*)(pDev->config + iOff);
63}
64
65DECLINLINE(bool) msiIsEnabled(PPDMPCIDEV pDev)
66{
67 return (msiGetMessageControl(pDev) & VBOX_PCI_MSI_FLAGS_ENABLE) != 0;
68}
69
70DECLINLINE(uint8_t) msiGetMme(PPDMPCIDEV pDev)
71{
72 return (msiGetMessageControl(pDev) & VBOX_PCI_MSI_FLAGS_QSIZE) >> 4;
73}
74
75DECLINLINE(RTGCPHYS) msiGetMsiAddress(PPDMPCIDEV pDev)
76{
77 if (msiIs64Bit(pDev))
78 {
79 uint32_t lo = PCIDevGetDWord(pDev, pDev->Int.s.u8MsiCapOffset + VBOX_MSI_CAP_MESSAGE_ADDRESS_LO);
80 uint32_t hi = PCIDevGetDWord(pDev, pDev->Int.s.u8MsiCapOffset + VBOX_MSI_CAP_MESSAGE_ADDRESS_HI);
81 return RT_MAKE_U64(lo, hi);
82 }
83 else
84 {
85 return PCIDevGetDWord(pDev, pDev->Int.s.u8MsiCapOffset + VBOX_MSI_CAP_MESSAGE_ADDRESS_32);
86 }
87}
88
89DECLINLINE(uint32_t) msiGetMsiData(PPDMPCIDEV pDev, int32_t iVector)
90{
91 int16_t iOff = msiIs64Bit(pDev) ? VBOX_MSI_CAP_MESSAGE_DATA_64 : VBOX_MSI_CAP_MESSAGE_DATA_32;
92 uint16_t lo = PCIDevGetWord(pDev, pDev->Int.s.u8MsiCapOffset + iOff);
93
94 // vector encoding into lower bits of message data
95 uint8_t bits = msiGetMme(pDev);
96 uint16_t uMask = ((1 << bits) - 1);
97 lo &= ~uMask;
98 lo |= iVector & uMask;
99
100 return RT_MAKE_U32(lo, 0);
101}
102
103#ifdef IN_RING3
104
105DECLINLINE(bool) msiBitJustCleared(uint32_t uOldValue,
106 uint32_t uNewValue,
107 uint32_t uMask)
108{
109 return (!!(uOldValue & uMask) && !(uNewValue & uMask));
110}
111
112DECLINLINE(bool) msiBitJustSet(uint32_t uOldValue,
113 uint32_t uNewValue,
114 uint32_t uMask)
115{
116 return (!(uOldValue & uMask) && !!(uNewValue & uMask));
117}
118
119void MsiPciConfigWrite(PPDMDEVINS pDevIns, PCPDMPCIHLP pPciHlp, PPDMPCIDEV pDev,
120 uint32_t u32Address, uint32_t val, unsigned len)
121{
122 int32_t iOff = u32Address - pDev->Int.s.u8MsiCapOffset;
123 Assert(iOff >= 0 && (pciDevIsMsiCapable(pDev) && iOff < pDev->Int.s.u8MsiCapSize));
124
125 Log2(("MsiPciConfigWrite: %d <- %x (%d)\n", iOff, val, len));
126
127 uint32_t uAddr = u32Address;
128 bool f64Bit = msiIs64Bit(pDev);
129
130 for (uint32_t i = 0; i < len; i++)
131 {
132 uint32_t reg = i + iOff;
133 uint8_t u8Val = (uint8_t)val;
134 switch (reg)
135 {
136 case 0: /* Capability ID, ro */
137 case 1: /* Next pointer, ro */
138 break;
139 case VBOX_MSI_CAP_MESSAGE_CONTROL:
140 /* don't change read-only bits: 1-3,7 */
141 u8Val &= UINT8_C(~0x8e);
142 pDev->config[uAddr] = u8Val | (pDev->config[uAddr] & UINT8_C(0x8e));
143 break;
144 case VBOX_MSI_CAP_MESSAGE_CONTROL + 1:
145 /* don't change read-only bit 8, and reserved 9-15 */
146 break;
147 default:
148 if (pDev->config[uAddr] != u8Val)
149 {
150 int32_t maskUpdated = -1;
151
152 /* If we're enabling masked vector, and have pending messages
153 for this vector, we have to send this message now */
154 if ( !f64Bit
155 && (reg >= VBOX_MSI_CAP_MASK_BITS_32)
156 && (reg < VBOX_MSI_CAP_MASK_BITS_32 + 4)
157 )
158 {
159 maskUpdated = reg - VBOX_MSI_CAP_MASK_BITS_32;
160 }
161 if ( f64Bit
162 && (reg >= VBOX_MSI_CAP_MASK_BITS_64)
163 && (reg < VBOX_MSI_CAP_MASK_BITS_64 + 4)
164 )
165 {
166 maskUpdated = reg - VBOX_MSI_CAP_MASK_BITS_64;
167 }
168
169 if (maskUpdated != -1 && msiIsEnabled(pDev))
170 {
171 uint32_t* puPending = msiGetPendingBits(pDev);
172 for (int iBitNum = 0; iBitNum < 8; iBitNum++)
173 {
174 int32_t iBit = 1 << iBitNum;
175 uint32_t uVector = maskUpdated*8 + iBitNum;
176
177 if (msiBitJustCleared(pDev->config[uAddr], u8Val, iBit))
178 {
179 Log(("msi: mask updated bit %d@%x (%d)\n", iBitNum, uAddr, maskUpdated));
180
181 /* To ensure that we're no longer masked */
182 pDev->config[uAddr] &= ~iBit;
183 if ((*puPending & (1 << uVector)) != 0)
184 {
185 Log(("msi: notify earlier masked pending vector: %d\n", uVector));
186 MsiNotify(pDevIns, pPciHlp, pDev, uVector, PDM_IRQ_LEVEL_HIGH, 0 /*uTagSrc*/);
187 }
188 }
189 if (msiBitJustSet(pDev->config[uAddr], u8Val, iBit))
190 {
191 Log(("msi: mask vector: %d\n", uVector));
192 }
193 }
194 }
195
196 pDev->config[uAddr] = u8Val;
197 }
198 }
199 uAddr++;
200 val >>= 8;
201 }
202}
203
204uint32_t MsiPciConfigRead (PPDMDEVINS pDevIns, PPDMPCIDEV pDev, uint32_t u32Address, unsigned len)
205{
206 RT_NOREF1(pDevIns);
207#if defined(LOG_ENABLED) || defined(VBOX_STRICT)
208 int32_t off = u32Address - pDev->Int.s.u8MsiCapOffset;
209 Assert(off >= 0 && (pciDevIsMsiCapable(pDev) && off < pDev->Int.s.u8MsiCapSize));
210#endif
211 uint32_t rv = 0;
212
213 switch (len)
214 {
215 case 1:
216 rv = PCIDevGetByte(pDev, u32Address);
217 break;
218 case 2:
219 rv = PCIDevGetWord(pDev, u32Address);
220 break;
221 case 4:
222 rv = PCIDevGetDWord(pDev, u32Address);
223 break;
224 default:
225 Assert(false);
226 }
227
228 Log2(("MsiPciConfigRead: %d (%d) -> %x\n", off, len, rv));
229
230 return rv;
231}
232
233int MsiInit(PPDMPCIDEV pDev, PPDMMSIREG pMsiReg)
234{
235 if (pMsiReg->cMsiVectors == 0)
236 return VINF_SUCCESS;
237
238 /* XXX: done in pcirawAnalyzePciCaps() */
239 if (pciDevIsPassthrough(pDev))
240 return VINF_SUCCESS;
241
242 uint16_t cVectors = pMsiReg->cMsiVectors;
243 uint8_t iCapOffset = pMsiReg->iMsiCapOffset;
244 uint8_t iNextOffset = pMsiReg->iMsiNextOffset;
245 bool f64bit = pMsiReg->fMsi64bit;
246 uint16_t iFlags = 0;
247 int iMmc;
248
249 /* Compute multiple-message capable bitfield */
250 for (iMmc = 0; iMmc < 6; iMmc++)
251 {
252 if ((1 << iMmc) >= cVectors)
253 break;
254 }
255
256 if ((cVectors > VBOX_MSI_MAX_ENTRIES) || (1 << iMmc) < cVectors)
257 return VERR_TOO_MUCH_DATA;
258
259 Assert(iCapOffset != 0 && iCapOffset < 0xff && iNextOffset < 0xff);
260
261 /* We always support per-vector masking */
262 iFlags |= VBOX_PCI_MSI_FLAGS_MASKBIT | iMmc;
263 if (f64bit)
264 iFlags |= VBOX_PCI_MSI_FLAGS_64BIT;
265 /* How many vectors we're capable of */
266 iFlags |= iMmc;
267
268 pDev->Int.s.u8MsiCapOffset = iCapOffset;
269 pDev->Int.s.u8MsiCapSize = f64bit ? VBOX_MSI_CAP_SIZE_64 : VBOX_MSI_CAP_SIZE_32;
270
271 PCIDevSetByte(pDev, iCapOffset + 0, VBOX_PCI_CAP_ID_MSI);
272 PCIDevSetByte(pDev, iCapOffset + 1, iNextOffset); /* next */
273 PCIDevSetWord(pDev, iCapOffset + VBOX_MSI_CAP_MESSAGE_CONTROL, iFlags);
274
275 *msiGetMaskBits(pDev) = 0;
276 *msiGetPendingBits(pDev) = 0;
277
278 pciDevSetMsiCapable(pDev);
279
280 return VINF_SUCCESS;
281}
282
283#endif /* IN_RING3 */
284
285
286bool MsiIsEnabled(PPDMPCIDEV pDev)
287{
288 return pciDevIsMsiCapable(pDev) && msiIsEnabled(pDev);
289}
290
291void MsiNotify(PPDMDEVINS pDevIns, PCPDMPCIHLP pPciHlp, PPDMPCIDEV pDev, int iVector, int iLevel, uint32_t uTagSrc)
292{
293 AssertMsg(msiIsEnabled(pDev), ("Must be enabled to use that"));
294
295 uint32_t uMask;
296 uint32_t *puPending = msiGetPendingBits(pDev);
297 if (puPending)
298 {
299 uint32_t *puMask = msiGetMaskBits(pDev);
300 AssertPtr(puMask);
301 uMask = *puMask;
302 LogFlow(("MsiNotify: %d pending=%x mask=%x\n", iVector, *puPending, uMask));
303 }
304 else
305 {
306 uMask = 0;
307 LogFlow(("MsiNotify: %d\n", iVector));
308 }
309
310 /* We only trigger MSI on level up */
311 if ((iLevel & PDM_IRQ_LEVEL_HIGH) == 0)
312 {
313 /** @todo maybe clear pending interrupts on level down? */
314#if 0
315 if (puPending)
316 {
317 *puPending &= ~(1<<iVector);
318 LogFlow(("msi: clear pending %d, now %x\n", iVector, *puPending));
319 }
320#endif
321 return;
322 }
323
324 if ((uMask & (1<<iVector)) != 0)
325 {
326 *puPending |= (1<<iVector);
327 LogFlow(("msi: %d is masked, mark pending, now %x\n", iVector, *puPending));
328 return;
329 }
330
331 RTGCPHYS GCAddr = msiGetMsiAddress(pDev);
332 uint32_t u32Value = msiGetMsiData(pDev, iVector);
333
334 if (puPending)
335 *puPending &= ~(1<<iVector);
336
337 Assert(pPciHlp->pfnIoApicSendMsi != NULL);
338 pPciHlp->pfnIoApicSendMsi(pDevIns, GCAddr, u32Value, uTagSrc);
339}
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