VirtualBox

source: vbox/trunk/src/VBox/Devices/Bus/MsiCommon.cpp@ 90211

Last change on this file since 90211 was 84826, checked in by vboxsync, 4 years ago

AMD IOMMU: bugref:9654 PDM interface changes for supplying bus:device:function for devices' initiating PCI interrupts and MSIs.
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File size: 11.2 KB
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1/* $Id: MsiCommon.cpp 84826 2020-06-15 08:20:40Z vboxsync $ */
2/** @file
3 * MSI support routines
4 *
5 * @todo Straighten up this file!!
6 */
7
8/*
9 * Copyright (C) 2010-2020 Oracle Corporation
10 *
11 * This file is part of VirtualBox Open Source Edition (OSE), as
12 * available from http://www.virtualbox.org. This file is free software;
13 * you can redistribute it and/or modify it under the terms of the GNU
14 * General Public License (GPL) as published by the Free Software
15 * Foundation, in version 2 as it comes in the "COPYING" file of the
16 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
17 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
18 */
19
20#define LOG_GROUP LOG_GROUP_DEV_PCI
21#define PDMPCIDEV_INCLUDE_PRIVATE /* Hack to get pdmpcidevint.h included at the right point. */
22#include <VBox/pci.h>
23#include <VBox/msi.h>
24#include <VBox/vmm/pdmdev.h>
25#include <VBox/log.h>
26
27#include "MsiCommon.h"
28#include "PciInline.h"
29#include "DevPciInternal.h"
30
31
32DECLINLINE(uint16_t) msiGetMessageControl(PPDMPCIDEV pDev)
33{
34 uint32_t idxMessageControl = pDev->Int.s.u8MsiCapOffset + VBOX_MSI_CAP_MESSAGE_CONTROL;
35#ifdef IN_RING3
36 if (pciDevIsPassthrough(pDev) && pDev->Int.s.pfnConfigRead)
37 {
38 uint32_t u32Value = 0;
39 VBOXSTRICTRC rcStrict = pDev->Int.s.pfnConfigRead(pDev->Int.s.CTX_SUFF(pDevIns), pDev, idxMessageControl, 2, &u32Value);
40 AssertRCSuccess(VBOXSTRICTRC_VAL(rcStrict));
41 return (uint16_t)u32Value;
42 }
43#endif
44 return PCIDevGetWord(pDev, idxMessageControl);
45}
46
47DECLINLINE(bool) msiIs64Bit(PPDMPCIDEV pDev)
48{
49 return pciDevIsMsi64Capable(pDev);
50}
51
52/** @todo r=klaus This design assumes that the config space cache is always
53 * up to date, which is a wrong assumption for the "emulate passthrough" case
54 * where only the callbacks give the correct data. */
55DECLINLINE(uint32_t *) msiGetMaskBits(PPDMPCIDEV pDev)
56{
57 uint8_t iOff = msiIs64Bit(pDev) ? VBOX_MSI_CAP_MASK_BITS_64 : VBOX_MSI_CAP_MASK_BITS_32;
58 /* devices may have no masked/pending support */
59 if (iOff >= pDev->Int.s.u8MsiCapSize)
60 return NULL;
61 iOff += pDev->Int.s.u8MsiCapOffset;
62 return (uint32_t*)(pDev->abConfig + iOff);
63}
64
65/** @todo r=klaus This design assumes that the config space cache is always
66 * up to date, which is a wrong assumption for the "emulate passthrough" case
67 * where only the callbacks give the correct data. */
68DECLINLINE(uint32_t*) msiGetPendingBits(PPDMPCIDEV pDev)
69{
70 uint8_t iOff = msiIs64Bit(pDev) ? VBOX_MSI_CAP_PENDING_BITS_64 : VBOX_MSI_CAP_PENDING_BITS_32;
71 /* devices may have no masked/pending support */
72 if (iOff >= pDev->Int.s.u8MsiCapSize)
73 return NULL;
74 iOff += pDev->Int.s.u8MsiCapOffset;
75 return (uint32_t*)(pDev->abConfig + iOff);
76}
77
78DECLINLINE(bool) msiIsEnabled(PPDMPCIDEV pDev)
79{
80 return (msiGetMessageControl(pDev) & VBOX_PCI_MSI_FLAGS_ENABLE) != 0;
81}
82
83DECLINLINE(uint8_t) msiGetMme(PPDMPCIDEV pDev)
84{
85 return (msiGetMessageControl(pDev) & VBOX_PCI_MSI_FLAGS_QSIZE) >> 4;
86}
87
88DECLINLINE(RTGCPHYS) msiGetMsiAddress(PPDMPCIDEV pDev)
89{
90 if (msiIs64Bit(pDev))
91 {
92 uint32_t lo = PCIDevGetDWord(pDev, pDev->Int.s.u8MsiCapOffset + VBOX_MSI_CAP_MESSAGE_ADDRESS_LO);
93 uint32_t hi = PCIDevGetDWord(pDev, pDev->Int.s.u8MsiCapOffset + VBOX_MSI_CAP_MESSAGE_ADDRESS_HI);
94 return RT_MAKE_U64(lo, hi);
95 }
96 return PCIDevGetDWord(pDev, pDev->Int.s.u8MsiCapOffset + VBOX_MSI_CAP_MESSAGE_ADDRESS_32);
97}
98
99DECLINLINE(uint32_t) msiGetMsiData(PPDMPCIDEV pDev, int32_t iVector)
100{
101 int16_t iOff = msiIs64Bit(pDev) ? VBOX_MSI_CAP_MESSAGE_DATA_64 : VBOX_MSI_CAP_MESSAGE_DATA_32;
102 uint16_t lo = PCIDevGetWord(pDev, pDev->Int.s.u8MsiCapOffset + iOff);
103
104 // vector encoding into lower bits of message data
105 uint8_t bits = msiGetMme(pDev);
106 uint16_t uMask = ((1 << bits) - 1);
107 lo &= ~uMask;
108 lo |= iVector & uMask;
109
110 return RT_MAKE_U32(lo, 0);
111}
112
113#ifdef IN_RING3
114
115DECLINLINE(bool) msiR3BitJustCleared(uint32_t uOldValue, uint32_t uNewValue, uint32_t uMask)
116{
117 return !!(uOldValue & uMask) && !(uNewValue & uMask);
118}
119
120DECLINLINE(bool) msiR3BitJustSet(uint32_t uOldValue, uint32_t uNewValue, uint32_t uMask)
121{
122 return !(uOldValue & uMask) && !!(uNewValue & uMask);
123}
124
125/**
126 * PCI config space accessors for MSI registers.
127 */
128void MsiR3PciConfigWrite(PPDMDEVINS pDevIns, PCPDMPCIHLP pPciHlp, PPDMPCIDEV pDev,
129 uint32_t u32Address, uint32_t val, unsigned len)
130{
131 int32_t iOff = u32Address - pDev->Int.s.u8MsiCapOffset;
132 Assert(iOff >= 0 && (pciDevIsMsiCapable(pDev) && iOff < pDev->Int.s.u8MsiCapSize));
133
134 Log2(("MsiR3PciConfigWrite: %d <- %x (%d)\n", iOff, val, len));
135
136 uint32_t uAddr = u32Address;
137 bool f64Bit = msiIs64Bit(pDev);
138
139 for (uint32_t i = 0; i < len; i++)
140 {
141 uint32_t reg = i + iOff;
142 uint8_t u8Val = (uint8_t)val;
143 switch (reg)
144 {
145 case 0: /* Capability ID, ro */
146 case 1: /* Next pointer, ro */
147 break;
148 case VBOX_MSI_CAP_MESSAGE_CONTROL:
149 /* don't change read-only bits: 1-3,7 */
150 u8Val &= UINT8_C(~0x8e);
151 pDev->abConfig[uAddr] = u8Val | (pDev->abConfig[uAddr] & UINT8_C(0x8e));
152 break;
153 case VBOX_MSI_CAP_MESSAGE_CONTROL + 1:
154 /* don't change read-only bit 8, and reserved 9-15 */
155 break;
156 default:
157 if (pDev->abConfig[uAddr] != u8Val)
158 {
159 int32_t maskUpdated = -1;
160
161 /* If we're enabling masked vector, and have pending messages
162 for this vector, we have to send this message now */
163 if ( !f64Bit
164 && (reg >= VBOX_MSI_CAP_MASK_BITS_32)
165 && (reg < VBOX_MSI_CAP_MASK_BITS_32 + 4)
166 )
167 {
168 maskUpdated = reg - VBOX_MSI_CAP_MASK_BITS_32;
169 }
170 if ( f64Bit
171 && (reg >= VBOX_MSI_CAP_MASK_BITS_64)
172 && (reg < VBOX_MSI_CAP_MASK_BITS_64 + 4)
173 )
174 {
175 maskUpdated = reg - VBOX_MSI_CAP_MASK_BITS_64;
176 }
177
178 if (maskUpdated != -1 && msiIsEnabled(pDev))
179 {
180 uint32_t* puPending = msiGetPendingBits(pDev);
181 for (int iBitNum = 0; iBitNum < 8; iBitNum++)
182 {
183 int32_t iBit = 1 << iBitNum;
184 uint32_t uVector = maskUpdated*8 + iBitNum;
185
186 if (msiR3BitJustCleared(pDev->abConfig[uAddr], u8Val, iBit))
187 {
188 Log(("msi: mask updated bit %d@%x (%d)\n", iBitNum, uAddr, maskUpdated));
189
190 /* To ensure that we're no longer masked */
191 pDev->abConfig[uAddr] &= ~iBit;
192 if ((*puPending & (1 << uVector)) != 0)
193 {
194 Log(("msi: notify earlier masked pending vector: %d\n", uVector));
195 MsiNotify(pDevIns, pPciHlp, pDev, uVector, PDM_IRQ_LEVEL_HIGH, 0 /*uTagSrc*/);
196 }
197 }
198 if (msiR3BitJustSet(pDev->abConfig[uAddr], u8Val, iBit))
199 {
200 Log(("msi: mask vector: %d\n", uVector));
201 }
202 }
203 }
204
205 pDev->abConfig[uAddr] = u8Val;
206 }
207 }
208 uAddr++;
209 val >>= 8;
210 }
211}
212
213/**
214 * Initializes MSI support for the given PCI device.
215 */
216int MsiR3Init(PPDMPCIDEV pDev, PPDMMSIREG pMsiReg)
217{
218 if (pMsiReg->cMsiVectors == 0)
219 return VINF_SUCCESS;
220
221 /* XXX: done in pcirawAnalyzePciCaps() */
222 if (pciDevIsPassthrough(pDev))
223 return VINF_SUCCESS;
224
225 uint16_t cVectors = pMsiReg->cMsiVectors;
226 uint8_t iCapOffset = pMsiReg->iMsiCapOffset;
227 uint8_t iNextOffset = pMsiReg->iMsiNextOffset;
228 bool f64bit = pMsiReg->fMsi64bit;
229 bool fNoMasking = pMsiReg->fMsiNoMasking;
230 uint16_t iFlags = 0;
231
232 Assert(iCapOffset != 0 && iCapOffset < 0xff && iNextOffset < 0xff);
233
234 if (!fNoMasking)
235 {
236 int iMmc;
237
238 /* Compute multiple-message capable bitfield */
239 for (iMmc = 0; iMmc < 6; iMmc++)
240 {
241 if ((1 << iMmc) >= cVectors)
242 break;
243 }
244
245 if ((cVectors > VBOX_MSI_MAX_ENTRIES) || (1 << iMmc) < cVectors)
246 return VERR_TOO_MUCH_DATA;
247
248 /* We support per-vector masking */
249 iFlags |= VBOX_PCI_MSI_FLAGS_MASKBIT;
250 /* How many vectors we're capable of */
251 iFlags |= iMmc;
252 }
253
254 if (f64bit)
255 iFlags |= VBOX_PCI_MSI_FLAGS_64BIT;
256
257 pDev->Int.s.u8MsiCapOffset = iCapOffset;
258 pDev->Int.s.u8MsiCapSize = f64bit ? VBOX_MSI_CAP_SIZE_64 : VBOX_MSI_CAP_SIZE_32;
259
260 PCIDevSetByte(pDev, iCapOffset + 0, VBOX_PCI_CAP_ID_MSI);
261 PCIDevSetByte(pDev, iCapOffset + 1, iNextOffset); /* next */
262 PCIDevSetWord(pDev, iCapOffset + VBOX_MSI_CAP_MESSAGE_CONTROL, iFlags);
263
264 if (!fNoMasking)
265 {
266 *msiGetMaskBits(pDev) = 0;
267 *msiGetPendingBits(pDev) = 0;
268 }
269
270 pciDevSetMsiCapable(pDev);
271 if (f64bit)
272 pciDevSetMsi64Capable(pDev);
273
274 return VINF_SUCCESS;
275}
276
277#endif /* IN_RING3 */
278
279
280/**
281 * Checks if MSI is enabled for the given PCI device.
282 *
283 * (Must use MSINotify() for notifications when true.)
284 */
285bool MsiIsEnabled(PPDMPCIDEV pDev)
286{
287 return pciDevIsMsiCapable(pDev) && msiIsEnabled(pDev);
288}
289
290/**
291 * Device notification (aka interrupt).
292 */
293void MsiNotify(PPDMDEVINS pDevIns, PCPDMPCIHLP pPciHlp, PPDMPCIDEV pDev, int iVector, int iLevel, uint32_t uTagSrc)
294{
295 AssertMsg(msiIsEnabled(pDev), ("Must be enabled to use that"));
296
297 uint32_t uMask;
298 uint32_t *puPending = msiGetPendingBits(pDev);
299 if (puPending)
300 {
301 uint32_t *puMask = msiGetMaskBits(pDev);
302 AssertPtr(puMask);
303 uMask = *puMask;
304 LogFlow(("MsiNotify: %d pending=%x mask=%x\n", iVector, *puPending, uMask));
305 }
306 else
307 {
308 uMask = 0;
309 LogFlow(("MsiNotify: %d\n", iVector));
310 }
311
312 /* We only trigger MSI on level up */
313 if ((iLevel & PDM_IRQ_LEVEL_HIGH) == 0)
314 {
315 /** @todo maybe clear pending interrupts on level down? */
316#if 0
317 if (puPending)
318 {
319 *puPending &= ~(1<<iVector);
320 LogFlow(("msi: clear pending %d, now %x\n", iVector, *puPending));
321 }
322#endif
323 return;
324 }
325
326 if ((uMask & (1<<iVector)) != 0)
327 {
328 *puPending |= (1<<iVector);
329 LogFlow(("msi: %d is masked, mark pending, now %x\n", iVector, *puPending));
330 return;
331 }
332
333 MSIMSG Msi;
334 Msi.Addr.u64 = msiGetMsiAddress(pDev);
335 Msi.Data.u32 = msiGetMsiData(pDev, iVector);
336
337 if (puPending)
338 *puPending &= ~(1<<iVector);
339
340 PPDMDEVINS pDevInsBus = pPciHlp->pfnGetBusByNo(pDevIns, pDev->Int.s.idxPdmBus);
341 Assert(pDevInsBus);
342 PDEVPCIBUS pBus = PDMINS_2_DATA(pDevInsBus, PDEVPCIBUS);
343 uint16_t const uBusDevFn = PCIBDF_MAKE(pBus->iBus, pDev->uDevFn);
344
345 Assert(pPciHlp->pfnIoApicSendMsi != NULL);
346 pPciHlp->pfnIoApicSendMsi(pDevIns, uBusDevFn, &Msi, uTagSrc);
347}
348
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