1 | /* $Id: MsixCommon.cpp 71773 2018-04-09 14:35:02Z vboxsync $ */
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2 | /** @file
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3 | * MSI-X support routines
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4 | */
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5 |
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6 | /*
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7 | * Copyright (C) 2010-2017 Oracle Corporation
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8 | *
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9 | * This file is part of VirtualBox Open Source Edition (OSE), as
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10 | * available from http://www.virtualbox.org. This file is free software;
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11 | * you can redistribute it and/or modify it under the terms of the GNU
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12 | * General Public License (GPL) as published by the Free Software
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13 | * Foundation, in version 2 as it comes in the "COPYING" file of the
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14 | * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
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15 | * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
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16 | */
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17 |
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18 |
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19 | #define LOG_GROUP LOG_GROUP_DEV_PCI
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20 | #define PDMPCIDEV_INCLUDE_PRIVATE /* Hack to get pdmpcidevint.h included at the right point. */
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21 | #include <VBox/pci.h>
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22 | #include <VBox/msi.h>
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23 | #include <VBox/vmm/pdmdev.h>
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24 | #include <VBox/log.h>
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25 | #include <VBox/vmm/mm.h>
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26 |
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27 | #include <iprt/assert.h>
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28 |
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29 | #include "MsiCommon.h"
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30 | #include "PciInline.h"
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31 |
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32 | typedef struct
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33 | {
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34 | uint32_t u32MsgAddressLo;
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35 | uint32_t u32MsgAddressHi;
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36 | uint32_t u32MsgData;
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37 | uint32_t u32VectorControl;
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38 | } MsixTableRecord;
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39 | AssertCompileSize(MsixTableRecord, VBOX_MSIX_ENTRY_SIZE);
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40 |
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41 |
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42 | /** @todo use accessors so that raw PCI devices work correctly with MSI-X. */
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43 | DECLINLINE(uint16_t) msixGetMessageControl(PPDMPCIDEV pDev)
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44 | {
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45 | return PCIDevGetWord(pDev, pDev->Int.s.u8MsixCapOffset + VBOX_MSIX_CAP_MESSAGE_CONTROL);
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46 | }
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47 |
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48 | DECLINLINE(bool) msixIsEnabled(PPDMPCIDEV pDev)
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49 | {
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50 | return (msixGetMessageControl(pDev) & VBOX_PCI_MSIX_FLAGS_ENABLE) != 0;
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51 | }
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52 |
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53 | DECLINLINE(bool) msixIsMasked(PPDMPCIDEV pDev)
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54 | {
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55 | return (msixGetMessageControl(pDev) & VBOX_PCI_MSIX_FLAGS_FUNCMASK) != 0;
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56 | }
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57 |
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58 | #ifdef IN_RING3
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59 | DECLINLINE(uint16_t) msixTableSize(PPDMPCIDEV pDev)
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60 | {
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61 | return (msixGetMessageControl(pDev) & 0x3ff) + 1;
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62 | }
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63 | #endif
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64 |
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65 | DECLINLINE(uint8_t *) msixGetPageOffset(PPDMPCIDEV pDev, uint32_t off)
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66 | {
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67 | return (uint8_t *)pDev->Int.s.CTX_SUFF(pMsixPage) + off;
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68 | }
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69 |
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70 | DECLINLINE(MsixTableRecord *) msixGetVectorRecord(PPDMPCIDEV pDev, uint32_t iVector)
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71 | {
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72 | return (MsixTableRecord *)msixGetPageOffset(pDev, iVector * VBOX_MSIX_ENTRY_SIZE);
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73 | }
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74 |
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75 | DECLINLINE(RTGCPHYS) msixGetMsiAddress(PPDMPCIDEV pDev, uint32_t iVector)
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76 | {
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77 | MsixTableRecord *pRec = msixGetVectorRecord(pDev, iVector);
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78 | return RT_MAKE_U64(pRec->u32MsgAddressLo & ~UINT32_C(0x3), pRec->u32MsgAddressHi);
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79 | }
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80 |
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81 | DECLINLINE(uint32_t) msixGetMsiData(PPDMPCIDEV pDev, uint32_t iVector)
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82 | {
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83 | return msixGetVectorRecord(pDev, iVector)->u32MsgData;
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84 | }
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85 |
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86 | DECLINLINE(uint32_t) msixIsVectorMasked(PPDMPCIDEV pDev, uint32_t iVector)
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87 | {
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88 | return (msixGetVectorRecord(pDev, iVector)->u32VectorControl & 0x1) != 0;
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89 | }
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90 |
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91 | DECLINLINE(uint8_t *) msixPendingByte(PPDMPCIDEV pDev, uint32_t iVector)
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92 | {
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93 | return msixGetPageOffset(pDev, pDev->Int.s.offMsixPba + iVector / 8);
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94 | }
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95 |
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96 | DECLINLINE(void) msixSetPending(PPDMPCIDEV pDev, uint32_t iVector)
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97 | {
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98 | *msixPendingByte(pDev, iVector) |= (1 << (iVector & 0x7));
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99 | }
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100 |
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101 | DECLINLINE(void) msixClearPending(PPDMPCIDEV pDev, uint32_t iVector)
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102 | {
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103 | *msixPendingByte(pDev, iVector) &= ~(1 << (iVector & 0x7));
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104 | }
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105 |
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106 | #ifdef IN_RING3
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107 |
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108 | DECLINLINE(bool) msixR3IsPending(PPDMPCIDEV pDev, uint32_t iVector)
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109 | {
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110 | return (*msixPendingByte(pDev, iVector) & (1 << (iVector & 0x7))) != 0;
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111 | }
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112 |
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113 | static void msixR3CheckPendingVector(PPDMDEVINS pDevIns, PCPDMPCIHLP pPciHlp, PPDMPCIDEV pDev, uint32_t iVector)
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114 | {
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115 | if (msixR3IsPending(pDev, iVector) && !msixIsVectorMasked(pDev, iVector))
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116 | MsixNotify(pDevIns, pPciHlp, pDev, iVector, 1 /* iLevel */, 0 /*uTagSrc*/);
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117 | }
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118 |
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119 |
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120 | PDMBOTHCBDECL(int) msixR3MMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
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121 | {
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122 | LogFlowFunc(("\n"));
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123 |
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124 | uint32_t off = (uint32_t)(GCPhysAddr & 0xffff);
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125 | PPDMPCIDEV pPciDev = (PPDMPCIDEV)pvUser;
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126 |
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127 | /// @todo qword accesses?
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128 | RT_NOREF(pDevIns);
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129 | AssertMsgReturn(cb == 4,
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130 | ("MSI-X must be accessed with 4-byte reads"),
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131 | VERR_INTERNAL_ERROR);
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132 | AssertMsgReturn(off + cb <= pPciDev->Int.s.cbMsixRegion,
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133 | ("Out of bounds access for the MSI-X region\n"),
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134 | VINF_IOM_MMIO_UNUSED_FF);
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135 |
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136 | *(uint32_t *)pv = *(uint32_t *)msixGetPageOffset(pPciDev, off);
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137 | return VINF_SUCCESS;
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138 | }
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139 |
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140 | PDMBOTHCBDECL(int) msixR3MMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void const *pv, unsigned cb)
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141 | {
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142 | LogFlowFunc(("\n"));
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143 |
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144 | PPDMPCIDEV pPciDev = (PPDMPCIDEV)pvUser;
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145 | uint32_t off = (uint32_t)(GCPhysAddr & 0xffff);
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146 |
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147 | /// @todo qword accesses?
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148 | AssertMsgReturn(cb == 4,
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149 | ("MSI-X must be accessed with 4-byte reads"),
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150 | VERR_INTERNAL_ERROR);
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151 | AssertMsgReturn(off + cb <= pPciDev->Int.s.offMsixPba,
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152 | ("Trying to write to PBA\n"), VINF_SUCCESS);
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153 |
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154 | *(uint32_t *)msixGetPageOffset(pPciDev, off) = *(uint32_t *)pv;
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155 |
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156 | msixR3CheckPendingVector(pDevIns, (PCPDMPCIHLP)pPciDev->Int.s.pPciBusPtrR3, pPciDev, off / VBOX_MSIX_ENTRY_SIZE);
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157 | return VINF_SUCCESS;
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158 | }
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159 |
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160 | /**
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161 | * @callback_method_impl{FNPCIIOREGIONMAP}
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162 | */
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163 | static DECLCALLBACK(int) msixR3Map(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
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164 | RTGCPHYS GCPhysAddress, RTGCPHYS cb, PCIADDRESSSPACE enmType)
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165 | {
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166 | Assert(enmType == PCI_ADDRESS_SPACE_MEM);
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167 | NOREF(iRegion); NOREF(enmType);
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168 |
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169 | int rc = PDMDevHlpMMIORegister(pDevIns, GCPhysAddress, cb, pPciDev,
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170 | IOMMMIO_FLAGS_READ_PASSTHRU | IOMMMIO_FLAGS_WRITE_PASSTHRU,
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171 | msixR3MMIOWrite, msixR3MMIORead, "MSI-X tables");
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172 |
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173 | if (RT_FAILURE(rc))
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174 | return rc;
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175 |
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176 | return VINF_SUCCESS;
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177 | }
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178 |
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179 | /**
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180 | * Initalizes MSI-X support for the given PCI device.
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181 | */
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182 | int MsixR3Init(PCPDMPCIHLP pPciHlp, PPDMPCIDEV pDev, PPDMMSIREG pMsiReg)
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183 | {
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184 | if (pMsiReg->cMsixVectors == 0)
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185 | return VINF_SUCCESS;
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186 |
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187 | /* We cannot init MSI-X on raw devices yet. */
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188 | Assert(!pciDevIsPassthrough(pDev));
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189 |
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190 | uint16_t cVectors = pMsiReg->cMsixVectors;
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191 | uint8_t iCapOffset = pMsiReg->iMsixCapOffset;
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192 | uint8_t iNextOffset = pMsiReg->iMsixNextOffset;
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193 | uint8_t iBar = pMsiReg->iMsixBar;
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194 |
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195 | AssertMsgReturn(cVectors <= VBOX_MSIX_MAX_ENTRIES,
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196 | ("Too many MSI-X vectors: %d\n", cVectors),
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197 | VERR_TOO_MUCH_DATA);
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198 | AssertMsgReturn(iBar <= 5,
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199 | ("Using wrong BAR for MSI-X: %d\n", iBar),
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200 | VERR_INVALID_PARAMETER);
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201 |
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202 | Assert(iCapOffset != 0 && iCapOffset < 0xff && iNextOffset < 0xff);
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203 |
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204 | int rc = VINF_SUCCESS;
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205 | uint16_t cbPba = cVectors / 8;
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206 | if (cVectors % 8)
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207 | cbPba++;
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208 | uint16_t cbMsixRegion = RT_ALIGN_T(cVectors * sizeof(MsixTableRecord) + cbPba, _4K, uint16_t);
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209 |
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210 | /* If device is passthrough, BAR is registered using common mechanism. */
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211 | if (!pciDevIsPassthrough(pDev))
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212 | {
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213 | rc = PDMDevHlpPCIIORegionRegister(pDev->Int.s.CTX_SUFF(pDevIns), iBar, cbMsixRegion, PCI_ADDRESS_SPACE_MEM, msixR3Map);
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214 | if (RT_FAILURE (rc))
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215 | return rc;
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216 | }
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217 |
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218 | uint16_t offTable = 0;
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219 | uint16_t offPBA = cVectors * sizeof(MsixTableRecord);
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220 |
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221 | pDev->Int.s.u8MsixCapOffset = iCapOffset;
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222 | pDev->Int.s.u8MsixCapSize = VBOX_MSIX_CAP_SIZE;
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223 | pDev->Int.s.cbMsixRegion = cbMsixRegion;
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224 | pDev->Int.s.offMsixPba = offPBA;
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225 | PVM pVM = PDMDevHlpGetVM(pDev->Int.s.CTX_SUFF(pDevIns));
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226 |
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227 | pDev->Int.s.pMsixPageR3 = NULL;
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228 |
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229 | rc = MMHyperAlloc(pVM, cbMsixRegion, 1, MM_TAG_PDM_DEVICE_USER, (void **)&pDev->Int.s.pMsixPageR3);
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230 | if (RT_FAILURE(rc) || (pDev->Int.s.pMsixPageR3 == NULL))
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231 | return VERR_NO_VM_MEMORY;
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232 | RT_BZERO(pDev->Int.s.pMsixPageR3, cbMsixRegion);
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233 | pDev->Int.s.pMsixPageR0 = MMHyperR3ToR0(pVM, pDev->Int.s.pMsixPageR3);
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234 | pDev->Int.s.pMsixPageRC = MMHyperR3ToRC(pVM, pDev->Int.s.pMsixPageR3);
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235 |
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236 | /* R3 PCI helper */
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237 | pDev->Int.s.pPciBusPtrR3 = pPciHlp;
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238 |
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239 | PCIDevSetByte(pDev, iCapOffset + 0, VBOX_PCI_CAP_ID_MSIX);
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240 | PCIDevSetByte(pDev, iCapOffset + 1, iNextOffset); /* next */
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241 | PCIDevSetWord(pDev, iCapOffset + VBOX_MSIX_CAP_MESSAGE_CONTROL, cVectors - 1);
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242 |
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243 | PCIDevSetDWord(pDev, iCapOffset + VBOX_MSIX_TABLE_BIROFFSET, offTable | iBar);
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244 | PCIDevSetDWord(pDev, iCapOffset + VBOX_MSIX_PBA_BIROFFSET, offPBA | iBar);
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245 |
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246 | pciDevSetMsixCapable(pDev);
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247 |
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248 | return VINF_SUCCESS;
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249 | }
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250 |
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251 | #endif /* IN_RING3 */
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252 |
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253 | /**
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254 | * Checks if MSI-X is enabled for the tiven PCI device.
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255 | *
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256 | * (Must use MSIXNotify() for notifications when true.)
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257 | */
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258 | bool MsixIsEnabled(PPDMPCIDEV pDev)
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259 | {
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260 | return pciDevIsMsixCapable(pDev) && msixIsEnabled(pDev);
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261 | }
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262 |
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263 | /**
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264 | * Device notification (aka interrupt).
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265 | */
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266 | void MsixNotify(PPDMDEVINS pDevIns, PCPDMPCIHLP pPciHlp, PPDMPCIDEV pDev, int iVector, int iLevel, uint32_t uTagSrc)
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267 | {
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268 | AssertMsg(msixIsEnabled(pDev), ("Must be enabled to use that"));
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269 |
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270 | Assert(pPciHlp->pfnIoApicSendMsi != NULL);
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271 |
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272 | /* We only trigger MSI-X on level up */
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273 | if ((iLevel & PDM_IRQ_LEVEL_HIGH) == 0)
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274 | {
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275 | return;
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276 | }
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277 |
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278 | // if this vector is somehow disabled
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279 | if (msixIsMasked(pDev) || msixIsVectorMasked(pDev, iVector))
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280 | {
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281 | // mark pending bit
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282 | msixSetPending(pDev, iVector);
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283 | return;
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284 | }
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285 |
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286 | // clear pending bit
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287 | msixClearPending(pDev, iVector);
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288 |
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289 | RTGCPHYS GCAddr = msixGetMsiAddress(pDev, iVector);
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290 | uint32_t u32Value = msixGetMsiData(pDev, iVector);
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291 |
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292 | pPciHlp->pfnIoApicSendMsi(pDevIns, GCAddr, u32Value, uTagSrc);
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293 | }
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294 |
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295 | #ifdef IN_RING3
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296 |
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297 | DECLINLINE(bool) msixR3BitJustCleared(uint32_t uOldValue, uint32_t uNewValue, uint32_t uMask)
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298 | {
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299 | return !!(uOldValue & uMask) && !(uNewValue & uMask);
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300 | }
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301 |
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302 |
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303 | static void msixR3CheckPendingVectors(PPDMDEVINS pDevIns, PCPDMPCIHLP pPciHlp, PPDMPCIDEV pDev)
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304 | {
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305 | for (uint32_t i = 0; i < msixTableSize(pDev); i++)
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306 | msixR3CheckPendingVector(pDevIns, pPciHlp, pDev, i);
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307 | }
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308 |
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309 | /**
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310 | * PCI config space accessors for MSI-X.
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311 | */
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312 | void MsixR3PciConfigWrite(PPDMDEVINS pDevIns, PCPDMPCIHLP pPciHlp, PPDMPCIDEV pDev, uint32_t u32Address, uint32_t val, unsigned len)
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313 | {
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314 | int32_t iOff = u32Address - pDev->Int.s.u8MsixCapOffset;
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315 | Assert(iOff >= 0 && (pciDevIsMsixCapable(pDev) && iOff < pDev->Int.s.u8MsixCapSize));
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316 |
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317 | Log2(("MsixR3PciConfigWrite: %d <- %x (%d)\n", iOff, val, len));
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318 |
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319 | uint32_t uAddr = u32Address;
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320 | uint8_t u8NewVal;
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321 | bool fJustEnabled = false;
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322 |
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323 | for (uint32_t i = 0; i < len; i++)
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324 | {
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325 | uint32_t reg = i + iOff;
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326 | uint8_t u8Val = (uint8_t)val;
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327 | switch (reg)
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328 | {
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329 | case 0: /* Capability ID, ro */
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330 | case 1: /* Next pointer, ro */
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331 | break;
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332 | case VBOX_MSIX_CAP_MESSAGE_CONTROL:
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333 | /* don't change read-only bits: 0-7 */
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334 | break;
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335 | case VBOX_MSIX_CAP_MESSAGE_CONTROL + 1:
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336 | {
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337 | /* don't change read-only bits 8-13 */
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338 | u8NewVal = (u8Val & UINT8_C(~0x3f)) | (pDev->abConfig[uAddr] & UINT8_C(0x3f));
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339 | /* If just enabled globally - check pending vectors */
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340 | fJustEnabled |= msixR3BitJustCleared(pDev->abConfig[uAddr], u8NewVal, VBOX_PCI_MSIX_FLAGS_ENABLE >> 8);
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341 | fJustEnabled |= msixR3BitJustCleared(pDev->abConfig[uAddr], u8NewVal, VBOX_PCI_MSIX_FLAGS_FUNCMASK >> 8);
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342 | pDev->abConfig[uAddr] = u8NewVal;
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343 | break;
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344 | }
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345 | default:
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346 | /* other fields read-only too */
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347 | break;
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348 | }
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349 | uAddr++;
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350 | val >>= 8;
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351 | }
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352 |
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353 | if (fJustEnabled)
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354 | msixR3CheckPendingVectors(pDevIns, pPciHlp, pDev);
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355 | }
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356 |
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357 | #endif /* IN_RING3 */
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