| 1 | /* $Id: PCIInternal.h 13217 2008-10-13 13:40:54Z vboxsync $ */
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| 2 | /** @file
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| 3 | * DevPCI - PCI Internal header - Only for hiding bits of PCIDEVICE.
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| 4 | */
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| 5 |
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| 6 | /*
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| 7 | * Copyright (C) 2006-2007 Sun Microsystems, Inc.
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| 8 | *
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| 9 | * This file is part of VirtualBox Open Source Edition (OSE), as
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| 10 | * available from http://www.virtualbox.org. This file is free software;
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| 11 | * you can redistribute it and/or modify it under the terms of the GNU
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| 12 | * General Public License (GPL) as published by the Free Software
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| 13 | * Foundation, in version 2 as it comes in the "COPYING" file of the
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| 14 | * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
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| 15 | * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
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| 16 | *
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| 17 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
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| 18 | * Clara, CA 95054 USA or visit http://www.sun.com if you need
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| 19 | * additional information or have any questions.
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| 20 | */
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| 21 |
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| 22 | #ifndef __PCIInternal_h__
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| 23 | #define __PCIInternal_h__
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| 24 |
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| 25 | /**
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| 26 | * PCI I/O region.
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| 27 | */
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| 28 | typedef struct PCIIOREGION
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| 29 | {
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| 30 | /** Current PCI mapping address.
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| 31 | * -1 means not mapped. Memory addresses are relative to pci_mem_base. */
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| 32 | uint32_t addr;
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| 33 | uint32_t size;
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| 34 | uint8_t type; /* PCIADDRESSSPACE */
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| 35 | uint8_t padding[HC_ARCH_BITS == 32 ? 3 : 7];
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| 36 | /** Callback called when the region is mapped. */
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| 37 | R3PTRTYPE(PFNPCIIOREGIONMAP) map_func;
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| 38 | } PCIIOREGION, PCIIORegion;
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| 39 | /** Pointer to PCI I/O region. */
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| 40 | typedef PCIIOREGION *PPCIIOREGION;
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| 41 |
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| 42 | /**
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| 43 | * Callback function for reading from the PCI configuration space.
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| 44 | *
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| 45 | * @returns The register value.
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| 46 | * @param pDevIns Pointer to the device instance of the PCI bus.
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| 47 | * @param iBus The bus number this device is on.
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| 48 | * @param iDevice The number of the device on the bus.
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| 49 | * @param Address The configuration space register address. [0..255]
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| 50 | * @param cb The register size. [1,2,4]
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| 51 | */
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| 52 | typedef DECLCALLBACK(uint32_t) FNPCIBRIDGECONFIGREAD(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice, uint32_t u32Address, unsigned cb);
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| 53 | /** Pointer to a FNPCICONFIGREAD() function. */
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| 54 | typedef FNPCIBRIDGECONFIGREAD *PFNPCIBRIDGECONFIGREAD;
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| 55 | /** Pointer to a PFNPCICONFIGREAD. */
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| 56 | typedef PFNPCIBRIDGECONFIGREAD *PPFNPCIBRIDGECONFIGREAD;
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| 57 |
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| 58 | /**
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| 59 | * Callback function for writing to the PCI configuration space.
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| 60 | *
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| 61 | * @param pDevIns Pointer to the device instance of the PCI bus.
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| 62 | * @param iBus The bus number this device is on.
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| 63 | * @param iDevice The number of the device on the bus.
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| 64 | * @param Address The configuration space register address. [0..255]
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| 65 | * @param u32Value The value that's being written. The number of bits actually used from
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| 66 | * this value is determined by the cb parameter.
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| 67 | * @param cb The register size. [1,2,4]
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| 68 | */
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| 69 | typedef DECLCALLBACK(void) FNPCIBRIDGECONFIGWRITE(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice, uint32_t u32Address, uint32_t u32Value, unsigned cb);
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| 70 | /** Pointer to a FNPCICONFIGWRITE() function. */
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| 71 | typedef FNPCIBRIDGECONFIGWRITE *PFNPCIBRIDGECONFIGWRITE;
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| 72 | /** Pointer to a PFNPCICONFIGWRITE. */
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| 73 | typedef PFNPCIBRIDGECONFIGWRITE *PPFNPCIBRIDGECONFIGWRITE;
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| 74 |
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| 75 | /**
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| 76 | * PCI Device - Internal data.
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| 77 | */
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| 78 | typedef struct PCIDEVICEINT
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| 79 | {
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| 80 | /** I/O regions. */
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| 81 | PCIIOREGION aIORegions[PCI_NUM_REGIONS];
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| 82 | /** Pointer to the PCI bus of the device. - R3 ptr */
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| 83 | R3PTRTYPE(struct PCIBus *) pBusR3;
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| 84 | /** Pointer to the PCI bus of the device. - R0 ptr */
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| 85 | R0PTRTYPE(struct PCIBus *) pBusR0;
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| 86 | /** Pointer to the PCI bus of the device. - RC ptr */
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| 87 | RCPTRTYPE(struct PCIBus *) pBusRC;
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| 88 | #if HC_ARCH_BITS == 64
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| 89 | RTRCPTR Alignment0;
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| 90 | #endif
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| 91 |
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| 92 | /** Read config callback. */
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| 93 | R3PTRTYPE(PFNPCICONFIGREAD) pfnConfigRead;
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| 94 | /** Write config callback. */
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| 95 | R3PTRTYPE(PFNPCICONFIGWRITE) pfnConfigWrite;
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| 96 |
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| 97 | /** Set if the specific device fun was requested by PDM.
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| 98 | * If clear the device and it's functions can be relocated to satisfy the slot request of another device. */
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| 99 | bool fRequestedDevFn;
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| 100 | /** Flag whether the device is a pci-to-pci bridge. */
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| 101 | bool fPciToPciBridge;
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| 102 | /** Current state of the IRQ pin of the device. */
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| 103 | int32_t uIrqPinState;
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| 104 |
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| 105 | /** Read config callback for PCI bridges to pass requests
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| 106 | * to devices on another bus.
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| 107 | */
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| 108 | R3PTRTYPE(PFNPCIBRIDGECONFIGREAD) pfnBridgeConfigRead;
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| 109 | /** Write config callback for PCI bridges to pass requests
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| 110 | * to devices on another bus.
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| 111 | */
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| 112 | R3PTRTYPE(PFNPCIBRIDGECONFIGWRITE) pfnBridgeConfigWrite;
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| 113 |
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| 114 | } PCIDEVICEINT;
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| 115 |
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| 116 | /* Indicate that PCIDEVICE::Int.s can be declared. */
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| 117 | #define __PCIDEVICEINT_DECLARED__
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| 118 |
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| 119 | #endif
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