VirtualBox

source: vbox/trunk/src/VBox/Devices/Bus/PCIInternal.h@ 49435

Last change on this file since 49435 was 44528, checked in by vboxsync, 12 years ago

header (C) fixes

  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 6.3 KB
Line 
1/* $Id: PCIInternal.h 44528 2013-02-04 14:27:54Z vboxsync $ */
2/** @file
3 * DevPCI - PCI Internal header - Only for hiding bits of PCIDEVICE.
4 */
5
6/*
7 * Copyright (C) 2006-2011 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#ifndef __PCIInternal_h__
19#define __PCIInternal_h__
20
21/**
22 * PCI I/O region.
23 */
24typedef struct PCIIOREGION
25{
26 /** Current PCI mapping address, 0xffffffff means not mapped. */
27 uint64_t addr;
28 uint64_t size;
29 uint8_t type; /* PCIADDRESSSPACE */
30 uint8_t padding[HC_ARCH_BITS == 32 ? 3 : 7];
31 /** Callback called when the region is mapped. */
32 R3PTRTYPE(PFNPCIIOREGIONMAP) map_func;
33} PCIIOREGION, PCIIORegion;
34/** Pointer to PCI I/O region. */
35typedef PCIIOREGION *PPCIIOREGION;
36
37/**
38 * Callback function for reading from the PCI configuration space.
39 *
40 * @returns The register value.
41 * @param pDevIns Pointer to the device instance of the PCI bus.
42 * @param iBus The bus number this device is on.
43 * @param iDevice The number of the device on the bus.
44 * @param Address The configuration space register address. [0..255]
45 * @param cb The register size. [1,2,4]
46 */
47typedef DECLCALLBACK(uint32_t) FNPCIBRIDGECONFIGREAD(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice, uint32_t u32Address, unsigned cb);
48/** Pointer to a FNPCICONFIGREAD() function. */
49typedef FNPCIBRIDGECONFIGREAD *PFNPCIBRIDGECONFIGREAD;
50/** Pointer to a PFNPCICONFIGREAD. */
51typedef PFNPCIBRIDGECONFIGREAD *PPFNPCIBRIDGECONFIGREAD;
52
53/**
54 * Callback function for writing to the PCI configuration space.
55 *
56 * @param pDevIns Pointer to the device instance of the PCI bus.
57 * @param iBus The bus number this device is on.
58 * @param iDevice The number of the device on the bus.
59 * @param Address The configuration space register address. [0..255]
60 * @param u32Value The value that's being written. The number of bits actually used from
61 * this value is determined by the cb parameter.
62 * @param cb The register size. [1,2,4]
63 */
64typedef DECLCALLBACK(void) FNPCIBRIDGECONFIGWRITE(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice, uint32_t u32Address, uint32_t u32Value, unsigned cb);
65/** Pointer to a FNPCICONFIGWRITE() function. */
66typedef FNPCIBRIDGECONFIGWRITE *PFNPCIBRIDGECONFIGWRITE;
67/** Pointer to a PFNPCICONFIGWRITE. */
68typedef PFNPCIBRIDGECONFIGWRITE *PPFNPCIBRIDGECONFIGWRITE;
69
70/* Forward declaration */
71struct PCIBus;
72
73enum {
74 /** Set if the specific device function was requested by PDM.
75 * If clear the device and it's functions can be relocated to satisfy the slot request of another device. */
76 PCIDEV_FLAG_REQUESTED_DEVFUNC = 1<<0,
77 /** Flag whether the device is a pci-to-pci bridge.
78 * This is set prior to device registration. */
79 PCIDEV_FLAG_PCI_TO_PCI_BRIDGE = 1<<1,
80 /** Flag whether the device is a PCI Express device.
81 * This is set prior to device registration. */
82 PCIDEV_FLAG_PCI_EXPRESS_DEVICE = 1<<2,
83 /** Flag whether the device is capable of MSI.
84 * This one is set by MsiInit(). */
85 PCIDEV_FLAG_MSI_CAPABLE = 1<<3,
86 /** Flag whether the device is capable of MSI-X.
87 * This one is set by MsixInit(). */
88 PCIDEV_FLAG_MSIX_CAPABLE = 1<<4,
89 /** Flag if device represents real physical device in passthrough mode. */
90 PCIDEV_FLAG_PASSTHROUGH = 1<<5,
91 /** Flag whether the device is capable of MSI using 64-bit address. */
92 PCIDEV_FLAG_MSI64_CAPABLE = 1<<6
93
94};
95
96/**
97 * PCI Device - Internal data.
98 */
99typedef struct PCIDEVICEINT
100{
101 /** I/O regions. */
102 PCIIOREGION aIORegions[PCI_NUM_REGIONS];
103 /** Pointer to the PCI bus of the device. (R3 ptr) */
104 R3PTRTYPE(struct PCIBus *) pBusR3;
105 /** Pointer to the PCI bus of the device. (R0 ptr) */
106 R0PTRTYPE(struct PCIBus *) pBusR0;
107 /** Pointer to the PCI bus of the device. (RC ptr) */
108 RCPTRTYPE(struct PCIBus *) pBusRC;
109#if HC_ARCH_BITS == 64
110 RTRCPTR Alignment0;
111#endif
112
113 /** Page used for MSI-X state. (R3 ptr) */
114 R3PTRTYPE(void*) pMsixPageR3;
115 /** Page used for MSI-X state. (R0 ptr) */
116 R0PTRTYPE(void*) pMsixPageR0;
117 /** Page used for MSI-X state. (RC ptr) */
118 RCPTRTYPE(void*) pMsixPageRC;
119#if HC_ARCH_BITS == 64
120 RTRCPTR Alignment1;
121#endif
122
123
124 /** Read config callback. */
125 R3PTRTYPE(PFNPCICONFIGREAD) pfnConfigRead;
126 /** Write config callback. */
127 R3PTRTYPE(PFNPCICONFIGWRITE) pfnConfigWrite;
128
129 /** Flags of this PCI device, see PCIDEV_FLAG_XXX constants. */
130 uint32_t fFlags;
131 /** Current state of the IRQ pin of the device. */
132 int32_t uIrqPinState;
133
134 /** Offset of MSI PCI capability in config space, or 0. */
135 uint8_t u8MsiCapOffset;
136 /** Size of MSI PCI capability in config space, or 0. */
137 uint8_t u8MsiCapSize;
138 /** Offset of MSI-X PCI capability in config space, or 0. */
139 uint8_t u8MsixCapOffset;
140 /** Size of MSI-X PCI capability in config space, or 0. */
141 uint8_t u8MsixCapSize;
142
143 uint32_t Alignment2;
144
145 /** Pointer to bus specific data. (R3 ptr) */
146 R3PTRTYPE(const void*) pPciBusPtrR3;
147
148 /** Read config callback for PCI bridges to pass requests
149 * to devices on another bus.
150 */
151 R3PTRTYPE(PFNPCIBRIDGECONFIGREAD) pfnBridgeConfigRead;
152 /** Write config callback for PCI bridges to pass requests
153 * to devices on another bus.
154 */
155 R3PTRTYPE(PFNPCIBRIDGECONFIGWRITE) pfnBridgeConfigWrite;
156
157} PCIDEVICEINT;
158
159/** Indicate that PCIDEVICE::Int.s can be declared. */
160#define PCIDEVICEINT_DECLARED
161
162#endif
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