1 | ## @file
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2 | # Provides drivers and definitions to support fsp in EDKII bios.
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3 | #
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4 | # Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.<BR>
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5 | # SPDX-License-Identifier: BSD-2-Clause-Patent
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6 | #
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7 | ##
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8 |
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9 | [Defines]
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10 | DEC_SPECIFICATION = 0x00010005
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11 | PACKAGE_NAME = IntelFsp2WrapperPkg
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12 | PACKAGE_GUID = FAFE06D4-7245-42D7-9FD2-E5D5E36AB0A0
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13 | PACKAGE_VERSION = 0.1
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14 |
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15 | [Includes]
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16 | Include
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17 |
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18 | [LibraryClasses]
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19 | ## @libraryclass Provide FSP API related function.
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20 | FspWrapperApiLib|Include/Library/FspWrapperApiLib.h
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21 | FspWrapperApiTestLib|Include/Library/FspWrapperApiTestLib.h
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22 |
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23 | ## @libraryclass Provide FSP hob process related function.
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24 | FspWrapperHobProcessLib|Include/Library/FspWrapperHobProcessLib.h
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25 |
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26 | ## @libraryclass Provide FSP platform related function.
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27 | FspWrapperPlatformLib|Include/Library/FspWrapperPlatformLib.h
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28 |
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29 | [Guids]
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30 | #
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31 | # GUID defined in package
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32 | #
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33 | gIntelFsp2WrapperTokenSpaceGuid = { 0xa34cf082, 0xf50, 0x4f0d, { 0x89, 0x8a, 0x3d, 0x39, 0x30, 0x2b, 0xc5, 0x1e } }
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34 | gFspApiPerformanceGuid = { 0xc9122295, 0x56ed, 0x4d4e, { 0x06, 0xa6, 0x50, 0x8d, 0x89, 0x4d, 0x3e, 0x40 } }
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35 | gFspHobGuid = { 0x6d86fb36, 0xba90, 0x472c, { 0xb5, 0x83, 0x3f, 0xbe, 0xd3, 0xfb, 0x20, 0x9a } }
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36 |
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37 | [Ppis]
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38 | gFspSiliconInitDonePpiGuid = { 0x4eb6e09c, 0xd256, 0x4e1e, { 0xb5, 0x0a, 0x87, 0x4b, 0xd2, 0x84, 0xb3, 0xde } }
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39 | gTopOfTemporaryRamPpiGuid = { 0x2f3962b2, 0x57c5, 0x44ec, { 0x9e, 0xfc, 0xa6, 0x9f, 0xd3, 0x02, 0x03, 0x2b } }
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40 |
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41 | [Protocols]
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42 | gAddPerfRecordProtocolGuid = { 0xc4a58d6d, 0x3677, 0x49cb, { 0xa0, 0x0a, 0x94, 0x70, 0x76, 0x5f, 0xb5, 0x5e } }
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43 |
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44 | ################################################################################
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45 | #
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46 | # PCD Declarations section - list of all PCDs Declared by this Package
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47 | # Only this package should be providing the
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48 | # declaration, other packages should not.
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49 | #
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50 | ################################################################################
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51 | [PcdsFixedAtBuild, PcdsPatchableInModule]
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52 | ## Provides the memory mapped base address of the BIOS CodeCache Flash Device.
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53 | gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheAddress|0xFFE00000|UINT32|0x10000001
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54 | ## Provides the size of the BIOS Flash Device.
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55 | gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize|0x00200000|UINT32|0x10000002
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56 |
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57 | ## Indicates the base address of the first Microcode Patch in the Microcode Region
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58 | gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress|0x0|UINT64|0x10000005
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59 | gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0x0|UINT64|0x10000006
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60 | ## Indicates the offset of the Cpu Microcode.
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61 | gIntelFsp2WrapperTokenSpaceGuid.PcdFlashMicrocodeOffset|0x90|UINT32|0x10000007
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62 |
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63 | ## Indicate the PEI memory size platform want to report
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64 | gIntelFsp2WrapperTokenSpaceGuid.PcdPeiMinMemSize|0x1800000|UINT32|0x40000004
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65 | ## Indicate the PEI memory size platform want to report
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66 | gIntelFsp2WrapperTokenSpaceGuid.PcdPeiRecoveryMinMemSize|0x3000000|UINT32|0x40000005
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67 |
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68 | ## This is the base address of FSP-T
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69 | gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress|0x00000000|UINT32|0x00000300
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70 |
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71 | ## This PCD indicates if FSP APIs are skipped from FSP wrapper.<BR><BR>
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72 | # If a bit is set, that means this FSP API is skipped.<BR>
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73 | # If a bit is clear, that means this FSP API is NOT skipped.<BR>
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74 | # NOTE: Only NotifyPhase Post PCI enumeration (BIT16) is implemented.<BR>
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75 | # BIT[15:0] is for function:<BR>
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76 | # BIT0 - Skip TempRamInit<BR>
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77 | # BIT1 - Skip MemoryInit<BR>
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78 | # BIT2 - Skip TempRamExit<BR>
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79 | # BIT3 - Skip SiliconInit<BR>
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80 | # BIT4 - Skip NotifyPhase<BR>
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81 | # BIT[32:16] is for sub-function:<BR>
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82 | # BIT16 - Skip NotifyPhase (AfterPciEnumeration)<BR>
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83 | # BIT17 - Skip NotifyPhase (ReadyToBoot)<BR>
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84 | # BIT18 - Skip NotifyPhase (EndOfFirmware)<BR>
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85 | # Any undefined BITs are reserved for future use.<BR>
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86 | # @Prompt Skip FSP API from FSP wrapper.
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87 | gIntelFsp2WrapperTokenSpaceGuid.PcdSkipFspApi|0x00000000|UINT32|0x40000009
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88 |
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89 | ## This PCD decides how Wrapper code utilizes FSP
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90 | # 0: DISPATCH mode (FSP Wrapper will load PeiCore from FSP without calling FSP API)
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91 | # 1: API mode (FSP Wrapper will call FSP API)
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92 | #
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93 | gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection|0x00000001|UINT8|0x4000000A
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94 |
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95 | [PcdsFixedAtBuild, PcdsPatchableInModule,PcdsDynamic,PcdsDynamicEx]
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96 | #
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97 | ## These are the base address of FSP-M/S
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98 | #
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99 | gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress|0x00000000|UINT32|0x00001000
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100 | gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress|0x00000000|UINT32|0x00001001
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101 | #
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102 | # To provide flexibility for platform to pre-allocate FSP UPD buffer
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103 | #
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104 | # The PCDs define the pre-allocated FSPM and FSPS UPD Data Buffer Address.
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105 | # 0x00000000 - Platform will not pre-allocate UPD buffer before FspWrapper module
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106 | # non-zero - Platform will pre-allocate UPD buffer and patch this value to
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107 | # buffer address before FspWrapper module executing.
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108 | #
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109 | gIntelFsp2WrapperTokenSpaceGuid.PcdFspmUpdDataAddress|0x00000000|UINT32|0x50000000
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110 | gIntelFsp2WrapperTokenSpaceGuid.PcdFspsUpdDataAddress|0x00000000|UINT32|0x50000001
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