| 1 | /** @file
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| 2 | This file defines the structure for the PCI Root Bridges.
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| 3 |
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| 4 | Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
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| 5 | SPDX-License-Identifier: BSD-2-Clause-Patent
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| 6 |
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| 7 | @par Revision Reference:
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| 8 | - Universal Payload Specification 0.75 (https://universalpayload.github.io/documentation/)
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| 9 | **/
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| 10 |
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| 11 | #ifndef UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGES_H_
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| 12 | #define UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGES_H_
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| 13 |
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| 14 | #include <UniversalPayload/UniversalPayload.h>
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| 15 |
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| 16 | #pragma pack(1)
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| 17 |
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| 18 | //
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| 19 | // (Base > Limit) indicates an aperture is not available.
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| 20 | //
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| 21 | typedef struct {
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| 22 | //
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| 23 | // Base and Limit are the device address instead of host address when
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| 24 | // Translation is not zero
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| 25 | //
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| 26 | UINT64 Base;
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| 27 | UINT64 Limit;
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| 28 | //
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| 29 | // According to UEFI 2.7, Device Address = Host Address + Translation,
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| 30 | // so Translation = Device Address - Host Address.
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| 31 | // On platforms where Translation is not zero, the subtraction is probably to
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| 32 | // be performed with UINT64 wrap-around semantics, for we may translate an
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| 33 | // above-4G host address into a below-4G device address for legacy PCIe device
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| 34 | // compatibility.
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| 35 | //
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| 36 | // NOTE: The alignment of Translation is required to be larger than any BAR
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| 37 | // alignment in the same root bridge, so that the same alignment can be
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| 38 | // applied to both device address and host address, which simplifies the
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| 39 | // situation and makes the current resource allocation code in generic PCI
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| 40 | // host bridge driver still work.
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| 41 | //
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| 42 | UINT64 Translation;
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| 43 | } UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE_APERTURE;
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| 44 |
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| 45 | ///
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| 46 | /// Payload PCI Root Bridge Information HOB
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| 47 | ///
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| 48 | typedef struct {
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| 49 | UINT32 Segment; ///< Segment number.
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| 50 | UINT64 Supports; ///< Supported attributes.
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| 51 | ///< Refer to EFI_PCI_ATTRIBUTE_xxx used by GetAttributes()
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| 52 | ///< and SetAttributes() in EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
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| 53 | UINT64 Attributes; ///< Initial attributes.
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| 54 | ///< Refer to EFI_PCI_ATTRIBUTE_xxx used by GetAttributes()
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| 55 | ///< and SetAttributes() in EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
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| 56 | BOOLEAN DmaAbove4G; ///< DMA above 4GB memory.
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| 57 | ///< Set to TRUE when root bridge supports DMA above 4GB memory.
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| 58 | BOOLEAN NoExtendedConfigSpace; ///< When FALSE, the root bridge supports
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| 59 | ///< Extended (4096-byte) Configuration Space.
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| 60 | ///< When TRUE, the root bridge supports
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| 61 | ///< 256-byte Configuration Space only.
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| 62 | UINT64 AllocationAttributes; ///< Allocation attributes.
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| 63 | ///< Refer to EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM and
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| 64 | ///< EFI_PCI_HOST_BRIDGE_MEM64_DECODE used by GetAllocAttributes()
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| 65 | ///< in EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.
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| 66 | UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE_APERTURE Bus; ///< Bus aperture which can be used by the root bridge.
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| 67 | UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE_APERTURE Io; ///< IO aperture which can be used by the root bridge.
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| 68 | UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE_APERTURE Mem; ///< MMIO aperture below 4GB which can be used by the root bridge.
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| 69 | UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE_APERTURE MemAbove4G; ///< MMIO aperture above 4GB which can be used by the root bridge.
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| 70 | UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE_APERTURE PMem; ///< Prefetchable MMIO aperture below 4GB which can be used by the root bridge.
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| 71 | UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE_APERTURE PMemAbove4G; ///< Prefetchable MMIO aperture above 4GB which can be used by the root bridge.
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| 72 | UINT32 HID; ///< PnP hardware ID of the root bridge. This value must match the corresponding
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| 73 | ///< _HID in the ACPI name space.
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| 74 | UINT32 UID; ///< Unique ID that is required by ACPI if two devices have the same _HID.
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| 75 | ///< This value must also match the corresponding _UID/_HID pair in the ACPI name space.
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| 76 | } UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE;
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| 77 |
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| 78 | typedef struct {
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| 79 | UNIVERSAL_PAYLOAD_GENERIC_HEADER Header;
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| 80 | BOOLEAN ResourceAssigned;
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| 81 | UINT8 Count;
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| 82 | UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE RootBridge[0];
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| 83 | } UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGES;
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| 84 |
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| 85 | #pragma pack()
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| 86 |
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| 87 | #define UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGES_REVISION 1
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| 88 |
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| 89 | extern GUID gUniversalPayloadPciRootBridgeInfoGuid;
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| 90 |
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| 91 | #endif // UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGES_H_
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