| 1 | /** @file
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| 2 | CXL 2.0 Register definitions
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| 3 |
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| 4 | This file contains the register definitions based on the Compute Express Link
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| 5 | (CXL) Specification Revision 2.0.
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| 6 |
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| 7 | Copyright (c) 2023, Ampere Computing LLC. All rights reserved.<BR>
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| 8 |
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| 9 | SPDX-License-Identifier: BSD-2-Clause-Patent
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| 10 |
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| 11 | **/
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| 12 |
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| 13 | #ifndef CXL20_H_
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| 14 | #define CXL20_H_
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| 15 |
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| 16 | #include <IndustryStandard/Cxl11.h>
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| 17 |
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| 18 | //
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| 19 | // CXL DVSEC IDs
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| 20 | // Compute Express Link Specification Revision 2.0 - Chapter 8.1.1
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| 21 | //
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| 22 | #define CXL_DVSEC_ID_PCIE_DVSEC_FOR_CXL_DEVICE 0x0
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| 23 | #define CXL_DVSEC_ID_NON_CXL_FUNCTION_MAP 0x2
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| 24 | #define CXL_DVSEC_ID_CXL20_EXTENSIONS_DVSEC_FOR_PORTS 0x3
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| 25 | #define CXL_DVSEC_ID_GPF_DVSEC_FOR_CXL_PORTS 0x4
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| 26 | #define CXL_DVSEC_ID_GPF_DVSEC_FOR_CXL_DEVICES 0x5
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| 27 | #define CXL_DVSEC_ID_PCIE_DVSEC_FOR_FLEX_BUS_PORT 0x7
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| 28 | #define CXL_DVSEC_ID_REGISTER_LOCATOR 0x8
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| 29 | #define CXL_DVSEC_ID_MLD 0x9
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| 30 | #define CXL_DVSEC_ID_PCIE_DVSEC_FOR_TEST_CAPABILITY 0xA
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| 31 |
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| 32 | //
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| 33 | // Register Block ID
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| 34 | // Compute Express Link Specification Revision 2.0 - Chapter 8.1.9.1
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| 35 | //
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| 36 | #define CXL_REGISTER_BLOCK_ID_EMPTY 0x0
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| 37 | #define CXL_REGISTER_BLOCK_ID_COMPONENT 0x1
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| 38 | #define CXL_REGISTER_BLOCK_ID_BAR_VIRTUALIZATION_ACL 0x2
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| 39 | #define CXL_REGISTER_BLOCK_ID_DEVICE 0x3
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| 40 |
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| 41 | //
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| 42 | // CXL component register layout
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| 43 | // Compute Express Link Specification Revision 2.0 - Chapter 8.2.4
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| 44 | //
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| 45 | // |------------------------------------|
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| 46 | // |--------- Range & Type -------------|
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| 47 | // |------------------------------------| IO Base - 0KB
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| 48 | // | (0KB - 4KB)IO Regs |
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| 49 | // |------------------------------------| Cache and Mem Base - 4KB
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| 50 | // | {4KB - 8KB)Cache & Mem Regs |
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| 51 | // |------------------------------------| Implementation Spec Regs Base - 8KB
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| 52 | // | (8KB - 56KB)Implement Spec Regs|
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| 53 | // |------------------------------------| ARB/Mux Regs Base - 56KB
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| 54 | // | (56KB - 57KB)ARBMUX Regs |
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| 55 | // |------------------------------------| Reserved Base - 57KB
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| 56 | // | (57KB - 63KB)Reserved |
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| 57 | // |------------------------------------| End 64KB
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| 58 | //
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| 59 | // Component Register Block Register Ranges Offset
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| 60 | //
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| 61 | #define CXL_COMPONENT_REGISTER_RANGE_OFFSET_IO 0x0
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| 62 | #define CXL_COMPONENT_REGISTER_RANGE_OFFSET_CACHE_MEM 0x1000
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| 63 | #define CXL_COMPONENT_REGISTER_RANGE_OFFSET_ARB_MUX 0xE000
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| 64 |
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| 65 | //
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| 66 | // CXL Cache Memory Capability IDs
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| 67 | // Compute Express Link Specification Revision 2.0 - Chapter 8.2.5
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| 68 | //
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| 69 | #define CXL_CACHE_MEM_CAPABILITY_ID_CXL 0x1
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| 70 | #define CXL_CACHE_MEM_CAPABILITY_ID_RAS 0x2
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| 71 | #define CXL_CACHE_MEM_CAPABILITY_ID_SECURITY 0x3
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| 72 | #define CXL_CACHE_MEM_CAPABILITY_ID_LINK 0x4
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| 73 | #define CXL_CACHE_MEM_CAPABILITY_ID_HDM_DECODER 0x5
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| 74 | #define CXL_CACHE_MEM_CAPABILITY_ID_EXTENDED_SECURITY 0x6
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| 75 | #define CXL_CACHE_MEM_CAPABILITY_ID_IDE 0x7
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| 76 | #define CXL_CACHE_MEM_CAPABILITY_ID_SNOOP_FILTER 0x8
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| 77 | #define CXL_CACHE_MEM_CAPABILITY_ID_MASK 0xFFFF
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| 78 |
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| 79 | //
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| 80 | // Generic CXL Device Capability IDs 0x0000 ~ 0x3FFF
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| 81 | // Compute Express Link Specification Revision 2.0 - Chapter 8.2.8.2.1
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| 82 | //
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| 83 | #define CXL_DEVICE_CAPABILITY_ID_CAPABILITIES_ARRAY_REGISTER 0x0000
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| 84 | #define CXL_DEVICE_CAPABILITY_ID_DEVICE_STATUS 0x0001
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| 85 | #define CXL_DEVICE_CAPABILITY_ID_PRIMARY_MAILBOX 0x0002
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| 86 | #define CXL_DEVICE_CAPABILITY_ID_SECONDARY_MAILBOX 0x0003
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| 87 |
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| 88 | //
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| 89 | // Specific CXL Device Capability IDs 0x4000 ~ 0x7FFF
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| 90 | // Compute Express Link Specification Revision 2.0 - Chapter 8.2.8.2.1 and 8.2.8.5
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| 91 |
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| 92 | //
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| 93 | #define CXL_DEVICE_CAPABILITY_ID_MEMORY_DEVICE_STATUS 0x4000
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| 94 | #define CXL_DEVICE_CAPABILITY_ID_MASK 0xFFFF
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| 95 |
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| 96 | //
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| 97 | // Memory Device Status
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| 98 | // Compute Express Link Specification Revision 2.0 - Chapter 8.2.8.5.1.1
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| 99 | //
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| 100 | #define CXL_MEM_DEVICE_MEDIA_STATUS_NOT_READY 0x0
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| 101 | #define CXL_MEM_DEVICE_MEDIA_STATUS_READY 0x1
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| 102 | #define CXL_MEM_DEVICE_MEDIA_STATUS_ERROR 0x2
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| 103 | #define CXL_MEM_DEVICE_MEDIA_STATUS_DISABLED 0x3
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| 104 |
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| 105 | //
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| 106 | // Ensure proper structure formats
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| 107 | //
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| 108 | #pragma pack(1)
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| 109 |
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| 110 | //
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| 111 | // PCIe DVSEC for CXL Device
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| 112 | // Compute Express Link Specification Revision 2.0 - Chapter 8.1.3
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| 113 | //
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| 114 | typedef union {
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| 115 | struct {
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| 116 | UINT16 CacheCapable : 1; // bit 0
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| 117 | UINT16 IoCapable : 1; // bit 1
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| 118 | UINT16 MemCapable : 1; // bit 2
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| 119 | UINT16 MemHwInitMode : 1; // bit 3
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| 120 | UINT16 HdmCount : 2; // bit 4..5
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| 121 | UINT16 CacheWriteBackAndInvalidateCapable : 1; // bit 6
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| 122 | UINT16 CxlResetCapable : 1; // bit 7
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| 123 | UINT16 CxlResetTimeout : 3; // bit 8..10
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| 124 | UINT16 CxlResetMemClrCapable : 1; // bit 11
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| 125 | UINT16 Reserved : 1; // bit 12
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| 126 | UINT16 MultipleLogicalDevice : 1; // bit 13
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| 127 | UINT16 ViralCapable : 1; // bit 14
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| 128 | UINT16 PmInitCompletionReportingCapable : 1; // bit 15
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| 129 | } Bits;
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| 130 | UINT16 Uint16;
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| 131 | } CXL_DVSEC_CXL_DEVICE_CAPABILITY;
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| 132 |
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| 133 | typedef union {
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| 134 | struct {
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| 135 | UINT16 CacheEnable : 1; // bit 0
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| 136 | UINT16 IoEnable : 1; // bit 1
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| 137 | UINT16 MemEnable : 1; // bit 2
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| 138 | UINT16 CacheSfCoverage : 5; // bit 3..7
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| 139 | UINT16 CacheSfGranularity : 3; // bit 8..10
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| 140 | UINT16 CacheCleanEviction : 1; // bit 11
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| 141 | UINT16 Reserved1 : 2; // bit 12..13
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| 142 | UINT16 ViralEnable : 1; // bit 14
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| 143 | UINT16 Reserved2 : 1; // bit 15
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| 144 | } Bits;
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| 145 | UINT16 Uint16;
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| 146 | } CXL_DVSEC_CXL_DEVICE_CONTROL;
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| 147 |
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| 148 | typedef union {
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| 149 | struct {
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| 150 | UINT16 Reserved1 : 14; // bit 0..13
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| 151 | UINT16 ViralStatus : 1; // bit 14
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| 152 | UINT16 Reserved2 : 1; // bit 15
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| 153 | } Bits;
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| 154 | UINT16 Uint16;
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| 155 | } CXL_DVSEC_CXL_DEVICE_STATUS;
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| 156 |
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| 157 | typedef union {
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| 158 | struct {
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| 159 | UINT16 DisableCaching : 1; // bit 0
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| 160 | UINT16 InitiateCacheWriteBackAndInvalidate : 1; // bit 1
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| 161 | UINT16 InitiateCxlReset : 1; // bit 2
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| 162 | UINT16 CxlResetMemClrEnable : 1; // bit 3
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| 163 | UINT16 Reserved : 12; // bit 4..15
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| 164 | } Bits;
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| 165 | UINT16 Uint16;
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| 166 | } CXL_DVSEC_CXL_DEVICE_CONTROL2;
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| 167 |
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| 168 | typedef union {
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| 169 | struct {
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| 170 | UINT16 CacheInvalid : 1; // bit 0
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| 171 | UINT16 CxlResetComplete : 1; // bit 1
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| 172 | UINT16 Reserved : 13; // bit 2..14
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| 173 | UINT16 PowerManagementInitialzationComplete : 1; // bit 15
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| 174 | } Bits;
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| 175 | UINT16 Uint16;
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| 176 | } CXL_DVSEC_CXL_DEVICE_STATUS2;
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| 177 |
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| 178 | typedef union {
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| 179 | struct {
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| 180 | UINT16 ConfigLock : 1; // bit 0
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| 181 | UINT16 Reserved : 15; // bit 1..15
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| 182 | } Bits;
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| 183 | UINT16 Uint16;
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| 184 | } CXL_DVSEC_CXL_DEVICE_LOCK;
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| 185 |
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| 186 | typedef union {
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| 187 | struct {
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| 188 | UINT16 CacheSizeUnit : 4; // bit 0..3
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| 189 | UINT16 Reserved : 4; // bit 4..7
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| 190 | UINT16 CacheSize : 8; // bit 8..15
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| 191 | } Bits;
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| 192 | UINT16 Uint16;
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| 193 | } CXL_DVSEC_CXL_DEVICE_CAPABILITY2;
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| 194 |
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| 195 | typedef union {
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| 196 | struct {
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| 197 | UINT32 MemorySizeHigh : 32; // bit 0..31
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| 198 | } Bits;
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| 199 | UINT32 Uint32;
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| 200 | } CXL_DVSEC_CXL_DEVICE_RANGE_SIZE_HIGH;
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| 201 |
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| 202 | typedef union {
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| 203 | struct {
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| 204 | UINT32 MemoryInfoValid : 1; // bit 0
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| 205 | UINT32 MemoryActive : 1; // bit 1
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| 206 | UINT32 MediaType : 3; // bit 2..4
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| 207 | UINT32 MemoryClass : 3; // bit 5..7
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| 208 | UINT32 DesiredInterleave : 5; // bit 8..12
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| 209 | UINT32 MemoryActiveTimeout : 3; // bit 13..15
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| 210 | UINT32 Reserved : 12; // bit 16..27
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| 211 | UINT32 MemorySizeLow : 4; // bit 28..31
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| 212 | } Bits;
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| 213 | UINT32 Uint32;
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| 214 | } CXL_DVSEC_CXL_DEVICE_RANGE_SIZE_LOW;
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| 215 |
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| 216 | typedef union {
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| 217 | struct {
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| 218 | UINT32 MemoryBaseHigh : 32; // bit 0..31
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| 219 | } Bits;
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| 220 | UINT32 Uint32;
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| 221 | } CXL_DVSEC_CXL_DEVICE_RANGE_BASE_HIGH;
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| 222 |
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| 223 | typedef union {
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| 224 | struct {
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| 225 | UINT32 Reserved : 28; // bit 0..27
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| 226 | UINT32 MemoryBaseLow : 4; // bit 28..31
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| 227 | } Bits;
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| 228 | UINT32 Uint32;
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| 229 | } CXL_DVSEC_CXL_DEVICE_RANGE_BASE_LOW;
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| 230 |
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| 231 | typedef struct {
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| 232 | PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header; // offset 0x00
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| 233 | PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_1 DvsecHeader1; // offset 0x04
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| 234 | PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_2 DvsecHeader2; // offset 0x08
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| 235 | CXL_DVSEC_CXL_DEVICE_CAPABILITY DeviceCapability; // offset 0x0A
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| 236 | CXL_DVSEC_CXL_DEVICE_CONTROL DeviceControl; // offset 0x0C
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| 237 | CXL_DVSEC_CXL_DEVICE_STATUS DeviceStatus; // offset 0x0E
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| 238 | CXL_DVSEC_CXL_DEVICE_CONTROL2 DeviceControl2; // offset 0x10
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| 239 | CXL_DVSEC_CXL_DEVICE_STATUS2 DeviceStatus2; // offset 0x12
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| 240 | CXL_DVSEC_CXL_DEVICE_LOCK DeviceLock; // offset 0x14
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| 241 | CXL_DVSEC_CXL_DEVICE_CAPABILITY2 DeviceCapability2; // offset 0x16
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| 242 | CXL_DVSEC_CXL_DEVICE_RANGE_SIZE_HIGH DeviceRange1SizeHigh; // offset 0x18
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| 243 | CXL_DVSEC_CXL_DEVICE_RANGE_SIZE_LOW DeviceRange1SizeLow; // offset 0x1C
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| 244 | CXL_DVSEC_CXL_DEVICE_RANGE_BASE_HIGH DeviceRange1BaseHigh; // offset 0x20
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| 245 | CXL_DVSEC_CXL_DEVICE_RANGE_BASE_LOW DeviceRange1BaseLow; // offset 0x24
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| 246 | CXL_DVSEC_CXL_DEVICE_RANGE_SIZE_HIGH DeviceRange2SizeHigh; // offset 0x28
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| 247 | CXL_DVSEC_CXL_DEVICE_RANGE_SIZE_LOW DeviceRange2SizeLow; // offset 0x2C
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| 248 | CXL_DVSEC_CXL_DEVICE_RANGE_BASE_HIGH DeviceRange2BaseHigh; // offset 0x30
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| 249 | CXL_DVSEC_CXL_DEVICE_RANGE_BASE_LOW DeviceRange2BaseLow; // offset 0x34
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| 250 | } CXL_DVSEC_CXL_DEVICE;
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| 251 |
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| 252 | #define CXL_DVSEC_CXL_DEVICE_REVISION_1 0x1
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| 253 |
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| 254 | //
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| 255 | // Register Locator DVSEC
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| 256 | // Compute Express Link Specification Revision 2.0 - Chapter 8.1.9
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| 257 | //
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| 258 |
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| 259 | typedef union {
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| 260 | struct {
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| 261 | UINT32 RegisterBir : 3; // bit 0..2
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| 262 | UINT32 Reserved : 5; // bit 3..7
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| 263 | UINT32 RegisterBlockIdentifier : 8; // bit 8..15
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| 264 | UINT32 RegisterBlockOffsetLow : 16; // bit 16..31
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| 265 | } Bits;
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| 266 | UINT32 Uint32;
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| 267 | } CXL_DVSEC_REGISTER_LOCATOR_REGISTER_OFFSET_LOW;
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| 268 |
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| 269 | typedef union {
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| 270 | struct {
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| 271 | UINT32 RegisterBlockOffsetHigh : 32; // bit 0..31
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| 272 | } Bits;
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| 273 | UINT32 Uint32;
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| 274 | } CXL_DVSEC_REGISTER_LOCATOR_REGISTER_OFFSET_HIGH;
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| 275 |
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| 276 | typedef struct {
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| 277 | CXL_DVSEC_REGISTER_LOCATOR_REGISTER_OFFSET_LOW OffsetLow;
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| 278 | CXL_DVSEC_REGISTER_LOCATOR_REGISTER_OFFSET_HIGH OffsetHigh;
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| 279 | } CXL_DVSEC_REGISTER_LOCATOR_REGISTER_BLOCK;
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| 280 |
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| 281 | typedef struct {
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| 282 | PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header; // offset 0x00
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| 283 | PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_1 DvsecHeader1; // offset 0x04
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| 284 | PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_2 DvsecHeader2; // offset 0x08
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| 285 | UINT16 Reserved; // offset 0x0A
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| 286 | CXL_DVSEC_REGISTER_LOCATOR_REGISTER_BLOCK RegisterBlock[]; // offset 0x0C
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| 287 | } CXL_DVSEC_REGISTER_LOCATOR;
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| 288 |
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| 289 | #define CXL_DVSEC_REGISTER_LOCATOR_REVISION_0 0x0
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| 290 |
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| 291 | //
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| 292 | // CXL HDM Decoder Capability Header Register
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| 293 | // Compute Express Link Specification Revision 2.0 - Chapter 8.2.5.5
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| 294 | //
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| 295 | typedef union {
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| 296 | struct {
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| 297 | UINT32 CxlCapabilityId : 16; // bit 0..15
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| 298 | UINT32 CxlCapabilityVersion : 4; // bit 16..19
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| 299 | UINT32 CxlHdmDecoderCapabilityPointer : 12; // bit 20..31
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| 300 | } Bits;
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| 301 | UINT32 Uint32;
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| 302 | } CXL_HDM_DECODER_CAPABILITY_HEADER_REGISTER;
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| 303 |
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| 304 | //
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| 305 | // CXL HDM Decoder Capability Register
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| 306 | // Compute Express Link Specification Revision 2.0 - Chapter 8.2.5.12
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| 307 | //
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| 308 | typedef union {
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| 309 | struct {
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| 310 | UINT32 DecoderCount : 4; // bit 0..3
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| 311 | UINT32 TargetCount : 4; // bit 4..7
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| 312 | UINT32 InterleaveCapableA11to8 : 1; // bit 8
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| 313 | UINT32 InterleaveCapableA14to12 : 1; // bit 9
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| 314 | UINT32 PoisonOnDecodeErrorCapability : 1; // bit 10
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| 315 | UINT32 Reserved : 21; // bit 11..31
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| 316 | } Bits;
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| 317 | UINT32 Uint32;
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| 318 | } CXL_HDM_DECODER_CAPABILITY_REGISTER;
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| 319 |
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| 320 | typedef union {
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| 321 | struct {
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| 322 | UINT32 PoisonOnDecodeErrorEnable : 1; // bit 0
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| 323 | UINT32 HdmDecoderEnable : 1; // bit 1
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| 324 | UINT32 Reserved : 30; // bit 2..31
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| 325 | } Bits;
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| 326 | UINT32 Uint32;
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| 327 | } CXL_HDM_DECODER_GLOBAL_CONTROL_REGISTER;
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| 328 |
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| 329 | typedef union {
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| 330 | struct {
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| 331 | UINT32 Reserved : 28; // bit 0..27
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| 332 | UINT32 MemoryBaseLow : 4; // bit 28..31
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| 333 | } Bits;
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| 334 | UINT32 Uint32;
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| 335 | } CXL_HDM_DECODER_BASE_LOW_REGISTER;
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| 336 |
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| 337 | typedef union {
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| 338 | struct {
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| 339 | UINT32 MemoryBaseHigh : 32; // bit 0..31
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| 340 | } Bits;
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| 341 | UINT32 Uint32;
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| 342 | } CXL_HDM_DECODER_BASE_HIGH_REGISTER;
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| 343 |
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| 344 | typedef union {
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| 345 | struct {
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| 346 | UINT32 Reserved : 28; // bit 0..27
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| 347 | UINT32 MemorySizeLow : 4; // bit 28..31
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| 348 | } Bits;
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| 349 | UINT32 Uint32;
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| 350 | } CXL_HDM_DECODER_SIZE_LOW_REGISTER;
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| 351 |
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| 352 | typedef union {
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| 353 | struct {
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| 354 | UINT32 MemorySizeHigh : 32; // bit 0..31
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| 355 | } Bits;
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| 356 | UINT32 Uint32;
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| 357 | } CXL_HDM_DECODER_SIZE_HIGH_REGISTER;
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| 358 |
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| 359 | typedef union {
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| 360 | struct {
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| 361 | UINT32 InterleaveGranularity : 4; // bit 0..3
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| 362 | UINT32 InterleaveWays : 4; // bit 4..7
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| 363 | UINT32 LockOnCommit : 1; // bit 8
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| 364 | UINT32 Commit : 1; // bit 9
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| 365 | UINT32 Committed : 1; // bit 10
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| 366 | UINT32 ErrorNotCommitted : 1; // bit 11
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| 367 | UINT32 TargetDeviceType : 1; // bit 12
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| 368 | UINT32 Reserved : 19; // bit 13..31
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| 369 | } Bits;
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| 370 | UINT32 Uint32;
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| 371 | } CXL_HDM_DECODER_CONTROL_REGISTER;
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| 372 |
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| 373 | typedef union {
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| 374 | struct {
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| 375 | UINT32 TargetPortIdentiferWay0 : 8; // bit 0..7
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| 376 | UINT32 TargetPortIdentiferWay1 : 8; // bit 8..15
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| 377 | UINT32 TargetPortIdentiferWay2 : 8; // bit 16..23
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| 378 | UINT32 TargetPortIdentiferWay3 : 8; // bit 24..31
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| 379 | } Bits;
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| 380 | UINT32 Uint32;
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| 381 | } CXL_HDM_DECODER_TARGET_LIST_LOW_REGISTER;
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| 382 |
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| 383 | typedef union {
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| 384 | struct {
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| 385 | UINT32 Reserved : 28; // bit 0..27
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| 386 | UINT32 DpaSkipLow : 4; // bit 28..31
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| 387 | } Bits;
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| 388 | UINT32 Uint32;
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| 389 | } CXL_HDM_DECODER_DPA_SKIP_LOW_REGISTER;
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| 390 |
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| 391 | typedef union {
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| 392 | struct {
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| 393 | UINT32 TargetPortIdentiferWay4 : 8; // bit 0..7
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| 394 | UINT32 TargetPortIdentiferWay5 : 8; // bit 8..15
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| 395 | UINT32 TargetPortIdentiferWay6 : 8; // bit 16..23
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| 396 | UINT32 TargetPortIdentiferWay7 : 8; // bit 24..31
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| 397 | } Bits;
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| 398 | UINT32 Uint32;
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| 399 | } CXL_HDM_DECODER_TARGET_LIST_HIGH_REGISTER;
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| 400 |
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| 401 | typedef union {
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| 402 | struct {
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| 403 | UINT32 DpaSkipHigh : 32; // bit 0..31
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| 404 | } Bits;
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| 405 | UINT32 Uint32;
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| 406 | } CXL_HDM_DECODER_DPA_SKIP_HIGH_REGISTER;
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| 407 |
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| 408 | typedef union {
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| 409 | CXL_HDM_DECODER_TARGET_LIST_LOW_REGISTER TargetListLow;
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| 410 | CXL_HDM_DECODER_DPA_SKIP_LOW_REGISTER DpaSkipLow;
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| 411 | } CXL_HDM_DECODER_TARGET_LIST_OR_DPA_SKIP_LOW;
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| 412 |
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| 413 | typedef union {
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| 414 | CXL_HDM_DECODER_TARGET_LIST_HIGH_REGISTER TargetListHigh;
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| 415 | CXL_HDM_DECODER_DPA_SKIP_HIGH_REGISTER DpaSkipHigh;
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| 416 | } CXL_HDM_DECODER_TARGET_LIST_OR_DPA_SKIP_HIGH;
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| 417 |
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| 418 | typedef struct {
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| 419 | CXL_HDM_DECODER_BASE_LOW_REGISTER DecoderBaseLow; // 0x10
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| 420 | CXL_HDM_DECODER_BASE_HIGH_REGISTER DecoderBaseHigh; // 0x14
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| 421 | CXL_HDM_DECODER_SIZE_LOW_REGISTER DecoderSizeLow; // 0x18
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| 422 | CXL_HDM_DECODER_SIZE_HIGH_REGISTER DecoderSizeHigh; // 0x1c
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| 423 | CXL_HDM_DECODER_CONTROL_REGISTER DecoderControl; // 0x20
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| 424 | CXL_HDM_DECODER_TARGET_LIST_OR_DPA_SKIP_LOW DecoderTargetListDpaSkipLow; // 0x24
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| 425 | CXL_HDM_DECODER_TARGET_LIST_OR_DPA_SKIP_HIGH DecoderTargetListDpaSkipHigh; // 0x28
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| 426 | UINT32 Reserved; // 0x2C
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| 427 | } CXL_HDM_DECODER;
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| 428 |
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| 429 | //
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| 430 | // CXL Device Capabilities Array Register
|
|---|
| 431 | // Compute Express Link Specification Revision 2.0 - Chapter 8.2.8.1
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| 432 | //
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| 433 |
|
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| 434 | typedef union {
|
|---|
| 435 | struct {
|
|---|
| 436 | UINT64 CxlDeviceCapabilityId : 16; // bit 0..15
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| 437 | UINT64 CxlDeviceCapabilityVersion : 8; // bit 16..23
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|---|
| 438 | UINT64 Reserved1 : 8; // bit 24..31
|
|---|
| 439 | UINT64 CxlDeviceCapabilitiesCount : 16; // bit 32..47
|
|---|
| 440 | UINT64 Reserved2 : 16; // bit 48..63
|
|---|
| 441 | } Bits;
|
|---|
| 442 | UINT64 Uint64;
|
|---|
| 443 | } CXL_DEVICE_CAPABILITIES_ARRAY_REGISTER;
|
|---|
| 444 |
|
|---|
| 445 | //
|
|---|
| 446 | // CXL Memory Status Register
|
|---|
| 447 | // Compute Express Link Specification Revision 2.0 - Chapter 8.2.8.5
|
|---|
| 448 | //
|
|---|
| 449 | typedef union {
|
|---|
| 450 | struct {
|
|---|
| 451 | UINT64 DeviceFatal : 1; // bit 0
|
|---|
| 452 | UINT64 FwHalt : 1; // bit 1
|
|---|
| 453 | UINT64 MediaStatus : 2; // bit 2..3
|
|---|
| 454 | UINT64 MailboxInterfacesReady : 1; // bit 4
|
|---|
| 455 | UINT64 ResetNeeded : 3; // bit 5..7
|
|---|
| 456 | UINT64 Reserved : 56; // bit 8..63
|
|---|
| 457 | } Bits;
|
|---|
| 458 | UINT64 Uint64;
|
|---|
| 459 | } CXL_MEMORY_DEVICE_STATUS_REGISTER;
|
|---|
| 460 |
|
|---|
| 461 | #pragma pack()
|
|---|
| 462 |
|
|---|
| 463 | #endif
|
|---|
