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source: vbox/trunk/src/VBox/Devices/EFI/Firmware/MdePkg/Include/IndustryStandard/Cxl30.h

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1/** @file
2 CXL 3.0 Register definitions
3
4 This file contains the register definitions based on the Compute Express Link
5 (CXL) Specification Revision 3.0.
6
7 Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
8
9 SPDX-License-Identifier: BSD-2-Clause-Patent
10
11**/
12
13#ifndef CXL30_H_
14#define CXL30_H_
15
16#include <IndustryStandard/Cxl20.h>
17
18//
19// CXL Cache Memory Capability IDs
20// Compute Express Link Specification Revision 3.0 - Chapter 8.2.4 Table 8-22
21//
22#define CXL_CACHE_MEM_CAPABILITY_ID_TIMEOUT_AND_ISOLATION 0x0009
23#define CXL_CACHE_MEM_CAPABILITY_ID_EXTENDED 0x000A
24#define CXL_CACHE_MEM_CAPABILITY_ID_BI_ROUTE_TABLE 0x000B
25#define CXL_CACHE_MEM_CAPABILITY_ID_BI_DECODER 0x000C
26#define CXL_CACHE_MEM_CAPABILITY_ID_CACHE_ID_ROUTE_TABLE 0x000D
27#define CXL_CACHE_MEM_CAPABILITY_ID_CACHE_ID_DECODER 0x000E
28#define CXL_CACHE_MEM_CAPABILITY_ID_EXTENDED_HDM_DECODER 0x000F
29
30//
31// CXL_Capability_Version
32// Compute Express ink Specification Revision 3.0 - Chapter 8.2.4.5
33//
34#define CXL_HDM_DECODER_VERSION_30 0x3
35
36//
37// CXL CXL HDM Decoder n Control
38// Compute Express Link Specification Revision 3.0 - 8.2.4.19.7
39//
40//
41// Bit4..7: Interleave Ways (IW)
42//
43#define CXL_HDM_16_WAY_INTERLEAVING 0x4
44#define CXL_HDM_3_WAY_INTERLEAVING 0x8
45#define CXL_HDM_6_WAY_INTERLEAVING 0x9
46#define CXL_HDM_12_WAY_INTERLEAVING 0xA
47
48//
49// Ensure proper structure formats
50//
51#pragma pack(1)
52
53//
54// CXL.cachemem Extended Register Capability
55// Compute Express Link Specification Revision 3.0 - Chapter 8.2.4.24
56//
57typedef union {
58 struct {
59 UINT32 ExtendedRangesBitmap : 16; // Bit 0..15
60 UINT32 Reserved : 16; // Bit 16..31
61 } Bits;
62 UINT32 Uint32;
63} CXL_CM_EXTENTED_REGISTER_CAPABILITY;
64
65#define CXL_CM_EXTENTED_RANGES_BITMAP (BIT2 | BIT3 | BIT4 | BIT5 | BIT6 | BIT7 | BIT8 | BIT9 | BIT10 | BIT11 | BIT12 | BIT13 | BIT15)
66
67//
68// CXL BI Route Table Capability
69// Compute Express Link Specification Revision 3.0 - Chapter 8.2.4.25
70//
71typedef union {
72 struct {
73 UINT32 ExplicitBiRtCommitRequired : 1; // bit 0
74 UINT32 Reserved : 31; // bit 1..31
75 } Bits;
76 UINT32 Uint32;
77} CXL_BI_RT_CAPABILITY;
78
79typedef union {
80 struct {
81 UINT32 BiRtCommit : 1; // bit 0
82 UINT32 Reserved : 31; // bit 1..31
83 } Bits;
84 UINT32 Uint32;
85} CXL_BI_RT_CONTROL;
86
87typedef union {
88 struct {
89 UINT32 BiRtCommitted : 1; // bit 0
90 UINT32 BiRtErrorNotCommitted : 1; // bit 1
91 UINT32 Reserved1 : 6; // bit 2..7
92 UINT32 BiRtCommitTimeoutScale : 4; // bit 8..11
93 UINT32 BiRtCommitTimeoutBase : 4; // bit 12..15
94 UINT32 Reserved2 : 16; // bit 16..31
95 } Bits;
96 UINT32 Uint32;
97} CXL_BI_RT_STATUS;
98
99typedef struct {
100 CXL_BI_RT_CAPABILITY BiRtCap; // offset 0x00
101 CXL_BI_RT_CONTROL BiRtControl; // offset 0x04
102 CXL_BI_RT_STATUS BiRtStatus; // offset 0x08
103} CXL_BI_ROUTE_TABLE_CAPABILITY;
104
105//
106// CXL BI Decoder Capability
107// Compute Express Link Specification Revision 3.0 - Chapter 8.2.4.26
108//
109typedef union {
110 struct {
111 UINT32 HdmDCapable : 1; // bit 0
112 UINT32 ExplicitBiDecoderCommitRequired : 1; // bit 1
113 UINT32 Reserved : 30; // bit 2..31
114 } Bits;
115 UINT32 Uint32;
116} CXL_BI_DECODER_CAP;
117
118typedef union {
119 struct {
120 UINT32 BiForward : 1; // bit 0
121 UINT32 BiEnable : 1; // bit 1
122 UINT32 BiDecoderCommit : 1; // bit 2
123 UINT32 Reserved : 29; // bit 3..31
124 } Bits;
125 UINT32 Uint32;
126} CXL_BI_DECODER_CONTROL;
127
128typedef union {
129 struct {
130 UINT32 BiDecoderCommitted : 1; // bit 0
131 UINT32 BiDecoderErrorNotCommitted : 1; // bit 1
132 UINT32 Reserved1 : 6; // bit 2..7
133 UINT32 BiDecoderCommitTimeoutScale : 4; // bit 8..11
134 UINT32 BiDecoderCommitTimeoutBase : 4; // bit 12..15
135 UINT32 Reserved2 : 16; // bit 16..31
136 } Bits;
137 UINT32 Uint32;
138} CXL_BI_DECODER_STATUS;
139
140typedef struct {
141 CXL_BI_DECODER_CAP BiDecoderCap; // offset 0x00
142 CXL_BI_DECODER_CONTROL BiDecoderControl; // offset 0x04
143 CXL_BI_DECODER_STATUS BiDecoderStatus; // offset 0x08
144} CXL_BI_DECODER_CAPABILITY;
145
146//
147// CXL Cache ID Route Table Capability
148// Compute Express Link Specification Revision 3.0 - Chapter 8.2.4.27
149//
150typedef union {
151 struct {
152 UINT32 CacheIdTargetCount : 5; // Bit 0..4
153 UINT32 Reserved1 : 3; // Bit 5..7
154 UINT32 HdmDType2DeviceMaxCount : 4; // Bit 8..11
155 UINT32 Reserved2 : 4; // Bit 12..15
156 UINT32 ExplicitCacheIdRtCommitRequired : 1; // Bit 16
157 UINT32 Reserved3 : 15; // Bit 17:31
158 } Bits;
159 UINT32 Uint32;
160} CXL_CACHE_ID_RT_CAPABILITY;
161
162typedef union {
163 struct {
164 UINT32 CacheIdRtCommit : 1; // Bit 0
165 UINT32 Reserved : 31; // Bit 1..31
166 } Bits;
167 UINT32 Uint32;
168} CXL_CACHE_ID_RT_CONTROL;
169
170typedef union {
171 struct {
172 UINT32 CacheIdRtCommitted : 1; // Bit 0
173 UINT32 CacheIdRtErrNotCommitted : 1; // Bit 1
174 UINT32 Reserved1 : 6; // Bit 2..7
175 UINT32 CacheIdRtCommitTimeoutScale : 4; // Bit 8..11
176 UINT32 CacheIdRtCommitTimeoutBase : 4; // Bit 12..15
177 UINT32 Reserved2 : 16; // Bit 16..31
178 } Bits;
179 UINT32 Uint32;
180} CXL_CACHE_ID_RT_STATUS;
181
182typedef union {
183 struct {
184 UINT16 Valid : 1; // Bit 0
185 UINT16 Reserved : 7; // Bit 1..7
186 UINT16 PortNumber : 8; // Bit 8..15
187 } Bits;
188 UINT16 Uint16;
189} CXL_CACHE_ID_RT_TARGET;
190
191typedef struct {
192 CXL_CACHE_ID_RT_CAPABILITY CacheIdRtCap; // offset 0x00
193 CXL_CACHE_ID_RT_CONTROL CacheIdRtControl; // offset 0x04
194 CXL_CACHE_ID_RT_STATUS CacheIdRtStatus; // offset 0x08
195 UINT32 Reserved; // offset 0x0C
196 CXL_CACHE_ID_RT_TARGET CacheIdRtTarget[]; // offset 0x10
197} CXL_CACHE_ID_ROUTE_TABLE_CAPABILITY;
198
199//
200// CXL Cache ID Decoder Capability
201// Compute Express Link Specification Revision 3.0 - Chapter 8.2.4.28
202//
203typedef union {
204 struct {
205 UINT32 ExplicitCacheIdDecoderCommitRequired : 1; // Bit 0
206 UINT32 Reserved : 31; // Bit 1..31
207 } Bits;
208 UINT32 Uint32;
209} CXL_CACHE_ID_DECODER_CAP;
210
211typedef union {
212 struct {
213 UINT32 ForwardCacheId : 1; // Bit 0
214 UINT32 AssignCacheId : 1; // Bit 1
215 UINT32 HdmDType2DevicePresent : 1; // Bit 2
216 UINT32 CacheIdDecoderCommit : 1; // Bit 3
217 UINT32 Reserved1 : 4; // Bit 4..7
218 UINT32 HdmDType2DeviceCacheId : 4; // Bit 8..11
219 UINT32 Reserved2 : 4; // Bit 12..15
220 UINT32 LocalCacheId : 4; // Bit 16..19
221 UINT32 Reserved3 : 4; // Bit 20..23
222 UINT32 TrustLevel : 2; // Bit 24..25
223 UINT32 Reserved4 : 6; // Bit 26..31
224 } Bits;
225 UINT32 Uint32;
226} CXL_CACHE_ID_DECODER_CONTROL;
227
228typedef union {
229 struct {
230 UINT32 CacheIdDecoderCommitted : 1; // Bit 0
231 UINT32 CacheIdDecoderErrorNotCommitted : 1; // Bit 1
232 UINT32 Reserved1 : 6; // Bit 2..7
233 UINT32 CacheIdDecoderCommitTimeoutScale : 4; // Bit 8..11
234 UINT32 CacheIdDecoderCommitTimeoutBase : 4; // Bit 12..15
235 UINT32 Reserved2 : 16; // Bit 16..31
236 } Bits;
237 UINT32 Uint32;
238} CXL_CACHE_ID_DECODER_STATUS;
239
240typedef struct {
241 CXL_CACHE_ID_DECODER_CAP CacheIdDecoderCap; // offset 0x00
242 CXL_CACHE_ID_DECODER_CONTROL CacheIdDecoderControl; // offset 0x04
243 CXL_CACHE_ID_DECODER_STATUS CacheIdDecoderStatus; // offset 0x08
244} CXL_CACHE_ID_DECODER_CAPABILITY;
245
246//
247// CXL Timeout and Isolation Capability Structure
248// Compute Express Link Specification Revision 3.0 - Chapter 8.2.4.23
249//
250typedef union {
251 struct {
252 UINT32 CxlmemTransactionTimeoutRangesSupported : 4; // Bits 3:0
253 UINT32 CxlmemTransactionTimeoutSupported : 1; // Bits 4
254 UINT32 Reserved1 : 3; // Bits 7:5
255 UINT32 CxlcacheTransactionTimeoutRangesSupported : 4; // Bits 11:8
256 UINT32 CxlcacheTransactionTimeoutSupported : 1; // Bits 12
257 UINT32 Reserved2 : 3; // Bits 15:13
258 UINT32 CxlmemIsolationSupported : 1; // Bits 16
259 UINT32 CxlmemIsolationLinkdownSupported : 1; // Bits 17
260 UINT32 CxlcacheIsolationSupported : 1; // Bits 18
261 UINT32 CxlcacheIsolationLinkdownSupported : 1; // Bits 19
262 UINT32 Reserved3 : 5; // Bits 24:20
263 UINT32 IsolationErrCorSignalingSupported : 1; // Bits 25
264 UINT32 IsolationInterruptSupported : 1; // Bits 26
265 UINT32 IsolationInterruptMessageNumber : 5; // Bits 31:27
266 } Bits;
267 UINT32 Uint32;
268} CXL_3_0_CXL_TIMEOUT_AND_ISOLATION_CAPABILITY;
269
270typedef union {
271 struct {
272 UINT32 CxlmemTransactionTimeoutValue : 4; // Bits 3:0
273 UINT32 CxlmemTransactionTimeoutEnable : 1; // Bits 4
274 UINT32 Reserved1 : 3; // Bits 7:5
275 UINT32 CxlcacheTransactionTimeoutValue : 4; // Bits 11:8
276 UINT32 CxlcacheTransactionTimeoutEnable : 1; // Bits 12
277 UINT32 Reserved2 : 3; // Bits 15:13
278 UINT32 CxlmemIsolationEnable : 1; // Bits 16
279 UINT32 CxlmemIsolationLinkdownEnable : 1; // Bits 17
280 UINT32 CxlcacheIsolationEnable : 1; // Bits 18
281 UINT32 CxlcacheIsolationLinkdownEnable : 1; // Bits 19
282 UINT32 Reserved3 : 5; // Bits 24:20
283 UINT32 IsolationErrCorSignalingEnable : 1; // Bits 25
284 UINT32 IsolationInterruptEnable : 1; // Bits 26
285 UINT32 Reserved4 : 5; // Bits 31:27
286 } Bits;
287 UINT32 Uint32;
288} CXL_3_0_CXL_TIMEOUT_AND_ISOLATION_CONTROL;
289
290typedef union {
291 struct {
292 UINT32 CxlmemTransactionTimeout : 1; // Bits 0
293 UINT32 Reserved1 : 3; // Bits 3:1
294 UINT32 CxlcacheTransactionTimeout : 1; // Bits 4
295 UINT32 Reserved2 : 3; // Bits 7:5
296 UINT32 CxlmemIsolationStatus : 1; // Bits 8
297 UINT32 CxlmemIsolationLinkdownStatus : 1; // Bits 9
298 UINT32 Reserved3 : 2; // Bits 11:10
299 UINT32 CxlcacheIsolationStatus : 1; // Bits 12
300 UINT32 CxlcacheIsolationLinkdownStatus : 1; // Bits 13
301 UINT32 CxlRpBusy : 1; // Bits 14
302 UINT32 Reserved4 : 17; // Bits 31:15
303 } Bits;
304 UINT32 Uint32;
305} CXL_3_0_CXL_TIMEOUT_AND_ISOLATION_STATUS;
306
307typedef struct {
308 CXL_3_0_CXL_TIMEOUT_AND_ISOLATION_CAPABILITY TimeoutAndIsolationCap;
309 UINT32 Reserved;
310 CXL_3_0_CXL_TIMEOUT_AND_ISOLATION_CONTROL TimeoutAndIsolationControl;
311 CXL_3_0_CXL_TIMEOUT_AND_ISOLATION_STATUS TimeoutAndIsolationStatus;
312} CXL_3_0_CXL_TIMEOUT_AND_ISOLATION_CAPABILITY_STRUCTURE;
313
314#pragma pack()
315
316#endif
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