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source: vbox/trunk/src/VBox/Devices/EFI/Firmware/MdePkg/Include/IndustryStandard/Pci22.h@ 58466

Last change on this file since 58466 was 58466, checked in by vboxsync, 9 years ago

EFI/Firmware: Merged in the svn:eol-style, svn:mime-type and trailing whitespace cleanup that was done after the initial UDK2014.SP1 import: svn merge /vendor/edk2/UDK2014.SP1 /vendor/edk2/current .
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1/** @file
2 Support for PCI 2.2 standard.
3
4 This file includes the definitions in the following specifications,
5 PCI Local Bus Specification, 2.2
6 PCI-to-PCI Bridge Architecture Specification, Revision 1.2
7 PC Card Standard, 8.0
8
9
10
11 Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>
12 Copyright (c) 2014, Hewlett-Packard Development Company, L.P.<BR>
13 This program and the accompanying materials
14 are licensed and made available under the terms and conditions of the BSD License
15 which accompanies this distribution. The full text of the license may be found at
16 http://opensource.org/licenses/bsd-license.php
17
18 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
19 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
20
21**/
22
23#ifndef _PCI22_H_
24#define _PCI22_H_
25
26#define PCI_MAX_BUS 255
27#define PCI_MAX_DEVICE 31
28#define PCI_MAX_FUNC 7
29
30#pragma pack(1)
31
32///
33/// Common header region in PCI Configuration Space
34/// Section 6.1, PCI Local Bus Specification, 2.2
35///
36typedef struct {
37 UINT16 VendorId;
38 UINT16 DeviceId;
39 UINT16 Command;
40 UINT16 Status;
41 UINT8 RevisionID;
42 UINT8 ClassCode[3];
43 UINT8 CacheLineSize;
44 UINT8 LatencyTimer;
45 UINT8 HeaderType;
46 UINT8 BIST;
47} PCI_DEVICE_INDEPENDENT_REGION;
48
49///
50/// PCI Device header region in PCI Configuration Space
51/// Section 6.1, PCI Local Bus Specification, 2.2
52///
53typedef struct {
54 UINT32 Bar[6];
55 UINT32 CISPtr;
56 UINT16 SubsystemVendorID;
57 UINT16 SubsystemID;
58 UINT32 ExpansionRomBar;
59 UINT8 CapabilityPtr;
60 UINT8 Reserved1[3];
61 UINT32 Reserved2;
62 UINT8 InterruptLine;
63 UINT8 InterruptPin;
64 UINT8 MinGnt;
65 UINT8 MaxLat;
66} PCI_DEVICE_HEADER_TYPE_REGION;
67
68///
69/// PCI Device Configuration Space
70/// Section 6.1, PCI Local Bus Specification, 2.2
71///
72typedef struct {
73 PCI_DEVICE_INDEPENDENT_REGION Hdr;
74 PCI_DEVICE_HEADER_TYPE_REGION Device;
75} PCI_TYPE00;
76
77///
78/// PCI-PCI Bridge header region in PCI Configuration Space
79/// Section 3.2, PCI-PCI Bridge Architecture, Version 1.2
80///
81typedef struct {
82 UINT32 Bar[2];
83 UINT8 PrimaryBus;
84 UINT8 SecondaryBus;
85 UINT8 SubordinateBus;
86 UINT8 SecondaryLatencyTimer;
87 UINT8 IoBase;
88 UINT8 IoLimit;
89 UINT16 SecondaryStatus;
90 UINT16 MemoryBase;
91 UINT16 MemoryLimit;
92 UINT16 PrefetchableMemoryBase;
93 UINT16 PrefetchableMemoryLimit;
94 UINT32 PrefetchableBaseUpper32;
95 UINT32 PrefetchableLimitUpper32;
96 UINT16 IoBaseUpper16;
97 UINT16 IoLimitUpper16;
98 UINT8 CapabilityPtr;
99 UINT8 Reserved[3];
100 UINT32 ExpansionRomBAR;
101 UINT8 InterruptLine;
102 UINT8 InterruptPin;
103 UINT16 BridgeControl;
104} PCI_BRIDGE_CONTROL_REGISTER;
105
106///
107/// PCI-to-PCI Bridge Configuration Space
108/// Section 3.2, PCI-PCI Bridge Architecture, Version 1.2
109///
110typedef struct {
111 PCI_DEVICE_INDEPENDENT_REGION Hdr;
112 PCI_BRIDGE_CONTROL_REGISTER Bridge;
113} PCI_TYPE01;
114
115typedef union {
116 PCI_TYPE00 Device;
117 PCI_TYPE01 Bridge;
118} PCI_TYPE_GENERIC;
119
120///
121/// CardBus Conroller Configuration Space,
122/// Section 4.5.1, PC Card Standard. 8.0
123///
124typedef struct {
125 UINT32 CardBusSocketReg; ///< Cardus Socket/ExCA Base
126 UINT8 Cap_Ptr;
127 UINT8 Reserved;
128 UINT16 SecondaryStatus; ///< Secondary Status
129 UINT8 PciBusNumber; ///< PCI Bus Number
130 UINT8 CardBusBusNumber; ///< CardBus Bus Number
131 UINT8 SubordinateBusNumber; ///< Subordinate Bus Number
132 UINT8 CardBusLatencyTimer; ///< CardBus Latency Timer
133 UINT32 MemoryBase0; ///< Memory Base Register 0
134 UINT32 MemoryLimit0; ///< Memory Limit Register 0
135 UINT32 MemoryBase1;
136 UINT32 MemoryLimit1;
137 UINT32 IoBase0;
138 UINT32 IoLimit0; ///< I/O Base Register 0
139 UINT32 IoBase1; ///< I/O Limit Register 0
140 UINT32 IoLimit1;
141 UINT8 InterruptLine; ///< Interrupt Line
142 UINT8 InterruptPin; ///< Interrupt Pin
143 UINT16 BridgeControl; ///< Bridge Control
144} PCI_CARDBUS_CONTROL_REGISTER;
145
146//
147// Definitions of PCI class bytes and manipulation macros.
148//
149#define PCI_CLASS_OLD 0x00
150#define PCI_CLASS_OLD_OTHER 0x00
151#define PCI_CLASS_OLD_VGA 0x01
152
153#define PCI_CLASS_MASS_STORAGE 0x01
154#define PCI_CLASS_MASS_STORAGE_SCSI 0x00
155#define PCI_CLASS_MASS_STORAGE_IDE 0x01
156#define PCI_CLASS_MASS_STORAGE_FLOPPY 0x02
157#define PCI_CLASS_MASS_STORAGE_IPI 0x03
158#define PCI_CLASS_MASS_STORAGE_RAID 0x04
159#define PCI_CLASS_MASS_STORAGE_OTHER 0x80
160
161#define PCI_CLASS_NETWORK 0x02
162#define PCI_CLASS_NETWORK_ETHERNET 0x00
163#define PCI_CLASS_NETWORK_TOKENRING 0x01
164#define PCI_CLASS_NETWORK_FDDI 0x02
165#define PCI_CLASS_NETWORK_ATM 0x03
166#define PCI_CLASS_NETWORK_ISDN 0x04
167#define PCI_CLASS_NETWORK_OTHER 0x80
168
169#define PCI_CLASS_DISPLAY 0x03
170#define PCI_CLASS_DISPLAY_VGA 0x00
171#define PCI_IF_VGA_VGA 0x00
172#define PCI_IF_VGA_8514 0x01
173#define PCI_CLASS_DISPLAY_XGA 0x01
174#define PCI_CLASS_DISPLAY_3D 0x02
175#define PCI_CLASS_DISPLAY_OTHER 0x80
176
177#define PCI_CLASS_MEDIA 0x04
178#define PCI_CLASS_MEDIA_VIDEO 0x00
179#define PCI_CLASS_MEDIA_AUDIO 0x01
180#define PCI_CLASS_MEDIA_TELEPHONE 0x02
181#define PCI_CLASS_MEDIA_OTHER 0x80
182
183#define PCI_CLASS_MEMORY_CONTROLLER 0x05
184#define PCI_CLASS_MEMORY_RAM 0x00
185#define PCI_CLASS_MEMORY_FLASH 0x01
186#define PCI_CLASS_MEMORY_OTHER 0x80
187
188#define PCI_CLASS_BRIDGE 0x06
189#define PCI_CLASS_BRIDGE_HOST 0x00
190#define PCI_CLASS_BRIDGE_ISA 0x01
191#define PCI_CLASS_BRIDGE_EISA 0x02
192#define PCI_CLASS_BRIDGE_MCA 0x03
193#define PCI_CLASS_BRIDGE_P2P 0x04
194#define PCI_IF_BRIDGE_P2P 0x00
195#define PCI_IF_BRIDGE_P2P_SUBTRACTIVE 0x01
196#define PCI_CLASS_BRIDGE_PCMCIA 0x05
197#define PCI_CLASS_BRIDGE_NUBUS 0x06
198#define PCI_CLASS_BRIDGE_CARDBUS 0x07
199#define PCI_CLASS_BRIDGE_RACEWAY 0x08
200#define PCI_CLASS_BRIDGE_OTHER 0x80
201#define PCI_CLASS_BRIDGE_ISA_PDECODE 0x80
202
203#define PCI_CLASS_SCC 0x07 ///< Simple communications controllers
204#define PCI_SUBCLASS_SERIAL 0x00
205#define PCI_IF_GENERIC_XT 0x00
206#define PCI_IF_16450 0x01
207#define PCI_IF_16550 0x02
208#define PCI_IF_16650 0x03
209#define PCI_IF_16750 0x04
210#define PCI_IF_16850 0x05
211#define PCI_IF_16950 0x06
212#define PCI_SUBCLASS_PARALLEL 0x01
213#define PCI_IF_PARALLEL_PORT 0x00
214#define PCI_IF_BI_DIR_PARALLEL_PORT 0x01
215#define PCI_IF_ECP_PARALLEL_PORT 0x02
216#define PCI_IF_1284_CONTROLLER 0x03
217#define PCI_IF_1284_DEVICE 0xFE
218#define PCI_SUBCLASS_MULTIPORT_SERIAL 0x02
219#define PCI_SUBCLASS_MODEM 0x03
220#define PCI_IF_GENERIC_MODEM 0x00
221#define PCI_IF_16450_MODEM 0x01
222#define PCI_IF_16550_MODEM 0x02
223#define PCI_IF_16650_MODEM 0x03
224#define PCI_IF_16750_MODEM 0x04
225#define PCI_SUBCLASS_SCC_OTHER 0x80
226
227#define PCI_CLASS_SYSTEM_PERIPHERAL 0x08
228#define PCI_SUBCLASS_PIC 0x00
229#define PCI_IF_8259_PIC 0x00
230#define PCI_IF_ISA_PIC 0x01
231#define PCI_IF_EISA_PIC 0x02
232#define PCI_IF_APIC_CONTROLLER 0x10 ///< I/O APIC interrupt controller , 32 bye none-prefectable memory.
233#define PCI_IF_APIC_CONTROLLER2 0x20
234#define PCI_SUBCLASS_DMA 0x01
235#define PCI_IF_8237_DMA 0x00
236#define PCI_IF_ISA_DMA 0x01
237#define PCI_IF_EISA_DMA 0x02
238#define PCI_SUBCLASS_TIMER 0x02
239#define PCI_IF_8254_TIMER 0x00
240#define PCI_IF_ISA_TIMER 0x01
241#define PCI_IF_EISA_TIMER 0x02
242#define PCI_SUBCLASS_RTC 0x03
243#define PCI_IF_GENERIC_RTC 0x00
244#define PCI_IF_ISA_RTC 0x01
245#define PCI_SUBCLASS_PNP_CONTROLLER 0x04 ///< HotPlug Controller
246#define PCI_SUBCLASS_PERIPHERAL_OTHER 0x80
247
248#define PCI_CLASS_INPUT_DEVICE 0x09
249#define PCI_SUBCLASS_KEYBOARD 0x00
250#define PCI_SUBCLASS_PEN 0x01
251#define PCI_SUBCLASS_MOUSE_CONTROLLER 0x02
252#define PCI_SUBCLASS_SCAN_CONTROLLER 0x03
253#define PCI_SUBCLASS_GAMEPORT 0x04
254#define PCI_IF_GAMEPORT 0x00
255#define PCI_IF_GAMEPORT1 0x10
256#define PCI_SUBCLASS_INPUT_OTHER 0x80
257
258#define PCI_CLASS_DOCKING_STATION 0x0A
259#define PCI_SUBCLASS_DOCKING_GENERIC 0x00
260#define PCI_SUBCLASS_DOCKING_OTHER 0x80
261
262#define PCI_CLASS_PROCESSOR 0x0B
263#define PCI_SUBCLASS_PROC_386 0x00
264#define PCI_SUBCLASS_PROC_486 0x01
265#define PCI_SUBCLASS_PROC_PENTIUM 0x02
266#define PCI_SUBCLASS_PROC_ALPHA 0x10
267#define PCI_SUBCLASS_PROC_POWERPC 0x20
268#define PCI_SUBCLASS_PROC_MIPS 0x30
269#define PCI_SUBCLASS_PROC_CO_PORC 0x40 ///< Co-Processor
270
271#define PCI_CLASS_SERIAL 0x0C
272#define PCI_CLASS_SERIAL_FIREWIRE 0x00
273#define PCI_IF_1394 0x00
274#define PCI_IF_1394_OPEN_HCI 0x10
275#define PCI_CLASS_SERIAL_ACCESS_BUS 0x01
276#define PCI_CLASS_SERIAL_SSA 0x02
277#define PCI_CLASS_SERIAL_USB 0x03
278#define PCI_IF_UHCI 0x00
279#define PCI_IF_OHCI 0x10
280#define PCI_IF_USB_OTHER 0x80
281#define PCI_IF_USB_DEVICE 0xFE
282#define PCI_CLASS_SERIAL_FIBRECHANNEL 0x04
283#define PCI_CLASS_SERIAL_SMB 0x05
284
285#define PCI_CLASS_WIRELESS 0x0D
286#define PCI_SUBCLASS_IRDA 0x00
287#define PCI_SUBCLASS_IR 0x01
288#define PCI_SUBCLASS_RF 0x10
289#define PCI_SUBCLASS_WIRELESS_OTHER 0x80
290
291#define PCI_CLASS_INTELLIGENT_IO 0x0E
292
293#define PCI_CLASS_SATELLITE 0x0F
294#define PCI_SUBCLASS_TV 0x01
295#define PCI_SUBCLASS_AUDIO 0x02
296#define PCI_SUBCLASS_VOICE 0x03
297#define PCI_SUBCLASS_DATA 0x04
298
299#define PCI_SECURITY_CONTROLLER 0x10 ///< Encryption and decryption controller
300#define PCI_SUBCLASS_NET_COMPUT 0x00
301#define PCI_SUBCLASS_ENTERTAINMENT 0x10
302#define PCI_SUBCLASS_SECURITY_OTHER 0x80
303
304#define PCI_CLASS_DPIO 0x11
305#define PCI_SUBCLASS_DPIO 0x00
306#define PCI_SUBCLASS_DPIO_OTHER 0x80
307
308/**
309 Macro that checks whether the Base Class code of device matched.
310
311 @param _p Specified device.
312 @param c Base Class code needs matching.
313
314 @retval TRUE Base Class code matches the specified device.
315 @retval FALSE Base Class code doesn't match the specified device.
316
317**/
318#define IS_CLASS1(_p, c) ((_p)->Hdr.ClassCode[2] == (c))
319/**
320 Macro that checks whether the Base Class code and Sub-Class code of device matched.
321
322 @param _p Specified device.
323 @param c Base Class code needs matching.
324 @param s Sub-Class code needs matching.
325
326 @retval TRUE Base Class code and Sub-Class code match the specified device.
327 @retval FALSE Base Class code and Sub-Class code don't match the specified device.
328
329**/
330#define IS_CLASS2(_p, c, s) (IS_CLASS1 (_p, c) && ((_p)->Hdr.ClassCode[1] == (s)))
331/**
332 Macro that checks whether the Base Class code, Sub-Class code and Interface code of device matched.
333
334 @param _p Specified device.
335 @param c Base Class code needs matching.
336 @param s Sub-Class code needs matching.
337 @param p Interface code needs matching.
338
339 @retval TRUE Base Class code, Sub-Class code and Interface code match the specified device.
340 @retval FALSE Base Class code, Sub-Class code and Interface code don't match the specified device.
341
342**/
343#define IS_CLASS3(_p, c, s, p) (IS_CLASS2 (_p, c, s) && ((_p)->Hdr.ClassCode[0] == (p)))
344
345/**
346 Macro that checks whether device is a display controller.
347
348 @param _p Specified device.
349
350 @retval TRUE Device is a display controller.
351 @retval FALSE Device is not a display controller.
352
353**/
354#define IS_PCI_DISPLAY(_p) IS_CLASS1 (_p, PCI_CLASS_DISPLAY)
355/**
356 Macro that checks whether device is a VGA-compatible controller.
357
358 @param _p Specified device.
359
360 @retval TRUE Device is a VGA-compatible controller.
361 @retval FALSE Device is not a VGA-compatible controller.
362
363**/
364#define IS_PCI_VGA(_p) IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, PCI_IF_VGA_VGA)
365/**
366 Macro that checks whether device is an 8514-compatible controller.
367
368 @param _p Specified device.
369
370 @retval TRUE Device is an 8514-compatible controller.
371 @retval FALSE Device is not an 8514-compatible controller.
372
373**/
374#define IS_PCI_8514(_p) IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, PCI_IF_VGA_8514)
375/**
376 Macro that checks whether device is built before the Class Code field was defined.
377
378 @param _p Specified device.
379
380 @retval TRUE Device is an old device.
381 @retval FALSE Device is not an old device.
382
383**/
384#define IS_PCI_OLD(_p) IS_CLASS1 (_p, PCI_CLASS_OLD)
385/**
386 Macro that checks whether device is a VGA-compatible device built before the Class Code field was defined.
387
388 @param _p Specified device.
389
390 @retval TRUE Device is an old VGA-compatible device.
391 @retval FALSE Device is not an old VGA-compatible device.
392
393**/
394#define IS_PCI_OLD_VGA(_p) IS_CLASS2 (_p, PCI_CLASS_OLD, PCI_CLASS_OLD_VGA)
395/**
396 Macro that checks whether device is an IDE controller.
397
398 @param _p Specified device.
399
400 @retval TRUE Device is an IDE controller.
401 @retval FALSE Device is not an IDE controller.
402
403**/
404#define IS_PCI_IDE(_p) IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_IDE)
405/**
406 Macro that checks whether device is a SCSI bus controller.
407
408 @param _p Specified device.
409
410 @retval TRUE Device is a SCSI bus controller.
411 @retval FALSE Device is not a SCSI bus controller.
412
413**/
414#define IS_PCI_SCSI(_p) IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_SCSI)
415/**
416 Macro that checks whether device is a RAID controller.
417
418 @param _p Specified device.
419
420 @retval TRUE Device is a RAID controller.
421 @retval FALSE Device is not a RAID controller.
422
423**/
424#define IS_PCI_RAID(_p) IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_RAID)
425/**
426 Macro that checks whether device is an ISA bridge.
427
428 @param _p Specified device.
429
430 @retval TRUE Device is an ISA bridge.
431 @retval FALSE Device is not an ISA bridge.
432
433**/
434#define IS_PCI_LPC(_p) IS_CLASS2 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_ISA)
435/**
436 Macro that checks whether device is a PCI-to-PCI bridge.
437
438 @param _p Specified device.
439
440 @retval TRUE Device is a PCI-to-PCI bridge.
441 @retval FALSE Device is not a PCI-to-PCI bridge.
442
443**/
444#define IS_PCI_P2P(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, PCI_IF_BRIDGE_P2P)
445/**
446 Macro that checks whether device is a Subtractive Decode PCI-to-PCI bridge.
447
448 @param _p Specified device.
449
450 @retval TRUE Device is a Subtractive Decode PCI-to-PCI bridge.
451 @retval FALSE Device is not a Subtractive Decode PCI-to-PCI bridge.
452
453**/
454#define IS_PCI_P2P_SUB(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, PCI_IF_BRIDGE_P2P_SUBTRACTIVE)
455/**
456 Macro that checks whether device is a 16550-compatible serial controller.
457
458 @param _p Specified device.
459
460 @retval TRUE Device is a 16550-compatible serial controller.
461 @retval FALSE Device is not a 16550-compatible serial controller.
462
463**/
464#define IS_PCI_16550_SERIAL(_p) IS_CLASS3 (_p, PCI_CLASS_SCC, PCI_SUBCLASS_SERIAL, PCI_IF_16550)
465/**
466 Macro that checks whether device is a Universal Serial Bus controller.
467
468 @param _p Specified device.
469
470 @retval TRUE Device is a Universal Serial Bus controller.
471 @retval FALSE Device is not a Universal Serial Bus controller.
472
473**/
474#define IS_PCI_USB(_p) IS_CLASS2 (_p, PCI_CLASS_SERIAL, PCI_CLASS_SERIAL_USB)
475
476//
477// the definition of Header Type
478//
479#define HEADER_TYPE_DEVICE 0x00
480#define HEADER_TYPE_PCI_TO_PCI_BRIDGE 0x01
481#define HEADER_TYPE_CARDBUS_BRIDGE 0x02
482#define HEADER_TYPE_MULTI_FUNCTION 0x80
483//
484// Mask of Header type
485//
486#define HEADER_LAYOUT_CODE 0x7f
487/**
488 Macro that checks whether device is a PCI-PCI bridge.
489
490 @param _p Specified device.
491
492 @retval TRUE Device is a PCI-PCI bridge.
493 @retval FALSE Device is not a PCI-PCI bridge.
494
495**/
496#define IS_PCI_BRIDGE(_p) (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_PCI_TO_PCI_BRIDGE))
497/**
498 Macro that checks whether device is a CardBus bridge.
499
500 @param _p Specified device.
501
502 @retval TRUE Device is a CardBus bridge.
503 @retval FALSE Device is not a CardBus bridge.
504
505**/
506#define IS_CARDBUS_BRIDGE(_p) (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_CARDBUS_BRIDGE))
507/**
508 Macro that checks whether device is a multiple functions device.
509
510 @param _p Specified device.
511
512 @retval TRUE Device is a multiple functions device.
513 @retval FALSE Device is not a multiple functions device.
514
515**/
516#define IS_PCI_MULTI_FUNC(_p) ((_p)->Hdr.HeaderType & HEADER_TYPE_MULTI_FUNCTION)
517
518///
519/// Rom Base Address in Bridge, defined in PCI-to-PCI Bridge Architecure Specification,
520///
521#define PCI_BRIDGE_ROMBAR 0x38
522
523#define PCI_MAX_BAR 0x0006
524#define PCI_MAX_CONFIG_OFFSET 0x0100
525
526#define PCI_VENDOR_ID_OFFSET 0x00
527#define PCI_DEVICE_ID_OFFSET 0x02
528#define PCI_COMMAND_OFFSET 0x04
529#define PCI_PRIMARY_STATUS_OFFSET 0x06
530#define PCI_REVISION_ID_OFFSET 0x08
531#define PCI_CLASSCODE_OFFSET 0x09
532#define PCI_CACHELINE_SIZE_OFFSET 0x0C
533#define PCI_LATENCY_TIMER_OFFSET 0x0D
534#define PCI_HEADER_TYPE_OFFSET 0x0E
535#define PCI_BIST_OFFSET 0x0F
536#define PCI_BASE_ADDRESSREG_OFFSET 0x10
537#define PCI_CARDBUS_CIS_OFFSET 0x28
538#define PCI_SVID_OFFSET 0x2C ///< SubSystem Vendor id
539#define PCI_SUBSYSTEM_VENDOR_ID_OFFSET 0x2C
540#define PCI_SID_OFFSET 0x2E ///< SubSystem ID
541#define PCI_SUBSYSTEM_ID_OFFSET 0x2E
542#define PCI_EXPANSION_ROM_BASE 0x30
543#define PCI_CAPBILITY_POINTER_OFFSET 0x34
544#define PCI_INT_LINE_OFFSET 0x3C ///< Interrupt Line Register
545#define PCI_INT_PIN_OFFSET 0x3D ///< Interrupt Pin Register
546#define PCI_MAXGNT_OFFSET 0x3E ///< Max Grant Register
547#define PCI_MAXLAT_OFFSET 0x3F ///< Max Latency Register
548
549//
550// defined in PCI-to-PCI Bridge Architecture Specification
551//
552#define PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET 0x18
553#define PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET 0x19
554#define PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET 0x1a
555#define PCI_BRIDGE_STATUS_REGISTER_OFFSET 0x1E
556#define PCI_BRIDGE_CONTROL_REGISTER_OFFSET 0x3E
557
558///
559/// Interrupt Line "Unknown" or "No connection" value defined for x86 based system
560///
561#define PCI_INT_LINE_UNKNOWN 0xFF
562
563///
564/// PCI Access Data Format
565///
566typedef union {
567 struct {
568 UINT32 Reg : 8;
569 UINT32 Func : 3;
570 UINT32 Dev : 5;
571 UINT32 Bus : 8;
572 UINT32 Reserved : 7;
573 UINT32 Enable : 1;
574 } Bits;
575 UINT32 Uint32;
576} PCI_CONFIG_ACCESS_CF8;
577
578#pragma pack()
579
580#define EFI_PCI_COMMAND_IO_SPACE BIT0 ///< 0x0001
581#define EFI_PCI_COMMAND_MEMORY_SPACE BIT1 ///< 0x0002
582#define EFI_PCI_COMMAND_BUS_MASTER BIT2 ///< 0x0004
583#define EFI_PCI_COMMAND_SPECIAL_CYCLE BIT3 ///< 0x0008
584#define EFI_PCI_COMMAND_MEMORY_WRITE_AND_INVALIDATE BIT4 ///< 0x0010
585#define EFI_PCI_COMMAND_VGA_PALETTE_SNOOP BIT5 ///< 0x0020
586#define EFI_PCI_COMMAND_PARITY_ERROR_RESPOND BIT6 ///< 0x0040
587#define EFI_PCI_COMMAND_STEPPING_CONTROL BIT7 ///< 0x0080
588#define EFI_PCI_COMMAND_SERR BIT8 ///< 0x0100
589#define EFI_PCI_COMMAND_FAST_BACK_TO_BACK BIT9 ///< 0x0200
590
591//
592// defined in PCI-to-PCI Bridge Architecture Specification
593//
594#define EFI_PCI_BRIDGE_CONTROL_PARITY_ERROR_RESPONSE BIT0 ///< 0x0001
595#define EFI_PCI_BRIDGE_CONTROL_SERR BIT1 ///< 0x0002
596#define EFI_PCI_BRIDGE_CONTROL_ISA BIT2 ///< 0x0004
597#define EFI_PCI_BRIDGE_CONTROL_VGA BIT3 ///< 0x0008
598#define EFI_PCI_BRIDGE_CONTROL_VGA_16 BIT4 ///< 0x0010
599#define EFI_PCI_BRIDGE_CONTROL_MASTER_ABORT BIT5 ///< 0x0020
600#define EFI_PCI_BRIDGE_CONTROL_RESET_SECONDARY_BUS BIT6 ///< 0x0040
601#define EFI_PCI_BRIDGE_CONTROL_FAST_BACK_TO_BACK BIT7 ///< 0x0080
602#define EFI_PCI_BRIDGE_CONTROL_PRIMARY_DISCARD_TIMER BIT8 ///< 0x0100
603#define EFI_PCI_BRIDGE_CONTROL_SECONDARY_DISCARD_TIMER BIT9 ///< 0x0200
604#define EFI_PCI_BRIDGE_CONTROL_TIMER_STATUS BIT10 ///< 0x0400
605#define EFI_PCI_BRIDGE_CONTROL_DISCARD_TIMER_SERR BIT11 ///< 0x0800
606
607//
608// Following are the PCI-CARDBUS bridge control bit, defined in PC Card Standard
609//
610#define EFI_PCI_BRIDGE_CONTROL_IREQINT_ENABLE BIT7 ///< 0x0080
611#define EFI_PCI_BRIDGE_CONTROL_RANGE0_MEMORY_TYPE BIT8 ///< 0x0100
612#define EFI_PCI_BRIDGE_CONTROL_RANGE1_MEMORY_TYPE BIT9 ///< 0x0200
613#define EFI_PCI_BRIDGE_CONTROL_WRITE_POSTING_ENABLE BIT10 ///< 0x0400
614
615//
616// Following are the PCI status control bit
617//
618#define EFI_PCI_STATUS_CAPABILITY BIT4 ///< 0x0010
619#define EFI_PCI_STATUS_66MZ_CAPABLE BIT5 ///< 0x0020
620#define EFI_PCI_FAST_BACK_TO_BACK_CAPABLE BIT7 ///< 0x0080
621#define EFI_PCI_MASTER_DATA_PARITY_ERROR BIT8 ///< 0x0100
622
623///
624/// defined in PC Card Standard
625///
626#define EFI_PCI_CARDBUS_BRIDGE_CAPABILITY_PTR 0x14
627
628#pragma pack(1)
629//
630// PCI Capability List IDs and records
631//
632#define EFI_PCI_CAPABILITY_ID_PMI 0x01
633#define EFI_PCI_CAPABILITY_ID_AGP 0x02
634#define EFI_PCI_CAPABILITY_ID_VPD 0x03
635#define EFI_PCI_CAPABILITY_ID_SLOTID 0x04
636#define EFI_PCI_CAPABILITY_ID_MSI 0x05
637#define EFI_PCI_CAPABILITY_ID_HOTPLUG 0x06
638
639///
640/// Capabilities List Header
641/// Section 6.7, PCI Local Bus Specification, 2.2
642///
643typedef struct {
644 UINT8 CapabilityID;
645 UINT8 NextItemPtr;
646} EFI_PCI_CAPABILITY_HDR;
647
648///
649/// Power Management Register Block Definition
650/// Section 3.2, PCI Power Management Interface Specifiction, Revision 1.2
651///
652typedef struct {
653 EFI_PCI_CAPABILITY_HDR Hdr;
654 UINT16 PMC;
655 UINT16 PMCSR;
656 UINT8 BridgeExtention;
657 UINT8 Data;
658} EFI_PCI_CAPABILITY_PMI;
659
660///
661/// PMC - Power Management Capabilities
662/// Section 3.2.3, PCI Power Management Interface Specifiction, Revision 1.2
663///
664typedef union {
665 struct {
666 UINT16 Version : 3;
667 UINT16 PmeClock : 1;
668 UINT16 : 1;
669 UINT16 DeviceSpecificInitialization : 1;
670 UINT16 AuxCurrent : 3;
671 UINT16 D1Support : 1;
672 UINT16 D2Support : 1;
673 UINT16 PmeSupport : 5;
674 } Bits;
675 UINT16 Data;
676} EFI_PCI_PMC;
677
678#define EFI_PCI_PMC_D3_COLD_MASK (BIT15)
679
680///
681/// PMCSR - Power Management Control/Status
682/// Section 3.2.4, PCI Power Management Interface Specifiction, Revision 1.2
683///
684typedef union {
685 struct {
686 UINT16 PowerState : 2;
687 UINT16 : 6;
688 UINT16 PmeEnable : 1;
689 UINT16 DataSelect : 4;
690 UINT16 DataScale : 2;
691 UINT16 PmeStatus : 1;
692 } Bits;
693 UINT16 Data;
694} EFI_PCI_PMCSR;
695
696///
697/// A.G.P Capability
698/// Section 6.1.4, Accelerated Graphics Port Interface Specification, Revision 1.0
699///
700typedef struct {
701 EFI_PCI_CAPABILITY_HDR Hdr;
702 UINT8 Rev;
703 UINT8 Reserved;
704 UINT32 Status;
705 UINT32 Command;
706} EFI_PCI_CAPABILITY_AGP;
707
708///
709/// VPD Capability Structure
710/// Appendix I, PCI Local Bus Specification, 2.2
711///
712typedef struct {
713 EFI_PCI_CAPABILITY_HDR Hdr;
714 UINT16 AddrReg;
715 UINT32 DataReg;
716} EFI_PCI_CAPABILITY_VPD;
717
718///
719/// Slot Numbering Capabilities Register
720/// Section 3.2.6, PCI-to-PCI Bridge Architeture Specification, Revision 1.2
721///
722typedef struct {
723 EFI_PCI_CAPABILITY_HDR Hdr;
724 UINT8 ExpnsSlotReg;
725 UINT8 ChassisNo;
726} EFI_PCI_CAPABILITY_SLOTID;
727
728///
729/// Message Capability Structure for 32-bit Message Address
730/// Section 6.8.1, PCI Local Bus Specification, 2.2
731///
732typedef struct {
733 EFI_PCI_CAPABILITY_HDR Hdr;
734 UINT16 MsgCtrlReg;
735 UINT32 MsgAddrReg;
736 UINT16 MsgDataReg;
737} EFI_PCI_CAPABILITY_MSI32;
738
739///
740/// Message Capability Structure for 64-bit Message Address
741/// Section 6.8.1, PCI Local Bus Specification, 2.2
742///
743typedef struct {
744 EFI_PCI_CAPABILITY_HDR Hdr;
745 UINT16 MsgCtrlReg;
746 UINT32 MsgAddrRegLsdw;
747 UINT32 MsgAddrRegMsdw;
748 UINT16 MsgDataReg;
749} EFI_PCI_CAPABILITY_MSI64;
750
751///
752/// Capability EFI_PCI_CAPABILITY_ID_HOTPLUG,
753/// CompactPCI Hot Swap Specification PICMG 2.1, R1.0
754///
755typedef struct {
756 EFI_PCI_CAPABILITY_HDR Hdr;
757 ///
758 /// not finished - fields need to go here
759 ///
760} EFI_PCI_CAPABILITY_HOTPLUG;
761
762#define DEVICE_ID_NOCARE 0xFFFF
763
764#define PCI_ACPI_UNUSED 0
765#define PCI_BAR_NOCHANGE 0
766#define PCI_BAR_OLD_ALIGN 0xFFFFFFFFFFFFFFFFULL
767#define PCI_BAR_EVEN_ALIGN 0xFFFFFFFFFFFFFFFEULL
768#define PCI_BAR_SQUAD_ALIGN 0xFFFFFFFFFFFFFFFDULL
769#define PCI_BAR_DQUAD_ALIGN 0xFFFFFFFFFFFFFFFCULL
770
771#define PCI_BAR_IDX0 0x00
772#define PCI_BAR_IDX1 0x01
773#define PCI_BAR_IDX2 0x02
774#define PCI_BAR_IDX3 0x03
775#define PCI_BAR_IDX4 0x04
776#define PCI_BAR_IDX5 0x05
777#define PCI_BAR_ALL 0xFF
778
779///
780/// EFI PCI Option ROM definitions
781///
782#define EFI_ROOT_BRIDGE_LIST 'eprb'
783#define EFI_PCI_EXPANSION_ROM_HEADER_EFISIGNATURE 0x0EF1 ///< defined in UEFI Spec.
784
785#define PCI_EXPANSION_ROM_HEADER_SIGNATURE 0xaa55
786#define PCI_DATA_STRUCTURE_SIGNATURE SIGNATURE_32 ('P', 'C', 'I', 'R')
787#define PCI_CODE_TYPE_PCAT_IMAGE 0x00
788#define EFI_PCI_EXPANSION_ROM_HEADER_COMPRESSED 0x0001 ///< defined in UEFI spec.
789
790///
791/// Standard PCI Expansion ROM Header
792/// Section 13.4.2, Unified Extensible Firmware Interface Specification, Version 2.1
793///
794typedef struct {
795 UINT16 Signature; ///< 0xaa55
796 UINT8 Reserved[0x16];
797 UINT16 PcirOffset;
798} PCI_EXPANSION_ROM_HEADER;
799
800///
801/// Legacy ROM Header Extensions
802/// Section 6.3.3.1, PCI Local Bus Specification, 2.2
803///
804typedef struct {
805 UINT16 Signature; ///< 0xaa55
806 UINT8 Size512;
807 UINT8 InitEntryPoint[3];
808 UINT8 Reserved[0x12];
809 UINT16 PcirOffset;
810} EFI_LEGACY_EXPANSION_ROM_HEADER;
811
812///
813/// PCI Data Structure Format
814/// Section 6.3.1.2, PCI Local Bus Specification, 2.2
815///
816typedef struct {
817 UINT32 Signature; ///< "PCIR"
818 UINT16 VendorId;
819 UINT16 DeviceId;
820 UINT16 Reserved0;
821 UINT16 Length;
822 UINT8 Revision;
823 UINT8 ClassCode[3];
824 UINT16 ImageLength;
825 UINT16 CodeRevision;
826 UINT8 CodeType;
827 UINT8 Indicator;
828 UINT16 Reserved1;
829} PCI_DATA_STRUCTURE;
830
831///
832/// EFI PCI Expansion ROM Header
833/// Section 13.4.2, Unified Extensible Firmware Interface Specification, Version 2.1
834///
835typedef struct {
836 UINT16 Signature; ///< 0xaa55
837 UINT16 InitializationSize;
838 UINT32 EfiSignature; ///< 0x0EF1
839 UINT16 EfiSubsystem;
840 UINT16 EfiMachineType;
841 UINT16 CompressionType;
842 UINT8 Reserved[8];
843 UINT16 EfiImageHeaderOffset;
844 UINT16 PcirOffset;
845} EFI_PCI_EXPANSION_ROM_HEADER;
846
847typedef union {
848 UINT8 *Raw;
849 PCI_EXPANSION_ROM_HEADER *Generic;
850 EFI_PCI_EXPANSION_ROM_HEADER *Efi;
851 EFI_LEGACY_EXPANSION_ROM_HEADER *PcAt;
852} EFI_PCI_ROM_HEADER;
853
854#pragma pack()
855
856#endif
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