| 1 | /** @file
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| 2 | Support for the latest PCI standard.
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| 3 |
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| 4 | Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
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| 5 | This program and the accompanying materials
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| 6 | are licensed and made available under the terms and conditions of the BSD License
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| 7 | which accompanies this distribution. The full text of the license may be found at
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| 8 | http://opensource.org/licenses/bsd-license.php
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| 9 |
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| 10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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| 11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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| 12 |
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| 13 | **/
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| 14 |
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| 15 | #ifndef _PCIEXPRESS21_H_
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| 16 | #define _PCIEXPRESS21_H_
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| 17 |
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| 18 | #define EFI_PCIE_CAPABILITY_BASE_OFFSET 0x100
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| 19 | #define EFI_PCIE_CAPABILITY_ID_SRIOV_CONTROL_ARI_HIERARCHY 0x10
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| 20 | #define EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_OFFSET 0x24
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| 21 | #define EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_ARI_FORWARDING 0x20
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| 22 | #define EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_OFFSET 0x28
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| 23 | #define EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_ARI_FORWARDING 0x20
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| 24 |
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| 25 | //
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| 26 | // for SR-IOV
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| 27 | //
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| 28 | #define EFI_PCIE_CAPABILITY_ID_ARI 0x0E
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| 29 | #define EFI_PCIE_CAPABILITY_ID_ATS 0x0F
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| 30 | #define EFI_PCIE_CAPABILITY_ID_SRIOV 0x10
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| 31 | #define EFI_PCIE_CAPABILITY_ID_MRIOV 0x11
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| 32 |
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| 33 | typedef struct {
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| 34 | UINT32 CapabilityHeader;
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| 35 | UINT32 Capability;
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| 36 | UINT16 Control;
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| 37 | UINT16 Status;
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| 38 | UINT16 InitialVFs;
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| 39 | UINT16 TotalVFs;
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| 40 | UINT16 NumVFs;
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| 41 | UINT8 FunctionDependencyLink;
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| 42 | UINT8 Reserved0;
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| 43 | UINT16 FirstVFOffset;
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| 44 | UINT16 VFStride;
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| 45 | UINT16 Reserved1;
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| 46 | UINT16 VFDeviceID;
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| 47 | UINT32 SupportedPageSize;
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| 48 | UINT32 SystemPageSize;
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| 49 | UINT32 VFBar[6];
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| 50 | UINT32 VFMigrationStateArrayOffset;
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| 51 | } SR_IOV_CAPABILITY_REGISTER;
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| 52 |
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| 53 | #define EFI_PCIE_CAPABILITY_ID_SRIOV_CAPABILITIES 0x04
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| 54 | #define EFI_PCIE_CAPABILITY_ID_SRIOV_CONTROL 0x08
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| 55 | #define EFI_PCIE_CAPABILITY_ID_SRIOV_STATUS 0x0A
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| 56 | #define EFI_PCIE_CAPABILITY_ID_SRIOV_INITIALVFS 0x0C
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| 57 | #define EFI_PCIE_CAPABILITY_ID_SRIOV_TOTALVFS 0x0E
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| 58 | #define EFI_PCIE_CAPABILITY_ID_SRIOV_NUMVFS 0x10
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| 59 | #define EFI_PCIE_CAPABILITY_ID_SRIOV_FUNCTION_DEPENDENCY_LINK 0x12
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| 60 | #define EFI_PCIE_CAPABILITY_ID_SRIOV_FIRSTVF 0x14
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| 61 | #define EFI_PCIE_CAPABILITY_ID_SRIOV_VFSTRIDE 0x16
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| 62 | #define EFI_PCIE_CAPABILITY_ID_SRIOV_VFDEVICEID 0x1A
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| 63 | #define EFI_PCIE_CAPABILITY_ID_SRIOV_SUPPORTED_PAGE_SIZE 0x1C
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| 64 | #define EFI_PCIE_CAPABILITY_ID_SRIOV_SYSTEM_PAGE_SIZE 0x20
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| 65 | #define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR0 0x24
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| 66 | #define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR1 0x28
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| 67 | #define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR2 0x2C
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| 68 | #define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR3 0x30
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| 69 | #define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR4 0x34
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| 70 | #define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR5 0x38
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| 71 | #define EFI_PCIE_CAPABILITY_ID_SRIOV_VF_MIGRATION_STATE 0x3C
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| 72 |
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| 73 | #endif
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